repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
Interpolation_not_complete/detector.vhd
| 1 | 1,483 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity detector is
Port ( x : in std_logic_vector(10 downto 0);
y : out std_logic_vector(2 downto 0));
end detector;
architecture Behavioral of detector is
signal ND : std_logic_vector(7 downto 2);
signal ans : std_logic_vector(6 downto 1);
component or4t1
Port ( In1 : in std_logic;
In2 : in std_logic;
In3 : in std_logic;
In4 : in std_logic;
Output : out std_logic);
end component;
begin
ND(7) <= not x(7);
ND(6) <= not x(6);
ND(5) <= not x(5);
ND(4) <= not x(4);
ND(3) <= not x(3);
ND(2) <= not x(2);
ans(6) <= ND(7) and x(6);
ans(5) <= ND(7) and ND(6) and x(5);
ans(4) <= ND(7) and ND(6) and ND(5) and x(4);
ans(3) <= ND(7) and ND(6) and ND(5) and ND(4) and x(3);
ans(2) <= ND(7) and ND(6) and ND(5) and ND(4) and ND(3) and x(2);
ans(1) <= ND(7) and ND(6) and ND(5) and ND(4) and ND(3) and ND(2) and x(1);
C1 : or4t1
port map(x(7), ans(6), ans(5), ans(4), y(2));
C2 : or4t1
port map(x(7), ans(6), ans(3), ans(2), y(1));
C3 : or4t1
port map(x(7), ans(5), ans(3), ans(1), y(0));
end Behavioral;
|
mit
|
3f30d172ad5c4107f497843fb7b4e025
| 0.549562 | 2.667266 | false | false | false | false |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx
|
Frecuencimentro/clk_mod.vhd
| 2 | 1,435 |
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk_mod is
Port (
entrada: in STD_LOGIC;
reset : in STD_LOGIC;
salida : out STD_LOGIC
);
end clk_mod;
architecture Behavioral of clk_mod is
signal temporal: STD_LOGIC;
signal contador: integer range 0 to 150000 := 0;
begin
divisor_frecuencia: process (reset, entrada) begin
if (reset = '1') then
temporal <= '0';
contador <= 0;
elsif rising_edge(entrada) then
if (contador = 25000) then --ESTA VARIABLE ES LA QUE HACE QUE SE MODIFICA LA FRECUENCIA. HAY QUE DIVIDIR LA DEL RELOJ DE LA TARJETA ENTRE LA DESEADA Y DIVIDIRLA ENTRE 2 (semiperiodo).
temporal <= NOT(temporal);
contador <= 0;
else
contador <= contador+1;
end if;
end if;
end process;
salida <= temporal;
end Behavioral;
|
gpl-2.0
|
aad39b940448267c557de0c6d2332f62
| 0.536585 | 4.674267 | false | false | false | false |
Digilent/vivado-library
|
ip/axi_ps2_1.0/src/axi_ps2_v1_0_S_AXI.vhd
| 1 | 22,984 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_ps2_v1_0_S_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 5
);
port (
-- Users to add ports here
lTxDataReg : out std_logic_vector (31 downto 0);
lRxDataReg : in std_logic_vector (31 downto 0);
lRxAck : out std_logic;
lTxTrig : out std_logic;
lStatusReg : in std_logic_vector (31 downto 0);
IsrBitTxNoAck : in std_logic;
IsrBitTxAck : in std_logic;
IsrBitRxOvf : in std_logic;
IsrBitRxErr : in std_logic;
IsrBitRxFull : in std_logic;
SrstOut : out std_logic;
IntrOut : out std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end axi_ps2_v1_0_S_AXI;
architecture arch_imp of axi_ps2_v1_0_S_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 2;
------------------------------------------------
---- Signals for user logic register space example
signal TxDataWriteTrig : std_logic := '0';
signal SrstWriteTrig : std_logic := '0';
signal AuxRxAck : std_logic := '0';
signal CtlSrstOut : std_logic := '0';
signal a_IsrBuffReg :std_logic_vector (3 downto 0);
signal IsrBuffClr : std_logic := '0';
--------------------------------------------------
---- Number of Slave Registers 7
signal a_SrstReg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_StsReg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_RxDataReg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_TxDataReg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_GieReg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_IsrReg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal a_IerReg :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
begin
-- I/O Connections assignments
a_StsReg <= lStatusReg;
a_RxDataReg <= lRxDataReg;
lTxDataReg <= a_TxDataReg ; --TX Data sent to TX FIFO
lTxTrig <= TxDataWriteTrig; --new data has been written to the TX Data register
lRxAck <= axi_rvalid when AuxRxAck = '1' else '0'; --this signal indicates when data has been read from the RX Data register
--interrupt signal generated
IntrOut <= a_GieReg(0) and ((a_IsrReg(30) and a_IerReg(30)) or (a_IsrReg(29) and a_IerReg(29)) or (a_IsrReg(28) and a_IerReg(28) ) or (a_IsrReg(27) and a_IerReg(27)) or (a_IsrReg(26) and a_IerReg(26)));
-- IntrOut <= (a_IsrReg(30) and a_IerReg(30)) or (a_IsrReg(29) and a_IerReg(29)) or (a_IsrReg(28) and a_IerReg(28) ) or (a_IsrReg(27) and a_IerReg(27)) or (IsrBitRxFull and a_IerReg(26));
SrstOut <= CtlSrstOut;
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' or CtlSrstOut = '1' then
a_SrstReg <= (others => '0');
a_TxDataReg <= (others => '0');
TxDataWriteTrig <= '0';
SrstWriteTrig <= '0';
else
TxDataWriteTrig <= '0';
SrstWriteTrig <= '0';
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
a_SrstReg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
SrstWriteTrig <= '1';--signal indicates that the register has been written
end if;
end loop;
when b"001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
end if;
end loop;
when b"010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
end if;
end loop;
when b"011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
a_TxDataReg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
TxDataWriteTrig <= '1';--signal indicates that the register has been written
end if;
end loop;
when b"100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
end if;
end loop;
when b"101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
end if;
end loop;
when b"110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
end if;
end loop;
when others =>
a_SrstReg <= a_SrstReg;
a_TxDataReg <= a_TxDataReg;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (a_SrstReg, a_StsReg, a_RxDataReg, a_TxDataReg, a_GieReg, a_IsrReg, a_IerReg, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
AuxRxAck <= '0';
case loc_addr is
when b"000" =>
reg_data_out <= a_SrstReg;
when b"001" =>
reg_data_out <= a_StsReg;
when b"010" =>
reg_data_out <= a_RxDataReg;
AuxRxAck <= '1';
when b"011" =>
reg_data_out <= a_TxDataReg;
when b"100" =>
reg_data_out <= a_GieReg;
when b"101" =>
reg_data_out <= a_IsrReg;
when b"110" =>
reg_data_out <= a_IerReg;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
--ISR signals buffer which helps the hw to avoid software-hardware conflicts on the ISR
a_IsrBuffReg_PROC: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' or CtlSrstOut = '1' or IsrBuffClr = '1' then
a_IsrBuffReg <= (others => '0');
elsif (IsrBitTxNoAck = '1' or IsrBitTxAck = '1' or IsrBitRxOvf = '1' or IsrBitRxErr = '1') then
a_IsrBuffReg(3) <= IsrBitTxNoack or a_IsrBuffReg(3);
a_IsrBuffReg(2) <= IsrBitTxack or a_IsrBuffReg(2);
a_IsrBuffReg(1) <= IsrBitRxOvf or a_IsrBuffReg(1);
a_IsrBuffReg(0) <= IsrBitRxErr or a_IsrBuffReg(0);
end if;
end if;
end process;
--ISR management
a_IsrReg_PROC: process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' or CtlSrstOut = '1' then
a_IsrReg <= (others => '0');
IsrBuffClr <= '0';
else
IsrBuffClr <= '0';
a_IsrReg(26) <= IsrBitRxFull;--This interrupt is not software resetable
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1' and loc_addr = "101") then
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- using this construct gives the register toggle-on-write access
a_IsrReg(byte_index*8+7 downto byte_index*8) <= (a_IsrReg(byte_index*8+7 downto byte_index*8)) and (not (S_AXI_WDATA(byte_index*8+7 downto byte_index*8)));
end if;
end loop;
elsif (a_IsrBuffReg(3) = '1' or a_IsrBuffReg(2) = '1' or a_IsrBuffReg(1) = '1' or a_IsrBuffReg(0) = '1') then
--by or-ing the current value with the potentially new value, all the bits that are '1' will remain '1'
--clearing an interrupt is done above
a_IsrReg(30) <= a_IsrBuffReg(3) or a_IsrReg(30);
a_IsrReg(29) <= a_IsrBuffReg(2) or a_IsrReg(29);
a_IsrReg(28) <= a_IsrBuffReg(1) or a_IsrReg(28);
a_IsrReg(27) <= a_IsrBuffReg(0) or a_IsrReg(27);
IsrBuffClr <= '1';
end if;
end if;
end if;
end process;
--IER management
a_IerReg_PROC: process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' or CtlSrstOut = '1' then
a_IerReg <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1' and loc_addr = "110") then
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
--IER is only managed by the software
a_IerReg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
end if;
end if;
end if;
end process;
--GIE management
a_GieReg_PROC: process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' or CtlSrstOut = '1' then
a_GieReg <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1' and loc_addr = "100") then
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
--GIE is only managed by the software
a_GieReg(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- GieWriteTrig <= '1';
end if;
end loop;
end if;
end if;
end if;
end process;
--Software reset process
a_SrstReg_PROC: process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
CtlSrstOut <= '0';
--the hardwear is reset when 0xA is written to the register
elsif SrstWriteTrig = '1' and a_SrstReg = "00000000000000000000000000001010" then
CtlSrstOut <= '1';
else
CtlSrstOut <= '0';
end if;
end if;
end process;
-- User logic ends
end arch_imp;
|
mit
|
42e6beedbb35fa9270ef128bd3320fbf
| 0.585233 | 3.613268 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodDigitizerController/src/ADI_SPI.vhd
| 1 | 15,881 |
-------------------------------------------------------------------------------
--
-- File: ADI_SPI.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module manages the SPI communication with the Analog Devices 3 wire SPI
-- configuration interface
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
use IEEE.math_real.all;
use work.PkgZmodDigitizer.all;
entity ADI_SPI is
Generic
(
-- The sSPI_Clk signal is obtained by dividing SysClk100 to 2^kSysClkDiv.
kSysClkDiv : integer range 2 to 63 := 4;
-- The number of data bits for the data phase of the transaction:
-- only 8 data bits currently supported.
kDataWidth : integer range 8 to 8 := 8;
-- The number of bits of the command phase of the SPI transaction.
kCommandWidth : integer range 8 to 16 := 16
);
Port (
-- input clock (100MHZ).
SysClk100 : in STD_LOGIC;
-- active low synchronous reset signal.
asRst_n : in STD_LOGIC;
--AD92xx/AD96xx SPI interface signals.
sSPI_Clk : out STD_LOGIC;
sSDIO : inout STD_LOGIC;
sCS : out STD_LOGIC := '1';
--Upper layer Interface signals
--a pulse on this input initiates the transfers, also used to register upper layer interface inputs.
sApStart : in STD_LOGIC;
--SPI read data output.
sRdData : out std_logic_vector(kDataWidth - 1 downto 0);
--SPI command data.
sWrData : in std_logic_vector(kDataWidth - 1 downto 0);
--SPI command register address.
sAddr : in std_logic_vector(kCommandWidth - 4 downto 0);
--Number of data bytes + 1; not currently used (for future development).
sWidth : in std_logic_vector(1 downto 0);
--Select between Read/Write operations.
sRdWr : in STD_LOGIC;
--A pulse is generated on this output once the SPI transfer is successfully completed.
sDone : out STD_LOGIC;
--Busy flag; sApStart ignored while this signal is asserted .
sBusy : out STD_LOGIC);
end ADI_SPI;
architecture Behavioral of ADI_SPI is
function MAX(In1 : integer; In2 : integer)
return integer is
begin
if (In1 > In2) then
return In1;
else
return In2;
end if;
end function;
constant kZeros : unsigned (kSysClkDiv - 1 downto 0) := (others => '0');
constant kOnes : unsigned (kSysClkDiv - 1 downto 0) := (others => '1');
signal sClkCounter : unsigned(kSysClkDiv - 1 downto 0) := (others => '0');
signal sSPI_ClkRst: std_logic;
signal sRdDataR : std_logic_vector(kDataWidth - 1 downto 0);
signal sTxVector : std_logic_vector (kDataWidth + kCommandWidth - 1 downto 0);
signal sRxData : std_logic;
signal sTxData : std_logic := '0';
signal sTxShift, sRxShift : std_logic;
signal sLdTx : std_logic;
signal sApStartR, sApStartPulse : std_logic;
constant kCounterMax : integer := MAX((kDataWidth + kCommandWidth + 1), kCS_PulseWidthHigh);
constant kCounterNumBits : integer := integer(ceil(log2(real(kCounterMax))));
signal sCounter : unsigned (kCounterNumBits-1 downto 0);
signal sCounterInt : integer range 0 to (2**kCounterNumBits-1);
signal sCntRst_n, sTxCntEn, sRxCntEn, sDoneCntEn : std_logic := '0';
signal sBitCount : integer range 0 to kDataWidth; --Maximum 4 byte transfers for Analog Devices 2 Wire SPI
signal sDir : std_logic := '0';
signal sDirFsm : std_logic;
signal sCS_Fsm : std_logic;
signal sDoneFsm : std_logic;
signal sBusyFsm : std_logic;
signal sCurrentState : FsmStatesSPI_t := StIdle;
signal sNextState : FsmStatesSPI_t;
-- signals used for debug purposes
-- signal fsm_state, fsm_state_r : std_logic_vector(3 downto 0);
signal kHalfScale : unsigned (kSysClkDiv - 1 downto 0);
begin
kHalfScale <= '1' & kZeros(kSysClkDiv - 2 downto 0);
------------------------------------------------------------------------------------------
-- SPI interface signal assignment
------------------------------------------------------------------------------------------
InstIOBUF : IOBUF -- instantiate SDIO three state output buffer.
generic map (
DRIVE => 12,
IOSTANDARD => "LVCMOS18",
SLEW => "SLOW")
port map (
O => sRxData, -- Buffer output
IO => sSDIO, -- Buffer inout port (connect directly to top-level port)
I => sTxData, -- Buffer input
T => sDir -- 3-state enable input, high=input, low=output
);
-- Three state buffer direction control register.
ProcDir: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sDir <= '0';
elsif (rising_edge(SysClk100)) then
if (sLdTx = '1') then
sDir <= sDirFsm;
else
if ((sClkCounter = kOnes) or (sCS_Fsm = '1')) then
sDir <= sDirFsm;
end if;
end if;
end if;
end process;
ProcRegCS: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCS <= '1';
--fsm_state_r <= (others => '0');
elsif (rising_edge (SysClk100)) then
sCS <= sCS_Fsm;
--fsm_state_r <= fsm_state;
end if;
end process;
sSPI_Clk <= sClkCounter(kSysClkDiv - 1 );
------------------------------------------------------------------------------------------
-- Input clock frequency divider
------------------------------------------------------------------------------------------
ProcClkCounter: process (SysClk100, asRst_n) --clock frequency divider
begin
if (asRst_n = '0') then
sClkCounter <= (others => '0');
elsif (rising_edge(SysClk100)) then
if (sSPI_ClkRst = '1') then
sClkCounter <= (others => '0');
else
sClkCounter <= sClkCounter + 1;
end if;
end if;
end process;
------------------------------------------------------------------------------------------
-- Transmit logic
------------------------------------------------------------------------------------------
sBitCount <= kDataWidth;
ProcApStartReg: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sApStartR <= '0';
elsif (rising_edge(SysClk100)) then
sApStartR <= sApStart;
end if;
end process;
sApStartPulse <= sApStart and (not sApStartR);
ProcShiftTx: process (SysClk100, asRst_n) --Transmit shift register
begin
if (asRst_n = '0') then
sTxVector <= (others => '0');--sRdWr & "00" & sAddr & sWrData;
sTxData <= '0';
elsif (rising_edge(SysClk100)) then
if (sApStartPulse = '1') then
--sTxVector <= sRdWr & sWidth & sAddr & sWrData;
sTxVector <= sRdWr & "00" & sAddr & sWrData;
sTxData <= '0';
else
if(sTxShift = '1') then
--data is placed on the falling edge (sClkCounter = kZeros) of sSPI_Clk for the transmit phase.
if ((sClkCounter = kZeros) and (sCounterInt <= kDataWidth+kCommandWidth)) then
sTxVector(kDataWidth + kCommandWidth - 1 downto 0) <= sTxVector(kDataWidth + kCommandWidth - 2 downto 0) & '0';
sTxData <= sTxVector(kDataWidth + kCommandWidth - 1);
elsif (sCounterInt > kDataWidth+kCommandWidth) then
sTxData <= '0';
end if;
else
sTxData <= '0';
end if;
end if;
end if;
end process;
ProcTxCount: process (asRst_n, sTxShift, sLdTx, sClkCounter) --Transmit bit count
begin
if ((asRst_n = '0') or (sLdTx = '1')) then
sTxCntEn <= '0';
else
if(sTxShift = '1') then
--The TX bit count incremented on the falling edge of the sSPI_Clk (sClkCounter = kZeros).
if (sClkCounter = kZeros) then
sTxCntEn <= '1';
else
sTxCntEn <= '0';
end if;
else
sTxCntEn <= '0';
end if;
end if;
end process;
------------------------------------------------------------------------------------------
-- Receive logic
------------------------------------------------------------------------------------------
-- Receive deserializer.
ProcShiftRx: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sRdDataR <= (others =>'0');
elsif (rising_edge(SysClk100)) then
if (sRxShift = '0') then
sRdDataR <= (others =>'0');
else
if ((sRxShift = '1') and (sClkCounter = kHalfScale)) then
--The read data is sampled on the rising edge of the sSPI_Clk (sClkCounter = kHalfScale).
sRdDataR(kDataWidth - 1 downto 0) <= sRdDataR(kDataWidth - 2 downto 0) & sRxData;
end if;
end if;
end if;
end process;
ProcRxCount: process (asRst_n, sRxShift, sClkCounter, kHalfScale) --Receive bit count
begin
if ((asRst_n = '0') or (sRxShift = '0')) then
sRxCntEn <= '0';
else
if (sRxShift = '1') then
--The RX bit count is incremented on the rising edge of the sSPI_Clk (sClkCounter = kHalfScale).
if (sClkCounter = kHalfScale) then
sRxCntEn <= '1';
else
sRxCntEn <= '0';
end if;
else
sRxCntEn <= '0';
end if;
end if;
end process;
-- Register SPI read data once read instruction is completed.
ProcRdData: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sRdData <= (others => '0');
sDone <= '0';
elsif (rising_edge (SysClk100)) then
sDone <= sDoneFsm;
if (sDoneFsm = '1') then
sRdData <= sRdDataR;
end if;
end if;
end process;
ProcBusy: process (SysClk100, asRst_n) --register sBusyFsm output
begin
if (asRst_n = '0') then
sBusy <= '1';
elsif (rising_edge (SysClk100)) then
sBusy <= sBusyFsm;
end if;
end process;
--Counter used by both transmit and receive logic; sCS minimum pulse width high is also timed by this counter.
ProcCounter: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCounter <= (others => '0');
elsif (rising_edge(SysClk100)) then
if (sCntRst_n = '0') then
sCounter <= (others => '0');
else
if ((sTxCntEn = '1') or (sRxCntEn = '1') or (sDoneCntEn = '1')) then
sCounter <= sCounter + 1;
end if;
end if;
end if;
end process;
sCounterInt <= to_integer (sCounter);
------------------------------------------------------------------------------------------
-- SPI State Machine
------------------------------------------------------------------------------------------
ProcFsmSync: process (SysClk100, asRst_n) --State machine synchronous process
begin
if (asRst_n = '0') then
sCurrentState <= StIdle;
elsif (rising_edge (SysClk100)) then
sCurrentState <= sNextState;
end if;
end process;
--Next State decode logic
ProcNextStateAndOutputDecode: process (sCurrentState, sApStart, sRdWr, sCounterInt, sClkCounter, sBitCount)
begin
sNextState <= sCurrentState;
sDirFsm <= '0';
sCS_Fsm <= '1';
sDoneFsm <= '0';
sRxShift <= '0';
sTxShift <= '0';
--fsm_state <= (others => '0');
sLdTx <= '0';
sSPI_ClkRst <= '1';
sCntRst_n <= '0';
sDoneCntEn <= '0';
sBusyFsm <= '1';
case (sCurrentState) is
when StIdle =>
--fsm_state <= "0000";
sBusyFsm <= '0';
sLdTx <= '1';
if (sApStart = '1') then
if (sRdWr = '1') then
sNextState <= StRead1;
else
sNextState <= StWrite;
end if;
end if;
when StRead1 => --send command bytes
--fsm_state <= "0001";
sCS_Fsm <= '0';
sTxShift <= '1';
sSPI_ClkRst <= '0';
sCntRst_n <= '1';
if (sCounterInt = kCommandWidth) then
sDirFsm <= '1';
sNextState <= StRead2;
end if;
when StRead2 => --send last command bit; change three state buffer direction
--fsm_state <= "0010";
sDirFsm <= '1';
sCS_Fsm <= '0';
sTxShift <= '1';
sSPI_ClkRst <= '0';
sCntRst_n <= '1';
if (sCounterInt = kCommandWidth + 1) then
sNextState <= StRead3;
sCntRst_n <= '0';
end if;
when StRead3 => --receive register read data
--fsm_state <= "0011";
sDirFsm <= '1';
sCS_Fsm <= '0';
sRxShift <= '1';
sSPI_ClkRst <= '0';
sCntRst_n <= '1';
if ((sCounterInt = sBitCount) and (sClkCounter = kOnes + 1)) then
--this condition assures a sSPI_Clk pulse width low of 2 SysClk100 cycles for last data bit
sCntRst_n <= '0';
sDirFsm <= '0';
sNextState <= StDone;
end if;
when StWrite => --send SPI command and register data
--fsm_state <= "0100";
sCS_Fsm <= '0';
sTxShift <= '1';
sSPI_ClkRst <= '0';
sCntRst_n <= '1';
if (sCounterInt = (sBitCount + kCommandWidth + 1)) then
sSPI_ClkRst <= '1';
sNextState <= StDone;
end if;
when StDone => --signal SPI instruction complete
--fsm_state <= "0101";
sDoneFsm <= '1';
sNextState <= StAssertCS;
when StAssertCS => --hold CS high for at least kCS_PulseWidthHigh SysClk100 cycles
--fsm_state <= "0111";
sCntRst_n <= '1';
sDoneCntEn <= '1';
if (sCounterInt = kCS_PulseWidthHigh) then
sNextState <= StIdle;
end if;
when others =>
--fsm_state <= (others => '1');
sNextState <= StIdle;
end case;
end process;
end Behavioral;
|
mit
|
cc8cf4cb4c803c444d331c0a4d0ecf6d
| 0.550091 | 4.465973 | false | false | false | false |
Digilent/vivado-library
|
ip/video_scaler/hdl/vhdl/Block_Mat_exit45_pro.vhd
| 1 | 11,962 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Block_Mat_exit45_pro is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
start_full_n : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
start_out : OUT STD_LOGIC;
start_write : OUT STD_LOGIC;
in_width : IN STD_LOGIC_VECTOR (31 downto 0);
in_height : IN STD_LOGIC_VECTOR (31 downto 0);
out_width : IN STD_LOGIC_VECTOR (31 downto 0);
out_height : IN STD_LOGIC_VECTOR (31 downto 0);
img_in_rows_V_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
img_in_rows_V_out_full_n : IN STD_LOGIC;
img_in_rows_V_out_write : OUT STD_LOGIC;
img_in_cols_V_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
img_in_cols_V_out_full_n : IN STD_LOGIC;
img_in_cols_V_out_write : OUT STD_LOGIC;
img_out_rows_V_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
img_out_rows_V_out_full_n : IN STD_LOGIC;
img_out_rows_V_out_write : OUT STD_LOGIC;
img_out_cols_V_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
img_out_cols_V_out_full_n : IN STD_LOGIC;
img_out_cols_V_out_write : OUT STD_LOGIC );
end;
architecture behav of Block_Mat_exit45_pro is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
signal real_start : STD_LOGIC;
signal start_once_reg : STD_LOGIC := '0';
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal internal_ap_ready : STD_LOGIC;
signal img_in_rows_V_out_blk_n : STD_LOGIC;
signal img_in_cols_V_out_blk_n : STD_LOGIC;
signal img_out_rows_V_out_blk_n : STD_LOGIC;
signal img_out_cols_V_out_blk_n : STD_LOGIC;
signal ap_block_state1 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
begin
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_continue = ap_const_logic_1)) then
ap_done_reg <= ap_const_logic_0;
elsif ((not(((real_start = ap_const_logic_0) or (img_out_cols_V_out_full_n = ap_const_logic_0) or (img_out_rows_V_out_full_n = ap_const_logic_0) or (img_in_cols_V_out_full_n = ap_const_logic_0) or (img_in_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
start_once_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
start_once_reg <= ap_const_logic_0;
else
if (((internal_ap_ready = ap_const_logic_0) and (real_start = ap_const_logic_1))) then
start_once_reg <= ap_const_logic_1;
elsif ((internal_ap_ready = ap_const_logic_1)) then
start_once_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (real_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, img_in_rows_V_out_full_n, img_in_cols_V_out_full_n, img_out_rows_V_out_full_n, img_out_cols_V_out_full_n)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_block_state1_assign_proc : process(real_start, ap_done_reg, img_in_rows_V_out_full_n, img_in_cols_V_out_full_n, img_out_rows_V_out_full_n, img_out_cols_V_out_full_n)
begin
ap_block_state1 <= ((real_start = ap_const_logic_0) or (img_out_cols_V_out_full_n = ap_const_logic_0) or (img_out_rows_V_out_full_n = ap_const_logic_0) or (img_in_cols_V_out_full_n = ap_const_logic_0) or (img_in_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
ap_done_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_in_rows_V_out_full_n, img_in_cols_V_out_full_n, img_out_rows_V_out_full_n, img_out_cols_V_out_full_n)
begin
if ((not(((real_start = ap_const_logic_0) or (img_out_cols_V_out_full_n = ap_const_logic_0) or (img_out_rows_V_out_full_n = ap_const_logic_0) or (img_in_cols_V_out_full_n = ap_const_logic_0) or (img_in_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_idle_assign_proc : process(real_start, ap_CS_fsm_state1)
begin
if (((real_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready <= internal_ap_ready;
img_in_cols_V_out_blk_n_assign_proc : process(ap_CS_fsm_state1, img_in_cols_V_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
img_in_cols_V_out_blk_n <= img_in_cols_V_out_full_n;
else
img_in_cols_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img_in_cols_V_out_din <= in_width;
img_in_cols_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_in_rows_V_out_full_n, img_in_cols_V_out_full_n, img_out_rows_V_out_full_n, img_out_cols_V_out_full_n)
begin
if ((not(((real_start = ap_const_logic_0) or (img_out_cols_V_out_full_n = ap_const_logic_0) or (img_out_rows_V_out_full_n = ap_const_logic_0) or (img_in_cols_V_out_full_n = ap_const_logic_0) or (img_in_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_in_cols_V_out_write <= ap_const_logic_1;
else
img_in_cols_V_out_write <= ap_const_logic_0;
end if;
end process;
img_in_rows_V_out_blk_n_assign_proc : process(ap_CS_fsm_state1, img_in_rows_V_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
img_in_rows_V_out_blk_n <= img_in_rows_V_out_full_n;
else
img_in_rows_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img_in_rows_V_out_din <= in_height;
img_in_rows_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_in_rows_V_out_full_n, img_in_cols_V_out_full_n, img_out_rows_V_out_full_n, img_out_cols_V_out_full_n)
begin
if ((not(((real_start = ap_const_logic_0) or (img_out_cols_V_out_full_n = ap_const_logic_0) or (img_out_rows_V_out_full_n = ap_const_logic_0) or (img_in_cols_V_out_full_n = ap_const_logic_0) or (img_in_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_in_rows_V_out_write <= ap_const_logic_1;
else
img_in_rows_V_out_write <= ap_const_logic_0;
end if;
end process;
img_out_cols_V_out_blk_n_assign_proc : process(ap_CS_fsm_state1, img_out_cols_V_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
img_out_cols_V_out_blk_n <= img_out_cols_V_out_full_n;
else
img_out_cols_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img_out_cols_V_out_din <= out_width;
img_out_cols_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_in_rows_V_out_full_n, img_in_cols_V_out_full_n, img_out_rows_V_out_full_n, img_out_cols_V_out_full_n)
begin
if ((not(((real_start = ap_const_logic_0) or (img_out_cols_V_out_full_n = ap_const_logic_0) or (img_out_rows_V_out_full_n = ap_const_logic_0) or (img_in_cols_V_out_full_n = ap_const_logic_0) or (img_in_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_out_cols_V_out_write <= ap_const_logic_1;
else
img_out_cols_V_out_write <= ap_const_logic_0;
end if;
end process;
img_out_rows_V_out_blk_n_assign_proc : process(ap_CS_fsm_state1, img_out_rows_V_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
img_out_rows_V_out_blk_n <= img_out_rows_V_out_full_n;
else
img_out_rows_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img_out_rows_V_out_din <= out_height;
img_out_rows_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_in_rows_V_out_full_n, img_in_cols_V_out_full_n, img_out_rows_V_out_full_n, img_out_cols_V_out_full_n)
begin
if ((not(((real_start = ap_const_logic_0) or (img_out_cols_V_out_full_n = ap_const_logic_0) or (img_out_rows_V_out_full_n = ap_const_logic_0) or (img_in_cols_V_out_full_n = ap_const_logic_0) or (img_in_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_out_rows_V_out_write <= ap_const_logic_1;
else
img_out_rows_V_out_write <= ap_const_logic_0;
end if;
end process;
internal_ap_ready_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_in_rows_V_out_full_n, img_in_cols_V_out_full_n, img_out_rows_V_out_full_n, img_out_cols_V_out_full_n)
begin
if ((not(((real_start = ap_const_logic_0) or (img_out_cols_V_out_full_n = ap_const_logic_0) or (img_out_rows_V_out_full_n = ap_const_logic_0) or (img_in_cols_V_out_full_n = ap_const_logic_0) or (img_in_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
internal_ap_ready <= ap_const_logic_1;
else
internal_ap_ready <= ap_const_logic_0;
end if;
end process;
real_start_assign_proc : process(ap_start, start_full_n, start_once_reg)
begin
if (((start_full_n = ap_const_logic_0) and (start_once_reg = ap_const_logic_0))) then
real_start <= ap_const_logic_0;
else
real_start <= ap_start;
end if;
end process;
start_out <= real_start;
start_write_assign_proc : process(real_start, start_once_reg)
begin
if (((start_once_reg = ap_const_logic_0) and (real_start = ap_const_logic_1))) then
start_write <= ap_const_logic_1;
else
start_write <= ap_const_logic_0;
end if;
end process;
end behav;
|
mit
|
8c6cfa5f044b41f116cfeb36cb25edb5
| 0.590871 | 2.706335 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
Interpolation_not_complete/LS.vhd
| 1 | 2,516 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity LS is
Port ( x : in std_logic_vector(10 downto 0);
shift : in std_logic_vector(2 downto 0);
y : out std_logic_vector(18 downto 0));
-- y : out std_logic_vector(16 downto 0);
-- clk : in std_logic);
end LS;
architecture Behavioral of LS is
signal reg1 : std_logic_vector(13 downto 0);
signal reg2 : std_logic_vector(17 downto 0);
component mux2t1
Port ( In1 : in std_logic;
In2 : in std_logic;
sel : in std_logic;
Output : out std_logic);
-- Output : out std_logic;
-- clock : in std_logic);
end component;
begin
C1: mux2t1 port map('0', x(0), shift(0), reg1(0));
-- port map('0', x(0), shift(0), reg1(0), clk);
Layer1 : for i in 1 to 10 generate
C1: mux2t1
port map(x(i - 1), x(i), shift(0), reg1(i));
-- port map(x(i - 1), x(i), shift(0), reg1(i), clk);
end generate;
reg1(13) <= x(10);
reg1(12) <= x(10);
reg1(11) <= x(10);
C20: mux2t1
port map('0', reg1(0), shift(1), reg2(0));
-- port map('0', reg1(0), shift(1), reg2(0), clk);
C21: mux2t1
port map('0', reg1(1), shift(1), reg2(1));
-- port map('0', reg1(1), shift(1), reg2(1), clk);
Layer2 : for i in 2 to 13 generate
C2: mux2t1
port map(reg1(i - 2), reg1(i), shift(1), reg2(i));
-- port map(reg1(i - 2), reg1(i), shift(1), reg2(i), clk);
end generate;
reg2(17) <= x(10);
reg2(16) <= x(10);
reg2(15) <= x(10);
reg2(14) <= x(10);
C30: mux2t1
port map('0', reg2(0), shift(2), y(0));
-- port map('0', reg2(0), shift(2), y(0), clk);
C31: mux2t1
port map('0', reg2(1), shift(2), y(1));
-- port map('0', reg2(1), shift(2), y(1), clk);
C32: mux2t1
port map('0', reg2(2), shift(2), y(2));
-- port map('0', reg2(2), shift(2), y(2), clk);
C33: mux2t1
port map('0', reg2(3), shift(2), y(3));
-- port map('0', reg2(3), shift(2), y(3), clk);
Layer3 : for i in 4 to 17 generate
C3: mux2t1
port map(reg2(i - 4), reg2(i), shift(2), y(i));
-- port map(reg2(i - 4), reg2(i), shift(2), y(i), clk);
end generate;
y(18) <= x(10);
end Behavioral;
|
mit
|
19cb4cb8f624ecb8eb5b3de9cb1eb8d8
| 0.535374 | 2.634555 | false | false | false | false |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx
|
Frecuencimentro/CountEventsDownTB.vhd
| 2 | 1,766 |
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY CountEventsDownTB IS
END CountEventsDownTB;
ARCHITECTURE behavior OF CountEventsDownTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CountEventsDown
PORT(
entrada_clk : IN std_logic;
reset : IN std_logic;
salida : OUT std_logic
);
END COMPONENT;
--Inputs
signal reset : std_logic := '0';
signal entrada_clk : std_logic := '0';
--Outputs
signal salida : std_logic;
-- Clock period definitions
constant entrada_clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CountEventsDown PORT MAP (
reset => reset,
entrada_clk => entrada_clk,
salida => salida
);
-- Clock process definitions
entrada_clk_process :process
begin
entrada_clk <= '0';
wait for entrada_clk_period/2;
entrada_clk <= '1';
wait for entrada_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';-- hold reset state for 100 ns.
wait for 100 ns;
reset <= '0';
wait for entrada_clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
gpl-2.0
|
e535ec451e9145a2381f8187e18b73b1
| 0.561155 | 4.598958 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/start_for_CvtColowdI.vhd
| 1 | 4,490 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity start_for_CvtColowdI_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end start_for_CvtColowdI_shiftReg;
architecture rtl of start_for_CvtColowdI_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity start_for_CvtColowdI is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of start_for_CvtColowdI is
component start_for_CvtColowdI_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_start_for_CvtColowdI_shiftReg : start_for_CvtColowdI_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
d33b633ab4006d7b83be50c3a684ba0a
| 0.532962 | 3.594876 | false | false | false | false |
scottlbaker/Nova-SOC
|
src/uart.vhd
| 1 | 32,444 |
--======================================================================
-- uart.vhd :: Generic UART
--
-- no hardware handshake
-- 16-deep FIFO
--
-- (c) Scott L. Baker, Sierra Circuit Design
--======================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity UART is
port(
CS : in std_logic; -- chip select
WE : in std_logic; -- write enable
REG_SEL : in std_logic_vector( 1 downto 0); -- register select
WR_DATA : in std_logic_vector(15 downto 0); -- write data
RD_DATA : out std_logic_vector( 7 downto 0); -- read data
RX_IRQ : out std_logic; -- RX interrupt request
TX_IRQ : out std_logic; -- TX interrupt request
RXD : in std_logic; -- RX serial data
TXD : out std_logic; -- TX serial data
RESET : in std_logic; -- system reset
RDV : in std_logic; -- read data valid
FCLK : in std_logic -- fast clock
);
end UART;
architecture BEHAVIORAL of UART is
--=================================================================
-- Signal definitions
--=================================================================
signal PARITY_MODE : std_logic_vector(1 downto 0);
signal FRAMING_ERR : std_logic;
signal PARITY_ERR : std_logic;
signal OVERRUN_ERR : std_logic;
signal STATUS_CLR : std_logic; -- clear status register
signal TX_STATE : std_logic_vector(3 downto 0); -- TX state
signal TX_NSTATE : std_logic_vector(3 downto 0); -- TX next state
signal TX_SHIFT_REG : std_logic_vector(7 downto 0); -- TX shift reg
signal TX_COUNT : std_logic_vector(3 downto 0); -- TX shift counter
signal TX_FIFO_DATA : std_logic_vector(7 downto 0); -- TX FIFO out
signal TX_FIFO_OVFL : std_logic; -- TX FIFO overflow flag
signal TX_FIFO_FULL : std_logic; -- TX FIFO full flag
signal TX_FIFO_EMPTY : std_logic; -- TX FIFO empty flag
signal TX_FIFO_OP : std_logic; -- TX FIFO 1==push 0== pop
signal TX_FIFO_CKEN : std_logic; -- TX FIFO clock enable
signal TX_SHIFT_LD : std_logic; -- TX shift reg load
signal TX_EN : std_logic; -- TX enabled
signal TX_CLK_EN : std_logic; -- TX clock enable
signal TX_PARITY : std_logic; -- TX parity
signal TX_SHIFT_EN : std_logic; -- TX shift reg enable
signal TX_SHIFT_EN1 : std_logic; -- TX shift reg enable delayed
signal TX_BCLK : std_logic; -- TX baud clock
signal TX_BCLK_DLY : std_logic; -- TX baud clock delayed
signal RX_STATE : std_logic_vector(3 downto 0); -- RX state
signal RX_NSTATE : std_logic_vector(3 downto 0); -- RX next state
signal RX_COUNT : std_logic_vector(2 downto 0); -- RX shift counter
signal RX_SHIFT_REG : std_logic_vector(7 downto 0); -- RX shift register
signal RX_FIFO_DATA : std_logic_vector(7 downto 0); -- RX FIFO data
signal RX_FIFO_OVFL : std_logic; -- RX FIFO overflow flag
signal RX_FIFO_STOP : std_logic; -- RX FIFO stop flag
signal RX_FIFO_FULL : std_logic; -- RX FIFO full flag
signal RX_FIFO_EMPTY : std_logic; -- RX FIFO empty flag
signal RX_FIFO_OP : std_logic; -- RX FIFO 1==push 0== pop
signal RX_FIFO_CKEN : std_logic; -- RX FIFO clock enable
signal RX_EN : std_logic; -- RX enable
signal RX_ACCEPT : std_logic; -- receiver has accepted frame
signal RXD_SYNC : std_logic; -- synchronize received data
signal RXD_SYNC1 : std_logic; -- synchronize received data
signal RX_CLK_EN : std_logic; -- receiver clock enable
signal RX_SHIFT_EN : std_logic; -- receiver shift enable
signal RX_PARITY : std_logic; -- calculated receiver parity
signal RX_START : std_logic; -- testing start bit
signal RX_BCLK : std_logic; -- receiver baud clock
signal RX_BCLK_DLY : std_logic; -- receiver baud clock delayed
signal RXDI : std_logic; -- receive data
signal TXDI : std_logic; -- transmit data
signal PRELOAD : std_logic_vector(15 downto 0); -- baud rate preload
signal RX_BAUD : std_logic_vector(15 downto 0); -- RX baud counter
signal TX_BAUD : std_logic_vector(15 downto 0); -- TX baud counter
-- Registers
signal CNTL_REG : std_logic_vector( 3 downto 0); -- control
signal BRSR_REG : std_logic_vector(15 downto 0); -- baud rate select
signal STAT_REG : std_logic_vector( 7 downto 0); -- status
signal MASK_REG : std_logic_vector( 1 downto 0); -- interrupt mask
-- Register addresses
constant CNTL_ADDR : std_logic_vector(1 downto 0) := "00"; -- control
constant STAT_ADDR : std_logic_vector(1 downto 0) := "00"; -- status
constant BRSR_ADDR : std_logic_vector(1 downto 0) := "01"; -- baud rate
constant MASK_ADDR : std_logic_vector(1 downto 0) := "10"; -- irq mask
constant HOLD_ADDR : std_logic_vector(1 downto 0) := "11"; -- hold reg
-- parity modes
constant NONE : std_logic_vector(1 downto 0) := "00";
constant EVEN : std_logic_vector(1 downto 0) := "01";
constant ODD : std_logic_vector(1 downto 0) := "10";
-- State Constants
constant IDLE : std_logic_vector(3 downto 0) := "1000";
constant LOAD : std_logic_vector(3 downto 0) := "0010";
constant D7 : std_logic_vector(3 downto 0) := "0010";
constant SHIFT : std_logic_vector(3 downto 0) := "0100";
constant PRTY : std_logic_vector(3 downto 0) := "0000";
constant STOP : std_logic_vector(3 downto 0) := "0001";
-- Misc
constant CKDIV_TC : std_logic_vector(9 downto 0) := "0000000000";
constant TX_INIT : std_logic_vector(3 downto 0) := "0011";
constant TX_TC : std_logic_vector(3 downto 0) := "0000";
constant RX_INIT : std_logic_vector(2 downto 0) := "000";
constant RX_TC : std_logic_vector(2 downto 0) := "100";
--================================================================
-- component definitions
--================================================================
component FIFO
port (
FIFO_OUT : out std_logic_vector(7 downto 0);
FIFO_IN : in std_logic_vector(7 downto 0);
OVFL : out std_logic; -- overflow
LAST : out std_logic; -- nearly full
EMPTY : out std_logic; -- empty
FIFO_OP : in std_logic; -- 1==push 0==pop
CKEN : in std_logic; -- clock enable
CLK : in std_logic; -- clock
RESET : in std_logic -- Reset
);
end component;
--================================================================
-- End of types, component, and signal definition section
--================================================================
begin
--=============================================
-- Register Writes
--=============================================
REGISTER_WRITES:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
STATUS_CLR <= '0';
if ((CS = '1') and (WE = '1')) then
case REG_SEL is
when CNTL_ADDR =>
if (WR_DATA(4) = '1') then
STATUS_CLR <= '1';
else
CNTL_REG <= WR_DATA(3 downto 0);
end if;
when BRSR_ADDR =>
BRSR_REG <= WR_DATA;
when MASK_ADDR =>
MASK_REG <= WR_DATA(1 downto 0);
when others =>
end case;
end if;
-- reset state
if (RESET = '1') then
CNTL_REG <= (others => '0');
BRSR_REG <= (others => '0');
MASK_REG <= (others => '0');
STATUS_CLR <= '1';
end if;
end if;
end process;
--=============================================
-- TX FIFO Control
--=============================================
TX_FIFO_CONTROL:
process (CS, WE, REG_SEL, TX_EN, TX_SHIFT_LD)
begin
TX_FIFO_CKEN <= '0';
TX_FIFO_OP <= '0';
-- push tx FIFO
if ((CS = '1') and (WE = '1') and (REG_SEL = HOLD_ADDR)) then
if (TX_EN = '1') then
TX_FIFO_OP <= '1';
TX_FIFO_CKEN <= '1';
end if;
end if;
-- pop TX FIFO
if (TX_SHIFT_LD = '1') then
TX_FIFO_CKEN <= '1';
end if;
end process;
--=============================================
-- Status Register
--=============================================
STATUS_REGISTER:
process (FRAMING_ERR, PARITY_ERR, OVERRUN_ERR,
TX_FIFO_FULL, TX_FIFO_EMPTY, RX_FIFO_FULL, RX_FIFO_EMPTY)
begin
STAT_REG(7) <= '0';
STAT_REG(6) <= FRAMING_ERR;
STAT_REG(5) <= PARITY_ERR;
STAT_REG(4) <= OVERRUN_ERR;
STAT_REG(3) <= TX_FIFO_EMPTY; -- TX FIFO is empty
STAT_REG(2) <= not TX_FIFO_FULL; -- TX FIFO is not full
STAT_REG(1) <= RX_FIFO_FULL; -- RX FIFO is full
STAT_REG(0) <= not RX_FIFO_EMPTY; -- RX FIFO is not empty
end process;
--=============================================
-- Control Register Outputs
--=============================================
PRELOAD <= BRSR_REG; -- baud rate select constant
PARITY_MODE <= CNTL_REG(3 downto 2); -- parity mode (even/odd/none)
RX_EN <= CNTL_REG(1); -- receiver enable
TX_EN <= CNTL_REG(0); -- transmit enable
--=============================================
-- Register Reads
--=============================================
REGISTER_READS:
process (CS, REG_SEL, RX_FIFO_DATA, STAT_REG)
begin
RD_DATA <= RX_FIFO_DATA;
if (CS = '1') then
case REG_SEL is
when STAT_ADDR => -- status register
RD_DATA <= STAT_REG;
when others =>
end case;
end if;
end process;
--=========================================================================
-- RX Interrupt Generation Logic
--
-- Generated RX_IRQ if: Data is ready in the receiver reg
-- and the RX IRQ is not masked.
--=========================================================================
RX_IRQ_GENERATION:
process (RX_FIFO_FULL, MASK_REG)
begin
RX_IRQ <= '0';
if ((RX_FIFO_FULL = '1') and (MASK_REG(0)= '1')) then
RX_IRQ <= '1';
end if;
end process;
--=========================================================================
-- TX Interrupt Generation Logic
--
-- Generated TX_IRQ if: The transmitter is empty and the TX IRQ
-- is not masked and the transmitter is enabled
-- Note: The transmit interrupt can only be cleared by writing new data
-- to the transmit hold register or by disabling the transmitter.
--=========================================================================
TX_IRQ_GENERATION:
process (TX_FIFO_EMPTY, MASK_REG, TX_EN)
begin
TX_IRQ <= '0';
if ((TX_FIFO_EMPTY = '1') and (MASK_REG(1) = '1') and
(TX_EN = '1')) then
TX_IRQ <= '1';
end if;
end process;
TXD <= TXDI; -- transmit data from tx shift reg
RXDI <= RXD; -- receive data from pin
--================================================
-- Transmit state machine
--================================================
TRANSMIT_STATE_MACHINE:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
if (TX_CLK_EN = '1') then
TX_STATE <= TX_NSTATE;
end if;
-- reset state
if (RESET = '1') then
TX_STATE <= IDLE;
end if;
end if;
end process;
--================================================
-- Transmit shift counter
--
-- 0) 0011 3) 1011 6) 1100
-- 1) 0110 4) 0111 7) 1000
-- 2) 1101 5) 1110 8) 0000 <- TC
--
--================================================
TRANSMIT_SHIFT_COUNTER:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
if ((TX_STATE = SHIFT) and (TX_CLK_EN = '1')) then
TX_COUNT <= TX_COUNT(2 downto 0) &
not(TX_COUNT(0) xor TX_COUNT(3));
end if;
if (TX_STATE = IDLE) then
TX_COUNT <= TX_INIT;
end if;
end if;
end process;
--================================================
-- Transmit state machine next state logic
--================================================
TRANSMIT_NEXT_STATE_LOGIC:
process (TX_STATE, TX_SHIFT_EN, TX_CLK_EN,
TX_COUNT, PARITY_MODE)
begin
case TX_STATE is
when IDLE =>
-- detect the leading edge of the transmit shift enable
if (TX_SHIFT_EN = '1') then
TX_NSTATE <= LOAD;
else
TX_NSTATE <= IDLE;
end if;
when LOAD =>
-- detect the first transmit clock enable
if (TX_CLK_EN = '1') then
TX_NSTATE <= SHIFT;
else
TX_NSTATE <= LOAD;
end if;
when SHIFT =>
if ((TX_CLK_EN = '1') and (TX_COUNT = TX_TC)) then
if (PARITY_MODE = NONE) then
TX_NSTATE <= STOP;
else
TX_NSTATE <= PRTY;
end if;
else
TX_NSTATE <= SHIFT;
end if;
when PRTY =>
if (TX_CLK_EN = '1') then
TX_NSTATE <= STOP;
else
TX_NSTATE <= PRTY;
end if;
when STOP =>
if (TX_CLK_EN = '1') then
TX_NSTATE <= IDLE;
else
TX_NSTATE <= STOP;
end if;
when others =>
TX_NSTATE <= IDLE;
end case;
end process;
--================================================
-- Transmit Shift Enable
--================================================
TRANSMIT_SHIFT_ENABLE:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
-- TX_SHIFT_EN is active if:
-- the previous shift has finished (TX_STATE=IDLE) and
-- the FIFO has data (TX_FIFO_EMPTY=0) and
-- the transmitter is enabled (TX_EN=1)
if ((TX_STATE = IDLE) and (TX_FIFO_EMPTY = '0') and
(TX_EN = '1')) then
TX_SHIFT_EN <= '1';
elsif ((TX_STATE = STOP) and (TX_CLK_EN = '1')) then
TX_SHIFT_EN <= '0';
end if;
-- delay for edge detection
TX_SHIFT_EN1 <= TX_SHIFT_EN;
-- reset state
if ((RESET = '1') or (TX_EN = '0')) then
TX_SHIFT_EN <= '0';
TX_SHIFT_EN1 <= '0';
end if;
end if;
end process;
--=============================================
-- Transmit baud-rate clock divider
--=============================================
TRANSMIT_BAUD_CLK_DIVIDER:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
-- delayed baud clock for edge detection
TX_BCLK_DLY <= TX_BCLK;
if (TX_SHIFT_EN = '1') then
-- count
TX_BAUD <= TX_BAUD(14 downto 0) &
not(TX_BAUD(2) xor TX_BAUD(15));
-- reload at terminal count
if (TX_BAUD = CKDIV_TC) then
TX_BAUD <= PRELOAD;
TX_BCLK <= not TX_BCLK;
end if;
end if;
-- load the initial count on reset or
-- when we start to send a new frame
if ((RESET = '1') or
((TX_SHIFT_EN = '1') and (TX_SHIFT_EN1 = '0'))) then
TX_BAUD <= PRELOAD;
TX_BCLK <= '0';
end if;
end if;
end process;
--==========================================
-- Transmit Clock Enable
--==========================================
TRANSMIT_CLOCK_ENABLE:
process (TX_BCLK, TX_BCLK_DLY)
begin
if ((TX_BCLK = '0') and (TX_BCLK_DLY = '1')) then
-- center TX clock in the middle of the data
-- at the falling edge of TX_BCLK
TX_CLK_EN <= '1';
else
TX_CLK_EN <= '0';
end if;
end process;
--==========================================
-- Transmit Parity Generation
--==========================================
TRANSMITTER_PARITY_GENERATION:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
if (TX_STATE = IDLE) then
-- for odd parity init TX_PARITY to 1
-- for even parity init TX_PARITY to 0
TX_PARITY <= PARITY_MODE(0);
end if;
if ((TX_CLK_EN = '1') and (TX_STATE = SHIFT)) then
-- calculate parity during shift
TX_PARITY <= TX_PARITY xor TX_SHIFT_REG(0);
end if;
end if;
end process;
--==========================================
-- Transmit Shift Register
--==========================================
TRANSMIT_SHIFT_REGISTER:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
TX_SHIFT_LD <= '0';
-- load from the hold register
if (TX_SHIFT_EN = '1' and TX_SHIFT_EN1 = '0') then
TX_SHIFT_REG <= TX_FIFO_DATA;
TX_SHIFT_LD <= '1';
end if;
-- shift
if ((TX_CLK_EN = '1') and (TX_STATE = SHIFT)) then
TX_SHIFT_REG <= '1' & TX_SHIFT_REG(7 downto 1);
end if;
-- reset state
if (RESET = '1') then
TX_SHIFT_REG <= (others => '0');
end if;
end if;
end process;
--==========================================
-- Transmit Data
--==========================================
TRANSMIT_DATA:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
if (TX_CLK_EN = '1') then
TXDI <= '1'; -- mark bit
if (TX_STATE = LOAD) then
TXDI <= '0'; -- start bit
end if;
if (TX_STATE = SHIFT) then
TXDI <= TX_SHIFT_REG(0); -- data bit
end if;
if (TX_NSTATE = PRTY) then
TXDI <= TX_PARITY; -- parity bit
end if;
end if;
-- reset state
if (RESET = '1') then
TXDI <= '1';
end if;
end if;
end process;
--================================================
-- Receiver shift enable
--================================================
RECEIVER_SHIFT_ENABLE:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
-- RX_SHIFT_EN is active if the start bit is OK
-- and the shift register is not full.
-- It is only hi during data bits
if ((RX_STATE = IDLE) and (RX_START = '1') and
(RX_FIFO_STOP = '0')) then
RX_SHIFT_EN <= '1';
end if;
-- clear the RX shift enable
if ((RX_CLK_EN = '1') and (RX_STATE = D7)) then
RX_SHIFT_EN <= '0';
end if;
-- reset state
if ((RESET = '1') or (RX_EN = '0')) then
RX_SHIFT_EN <= '0';
end if;
end if;
end process;
--=============================================
-- Receiver baud-rate clock divider
--=============================================
RECEIVER_BAUD_CLK_DIVIDER:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
-- delayed baud clock for edge detection
RX_BCLK_DLY <= RX_BCLK;
if ((RX_SHIFT_EN = '1') or (RX_STATE /= IDLE)) then
-- count
RX_BAUD <= RX_BAUD(14 downto 0) &
not(RX_BAUD(2) xor RX_BAUD(15));
-- reload at terminal count
if (RX_BAUD = CKDIV_TC) then
RX_BAUD <= PRELOAD;
RX_BCLK <= not RX_BCLK;
end if;
end if;
-- load the initial count on Reset or
-- when we start to receive a new frame
if ((RESET = '1') or (RX_START = '1')) then
RX_BAUD <= PRELOAD;
RX_BCLK <= '0';
end if;
end if;
end process;
--==========================================
-- Receiver Clock Enable
--==========================================
RECEIVER_CLOCK_ENABLE:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
if ((RX_BCLK_DLY = '0') and (RX_BCLK = '1')) then
-- center RX clock in the middle of the data
-- at the rising edge of RX_BCLK
RX_CLK_EN <= '1';
else
RX_CLK_EN <= '0';
end if;
end if;
end process;
--==========================================
-- Receive start of frame
--==========================================
RECEIVE_START_OF_FRAME:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
-- find the falling edge of the start bit
if ((RX_STATE = IDLE) and
((RXD_SYNC1 = '0') and (RXD_SYNC = '1'))) then
RX_START <= '1';
else
RX_START <= '0';
end if;
-- reset state
if (RESET= '1') then
RX_START <= '0';
end if;
end if;
end process;
--================================================
-- Receiver shift counter
--
-- 0) 000 3) 101 6) 100 <- TC
-- 1) 001 4) 011
-- 2) 010 5) 110
--
--================================================
RECEIVER_SHIFT_COUNTER:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
if ((RX_STATE = SHIFT) and (RX_CLK_EN = '1')) then
RX_COUNT <= RX_COUNT(1 downto 0) &
not(RX_COUNT(0) xor RX_COUNT(2));
end if;
if (RX_STATE = IDLE) then
RX_COUNT <= RX_INIT;
end if;
end if;
end process;
--================================================
-- Receiver state machine
--================================================
RECEIVER_STATE_MACHINE:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
if (RX_CLK_EN = '1') then
RX_STATE <= RX_NSTATE;
end if;
-- reset state
if (RESET = '1') then
RX_STATE <= IDLE;
end if;
end if;
end process;
--=============================================================
-- Receiver state machine next state logic
--=============================================================
RECEIVER_NEXT_STATE_LOGIC:
process (RX_STATE, RX_ACCEPT, RX_COUNT, PARITY_MODE)
begin
case RX_STATE is
when IDLE =>
if (RX_ACCEPT = '1') then
RX_NSTATE <= SHIFT; -- accept data
else
RX_NSTATE <= IDLE; -- wait
end if;
when SHIFT =>
if (RX_COUNT = RX_TC) then
RX_NSTATE <= D7;
else
RX_NSTATE <= SHIFT;
end if;
when D7 =>
if (PARITY_MODE = NONE) then
RX_NSTATE <= STOP; -- skip parity
else
RX_NSTATE <= PRTY; -- get parity
end if;
when PRTY =>
RX_NSTATE <= STOP;
when STOP =>
RX_NSTATE <= IDLE;
when others =>
RX_NSTATE <= IDLE;
end case;
end process;
--================================================
-- Receiver shift register accept data
--================================================
RECEIVER_SHIFT_ACCEPT_DATA:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
-- RX_ACCEPT goes hi if start bit is OK & there's room
-- It stays hi until the data has been received
if ((RX_STATE = IDLE) and (RX_START = '1') and
(RX_FIFO_STOP = '0')) then
RX_ACCEPT<= '1';
end if;
if (RX_STATE = D7) then
RX_ACCEPT<= '0';
end if;
-- reset state
if ((RESET = '1') or (RX_EN = '0')) then
RX_ACCEPT <= '0';
end if;
end if;
end process;
--================================================
-- Receiver shift register
--================================================
RECEIVER_SHIFT_REGISTER:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
-- synchronize the received data
RXD_SYNC1 <= RXDI;
RXD_SYNC <= RXD_SYNC1;
-- shift in the data
if ((RX_CLK_EN = '1') and (RX_SHIFT_EN = '1')) then
RX_SHIFT_REG <= RXD_SYNC & RX_SHIFT_REG(7 downto 1);
end if;
end if;
end process;
--================================================
-- RX FIFO control
--================================================
RX_FIFO_CONTROL:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
RX_FIFO_OP <= '0';
RX_FIFO_CKEN <= '0';
-- push the RX FIFO when data received
if ((RX_CLK_EN = '1') and (RX_STATE = STOP)) then
RX_FIFO_OP <= '1';
RX_FIFO_CKEN <= '1';
end if;
-- RX FIFO on a uP read
if (RDV = '1') then
if ((CS = '1') and (REG_SEL = HOLD_ADDR)) then
RX_FIFO_OP <= '0';
RX_FIFO_CKEN <= '1';
end if;
end if;
end if;
end process;
--================================================
-- Receiver parity generation
--================================================
RECEIVER_PARITY_GENERATION:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
if ((RX_STATE = IDLE) and (RX_ACCEPT = '0')) then
-- for odd parity init RX_PARITY to 1
-- for even parity init RX_PARITY to 0
RX_PARITY <= PARITY_MODE(0);
else
if (RX_CLK_EN = '1') then
-- calculate parity during shift
RX_PARITY <= RX_PARITY xor RXD_SYNC;
end if;
end if;
end if;
end process;
--================================================
-- Receiver error flags
--================================================
RECEIVER_ERROR_FLAGS:
process (FCLK)
begin
-- PARITY_ERR is set when the calculated parity doesn't match
-- the received parity. It stays set until a character
-- without a parity error is received.
-- FRAMING_ERR is set if the stop bit=0. It stays set until
-- a character without a frame error is received.
-- OVERRUN_ERR set if a new start bit is seen but there's no room
-- for more data. It stays set until explicitly cleared.
if (FCLK = '0' and FCLK'event) then
if (RX_CLK_EN = '1') then
-- check for framing sync
if (RX_STATE = STOP) then
FRAMING_ERR <= not RXD_SYNC;
end if;
-- check parity
if ((RX_STATE = STOP) and (PARITY_MODE /= NONE)) then
PARITY_ERR <= RX_PARITY;
end if;
end if;
-- check for FIFO overrun
if ((RX_FIFO_STOP = '1') and (RX_STATE = IDLE) and
(RX_START = '1')) then
OVERRUN_ERR <= '1';
end if;
-- Clear framing error
if ((RX_EN = '0') or (STATUS_CLR = '1')) then
FRAMING_ERR <= '0';
end if;
-- Clear parity error
if ((RX_EN = '0') or (PARITY_MODE = NONE) or
(STATUS_CLR = '1')) then
PARITY_ERR <= '0';
end if;
-- Clear overrun error
if ((RX_EN = '0') or (STATUS_CLR = '1')) then
OVERRUN_ERR <= '0';
end if;
end if;
end process;
--================================================
-- RX FIFO flags
--================================================
RX_FIFO_FLAGS:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
-- set overflow
if (RX_FIFO_OVFL = '1') then
RX_FIFO_STOP <= '1';
end if;
-- reset state
if ((RESET = '1') or (STATUS_CLR = '1')) then
RX_FIFO_STOP <= '0';
end if;
end if;
end process;
--============================================
-- Instantiate the RX FIFO
--============================================
RX_FIFO: FIFO port map (
FIFO_OUT => RX_FIFO_DATA,
FIFO_IN => RX_SHIFT_REG,
OVFL => RX_FIFO_OVFL,
LAST => RX_FIFO_FULL,
EMPTY => RX_FIFO_EMPTY,
FIFO_OP => RX_FIFO_OP,
CKEN => RX_FIFO_CKEN,
CLK => FCLK,
RESET => RESET
);
--============================================
-- Instantiate the TX FIFO
--============================================
TX_FIFO: FIFO port map (
FIFO_OUT => TX_FIFO_DATA,
FIFO_IN => WR_DATA(7 downto 0),
OVFL => TX_FIFO_OVFL,
LAST => TX_FIFO_FULL,
EMPTY => TX_FIFO_EMPTY,
FIFO_OP => TX_FIFO_OP,
CKEN => TX_FIFO_CKEN,
CLK => FCLK,
RESET => RESET
);
end BEHAVIORAL;
|
gpl-3.0
|
e343ce68623e0332f951af9910eb8fc8
| 0.396406 | 4.568291 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
bcd2excess3/bcd2excess3.vhd
| 1 | 851 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bcd2excess3 is
Port ( A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
W : out std_logic;
X : out std_logic;
Y : out std_logic;
Z : out std_logic);
end bcd2excess3;
architecture Behavioral of bcd2excess3 is
signal T: std_logic;
begin
T <= C or D;
W <= A or ( B and T );
X <= ( ( not B ) and T ) or ( B and ( not C ) and ( not D ) );
Y <= ( C and D ) or ( ( not C ) and ( not D ) );
Z <= not D;
end Behavioral;
|
mit
|
f5005cd0364356daa6e70cd90a5b47ec
| 0.567568 | 3.199248 | false | false | false | false |
Digilent/vivado-library
|
ip/video_scaler/hdl/vhdl/video_scaler_udivibs.vhd
| 1 | 7,269 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity video_scaler_udivibs_div_u is
generic (
in0_WIDTH : INTEGER :=32;
in1_WIDTH : INTEGER :=32;
out_WIDTH : INTEGER :=32);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
dividend : in STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
divisor : in STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
quot : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
remd : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0));
function max (left, right : INTEGER) return INTEGER is
begin
if left > right then return left;
else return right;
end if;
end max;
end entity;
architecture rtl of video_scaler_udivibs_div_u is
constant cal_WIDTH : INTEGER := max(in0_WIDTH, in1_WIDTH);
type in0_vector is array(INTEGER range <>) of UNSIGNED(in0_WIDTH-1 downto 0);
type in1_vector is array(INTEGER range <>) of UNSIGNED(in1_WIDTH-1 downto 0);
type cal_vector is array(INTEGER range <>) of UNSIGNED(cal_WIDTH downto 0);
signal dividend_tmp : in0_vector(0 to in0_WIDTH);
signal divisor_tmp : in1_vector(0 to in0_WIDTH);
signal remd_tmp : in0_vector(0 to in0_WIDTH);
signal comb_tmp : in0_vector(0 to in0_WIDTH-1);
signal cal_tmp : cal_vector(0 to in0_WIDTH-1);
begin
quot <= STD_LOGIC_VECTOR(RESIZE(dividend_tmp(in0_WIDTH), out_WIDTH));
remd <= STD_LOGIC_VECTOR(RESIZE(remd_tmp(in0_WIDTH), out_WIDTH));
tran_tmp_proc : process (clk)
begin
if (clk'event and clk='1') then
if (ce = '1') then
dividend_tmp(0) <= UNSIGNED(dividend);
divisor_tmp(0) <= UNSIGNED(divisor);
remd_tmp(0) <= (others => '0');
end if;
end if;
end process tran_tmp_proc;
run_proc: for i in 0 to in0_WIDTH-1 generate
begin
comb_tmp(i) <= remd_tmp(i)(in0_WIDTH-2 downto 0) & dividend_tmp(i)(in0_WIDTH-1);
cal_tmp(i) <= ('0' & comb_tmp(i)) - ('0' & divisor_tmp(i));
process (clk)
begin
if (clk'event and clk='1') then
if (ce = '1') then
dividend_tmp(i+1) <= dividend_tmp(i)(in0_WIDTH-2 downto 0) & (not cal_tmp(i)(cal_WIDTH));
divisor_tmp(i+1) <= divisor_tmp(i);
if cal_tmp(i)(cal_WIDTH) = '1' then
remd_tmp(i+1) <= comb_tmp(i);
else
remd_tmp(i+1) <= cal_tmp(i)(in0_WIDTH-1 downto 0);
end if;
end if;
end if;
end process;
end generate run_proc;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity video_scaler_udivibs_div is
generic (
in0_WIDTH : INTEGER :=32;
in1_WIDTH : INTEGER :=32;
out_WIDTH : INTEGER :=32);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
dividend : in STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
divisor : in STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
quot : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
remd : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0));
end entity;
architecture rtl of video_scaler_udivibs_div is
component video_scaler_udivibs_div_u is
generic (
in0_WIDTH : INTEGER :=32;
in1_WIDTH : INTEGER :=32;
out_WIDTH : INTEGER :=32);
port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
dividend : in STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
divisor : in STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
quot : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
remd : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0));
end component;
signal dividend0 : STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
signal divisor0 : STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
signal dividend_u : STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
signal divisor_u : STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
signal quot_u : STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
signal remd_u : STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
begin
video_scaler_udivibs_div_u_0 : video_scaler_udivibs_div_u
generic map(
in0_WIDTH => in0_WIDTH,
in1_WIDTH => in1_WIDTH,
out_WIDTH => out_WIDTH)
port map(
clk => clk,
reset => reset,
ce => ce,
dividend => dividend_u,
divisor => divisor_u,
quot => quot_u,
remd => remd_u);
dividend_u <= dividend0;
divisor_u <= divisor0;
process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
dividend0 <= dividend;
divisor0 <= divisor;
end if;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
quot <= quot_u;
remd <= remd_u;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity video_scaler_udivibs is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of video_scaler_udivibs is
component video_scaler_udivibs_div is
generic (
in0_WIDTH : INTEGER;
in1_WIDTH : INTEGER;
out_WIDTH : INTEGER);
port (
dividend : IN STD_LOGIC_VECTOR;
divisor : IN STD_LOGIC_VECTOR;
quot : OUT STD_LOGIC_VECTOR;
remd : OUT STD_LOGIC_VECTOR;
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
reset : IN STD_LOGIC);
end component;
signal sig_quot : STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0);
signal sig_remd : STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0);
begin
video_scaler_udivibs_div_U : component video_scaler_udivibs_div
generic map (
in0_WIDTH => din0_WIDTH,
in1_WIDTH => din1_WIDTH,
out_WIDTH => dout_WIDTH)
port map (
dividend => din0,
divisor => din1,
quot => dout,
remd => sig_remd,
clk => clk,
ce => ce,
reset => reset);
end architecture;
|
mit
|
5a8ee34d39d25ce8bb73cc2adcfc33a2
| 0.529371 | 3.542398 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodDigitizerController/tb/TWI_SlaveCtl.vhd
| 1 | 11,407 |
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a two-wire (I2C compatible) slave controller responding
-- to the address defined in SLAVE_ADDRESS. It samples the bus and
-- deserializes data. The module needs to be controlled in turn by a
-- high-level controller.
-- Status signals:
-- DONE_O active-high pulsed when the slave is addressed by a master,
-- or when a data byte is either sent or received
-- END_O active-high pulsed when the master ended the transfer
-- RD_WRN_O high when transfer is read, low when write
-- Control signals:
-- STB_I needs to be held high when the current byte needs to be
-- acknowledged; this is the case for the device address, as
-- well as every byte written to-slave
-- D_I data needs to be provided on this bus when read transaction
-- occurs; needs to be held until DONE_O
-- D_O data will appear on D_O when a write transaction occurs;
-- valid on DONE_O
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use IEEE.NUMERIC_STD.ALL;
entity TWI_SlaveCtl is
generic (
SLAVE_ADDRESS : std_logic_vector(7 downto 0) := x"A0"; -- TWI Slave address
kSampleClkFreqInMHz : natural := 100
);
Port ( D_I : in STD_LOGIC_VECTOR (7 downto 0);
D_O : out STD_LOGIC_VECTOR (7 downto 0);
RD_WRN_O : out STD_LOGIC;
END_O : out STD_LOGIC;
DONE_O : out STD_LOGIC;
STB_I : in STD_LOGIC;
SampleClk : in STD_LOGIC;
SRST : in STD_LOGIC;
--two-wire bus
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_T : out STD_LOGIC;
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_T : out STD_LOGIC
);
end TWI_SlaveCtl;
architecture Behavioral of TWI_SlaveCtl is
constant kGlitchDurationInNs : natural := 50; --tSP in I2C specs
constant kNoOfPeriodsToFilter : natural := natural(ceil(real(kGlitchDurationInNs * kSampleClkFreqInMHz) / 1000.0));
attribute fsm_encoding: string;
type state_type is (stIdle, stAddress, stRead, stWrite, stSAck, stMAck, stTurnAround);
signal state, nstate : state_type;
attribute fsm_encoding of state: signal is "gray";
signal dSda, ddSda, dScl, ddScl : std_logic;
signal fStart, fStop, fSCLFalling, fSCLRising : std_logic;
signal dataByte : std_logic_vector(7 downto 0); --shift register and parallel load
signal iEnd, iDone, latchData, dataBitOut, shiftBitIn, shiftBitOut : std_logic;
signal rd_wrn, drive : std_logic;
signal bitCount : natural range 0 to 7 := 7;
signal sSda, sScl, sSdaFtr, sSclFtr : std_logic;
begin
-- Synchronize SDA and SCL inputs
SyncSDA: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aoReset => '0',
aIn => SDA_I,
OutClk => SampleClk,
oOut => sSda);
SyncSCL: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aoReset => '0',
aIn => SCL_I,
OutClk => SampleClk,
oOut => sScl);
-- Glitch filter as required by I2C Fast-mode specs
GlitchF_SDA: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sSda,
sOut => sSdaFtr,
sRst => SRST);
GlitchF_SCL: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sScl,
sOut => sSclFtr,
sRst => SRST);
----------------------------------------------------------------------------------
--Bus State detection
----------------------------------------------------------------------------------
EdgeDetect: process(SampleClk)
begin
if Rising_Edge(SampleClk) then
dSda <= to_X01(sSdaFtr);
ddSda <= to_X01(dSda);
dScl <= to_X01(sSclFtr);
ddScl <= to_X01(dScl);
end if;
end process;
fStart <= dSCL and not dSda and ddSda; --if SCL high while SDA falling, start condition
fStop <= dSCL and dSda and not ddSda; --if SCL high while SDA rising, stop condition
fSCLFalling <= ddSCL and not dScl; -- SCL falling
fSCLRising <= not ddSCL and dScl; -- SCL rising
----------------------------------------------------------------------------------
-- Open-drain outputs for bi-directional SDA and SCL
----------------------------------------------------------------------------------
SDA_T <= '1' when dataBitOut = '1' or drive = '0' else -- high-Z
'0'; --drive
SDA_O <= '0';
SCL_T <= '1'; -- input 4eva
SCL_O <= '0';
----------------------------------------------------------------------------------
-- Title: Data byte shift register
-- Description: Stores the byte to be written or the byte read depending on the
-- transfer direction.
----------------------------------------------------------------------------------
DATABYTE_SHREG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if ((latchData = '1' and fSCLFalling = '1') or state = stIdle or fStart = '1') then
dataByte <= D_I; --latch data
bitCount <= 7;
elsif (shiftBitOut = '1' and fSCLFalling = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
elsif (shiftBitIn = '1' and fSCLRising = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
end if;
end if;
end process;
dataBitOut <= '0' when state = stSAck else
dataByte(dataByte'high);
D_O <= dataByte;
RD_WRN_O <= to_X01(rd_wrn);
RDWRN_BIT_REG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (state = stAddress and bitCount = 0 and fSCLRising = '1') then
rd_wrn <= to_X01(dSDA);
end if;
end if;
end process;
SYNC_PROC: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
state <= nstate;
END_O <= iEnd;
DONE_O <= iDone;
end if;
end process;
OUTPUT_DECODE: process (nstate, state, fSCLRising, fSCLFalling, ddSDA, bitCount, rd_wrn, dataByte, fStop, fStart)
begin
iDone <= '0';
iEnd <= '0';
shiftBitIn <= '0';
shiftBitOut <= '0';
latchData <= '0';
drive <= '0';
if (state = stRead or state = stSAck) then
drive <= '1';
end if;
if (state = stAddress or state = stWrite) then
shiftBitIn <= '1';
end if;
if (state = stRead) then
shiftBitOut <= '1';
end if;
if ((state = stSAck) or
(state = stMAck and ddSda = '0')) then --get the data byte for the next read
latchData <= '1';
end if;
if ((state = stAddress and bitCount = 0 and fSCLRising = '1' and dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) or
(state = stWrite and bitCount = 0 and fSCLRising = '1') or
(state = stRead and bitCount = 0 and fSCLFalling = '1')) then
iDone <= '1';
end if;
if (fStop = '1' or fStart = '1' or
(state = stMAck and fSCLRising = '1' and ddSDA = '1')) then
iEnd <= '1';
end if;
end process;
NEXT_STATE_DECODE: process (state, fStart, STB_I, fSCLRising, fSCLFalling, bitCount, ddSDA, rd_wrn, dataByte, fStop)
begin
nstate <= state; --default is to stay in current state
case (state) is
when stIdle =>
if (fStart = '1') then -- start condition received
nstate <= stAddress;
end if;
when stAddress =>
if (fStop = '1') then
nstate <= stIdle;
elsif (bitCount = 0 and fSCLRising = '1') then
if (dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) then
nstate <= stTurnAround;
else
nstate <= stIdle;
end if;
end if;
when stTurnAround =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (STB_I = '1') then
nstate <= stSAck; --we acknowledge and continue
else
nstate <= stIdle; --don't ack and stop
end if;
end if;
when stSAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif fSCLFalling = '1' then
if (rd_wrn = '1') then
nstate <= stRead;
else
nstate <= stWrite;
end if;
end if;
when stWrite =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLRising = '1') then
nstate <= stTurnAround;
end if;
when stMAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (ddSDA = '1') then
nstate <= stIdle;
else
nstate <= stRead;
end if;
end if;
when stRead =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLFalling = '1') then
nstate <= stMAck;
end if;
when others =>
nstate <= stIdle;
end case;
end process;
end Behavioral;
|
mit
|
0ccf996f6d5f1d6345921f42efcbf995
| 0.577891 | 3.952529 | false | false | false | false |
Digilent/vivado-library
|
ip/axi_dynclk/src/SyncAsync.vhd
| 1 | 3,823 |
-------------------------------------------------------------------------------
--
-- File: SyncAsync.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module synchronizes the asynchronous signal (aIn) with the OutClk clock
-- domain and provides it on oOut. The number of FFs in the synchronizer chain
-- can be configured with kStages. The reset value for oOut can be configured
-- with kResetTo. The asynchronous reset (aReset) is always active-high.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SyncAsync is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2; --double sync by default
kResetPolarity : std_logic := '1'); --aReset active-high by default
Port (
aReset : in STD_LOGIC; -- active-high/active-low asynchronous reset
aIn : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end SyncAsync;
architecture Behavioral of SyncAsync is
signal oSyncStages : std_logic_vector(kStages-1 downto 0) := (others => kResetTo);
attribute ASYNC_REG : string;
attribute ASYNC_REG of oSyncStages: signal is "TRUE";
begin
Sync: process (OutClk, aReset)
begin
if (aReset = kResetPolarity) then
oSyncStages <= (others => kResetTo);
elsif Rising_Edge(OutClk) then
oSyncStages <= oSyncStages(oSyncStages'high-1 downto 0) & aIn;
end if;
end process Sync;
oOut <= oSyncStages(oSyncStages'high);
end Behavioral;
|
mit
|
caab8b1b0e56348ad1793bf3cee04cf5
| 0.678525 | 4.69656 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/CvtColor_1.vhd
| 1 | 65,520 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CvtColor_1 is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_src_rows_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
p_src_rows_V_empty_n : IN STD_LOGIC;
p_src_rows_V_read : OUT STD_LOGIC;
p_src_cols_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
p_src_cols_V_empty_n : IN STD_LOGIC;
p_src_cols_V_read : OUT STD_LOGIC;
p_src_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_0_V_empty_n : IN STD_LOGIC;
p_src_data_stream_0_V_read : OUT STD_LOGIC;
p_src_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_1_V_empty_n : IN STD_LOGIC;
p_src_data_stream_1_V_read : OUT STD_LOGIC;
p_src_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_2_V_empty_n : IN STD_LOGIC;
p_src_data_stream_2_V_read : OUT STD_LOGIC;
p_dst_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_0_V_full_n : IN STD_LOGIC;
p_dst_data_stream_0_V_write : OUT STD_LOGIC;
p_dst_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_1_V_full_n : IN STD_LOGIC;
p_dst_data_stream_1_V_write : OUT STD_LOGIC;
p_dst_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_2_V_full_n : IN STD_LOGIC;
p_dst_data_stream_2_V_write : OUT STD_LOGIC );
end;
architecture behav of CvtColor_1 is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv19_0 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000000000";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv20_0 : STD_LOGIC_VECTOR (19 downto 0) := "00000000000000000000";
constant ap_const_lv5_5 : STD_LOGIC_VECTOR (4 downto 0) := "00101";
constant ap_const_lv5_1A : STD_LOGIC_VECTOR (4 downto 0) := "11010";
constant ap_const_lv32_2E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101110";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
constant ap_const_lv24_4444 : STD_LOGIC_VECTOR (23 downto 0) := "000000000100010001000100";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal sector_data_0_address0 : STD_LOGIC_VECTOR (2 downto 0);
signal sector_data_0_ce0 : STD_LOGIC;
signal sector_data_0_q0 : STD_LOGIC_VECTOR (1 downto 0);
signal sector_data_1_address0 : STD_LOGIC_VECTOR (2 downto 0);
signal sector_data_1_ce0 : STD_LOGIC;
signal sector_data_1_q0 : STD_LOGIC_VECTOR (1 downto 0);
signal sector_data_2_address0 : STD_LOGIC_VECTOR (2 downto 0);
signal sector_data_2_ce0 : STD_LOGIC;
signal sector_data_2_q0 : STD_LOGIC_VECTOR (1 downto 0);
signal p_src_rows_V_blk_n : STD_LOGIC;
signal p_src_cols_V_blk_n : STD_LOGIC;
signal p_src_data_stream_0_V_blk_n : STD_LOGIC;
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_block_pp0_stage0 : BOOLEAN;
signal tmp_53_i_reg_783 : STD_LOGIC_VECTOR (0 downto 0);
signal p_src_data_stream_1_V_blk_n : STD_LOGIC;
signal p_src_data_stream_2_V_blk_n : STD_LOGIC;
signal p_dst_data_stream_0_V_blk_n : STD_LOGIC;
signal ap_enable_reg_pp0_iter10 : STD_LOGIC := '0';
signal ap_reg_pp0_iter9_tmp_53_i_reg_783 : STD_LOGIC_VECTOR (0 downto 0);
signal p_dst_data_stream_1_V_blk_n : STD_LOGIC;
signal p_dst_data_stream_2_V_blk_n : STD_LOGIC;
signal j_i_reg_226 : STD_LOGIC_VECTOR (10 downto 0);
signal p_src_cols_V_read_reg_764 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_block_state1 : BOOLEAN;
signal p_src_rows_V_read_reg_769 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_i_fu_241_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal i_fu_246_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal i_reg_778 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_53_i_fu_256_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state5_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_state6_pp0_stage0_iter3 : BOOLEAN;
signal ap_block_state7_pp0_stage0_iter4 : BOOLEAN;
signal ap_block_state8_pp0_stage0_iter5 : BOOLEAN;
signal ap_block_state9_pp0_stage0_iter6 : BOOLEAN;
signal ap_block_state10_pp0_stage0_iter7 : BOOLEAN;
signal ap_block_state11_pp0_stage0_iter8 : BOOLEAN;
signal ap_block_state12_pp0_stage0_iter9 : BOOLEAN;
signal ap_block_state13_pp0_stage0_iter10 : BOOLEAN;
signal ap_block_pp0_stage0_11001 : BOOLEAN;
signal ap_reg_pp0_iter1_tmp_53_i_reg_783 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter2_tmp_53_i_reg_783 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter3_tmp_53_i_reg_783 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter4_tmp_53_i_reg_783 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter5_tmp_53_i_reg_783 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter6_tmp_53_i_reg_783 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter7_tmp_53_i_reg_783 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter8_tmp_53_i_reg_783 : STD_LOGIC_VECTOR (0 downto 0);
signal j_fu_261_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal tmp_26_reg_792 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_tmp_26_reg_792 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_27_reg_797 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_tmp_27_reg_797 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_27_reg_797 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_28_reg_804 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_tmp_28_reg_804 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_reg_811 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter2_tmp_reg_811 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_fu_275_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_10_reg_816 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_reg_pp0_iter2_tmp_10_reg_816 : STD_LOGIC_VECTOR (6 downto 0);
signal p_Val2_i_fu_752_p2 : STD_LOGIC_VECTOR (26 downto 0);
signal p_Val2_i_reg_821 : STD_LOGIC_VECTOR (26 downto 0);
signal r_V_3_fu_758_p2 : STD_LOGIC_VECTOR (23 downto 0);
signal r_V_3_reg_827 : STD_LOGIC_VECTOR (23 downto 0);
signal tab_0_V_fu_346_p3 : STD_LOGIC_VECTOR (27 downto 0);
signal tab_0_V_reg_833 : STD_LOGIC_VECTOR (27 downto 0);
signal ap_reg_pp0_iter4_tab_0_V_reg_833 : STD_LOGIC_VECTOR (27 downto 0);
signal ap_reg_pp0_iter5_tab_0_V_reg_833 : STD_LOGIC_VECTOR (27 downto 0);
signal ap_reg_pp0_iter6_tab_0_V_reg_833 : STD_LOGIC_VECTOR (27 downto 0);
signal ap_reg_pp0_iter7_tab_0_V_reg_833 : STD_LOGIC_VECTOR (27 downto 0);
signal ap_reg_pp0_iter8_tab_0_V_reg_833 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_s_fu_356_p4 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_s_reg_843 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_pp0_iter5_tmp_s_reg_843 : STD_LOGIC_VECTOR (4 downto 0);
signal f_V_fu_377_p2 : STD_LOGIC_VECTOR (24 downto 0);
signal f_V_reg_850 : STD_LOGIC_VECTOR (24 downto 0);
signal tab_1_V_fu_390_p2 : STD_LOGIC_VECTOR (27 downto 0);
signal tab_1_V_reg_855 : STD_LOGIC_VECTOR (27 downto 0);
signal ap_reg_pp0_iter5_tab_1_V_reg_855 : STD_LOGIC_VECTOR (27 downto 0);
signal ap_reg_pp0_iter6_tab_1_V_reg_855 : STD_LOGIC_VECTOR (27 downto 0);
signal ap_reg_pp0_iter7_tab_1_V_reg_855 : STD_LOGIC_VECTOR (27 downto 0);
signal ap_reg_pp0_iter8_tab_1_V_reg_855 : STD_LOGIC_VECTOR (27 downto 0);
signal r_V_fu_402_p2 : STD_LOGIC_VECTOR (28 downto 0);
signal r_V_reg_863 : STD_LOGIC_VECTOR (28 downto 0);
signal h_i_1_fu_434_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal h_i_1_reg_878 : STD_LOGIC_VECTOR (4 downto 0);
signal grp_fu_418_p2 : STD_LOGIC_VECTOR (46 downto 0);
signal p_Val2_4_i_reg_883 : STD_LOGIC_VECTOR (46 downto 0);
signal tab_2_V_reg_904 : STD_LOGIC_VECTOR (27 downto 0);
signal tab_3_V_reg_911 : STD_LOGIC_VECTOR (27 downto 0);
signal sector_data_0_load_reg_918 : STD_LOGIC_VECTOR (1 downto 0);
signal sector_data_1_load_reg_923 : STD_LOGIC_VECTOR (1 downto 0);
signal sector_data_2_load_reg_928 : STD_LOGIC_VECTOR (1 downto 0);
signal p_Val2_20_fu_570_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Val2_20_reg_933 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Val2_21_fu_657_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Val2_21_reg_938 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Val2_22_fu_744_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Val2_22_reg_943 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_pp0_stage0_subdone : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC;
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter5 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter6 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter7 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter8 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter9 : STD_LOGIC := '0';
signal i_i_reg_215 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_CS_fsm_state14 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state14 : signal is "none";
signal tmp_79_i_fu_441_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage0_01001 : BOOLEAN;
signal i_cast_i_cast_fu_237_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal j_cast_i_cast_fu_252_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal r_V_4_fu_279_p4 : STD_LOGIC_VECTOR (18 downto 0);
signal tmp_62_i_fu_303_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_61_i_fu_300_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_63_i_fu_306_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_65_i_fu_312_p3 : STD_LOGIC_VECTOR (27 downto 0);
signal p_Val2_cast_i_fu_297_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_66_i_fu_326_p3 : STD_LOGIC_VECTOR (25 downto 0);
signal tmp_66_cast_i_fu_333_p1 : STD_LOGIC_VECTOR (26 downto 0);
signal p_Val2_2_i_fu_337_p2 : STD_LOGIC_VECTOR (26 downto 0);
attribute use_dsp48 : string;
attribute use_dsp48 of p_Val2_2_i_fu_337_p2 : signal is "no";
signal p_Val2_1_i_fu_320_p2 : STD_LOGIC_VECTOR (27 downto 0);
signal p_Val2_2_cast_i_fu_342_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_55_i_fu_365_p3 : STD_LOGIC_VECTOR (23 downto 0);
signal r_V_10_cast1_i_cast_fu_353_p1 : STD_LOGIC_VECTOR (24 downto 0);
signal tmp_55_cast_i_cast_fu_373_p1 : STD_LOGIC_VECTOR (24 downto 0);
signal tmp_67_i_fu_383_p3 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_68_i_fu_395_p1 : STD_LOGIC_VECTOR (28 downto 0);
signal tmp_69_i_fu_398_p1 : STD_LOGIC_VECTOR (28 downto 0);
signal f_V_cast_fu_408_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal grp_fu_418_p1 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_58_i_fu_424_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal h_i_fu_429_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_71_i_fu_447_p3 : STD_LOGIC_VECTOR (46 downto 0);
signal p_Val2_5_fu_454_p2 : STD_LOGIC_VECTOR (46 downto 0);
signal tmp_76_i_fu_469_p3 : STD_LOGIC_VECTOR (46 downto 0);
signal p_Val2_6_fu_476_p2 : STD_LOGIC_VECTOR (46 downto 0);
signal p_Val2_7_fu_491_p6 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_11_fu_510_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_8_fu_500_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_i_i_i_fu_518_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Val2_9_fu_530_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_13_fu_536_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_12_fu_522_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_14_i_i_i_fu_544_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal carry_fu_550_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal lD_fu_556_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal Range1_all_ones_fu_564_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_11_fu_578_p6 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_15_fu_597_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_12_fu_587_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_i_i109_i_fu_605_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Val2_13_fu_617_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_17_fu_623_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_16_fu_609_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_14_i_i113_i_fu_631_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal carry_1_fu_637_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal lD_1_fu_643_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal Range1_all_ones_6_fu_651_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_s_fu_665_p6 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_19_fu_684_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_17_fu_674_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_i_i122_i_fu_692_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Val2_18_fu_704_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_21_fu_710_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_20_fu_696_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_14_i_i126_i_fu_718_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal carry_2_fu_724_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal lD_2_fu_730_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal Range1_all_ones_7_fu_738_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_i_fu_752_p0 : STD_LOGIC_VECTOR (18 downto 0);
signal p_Val2_i_fu_752_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal r_V_3_fu_758_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal r_V_3_fu_758_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_418_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
signal grp_fu_418_p10 : STD_LOGIC_VECTOR (46 downto 0);
signal p_Val2_i_fu_752_p00 : STD_LOGIC_VECTOR (26 downto 0);
signal p_Val2_i_fu_752_p10 : STD_LOGIC_VECTOR (26 downto 0);
signal r_V_3_fu_758_p10 : STD_LOGIC_VECTOR (23 downto 0);
component hls_saturation_enpcA IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (28 downto 0);
din1 : IN STD_LOGIC_VECTOR (27 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (46 downto 0) );
end component;
component hls_saturation_enqcK IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
din3_WIDTH : INTEGER;
din4_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (27 downto 0);
din1 : IN STD_LOGIC_VECTOR (27 downto 0);
din2 : IN STD_LOGIC_VECTOR (27 downto 0);
din3 : IN STD_LOGIC_VECTOR (27 downto 0);
din4 : IN STD_LOGIC_VECTOR (1 downto 0);
dout : OUT STD_LOGIC_VECTOR (27 downto 0) );
end component;
component hls_saturation_enrcU IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (18 downto 0);
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
dout : OUT STD_LOGIC_VECTOR (26 downto 0) );
end component;
component hls_saturation_ensc4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (15 downto 0);
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
dout : OUT STD_LOGIC_VECTOR (23 downto 0) );
end component;
component CvtColor_1_sectormb6 IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (2 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (1 downto 0) );
end component;
component CvtColor_1_sectorncg IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (2 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (1 downto 0) );
end component;
component CvtColor_1_sectorocq IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (2 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (1 downto 0) );
end component;
begin
sector_data_0_U : component CvtColor_1_sectormb6
generic map (
DataWidth => 2,
AddressRange => 6,
AddressWidth => 3)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => sector_data_0_address0,
ce0 => sector_data_0_ce0,
q0 => sector_data_0_q0);
sector_data_1_U : component CvtColor_1_sectorncg
generic map (
DataWidth => 2,
AddressRange => 6,
AddressWidth => 3)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => sector_data_1_address0,
ce0 => sector_data_1_ce0,
q0 => sector_data_1_q0);
sector_data_2_U : component CvtColor_1_sectorocq
generic map (
DataWidth => 2,
AddressRange => 6,
AddressWidth => 3)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => sector_data_2_address0,
ce0 => sector_data_2_ce0,
q0 => sector_data_2_q0);
hls_saturation_enpcA_U60 : component hls_saturation_enpcA
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 29,
din1_WIDTH => 28,
dout_WIDTH => 47)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => r_V_reg_863,
din1 => grp_fu_418_p1,
ce => grp_fu_418_ce,
dout => grp_fu_418_p2);
hls_saturation_enqcK_U61 : component hls_saturation_enqcK
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 28,
din1_WIDTH => 28,
din2_WIDTH => 28,
din3_WIDTH => 28,
din4_WIDTH => 2,
dout_WIDTH => 28)
port map (
din0 => ap_reg_pp0_iter8_tab_0_V_reg_833,
din1 => ap_reg_pp0_iter8_tab_1_V_reg_855,
din2 => tab_2_V_reg_904,
din3 => tab_3_V_reg_911,
din4 => sector_data_0_load_reg_918,
dout => p_Val2_7_fu_491_p6);
hls_saturation_enqcK_U62 : component hls_saturation_enqcK
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 28,
din1_WIDTH => 28,
din2_WIDTH => 28,
din3_WIDTH => 28,
din4_WIDTH => 2,
dout_WIDTH => 28)
port map (
din0 => ap_reg_pp0_iter8_tab_0_V_reg_833,
din1 => ap_reg_pp0_iter8_tab_1_V_reg_855,
din2 => tab_2_V_reg_904,
din3 => tab_3_V_reg_911,
din4 => sector_data_1_load_reg_923,
dout => p_Val2_11_fu_578_p6);
hls_saturation_enqcK_U63 : component hls_saturation_enqcK
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 28,
din1_WIDTH => 28,
din2_WIDTH => 28,
din3_WIDTH => 28,
din4_WIDTH => 2,
dout_WIDTH => 28)
port map (
din0 => ap_reg_pp0_iter8_tab_0_V_reg_833,
din1 => ap_reg_pp0_iter8_tab_1_V_reg_855,
din2 => tab_2_V_reg_904,
din3 => tab_3_V_reg_911,
din4 => sector_data_2_load_reg_928,
dout => p_Val2_s_fu_665_p6);
hls_saturation_enrcU_U64 : component hls_saturation_enrcU
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 19,
din1_WIDTH => 8,
dout_WIDTH => 27)
port map (
din0 => p_Val2_i_fu_752_p0,
din1 => p_Val2_i_fu_752_p1,
dout => p_Val2_i_fu_752_p2);
hls_saturation_ensc4_U65 : component hls_saturation_ensc4
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 16,
din1_WIDTH => 8,
dout_WIDTH => 24)
port map (
din0 => r_V_3_fu_758_p0,
din1 => r_V_3_fu_758_p1,
dout => r_V_3_fu_758_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_continue = ap_const_logic_1)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_241_p2 = ap_const_lv1_0))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_241_p2 = ap_const_lv1_1))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3)) then
ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state3);
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end if;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter10_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter10 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_241_p2 = ap_const_lv1_1))) then
ap_enable_reg_pp0_iter10 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter6 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter7 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter8 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter9 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8;
end if;
end if;
end if;
end process;
i_i_reg_215_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state14)) then
i_i_reg_215 <= i_reg_778;
elsif ((not(((ap_start = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
i_i_reg_215 <= ap_const_lv11_0;
end if;
end if;
end process;
j_i_reg_226_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (tmp_53_i_fu_256_p2 = ap_const_lv1_1))) then
j_i_reg_226 <= j_fu_261_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_241_p2 = ap_const_lv1_1))) then
j_i_reg_226 <= ap_const_lv11_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_reg_pp0_iter1_tmp_53_i_reg_783 <= tmp_53_i_reg_783;
tmp_53_i_reg_783 <= tmp_53_i_fu_256_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_0 = ap_block_pp0_stage0_11001)) then
ap_reg_pp0_iter2_tmp_10_reg_816 <= tmp_10_reg_816;
ap_reg_pp0_iter2_tmp_26_reg_792 <= tmp_26_reg_792;
ap_reg_pp0_iter2_tmp_27_reg_797 <= tmp_27_reg_797;
ap_reg_pp0_iter2_tmp_28_reg_804 <= tmp_28_reg_804;
ap_reg_pp0_iter2_tmp_53_i_reg_783 <= ap_reg_pp0_iter1_tmp_53_i_reg_783;
ap_reg_pp0_iter2_tmp_reg_811 <= tmp_reg_811;
ap_reg_pp0_iter3_tmp_27_reg_797 <= ap_reg_pp0_iter2_tmp_27_reg_797;
ap_reg_pp0_iter3_tmp_53_i_reg_783 <= ap_reg_pp0_iter2_tmp_53_i_reg_783;
ap_reg_pp0_iter4_tab_0_V_reg_833 <= tab_0_V_reg_833;
ap_reg_pp0_iter4_tmp_53_i_reg_783 <= ap_reg_pp0_iter3_tmp_53_i_reg_783;
ap_reg_pp0_iter5_tab_0_V_reg_833 <= ap_reg_pp0_iter4_tab_0_V_reg_833;
ap_reg_pp0_iter5_tab_1_V_reg_855 <= tab_1_V_reg_855;
ap_reg_pp0_iter5_tmp_53_i_reg_783 <= ap_reg_pp0_iter4_tmp_53_i_reg_783;
ap_reg_pp0_iter5_tmp_s_reg_843 <= tmp_s_reg_843;
ap_reg_pp0_iter6_tab_0_V_reg_833 <= ap_reg_pp0_iter5_tab_0_V_reg_833;
ap_reg_pp0_iter6_tab_1_V_reg_855 <= ap_reg_pp0_iter5_tab_1_V_reg_855;
ap_reg_pp0_iter6_tmp_53_i_reg_783 <= ap_reg_pp0_iter5_tmp_53_i_reg_783;
ap_reg_pp0_iter7_tab_0_V_reg_833 <= ap_reg_pp0_iter6_tab_0_V_reg_833;
ap_reg_pp0_iter7_tab_1_V_reg_855 <= ap_reg_pp0_iter6_tab_1_V_reg_855;
ap_reg_pp0_iter7_tmp_53_i_reg_783 <= ap_reg_pp0_iter6_tmp_53_i_reg_783;
ap_reg_pp0_iter8_tab_0_V_reg_833 <= ap_reg_pp0_iter7_tab_0_V_reg_833;
ap_reg_pp0_iter8_tab_1_V_reg_855 <= ap_reg_pp0_iter7_tab_1_V_reg_855;
ap_reg_pp0_iter8_tmp_53_i_reg_783 <= ap_reg_pp0_iter7_tmp_53_i_reg_783;
ap_reg_pp0_iter9_tmp_53_i_reg_783 <= ap_reg_pp0_iter8_tmp_53_i_reg_783;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_reg_pp0_iter3_tmp_53_i_reg_783 = ap_const_lv1_1))) then
f_V_reg_850 <= f_V_fu_377_p2;
r_V_reg_863 <= r_V_fu_402_p2;
tab_1_V_reg_855 <= tab_1_V_fu_390_p2;
tmp_s_reg_843 <= r_V_3_reg_827(23 downto 19);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_reg_pp0_iter5_tmp_53_i_reg_783 = ap_const_lv1_1))) then
h_i_1_reg_878 <= h_i_1_fu_434_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
i_reg_778 <= i_fu_246_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_reg_pp0_iter8_tmp_53_i_reg_783 = ap_const_lv1_1))) then
p_Val2_20_reg_933 <= p_Val2_20_fu_570_p3;
p_Val2_21_reg_938 <= p_Val2_21_fu_657_p3;
p_Val2_22_reg_943 <= p_Val2_22_fu_744_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_reg_pp0_iter6_tmp_53_i_reg_783 = ap_const_lv1_1))) then
p_Val2_4_i_reg_883 <= grp_fu_418_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_reg_pp0_iter1_tmp_53_i_reg_783 = ap_const_lv1_1))) then
p_Val2_i_reg_821 <= p_Val2_i_fu_752_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_start = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_src_cols_V_read_reg_764 <= p_src_cols_V_dout;
p_src_rows_V_read_reg_769 <= p_src_rows_V_dout;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_reg_pp0_iter2_tmp_53_i_reg_783 = ap_const_lv1_1))) then
r_V_3_reg_827 <= r_V_3_fu_758_p2;
tab_0_V_reg_833 <= tab_0_V_fu_346_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_reg_pp0_iter7_tmp_53_i_reg_783 = ap_const_lv1_1))) then
sector_data_0_load_reg_918 <= sector_data_0_q0;
sector_data_1_load_reg_923 <= sector_data_1_q0;
sector_data_2_load_reg_928 <= sector_data_2_q0;
tab_2_V_reg_904 <= p_Val2_5_fu_454_p2(46 downto 19);
tab_3_V_reg_911 <= p_Val2_6_fu_476_p2(46 downto 19);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_53_i_reg_783 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
tmp_10_reg_816 <= tmp_10_fu_275_p1;
tmp_26_reg_792 <= p_src_data_stream_0_V_dout;
tmp_27_reg_797 <= p_src_data_stream_1_V_dout;
tmp_28_reg_804 <= p_src_data_stream_2_V_dout;
tmp_reg_811 <= p_src_data_stream_1_V_dout(7 downto 7);
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, p_src_rows_V_empty_n, p_src_cols_V_empty_n, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter10, tmp_i_fu_241_p2, ap_CS_fsm_state2, tmp_53_i_fu_256_p2, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_subdone, ap_enable_reg_pp0_iter9)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if ((not(((ap_start = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_241_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage0 =>
if ((not(((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (tmp_53_i_fu_256_p2 = ap_const_lv1_0))) and not(((ap_enable_reg_pp0_iter9 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter10 = ap_const_logic_1))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
elsif ((((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (tmp_53_i_fu_256_p2 = ap_const_lv1_0)) or ((ap_enable_reg_pp0_iter9 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter10 = ap_const_logic_1)))) then
ap_NS_fsm <= ap_ST_fsm_state14;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_state14 =>
ap_NS_fsm <= ap_ST_fsm_state2;
when others =>
ap_NS_fsm <= "XXXX";
end case;
end process;
Range1_all_ones_6_fu_651_p2 <= (lD_1_fu_643_p3 or carry_1_fu_637_p2);
Range1_all_ones_7_fu_738_p2 <= (lD_2_fu_730_p3 or carry_2_fu_724_p2);
Range1_all_ones_fu_564_p2 <= (lD_fu_556_p3 or carry_fu_550_p2);
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state14 <= ap_CS_fsm(3);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_01001_assign_proc : process(p_src_data_stream_0_V_empty_n, p_src_data_stream_1_V_empty_n, p_src_data_stream_2_V_empty_n, p_dst_data_stream_0_V_full_n, p_dst_data_stream_1_V_full_n, p_dst_data_stream_2_V_full_n, ap_enable_reg_pp0_iter1, tmp_53_i_reg_783, ap_enable_reg_pp0_iter10, ap_reg_pp0_iter9_tmp_53_i_reg_783)
begin
ap_block_pp0_stage0_01001 <= (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((tmp_53_i_reg_783 = ap_const_lv1_1) and (p_src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((tmp_53_i_reg_783 = ap_const_lv1_1) and (p_src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((tmp_53_i_reg_783 = ap_const_lv1_1) and (p_src_data_stream_0_V_empty_n = ap_const_logic_0)))) or ((ap_enable_reg_pp0_iter10 = ap_const_logic_1) and (((p_dst_data_stream_2_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter9_tmp_53_i_reg_783 = ap_const_lv1_1)) or ((p_dst_data_stream_1_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter9_tmp_53_i_reg_783 = ap_const_lv1_1)) or ((p_dst_data_stream_0_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter9_tmp_53_i_reg_783 = ap_const_lv1_1)))));
end process;
ap_block_pp0_stage0_11001_assign_proc : process(p_src_data_stream_0_V_empty_n, p_src_data_stream_1_V_empty_n, p_src_data_stream_2_V_empty_n, p_dst_data_stream_0_V_full_n, p_dst_data_stream_1_V_full_n, p_dst_data_stream_2_V_full_n, ap_enable_reg_pp0_iter1, tmp_53_i_reg_783, ap_enable_reg_pp0_iter10, ap_reg_pp0_iter9_tmp_53_i_reg_783)
begin
ap_block_pp0_stage0_11001 <= (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((tmp_53_i_reg_783 = ap_const_lv1_1) and (p_src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((tmp_53_i_reg_783 = ap_const_lv1_1) and (p_src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((tmp_53_i_reg_783 = ap_const_lv1_1) and (p_src_data_stream_0_V_empty_n = ap_const_logic_0)))) or ((ap_enable_reg_pp0_iter10 = ap_const_logic_1) and (((p_dst_data_stream_2_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter9_tmp_53_i_reg_783 = ap_const_lv1_1)) or ((p_dst_data_stream_1_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter9_tmp_53_i_reg_783 = ap_const_lv1_1)) or ((p_dst_data_stream_0_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter9_tmp_53_i_reg_783 = ap_const_lv1_1)))));
end process;
ap_block_pp0_stage0_subdone_assign_proc : process(p_src_data_stream_0_V_empty_n, p_src_data_stream_1_V_empty_n, p_src_data_stream_2_V_empty_n, p_dst_data_stream_0_V_full_n, p_dst_data_stream_1_V_full_n, p_dst_data_stream_2_V_full_n, ap_enable_reg_pp0_iter1, tmp_53_i_reg_783, ap_enable_reg_pp0_iter10, ap_reg_pp0_iter9_tmp_53_i_reg_783)
begin
ap_block_pp0_stage0_subdone <= (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((tmp_53_i_reg_783 = ap_const_lv1_1) and (p_src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((tmp_53_i_reg_783 = ap_const_lv1_1) and (p_src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((tmp_53_i_reg_783 = ap_const_lv1_1) and (p_src_data_stream_0_V_empty_n = ap_const_logic_0)))) or ((ap_enable_reg_pp0_iter10 = ap_const_logic_1) and (((p_dst_data_stream_2_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter9_tmp_53_i_reg_783 = ap_const_lv1_1)) or ((p_dst_data_stream_1_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter9_tmp_53_i_reg_783 = ap_const_lv1_1)) or ((p_dst_data_stream_0_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter9_tmp_53_i_reg_783 = ap_const_lv1_1)))));
end process;
ap_block_state1_assign_proc : process(ap_start, ap_done_reg, p_src_rows_V_empty_n, p_src_cols_V_empty_n)
begin
ap_block_state1 <= ((ap_start = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
ap_block_state10_pp0_stage0_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state11_pp0_stage0_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state12_pp0_stage0_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state13_pp0_stage0_iter10_assign_proc : process(p_dst_data_stream_0_V_full_n, p_dst_data_stream_1_V_full_n, p_dst_data_stream_2_V_full_n, ap_reg_pp0_iter9_tmp_53_i_reg_783)
begin
ap_block_state13_pp0_stage0_iter10 <= (((p_dst_data_stream_2_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter9_tmp_53_i_reg_783 = ap_const_lv1_1)) or ((p_dst_data_stream_1_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter9_tmp_53_i_reg_783 = ap_const_lv1_1)) or ((p_dst_data_stream_0_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter9_tmp_53_i_reg_783 = ap_const_lv1_1)));
end process;
ap_block_state3_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage0_iter1_assign_proc : process(p_src_data_stream_0_V_empty_n, p_src_data_stream_1_V_empty_n, p_src_data_stream_2_V_empty_n, tmp_53_i_reg_783)
begin
ap_block_state4_pp0_stage0_iter1 <= (((tmp_53_i_reg_783 = ap_const_lv1_1) and (p_src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((tmp_53_i_reg_783 = ap_const_lv1_1) and (p_src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((tmp_53_i_reg_783 = ap_const_lv1_1) and (p_src_data_stream_0_V_empty_n = ap_const_logic_0)));
end process;
ap_block_state5_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage0_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp0_stage0_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_condition_pp0_exit_iter0_state3_assign_proc : process(tmp_53_i_fu_256_p2)
begin
if ((tmp_53_i_fu_256_p2 = ap_const_lv1_0)) then
ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_done_reg, tmp_i_fu_241_p2, ap_CS_fsm_state2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_241_p2 = ap_const_lv1_0))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter10, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9)
begin
if (((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter9 = ap_const_logic_0) and (ap_enable_reg_pp0_iter8 = ap_const_logic_0) and (ap_enable_reg_pp0_iter7 = ap_const_logic_0) and (ap_enable_reg_pp0_iter6 = ap_const_logic_0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_0) and (ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0) and (ap_enable_reg_pp0_iter10 = ap_const_logic_0))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(tmp_i_fu_241_p2, ap_CS_fsm_state2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_241_p2 = ap_const_lv1_0))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
carry_1_fu_637_p2 <= (tmp_16_fu_609_p3 and tmp_14_i_i113_i_fu_631_p2);
carry_2_fu_724_p2 <= (tmp_20_fu_696_p3 and tmp_14_i_i126_i_fu_718_p2);
carry_fu_550_p2 <= (tmp_14_i_i_i_fu_544_p2 and tmp_12_fu_522_p3);
f_V_cast_fu_408_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(f_V_reg_850),28));
f_V_fu_377_p2 <= std_logic_vector(unsigned(r_V_10_cast1_i_cast_fu_353_p1) - unsigned(tmp_55_cast_i_cast_fu_373_p1));
grp_fu_418_ce_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
grp_fu_418_ce <= ap_const_logic_1;
else
grp_fu_418_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_418_p1 <= grp_fu_418_p10(28 - 1 downto 0);
grp_fu_418_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(f_V_cast_fu_408_p1),47));
h_i_1_fu_434_p3 <=
h_i_fu_429_p2 when (tmp_58_i_fu_424_p2(0) = '1') else
ap_reg_pp0_iter5_tmp_s_reg_843;
h_i_fu_429_p2 <= std_logic_vector(signed(ap_const_lv5_1A) + signed(ap_reg_pp0_iter5_tmp_s_reg_843));
i_cast_i_cast_fu_237_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_i_reg_215),16));
i_fu_246_p2 <= std_logic_vector(unsigned(i_i_reg_215) + unsigned(ap_const_lv11_1));
j_cast_i_cast_fu_252_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_i_reg_226),16));
j_fu_261_p2 <= std_logic_vector(unsigned(j_i_reg_226) + unsigned(ap_const_lv11_1));
lD_1_fu_643_p3 <= p_Val2_11_fu_578_p6(27 downto 27);
lD_2_fu_730_p3 <= p_Val2_s_fu_665_p6(27 downto 27);
lD_fu_556_p3 <= p_Val2_7_fu_491_p6(27 downto 27);
p_Val2_12_fu_587_p4 <= p_Val2_11_fu_578_p6(26 downto 19);
p_Val2_13_fu_617_p2 <= std_logic_vector(unsigned(p_Val2_12_fu_587_p4) + unsigned(tmp_i_i109_i_fu_605_p1));
p_Val2_17_fu_674_p4 <= p_Val2_s_fu_665_p6(26 downto 19);
p_Val2_18_fu_704_p2 <= std_logic_vector(unsigned(p_Val2_17_fu_674_p4) + unsigned(tmp_i_i122_i_fu_692_p1));
p_Val2_1_i_fu_320_p2 <= std_logic_vector(unsigned(tmp_65_i_fu_312_p3) - unsigned(p_Val2_cast_i_fu_297_p1));
p_Val2_20_fu_570_p3 <=
ap_const_lv8_FF when (Range1_all_ones_fu_564_p2(0) = '1') else
p_Val2_9_fu_530_p2;
p_Val2_21_fu_657_p3 <=
ap_const_lv8_FF when (Range1_all_ones_6_fu_651_p2(0) = '1') else
p_Val2_13_fu_617_p2;
p_Val2_22_fu_744_p3 <=
ap_const_lv8_FF when (Range1_all_ones_7_fu_738_p2(0) = '1') else
p_Val2_18_fu_704_p2;
p_Val2_2_cast_i_fu_342_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_Val2_2_i_fu_337_p2),28));
p_Val2_2_i_fu_337_p2 <= std_logic_vector(unsigned(p_Val2_i_reg_821) + unsigned(tmp_66_cast_i_fu_333_p1));
p_Val2_5_fu_454_p2 <= std_logic_vector(unsigned(tmp_71_i_fu_447_p3) - unsigned(p_Val2_4_i_reg_883));
p_Val2_6_fu_476_p2 <= std_logic_vector(unsigned(tmp_76_i_fu_469_p3) + unsigned(p_Val2_4_i_reg_883));
p_Val2_8_fu_500_p4 <= p_Val2_7_fu_491_p6(26 downto 19);
p_Val2_9_fu_530_p2 <= std_logic_vector(unsigned(p_Val2_8_fu_500_p4) + unsigned(tmp_i_i_i_fu_518_p1));
p_Val2_cast_i_fu_297_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_Val2_i_reg_821),28));
p_Val2_i_fu_752_p0 <= p_Val2_i_fu_752_p00(19 - 1 downto 0);
p_Val2_i_fu_752_p00 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(r_V_4_fu_279_p4),27));
p_Val2_i_fu_752_p1 <= p_Val2_i_fu_752_p10(8 - 1 downto 0);
p_Val2_i_fu_752_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_27_reg_797),27));
p_dst_data_stream_0_V_blk_n_assign_proc : process(p_dst_data_stream_0_V_full_n, ap_block_pp0_stage0, ap_enable_reg_pp0_iter10, ap_reg_pp0_iter9_tmp_53_i_reg_783)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter10 = ap_const_logic_1) and (ap_reg_pp0_iter9_tmp_53_i_reg_783 = ap_const_lv1_1))) then
p_dst_data_stream_0_V_blk_n <= p_dst_data_stream_0_V_full_n;
else
p_dst_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_dst_data_stream_0_V_din <= p_Val2_20_reg_933;
p_dst_data_stream_0_V_write_assign_proc : process(ap_enable_reg_pp0_iter10, ap_reg_pp0_iter9_tmp_53_i_reg_783, ap_block_pp0_stage0_11001)
begin
if (((ap_enable_reg_pp0_iter10 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_reg_pp0_iter9_tmp_53_i_reg_783 = ap_const_lv1_1))) then
p_dst_data_stream_0_V_write <= ap_const_logic_1;
else
p_dst_data_stream_0_V_write <= ap_const_logic_0;
end if;
end process;
p_dst_data_stream_1_V_blk_n_assign_proc : process(p_dst_data_stream_1_V_full_n, ap_block_pp0_stage0, ap_enable_reg_pp0_iter10, ap_reg_pp0_iter9_tmp_53_i_reg_783)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter10 = ap_const_logic_1) and (ap_reg_pp0_iter9_tmp_53_i_reg_783 = ap_const_lv1_1))) then
p_dst_data_stream_1_V_blk_n <= p_dst_data_stream_1_V_full_n;
else
p_dst_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_dst_data_stream_1_V_din <= p_Val2_21_reg_938;
p_dst_data_stream_1_V_write_assign_proc : process(ap_enable_reg_pp0_iter10, ap_reg_pp0_iter9_tmp_53_i_reg_783, ap_block_pp0_stage0_11001)
begin
if (((ap_enable_reg_pp0_iter10 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_reg_pp0_iter9_tmp_53_i_reg_783 = ap_const_lv1_1))) then
p_dst_data_stream_1_V_write <= ap_const_logic_1;
else
p_dst_data_stream_1_V_write <= ap_const_logic_0;
end if;
end process;
p_dst_data_stream_2_V_blk_n_assign_proc : process(p_dst_data_stream_2_V_full_n, ap_block_pp0_stage0, ap_enable_reg_pp0_iter10, ap_reg_pp0_iter9_tmp_53_i_reg_783)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter10 = ap_const_logic_1) and (ap_reg_pp0_iter9_tmp_53_i_reg_783 = ap_const_lv1_1))) then
p_dst_data_stream_2_V_blk_n <= p_dst_data_stream_2_V_full_n;
else
p_dst_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_dst_data_stream_2_V_din <= p_Val2_22_reg_943;
p_dst_data_stream_2_V_write_assign_proc : process(ap_enable_reg_pp0_iter10, ap_reg_pp0_iter9_tmp_53_i_reg_783, ap_block_pp0_stage0_11001)
begin
if (((ap_enable_reg_pp0_iter10 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_reg_pp0_iter9_tmp_53_i_reg_783 = ap_const_lv1_1))) then
p_dst_data_stream_2_V_write <= ap_const_logic_1;
else
p_dst_data_stream_2_V_write <= ap_const_logic_0;
end if;
end process;
p_src_cols_V_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_src_cols_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_src_cols_V_blk_n <= p_src_cols_V_empty_n;
else
p_src_cols_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_src_cols_V_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_src_rows_V_empty_n, p_src_cols_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_src_cols_V_read <= ap_const_logic_1;
else
p_src_cols_V_read <= ap_const_logic_0;
end if;
end process;
p_src_data_stream_0_V_blk_n_assign_proc : process(p_src_data_stream_0_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, tmp_53_i_reg_783)
begin
if (((tmp_53_i_reg_783 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
p_src_data_stream_0_V_blk_n <= p_src_data_stream_0_V_empty_n;
else
p_src_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_src_data_stream_0_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_53_i_reg_783, ap_block_pp0_stage0_11001)
begin
if (((tmp_53_i_reg_783 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_src_data_stream_0_V_read <= ap_const_logic_1;
else
p_src_data_stream_0_V_read <= ap_const_logic_0;
end if;
end process;
p_src_data_stream_1_V_blk_n_assign_proc : process(p_src_data_stream_1_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, tmp_53_i_reg_783)
begin
if (((tmp_53_i_reg_783 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
p_src_data_stream_1_V_blk_n <= p_src_data_stream_1_V_empty_n;
else
p_src_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_src_data_stream_1_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_53_i_reg_783, ap_block_pp0_stage0_11001)
begin
if (((tmp_53_i_reg_783 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_src_data_stream_1_V_read <= ap_const_logic_1;
else
p_src_data_stream_1_V_read <= ap_const_logic_0;
end if;
end process;
p_src_data_stream_2_V_blk_n_assign_proc : process(p_src_data_stream_2_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, tmp_53_i_reg_783)
begin
if (((tmp_53_i_reg_783 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
p_src_data_stream_2_V_blk_n <= p_src_data_stream_2_V_empty_n;
else
p_src_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_src_data_stream_2_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_53_i_reg_783, ap_block_pp0_stage0_11001)
begin
if (((tmp_53_i_reg_783 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_src_data_stream_2_V_read <= ap_const_logic_1;
else
p_src_data_stream_2_V_read <= ap_const_logic_0;
end if;
end process;
p_src_rows_V_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_src_rows_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_src_rows_V_blk_n <= p_src_rows_V_empty_n;
else
p_src_rows_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_src_rows_V_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_src_rows_V_empty_n, p_src_cols_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_src_rows_V_read <= ap_const_logic_1;
else
p_src_rows_V_read <= ap_const_logic_0;
end if;
end process;
r_V_10_cast1_i_cast_fu_353_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(r_V_3_reg_827),25));
r_V_3_fu_758_p0 <= ap_const_lv24_4444(16 - 1 downto 0);
r_V_3_fu_758_p1 <= r_V_3_fu_758_p10(8 - 1 downto 0);
r_V_3_fu_758_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter2_tmp_26_reg_792),24));
r_V_4_fu_279_p4 <= ((tmp_28_reg_804 & tmp_28_reg_804) & ap_const_lv3_0);
r_V_fu_402_p2 <= std_logic_vector(unsigned(tmp_68_i_fu_395_p1) - unsigned(tmp_69_i_fu_398_p1));
sector_data_0_address0 <= tmp_79_i_fu_441_p1(3 - 1 downto 0);
sector_data_0_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter7)
begin
if (((ap_enable_reg_pp0_iter7 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
sector_data_0_ce0 <= ap_const_logic_1;
else
sector_data_0_ce0 <= ap_const_logic_0;
end if;
end process;
sector_data_1_address0 <= tmp_79_i_fu_441_p1(3 - 1 downto 0);
sector_data_1_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter7)
begin
if (((ap_enable_reg_pp0_iter7 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
sector_data_1_ce0 <= ap_const_logic_1;
else
sector_data_1_ce0 <= ap_const_logic_0;
end if;
end process;
sector_data_2_address0 <= tmp_79_i_fu_441_p1(3 - 1 downto 0);
sector_data_2_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter7)
begin
if (((ap_enable_reg_pp0_iter7 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
sector_data_2_ce0 <= ap_const_logic_1;
else
sector_data_2_ce0 <= ap_const_logic_0;
end if;
end process;
tab_0_V_fu_346_p3 <=
p_Val2_1_i_fu_320_p2 when (ap_reg_pp0_iter2_tmp_reg_811(0) = '1') else
p_Val2_2_cast_i_fu_342_p1;
tab_1_V_fu_390_p2 <= std_logic_vector(unsigned(tmp_67_i_fu_383_p3) - unsigned(tab_0_V_reg_833));
tmp_10_fu_275_p1 <= p_src_data_stream_1_V_dout(7 - 1 downto 0);
tmp_11_fu_510_p3 <= p_Val2_7_fu_491_p6(18 downto 18);
tmp_12_fu_522_p3 <= p_Val2_7_fu_491_p6(26 downto 26);
tmp_13_fu_536_p3 <= p_Val2_9_fu_530_p2(7 downto 7);
tmp_14_i_i113_i_fu_631_p2 <= (tmp_17_fu_623_p3 xor ap_const_lv1_1);
tmp_14_i_i126_i_fu_718_p2 <= (tmp_21_fu_710_p3 xor ap_const_lv1_1);
tmp_14_i_i_i_fu_544_p2 <= (tmp_13_fu_536_p3 xor ap_const_lv1_1);
tmp_15_fu_597_p3 <= p_Val2_11_fu_578_p6(18 downto 18);
tmp_16_fu_609_p3 <= p_Val2_11_fu_578_p6(26 downto 26);
tmp_17_fu_623_p3 <= p_Val2_13_fu_617_p2(7 downto 7);
tmp_19_fu_684_p3 <= p_Val2_s_fu_665_p6(18 downto 18);
tmp_20_fu_696_p3 <= p_Val2_s_fu_665_p6(26 downto 26);
tmp_21_fu_710_p3 <= p_Val2_18_fu_704_p2(7 downto 7);
tmp_53_i_fu_256_p2 <= "1" when (unsigned(j_cast_i_cast_fu_252_p1) < unsigned(p_src_cols_V_read_reg_764)) else "0";
tmp_55_cast_i_cast_fu_373_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_55_i_fu_365_p3),25));
tmp_55_i_fu_365_p3 <= (tmp_s_fu_356_p4 & ap_const_lv19_0);
tmp_58_i_fu_424_p2 <= "1" when (unsigned(ap_reg_pp0_iter5_tmp_s_reg_843) > unsigned(ap_const_lv5_5)) else "0";
tmp_61_i_fu_300_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter2_tmp_28_reg_804),9));
tmp_62_i_fu_303_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter2_tmp_27_reg_797),9));
tmp_63_i_fu_306_p2 <= std_logic_vector(unsigned(tmp_62_i_fu_303_p1) + unsigned(tmp_61_i_fu_300_p1));
tmp_65_i_fu_312_p3 <= (tmp_63_i_fu_306_p2 & ap_const_lv19_0);
tmp_66_cast_i_fu_333_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_66_i_fu_326_p3),27));
tmp_66_i_fu_326_p3 <= (ap_reg_pp0_iter2_tmp_10_reg_816 & ap_const_lv19_0);
tmp_67_i_fu_383_p3 <= (ap_reg_pp0_iter3_tmp_27_reg_797 & ap_const_lv20_0);
tmp_68_i_fu_395_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tab_0_V_reg_833),29));
tmp_69_i_fu_398_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tab_1_V_fu_390_p2),29));
tmp_71_i_fu_447_p3 <= (ap_reg_pp0_iter7_tab_0_V_reg_833 & ap_const_lv19_0);
tmp_76_i_fu_469_p3 <= (ap_reg_pp0_iter7_tab_1_V_reg_855 & ap_const_lv19_0);
tmp_79_i_fu_441_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(h_i_1_reg_878),64));
tmp_i_fu_241_p2 <= "1" when (unsigned(i_cast_i_cast_fu_237_p1) < unsigned(p_src_rows_V_read_reg_769)) else "0";
tmp_i_i109_i_fu_605_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_15_fu_597_p3),8));
tmp_i_i122_i_fu_692_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_19_fu_684_p3),8));
tmp_i_i_i_fu_518_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_fu_510_p3),8));
tmp_s_fu_356_p4 <= r_V_3_reg_827(23 downto 19);
end behav;
|
mit
|
359416aea09b33ea0b05b6f49f5e4a5c
| 0.598779 | 2.598659 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodDigitizerController/src/GainOffsetCalib.vhd
| 1 | 12,019 |
-------------------------------------------------------------------------------
--
-- File: GainOffsetCalib.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module applies the gain and offset calibration to the raw data samples
-- received from the DataPath module.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity GainOffsetCalib is
Generic (
-- ADC/DAC number of bits
kWidth : integer range 10 to 16 := 14;
-- ADC/DAC dynamic/static calibration
kExtCalibEn : boolean := true;
-- When asserted, kInvert determines the sign inversion of the data samples
-- received. Used to compensate the physical inversion of some of the
-- channels on the PCB at the ADC/DAC input/output on the Zmod.
kInvert : boolean := false;
-- Low gain multiplicative (gain) compensation coefficient parameter
kLgMultCoefStatic : std_logic_vector (17 downto 0) := "010000000000000000";
-- Low gain additive (offset) compensation coefficient parameter
kLgAddCoefStatic : std_logic_vector (17 downto 0) := "000000000000000000";
-- High gain multiplicative (gain) compensation coefficient parameter
kHgMultCoefStatic : std_logic_vector (17 downto 0) := "010000000000000000";
-- High gain additive (offset) compensation coefficient parameter
kHgAddCoefStatic : std_logic_vector (17 downto 0) := "000000000000000000"
);
Port (
-- Sampling clock
SamplingClk : in STD_LOGIC;
-- Reset signal asynchronously asserted and synchronously
-- de-asserted (in the SamplingClk domain)
acRst_n : in STD_LOGIC;
-- cTestMode is used to bypass the calibration block. When this signal
-- is asserted, raw samples are provided on the data interface
cTestMode : in STD_LOGIC;
-- If at the start of the acquisition, this module puts on cCalibDataOut output signal the first acquired and calibrated samples,
-- together with cDataCalibValid = '1', but doDataAxisTready is not asserted, in the next clock cycle the value on cCalibDataOut will change,
-- since it will take the values of the next calibrated samples. This violates the AXI Stream interface specification.
-- This signal was added to prevent that. In a top level this signal should be connected to an AXI Stream Slave TREADY signal.
cDataAcceptanceReady : in STD_LOGIC;
-- Low gain gain compensation coefficient external port
cExtLgMultCoef : in std_logic_vector (17 downto 0);
-- Low gain offset compensation coefficient external port
cExtLgAddCoef : in std_logic_vector (17 downto 0);
-- High gain gain compensation coefficient external port
cExtHgMultCoef : in std_logic_vector (17 downto 0);
-- High gain offset compensation coefficient external port
cExtHgAddCoef : in std_logic_vector (17 downto 0);
-- Gain Relay State (1 -> High Gain; 0 -> Low Gain)
cGainState : in std_logic;
-- Raw data input
cDataRaw : in STD_LOGIC_VECTOR (kWidth-1 downto 0);
-- Raw data valid signal
cDataInValid : in STD_LOGIC;
-- Calibrated output data
cCalibDataOut : out STD_LOGIC_VECTOR (15 downto 0);
-- Output data valid signal
cDataCalibValid : out STD_LOGIC
);
end GainOffsetCalib;
architecture Behavioral of GainOffsetCalib is
signal cDataRaw18bSigned : signed(17 downto 0);
signal cDataRaw18b : std_logic_vector(17 downto 0);
signal cCalibMult : signed(35 downto 0);
signal cCalibAdd : signed(35 downto 0);
signal cCoefAdd : std_logic_vector(35 downto 0);
signal cCoefAddSigned : signed(35 downto 0);
signal cCoefMult : std_logic_vector(17 downto 0);
signal cCoefMultSigned : signed(17 downto 0);
signal cCoefMultLg, cCoefMultHg : std_logic_vector (17 downto 0);
signal cCoefAddLg, cCoefAddHg : std_logic_vector (17 downto 0);
signal cDataInValidR : STD_LOGIC;
signal cDataCalibValidLoc : std_logic;
signal cCalibDataOutLoc : std_logic_vector(15 downto 0);
signal cFirstWordAccepted : std_logic;
constant kDummy : std_logic_vector (17-kWidth downto 0) := (others => '0');
begin
--Channel1 low gain gain compensation coefficient (output port or IP parameter).
cCoefMultLg <= cExtLgMultCoef when kExtCalibEn = true else kLgMultCoefStatic;
--Channel1 high gain gain compensation coefficient (output port or IP parameter).
cCoefMultHg <= cExtHgMultCoef when kExtCalibEn = true else kHgMultCoefStatic;
--Channel1 low gain offset compensation coefficient (output port or IP parameter).
cCoefAddLg <= cExtLgAddCoef when kExtCalibEn = true else kLgAddCoefStatic;
--Channel1 high gain offset compensation coefficient (output port or IP parameter).
cCoefAddHg <= cExtHgAddCoef when kExtCalibEn = true else kHgAddCoefStatic;
-- Numerical representation of the calibration module's signals:
-- The first operation of the calibration block is represented by the multiplication
-- of the raw data input by the multiplicative coefficient. The multiplier's
-- operands are represented as follows:
-- 1. The input raw data is considered to be a fractional number < 1, consisting
-- of a sign bit and 17 fractional bits.
-- 2. The multiplicative coefficient, which can be slightly higher or slightly
-- lower than 1, is also represented on 18 bits, i.e. 1 sign bit, 1 integer bit,
-- and 16 fractional bis.
-- The result of the multiplication is a 36 bit number, consisting of a sign bit,
-- 2 integer bits and 33 fractional bits. Thus, to apply the additive coefficient,
-- (which is interpreted by the module as a 18 bit fractional number - 1 sign bit
-- + 17 fractional bits)the additive coefficient is also converted to this format
-- (sign extended by 2 bits and padded with 16 fractional bits).
-- Determine the additive coefficient based on the channel's gain relay state
-- and convert it to a 36 bit representation (as explained above).
ProcAddCoef : process (SamplingClk, acRst_n)
begin
if (acRst_n = '0') then
cCoefAdd <= (others => '0');
elsif (rising_edge(SamplingClk)) then
if (cGainState = '0') then --Low Gain
cCoefAdd <= cCoefAddLg(17) & cCoefAddLg(17) & cCoefAddLg & x"0000";
else --High Gain
cCoefAdd <= cCoefAddHg(17) & cCoefAddHg(17) & cCoefAddHg & x"0000";
end if;
end if;
end process;
-- Determine the multiplicative coefficient based on the channel's gain relay state.
ProcMultCoef : process (SamplingClk, acRst_n)
begin
if (acRst_n = '0') then
cCoefMult <= "010000000000000000";
elsif (rising_edge(SamplingClk)) then
if (cGainState = '0') then
cCoefMult <= cCoefMultLg;
else
cCoefMult <= cCoefMultHg;
end if;
end if;
end process;
cDataRaw18b <= cDataRaw & kDummy;
-- Invert raw data input if the analog channel is inverted at the
-- ADC/DAC input/output. Inversion of the minimum negative value (-2^kWidth)
-- needs to be done explicitly.
ProcInvert : process (cDataRaw18b)
begin
if (kInvert = false) then
if (cDataRaw18b = "100000000000000000") then
-- For the inverted channel, because the inversion is done at the FPGA
-- level, the minimum negative value is -2^kWidth+1. For symmetry
-- reasons the non inverted channel also limits the minimum negative value
-- at -2^kWidth+1.
cDataRaw18bSigned <= "100000000000000001";
else
cDataRaw18bSigned <= signed(cDataRaw18b);
end if;
else
if (cDataRaw18b = "100000000000000000") then
cDataRaw18bSigned <= "011111111111111111";
else
cDataRaw18bSigned <= - signed (cDataRaw18b);
end if;
end if;
end process;
cCoefMultSigned <= signed (cCoefMult);
cCoefAddSigned <= signed (cCoefAdd);
-- Apply the multiplicative coefficient. Register multiplication result.
ProcRegMultResult : process (SamplingClk, acRst_n)
begin
if (acRst_n = '0') then
cCalibMult <= (others => '0');
cDataInValidR <= '0';
elsif (rising_edge(SamplingClk)) then
cCalibMult <= cDataRaw18bSigned * cCoefMultSigned;
--Data out valid flag must be synchronized with its corresponding sample.
cDataInValidR <= cDataInValid;
end if;
end process;
-- Apply additive coefficient.
cCalibAdd <= cCalibMult + cCoefAddSigned;
-- Register calibration result; the calibration output is saturated at
-- 2^kWidth - 1 for positive values or -2^kWidth for negative values;
-- the calibration process is bypassed if cTestMode = '1'.
-- If at the start of the acquisition, this module puts on cCalibDataOut output signal the first acquired and calibrated samples,
-- together with cDataCalibValid = '1', but doDataAxisTready is not asserted, in the next clock cycle the value on cCalibDataOut will change,
-- since it will take the values of the next calibrated samples. This violates the AXI Stream interface specification.
ProcCalibDataAndValid : process (SamplingClk, acRst_n, cDataAcceptanceReady)
begin
if (acRst_n = '0') then
cCalibDataOut <= (others => '0');
cDataCalibValidLoc <= '0';
cFirstWordAccepted <= '0';
elsif (rising_edge(SamplingClk)) then
cDataCalibValidLoc <= cDataInValidR;
if (cDataCalibValidLoc = '1' and cDataAcceptanceReady = '1') then
cFirstWordAccepted <= '1';
end if;
if(cFirstWordAccepted = '0' or (cDataCalibValidLoc = '1' and cDataAcceptanceReady = '1')) then
cCalibDataOut <= cCalibDataOutLoc;
end if;
end if;
end process;
cDataCalibValid <= cDataCalibValidLoc;
cCalibDataOutLoc <= cDataRaw18b(17 downto 2) when cTestMode = '1' else
x"8000" when ((cCalibAdd(35) = '1') and (cCalibAdd(34 downto 33) /= "11")) else
x"7FFF" when ((cCalibAdd(35) = '0') and (cCalibAdd(34 downto 33) /= "00")) else
(std_logic_vector(cCalibAdd(33 downto 18)));
end Behavioral;
|
mit
|
984e872f57051e64be53fea4066364cf
| 0.691322 | 4.626251 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodDigitizerController/tb/tb_TestTop.vhd
| 1 | 24,803 |
-------------------------------------------------------------------------------
--
-- File: tb_TestTop.vhd
-- Author: Tudor Gherman, Robert Bocos
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Top level test bench. This test bench does not extensively test all modules
-- of the ZmodScopeController. Such tests are carried out at component level.
-- A simulation model is provided for the ADC SPI interface to test
-- configuration registers read/write commands.
-- A command queue is loaded into an external FIFO to exercise the IP's SPI
-- indirect access port.
-- A ramp signal is used as stimulus for the data bus. The calibrated samples
-- output by the IP are compared against the expected values in order to test
-- the calibration functionality.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.PkgZmodDigitizer.all;
library UNISIM;
use UNISIM.VComponents.all;
entity tb_TestTop is
Generic (
-- Parameter identifying the Zmod:
-- 6 -> Zmod Scope 1410 - 125 (AD9648)
kZmodID : integer range 6 to 6 := 6;
-- Sampling Clock Period of type "time" in ns
kADC_SamplingClkPeriod : time := 8.138ns;
-- ADC Clock divider ratio (Register 0x0B of AD96xx and AD92xx)
kADC_ClkDiv : integer range 1 to 1 := 1;
-- ADC dynamic/static calibration
kExtCalibEn : boolean := true;
-- Enable/Disable SPI Inirect Access Port
kExtCmdInterfaceEn : boolean := true;
-- Channel1 high gain multiplicative (gain) compensation coefficient parameter
kCh1HgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101010111000";
-- Channel1 high gain additive (offset) compensation coefficient parameter
kCh1HgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101111011000";
-- Channel2 high gain multiplicative (gain) compensation coefficient parameter
kCh2HgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101010111000";
-- Channel2 high gain additive (offset) compensation coefficient parameter
kCh2HgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101111011000";
-- Clock Generator I2C config address (0x67, 0x68(Default), 0x69)
kCDCEI2C_Addr : std_logic_vector(7 downto 0) := x"CE";
--Parameter to shorten the Clock generator configuration time over I2C
kCDCE_SimulationConfig : boolean := true;
-- Clock Generator I2C shortened configuration number of commands to send over I2C for simulation
kCDCE_SimulationCmdTotal : integer range 0 to kCDCE_RegNrZeroBased := 2;
-- Parameter identifying the CDCE output frequency with SECREF(XTAL) as reference frequency:
-- 0 -> 122.88MHz
-- 1 -> 30MHz
-- 2 -> 40MHz
-- 3 -> 50MHz
-- 4 -> 60MHz
-- 5 -> 80MHz
-- 6 -> 100MHz
-- 7 -> 120MHz
kCDCEFreqSel : integer range 0 to CDCE_I2C_Cmds'length := 0
);
end tb_TestTop;
architecture Behavioral of tb_TestTop is
constant kNumClockCycles : integer := 5000000;
-- ADC number of bits.
constant kADC_Width : integer := SelADC_Width(kZmodID);
signal SysClk100: std_logic := '1';
signal ADC_SamplingClk: std_logic := '1';
signal CDCE_InClk: std_logic := '1';
signal DcoClkOut : std_logic := '1';
signal aRst_n, aRst: std_logic;
signal sInitDoneADC: std_logic;
signal sConfigError: std_logic;
signal doDataAxisTvalid: STD_LOGIC;
signal doDataAxisTready: STD_LOGIC;
signal doDataAxisTdata: STD_LOGIC_VECTOR(31 DOWNTO 0);
signal doExtCh1HgMultCoef: std_logic_vector (17 downto 0);
signal doExtCh1HgAddCoef: std_logic_vector (17 downto 0);
signal doExtCh2HgAddCoef: std_logic_vector (17 downto 0);
signal doExtCh2HgMultCoef: std_logic_vector (17 downto 0);
signal sTestMode: std_logic;
signal doSyncIn: std_logic_vector(kADC_ClkDiv-1 downto 0);
signal sCmdTxAxisTvalid: STD_LOGIC;
signal sCmdTxAxisTready: STD_LOGIC;
signal sCmdTxAxisTdata: STD_LOGIC_VECTOR(31 DOWNTO 0);
signal sCmdRxAxisTvalid: STD_LOGIC;
signal sCmdRxAxisTready: STD_LOGIC;
signal sCmdRxAxisTdata: STD_LOGIC_VECTOR(31 DOWNTO 0);
signal ZmodAdcClkIn_p: std_logic;
signal ZmodAdcClkIn_n: std_logic;
signal aZmodSync: std_logic;
signal ZmodDcoClk, ZmodDcoClkDly: std_logic := '1';
signal diZmodADC_Data: std_logic_vector(kADC_Width-1 downto 0);
signal sZmodADC_SDIO: std_logic;
signal sZmodADC_CS: std_logic;
signal sZmodADC_Sclk: std_logic;
signal s_scl_i : std_logic;
signal s_scl_o : std_logic;
signal s_scl_t : std_logic;
signal s_sda_i : std_logic;
signal s_sda_o : std_logic;
signal s_sda_t : std_logic;
signal t_scl_io : std_logic;
signal t_sda_io : std_logic;
signal e_scl_i : std_logic;
signal e_scl_o : std_logic;
signal e_scl_t : std_logic;
signal e_sda_i : std_logic;
signal e_sda_o : std_logic;
signal e_sda_t : std_logic;
signal sZmodDcoPLL_Lock : std_logic;
signal aCG_PLL_Lock : std_logic := '1';
signal sInitDoneClockGen : std_logic;
signal sPLL_LockClockGen : std_logic;
signal REFSEL : std_logic;
signal HW_SW_CTRL : std_logic;
signal PDN : std_logic;
signal diZmodADC_DataCnt : unsigned(kADC_Width-1 downto 0);
signal diDataGenCntEn, diDataGenRst_n : std_logic;
signal doChA_DataPathTest, doChB_DataPathTest : std_logic_vector (kADC_Width-1 downto 0);
signal doChannel1_Test, doChannel2_Test : std_logic_vector(kADC_Width-1 downto 0);
signal doCh1OutInt, doCh2OutInt : integer;
signal doCh1TestInt, doCh2TestInt : integer;
signal doCh1Diff, doCh2Diff : integer;
signal aEnOverflowTest : std_logic;
signal sEnableAcquisition : std_logic;
constant kSysClkPeriod : time := 10ns; -- System Clock Period
--constant kADC_SamplingClkPeriod : time := 8.138ns;
constant kInitDoneLatency : time := kSysClkPeriod;
-- 2 stages SyncAsync module latency for crossings in SysClk100 domain
constant kSyncAsyncSysLatency: time := kSysClkPeriod*2;
-- Handshake data module latency when crossing from SysClk100 to ADC_samplingClk domain.
constant kHandshakeSys2ADC_Latency: time := kSysClkPeriod+4*kADC_SamplingClkPeriod;
-- The latency with which cDataAxisTvalid is de-asserted after a relay state modification
-- is requested.
-- The sInitDoneRelay signal is pushed through a HandshakeData
-- synchronization module and it will take 1 extra ADC_samplingClk cycle for the
-- FIFO reset to be generated.
-- The ADC_Calibration module adds a latency of extra 3 ADC_SamplingClk cycles
-- The valid signal should be de-asserted in HandshakeDataLatency +
-- + 3 ADC_SamplingClk cycles + 1 ADC_SamplingClk cycle (wait for valid de-assert after FIFO reset).
constant kAxisValidLatency : time := kHandshakeSys2ADC_Latency + 4*kADC_SamplingClkPeriod;
-- Synchronization FIFO depth
constant kSyncFIFO_Depth : integer := 16;
-- Time required for sDataOverflow to assert after cDataAxisTready is de-asserted:
-- If the FIFO is empty and rd_en is de-asserted it will take kSyncFIFO_Depth write clock cycles
-- to fill the FIFO. 1 extra clock cycle will be required by the FIFO to assert the overflow
-- signal, 1 clock cycle will be added by the ProcDataOverflow synchronous process and a maximum
-- time interval equal to kSyncAsyncSysClkLatency is added to pass the dDataOverflow into the
-- SysClk100 domain. This assessment is based on the presumption that the FIFO wr_en signal is
-- asserted for longer that the FIFO latency before the rd_en signal is de-asserted.
constant kOverflowLatency: time := kSyncAsyncSysLatency + kSyncFIFO_Depth * kADC_SamplingClkPeriod + 2 * kADC_SamplingClkPeriod;
-- Calibration constants used to test the dynamic calibration behavior
constant kCh1HgMultCoefDynamic : std_logic_vector (17 downto 0) := "010001101000010001";
constant kCh1HgAddCoefDynamic : std_logic_vector (17 downto 0) := "111111101110111000";
constant kCh2HgMultCoefDynamic : std_logic_vector (17 downto 0) := "010001011010101111";
constant kCh2HgAddCoefDynamic : std_logic_vector (17 downto 0) := "000000001000000111";
-- Adding padding (i.e. 2 bits on the most significant positions) to the static
-- calibration constants.
-- The padding is necessary only to be able to enter hexadecimal calibration constants
-- from the GUI.
-- Channel1 high gain multiplicative (gain) compensation coefficient parameter
constant kCh1HgMultCoefStaticPad : std_logic_vector(19 downto 0) :=
"00"&kCh1HgMultCoefStatic;
-- Channel1 high gain additive (offset) compensation coefficient parameter
constant kCh1HgAddCoefStaticPad : std_logic_vector(19 downto 0) :=
"00"&kCh1HgAddCoefStatic;
-- Channel2 high gain multiplicative (gain) compensation coefficient parameter
constant kCh2HgMultCoefStaticPad : std_logic_vector(19 downto 0) :=
"00"&kCh2HgMultCoefStatic;
-- Channel2 high gain additive (offset) compensation coefficient parameter
constant kCh2HgAddCoefStaticPad : std_logic_vector(19 downto 0) :=
"00"&kCh2HgAddCoefStatic;
constant kSamplingPeriod : integer := integer(DCO_ClockPeriod(kCDCEFreqSel));
constant kSamplingPeriodReal : real := (real(kSamplingPeriod)*0.001);
begin
------------------------------------------------------------------------------------------
--Top level component instantiation
------------------------------------------------------------------------------------------
InstZmodDigitizer_Cotroller: entity work.ZmodDigitizerController
Generic Map(
kZmodID => kZmodID,
kADC_ClkDiv => kADC_ClkDiv,
kADC_Width => kADC_Width,
kExtCalibEn => kExtCalibEn,
kExtCmdInterfaceEn => kExtCmdInterfaceEn,
kCh1HgMultCoefStatic => kCh1HgMultCoefStaticPad,
kCh1HgAddCoefStatic => kCh1HgAddCoefStaticPad,
kCh2HgMultCoefStatic => kCh2HgMultCoefStaticPad,
kCh2HgAddCoefStatic => kCh2HgAddCoefStaticPad,
kCGI2C_Addr => kCDCEI2C_Addr,
kCG_SimulationConfig => kCDCE_SimulationConfig,
kCG_SimulationCmdTotal => kCDCE_SimulationCmdTotal,
kCDCEFreqSel => kCDCEFreqSel
)
Port Map(
SysClk100 => SysClk100,
ClockGenPriRefClk => CDCE_InClk,
aRst_n => aRst_n,
sInitDoneADC => sInitDoneADC,
sConfigError => sConfigError,
sEnableAcquisition => sEnableAcquisition,
doDataAxisTvalid => doDataAxisTvalid,
doDataAxisTready => doDataAxisTready,
doDataAxisTdata => doDataAxisTdata,
doExtCh1HgMultCoef => doExtCh1HgMultCoef,
doExtCh1HgAddCoef => doExtCh1HgAddCoef,
doExtCh2HgMultCoef => doExtCh2HgMultCoef,
doExtCh2HgAddCoef => doExtCh2HgAddCoef,
sTestMode => sTestMode,
sCmdTxAxisTvalid => sCmdTxAxisTvalid,
sCmdTxAxisTready => sCmdTxAxisTready,
sCmdTxAxisTdata => sCmdTxAxisTdata,
sCmdRxAxisTvalid => sCmdRxAxisTvalid,
sCmdRxAxisTready => sCmdRxAxisTready,
sCmdRxAxisTdata => sCmdRxAxisTdata,
CG_InputClk_p => ZmodAdcClkIn_p,
CG_InputClk_n => ZmodAdcClkIn_n,
aZmodSync => aZmodSync,
DcoClkIn => ZmodDcoClk,
ZmodDcoClkOut => DcoClkOut,
sZmodDcoPLL_Lock => sZmodDcoPLL_Lock,
diZmodADC_Data => diZmodADC_Data,
sZmodADC_SDIO => sZmodADC_SDIO,
sZmodADC_CS => sZmodADC_CS,
sZmodADC_Sclk => sZmodADC_Sclk,
aCG_PLL_Lock => aCG_PLL_Lock,
sInitDoneClockGen => sInitDoneClockGen,
sPLL_LockClockGen => sPLL_LockClockGen,
aREFSEL => REFSEL,
aHW_SW_CTRL => HW_SW_CTRL,
sPDNout_n => PDN,
----------------------------------------------------------------------------------
-- IIC bus signals
----------------------------------------------------------------------------------
s_scl_i => s_scl_i, -- IIC Serial Clock Input from 3-state buffer (required)
s_scl_o => s_scl_o, -- IIC Serial Clock Output to 3-state buffer (required)
s_scl_t => s_scl_t, -- IIC Serial Clock Output Enable to 3-state buffer (required)
s_sda_i => s_sda_i, -- IIC Serial Data Input from 3-state buffer (required)
s_sda_o => s_sda_o, -- IIC Serial Data Output to 3-state buffer (required)
s_sda_t => s_sda_t -- IIC Serial Data Output Enable to 3-state buffer (required)
);
CDCE_IIC_scl_iobuf: component IOBUF
port map (
I => s_scl_o,
IO => t_scl_io,
O => s_scl_i,
T => s_scl_t
);
CDCE_IIC_sda_iobuf: component IOBUF
port map (
I => s_sda_o,
IO => t_sda_io,
O => s_sda_i,
T => s_sda_t
);
TWISlave_IIC_scl_iobuf: component IOBUF
port map (
I => e_scl_o,
IO => t_scl_io,
O => e_scl_i,
T => e_scl_t
);
TWISlave_IIC_sda_iobuf: component IOBUF
port map (
I => e_sda_o,
IO => t_sda_io,
O => e_sda_i,
T => e_sda_t
);
SlaveController: entity work.ClockGen_I2C_DataCheck
generic map (
kSampleClkFreqInMHz => 100,
kSlaveAddress => kCDCEI2C_Addr(7 downto 1),
kFreqSel => kCDCEFreqSel
)
port map (
SampleClk => SysClk100,
SRST => aRst,
-- two-wire interface
aSDA_I => e_sda_i,
aSDA_O => e_sda_o,
aSDA_T => e_sda_t,
aSCL_I => e_scl_i,
aSCL_O => e_scl_o,
aSCL_T => e_scl_t
);
--Emulate Pull-Up in Simulation
t_scl_io <= 'H';
t_sda_io <= 'H';
------------------------------------------------------------------------------------------
-- SPI test related modules instantiation
------------------------------------------------------------------------------------------
InstAD96xx_92xx: entity work.AD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kDataWidth => kSPI_DataWidth,
kCommandWidth => kSPI_CommandWidth
)
Port Map(
SysClk100 => SysClk100,
asRst_n => aRst_n,
InsertError => '0',
sSPI_Clk => sZmodADC_Sclk,
sSDIO => sZmodADC_SDIO,
sCS => sZmodADC_CS
);
TestCmdFIFO: entity work.SPI_IAP_TestModule
Generic Map(
kZmodID => kZmodID
)
Port Map(
SysClk100 => SysClk100,
asRst_n => aRst_n,
sInitDoneADC => sInitDoneADC,
sCmdTxAxisTvalid => sCmdTxAxisTvalid,
sCmdTxAxisTready => sCmdTxAxisTready,
sCmdTxAxisTdata => sCmdTxAxisTdata,
sCmdRxAxisTvalid => sCmdRxAxisTvalid,
sCmdRxAxisTready => sCmdRxAxisTready,
sCmdRxAxisTdata => sCmdRxAxisTdata
);
------------------------------------------------------------------------------------------
-- Data path & calibration test related modules instantiation
------------------------------------------------------------------------------------------
InstDataPathDlyCh1 : entity work.DataPathLatency
Generic Map (
kNumFIFO_Stages => 0,
kDataWidth => kADC_Width
)
Port Map(
ZmodDcoClk => DcoClkOut,
ZmodDcoClkDly => ZmodDcoClkDly,
doDataIn => diZmodADC_Data,
doChA_DataOut => doChA_DataPathTest,
doChB_DataOut => doChB_DataPathTest);
InstCalibDataRefCh1 : entity work.CalibDataReference
Generic Map (
kWidth => kADC_Width,
kExtCalibEn => kExtCalibEn,
kLgMultCoefStatic => (others => '0'),
kLgAddCoefStatic => (others => '0'),
kHgMultCoefStatic => kCh1HgMultCoefStatic,
kHgAddCoefStatic => kCh1HgAddCoefStatic,
kInvert => true,
kLatency => 2,
kTestLatency => 1
)
Port Map(
SamplingClk => DcoClkOut,
cTestMode => sTestMode, -- sTestMode is constant in the current test bench
cChIn => doChA_DataPathTest,
cChOut => doChannel1_Test,
cExtLgMultCoef => (others => '0'),
cExtLgAddCoef => (others => '0'),
cExtHgMultCoef => doExtCh1HgMultCoef,
cExtHgAddCoef => doExtCh1HgAddCoef,
cGainState => '1' --Force High Gain
);
InstCalibDataRefCh2 : entity work.CalibDataReference
Generic Map (
kWidth => kADC_Width,
kExtCalibEn => kExtCalibEn,
kLgMultCoefStatic => (others => '0'),
kLgAddCoefStatic => (others => '0'),
kHgMultCoefStatic => kCh2HgMultCoefStatic,
kHgAddCoefStatic => kCh2HgAddCoefStatic,
kInvert => false,
kLatency => 2,
kTestLatency => 1
)
Port Map(
SamplingClk => DcoClkOut,
cTestMode => sTestMode, -- sTestMode is constant in the current test bench
cChIn => doChB_DataPathTest,
cChOut => doChannel2_Test,
cExtLgMultCoef => (others => '0'),
cExtLgAddCoef => (others => '0'),
cExtHgMultCoef => doExtCh2HgMultCoef,
cExtHgAddCoef => doExtCh2HgAddCoef,
cGainState => '1' --Force High Gain
);
doCh1OutInt <= to_integer(signed(doDataAxisTdata(31 downto 32-kADC_Width)));
doCh2OutInt <= to_integer(signed(doDataAxisTdata(15 downto 16-kADC_Width)));
doCh1TestInt <= to_integer(signed(doChannel1_Test));
doCh2TestInt <= to_integer(signed(doChannel2_Test));
doCh1Diff <= doCh1OutInt - doCh1TestInt;
doCh2Diff <= doCh2OutInt - doCh2TestInt;
------------------------------------------------------------------------------------------
-- Clock generation
------------------------------------------------------------------------------------------
ProcSystmClock: process
begin
for i in 0 to kNumClockCycles loop
wait for kSysClkPeriod/2;
SysClk100 <= not SysClk100;
wait for kSysClkPeriod/2;
SysClk100 <= not SysClk100;
end loop;
wait;
end process;
ProcSamplingClk: process
begin
for i in 0 to kNumClockCycles loop
wait for kADC_SamplingClkPeriod/2;
ADC_SamplingClk <= not ADC_SamplingClk;
wait for kADC_SamplingClkPeriod/2;
ADC_SamplingClk <= not ADC_SamplingClk;
end loop;
wait;
end process;
ProcCDCE_InClk: process
begin
for i in 0 to (kNumClockCycles*kADC_ClkDiv) loop
wait for kADC_SamplingClkPeriod/(2*kADC_ClkDiv);
CDCE_InClk <= not CDCE_InClk;
wait for kADC_SamplingClkPeriod/(2*kADC_ClkDiv);
CDCE_InClk <= not CDCE_InClk;
end loop;
wait;
end process;
ProcDcoClk: process
begin
wait for kTdcoMax;
for i in 0 to kNumClockCycles loop
wait for kADC_SamplingClkPeriod/2;
ZmodDcoClk <= not ZmodDcoClk;
wait for kADC_SamplingClkPeriod/2;
ZmodDcoClk <= not ZmodDcoClk;
end loop;
wait;
end process;
ZmodDcoClkDly <= ZmodDcoClk after
(IDDR_ClockPhase(kSamplingPeriodReal)/360.0)*kADC_SamplingClkPeriod;
------------------------------------------------------------------------------------------
-- Stimuli generation
------------------------------------------------------------------------------------------
-- A ramp signal is used as stimuli for the ADC data bus
ProcDataGen: process (ZmodDcoClk)
begin
if ((aRst_n = '0') or (diDataGenRst_n = '0')) then
diZmodADC_DataCnt <= (others => '0');
elsif (rising_edge(ZmodDcoClk) or falling_edge(ZmodDcoClk)) then
if (diDataGenCntEn = '1') then
diZmodADC_DataCnt <= diZmodADC_DataCnt + 1;
end if;
end if;
end process;
diZmodADC_Data <= std_logic_vector(diZmodADC_DataCnt);
aRst <= not aRst_n;
-- Stimuli generated in the SysClk100 domain
ProcSysClkDomainStimuli: process
begin
-- Assert reset for 10 clock cycles (this covers the minimum
-- hold time for the reset signal)
aRst_n <= '0';
aEnOverflowTest <= '0';
sEnableAcquisition <= '0';
sTestMode <= '0';
wait for 10 * kSysClkPeriod;
wait until falling_edge(SysClk100);
aRst_n <= '1';
sEnableAcquisition <= '1';
-- Process 2 * 2^14 samples to make sure all possible inputs are tested after calibration.
wait for (2**kADC_Width) * kADC_SamplingClkPeriod;
wait until doDataAxisTvalid = '1';
wait;
end process;
-- ZmodDcoClk domain stimuli. The counter used to generate the
-- ADC data bus stimuli is free running for this test bench.
ProcDcoDomainStimuli: process
begin
diDataGenRst_n <= '1';
diDataGenCntEn <= '1';
wait;
end process;
-- DcoClkOut domain stimuli.
ProcDcoClkOutDomainStimuli: process
begin
doSyncIn(0) <= '1';
if (kADC_ClkDiv > 1) then
doSyncIn(kADC_ClkDiv-1 downto 1) <= (others => '0');
end if;
doExtCh1HgMultCoef <= kCh1HgMultCoefDynamic;
doExtCh1HgAddCoef <= kCh1HgAddCoefDynamic;
doExtCh2HgMultCoef <= kCh2HgMultCoefDynamic;
doExtCh2HgAddCoef <= kCh2HgAddCoefDynamic;
wait until sInitDoneADC = '1';
doDataAxisTready <= '1';
wait;
end process;
-- Compare the calibrated data samples against the expected values.
ProcCh1CheckCalibData: process
begin
wait until sInitDoneADC = '1';
wait until doCh1TestInt'event or doCh1OutInt'event;
-- doCh1Diff is generated on the rising edge of DcoClkOut
-- and checked on the negative edge of DcoClkOut.
wait until falling_edge(DcoClkOut);
if ((doDataAxisTvalid = '1') and (aEnOverflowTest = '0')) then
assert (abs(doCh1Diff) < 2)
report "Calibration error: mismatch between expected data and actual data" & LF & HT & HT &
"Expected: " & integer'image(to_integer(signed(doChannel1_Test))) & LF & HT & HT &
"Actual: " & integer'image(doCh1OutInt) & LF & HT & HT &
"Difference: " & integer'image(doCh1Diff)
severity ERROR;
end if;
end process;
ProcCh2CheckCalibData: process
begin
wait until sInitDoneADC = '1';
wait until doCh2TestInt'event or doCh2OutInt'event;
-- doCh2Diff is generated on the rising edge of DcoClkOut
-- and checked on the negative edge of DcoClkOut.
wait until falling_edge(DcoClkOut);
if ((doDataAxisTvalid = '1') and (aEnOverflowTest = '0')) then
assert (abs(doCh2Diff) < 2)
report "Calibration error: mismatch between expected data and actual data" & LF & HT & HT &
"Expected: " & integer'image(to_integer(signed(doChannel2_Test))) & LF & HT & HT &
"Actual: " & integer'image(doCh2OutInt) & LF & HT & HT &
"Difference: " & integer'image(doCh2Diff)
severity ERROR;
end if;
end process;
ProcCheckADC_Init: process
begin
wait until sInitDoneClockGen = '1';
-- Wait for the reset signal to be de-asserted
wait until rising_edge(aRst_n);
-- Check if the sInitDoneADC signal is asserted and sConfigError is de-asserted
-- after the configuration timeout period (determined empirically)
wait for kCount5ms * kSysClkPeriod;
assert (sInitDoneADC = '1')
report "sInitDoneADC signal not asserted when expected" & LF & HT & HT
severity ERROR;
assert (sConfigError = '0')
report "sConfigError signal not de-asserted when expected" & LF & HT & HT
severity ERROR;
end process;
end Behavioral;
|
mit
|
48b34741403b1c2fa58b9cb185c7172f
| 0.645083 | 4.425946 | false | true | false | false |
JL-Grande/Ascensor_SED
|
ASCENSOR/antirrebote_vector.vhd
| 1 | 899 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity antirrebote_vector is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
vector_IN : in STD_LOGIC_VECTOR (2 downto 0);
vector_OUT : out STD_LOGIC_VECTOR(2 downto 0));
end antirrebote_vector;
architecture Dataflow of antirrebote_vector is
COMPONENT antirrebote
PORT (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
logic_IN : in STD_LOGIC;
logic_OUT : out STD_LOGIC);
END COMPONENT;
begin
inst_antirrebote_1:antirrebote port map(
CLK => CLK,
RST => RST,
logic_IN => vector_IN(0),
logic_OUT => vector_OUT(0)
);
inst_antirrebote_2:antirrebote port map(
CLK => CLK,
RST => RST,
logic_IN => vector_IN(1),
logic_OUT => vector_OUT(1)
);
inst_antirrebote_3:antirrebote port map(
CLK => CLK,
RST => RST,
logic_IN => vector_IN(2),
logic_OUT => vector_OUT(2)
);
end Dataflow;
|
gpl-3.0
|
d842fa65c052731b8b41094f243959ae
| 0.632925 | 2.937908 | false | false | false | false |
JL-Grande/Ascensor_SED
|
ASCENSOR/tb_antirrebote_vector.vhd
| 1 | 1,729 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_antirrebote_vector IS
END tb_antirrebote_vector;
ARCHITECTURE behavior OF tb_antirrebote_vector IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT antirrebote_vector
PORT(
CLK : IN std_logic;
RST : IN std_logic;
vector_IN : IN std_logic_vector(2 downto 0);
vector_OUT : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
signal vector_IN : std_logic_vector(2 downto 0) := (others => '0');
--Outputs
signal vector_OUT : std_logic_vector(2 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: antirrebote_vector PORT MAP (
CLK => CLK,
RST => RST,
vector_IN => vector_IN,
vector_OUT => vector_OUT
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
WAIT FOR 3 ns;
RST <= '0';
vector_IN <= "000";
WAIT FOR 35 ns;
RST <= '1';
WAIT FOR 5 ns;
vector_IN <= "100";
WAIT FOR 15 ns;
RST <= '0';
WAIT FOR 55 ns;
vector_IN <= "010";
WAIT FOR 2 ns;
vector_IN <= "101";
WAIT FOR 50 ns;
vector_IN <= "100";
WAIT FOR 4 ns;
vector_IN <= "110";
WAIT FOR 2 ns;
vector_IN <= "101";
WAIT FOR 3 ns;
vector_IN <= "010";
WAIT FOR 20 ns;
vector_IN <= "101";
WAIT FOR 50 ns;
ASSERT false
REPORT "Simulación finalizada. Test superado."
SEVERITY FAILURE;
end process;
END;
|
gpl-3.0
|
9c9a71ba90488da94ff3fdd324055ed7
| 0.596298 | 3.237828 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodDigitizerController/tb/tb_TestTop_AllZmods.vhd
| 1 | 9,610 |
-------------------------------------------------------------------------------
--
-- File: tb_TestTop_AllZmods.vhd
-- Author: Tudor Gherman, Robert Bocos
-- Original Project: Zmod ADC 1410 Low Level Controller
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This test bench is used to instantiate the tb_TestTop test bench for all
-- supported ZmodADC variants.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.PkgZmodDigitizer.all;
entity tb_TestTop_AllZmods is
end tb_TestTop_AllZmods;
architecture Behavioral of tb_TestTop_AllZmods is
constant kADC_SamplingClkPeriod_122_88 : time := 8.138ns;
constant kADC_SamplingClkPeriod_50 : time := 20ns;
constant kADC_SamplingClkPeriod_80 : time := 12.500ns;
constant kADC_SamplingClkPeriod_100 : time := 10ns;
constant kADC_SamplingClkPeriod_110 : time := 9.090ns;
constant kADC_SamplingClkPeriod_120 : time := 8.333ns;
constant kADC_SamplingClkPeriod_125 : time := 8ns;
constant kExtCalibEn : boolean := true;
constant kExtCmdInterfaceEn : boolean := true;
constant kCDCE_SimulationConfig : boolean := true;
constant kCDCE_SimulationCmdTotal : integer range 0 to kCDCE_RegNrZeroBased := 4;
constant kCDCEFreqSel_122_88 : integer range 0 to (kCDCE_FreqCfgsNr - 1) := 0;
constant kCDCEFreqSel_50 : integer range 0 to (kCDCE_FreqCfgsNr - 1) := 1;
constant kCDCEFreqSel_80 : integer range 0 to (kCDCE_FreqCfgsNr - 1) := 2;
constant kCDCEFreqSel_100 : integer range 0 to (kCDCE_FreqCfgsNr - 1) := 3;
constant kCDCEFreqSel_110 : integer range 0 to (kCDCE_FreqCfgsNr - 1) := 4;
constant kCDCEFreqSel_120 : integer range 0 to (kCDCE_FreqCfgsNr - 1) := 5;
constant kCDCEFreqSel_125 : integer range 0 to (kCDCE_FreqCfgsNr - 1) := 6;
constant kCDCEI2C_Addr : std_logic_vector(7 downto 0) := x"CE";
constant kCh1LgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101010110010";
constant kCh1LgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101111010101";
constant kCh1HgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101010100010";
constant kCh1HgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101111000101";
constant kCh2LgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101010010010";
constant kCh2LgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101101010101";
constant kCh2HgMultCoefStatic : std_logic_vector (17 downto 0) := "010001101000110010";
constant kCh2HgAddCoefStatic : std_logic_vector (17 downto 0) := "111111101111010001";
begin
------------------------------------------------------------------------------------------
-- Top level test bench instantiated for all supported Zmod ADC variants
------------------------------------------------------------------------------------------
InstTbTestTop_ZmodDigitizer_122_88: entity work.tb_TestTop
Generic Map(
kZmodID => kZmodDigitizer1430_125,
kADC_SamplingClkPeriod => kADC_SamplingClkPeriod_122_88,
kADC_ClkDiv => 1,
kExtCalibEn => kExtCalibEn,
kExtCmdInterfaceEn => kExtCmdInterfaceEn,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic,
kCDCEI2C_Addr => kCDCEI2C_Addr,
kCDCE_SimulationConfig => kCDCE_SimulationConfig,
kCDCE_SimulationCmdTotal => kCDCE_SimulationCmdTotal,
kCDCEFreqSel => kCDCEFreqSel_122_88
);
InstTbTestTop_ZmodDigitizer_50: entity work.tb_TestTop
Generic Map(
kZmodID => kZmodDigitizer1430_125,
kADC_SamplingClkPeriod => kADC_SamplingClkPeriod_50,
kADC_ClkDiv => 1,
kExtCalibEn => kExtCalibEn,
kExtCmdInterfaceEn => kExtCmdInterfaceEn,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic,
kCDCEI2C_Addr => kCDCEI2C_Addr,
kCDCE_SimulationConfig => kCDCE_SimulationConfig,
kCDCE_SimulationCmdTotal => kCDCE_SimulationCmdTotal,
kCDCEFreqSel => kCDCEFreqSel_50
);
InstTbTestTop_ZmodDigitizer_80: entity work.tb_TestTop
Generic Map(
kZmodID => kZmodDigitizer1430_125,
kADC_SamplingClkPeriod => kADC_SamplingClkPeriod_80,
kADC_ClkDiv => 1,
kExtCalibEn => kExtCalibEn,
kExtCmdInterfaceEn => kExtCmdInterfaceEn,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic,
kCDCEI2C_Addr => kCDCEI2C_Addr,
kCDCE_SimulationConfig => kCDCE_SimulationConfig,
kCDCE_SimulationCmdTotal => kCDCE_SimulationCmdTotal,
kCDCEFreqSel => kCDCEFreqSel_80
);
InstTbTestTop_ZmodDigitizer_100: entity work.tb_TestTop
Generic Map(
kZmodID => kZmodDigitizer1430_125,
kADC_SamplingClkPeriod => kADC_SamplingClkPeriod_100,
kADC_ClkDiv => 1,
kExtCalibEn => kExtCalibEn,
kExtCmdInterfaceEn => kExtCmdInterfaceEn,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic,
kCDCEI2C_Addr => kCDCEI2C_Addr,
kCDCE_SimulationConfig => kCDCE_SimulationConfig,
kCDCE_SimulationCmdTotal => kCDCE_SimulationCmdTotal,
kCDCEFreqSel => kCDCEFreqSel_100
);
InstTbTestTop_ZmodDigitizer_110: entity work.tb_TestTop
Generic Map(
kZmodID => kZmodDigitizer1430_125,
kADC_SamplingClkPeriod => kADC_SamplingClkPeriod_110,
kADC_ClkDiv => 1,
kExtCalibEn => kExtCalibEn,
kExtCmdInterfaceEn => kExtCmdInterfaceEn,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic,
kCDCEI2C_Addr => kCDCEI2C_Addr,
kCDCE_SimulationConfig => kCDCE_SimulationConfig,
kCDCE_SimulationCmdTotal => kCDCE_SimulationCmdTotal,
kCDCEFreqSel => kCDCEFreqSel_110
);
InstTbTestTop_ZmodDigitizer_120: entity work.tb_TestTop
Generic Map(
kZmodID => kZmodDigitizer1430_125,
kADC_SamplingClkPeriod => kADC_SamplingClkPeriod_120,
kADC_ClkDiv => 1,
kExtCalibEn => kExtCalibEn,
kExtCmdInterfaceEn => kExtCmdInterfaceEn,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic,
kCDCEI2C_Addr => kCDCEI2C_Addr,
kCDCE_SimulationConfig => kCDCE_SimulationConfig,
kCDCE_SimulationCmdTotal => kCDCE_SimulationCmdTotal,
kCDCEFreqSel => kCDCEFreqSel_120
);
InstTbTestTop_ZmodDigitizer_125: entity work.tb_TestTop
Generic Map(
kZmodID => kZmodDigitizer1430_125,
kADC_SamplingClkPeriod => kADC_SamplingClkPeriod_125,
kADC_ClkDiv => 1,
kExtCalibEn => kExtCalibEn,
kExtCmdInterfaceEn => kExtCmdInterfaceEn,
kCh1HgMultCoefStatic => kCh1HgMultCoefStatic,
kCh1HgAddCoefStatic => kCh1HgAddCoefStatic,
kCh2HgMultCoefStatic => kCh2HgMultCoefStatic,
kCh2HgAddCoefStatic => kCh2HgAddCoefStatic,
kCDCEI2C_Addr => kCDCEI2C_Addr,
kCDCE_SimulationConfig => kCDCE_SimulationConfig,
kCDCE_SimulationCmdTotal => kCDCE_SimulationCmdTotal,
kCDCEFreqSel => kCDCEFreqSel_125
);
end Behavioral;
|
mit
|
915c9e350e93181129b577dc0a1236a5
| 0.696358 | 4.933265 | false | true | false | false |
Digilent/vivado-library
|
ip/video_scaler/hdl/vhdl/Resize_opr_linearbkb.vhd
| 1 | 3,513 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Resize_opr_linearbkb_ram is
generic(
MEM_TYPE : string := "block";
DWIDTH : integer := 8;
AWIDTH : integer := 13;
MEM_SIZE : integer := 4097
);
port (
addr0 : in std_logic_vector(AWIDTH-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(DWIDTH-1 downto 0);
addr1 : in std_logic_vector(AWIDTH-1 downto 0);
ce1 : in std_logic;
d1 : in std_logic_vector(DWIDTH-1 downto 0);
we1 : in std_logic;
clk : in std_logic
);
end entity;
architecture rtl of Resize_opr_linearbkb_ram is
signal addr0_tmp : std_logic_vector(AWIDTH-1 downto 0);
type mem_array is array (0 to MEM_SIZE-1) of std_logic_vector (DWIDTH-1 downto 0);
shared variable ram : mem_array;
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is MEM_TYPE;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
p_memory_access_1: process (clk)
begin
if (clk'event and clk = '1') then
if (ce1 = '1') then
if (we1 = '1') then
ram(CONV_INTEGER(addr1)) := d1;
end if;
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity Resize_opr_linearbkb is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 4097;
AddressWidth : INTEGER := 13);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of Resize_opr_linearbkb is
component Resize_opr_linearbkb_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR);
end component;
begin
Resize_opr_linearbkb_ram_U : component Resize_opr_linearbkb_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
we1 => we1,
d1 => d1);
end architecture;
|
mit
|
2b1a9b7bf6f6c0638e64f2ff9e29ddf6
| 0.538286 | 3.570122 | false | false | false | false |
SLongofono/digital-design-final-project
|
VGA_ctrl.vhd
| 1 | 8,568 |
----------------------------------------------------------------------------------
-- Engineer: Longofono
-- Create Date: 04/26/2017 06:28:40 PM
-- Description: VGA control interface
--
-- Notes
--
-- Adapted from a starter module provided on
-- the Nexys4 Github site. Accessed 4/26/2017:
-- https://github.com/Digilent/Nexys4/tree/master/Projects/User_Demo/src/hdl
----------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.ALL;
use ieee.STD_LOGIC_ARITH.ALL;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
entity vga_ctrl is
Port (clk, rst : in STD_LOGIC;
VGA_HS_O : out STD_LOGIC;
VGA_VS_O : out STD_LOGIC;
VGA_RED_O : out STD_LOGIC_VECTOR (3 downto 0);
VGA_BLUE_O : out STD_LOGIC_VECTOR (3 downto 0);
VGA_GREEN_O : out STD_LOGIC_VECTOR (3 downto 0);
new_color : in std_logic_vector(11 downto 0);
address : in integer;
draw_enable : in std_logic
);
end vga_ctrl;
architecture Behavioral of vga_ctrl is
-- 640 x 480 @ 60Hz
constant FRAME_WIDTH : natural := 640;
constant FRAME_HEIGHT : natural := 480;
constant H_FP : natural := 16; --H front porch width (pixels)
constant H_PW : natural := 96; --H sync pulse width (pixels)
constant H_MAX : natural := 800; --H total period, sum of width, fp, sync, bp (pixels)
constant V_FP : natural := 10; --V front porch width (lines)
constant V_PW : natural := 2; --V sync pulse width (lines)
constant V_MAX : natural := 525; --V total period, sum of height, fp, sync, bp (lines)
constant H_POL : std_logic := '0';
constant V_POL : std_logic := '0';
-- Pixel clock, in this case 50 MHz
signal pxl_clk : std_logic;
signal pxl_counter : std_logic := '0';
signal toggle: std_logic := '0';
-- The active signal is used to signal the active region of the screen (when not blank)
signal active : std_logic;
-- Horizontal and Vertical counters
signal h_cntr_reg : std_logic_vector(11 downto 0) := (others =>'0');
signal v_cntr_reg : std_logic_vector(11 downto 0) := (others =>'0');
-- Indices for memory access
-- Pipe Horizontal and Vertical Counters
signal h_cntr_reg_dly : std_logic_vector(11 downto 0) := (others => '0');
signal v_cntr_reg_dly : std_logic_vector(11 downto 0) := (others => '0');
-- Horizontal and Vertical Sync
signal h_sync_reg : std_logic := not(H_POL);
signal v_sync_reg : std_logic := not(V_POL);
-- Pipe Horizontal and Vertical Sync
signal h_sync_reg_dly : std_logic := not(H_POL);
signal v_sync_reg_dly : std_logic := not(V_POL);
-- VGA R, G and B signals coming from the main multiplexers
signal vga_red_cmb : std_logic_vector(3 downto 0);
signal vga_green_cmb : std_logic_vector(3 downto 0);
signal vga_blue_cmb : std_logic_vector(3 downto 0);
--The main VGA R, G and B signals, validated by active
signal vga_red : std_logic_vector(3 downto 0);
signal vga_green : std_logic_vector(3 downto 0);
signal vga_blue : std_logic_vector(3 downto 0);
-- Register VGA R, G and B signals
signal vga_red_reg : std_logic_vector(3 downto 0) := (others =>'0');
signal vga_green_reg : std_logic_vector(3 downto 0) := (others =>'0');
signal vga_blue_reg : std_logic_vector(3 downto 0) := (others =>'0');
-- Colorbar red, greeen and blue signals
signal bg_red : std_logic_vector(3 downto 0);
signal bg_blue : std_logic_vector(3 downto 0);
signal bg_green : std_logic_vector(3 downto 0);
-- Pipe the colorbar red, green and blue signals
signal bg_red_dly : std_logic_vector(3 downto 0) := (others => '0');
signal bg_green_dly : std_logic_vector(3 downto 0) := (others => '0');
signal bg_blue_dly : std_logic_vector(3 downto 0) := (others => '0');
signal xpos : integer := 0;
signal ypos : integer := 0;
signal pix_write : integer := 5;
signal memory_write : std_logic := '1';
signal s_addr_read : integer := 0;
signal s_addr_write : integer := 0;
signal s_write_data : std_logic_vector(11 downto 0);
signal s_read_data : std_logic_vector(11 downto 0);
-- memory spoof
component memory is
port (
clk : in std_logic;
rst : in std_logic;
write : in std_logic;
address_read : in integer;
address_write : in integer;
write_data : in std_logic_vector(11 downto 0);
read_data : out std_logic_vector(11 downto 0)
);
end component;
signal pxl_write_count : integer := 0;
begin
pattern: memory
port map( clk => clk,
rst => rst,
write => draw_enable,
address_read => s_addr_read,
address_write => s_addr_write,
write_data => s_write_data,
read_data => s_read_data);
-- Generate special clock for the VGA
process(clk, rst)
begin
if('1' = rst) then
pxl_counter <= '0';
elsif(rising_edge(clk)) then
pxl_counter <= not pxl_counter;
-- 25 Mhz
if( '1' = pxl_counter ) then
pxl_clk <= not pxl_clk;
end if;
end if;
end process;
-- Generate Horizontal, Vertical counters and the Sync signals
-- Horizontal counter
process (pxl_clk)
begin
if (rising_edge(pxl_clk)) then
if (h_cntr_reg = (H_MAX - 1)) then
h_cntr_reg <= (others =>'0');
else
h_cntr_reg <= h_cntr_reg + 1;
end if;
end if;
end process;
-- Vertical counter
process (pxl_clk)
begin
if (rising_edge(pxl_clk)) then
if ((h_cntr_reg = (H_MAX - 1)) and (v_cntr_reg = (V_MAX - 1))) then
v_cntr_reg <= (others =>'0');
elsif (h_cntr_reg = (H_MAX - 1)) then
v_cntr_reg <= v_cntr_reg + 1;
end if;
end if;
end process;
-- Horizontal sync
process (pxl_clk)
begin
if (rising_edge(pxl_clk)) then
if (h_cntr_reg >= (H_FP + FRAME_WIDTH - 1)) and (h_cntr_reg < (H_FP + FRAME_WIDTH + H_PW - 1)) then
h_sync_reg <= H_POL;
else
h_sync_reg <= not(H_POL);
end if;
end if;
end process;
-- Vertical sync
process (pxl_clk)
begin
if (rising_edge(pxl_clk)) then
if (v_cntr_reg >= (V_FP + FRAME_HEIGHT - 1)) and (v_cntr_reg < (V_FP + FRAME_HEIGHT + V_PW - 1)) then
v_sync_reg <= V_POL;
else
v_sync_reg <= not(V_POL);
end if;
end if;
end process;
-- active signal
active <= '1' when h_cntr_reg_dly < FRAME_WIDTH and v_cntr_reg_dly < FRAME_HEIGHT
else '0';
-- If color or cursor position changes, update the memory
process(new_color,address)
begin
s_addr_write <= address;
s_write_data <= new_color;
end process;
-- update cursors sequentially
-- Beware of the signal delay! Using signals means the values of xpos, ypos
-- are not actually updated until the next clock cycle. This introduces error
-- in any computations which rely on the updated value, hence the use of FRAME_* -1
-- Using the next to last entry ensures that it gets updated at the correct time.
process(pxl_clk)
begin
if('1' = active and rising_edge(pxl_clk)) then
xpos <= xpos + 1;
if(xpos >= FRAME_WIDTH -1) then
xpos <= 0;
ypos <= ypos + 1;
if(ypos >= FRAME_HEIGHT -1) then
ypos <= 0;
end if;
end if;
s_addr_read <= (ypos * FRAME_WIDTH) + xpos;
end if;
end process;
-- Read from memory output
bg_red <= s_read_data(3 downto 0);
bg_green <= s_read_data(7 downto 4);
bg_blue <= s_read_data(11 downto 8);
-- Register Outputs coming from the displaying components and the horizontal and vertical counters
process (pxl_clk)
begin
if (rising_edge(pxl_clk)) then
h_cntr_reg_dly <= h_cntr_reg;
v_cntr_reg_dly <= v_cntr_reg;
end if;
end process;
vga_red <= bg_red;
vga_green <= bg_green;
vga_blue <= bg_blue;
-- Turn Off VGA RBG Signals if outside of the active screen
vga_red_cmb <= (active & active & active & active) and vga_red;
vga_green_cmb <= (active & active & active & active) and vga_green;
vga_blue_cmb <= (active & active & active & active) and vga_blue;
-- Register Outputs
process (pxl_clk)
begin
if (rising_edge(pxl_clk)) then
v_sync_reg_dly <= v_sync_reg;
h_sync_reg_dly <= h_sync_reg;
vga_red_reg <= vga_red_cmb;
vga_green_reg <= vga_green_cmb;
vga_blue_reg <= vga_blue_cmb;
end if;
end process;
-- Assign outputs
VGA_HS_O <= h_sync_reg_dly;
VGA_VS_O <= v_sync_reg_dly;
VGA_RED_O <= vga_red_reg;
VGA_GREEN_O <= vga_green_reg;
VGA_BLUE_O <= vga_blue_reg;
end Behavioral;
|
mit
|
422104c0a60f67a6da75f75ba9d8db7b
| 0.602007 | 3.239319 | false | false | false | false |
Digilent/vivado-library
|
ip/video_scaler/hdl/vhdl/fifo_w32_d3_A.vhd
| 1 | 4,597 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w32_d3_A_shiftReg is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w32_d3_A_shiftReg;
architecture rtl of fifo_w32_d3_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity fifo_w32_d3_A is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w32_d3_A is
component fifo_w32_d3_A_shiftReg is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - conv_std_logic_vector(1, 3);
if (mOutPtr = conv_std_logic_vector(0, 3)) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + conv_std_logic_vector(1, 3);
internal_empty_n <= '1';
if (mOutPtr = conv_std_logic_vector(DEPTH, 3) - conv_std_logic_vector(2, 3)) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w32_d3_A_shiftReg : fifo_w32_d3_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
1ef00c0a0d6bdfb4bd179107bc37648c
| 0.532956 | 3.420387 | false | false | false | false |
scottlbaker/Nova-SOC
|
src/decode.vhd
| 1 | 17,933 |
--========================================================================
-- decode.vhd :: Nova instruction decoder
--
-- (c) Scott L. Baker, Sierra Circuit Design
--========================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use work.my_types.all;
entity DECODE is
port (
-- decoder input
DECODE_IN : in std_logic_vector(15 downto 0);
-- opcode classes
FORMAT : out OP_FORMAT_TYPE; -- opcode format
ADDR_MODE : out ADDR_MODE_TYPE; -- address mode
-- ALU opcode fields
SRC_SEL : out std_logic_vector(1 downto 0); -- Source register
DST_SEL : out std_logic_vector(1 downto 0); -- Destination reg
ALU_OP : out ALU_OP_TYPE; -- ALU micro-op
SHIFT_CTL : out SHIFT_CTL_TYPE; -- Shifter control
CARRY_CTL : out CARRY_CTL_TYPE; -- Carry control
NO_LOAD : out std_logic; -- Don't load the dest
SKIP_CTL : out SKIP_CTL_TYPE; -- Skip control
-- Memory xfer opcode fields
FLOW_CTL : out FLOW_CTL_TYPE; -- Program flow control
IND_CTL : out std_logic; -- Indirect access
IDX_CTL : out IDX_CTL_TYPE; -- Index control
-- I/O opcode fields
XFER_CTL : out XFER_CTL_TYPE; -- Transfer control
IOU_CTL : out IOU_CTL_TYPE; -- I/O device control
EXT_OP : out EXT_OP_TYPE -- I/O device control
);
end DECODE;
architecture BEHAVIORAL of DECODE is
--=================================================================
-- signal definitions
--=================================================================
-- extended opcode group 1
signal GROUP1 : std_logic_vector(3 downto 0);
begin
GROUP1 <= DECODE_IN(12 downto 11) & DECODE_IN(7 downto 6);
--=========================================================
-- Decode the opcode and addressing mode
--=========================================================
DECODE_OPCODE_AND_ADDRESS_MODE:
process(DECODE_IN, GROUP1)
begin
--===================================================
-- Set the default states for the addressing modes
--===================================================
FORMAT <= UII_FORMAT;
ADDR_MODE <= ADM_OK;
SRC_SEL <= "00";
DST_SEL <= "00";
NO_LOAD <= '0';
IND_CTL <= '0';
ALU_OP <= TA;
FLOW_CTL <= JMP;
IDX_CTL <= ZPG;
SHIFT_CTL <= NOP;
CARRY_CTL <= NOP;
SKIP_CTL <= NOP;
XFER_CTL <= NOP;
IOU_CTL <= NOP;
EXT_OP <= NOP;
--====================================
-- Arithmetic/Logic Instructions
--====================================
if (DECODE_IN(15) = '1') then
FORMAT <= ALU_FORMAT;
SRC_SEL <= DECODE_IN(14 downto 13);
DST_SEL <= DECODE_IN(12 downto 11);
-- ALU control
case DECODE_IN(10 downto 8) is
when "000" =>
ALU_OP <= COM;
when "001" =>
ALU_OP <= NEG;
when "010" =>
ALU_OP <= TA;
when "011" =>
ALU_OP <= INC;
when "100" =>
ALU_OP <= ADC;
when "101" =>
ALU_OP <= SUB;
when "110" =>
ALU_OP <= ADD;
when "111" =>
ALU_OP <= ANA;
when others =>
end case;
-- shift control
case DECODE_IN(7 downto 6) is
when "00" =>
SHIFT_CTL <= NOP;
when "01" =>
SHIFT_CTL <= LEFT;
when "10" =>
SHIFT_CTL <= RIGHT;
when "11" =>
SHIFT_CTL <= SWAP;
when others =>
end case;
-- carry control
case DECODE_IN(5 downto 4) is
when "00" =>
CARRY_CTL <= NOP;
when "01" =>
CARRY_CTL <= CLEAR;
when "10" =>
CARRY_CTL <= SET;
when "11" =>
CARRY_CTL <= INVERT;
when others =>
end case;
NO_LOAD <= DECODE_IN(3);
-- skip control
case DECODE_IN(2 downto 0) is
when "000" =>
SKIP_CTL <= NOP; -- no skip
when "001" =>
SKIP_CTL <= SKP; -- skip
when "010" =>
SKIP_CTL <= SKC; -- skip if carry zero
when "011" =>
SKIP_CTL <= SNC; -- skip if carry non-zero
when "100" =>
SKIP_CTL <= SZR; -- skip if result zero
when "101" =>
SKIP_CTL <= SNR; -- skip if result non-zero
when "110" =>
SKIP_CTL <= SEZ; -- skip if either zero
when "111" =>
SKIP_CTL <= SBN; -- skip if both zero
when others =>
end case;
else
case DECODE_IN(15 downto 13) is
--=================================
-- Memory access Instructions
--=================================
when "000" =>
FORMAT <= MEM_FORMAT;
ADDR_MODE <= ADM_EA;
-- Program flow control
case DECODE_IN(12 downto 11) is
when "00" =>
FLOW_CTL <= JMP; -- jump to address
when "01" =>
FLOW_CTL <= JSR; -- jump to subroutine
when "10" =>
FLOW_CTL <= ISZ; -- incr and skip if zero
ALU_OP <= INC;
SKIP_CTL <= SZR;
when "11" =>
FLOW_CTL <= DSZ; -- decr and skip if zero
ALU_OP <= DEC;
SKIP_CTL <= SZR;
when others =>
end case;
IND_CTL <= DECODE_IN(10);
-- index control
case DECODE_IN(9 downto 8) is
when "00" =>
IDX_CTL <= ZPG; -- page zero
when "01" =>
IDX_CTL <= REL; -- PC relative
when "10" =>
IDX_CTL <= IDX2; -- index reg 2
when "11" =>
IDX_CTL <= IDX3; -- index reg 3
when others =>
end case;
--=================================
-- Load accumulator Instructions
--=================================
when "001" =>
FORMAT <= LDA_FORMAT;
ADDR_MODE <= ADM_EA;
DST_SEL <= DECODE_IN(12 downto 11);
IND_CTL <= DECODE_IN(10);
-- index control
case DECODE_IN(9 downto 8) is
when "00" =>
IDX_CTL <= ZPG; -- page zero
when "01" =>
IDX_CTL <= REL; -- PC relative
when "10" =>
IDX_CTL <= IDX2; -- index reg 2
when "11" =>
IDX_CTL <= IDX3; -- index reg 3
when others =>
end case;
--=================================
-- Store accumulator Instructions
--=================================
when "010" =>
FORMAT <= STA_FORMAT;
ADDR_MODE <= ADM_EA;
SRC_SEL <= DECODE_IN(12 downto 11);
IND_CTL <= DECODE_IN(10);
-- index control
case DECODE_IN(9 downto 8) is
when "00" =>
IDX_CTL <= ZPG; -- page zero
when "01" =>
IDX_CTL <= REL; -- PC relative
when "10" =>
IDX_CTL <= IDX2; -- index reg 2
when "11" =>
IDX_CTL <= IDX3; -- index reg 3
when others =>
end case;
--=================================
-- I/O Instructions
--=================================
when "011" =>
-- Device code 1 Extended opcodes
if (DECODE_IN(5 downto 0) = "000001") then
FORMAT <= EXT_FORMAT;
case DECODE_IN(10 downto 8) is
when "000" =>
case DECODE_IN(7 downto 6) is
-- move to frame pointer
when "00" =>
SRC_SEL <= DECODE_IN(12 downto 11);
EXT_OP <= MTFP;
-- move from frame pointer
when "10" =>
DST_SEL <= DECODE_IN(12 downto 11);
EXT_OP <= MFFP;
-- undefined opcodes
when others =>
end case;
-- load byte
when "001" =>
EXT_OP <= LDB;
DST_SEL <= DECODE_IN(7 downto 6);
SRC_SEL <= DECODE_IN(12 downto 11);
when "010" =>
case DECODE_IN(7 downto 6) is
-- move to stack pointer
when "00" =>
SRC_SEL <= DECODE_IN(12 downto 11);
EXT_OP <= MTSP;
-- move from stack pointer
when "10" =>
DST_SEL <= DECODE_IN(12 downto 11);
EXT_OP <= MFSP;
-- undefined opcodes
when others =>
end case;
when "011" =>
case DECODE_IN(7 downto 6) is
-- push onto stack
when "00" =>
SRC_SEL <= DECODE_IN(12 downto 11);
EXT_OP <= PSHA;
-- pop from stack
when "10" =>
DST_SEL <= DECODE_IN(12 downto 11);
EXT_OP <= POPA;
-- undefined opcodes
when others =>
end case;
-- store byte
when "100" =>
EXT_OP <= STB;
DST_SEL <= DECODE_IN(7 downto 6);
SRC_SEL <= DECODE_IN(12 downto 11);
when "101" =>
case GROUP1 is
-- save registers to stack
when "0000" =>
EXT_OP <= SAV;
-- return from subroutine
when "0010" =>
EXT_OP <= RET;
-- undefined opcodes
when others =>
end case;
-- store byte
when "110" =>
case GROUP1 is
-- unsigned multiply
when "1011" =>
EXT_OP <= MUL;
-- unsigned divide
when "1001" =>
EXT_OP <= DIV;
-- signed multiply
when "1110" =>
EXT_OP <= MULS;
-- signed divide
when "1100" =>
EXT_OP <= DIVS;
-- undefined opcodes
when others =>
end case;
-- undefined opcodes
when others =>
end case;
else
FORMAT <= IOU_FORMAT;
SRC_SEL <= DECODE_IN(12 downto 11);
DST_SEL <= DECODE_IN(12 downto 11);
-- transfer control
case DECODE_IN(10 downto 8) is
when "000" =>
XFER_CTL <= NOP; -- no I/O transfer
when "001" =>
XFER_CTL <= DIA; -- data in from buffer A
when "010" =>
XFER_CTL <= DOA; -- data out to buffer A
when "011" =>
XFER_CTL <= DIB; -- data in from buffer B
when "100" =>
XFER_CTL <= DOB; -- data out to buffer B
when "101" =>
XFER_CTL <= DIC; -- data in from buffer C
when "110" =>
XFER_CTL <= DOC; -- data out to buffer C
when "111" =>
XFER_CTL <= SKP; -- skip on condition
when others =>
end case;
-- IOU control
if DECODE_IN(10 downto 8) = "111" then
-- check for device 0x3f special cases
if (DECODE_IN(5 downto 0) = "111111") then
case DECODE_IN(7 downto 6) is
when "00" =>
SKIP_CTL <= SKPIE; -- skip if Int enabled
when "01" =>
SKIP_CTL <= SKPID; -- skip if Int disabled
when "10" =>
SKIP_CTL <= SKPPF; -- skip if power fail
when others =>
SKIP_CTL <= SKPPO; -- skip if power OK
end case;
else
case DECODE_IN(7 downto 6) is
when "00" =>
SKIP_CTL <= SKPBN; -- skip if busy is set
when "01" =>
SKIP_CTL <= SKPBZ; -- skip if busy is zero
when "10" =>
SKIP_CTL <= SKPDN; -- skip if done is set
when others =>
SKIP_CTL <= SKPDZ; -- skip if done is zero
end case;
end if;
else
case DECODE_IN(7 downto 6) is
when "00" =>
IOU_CTL <= NOP; -- no operation
when "01" =>
IOU_CTL <= SBCD; -- set busy; clear done
when "10" =>
IOU_CTL <= CBCD; -- clear busy and done
when others =>
IOU_CTL <= PULSE; -- issue a pulse
end case;
end if;
end if;
when others =>
end case;
end if;
end process;
end BEHAVIORAL;
|
gpl-3.0
|
e2f1397ef3509c21c1cd82e779d8312f
| 0.286511 | 6.156196 | false | false | false | false |
rickyzhangNYC/Pipelined_Multimedia_Cell_Lite_Unit
|
clz.vhd
| 1 | 1,659 |
-------------------------------------------------------------------------------
--
-- Title : clz
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\clz.vhd
-- Generated : Mon Dec 5 18:25:30 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {clz} architecture {behavioral}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity clz is
port(
rs1: in std_logic_vector(63 downto 0);
rd: out std_logic_vector (63 downto 0)
);
end clz;
--}} End of automatically maintained section
architecture behavioral of clz is
begin
process (rs1)
variable counter: integer range 0 to 32;
begin
for i in 32 to 63 loop
if (rs1(95-i) = '1') then
exit;
else
counter := counter + 1;
end if;
end loop;
rd(63 downto 32) <= std_logic_vector(to_unsigned(counter,32));
counter := 0;
for i in 0 to 31 loop
if (rs1(31-i) = '1') then
exit;
else
counter := counter + 1;
end if;
end loop;
rd(31 downto 0) <= std_logic_vector(to_unsigned(counter,32));
counter := 0;
end process;
end behavioral;
|
apache-2.0
|
61c0eb2dbba253ef0d5931246172ba33
| 0.468354 | 3.761905 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodDigitizerController/tb/AD96xx_92xxSPI_Model.vhd
| 1 | 15,997 |
-------------------------------------------------------------------------------
--
-- File: AD96xx_92xxSPI_Model.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Simulation model for the AD9648 ADC. Currently only the configuration SPI
-- interface implemented. The following conditions are tested:
-- 1. sSpiClk pulse high and low times are respected
-- 2. sSpiClk maximum and minimum (optional) frequency
-- 3. sCS to sSPI_Clk setup and hold times are respected
-- 4. sCS has no glitches during the 1 data byte transaction supported
-- 5. decodes command word and input data for write transactions
-- 6. generates output data byte for read transactions
-- 7. sSDIO to sSPI_Clk setup and hold times are respected
-- 8. No transitions occur on sSDIO and sCS during the idle state
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.PkgZmodDigitizer.all;
entity AD96xx_92xxSPI_Model is
Generic (
-- Parameter identifying the Zmod:
-- 0 -> Zmod Scope 1410 - 105 (AD9648)
-- 1 -> Zmod Scope 1010 - 40 (AD9204)
-- 2 -> Zmod Scope 1010 - 125 (AD9608)
-- 3 -> Zmod Scope 1210 - 40 (AD9231)
-- 4 -> Zmod Scope 1210 - 125 (AD9628)
-- 5 -> Zmod Scope 1410 - 40 (AD9251)
-- 6 -> Zmod Scope 1410 - 125 (AD9648)
kZmodID : integer range 0 to 6 := 6;
-- The number of data bits for the data phase of the transaction:
-- only 8 data bits currently supported.
kDataWidth : integer range 0 to 63 := 8;
-- The number of bits of the command phase of the SPI transaction.
kCommandWidth : integer range 0 to 63 := 8
);
Port (
-- 100MHz clock used by the AD9648_RegisterDecode block
SysClk100 : in STD_LOGIC;
-- Reset signal asynchronously asserted and synchronously
-- de-asserted (in SysClk100 domain)
asRst_n : in STD_LOGIC;
-- When InsertError is asserted the model produces an erroneous
-- reading for register address x01
InsertError : in STD_LOGIC;
-- 2 wire SPI interface
sSPI_Clk : in STD_LOGIC;
sSDIO : inout STD_LOGIC := 'Z';
sCS : in STD_LOGIC
);
end AD96xx_92xxSPI_Model;
architecture Behavioral of AD96xx_92xxSPI_Model is
signal sR_W_Decode : std_logic;
signal sWidthDecode : std_logic_vector(1 downto 0);
signal sAddrDecode : std_logic_vector(kCommandWidth - 4 downto 0);
signal sAddrDecodeReady : std_logic;
signal sDataWriteDecodeReady : std_logic;
signal sTransactionInProgress : boolean := false;
signal sDataDecode : std_logic_vector(kDataWidth-1 downto 0);
signal sSPI_ClkRising : time := 0 ns;
signal sSPI_ClkCounter : integer := 0;
signal sLastSPI_ClkEdge : time := 0ns;
signal sLastSPI_ClkRisingEdge : time := 0ns;
signal sSclkHigh : time := 0ns;
signal sRegDataOut : std_logic_vector(kDataWidth-1 downto 0) := x"00";
begin
AD9648_RegisterDecode_inst: entity work.AD96xx_92xx_RegisterDecode
Generic Map(
kZmodID => kZmodID,
kAddrWidth => kCommandWidth-3,
kRegDataWidth => kDataWidth
)
Port Map(
SysClk100 => SysClk100,
asRst_n => asRst_n,
InsertError => InsertError,
sDataWriteDecodeReady => sDataWriteDecodeReady,
sAddrDecodeReady => sAddrDecodeReady,
sDataDecode => sDataDecode,
sAddrDecode => sAddrDecode,
sRegDataOut => sRegDataOut
);
-- ADC Main process; checks for:
-- 1. sSpiClk pulse high and low times are respected.
-- 2. sSpiClk maximum and minimum (optional) frequency.
-- 3. sCS to sSPI_Clk setup and hold times are respected.
-- 4. sCS has no glitches during the 1 data byte transaction supported.
-- 5. decodes command word and input data for write transactions.
-- 6. generates output data byte for read transactions.
-- A sSPI_Clk falling edge is expected before sCS is pulled high.
ADC_Main: process
begin
sAddrDecodeReady <= '0';
sDataWriteDecodeReady <= '0';
if (sCS /= '0') then
wait until sCS = '0';
end if;
sSPI_ClkCounter <= 0;
sTransactionInProgress <= true;
sSDIO <= 'Z';
-- Wait for first sSPI_Clk rising edge
if (sSPI_Clk /= '0') then
wait until sSPI_Clk = '0';
end if;
wait until sSPI_Clk = '1';
-- First clock rising edge detected
sSPI_ClkCounter <= sSPI_ClkCounter + 1;
sLastSPI_ClkRisingEdge <= now;
sR_W_Decode <= sSDIO;
-- Check sCS to sSPI_Clk setup time
assert ((sCS'delayed'last_event) >= ktS)
report "setup time between sCS and sSPI_Clk is smaller than minimum allowed." & LF & HT & HT &
"Expected: " & time'image(ktS) & LF & HT & HT &
"Actual: " & time'image(sCS'delayed'last_event)
severity ERROR;
-- Check sSPI_Clk pulse width high for MSB
wait until sSPI_Clk = '0';
assert ((sSPI_Clk'delayed'last_event) >= kSclkHigh)
report "sSPI_Clk pulse width high is smaller than minimum allowed for command MSB." & LF & HT & HT &
"Expected: " & time'image(kSclkHigh) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event)
severity ERROR;
sSclkHigh <= sSPI_Clk'delayed'last_event;
-- Repeat for the following kCommandWidth-1 sSPI_Clk periods
for i in (kCommandWidth - 2) downto 0 loop
wait until sSPI_Clk = '1';
sSPI_ClkCounter <= sSPI_ClkCounter + 1;
sLastSPI_ClkRisingEdge <= now;
-- Check sSPI_Clk pulse width low
assert ((sSPI_Clk'delayed'last_event) >= kSclkLow)
report "sSPI_Clk pulse width low is smaller than minimum allowed for command bit" & integer'image(i+1) & LF & HT & HT &
"Expected: " & time'image(kSclkLow) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event)
severity ERROR;
-- Check sSPI_Clk frequency (measure between two consecutive rising edges) is smaller than the max allowed
assert ((sSPI_Clk'delayed'last_event + sSclkHigh) >= kSclkT_Min)
report "sSPI_Clk period is smaller than the minimum allowed for command bit" & integer'image(i+1) & LF & HT & HT &
"Expected: " & time'image(kSclkT_Min) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event + sSclkHigh)
severity ERROR;
-- Check sSPI_Clk frequency (measure between two consecutive rising edges) is higher than the min allowed
-- assert ((aSclkLow + sSclkHigh) <= kSclkT_Max)
-- report "sSPI_Clk period is higher than the maximum allowed." & LF & HT & HT &
-- "Expected: " & time'image(kSclkT_Max) & LF & HT & HT &
-- "Actual: " & time'image(aSclkLow + sSclkHigh)
-- severity ERROR;
if (i = kCommandWidth - 2) then
sWidthDecode(1) <= sSDIO;
elsif (i = kCommandWidth - 3) then
sWidthDecode(0) <= sSDIO;
else
sAddrDecode(i) <= sSDIO;
if (i=0) then
sAddrDecodeReady <= '1';
end if;
end if;
-- Wait sSPI_Clk falling edge
wait until sSPI_Clk = '0';
-- Check sSPI_Clk pulse width high
assert ((sSPI_Clk'delayed'last_event) >= kSclkHigh)
report "aSCK pulse width high is smaller than minimum allowed for command bit" & integer'image(i)& LF & HT & HT &
"Expected: " & time'image(kSclkHigh) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event)
severity ERROR;
sSclkHigh <= sSPI_Clk'delayed'last_event;
-- Drive first data byte when bus changes direction
if (i=0) then
if (sR_W_Decode = '1') then
sSDIO <= sRegDataOut(7);
end if;
sAddrDecodeReady <= '0';
end if;
end loop;
for i in (kDataWidth - 1) downto 0 loop
wait until sSPI_Clk = '1';
sSPI_ClkCounter <= sSPI_ClkCounter + 1;
sLastSPI_ClkRisingEdge <= now;
-- Check sSPI_Clk pulse width low
assert ((sSPI_Clk'delayed'last_event) >= kSclkLow)
report "sSPI_Clk pulse width low is smaller than minimum allowed for data bit " & integer'image(i+1) & LF & HT & HT &
"Expected: " & time'image(kSclkLow) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event)
severity ERROR;
-- Check sSPI_Clk frequency (measure between two consecutive rising edges) is smaller than the max allowed
assert ((sSPI_Clk'delayed'last_event + sSclkHigh) >= kSclkT_Min)
report "sSPI_Clk period is smaller than the minimum allowed for data bit " & integer'image(i+1) & LF & HT & HT &
"Expected: " & time'image(kSclkT_Min) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event + sSclkHigh)
severity ERROR;
-- Check sSPI_Clk frequency (measure between two consecutive rising edges) is higher than the min allowed
-- assert ((aSclkLow + sSclkHigh) <= kSclkT_Max)
-- report "sSPI_Clk period is higher than the maximum allowed." & LF & HT & HT &
-- "Expected: " & time'image(kSclkT_Max) & LF & HT & HT &
-- "Actual: " & time'image(aSclkLow + sSclkHigh)
-- severity ERROR;
-- Sample sSDIO on rising edge for write operations
if (sR_W_Decode = '0') then
sDataDecode(i) <= sSDIO;
end if;
-- Wait sSPI_Clk falling edge
wait until sSPI_Clk = '0';
-- Check sSPI_Clk pulse width high
assert ((sSPI_Clk'delayed'last_event) >= kSclkHigh)
report "aSCK pulse width high is smaller than minimum allowed for data bit" & integer'image(i) & LF & HT & HT &
"Expected: " & time'image(kSclkHigh) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event)
severity ERROR;
sSclkHigh <= sSPI_Clk'delayed'last_event;
-- Assign SDIO on falling edge for read operations
if (sR_W_Decode = '1') then
if (i > 0) then
sSDIO <= sRegDataOut(i-1);
else
sSDIO <= 'Z';
end if;
else
if (i=0) then
sDataWriteDecodeReady <= '1';
end if;
end if;
end loop;
sLastSPI_ClkEdge <= now;
sTransactionInProgress <= false;
wait until sCS = '1';
-- Check hold time between SCLK and sCS
assert ((now - sLastSPI_ClkRisingEdge) >= ktH)
report "Hold time (sCS to sSPI_Clk) is smaller than the minimum allowed." & LF & HT & HT &
"Expected: " & time'image(ktH) & LF & HT & HT &
"Actual: " & time'image(now - sLastSPI_ClkRisingEdge)
severity ERROR;
-- Check if no more than 24 bits transferred
assert ((now - sLastSPI_ClkEdge) = sSPI_Clk'last_event)
report "More than 24 bits transfered for current transaction." & LF & HT & HT
severity FAILURE;
-- Check last sSPI_Clk pulse low duration
assert ((now - sLastSPI_ClkEdge) >= kSclkLow)
report "aSCK pulse width low is smaller than minimum allowed data bit 0" & LF & HT & HT &
"Expected: " & time'image(kSclkLow) & LF & HT & HT &
"Actual: " & time'image(now - sLastSPI_ClkEdge)
severity ERROR;
end process ADC_Main;
-- Check if sCS low pulse is held low for the entire transaction
CheckCS: process
begin
if (sCS /= '0') then
wait until sCS = '0';
end if;
wait until sCS = '1';
assert (sTransactionInProgress = false)
report "CS pulse high during transaction." & LF & HT & HT
severity FAILURE;
end process CheckCS;
-- Check if sSDIO to sSPI_Clk setup time is respected
CheckSetup: process
begin
if (sSPI_Clk /= '0') then
wait until sSPI_Clk = '0';
end if;
wait until sSPI_Clk = '1';
sSPI_ClkRising <= now;
-- Check Setup Time
assert (sSDIO'last_active >= ktDS)
report "Setup time (data to sSPI_Clk) is smaller than minimum allowed." & LF & HT & HT &
"Expected: " & time'image(ktDS) & LF & HT & HT &
"Actual: " & time'image(sSDIO'last_active)
severity ERROR;
end process CheckSetup;
-- Check if sSDIO to sSPI_Clk hold time is respected
CheckHold: process
begin
-- Wait for first clock rising edge
wait until sSPI_ClkRising /= 0 ns;
-- Wait for SDIO next bit to be assigned
wait until sSDIO'event;
-- Check Hold Time
assert ((now - sSPI_ClkRising) >= ktDH)
report "Hold time (data to sSPI_Clk) is smaller than minimum allowed." & LF & HT & HT &
"Expected: " & time'image(ktDH) & LF & HT & HT &
"Actual: " & time'image(now - sSPI_ClkRising)
severity ERROR;
end process CheckHold;
-- Check sSDIO idle condition
CheckSDIO_Idle: process
begin
wait until now /= 0 ps;
if (sCS = '0') then
wait until sCS = '1';
end if;
-- Check that sSDIO is in '0' when entering the idle state
assert (sSDIO = '0')
report "SDIO idle condition not respected."
severity WARNING;
-- Monitor all changes on the sSDIO signal and check if they occur during the idle state (sCS = '1');
wait until sSDIO'event;
assert (sCS = '0')
report "SDIO idle condition not respected."
severity WARNING;
end process CheckSDIO_Idle;
CheckSPI_ClkIdle: process
begin
wait until now /= 0 ps;
if (sCS = '0') then
wait until sCS = '1';
end if;
-- Check that sSDIO is in '0' when entering the idle state
assert (sSPI_Clk = '0')
report "sSPI_Clk idle condition not respected."
severity WARNING;
-- Monitor all changes on the sSPI_Clk signal and check if they occur during the idle state (sCS = '1');
wait until sSPI_Clk'event;
assert (sCS = '0')
report "sSPI_Clk idle condition not respected."
severity WARNING;
end process CheckSPI_ClkIdle;
end Behavioral;
|
mit
|
beefcf79beec717f7cd86070f69deb90
| 0.617678 | 4.195384 | false | false | false | false |
JL-Grande/Ascensor_SED
|
ASCENSOR/gestor_display.vhd
| 1 | 985 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity gestor_display is
Port ( CLK : in STD_LOGIC;
piso_now : in STD_LOGIC_VECTOR (1 downto 0);
piso_obj : in STD_LOGIC_VECTOR (1 downto 0);
piso_seleccionado : out STD_LOGIC_VECTOR (1 downto 0);
piso_actual : out STD_LOGIC_VECTOR (1 downto 0);
accion : out STD_LOGIC_VECTOR (1 downto 0)
);
end gestor_display;
architecture Behavioral of gestor_display is
signal piso_act:STD_LOGIC_VECTOR (1 downto 0);
begin
gestor_display:process(clk)
begin
if rising_edge(clk) then
if (piso_now/="00") then
piso_act <= piso_now;
end if;
piso_seleccionado <= piso_obj;
piso_actual <= piso_act;
if (piso_obj= "00") then
accion <= "01";
elsif (piso_act < piso_obj) then
accion <= "11";
elsif (piso_act > piso_obj) then
accion <= "00";
else
accion <= "10";
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
3aafa50057e0a732e9c5946fd072192c
| 0.615228 | 2.984848 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_gamma_correction_1_0/hdl/vhdl/start_for_Mat2AXIkbM.vhd
| 1 | 4,490 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity start_for_Mat2AXIkbM_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end start_for_Mat2AXIkbM_shiftReg;
architecture rtl of start_for_Mat2AXIkbM_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity start_for_Mat2AXIkbM is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of start_for_Mat2AXIkbM is
component start_for_Mat2AXIkbM_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_start_for_Mat2AXIkbM_shiftReg : start_for_Mat2AXIkbM_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
78ce9310198df5a6db18c6f10206c8d2
| 0.532962 | 3.549407 | false | false | false | false |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx
|
Frecuencimentro/RelojEscaladoTB.vhd
| 2 | 1,096 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY clk200Hz_tb IS
END clk200Hz_tb;
ARCHITECTURE behavior OF clk200Hz_tb IS
COMPONENT clk200Hz
PORT(
entrada : IN std_logic;
reset : IN std_logic;
salida : OUT std_logic
);
END COMPONENT;
-- Entradas
signal entrada : std_logic := '0';
signal reset : std_logic := '0';
-- Salidas
signal salida : std_logic;
constant entrada_t : time := 20 ns;
BEGIN
-- Instancia de la unidad bajo prueba.
uut: clk200Hz PORT MAP (
entrada => entrada,
reset => reset,
salida => salida
);
-- Definición del reloj.
entrada_process :process
begin
entrada <= '0';
wait for entrada_t / 2;
entrada <= '1';
wait for entrada_t / 2;
end process;
-- Procesamiento de estímulos.
estimulos: process
begin
reset <= '1'; -- Condiciones iniciales.
wait for 100 ns;
reset <= '0'; -- ¡A trabajar!
wait;
end process;
END;
|
gpl-2.0
|
6788f0302ffad302c61e7a6aa41ab58d
| 0.534672 | 3.818815 | false | false | false | false |
scottlbaker/Nova-SOC
|
src/mem.vhd
| 2 | 7,347 |
--=================================================================
-- MEM.VHD :: 8Kx16 RAM model loaded with Hex Format
--
-- (c) Scott L. Baker, Sierra Circuit Design
--=================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
entity RAM is
port(
RADDR : in std_logic_vector(12 downto 0);
WADDR : in std_logic_vector(12 downto 0);
DATA_IN : in std_logic_vector(15 downto 0);
DATA_OUT : out std_logic_vector(15 downto 0);
BYTEOP : in std_logic; -- byte operation
REN : in std_logic; -- read enable
WEN : in std_logic; -- write enable
WCLK : in std_logic;
RCLK : in std_logic
);
end RAM;
architecture BEHAVIORAL of RAM is
type Memtype is array (integer range 0 to 16383) of std_logic_vector(7 downto 0);
file progfile : TEXT OPEN read_mode is "mem.hex";
signal Rd_Addr : integer range 16383 downto 0;
signal Wr_Addr : integer range 16383 downto 0;
signal Initialized : boolean := FALSE;
--==========================================
-- character to integer conversion function
--==========================================
function char_to_int(ch : character ) return integer is
variable result : integer := 0;
begin
case ch is
when '0' => result := 0;
when '1' => result := 1;
when '2' => result := 2;
when '3' => result := 3;
when '4' => result := 4;
when '5' => result := 5;
when '6' => result := 6;
when '7' => result := 7;
when '8' => result := 8;
when '9' => result := 9;
when 'a' => result := 10;
when 'b' => result := 11;
when 'c' => result := 12;
when 'd' => result := 13;
when 'e' => result := 14;
when 'f' => result := 15;
when 'A' => result := 10;
when 'B' => result := 11;
when 'C' => result := 12;
when 'D' => result := 13;
when 'E' => result := 14;
when 'F' => result := 15;
when others => result := 0;
end case;
return result;
end function char_to_int;
begin
Rd_Addr <= conv_integer(RADDR(12 downto 1) & '0');
Wr_Addr <= conv_integer(WADDR(12 downto 1) & '0');
--==========================================
-- Configurable Memory Model
--==========================================
MEMORY:
process (DATA_IN, Rd_Addr, Wr_Addr, RCLK, WCLK)
variable DATA : Memtype;
variable L : line;
variable ch : character;
variable rec_type : character;
variable digit : integer;
variable byte : integer;
variable byte_no : integer;
variable num_bytes : integer;
variable address : integer;
variable offset : integer;
variable end_of_data : boolean;
variable line_num : integer;
begin
-- Init from file
if not Initialized then
Initialized <= TRUE;
line_num := 0;
offset := 0;
end_of_data := FALSE;
while not (endfile(progfile) or end_of_data) loop
-- Reset the variables for the line
address := 0;
line_num := line_num + 1;
readline(progfile, L);
-- Read in the : character
read(L, ch);
if ch /= ':' then
next; -- get the next character
end if;
-- Read in the number of bytes
read(L, ch); -- msb
digit := char_to_int(ch);
read(L, ch); -- lsb
num_bytes := digit*16 + char_to_int(ch);
-- Read in the address
for k in 3 downto 0 loop
read(L, ch);
digit := char_to_int(ch);
address := address + digit * 16**k;
end loop;
-- Read in the record type
read(L,ch);
ASSERT ch = '0'
REPORT "Illegal record on line " & INTEGER'IMAGE(line_num);
read(L,rec_type);
-- If it is a line of all zeros, then it is the end of data.
if (num_bytes = 0) and (address = 0) then
end_of_data := TRUE;
-- If it is normal data, then read in all of the bytes to program_mem
elsif rec_type = '0' then -- it has normal data
byte_no := 0;
for byte_no in 0 to num_bytes-1 loop
read(L,ch);
digit := char_to_int(ch);
read(L,ch);
byte := digit*16 + char_to_int(ch);
DATA(offset + address + byte_no) := conv_std_logic_vector(byte, 8);
-- REPORT "writing data " & INTEGER'IMAGE(byte) & " to address " &
-- INTEGER'IMAGE(offset + address + byte_no);
end loop;
-- If it is an end of file record, then set end_of_data true
elsif rec_type = '1' then -- it is an end of file record
end_of_data := true;
-- If is an address-offset record update offset
elsif rec_type = '2' then
offset := 0;
for k in 3 downto 0 loop
read(l, ch);
digit := char_to_int(ch);
offset := offset + digit*16**k;
end loop;
offset := offset *16;
end if;
end loop;
else
-- Synchronous Read
if (RCLK = '1' and RCLK'event) then
if (REN = '1') then
DATA_OUT <= DATA(Rd_Addr+1) & DATA(Rd_Addr);
end if;
end if;
-- Synchronous Write
if (WCLK = '1' and WCLK'event) then
if (WEN = '1') then
if (BYTEOP = '1') then
if (WADDR(0) = '1') then
DATA(Wr_Addr+1) := DATA_IN(15 downto 8);
else
DATA(Wr_Addr) := DATA_IN( 7 downto 0);
end if;
else
DATA(Wr_Addr+1) := DATA_IN(15 downto 8);
DATA(Wr_Addr) := DATA_IN( 7 downto 0);
end if;
end if;
end if;
end if;
end process;
end BEHAVIORAL;
|
gpl-3.0
|
1a8744a259f482b46b1ea7a999203f8f
| 0.400708 | 4.496328 | false | false | false | false |
Digilent/vivado-library
|
ip/usb2device_v1_0/src/Receive_Path.vhd
| 2 | 31,706 |
-------------------------------------------------------------------------------
--
-- File: Receive_Path.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module stores the data received over the UPLI bus on demand from the
-- packet decoder state machine. The data is formated to the AXI Stream protocol
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity Receive_Path is
Port (
Ulpi_Clk : in STD_LOGIC;
Axi_Clk : IN std_logic;
reset : in STD_LOGIC;
--RX FIFO STREAM INTERFACE
u_Rx_Fifo_s_Aclk : OUT std_logic;
u_Rx_Fifo_s_Axis_Tready : IN std_logic;
u_Rx_Fifo_s_Axis_Tvalid : OUT std_logic;
u_Rx_Fifo_s_Axis_Tdata : OUT std_logic_vector(31 downto 0);
u_Rx_Fifo_s_Axis_Tkeep : OUT std_logic_vector (3 downto 0);
u_Rx_Fifo_s_Axis_Tlast : OUT std_logic;
u_Rx_Fifo_Axis_Overflow : IN std_logic;
u_Rx_Fifo_Axis_Underflow : IN std_logic;
u_Command_Fifo_Rd_En : IN std_logic;
u_Command_Fifo_Dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
u_Command_Fifo_Empty : OUT std_logic;
u_Command_Fifo_Valid : OUT std_logic;
u_Setup_Buffer_Bytes_3_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
u_Setup_Buffer_Bytes_7_4 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
u_Setup_Buffer_Bytes_3_0_Loc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
u_Device_Addr : IN STD_LOGIC_VECTOR (6 downto 0);
u_Fifo_Empty : OUT STD_LOGIC;
--inputs from ULPI
u_Rx_Data : in STD_LOGIC_VECTOR(7 downto 0);
u_Ulpi_Dir_Out : in STD_LOGIC;
--inputs from FSM
u_Store_Packet : in STD_LOGIC;
u_Store_Packet_State : in STD_LOGIC;
u_End_Packet_Set : in STD_LOGIC;
u_Fifo_Write_Toggle_Set : in STD_LOGIC;
u_Fifo_Write_Toggle_Rst : in STD_LOGIC;
u_Fifo_Rst_q : in STD_LOGIC;
u_Input_Buffer_Loaded_Rst : in STD_LOGIC;
u_Accept_Data_Set : in STD_LOGIC;
u_Accept_Setup_Data_Set : in STD_LOGIC;
u_Setup_Received_Set : OUT std_logic;
u_Input_CR16 : OUT std_logic_vector(15 downto 0)
);
end Receive_Path;
architecture Behavioral of Receive_Path is
COMPONENT fifo_generator_input_buffer
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fifo_generator_command
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
full : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
signal u_Command_Fifo_Din : STD_LOGIC_VECTOR (23 downto 0);
signal u_Command_Fifo_Wr_En : STD_LOGIC;
--DELAY PACKET BYTES
signal u_End_Packet : STD_LOGIC;
signal u_End_Packet_Rst : STD_LOGIC;
signal u_Rx_Data_q : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal u_Rx_Data_qq : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal u_Store_Packet_q : STD_LOGIC;
signal u_Store_Packet_qq : STD_LOGIC;
signal u_Input_Byte_Count : STD_LOGIC_VECTOR (14 downto 0);
signal u_Input_Byte_CE : STD_LOGIC;
signal u_Input_Byte_CE_Aux : STD_LOGIC;
signal u_Input_Byte_Count_Rst : STD_LOGIC;
type store_counter is array (1 downto 0) of std_logic_vector(14 downto 0);
signal u_Input_Byte_Count_Array : store_counter;
signal u_Input_Byte_Count_Aux : STD_LOGIC_VECTOR (14 downto 0);
signal u_Input_Byte_Count_Aux1 : STD_LOGIC_VECTOR (14 downto 0);
signal u_Input_Byte_Count_Complement : std_logic_vector(1 downto 0);
signal u_Packet_Byte_Count : STD_LOGIC_VECTOR (12 downto 0);
signal u_Packet_Byte_CE : STD_LOGIC;
signal u_Packet_Byte_Count_Rst : STD_LOGIC;
signal u_Fifo_Din : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal u_Fifo_Wr_En : STD_LOGIC;
signal u_Fifo_Wr_En_Aux : STD_LOGIC;
signal u_Fifo_Wr_En_Complete32 : STD_LOGIC; --if the packet has a number of bytes not multiple of 4 dummy bytes must be added so that the last 4 byte word is available at the FIFO output
signal u_Fifo_Rd_En : STD_LOGIC;
signal u_Fifo_Dout : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal u_Fifo_Valid : STD_LOGIC;
signal u_Fifo_Empty_Out : STD_LOGIC;
signal u_Fifo_Reset_Array : STD_LOGIC_VECTOR (1 downto 0);
signal u_Fifo1_Reset : STD_LOGIC;
signal u_Fifo1_Din : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal u_Fifo1_Wr_En : STD_LOGIC;
signal u_Fifo1_Rd_En : STD_LOGIC;
signal u_Fifo1_Dout : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal u_Fifo1_Full : STD_LOGIC;
signal u_Fifo1_Empty : STD_LOGIC;
signal u_Fifo1_Valid : STD_LOGIC;
signal u_Fifo2_Reset : STD_LOGIC;
signal u_Fifo2_Din : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal u_Fifo2_Wr_En : STD_LOGIC;
signal u_Fifo2_Rd_En : STD_LOGIC;
signal u_Fifo2_Dout : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal u_Fifo2_Full : STD_LOGIC;
signal u_Fifo2_Empty : STD_LOGIC;
signal u_Fifo2_Valid : STD_LOGIC;
signal u_Input_Buffer_Loaded_set : STD_LOGIC;
signal u_Input_Buffer_Loaded : STD_LOGIC;
signal u_Fifo_Write_Toggle_Aux : STD_LOGIC;
signal u_Fifo_Write_Toggle_En_Pulse : STD_LOGIC;
signal u_Fifo_Write_Toggle_En : STD_LOGIC;
signal u_Fifo_Write_Toggle_En_q : STD_LOGIC;
signal u_Fifo_Write_Toggle : STD_LOGIC;
signal u_Fifo_Write_Toggle_Ready : STD_LOGIC;
signal u_Fifo_Toggle_Read_Set : STD_LOGIC;
signal u_Fifo_Toggle_Read : STD_LOGIC;
signal u_Rx_Transfer_Done : STD_LOGIC;
signal u_Rx_Transfer_Done_q : STD_LOGIC;
signal u_Rx_Transfer_Done_Pulse : STD_LOGIC;
signal u_Accept_Setup_Data : STD_LOGIC;
signal u_Accept_Data : STD_LOGIC;
signal u_Setup_Buffer_Bytes_7_4_Latch : STD_LOGIC;
signal u_Setup_Buffer_Bytes_3_0_Latch : STD_LOGIC;
signal index1 : std_logic_vector(0 downto 0);
signal index2 : std_logic_vector(0 downto 0);
signal index1_int : integer range 0 to 1;
signal index2_int : integer range 0 to 1;
begin
u_Rx_Fifo_s_Aclk <= Ulpi_Clk;
-----COMMAND FIFO-----------------------------------------------
u_Command_Fifo_Din <= u_Packet_Byte_Count & u_Device_Addr & "0000";
RX_COMMAND_FIFO : fifo_generator_command
PORT MAP (
rst => reset,
wr_clk => Ulpi_Clk,
rd_clk => Axi_Clk,
din => u_Command_Fifo_Din,
wr_en => u_Command_Fifo_Wr_En,
rd_en => u_Command_Fifo_Rd_En,
dout => u_Command_Fifo_Dout,
full => open,
valid => u_Command_Fifo_Valid,
empty => u_Command_Fifo_Empty
);
--------------------------------------------------------------------
index1(0) <= u_Fifo_Toggle_Read;
index2(0) <= u_Fifo_Write_Toggle;
index1_int <= to_integer(unsigned(index1));
index2_int <= to_integer(unsigned(index2));
-- Load packet into input buffer. Separate CRC16 bytes from the rest of the packet
END_PACKET_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0' or u_End_Packet_Rst = '0') then
u_End_Packet <= '0';
elsif (u_End_Packet_Set = '1') then
u_End_Packet <= '1';
end if;
end if;
end process;
DELAY_PACKET_BYTES: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_End_Packet_Rst <= '0';
u_Input_Byte_CE_Aux <= '0';
u_Rx_Data_q <= (others => '0');
u_Rx_Data_qq <= (others => '0');
u_Store_Packet_q <= '0';
u_Store_Packet_qq <= '0';
u_Fifo_Wr_En_Complete32 <= '0';
u_Input_Buffer_Loaded_set <= '0';
u_Input_Byte_Count_Rst <= '0';
elsif (u_Store_Packet = '1') then
u_Fifo_Wr_En_Complete32 <= '0';
u_End_Packet_Rst <= '1';
u_Input_Buffer_Loaded_set <= '0';
u_Input_Byte_Count_Rst <= '1';
u_Rx_Data_q <= u_Rx_Data;
u_Rx_Data_qq <= u_Rx_Data_q;
u_Store_Packet_q <= u_Store_Packet;
u_Store_Packet_qq <= u_Store_Packet_q;
elsif (u_End_Packet = '1') then
if(u_Input_Byte_Count = "00000000000010") then --zero length packet
u_Store_Packet_qq <= '0';
u_Store_Packet_q <= '0';
u_End_Packet_Rst <= '0';
u_Rx_Data_qq <= (others => '0');
u_Input_Byte_Count_Rst <= '0';
u_Input_Byte_CE_Aux <= '0';
u_Fifo_Wr_En_Complete32 <= '0';
u_Input_Buffer_Loaded_set <= '1';
else
u_Store_Packet_qq <= '0';
u_Store_Packet_q <= '0';
if (u_Input_Byte_Count(1 downto 0) = "00" and u_End_Packet_Rst /= '0') then --u_Input_Byte_Count = packet bytes + 2bytes(CRC16)
u_End_Packet_Rst <= '0';
u_Rx_Data_qq <= (others => '0');
u_Input_Byte_Count_Rst <= '0';
u_Input_Byte_CE_Aux <= '0';
u_Fifo_Wr_En_Complete32 <= '0';
u_Input_Buffer_Loaded_set <= '1';
elsif (u_End_Packet_Rst = '0') then
u_Fifo_Wr_En_Complete32 <= '0';
u_Input_Byte_Count_Rst <= '0';
u_Input_Byte_CE_Aux <= '0';
u_Input_Buffer_Loaded_set <= '0';
else
u_Fifo_Wr_En_Complete32 <= '1';
u_Input_Byte_Count_Rst <= '1';
u_Input_Byte_CE_Aux <= '1';
u_Input_Buffer_Loaded_set <= '0';
end if;
end if;
else
u_Input_Buffer_Loaded_set <= '0';
u_Input_Byte_CE_Aux <= '0';
u_Fifo_Wr_En_Complete32 <= '0';
u_Rx_Data_q <= u_Rx_Data;
u_Rx_Data_qq <= u_Rx_Data_q;
u_Store_Packet_q <= u_Store_Packet;
u_Store_Packet_qq <= u_Store_Packet_q;
u_End_Packet_Rst <= '1';
end if;
end if;
end process;
CRC16_PROC: process (Ulpi_Clk, u_Store_Packet_q, u_Store_Packet_qq, u_Store_Packet)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Input_CR16 <= (others => '0');
elsif (u_End_Packet_Set = '1') then
u_Input_CR16 <= u_Rx_Data_qq & u_Rx_Data_q;
end if;
end if;
end process;
u_Input_Byte_CE <= u_Fifo_Wr_En or u_Input_Byte_CE_Aux;
INPUT_BUFFER_BYTE_PROC : process (Ulpi_Clk) --count bytes stored in the input buffer
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if ((reset = '0') or ((u_Input_Byte_Count_Rst or u_Store_Packet) = '0')) then
u_Input_Byte_Count <= (others => '0');
else
if (u_Input_Byte_CE = '1') then
u_Input_Byte_Count <= std_logic_vector(unsigned(u_Input_Byte_Count)+1);
end if;
end if;
end if;
end process;
---------------DOUBLE BUFFER--------------------------------------
FIFO1 : fifo_generator_input_buffer
PORT MAP (
rst => u_Fifo1_Reset,
wr_clk => Ulpi_Clk,
rd_clk => Ulpi_Clk,
din => u_Fifo1_Din,
wr_en => u_Fifo1_Wr_En,
rd_en => u_Fifo1_Rd_En,
dout => u_Fifo1_Dout,
full => u_Fifo1_Full,
empty => u_Fifo1_Empty,
valid => u_Fifo1_Valid
);
FIFO2 : fifo_generator_input_buffer
PORT MAP (
rst => u_Fifo2_Reset,
wr_clk => Ulpi_Clk,
rd_clk => Ulpi_Clk,
din => u_Fifo2_Din,
wr_en => u_Fifo2_Wr_En,
rd_en => u_Fifo2_Rd_En,
dout => u_Fifo2_Dout,
full => u_Fifo2_Full,
empty => u_Fifo2_Empty,
valid => u_Fifo2_Valid
);
FIFO_RESET_ARRAY_PROC: process (Ulpi_Clk, u_Store_Packet_q, u_Store_Packet_qq, u_Store_Packet)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Fifo_Reset_Array <= (others => '0');
else
u_Fifo_Reset_Array(to_integer(unsigned(index1))) <= u_Rx_Transfer_Done_Pulse;
end if;
end if;
end process;
u_Fifo_Din <= u_Rx_Data_qq;
u_Fifo_Wr_En_Aux <= (u_Store_Packet_qq and u_Store_Packet_State) when (u_Ulpi_Dir_Out = '1') else '0';
u_Fifo_Wr_En <= u_Fifo_Wr_En_Aux or u_Fifo_Wr_En_Complete32; --u_Fifo_Wr_En <= (u_Store_Packet_qq and store_packet) or u_Fifo_Wr_En_Complete32;
u_Fifo1_Reset <= u_Fifo_Rst_q or (not reset) or u_Fifo_Reset_Array(0); --The reset is edge-sensitive and not level-sensitive. The synchronization logic looks for the rising edge of rst and creates an internal reset for the core
u_Fifo2_Reset <= u_Fifo_Rst_q or (not reset) or u_Fifo_Reset_Array(1);
u_Fifo1_Din <= u_Fifo_Din when u_Fifo_Write_Toggle = '0' else (others => '0');
u_Fifo2_Din <= u_Fifo_Din when u_Fifo_Write_Toggle = '1' else (others => '0');
u_Fifo1_Wr_En <= u_Fifo_Wr_En when u_Fifo_Write_Toggle = '0' else '0';
u_Fifo2_Wr_En <= u_Fifo_Wr_En when u_Fifo_Write_Toggle = '1' else '0';
u_Fifo1_Rd_En <= u_Fifo_Rd_En when u_Fifo_Toggle_Read = '0' else '0';
u_Fifo2_Rd_En <= u_Fifo_Rd_En when u_Fifo_Toggle_Read = '1' else '0';
u_Fifo_Dout <= u_Fifo1_Dout when u_Fifo_Toggle_Read = '0' else u_Fifo2_Dout;
u_Fifo_Empty <= u_Fifo1_Empty when u_Fifo_Write_Toggle = '0' else u_Fifo2_Empty;
u_Fifo_Empty_Out <= u_Fifo1_Empty when u_Fifo_Toggle_Read = '0' else u_Fifo2_Empty;
u_Fifo_Valid <= u_Fifo1_Valid when u_Fifo_Toggle_Read = '0' else u_Fifo2_Valid;
---Double buffer selection signals--------------------------------
RX_TRANSFER_DONE_PULSE_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Rx_Transfer_Done_Pulse <= '0';
u_Rx_Transfer_Done_q <= '0';
else
u_Rx_Transfer_Done_q <= u_Rx_Transfer_Done;
u_Rx_Transfer_Done_Pulse <= u_Rx_Transfer_Done and (not u_Rx_Transfer_Done_q);
end if;
end if;
end process;
FSM_FIFO_IN_TOGGLE_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0' or u_Fifo_Write_Toggle_Rst = '0') then
u_Fifo_Write_Toggle_Aux <= '0';
elsif (u_Fifo_Write_Toggle_Set = '1') then
u_Fifo_Write_Toggle_Aux <= '1';
end if;
end if;
end process;
INPUT_BUFFER_LOADED_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0' or u_Input_Buffer_Loaded_Rst = '0') then
u_Input_Buffer_Loaded <= '0';
elsif (u_Input_Buffer_Loaded_set = '1') then
u_Input_Buffer_Loaded <= '1';
end if;
end if;
end process;
u_Fifo_Write_Toggle_En <= u_Input_Buffer_Loaded and u_Fifo_Write_Toggle_Aux;
FIFO_TOGGLE_IN_PULSE : process (Ulpi_Clk)
begin
if (Ulpi_Clk'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Fifo_Write_Toggle_En_Pulse <= '0';
u_Fifo_Write_Toggle_En_q <= '0';
else
u_Fifo_Write_Toggle_En_q <= u_Fifo_Write_Toggle_En;
u_Fifo_Write_Toggle_En_Pulse <= u_Fifo_Write_Toggle_En and (not u_Fifo_Write_Toggle_En_q);
end if;
end if;
end process;
FIFO_IN_TOGGLE_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Fifo_Write_Toggle <= '0';
elsif (u_Fifo_Write_Toggle_En_Pulse = '1') then
u_Fifo_Write_Toggle <= not (u_Fifo_Write_Toggle);
end if;
end if;
end process;
FIFO_IN_TOGGLE_READY_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0' or u_Rx_Transfer_Done_Pulse = '1') then
u_Fifo_Write_Toggle_Ready <= '0';
elsif (u_Fifo_Write_Toggle_En_Pulse = '1') then
u_Fifo_Write_Toggle_Ready <= '1';
end if;
end if;
end process;
FIFO_OUT_TOGGLE: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Fifo_Toggle_Read_Set <= '0';
elsif (u_Rx_Transfer_Done_Pulse = '1') then
if (u_Fifo_Write_Toggle /= u_Fifo_Toggle_Read) then
u_Fifo_Toggle_Read_Set <= '1';
end if;
else
u_Fifo_Toggle_Read_Set <= '0';
end if;
end if;
end process;
FIFO_OUT_TOGGLE_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Fifo_Toggle_Read <= '0';
elsif (u_Fifo_Toggle_Read_Set = '1') then
u_Fifo_Toggle_Read <= not (u_Fifo_Toggle_Read);
end if;
end if;
end process;
----------------------NATIVE FIFO TO AXI TREAM CONVERTER-------------------------------------
ACCEPT_DATA_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0' or u_Rx_Transfer_Done = '1') then
u_Accept_Data <= '0';
elsif (u_Accept_Data_Set = '1') then
u_Accept_Data <= '1';
end if;
end if;
end process;
ACCEPT_SETUP_DATA_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0' or u_Rx_Transfer_Done = '1') then
u_Accept_Setup_Data <= '0';
elsif (u_Accept_Setup_Data_Set = '1') then
u_Accept_Setup_Data <= '1';
end if;
end if;
end process;
RX_FIFO_COMB_PROC : process (reset, u_Fifo_Valid, u_Fifo_Write_Toggle_Ready, u_Input_Byte_Count_Array, index1, u_Accept_Setup_Data, u_Fifo_Dout, u_Input_Byte_Count_Aux, u_Packet_Byte_Count, u_Fifo_Valid, u_Accept_Data, u_Rx_Fifo_s_Axis_Tready)
begin
if (reset = '0') then
u_Fifo_Rd_En <= '0';
u_Packet_Byte_CE <= '0';
u_Rx_Transfer_Done <= '0';
u_Setup_Received_Set <= '0';
u_Packet_Byte_Count_Rst <= '0';
u_Command_Fifo_Wr_En <= '0';
u_Rx_Fifo_s_Axis_Tkeep <= "0000";
u_Rx_Fifo_s_Axis_Tdata <= (others => '0');
u_Rx_Fifo_s_Axis_Tlast <= '0';
u_Setup_Buffer_Bytes_7_4_Latch <= '0';
u_Setup_Buffer_Bytes_3_0_Latch <= '0';
elsif (u_Fifo_Write_Toggle_Ready = '1') then
if (u_Accept_Data = '1') then
u_Setup_Buffer_Bytes_7_4_Latch <= '0';
u_Setup_Buffer_Bytes_3_0_Latch <= '0';
u_Setup_Received_Set <= '0';
u_Rx_Fifo_s_Axis_Tdata <= u_Fifo_Dout;
u_Fifo_Rd_En <= '1';
if (u_Packet_Byte_Count = "0000000000000" and u_Input_Byte_Count_Aux = "000000000000000") then -- zero length packet
u_Rx_Fifo_s_Axis_Tlast <= '0';
u_Rx_Fifo_s_Axis_Tkeep <= "1111";
u_Command_Fifo_Wr_En <= '0';
u_Packet_Byte_Count_Rst <= '0';
u_Fifo_Rd_En <= '0';
u_Packet_Byte_CE <= '0';
u_Rx_Transfer_Done <= '1';
elsif (u_Rx_Fifo_s_Axis_Tready = '1') then
if (u_Fifo_Valid = '1') then
u_Packet_Byte_CE <= '1';
if (u_Packet_Byte_Count = u_Input_Byte_Count_Aux(14 downto 2)) then
u_Rx_Transfer_Done <= '1';
u_Packet_Byte_Count_Rst <= '0';
u_Command_Fifo_Wr_En <= '1';
u_Rx_Fifo_s_Axis_Tlast <= '1';
if (u_Input_Byte_Count_Array(to_integer(unsigned(index1)))(1 downto 0) = "00") then --n*4 bytes + 2CRC (CRC16 not saved)
u_Rx_Fifo_s_Axis_Tkeep <= "1111";
elsif (u_Input_Byte_Count_Array(to_integer(unsigned(index1)))(1 downto 0) = "01") then --n*4 bytes + 1byte + 2CRC
u_Rx_Fifo_s_Axis_Tkeep <= "0001";
elsif (u_Input_Byte_Count_Array(to_integer(unsigned(index1)))(1 downto 0) = "10") then --n*4 bytes + 2bytes + 2CRC
u_Rx_Fifo_s_Axis_Tkeep <= "0011";
elsif (u_Input_Byte_Count_Array(to_integer(unsigned(index1)))(1 downto 0) = "11") then --n*4 bytes + 3byte + 2CRC
u_Rx_Fifo_s_Axis_Tkeep <= "0111";
else
u_Rx_Fifo_s_Axis_Tkeep <= "1111";
end if;
else
u_Rx_Fifo_s_Axis_Tlast <= '0';
u_Rx_Fifo_s_Axis_Tkeep <= "1111";
u_Rx_Transfer_Done <= '0';
u_Packet_Byte_Count_Rst <= '1';
u_Command_Fifo_Wr_En <= '0';
end if;
else
u_Rx_Fifo_s_Axis_Tlast <= '0';
u_Rx_Fifo_s_Axis_Tkeep <= "1111";
u_Command_Fifo_Wr_En <= '0';
u_Packet_Byte_Count_Rst <= '1';
u_Rx_Transfer_Done <= '0';
u_Packet_Byte_CE <= '0';
end if;
else
u_Rx_Fifo_s_Axis_Tlast <= '0';
u_Rx_Fifo_s_Axis_Tkeep <= "1111";
u_Command_Fifo_Wr_En <= '0';
u_Packet_Byte_Count_Rst <= '1';
u_Fifo_Rd_En <= '0';
u_Packet_Byte_CE <= '0';
u_Rx_Transfer_Done <= '0';
end if;
elsif (u_Accept_Setup_Data = '1') then
u_Rx_Fifo_s_Axis_Tdata <= (others => '0');
u_Rx_Fifo_s_Axis_Tkeep <= "1111";
u_Rx_Fifo_s_Axis_Tlast <= '0';
u_Command_Fifo_Wr_En <= '0';
u_Fifo_Rd_En <= '1';
u_Setup_Buffer_Bytes_7_4_Latch <= '0';
u_Setup_Buffer_Bytes_3_0_Latch <= '0';
if (u_Fifo_Valid = '1') then
u_Packet_Byte_CE <= '1';
if (u_Packet_Byte_Count = "0000000000000") then
u_Rx_Transfer_Done <= '0';
u_Setup_Received_Set <= '0';
u_Packet_Byte_Count_Rst <= '1';
u_Setup_Buffer_Bytes_3_0_Latch <= '1';
elsif (u_Packet_Byte_Count = "0000000000001") then
u_Rx_Transfer_Done <= '1';
u_Setup_Received_Set <= '1';
u_Packet_Byte_Count_Rst <= '0';
u_Setup_Buffer_Bytes_7_4_Latch <= '1';
else
u_Rx_Transfer_Done <= '0';
u_Setup_Received_Set <= '0';
u_Packet_Byte_Count_Rst <= '1';
end if;
else
u_Setup_Received_Set <= '0';
u_Rx_Transfer_Done <= '0';
u_Packet_Byte_Count_Rst <= '1';
u_Packet_Byte_CE <= '0';
end if;
else
u_Packet_Byte_Count_Rst <= '0';
u_Rx_Fifo_s_Axis_Tdata <= (others => '0');
u_Setup_Buffer_Bytes_7_4_Latch <= '0';
u_Setup_Buffer_Bytes_3_0_Latch <= '0';
u_Rx_Fifo_s_Axis_Tlast <= '0';
u_Setup_Received_Set <= '0';
u_Command_Fifo_Wr_En <= '0';
u_Rx_Transfer_Done <= '0';
u_Fifo_Rd_En <= '0';
u_Packet_Byte_CE <= '0';
u_Rx_Fifo_s_Axis_Tkeep <= "1111";
end if;
else
u_Packet_Byte_Count_Rst <= '0';
u_Rx_Fifo_s_Axis_Tdata <= (others => '0');
u_Setup_Buffer_Bytes_7_4_Latch <= '0';
u_Setup_Buffer_Bytes_3_0_Latch <= '0';
u_Rx_Fifo_s_Axis_Tlast <= '0';
u_Setup_Received_Set <= '0';
u_Command_Fifo_Wr_En <= '0';
u_Rx_Transfer_Done <= '0';
u_Fifo_Rd_En <= '0';
u_Packet_Byte_CE <= '0';
u_Rx_Fifo_s_Axis_Tkeep <= "1111";
end if;
end process;
RX_FIFO_S_AXIS_TVALID_PROC: process (Ulpi_Clk, u_Accept_Setup_Data, u_Fifo_Valid)
begin
if (u_Accept_Setup_Data = '1') then
if (u_Fifo_Valid = '1') then
u_Rx_Fifo_s_Axis_Tvalid <= '1';
else
u_Rx_Fifo_s_Axis_Tvalid <= '0';
end if;
else
u_Rx_Fifo_s_Axis_Tvalid <= '0';
end if;
end process;
RX_FIFO_PROC : process (Ulpi_Clk, u_Setup_Buffer_Bytes_3_0_Latch, u_Setup_Buffer_Bytes_7_4_Latch)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Setup_Buffer_Bytes_3_0 <= (others => '0');
u_Setup_Buffer_Bytes_3_0_Loc <= (others => '0');
u_Setup_Buffer_Bytes_7_4 <= (others => '0');
else
if (u_Setup_Buffer_Bytes_3_0_Latch = '1') then
u_Setup_Buffer_Bytes_3_0 <= u_Fifo_Dout;
u_Setup_Buffer_Bytes_3_0_Loc <= u_Fifo_Dout;
elsif(u_Setup_Buffer_Bytes_7_4_Latch = '1') then
u_Setup_Buffer_Bytes_7_4 <= u_Fifo_Dout;
end if;
end if;
end if;
end process;
FIFO_BYTE_COUNT_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if ((reset = '0') or (u_Packet_Byte_Count_Rst = '0')) then
u_Packet_Byte_Count <= (others => '0');
else
if (u_Packet_Byte_CE = '1') then
u_Packet_Byte_Count <= std_logic_vector(unsigned(u_Packet_Byte_Count)+1);
end if;
end if;
end if;
end process;
TKEEP_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Input_Byte_Count_Array(0) <= (others => '0');
u_Input_Byte_Count_Array(1) <= (others => '0');
--index2 <= "0";
else
--index2(0) <= fifo_toggle_in;
if (u_End_Packet_Set = '1') then
u_Input_Byte_Count_Array (to_integer (unsigned (index2))) <= u_Input_Byte_Count;
end if;
end if;
end if;
end process;
BYTE_COUNT_ADD_PROC: process (Ulpi_Clk, u_Store_Packet_q, u_Store_Packet_qq, u_Store_Packet)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Input_Byte_Count_Complement <= (others => '0');
else
if (u_Input_Byte_CE_Aux = '1') then
u_Input_Byte_Count_Complement(to_integer(unsigned(index2))) <= '1';
elsif (u_Rx_Transfer_Done = '1') then
u_Input_Byte_Count_Complement(to_integer(unsigned(index1))) <= '0';
end if;
end if;
end if;
end process;
FIFO_BYTE_COUNT_INC_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
--index1 <= "0";
u_Input_Byte_Count_Aux <= (others => '0');
u_Input_Byte_Count_Aux1 <= (others => '0');
else
if (u_Input_Byte_Count_Array(index1_int) = "000000000000000") then
u_Input_Byte_Count_Aux <= (others => '0');
u_Input_Byte_Count_Aux1 <= (others => '0');
else
if (u_Input_Byte_Count_Complement(index1_int) = '0') then
u_Input_Byte_Count_Aux <= std_logic_vector(unsigned(u_Input_Byte_Count_Array(index1_int))-4);
u_Input_Byte_Count_Aux1 <= u_Input_Byte_Count_Array(index1_int);--std_logic_vector(unsigned(u_Input_Byte_Count_Array(index1_int)));
else
u_Input_Byte_Count_Aux <= u_Input_Byte_Count_Array(index1_int);--std_logic_vector(unsigned(tkeep_byte_count(index1_int)));
u_Input_Byte_Count_Aux1 <= std_logic_vector(unsigned(u_Input_Byte_Count_Array(index1_int))+4);
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
f4d4112474a028178c6cd152f5f45073
| 0.507916 | 3.415491 | false | false | false | false |
Digilent/vivado-library
|
ip/usb2device_v1_0/src/top.vhd
| 2 | 68,621 |
-------------------------------------------------------------------------------
--
-- File: top.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This is the top module of the USB_Device IP core. It is designed to work
-- with an ULPI PHY and, together, to implement the Electrical layer and the
-- Protocol layer of the USB 2.0 device. It exports an AXI Lite slave
-- interface to communicate with the processor. An integrated DMA engine is
-- suposed to connect to the system memory through an AXI4 interface.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top is
-- Port ( );
port (
S_AXI_ACLK : IN std_logic;
INTERRUPT : OUT STD_LOGIC;
--ULPI Interface
ulpi_clk : in STD_LOGIC;
ulpi_data : inout STD_LOGIC_VECTOR(7 downto 0);
ulpi_dir : in STD_LOGIC;
ulpi_nxt : in STD_LOGIC;
ulpi_stp : out STD_LOGIC;
led : out STD_LOGIC;
ulpi_resetn : out STD_LOGIC;
--AXI4 exported by the AXI DMA Controller
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
--AXI Lite Slave interface; Access to Control Registers
S_AXI_ARESETN : IN std_logic;
S_AXI_AWADDR : IN std_logic_vector(31 downto 0);
S_AXI_AWPROT : IN std_logic_vector(2 downto 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_WDATA : IN std_logic_vector(31 downto 0);
S_AXI_WSTRB : IN std_logic_vector(3 downto 0);
S_AXI_WVALID : IN std_logic;
S_AXI_BREADY : IN std_logic;
S_AXI_ARADDR : IN std_logic_vector(31 downto 0);
S_AXI_ARPROT : IN std_logic_vector(2 downto 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_RREADY : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BRESP : OUT std_logic_vector(1 downto 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RDATA : OUT std_logic_vector(31 downto 0);
S_AXI_RRESP : OUT std_logic_vector(1 downto 0);
S_AXI_RVALID : OUT std_logic
);
end top;
architecture Behavioral of top is
COMPONENT Control_Registers
PORT(
S_AXI_ACLK : IN std_logic;
S_AXI_ARESETN : IN std_logic;
S_AXI_AWADDR : IN std_logic_vector(31 downto 0);
S_AXI_AWPROT : IN std_logic_vector(2 downto 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_WDATA : IN std_logic_vector(31 downto 0);
S_AXI_WSTRB : IN std_logic_vector(3 downto 0);
S_AXI_WVALID : IN std_logic;
S_AXI_BREADY : IN std_logic;
S_AXI_ARADDR : IN std_logic_vector(31 downto 0);
S_AXI_ARPROT : IN std_logic_vector(2 downto 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_RREADY : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BRESP : OUT std_logic_vector(1 downto 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RDATA : OUT std_logic_vector(31 downto 0);
S_AXI_RRESP : OUT std_logic_vector(1 downto 0);
S_AXI_RVALID : OUT std_logic;
USBSCFG_rd : out std_logic_vector(31 downto 0);
USBCMD_rd : out std_logic_vector(31 downto 0);
USBCMD_SUTW_wr : in std_logic;
USBCMD_SUTW_wr_en : in std_logic;
USBCMD_ATDTW_wr : in std_logic;
USBCMD_ATDTW_wr_en : in std_logic;
USBSTS_rd : out std_logic_vector(31 downto 0);
USBSTS_wr_UI : in std_logic;
USBSTS_wr_NAKI : in std_logic;
USBSTS_wr_SLI : in std_logic;
USBSTS_wr_SRI : in std_logic;
USBSTS_wr_URI : in std_logic;
USBSTS_wr_PCI : in std_logic;
USBSTS_wr_en_NAK : in std_logic;
USBSTS_wr_en_SLI : in std_logic;
USBSTS_wr_en_SRI : in std_logic;
USBSTS_wr_en_URI : in std_logic;
USBSTS_wr_en_PCI : in std_logic;
USBSTS_wr_en_UI : in std_logic;
USBINTR_rd : out std_logic_vector(31 downto 0);
FRINDEX_rd : out std_logic_vector(31 downto 0);
FRINDEX_wr : in std_logic_vector(10 downto 0);
FRINDEX_wr_en : in std_logic;
a_DEVICEADDR_rd : out std_logic_vector(31 downto 0);
a_DEVICEADDR_IPush : out std_logic;
ENDPOINTLISTADDR_rd : out std_logic_vector(31 downto 0);
ENDPTNAK_rd : out std_logic_vector(31 downto 0);
ENDPTNAK_wr : in std_logic_vector(31 downto 0);
ENDPTNAK_wr_en : in std_logic;
ENDPTNAKEN_rd : out std_logic_vector(31 downto 0);
CONFIGFLAG_rd : out std_logic_vector(31 downto 0);
PORTSC1_rd : out std_logic_vector(31 downto 0);
PORTSC1_PSPD_Wr : in std_logic_vector(1 downto 0);
PORTSC1_PSPD_wr_en : in std_logic;
OTGSC_rd : out std_logic_vector(31 downto 0);
USBMODE_rd : out std_logic_vector(31 downto 0);
ENDPTSETUPSTAT_rd : out std_logic_vector(31 downto 0);
ENDPTSETUPSTAT_wr : in std_logic_vector(31 downto 0);
ENDPTSETUPSTAT_wr_en : in std_logic;
ENDPTPRIME_rd : out std_logic_vector(31 downto 0);
ENDPTPRIME_clear : in std_logic_vector(31 downto 0);
ENDPTPRIME_clear_en : in std_logic;
ENDPTPRIME_set : in std_logic_vector(31 downto 0);
ENDPTPRIME_set_en : in std_logic;
EMDPTFLUSH_rd : out std_logic_vector(31 downto 0);
EMDPTFLUSH_clear : in std_logic_vector(31 downto 0);
EMDPTFLUSH_clear_en : in std_logic;
EMDPTFLUSH_set : in std_logic_vector(31 downto 0);
EMDPTFLUSH_set_en : in std_logic;
ENDPTSTAT_wr : in std_logic_vector(31 downto 0);
ENDPTCOMPLETE_rd : out std_logic_vector(31 downto 0);
ENDPTCOMPLETE_wr : in std_logic_vector(31 downto 0);
ENDPTCOMPLETE_wr_en : in std_logic;
ENDPTCTRL0_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL1_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL2_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL3_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL4_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL5_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL6_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL7_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL8_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL9_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL10_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL11_rd : out std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT DMA_Transfer_Manager
PORT(
Axi_Resetn : IN STD_LOGIC;
Axi_Clk : IN STD_LOGIC;
ind_statte_axistream : out std_logic_vector(4 downto 0);
DEBUG_REG_DATA : OUT std_logic_vector(31 downto 0);
state_ind_dma : out STD_LOGIC_VECTOR(4 downto 0);
state_ind_arb : out std_logic_vector(5 downto 0);
a_M_Axi_Awaddr : out std_logic_vector(9 downto 0);
a_M_Axi_Awprot : out std_logic_vector(2 downto 0);
a_M_Axi_Awvalid : out std_logic;
a_M_Axi_Awready : in std_logic;
a_M_Axi_Wdata : out std_logic_vector(31 downto 0);
a_M_Axi_Wstrb : out std_logic_vector(3 downto 0);
a_M_Axi_Wvalid : out std_logic;
a_M_Axi_Wready : in std_logic;
a_M_Axi_Bresp : in std_logic_vector(1 downto 0);
a_M_Axi_Bvalid : in std_logic;
a_M_Axi_Bready : out std_logic;
a_M_Axi_Araddr : out std_logic_vector(9 downto 0);
a_M_Axi_Arprot : out std_logic_vector(2 downto 0);
a_M_Axi_Arvalid : out std_logic;
a_M_Axi_Arready : in std_logic;
a_M_Axi_Rdata : in std_logic_vector(31 downto 0);
a_M_Axi_Rresp : in std_logic_vector(1 downto 0);
a_M_Axi_Rvalid : in std_logic;
a_M_Axi_Rready : out std_logic;
a_S_Axis_MM2S_Tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_S_Axis_MM2S_Tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
a_S_Axis_MM2S_Tvalid : IN STD_LOGIC;
a_S_Axis_MM2S_Tready : OUT STD_LOGIC;
a_S_Axis_MM2S_Tlast : IN STD_LOGIC;
a_M_Axis_S2MM_Tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a_M_Axis_S2MM_Tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
a_M_Axis_S2MM_Tvalid : OUT STD_LOGIC;
a_M_Axis_S2MM_Tready : IN STD_LOGIC;
a_M_Axis_S2MM_Tlast : OUT STD_LOGIC;
RX_COMMAND_FIFO_RD_EN : OUT std_logic;
RX_COMMAND_FIFO_DOUT : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
RX_COMMAND_FIFO_EMPTY : IN std_logic;
RX_COMMAND_FIFO_VALID : IN std_logic;
a_Axis_MM2S_Mux_Ctrl : OUT STD_LOGIC;
a_Axis_S2MM_Mux_Ctrl : OUT STD_LOGIC;
a_Send_Zero_Length_Packet_Set : OUT STD_LOGIC_VECTOR(31 downto 0);
a_Send_Zero_Length_Packet_Set_En : OUT STD_LOGIC;
a_Send_Zero_Length_Packet_Ack_Rd : IN STD_LOGIC_VECTOR(31 downto 0);
a_Send_Zero_Length_Packet_Ack_Clear : OUT STD_LOGIC_VECTOR(31 downto 0);
a_Send_Zero_Length_Packet_Ack_Clear_En : OUT STD_LOGIC;
a_Arb_dQH_Setup_Buffer_Bytes_3_0_Wr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_Arb_dQH_Setup_Buffer_Bytes_7_4_Wr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_In_Packet_Complete_Rd : IN STD_LOGIC_VECTOR(31 downto 0);
a_In_Packet_Complete_Clear : OUT STD_LOGIC_VECTOR(31 downto 0);
a_In_Packet_Complete_Clear_En : OUT STD_LOGIC;
a_In_Token_Received_Rd : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_In_Token_Received_Clear : OUT STD_LOGIC_VECTOR(31 downto 0);
a_In_Token_Received_Clear_En : OUT STD_LOGIC;
a_Resend : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_Resend_Clear : OUT STD_LOGIC_VECTOR(31 downto 0);
a_Resend_Clear_En : OUT STD_LOGIC;
a_Cnt_Bytes_Sent : IN std_logic_vector(12 downto 0);
a_Cnt_Bytes_Sent_oValid : IN std_logic;
a_Pe_Endpt_Nr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
a_Arb_Endpt_Nr : out std_logic_vector(4 downto 0);
arb_tx_fifo_s_aresetn : OUT std_logic;
a_USBSTS_Wr_UI : OUT std_logic;
a_USBSTS_Wr_en_UI : OUT std_logic;
a_USBMODE_Rd : in std_logic_vector(31 downto 0);
a_USBCMD_SUTW_Wr : out std_logic;
a_USBCMD_SUTW_Wr_En : out std_logic;
a_USBCMD_ATDTW_Wr : out std_logic;
a_USBCMD_ATDTW_Wr_En : out std_logic;
a_EMDPTFLUSH_Rd : in std_logic_vector(31 downto 0);
a_EMDPTFLUSH_Set : out std_logic_vector(31 downto 0);
a_EMDPTFLUSH_Set_En : out std_logic;
a_ENDPTPRIME_Rd : in std_logic_vector(31 downto 0);
a_ENDPTPRIME_Clear : out std_logic_vector(31 downto 0);
a_ENDPTPRIME_Clear_En : out std_logic;
a_ENDPTPRIME_Set : out std_logic_vector(31 downto 0);
a_ENDPTPRIME_Set_En : out std_logic;
a_ENDPTSTAT_Wr : out std_logic_vector(31 downto 0);
a_ENDPTCOMPLETE_Wr : out std_logic_vector(31 downto 0);
a_ENDPTCOMPLETE_Wr_En : out std_logic;
a_ENDPTSETUPSTAT_Wr : out std_logic_vector(31 downto 0);
a_ENDPTSETUPSTAT_Wr_En : out std_logic;
a_Arb_ENDPTSETUP_RECEIVED_Rd : in std_logic_vector(31 downto 0);
a_Arb_ENDPTSETUP_RECEIVED_Clear : out std_logic_vector(31 downto 0);
a_Arb_ENDPTSETUP_RECEIVED_Clear_En : out std_logic;
a_Arb_ENDPTSETUP_RECEIVED_Ack : in std_logic;
a_ENDPOINTLISTADDR_Rd : in std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT axi_dma_0
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT FIFO
PORT(
resetn : IN STD_LOGIC;
rx_fifo_s_aresetn : IN std_logic;
rx_fifo_m_aclk : IN std_logic;
rx_fifo_s_aclk : IN std_logic;
rx_fifo_s_axis_tvalid : IN std_logic;
rx_fifo_s_axis_tdata : IN std_logic_vector(31 downto 0);
rx_fifo_s_axis_tkeep : IN std_logic_vector (3 downto 0);
rx_fifo_s_axis_tlast : IN std_logic;
rx_fifo_s_axis_tuser : IN std_logic_vector(3 downto 0);
rx_fifo_m_axis_tready : IN std_logic;
rx_fifo_s_axis_tready : OUT std_logic;
rx_fifo_m_axis_tvalid : OUT std_logic;
rx_fifo_m_axis_tdata : OUT std_logic_vector(31 downto 0);
rx_fifo_m_axis_tlast : OUT std_logic;
rx_fifo_m_axis_tuser : OUT std_logic_vector(3 downto 0);
rx_fifo_m_axis_tkeep : OUT std_logic_vector(3 downto 0);
rx_fifo_axis_overflow : OUT std_logic;
rx_fifo_axis_underflow : OUT std_logic
);
END COMPONENT;
COMPONENT Protocol_Engine
PORT(
axi_clk : IN std_logic;
Axi_ResetN : in STD_LOGIC;
Ulpi_Clk : in STD_LOGIC;
u_ResetN : in STD_LOGIC;
ulpi_reset : out STD_LOGIC;
u_Ulpi_Data : inout STD_LOGIC_VECTOR(7 downto 0);
u_Ulpi_Dir : in STD_LOGIC;
u_Ulpi_Nxt : in STD_LOGIC;
u_Ulpi_Stp : out STD_LOGIC;
led : out STD_LOGIC;
a_Arb_Endpt_Nr : in std_logic_vector(4 downto 0); --!!!!! bits need to be synchronised
Tx_Fifo_S_Aresetn : IN STD_LOGIC;
a_Tx_Fifo_S_Aclk : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tvalid : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tready : OUT STD_LOGIC;
a_Tx_Fifo_S_Axis_Tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_Tx_Fifo_S_Axis_Tlast : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tkeep : IN std_logic_vector(3 downto 0);
a_Tx_Fifo_S_Axis_Tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
tx_fifo_axis_overflow : OUT STD_LOGIC;
tx_fifo_axis_underflow : OUT STD_LOGIC;
u_Rx_Fifo_s_Aclk : OUT std_logic;
u_Rx_Fifo_s_Axis_Tready : IN std_logic;
u_Rx_Fifo_s_Axis_Tvalid : OUT std_logic;
u_Rx_Fifo_s_Axis_Tdata : OUT std_logic_vector(31 downto 0);
u_Rx_Fifo_s_Axis_Tkeep : OUT std_logic_vector (3 downto 0);
u_Rx_Fifo_s_Axis_Tlast : OUT std_logic;
u_Rx_Fifo_Axis_Overflow : IN std_logic;
u_Rx_Fifo_Axis_Underflow : IN std_logic;
u_Command_Fifo_Rd_En : IN std_logic;
u_Command_Fifo_Dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
u_Command_Fifo_Empty : OUT std_logic;
u_Command_Fifo_Valid : OUT std_logic;
u_USBADRA : in STD_LOGIC_VECTOR (7 downto 0);
u_Endp_Nr_Arb : IN STD_LOGIC_VECTOR(4 DOWNTO 0); --new
u_Endp_Nr_Arb_Ack : OUT std_logic;
u_Endp_Nr_Arb_Valid : IN std_logic;
u_Endp_Type : in STD_LOGIC_VECTOR(47 downto 0);
u_Endp_Stall : IN STD_LOGIC_VECTOR(23 downto 0);
u_USBCMD_RS : in std_logic;
-- endp_enable : IN STD_LOGIC(11 downto 0); --new
a_In_Packet_Complete_oData : OUT std_logic_vector(31 downto 0);
a_In_Packet_Complete_Set_En : OUT std_logic;
u_Send_Zero_Length_Packet_Rd : IN STD_LOGIC_VECTOR(31 downto 0);
a_Send_Zero_Length_Packet_Clear_oData : OUT STD_LOGIC_VECTOR(31 downto 0);
a_Send_Zero_Length_Packet_Clear_En : OUT STD_LOGIC;
a_Send_Zero_Length_Packet_Ack_oData : OUT STD_LOGIC_VECTOR(31 downto 0);
a_Send_Zero_Length_Packet_Ack_Set_En : OUT STD_LOGIC;
a_Cnt_Bytes_Sent_oData : out std_logic_vector(12 downto 0); --new
a_Cnt_Bytes_Sent_oValid : OUT std_logic;
a_In_Token_Received_oData : OUT std_logic_vector(31 downto 0); --new
a_In_Token_Received_Set_En : OUT std_logic; --new
a_Resend_oData : OUT STD_LOGIC_VECTOR(31 downto 0);
a_Resend_Wr_En : OUT std_logic;
a_Endpt_Nr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --new + 1 bit
u_Endp_Nr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
a_FRINDEX_oData : out std_logic_vector(10 downto 0);
a_FRINDEX_Wr_En : out std_logic;
a_Setup_Buffer_Bytes_3_0_oData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a_Setup_Buffer_Bytes_7_4_oData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a_PORTSC1_PSPD_oData : out std_logic_vector(1 downto 0);
a_PORTSC1_PSPD_Wr_En : out std_logic;
a_ENDPTNAK_oData : out std_logic_vector(31 downto 0);
a_ENDPTNAK_Wr_En : out std_logic;
a_ENDPTSETUP_RECEIVED_oData : out std_logic_vector(31 downto 0);
a_ENDPTSETUP_RECEIVED_Wr_En : out std_logic;
a_USBSTS_NAKI_oData : out std_logic;
a_USBSTS_NAKI_Wr_En : out std_logic;
a_USBSTS_SLI_oData : out std_logic;
a_USBSTS_SLI_Wr_En : out std_logic;
a_USBSTS_SRI_oData : out std_logic;
a_USBSTS_SRI_Wr_En : out std_logic;
a_USBSTS_URI_oData : out std_logic;
a_USBSTS_URI_Wr_En : out std_logic;
a_USBSTS_PCI_oData : out std_logic;
a_USBSTS_PCI_Wr_En : out std_logic;
state_ind : out STD_LOGIC_VECTOR(5 downto 0);
state_ind_pd : out STD_LOGIC_VECTOR(6 downto 0);
state_ind_hs : out STD_LOGIC_VECTOR(4 downto 0)
);
END COMPONENT;
COMPONENT ResetBridge
Generic (
kPolarity : std_logic);
PORT(
aRst : IN std_logic;
OutClk : IN std_logic;
oRst : OUT std_logic
);
END COMPONENT;
type ENDPOINTCTRL_REGISTERS is array (11 downto 0) of std_logic_vector(31 downto 0);
signal ENDPTCTRL : ENDPOINTCTRL_REGISTERS;
signal Ulpi_Clk_MMCM_Clkin : STD_LOGIC;
signal Ulpi_Clk_MMCM_Clkfbin : STD_LOGIC;
signal Ulpi_Clk_MMCM_Clkfbout : STD_LOGIC;
signal Ulpi_Clk_MMCM_Clkout0 : STD_LOGIC;
signal Ulpi_Clk_MMCM_Locked : STD_LOGIC;
signal Ulpi_ResetN_oRst : STD_LOGIC;
signal u_ResetN : STD_LOGIC;
signal u_MMCM_Rst : STD_LOGIC;
signal a_Axi_Reset : STD_LOGIC;
signal a_Axi_DMA_Tstvec : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_MM2S_Introut : STD_LOGIC;
signal a_S2MM_Introut : STD_LOGIC;
signal a_S2MM_Prmry_Reset_Out_N : STD_LOGIC;
signal a_MM2S_Prmry_Reset_Out_N : STD_LOGIC;
------------------------------------------------------------------------
signal a_Axis_MM2S_Mux_Ctrl, a_Axis_S2MM_Mux_Ctrl : STD_LOGIC;
signal a_Setup_Buffer_Bytes_3_0_Wr : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_Setup_Buffer_Bytes_7_4_Wr : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_Pe_Endpt_Nr, pe_endpt_nr_ulpi_clk : STD_LOGIC_VECTOR(4 DOWNTO 0);
signal a_DMA_S_Axis_S2MM_Tdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_DMA_S_Axis_S2MM_Tkeep : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal a_DMA_S_Axis_S2MM_Tvalid : STD_LOGIC;
signal a_DMA_S_Axis_S2MM_Tready : STD_LOGIC;
signal a_DMA_S_Axis_S2MM_Tlast : STD_LOGIC;
signal a_DMA_M_Axis_MM2S_Tdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_DMA_M_Axis_MM2S_Tkeep : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal a_DMA_M_Axis_MM2S_Tvalid : STD_LOGIC;
signal a_DMA_M_Axis_MM2S_Tready : STD_LOGIC;
signal a_DMA_M_Axis_MM2S_Tlast : STD_LOGIC;
signal a_FIFO_Axis_S2MM_Tdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_FIFO_Axis_S2MM_Tkeep : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal a_FIFO_Axis_S2MM_Tvalid : STD_LOGIC;
signal a_FIFO_Axis_S2MM_Tready : STD_LOGIC;
signal a_FIFO_Axis_S2MM_Tlast : STD_LOGIC;
signal a_FIFO_Axis_MM2S_Tdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_FIFO_Axis_MM2S_Tkeep : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal a_FIFO_Axis_MM2S_Tvalid : STD_LOGIC;
signal a_FIFO_Axis_MM2S_Tready : STD_LOGIC;
signal a_FIFO_Axis_MM2S_Tlast : STD_LOGIC;
signal a_Arb_Axis_S2MM_Tdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_Arb_Axis_S2MM_Tkeep : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal a_Arb_Axis_S2MM_Tvalid : STD_LOGIC;
signal a_Arb_Axis_S2MM_Tready : STD_LOGIC;
signal a_Arb_Axis_S2MM_Tlast : STD_LOGIC;
signal a_Arb_Axis_MM2S_Tdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_Arb_Axis_MM2S_Tkeep : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal a_Arb_Axis_MM2S_Tvalid : STD_LOGIC;
signal a_Arb_Axis_MM2S_Tready : STD_LOGIC;
signal a_Arb_Axis_MM2S_Tlast : STD_LOGIC;
------------------------------------------------------------------------
signal u_Rx_Fifo_s_Aclk : STD_LOGIC;
signal u_Rx_Fifo_s_Axis_Tready : STD_LOGIC;
signal u_Rx_Fifo_s_Axis_Tvalid : STD_LOGIC;
signal u_Rx_Fifo_s_Axis_Tdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal u_Rx_Fifo_s_Axis_Tkeep : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal u_Rx_Fifo_s_Axis_Tlast : STD_LOGIC;
signal u_Rx_Fifo_Axis_Overflow : std_logic;
signal u_Rx_Fifo_Axis_Underflow : std_logic;
signal tx_fifo_reset_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
signal u_Command_Fifo_Rd_En : std_logic;
signal u_Command_Fifo_Dout : STD_LOGIC_VECTOR(23 DOWNTO 0);
signal u_Command_Fifo_Empty : std_logic;
signal u_Command_Fifo_Valid : std_logic;
signal a_DMA_Axilite_Awaddr : std_logic_vector(9 downto 0);
signal a_DMA_Axilite_Awprot : std_logic_vector(2 downto 0);
signal a_DMA_Axilite_Awvalid : std_logic;
signal a_DMA_Axilite_Awready : std_logic;
signal a_DMA_Axilite_Wdata : std_logic_vector(31 downto 0);
signal a_DMA_Axilite_Wstrb : std_logic_vector(3 downto 0);
signal a_DMA_Axilite_Wvalid : std_logic;
signal a_DMA_Axilite_Wready : std_logic;
signal a_DMA_Axilite_Bresp : std_logic_vector(1 downto 0);
signal a_DMA_Axilite_Bvalid : std_logic;
signal a_DMA_Axilite_Bready : std_logic;
signal a_DMA_Axilite_Araddr : std_logic_vector(9 downto 0);
signal a_DMA_Axilite_Arprot : std_logic_vector(2 downto 0);
signal a_DMA_Axilite_Arvalid : std_logic;
signal a_DMA_Axilite_Arready : std_logic;
signal a_DMA_Axilite_Rdata : std_logic_vector(31 downto 0);
signal a_DMA_Axilite_Rresp : std_logic_vector(1 downto 0);
signal a_DMA_Axilite_Rvalid : std_logic;
signal a_DMA_Axilite_Ready : std_logic;
signal arb_tx_fifo_s_aresetn : std_logic;
signal a_SBUSCFG_Rd : std_logic_vector(31 downto 0);
signal a_USBCMD_Rd : std_logic_vector(31 downto 0);
signal a_USBCMD_SUTW_Wr : std_logic;
signal a_USBCMD_SUTW_Wr_En : std_logic;
signal a_USBCMD_ATDTW_Wr : std_logic;
signal a_USBCMD_ATDTW_Wr_En : std_logic;
signal a_USBSTS_Rd : std_logic_vector(31 downto 0);
signal a_USBSTS_Wr_NAKI : std_logic;
signal a_USBSTS_Wr_SLI : std_logic;
signal a_USBSTS_Wr_SRI : std_logic;
signal a_USBSTS_Wr_URI : std_logic;
signal a_USBSTS_Wr_PCI : std_logic;
signal a_USBSTS_Wr_En_NAK : std_logic;
signal a_USBSTS_Wr_En_SLI : std_logic;
signal a_USBSTS_Wr_En_SRI : std_logic;
signal a_USBSTS_Wr_En_URI : std_logic;
signal a_USBSTS_Wr_En_PCI : std_logic;
signal a_USBSTS_Wr_UI : std_logic;
signal a_USBSTS_Wr_en_UI : std_logic;
signal a_USBINTR_Rd : std_logic_vector(31 downto 0);
signal a_FRINDEX_Rd : std_logic_vector(31 downto 0);
signal a_FRINDEX_Wr : std_logic_vector(10 downto 0);
signal a_FRINDEX_Wr_En : std_logic;
signal a_DEVICEADDR_rd, u_DEVICEADDR_rd : std_logic_vector(31 downto 0);
signal a_DEVICEADDR_IPush : std_logic;
signal a_DEVICEADDR_IRdy : std_logic;
signal u_DEVICEADDR_oValid : std_logic;
signal a_ENDPOINTLISTADDR_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTNAK_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTNAK_Wr : std_logic_vector(31 downto 0);
signal a_ENDPTNAK_Wr_En : std_logic;
signal a_ENDPTNAKEN_Rd : std_logic_vector(31 downto 0);
signal a_CONFIGFLAG_Rd : std_logic_vector(31 downto 0);
signal a_PORTSC1_Rd : std_logic_vector(31 downto 0);
signal a_PORTSC1_PSPD_Wr : std_logic_vector(1 downto 0);
signal a_PORTSC1_PSPD_Wr_En : std_logic;
signal a_OTGSC_Rd : std_logic_vector(31 downto 0);
signal a_USBMODE_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTSETUPSTAT_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTSETUPSTAT_Wr : std_logic_vector(31 downto 0);
signal a_ENDPTSETUPSTAT_Wr_En : std_logic;
signal a_PE_ENDPTSETUP_RECEIVED_Wr : std_logic_vector(31 downto 0);
signal a_PE_ENDPTSETUP_RECEIVED_Wr_En : std_logic;
signal a_Arb_ENDPTSETUP_RECEIVED_Rd : std_logic_vector(31 downto 0);
signal a_Arb_ENDPTSETUP_RECEIVED_Clear : std_logic_vector(31 downto 0);
signal a_Arb_ENDPTSETUP_RECEIVED_Clear_En : std_logic;
signal a_Arb_ENDPTSETUP_RECEIVED_Ack : std_logic;
signal a_ENDPTPRIME_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTPRIME_Clear : std_logic_vector(31 downto 0);
signal a_ENDPTPRIME_Clear_En : std_logic;
signal a_ENDPTPRIME_Set : std_logic_vector(31 downto 0);
signal a_ENDPTPRIME_Set_En : std_logic;
signal a_EMDPTFLUSH_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTFLUSH_Clear, a_EMDPTFLUSH_Set : std_logic_vector(31 downto 0);
signal a_ENDPTFLUSH_Clear_En, a_EMDPTFLUSH_Set_En : std_logic;
signal a_ENDPTSTAT_Wr : std_logic_vector(31 downto 0);
signal a_ENDPTCOMPLETE_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCOMPLETE_Wr : std_logic_vector(31 downto 0);
signal a_ENDPTCOMPLETE_Wr_En : std_logic;
signal a_ENDPTCTRL0_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL1_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL2_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL3_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL4_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL5_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL6_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL7_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL8_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL9_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL10_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL11_Rd : std_logic_vector(31 downto 0);
signal a_USBCMD_RS, u_USBCMD_RS : std_logic;
signal a_In_Packet_Complete_Set : std_logic_vector(31 downto 0);
signal a_In_Packet_Complete_Set_En : std_logic;
signal a_In_Packet_Complete_Rd : std_logic_vector(31 downto 0);
signal a_In_Packet_Complete_Clear : STD_LOGIC_VECTOR(31 downto 0);
signal a_In_Packet_Complete_Clear_En : STD_LOGIC;
signal a_Send_Zero_Length_Packet_iData, u_Send_Zero_Length_Packet_oData, a_Send_Zero_Length_Packet_iData_q : STD_LOGIC_VECTOR(31 downto 0);
signal a_Send_Zero_Length_Packet_iPush, a_Send_Zero_Length_Packet_iRdy, u_Send_Zero_Length_Packet_oValid : std_logic;
signal a_Send_Zero_Length_Packet_Set : STD_LOGIC_VECTOR(31 downto 0);
signal a_Send_Zero_Length_Packet_Set_En : STD_LOGIC;
signal a_Send_Zero_Length_Packet_Clear : STD_LOGIC_VECTOR(31 downto 0);
signal a_Send_Zero_Length_Packet_Clear_En : STD_LOGIC;
signal a_Send_Zero_Length_Packet_Ack_Rd : STD_LOGIC_VECTOR(31 downto 0);
signal a_Send_Zero_Length_Packet_Ack_Clear : STD_LOGIC_VECTOR(31 downto 0);
signal a_Send_Zero_Length_Packet_Ack_Clear_En : STD_LOGIC;
signal a_Send_Zero_Length_Packet_Ack_Set : STD_LOGIC_VECTOR(31 downto 0);
signal a_Send_Zero_Length_Packet_Ack_Set_En : STD_LOGIC;
signal a_In_Token_Received_Set, a_In_Token_Received_Rd, a_In_Token_Received_Clear : STD_LOGIC_VECTOR(31 downto 0);
signal a_In_Token_Received_Set_En, a_In_Token_Received_Clear_En : STD_LOGIC;
signal a_Cnt_Bytes_Sent : std_logic_vector(12 downto 0);
signal a_Cnt_Bytes_Sent_oValid : STD_LOGIC;
signal a_Arb_Endpt_Nr : std_logic_vector(4 downto 0);
signal a_Endpt_Type_iData, u_Endpt_Type_oData, a_Endpt_Type_iData_q : std_logic_vector(47 downto 0);
signal a_Endpt_Type_iPush, a_Endpt_Type_iRdy, u_Endpt_Type_oValid : std_logic;
signal a_Endpt_Enable_iData, u_Endpt_Enable_oData, a_Endpt_Enable_iData_q : std_logic_vector(23 downto 0);
signal a_Endpt_Enable_iPush, a_Endpt_Enable_iRdy, u_Endpt_Enable_oValid : std_logic;
signal a_Endpt_Stall_iData, u_Endpt_Stall_oData, a_Endpt_Stall_iData_q : std_logic_vector(23 downto 0);
signal a_Endpt_Stall_iPush, a_Endpt_Stall_iRdy, u_Endpt_Stall_oValid : std_logic;
signal a_INTERRUPT_Loc : std_logic;
signal DEBUG_REG_DATA : std_logic_vector(31 downto 0);
signal a_USBSTS_UI_Change : std_logic;
signal a_Resend : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_Resend_Clear : STD_LOGIC_VECTOR(31 downto 0);
signal a_Resend_Clear_En : STD_LOGIC;
signal a_Resend_oData : STD_LOGIC_VECTOR(31 downto 0);
signal a_Resend_Wr_En : STD_LOGIC;
attribute clock_buffer_type : string;
attribute clock_buffer_type of ulpi_clk : signal is "none";
signal state_ind : STD_LOGIC_VECTOR(5 downto 0);
signal state_ind_pd : STD_LOGIC_VECTOR(6 downto 0);
signal state_ind_hs : STD_LOGIC_VECTOR(4 downto 0);
signal state_ind_dma : STD_LOGIC_VECTOR(4 downto 0);
signal state_ind_arb : std_logic_vector(5 downto 0);
signal ind_statte_axistream : std_logic_vector(4 downto 0);
-- attribute mark_debug : string;
-- attribute keep : string;
-- attribute mark_debug of u_USBCMD_RS : signal is "true";
-- attribute keep of u_USBCMD_RS : signal is "true";
begin
ulpi_resetn <= S_AXI_ARESETN;
a_Axi_Reset <= not S_AXI_ARESETN;
a_USBCMD_RS <= a_USBCMD_Rd(0);
led <= '0';
u_ResetN <= Ulpi_ResetN_oRst and (Ulpi_Clk_MMCM_Locked);
Inst_ResetBridge: ResetBridge
GENERIC MAP (
kPolarity => '0')
PORT MAP(
aRst => S_AXI_ARESETN,
OutClk => Ulpi_Clk_MMCM_Clkout0,
oRst => Ulpi_ResetN_oRst
);
u_MMCM_Rst <= '0';
-- This module implements the control registers required by USB Device IP.
-- Control Registers data is written/read over an AXI Lite interface
Inst_Control_Registers: Control_Registers PORT MAP(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWPROT => S_AXI_AWPROT,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARPROT => S_AXI_ARPROT,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
USBSCFG_rd => a_SBUSCFG_Rd,
USBCMD_rd => a_USBCMD_Rd,
USBCMD_SUTW_wr => a_USBCMD_SUTW_Wr,
USBCMD_SUTW_wr_en => a_USBCMD_SUTW_Wr_En,
USBCMD_ATDTW_wr => a_USBCMD_ATDTW_Wr,
USBCMD_ATDTW_wr_en => a_USBCMD_ATDTW_Wr_En,
USBSTS_rd => a_USBSTS_Rd,
USBSTS_wr_UI => a_USBSTS_Wr_UI,
USBSTS_wr_NAKI => a_USBSTS_Wr_NAKI,
USBSTS_wr_SLI => a_USBSTS_Wr_SLI,
USBSTS_wr_SRI => a_USBSTS_Wr_SRI,
USBSTS_wr_URI => a_USBSTS_Wr_URI,
USBSTS_wr_PCI => a_USBSTS_Wr_PCI,
USBSTS_wr_en_NAK => a_USBSTS_Wr_En_NAK,
USBSTS_wr_en_SLI => a_USBSTS_Wr_En_SLI,
USBSTS_wr_en_SRI => a_USBSTS_Wr_En_SRI,
USBSTS_wr_en_URI => a_USBSTS_Wr_En_URI,
USBSTS_wr_en_PCI => a_USBSTS_Wr_En_PCI,
USBSTS_wr_en_UI => a_USBSTS_Wr_en_UI,
USBINTR_rd => a_USBINTR_Rd,
FRINDEX_rd => a_FRINDEX_Rd,
FRINDEX_wr => a_FRINDEX_Wr,
FRINDEX_wr_en => a_FRINDEX_Wr_En,
a_DEVICEADDR_rd => a_DEVICEADDR_rd,
a_DEVICEADDR_IPush => a_DEVICEADDR_IPush,
ENDPOINTLISTADDR_rd => a_ENDPOINTLISTADDR_Rd,
ENDPTNAK_rd => a_ENDPTNAK_Rd,
ENDPTNAK_wr => a_ENDPTNAK_Wr,
ENDPTNAK_wr_en => a_ENDPTNAK_Wr_En,
ENDPTNAKEN_rd => a_ENDPTNAKEN_Rd,
CONFIGFLAG_rd => a_CONFIGFLAG_Rd,
PORTSC1_rd => a_PORTSC1_Rd,
PORTSC1_PSPD_wr => a_PORTSC1_PSPD_Wr,
PORTSC1_PSPD_wr_en => a_PORTSC1_PSPD_Wr_En,
OTGSC_rd => a_OTGSC_Rd,
USBMODE_rd => a_USBMODE_Rd,
ENDPTSETUPSTAT_rd => a_ENDPTSETUPSTAT_Rd,
ENDPTSETUPSTAT_wr => a_ENDPTSETUPSTAT_Wr,
ENDPTSETUPSTAT_wr_en => a_ENDPTSETUPSTAT_Wr_En,
ENDPTPRIME_rd => a_ENDPTPRIME_Rd,
ENDPTPRIME_clear => a_ENDPTPRIME_Clear,
ENDPTPRIME_clear_en => a_ENDPTPRIME_Clear_En,
ENDPTPRIME_set => a_ENDPTPRIME_Set,
ENDPTPRIME_set_en => a_ENDPTPRIME_Set_En,
EMDPTFLUSH_rd => a_EMDPTFLUSH_Rd,
EMDPTFLUSH_clear => a_ENDPTFLUSH_Clear,
EMDPTFLUSH_clear_en => a_ENDPTFLUSH_Clear_En,
EMDPTFLUSH_set => a_EMDPTFLUSH_Set,
EMDPTFLUSH_set_en => a_EMDPTFLUSH_Set_En,
ENDPTSTAT_wr => a_ENDPTSTAT_Wr,
ENDPTCOMPLETE_rd => a_ENDPTCOMPLETE_Rd,
ENDPTCOMPLETE_wr => a_ENDPTCOMPLETE_Wr,
ENDPTCOMPLETE_wr_en => a_ENDPTCOMPLETE_Wr_En,
ENDPTCTRL0_rd => a_ENDPTCTRL0_Rd,
ENDPTCTRL1_rd => a_ENDPTCTRL1_Rd,
ENDPTCTRL2_rd => a_ENDPTCTRL2_Rd,
ENDPTCTRL3_rd => a_ENDPTCTRL3_Rd,
ENDPTCTRL4_rd => a_ENDPTCTRL4_Rd,
ENDPTCTRL5_rd => a_ENDPTCTRL5_Rd,
ENDPTCTRL6_rd => a_ENDPTCTRL6_Rd,
ENDPTCTRL7_rd => a_ENDPTCTRL7_Rd,
ENDPTCTRL8_rd => a_ENDPTCTRL8_Rd,
ENDPTCTRL9_rd => a_ENDPTCTRL9_Rd,
ENDPTCTRL10_rd => a_ENDPTCTRL10_Rd,
ENDPTCTRL11_rd => a_ENDPTCTRL11_Rd
);
-- This module manages all transfers from main memory to local buffers through
-- DMA, both control data (Queue Heads, Transfer Descriptors)and packet data.
Inst_DMA_Transfer_Manager: DMA_Transfer_Manager PORT MAP(
Axi_Clk => S_AXI_ACLK,
Axi_Resetn => S_AXI_ARESETN,
ind_statte_axistream => ind_statte_axistream,
state_ind_dma => state_ind_dma,
state_ind_arb => state_ind_arb,
a_M_Axi_Awaddr => a_DMA_Axilite_Awaddr,
a_M_Axi_Awprot => a_DMA_Axilite_Awprot,
a_M_Axi_Awvalid => a_DMA_Axilite_Awvalid,
a_M_Axi_Awready => a_DMA_Axilite_Awready,
a_M_Axi_Wdata => a_DMA_Axilite_Wdata,
a_M_Axi_Wstrb => a_DMA_Axilite_Wstrb,
a_M_Axi_Wvalid => a_DMA_Axilite_Wvalid,
a_M_Axi_Wready => a_DMA_Axilite_Wready,
a_M_Axi_Bresp => a_DMA_Axilite_Bresp,
a_M_Axi_Bvalid => a_DMA_Axilite_Bvalid,
a_M_Axi_Bready => a_DMA_Axilite_Bready,
a_M_Axi_Araddr => a_DMA_Axilite_Araddr,
a_M_Axi_Arprot => a_DMA_Axilite_Arprot,
a_M_Axi_Arvalid => a_DMA_Axilite_Arvalid,
a_M_Axi_Arready => a_DMA_Axilite_Arready,
a_M_Axi_Rdata => a_DMA_Axilite_Rdata,
a_M_Axi_Rresp => a_DMA_Axilite_Rresp,
a_M_Axi_Rvalid => a_DMA_Axilite_Rvalid,
a_M_Axi_Rready => a_DMA_Axilite_Ready,
a_S_Axis_MM2S_Tdata => a_Arb_Axis_MM2S_Tdata,
a_S_Axis_MM2S_Tkeep => a_Arb_Axis_MM2S_Tkeep,
a_S_Axis_MM2S_Tvalid => a_Arb_Axis_MM2S_Tvalid,
a_S_Axis_MM2S_Tready => a_Arb_Axis_MM2S_Tready,
a_S_Axis_MM2S_Tlast => a_Arb_Axis_MM2S_Tlast,
a_M_Axis_S2MM_Tdata => a_Arb_Axis_S2MM_Tdata,
a_M_Axis_S2MM_Tkeep => a_Arb_Axis_S2MM_Tkeep,
a_M_Axis_S2MM_Tvalid => a_Arb_Axis_S2MM_Tvalid,
a_M_Axis_S2MM_Tready => a_Arb_Axis_S2MM_Tready,
a_M_Axis_S2MM_Tlast => a_Arb_Axis_S2MM_Tlast,
RX_COMMAND_FIFO_RD_EN => u_Command_Fifo_Rd_En,
RX_COMMAND_FIFO_DOUT => u_Command_Fifo_Dout,
RX_COMMAND_FIFO_EMPTY => u_Command_Fifo_Empty,
RX_COMMAND_FIFO_VALID => u_Command_Fifo_Valid,
a_Axis_MM2S_Mux_Ctrl => a_Axis_MM2S_Mux_Ctrl,
a_Axis_S2MM_Mux_Ctrl => a_Axis_S2MM_Mux_Ctrl,
a_Send_Zero_Length_Packet_Set => a_Send_Zero_Length_Packet_Set,
a_Send_Zero_Length_Packet_Set_En => a_Send_Zero_Length_Packet_Set_En,
a_Send_Zero_Length_Packet_Ack_Rd => a_Send_Zero_Length_Packet_Ack_Rd,
a_Send_Zero_Length_Packet_Ack_Clear => a_Send_Zero_Length_Packet_Ack_Clear,
a_Send_Zero_Length_Packet_Ack_Clear_En => a_Send_Zero_Length_Packet_Ack_Clear_En,
a_Arb_dQH_Setup_Buffer_Bytes_3_0_Wr => a_Setup_Buffer_Bytes_3_0_Wr,
a_Arb_dQH_Setup_Buffer_Bytes_7_4_Wr => a_Setup_Buffer_Bytes_7_4_Wr,
a_In_Packet_Complete_Rd => a_In_Packet_Complete_Rd,
a_In_Packet_Complete_Clear => a_In_Packet_Complete_Clear,
a_In_Packet_Complete_Clear_En => a_In_Packet_Complete_Clear_En,
a_In_Token_Received_Rd => a_In_Token_Received_Rd,
a_In_Token_Received_Clear => a_In_Token_Received_Clear,
a_In_Token_Received_Clear_En => a_In_Token_Received_Clear_En,
a_Cnt_Bytes_Sent => a_Cnt_Bytes_Sent,
a_Cnt_Bytes_Sent_oValid => a_Cnt_Bytes_Sent_oValid,
a_Pe_Endpt_Nr => a_Pe_Endpt_Nr,
a_Arb_Endpt_Nr => a_Arb_Endpt_Nr,
a_Resend => a_Resend,
a_Resend_Clear => a_Resend_Clear,
a_Resend_Clear_En => a_Resend_Clear_En,
arb_tx_fifo_s_aresetn => arb_tx_fifo_s_aresetn,
a_USBSTS_Wr_UI => a_USBSTS_Wr_UI,
a_USBSTS_Wr_en_UI => a_USBSTS_Wr_en_UI,
a_USBMODE_Rd => a_USBMODE_Rd,
a_USBCMD_SUTW_Wr => a_USBCMD_SUTW_Wr,
a_USBCMD_SUTW_Wr_En => a_USBCMD_SUTW_Wr_En,
a_USBCMD_ATDTW_Wr => a_USBCMD_ATDTW_Wr,
a_USBCMD_ATDTW_Wr_En => a_USBCMD_ATDTW_Wr_En,
a_EMDPTFLUSH_Rd => a_EMDPTFLUSH_Rd,
a_EMDPTFLUSH_Set => a_EMDPTFLUSH_Set,
a_EMDPTFLUSH_Set_En => a_EMDPTFLUSH_Set_En,
a_ENDPTPRIME_Rd => a_ENDPTPRIME_Rd,
a_ENDPTPRIME_Clear => a_ENDPTPRIME_Clear,
a_ENDPTPRIME_Clear_En => a_ENDPTPRIME_Clear_En,
a_ENDPTPRIME_Set => a_ENDPTPRIME_Set,
a_ENDPTPRIME_Set_En => a_ENDPTPRIME_Set_En,
a_ENDPTSTAT_Wr => a_ENDPTSTAT_Wr,
a_ENDPTCOMPLETE_Wr => a_ENDPTCOMPLETE_Wr,
a_ENDPTCOMPLETE_Wr_En => a_ENDPTCOMPLETE_Wr_En,
a_ENDPTSETUPSTAT_Wr => a_ENDPTSETUPSTAT_Wr,
a_ENDPTSETUPSTAT_Wr_En => a_ENDPTSETUPSTAT_Wr_En,
a_Arb_ENDPTSETUP_RECEIVED_Rd => a_Arb_ENDPTSETUP_RECEIVED_Rd,
a_Arb_ENDPTSETUP_RECEIVED_Clear => a_Arb_ENDPTSETUP_RECEIVED_Clear,
a_Arb_ENDPTSETUP_RECEIVED_Clear_En => a_Arb_ENDPTSETUP_RECEIVED_Clear_En,
a_Arb_ENDPTSETUP_RECEIVED_Ack => a_Arb_ENDPTSETUP_RECEIVED_Ack,
a_ENDPOINTLISTADDR_Rd => a_ENDPOINTLISTADDR_Rd
);
--AXI DMA Controller
your_instance_name: axi_dma_0 PORT MAP (
s_axi_lite_aclk => S_AXI_ACLK,
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
axi_resetn => S_AXI_ARESETN,
s_axi_lite_awvalid => a_DMA_Axilite_Awvalid,
s_axi_lite_awready => a_DMA_Axilite_Awready,
s_axi_lite_awaddr => a_DMA_Axilite_Awaddr,
s_axi_lite_wvalid => a_DMA_Axilite_Wvalid,
s_axi_lite_wready => a_DMA_Axilite_Wready,
s_axi_lite_wdata => a_DMA_Axilite_Wdata,
s_axi_lite_bresp => a_DMA_Axilite_Bresp,
s_axi_lite_bvalid => a_DMA_Axilite_Bvalid,
s_axi_lite_bready => a_DMA_Axilite_Bready,
s_axi_lite_arvalid => a_DMA_Axilite_Arvalid,
s_axi_lite_arready => a_DMA_Axilite_Arready,
s_axi_lite_araddr => a_DMA_Axilite_Araddr,
s_axi_lite_rvalid => a_DMA_Axilite_Rvalid,
s_axi_lite_rready => a_DMA_Axilite_Ready,
s_axi_lite_rdata => a_DMA_Axilite_Rdata,
s_axi_lite_rresp => a_DMA_Axilite_Rresp,
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => a_MM2S_Prmry_Reset_Out_N,
m_axis_mm2s_tdata => a_DMA_M_Axis_MM2S_Tdata,
m_axis_mm2s_tkeep => a_DMA_M_Axis_MM2S_Tkeep,
m_axis_mm2s_tvalid => a_DMA_M_Axis_MM2S_Tvalid,
m_axis_mm2s_tready => a_DMA_M_Axis_MM2S_Tready,
m_axis_mm2s_tlast => a_DMA_M_Axis_MM2S_Tlast,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => a_S2MM_Prmry_Reset_Out_N,
s_axis_s2mm_tdata => a_DMA_S_Axis_S2MM_Tdata,
s_axis_s2mm_tkeep => a_DMA_S_Axis_S2MM_Tkeep,
s_axis_s2mm_tvalid => a_DMA_S_Axis_S2MM_Tvalid,
s_axis_s2mm_tready => a_DMA_S_Axis_S2MM_Tready,
s_axis_s2mm_tlast => a_DMA_S_Axis_S2MM_Tlast,
mm2s_introut => a_MM2S_Introut,
s2mm_introut => a_S2MM_Introut,
axi_dma_tstvec => a_Axi_DMA_Tstvec
);
--Receive Packet FIFO
Inst_FIFO: FIFO PORT MAP(
resetn => S_AXI_ARESETN,
rx_fifo_s_aresetn => S_AXI_ARESETN,
rx_fifo_m_aclk => m_axi_mm2s_aclk,
rx_fifo_s_aclk => u_Rx_Fifo_s_Aclk ,
rx_fifo_s_axis_tvalid => u_Rx_Fifo_s_Axis_Tvalid,
rx_fifo_s_axis_tready => u_Rx_Fifo_s_Axis_Tready,
rx_fifo_s_axis_tdata => u_Rx_Fifo_s_Axis_Tdata,
rx_fifo_s_axis_tkeep => u_Rx_Fifo_s_Axis_Tkeep,
rx_fifo_s_axis_tlast => u_Rx_Fifo_s_Axis_Tlast,
rx_fifo_s_axis_tuser => "0000",
rx_fifo_m_axis_tvalid => a_FIFO_Axis_S2MM_Tvalid,
rx_fifo_m_axis_tready => a_FIFO_Axis_S2MM_Tready,
rx_fifo_m_axis_tdata => a_FIFO_Axis_S2MM_Tdata,
rx_fifo_m_axis_tlast => a_FIFO_Axis_S2MM_Tlast,
rx_fifo_m_axis_tkeep => a_FIFO_Axis_S2MM_Tkeep,
rx_fifo_m_axis_tuser => open,
rx_fifo_axis_overflow => u_Rx_Fifo_Axis_Overflow,
rx_fifo_axis_underflow => u_Rx_Fifo_Axis_Underflow
);
-- This module instantiates all the necessary modules to implement ULPI
-- communication, Speed negotiation , Reset and Suspend. Packet data is
-- sent/received over AXI Stream. Synchronization modules for registers
-- that corss the ULPI Clock domain to AXI clock domain is implemented
-- here
Inst_Protocol_Engine: Protocol_Engine PORT MAP(
Axi_Clk => S_AXI_ACLK,
axi_resetn => S_AXI_ARESETN,
Ulpi_Clk => Ulpi_Clk_MMCM_Clkout0,
u_ResetN => u_ResetN,
ulpi_reset => open,
u_Ulpi_Data => ulpi_data,
u_Ulpi_Dir => ulpi_dir,
u_Ulpi_Nxt => ulpi_nxt,
u_Ulpi_Stp => ulpi_stp,
led => open,
a_Arb_Endpt_Nr => a_Arb_Endpt_Nr,
Tx_Fifo_S_Aresetn => arb_tx_fifo_s_aresetn,
a_Tx_Fifo_S_Aclk => m_axi_s2mm_aclk,
a_Tx_Fifo_S_Axis_Tvalid => a_FIFO_Axis_MM2S_Tvalid,
a_Tx_Fifo_S_Axis_Tready => a_FIFO_Axis_MM2S_Tready,
a_Tx_Fifo_S_Axis_Tdata => a_FIFO_Axis_MM2S_Tdata,
a_Tx_Fifo_S_Axis_Tlast => a_FIFO_Axis_MM2S_Tlast,
a_Tx_Fifo_S_Axis_Tkeep => a_FIFO_Axis_MM2S_Tkeep,
a_Tx_Fifo_S_Axis_Tuser => "0000",
tx_fifo_axis_overflow => open,
tx_fifo_axis_underflow => open,
u_Rx_Fifo_s_Aclk => u_Rx_Fifo_s_Aclk ,
u_Rx_Fifo_s_Axis_Tready => u_Rx_Fifo_s_Axis_Tready,
u_Rx_Fifo_s_Axis_Tvalid => u_Rx_Fifo_s_Axis_Tvalid,
u_Rx_Fifo_s_Axis_Tdata => u_Rx_Fifo_s_Axis_Tdata,
u_Rx_Fifo_s_Axis_Tkeep => u_Rx_Fifo_s_Axis_Tkeep,
u_Rx_Fifo_s_Axis_Tlast => u_Rx_Fifo_s_Axis_Tlast,
u_Rx_Fifo_Axis_Overflow => u_Rx_Fifo_Axis_Overflow,
u_Rx_Fifo_Axis_Underflow => u_Rx_Fifo_Axis_Underflow,
u_Command_Fifo_Rd_En => u_Command_Fifo_Rd_En,
u_Command_Fifo_Dout => u_Command_Fifo_Dout,
u_Command_Fifo_Empty => u_Command_Fifo_Empty,
u_Command_Fifo_Valid => u_Command_Fifo_Valid,
a_FRINDEX_oData => a_FRINDEX_Wr,
a_FRINDEX_Wr_En => a_FRINDEX_Wr_En,
a_Setup_Buffer_Bytes_3_0_oData => a_Setup_Buffer_Bytes_3_0_Wr,
a_Setup_Buffer_Bytes_7_4_oData => a_Setup_Buffer_Bytes_7_4_Wr,
a_PORTSC1_PSPD_oData => a_PORTSC1_PSPD_Wr,
a_PORTSC1_PSPD_Wr_En => a_PORTSC1_PSPD_Wr_En,
a_ENDPTNAK_oData => a_ENDPTNAK_Wr,
a_ENDPTNAK_Wr_En => a_ENDPTNAK_Wr_En,
a_ENDPTSETUP_RECEIVED_oData => a_PE_ENDPTSETUP_RECEIVED_Wr,
a_ENDPTSETUP_RECEIVED_Wr_En => a_PE_ENDPTSETUP_RECEIVED_Wr_En,
a_USBSTS_NAKI_oData => a_USBSTS_Wr_NAKI,
a_USBSTS_SLI_oData => a_USBSTS_Wr_SLI,
a_USBSTS_SRI_oData => a_USBSTS_Wr_SRI,
a_USBSTS_URI_oData => a_USBSTS_Wr_URI,
a_USBSTS_PCI_oData => a_USBSTS_Wr_PCI,
a_USBSTS_NAKI_Wr_En => a_USBSTS_Wr_En_NAK,
a_USBSTS_SLI_Wr_En => a_USBSTS_Wr_En_SLI,
a_USBSTS_SRI_Wr_En => a_USBSTS_Wr_En_SRI,
a_USBSTS_URI_Wr_En => a_USBSTS_Wr_En_URI,
a_USBSTS_PCI_Wr_En => a_USBSTS_Wr_En_PCI,
u_Send_Zero_Length_Packet_Rd => u_Send_Zero_Length_Packet_oData,
a_Send_Zero_Length_Packet_Clear_oData => a_Send_Zero_Length_Packet_Clear,
a_Send_Zero_Length_Packet_Clear_En => a_Send_Zero_Length_Packet_Clear_En,
a_Send_Zero_Length_Packet_Ack_oData => a_Send_Zero_Length_Packet_Ack_Set,
a_Send_Zero_Length_Packet_Ack_Set_En => a_Send_Zero_Length_Packet_Ack_Set_En,
a_In_Packet_Complete_oData => a_In_Packet_Complete_Set,
a_In_Packet_Complete_Set_En => a_In_Packet_Complete_Set_En,
a_Cnt_Bytes_Sent_oData => a_Cnt_Bytes_Sent,
a_Cnt_Bytes_Sent_oValid => a_Cnt_Bytes_Sent_oValid,
a_In_Token_Received_oData => a_In_Token_Received_Set,
a_In_Token_Received_Set_En => a_In_Token_Received_Set_En,
a_Resend_oData => a_Resend_oData,
a_Resend_Wr_En => a_Resend_Wr_En,
a_Endpt_Nr => a_Pe_Endpt_Nr,
u_Endp_Nr => pe_endpt_nr_ulpi_clk,
u_Endp_Nr_Arb => "00000",
u_Endp_Nr_Arb_Ack => open,
u_Endp_Nr_Arb_Valid => '0',
u_USBCMD_RS => u_USBCMD_RS,
u_Endp_Type => u_Endpt_Type_oData,
u_Endp_Stall => u_Endpt_Stall_oData,
u_USBADRA => u_DEVICEADDR_rd(31 downto 24),
-- endp_enable => pe_endpt_enable,
state_ind => state_ind,
state_ind_hs => state_ind_hs,
state_ind_pd => state_ind_pd
);
-- ULPI clock deskew
Ulpi_Clk_MMCM_Clkin <= ulpi_clk;
MMCME2_BASE_inst: MMCME2_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- Jitter programming (OPTIMIZED, HIGH, LOW)
CLKFBOUT_MULT_F => 10.0, -- Multiply value for all CLKOUT (2.000-64.000).
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB (-360.000-360.000).
CLKIN1_PERIOD => 0.0, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
-- CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT6_DIVIDE => 1,
CLKOUT0_DIVIDE_F => 10.0, -- Divide amount for CLKOUT0 (1.000-128.000).
-- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
CLKOUT6_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
CLKOUT6_PHASE => 0.0,
CLKOUT4_CASCADE => FALSE, -- Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
DIVCLK_DIVIDE => 1, -- Master division value (1-106)
REF_JITTER1 => 0.0, -- Reference input jitter in UI (0.000-0.999).
STARTUP_WAIT => FALSE -- Delays DONE until MMCM is locked (FALSE, TRUE)
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => Ulpi_Clk_MMCM_Clkout0, -- 1-bit output: CLKOUT0
CLKOUT0B => open, -- 1-bit output: Inverted CLKOUT0
CLKOUT1 => open, -- 1-bit output: CLKOUT1
CLKOUT1B => open, -- 1-bit output: Inverted CLKOUT1
CLKOUT2 => open, -- 1-bit output: CLKOUT2
CLKOUT2B => open, -- 1-bit output: Inverted CLKOUT2
CLKOUT3 => open, -- 1-bit output: CLKOUT3
CLKOUT3B => open, -- 1-bit output: Inverted CLKOUT3
CLKOUT4 => open, -- 1-bit output: CLKOUT4
CLKOUT5 => open, -- 1-bit output: CLKOUT5
CLKOUT6 => open, -- 1-bit output: CLKOUT6
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => Ulpi_Clk_MMCM_Clkfbout, -- 1-bit output: Feedback clock
CLKFBOUTB => open, -- 1-bit output: Inverted CLKFBOUT
-- Status Ports: 1-bit (each) output: MMCM status ports
LOCKED => Ulpi_Clk_MMCM_Locked, -- 1-bit output: LOCK
-- Clock Inputs: 1-bit (each) input: Clock input
CLKIN1 => Ulpi_Clk_MMCM_Clkin, -- 1-bit input: Clock
-- Control Ports: 1-bit (each) input: MMCM control ports
PWRDWN => '0', -- 1-bit input: Power-down
RST => u_MMCM_Rst, -- 1-bit input: Reset
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => Ulpi_Clk_MMCM_Clkfbin -- 1-bit input: Feedback clock
);
BUFG_inst : BUFG
port map (
O => Ulpi_Clk_MMCM_Clkfbin, -- 1-bit output: Clock output
I => Ulpi_Clk_MMCM_Clkfbout -- 1-bit input: Clock input
);
--DMA needs to write/read to/from both packet FIFOs and context memory; "MUX" implemented below
a_DMA_S_Axis_S2MM_Tdata <= a_Arb_Axis_S2MM_Tdata when (a_Axis_S2MM_Mux_Ctrl = '1') else
a_FIFO_Axis_S2MM_Tdata;
a_DMA_S_Axis_S2MM_Tkeep <= a_Arb_Axis_S2MM_Tkeep when (a_Axis_S2MM_Mux_Ctrl = '1') else
a_FIFO_Axis_S2MM_Tkeep;
a_DMA_S_Axis_S2MM_Tvalid <= a_Arb_Axis_S2MM_Tvalid when (a_Axis_S2MM_Mux_Ctrl = '1') else
a_FIFO_Axis_S2MM_Tvalid;
a_Arb_Axis_S2MM_Tready <= a_DMA_S_Axis_S2MM_Tready when (a_Axis_S2MM_Mux_Ctrl = '1') else
'0';
a_FIFO_Axis_S2MM_Tready <= a_DMA_S_Axis_S2MM_Tready when (a_Axis_S2MM_Mux_Ctrl = '0') else
'0';
a_DMA_S_Axis_S2MM_Tlast <= a_Arb_Axis_S2MM_Tlast when (a_Axis_S2MM_Mux_Ctrl = '1') else
a_FIFO_Axis_S2MM_Tlast;
a_Arb_Axis_MM2S_Tdata <= a_DMA_M_Axis_MM2S_Tdata when (a_Axis_MM2S_Mux_Ctrl = '1') else (others => '0');
a_FIFO_Axis_MM2S_Tdata <= a_DMA_M_Axis_MM2S_Tdata when (a_Axis_MM2S_Mux_Ctrl = '0') else (others => '0');
a_Arb_Axis_MM2S_Tkeep <= a_DMA_M_Axis_MM2S_Tkeep when (a_Axis_MM2S_Mux_Ctrl = '1') else (others => '0');
a_FIFO_Axis_MM2S_Tkeep <= a_DMA_M_Axis_MM2S_Tkeep when (a_Axis_MM2S_Mux_Ctrl = '0') else (others => '0');
a_Arb_Axis_MM2S_Tvalid <= a_DMA_M_Axis_MM2S_Tvalid when (a_Axis_MM2S_Mux_Ctrl = '1') else '0';
a_FIFO_Axis_MM2S_Tvalid <= a_DMA_M_Axis_MM2S_Tvalid when (a_Axis_MM2S_Mux_Ctrl = '0') else '0';
a_DMA_M_Axis_MM2S_Tready <= a_Arb_Axis_MM2S_Tready when (a_Axis_MM2S_Mux_Ctrl = '1') else
a_FIFO_Axis_MM2S_Tready;
a_Arb_Axis_MM2S_Tlast <= a_DMA_M_Axis_MM2S_Tlast when (a_Axis_MM2S_Mux_Ctrl = '1') else '0';
a_FIFO_Axis_MM2S_Tlast <= a_DMA_M_Axis_MM2S_Tlast when (a_Axis_MM2S_Mux_Ctrl = '0') else '0';
--------------------------------------------------------------------------------------------------
ENDPTCTRL(0) <= a_ENDPTCTRL0_Rd;
ENDPTCTRL(1) <= a_ENDPTCTRL1_Rd;
ENDPTCTRL(2) <= a_ENDPTCTRL2_Rd;
ENDPTCTRL(3) <= a_ENDPTCTRL3_Rd;
ENDPTCTRL(4) <= a_ENDPTCTRL4_Rd;
ENDPTCTRL(5) <= a_ENDPTCTRL5_Rd;
ENDPTCTRL(6) <= a_ENDPTCTRL6_Rd;
ENDPTCTRL(7) <= a_ENDPTCTRL7_Rd;
ENDPTCTRL(8) <= a_ENDPTCTRL8_Rd;
ENDPTCTRL(9) <= a_ENDPTCTRL9_Rd;
ENDPTCTRL(10) <= a_ENDPTCTRL10_Rd;
ENDPTCTRL(11) <= a_ENDPTCTRL11_Rd;
ENDP_TYPE_PROC: process (ENDPTCTRL)
begin
for endpt_type_index in 0 to 11 loop
a_Endpt_Type_iData((endpt_type_index*4+3) downto endpt_type_index*4) <= ENDPTCTRL(endpt_type_index)(19 downto 18) & ENDPTCTRL(endpt_type_index)(3 downto 2);
a_Endpt_Stall_iData((endpt_type_index*2+1) downto endpt_type_index*2) <= ENDPTCTRL(endpt_type_index)(16) & ENDPTCTRL(endpt_type_index)(0);
a_Endpt_Enable_iData((endpt_type_index*2+1) downto endpt_type_index*2) <= ENDPTCTRL(endpt_type_index)(23) & ENDPTCTRL(endpt_type_index)(7);
end loop;
end process;
TX_FIFO_RESET_PROC: process (ENDPTCTRL)
begin
for tx_fifo_reset_index in 0 to 11 loop
tx_fifo_reset_vector(tx_fifo_reset_index) <= (not(a_EMDPTFLUSH_Rd(tx_fifo_reset_index+16)) and arb_tx_fifo_s_aresetn);
end loop;
end process;
--Synchronization modules for data that crosses the AXI clock domain to ULPI clock domain
ENDPT_TYPE_IPUSH_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_Endpt_Type_iData_q <= (others => '0');
a_Endpt_Type_iPush <= '0';
else
a_Endpt_Type_iData_q <= a_Endpt_Type_iData;
if(a_Endpt_Type_iData_q /= a_Endpt_Type_iData and a_Endpt_Type_iRdy = '1') then
a_Endpt_Type_iPush <= '1';
else
a_Endpt_Type_iPush <= '0';
end if;
end if;
end if;
end process;
ENDPT_STALL_IPUSH_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_Endpt_Stall_iData_q <= (others => '0');
a_Endpt_Stall_iPush <= '0';
else
a_Endpt_Stall_iData_q <= a_Endpt_Stall_iData;
if(a_Endpt_Stall_iData_q /= a_Endpt_Stall_iData and a_Endpt_Stall_iRdy = '1') then
a_Endpt_Stall_iPush <= '1';
else
a_Endpt_Stall_iPush <= '0';
end if;
end if;
end if;
end process;
ENDPT_ENABLE_IPUSH_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_Endpt_Enable_iData_q <= (others => '0');
a_Endpt_Enable_iPush <= '0';
else
a_Endpt_Enable_iData_q <= a_Endpt_Enable_iData;
if(a_Endpt_Enable_iData_q /= a_Endpt_Enable_iData and a_Endpt_Enable_iRdy = '1') then
a_Endpt_Enable_iPush <= '1';
else
a_Endpt_Enable_iPush <= '0';
end if;
end if;
end if;
end process;
ZERO_LENGTH_PUSH_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_Send_Zero_Length_Packet_iData_q <= (others => '0');
a_Send_Zero_Length_Packet_iPush <= '0';
else
a_Send_Zero_Length_Packet_iData_q <= a_Send_Zero_Length_Packet_iData;
if(a_Send_Zero_Length_Packet_iData_q /= a_Send_Zero_Length_Packet_iData and a_Send_Zero_Length_Packet_iRdy = '1') then
a_Send_Zero_Length_Packet_iPush <= '1';
else
a_Send_Zero_Length_Packet_iPush <= '0';
end if;
end if;
end if;
end process;
SyncAsyncPushT_USBCMD_RS: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aReset => a_Axi_Reset,
aIn => a_USBCMD_RS,
OutClk => Ulpi_Clk_MMCM_Clkout0,
oOut => u_USBCMD_RS
);
Inst_HandshakeData_endpt_type: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 48)
PORT MAP(
InClk => S_AXI_ACLK,
OutClk => Ulpi_Clk_MMCM_Clkout0,
iData => a_Endpt_Type_iData,
oData => u_Endpt_Type_oData,
iPush => a_Endpt_Type_iPush,
iRdy => a_Endpt_Type_iRdy,
oAck => u_Endpt_Type_oValid,
oValid => u_Endpt_Type_oValid,
aReset => a_Axi_Reset
);
Inst_HandshakeData_endpt_stall: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 24)
PORT MAP(
InClk => S_AXI_ACLK,
OutClk => Ulpi_Clk_MMCM_Clkout0,
iData => a_Endpt_Stall_iData,
oData => u_Endpt_Stall_oData,
iPush => a_Endpt_Stall_iPush,
iRdy => a_Endpt_Stall_iRdy,
oAck => u_Endpt_Stall_oValid,
oValid => u_Endpt_Stall_oValid,
aReset => a_Axi_Reset
);
Inst_HandshakeData_endpt_enable: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 24)
PORT MAP(
InClk => S_AXI_ACLK,
OutClk => Ulpi_Clk_MMCM_Clkout0,
iData => a_Endpt_Enable_iData,
oData => u_Endpt_Enable_oData,
iPush => a_Endpt_Enable_iPush,
iRdy => a_Endpt_Enable_iRdy,
oAck => u_Endpt_Enable_oValid,
oValid => u_Endpt_Enable_oValid,
aReset => a_Axi_Reset
);
Inst_HandshakeData_send_zero_length_packet: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => S_AXI_ACLK,
OutClk => Ulpi_Clk_MMCM_Clkout0,
iData => a_Send_Zero_Length_Packet_iData,
oData => u_Send_Zero_Length_Packet_oData,
iPush => a_Send_Zero_Length_Packet_iPush,
iRdy => a_Send_Zero_Length_Packet_iRdy,
oAck => u_Send_Zero_Length_Packet_oValid,
oValid => u_Send_Zero_Length_Packet_oValid,
aReset => a_Axi_Reset
);
Inst_HandshakeData_DEVICEADDR: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => S_AXI_ACLK,
OutClk => Ulpi_Clk_MMCM_Clkout0,
iData => a_DEVICEADDR_rd,
oData => u_DEVICEADDR_rd,
iPush => a_DEVICEADDR_IPush,
iRdy => a_DEVICEADDR_IRdy,
oAck => u_DEVICEADDR_oValid,
oValid => u_DEVICEADDR_oValid,
aReset => a_Axi_Reset
);
--Interrupts
a_USBSTS_UI_Change <= a_ENDPTSETUPSTAT_Wr_En or a_ENDPTCOMPLETE_Wr_En;
INTERRUPT_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_INTERRUPT_Loc <= '0';
else
if ((a_USBINTR_Rd and a_USBSTS_Rd) /= "00000000000000000000000000000000") then
if (a_USBSTS_UI_Change = '1') then
a_INTERRUPT_Loc <= '0';
else
a_INTERRUPT_Loc <= '1';
end if;
else
a_INTERRUPT_Loc <= '0';
end if;
end if;
end if;
end process;
INTERRUPT <= a_INTERRUPT_Loc;
--Status Registers, Hanshake between Protocol_Engine and DMA_Transfer_Manager
ENDPT_FLUSH_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_ENDPTFLUSH_Clear <= (others => '0');
a_ENDPTFLUSH_Clear_En <= '0';
else
if(a_EMDPTFLUSH_Rd /= "00000000000000000000000000000000") then
a_ENDPTFLUSH_Clear_En <= '1';
a_ENDPTFLUSH_Clear <= (others => '0');
else
a_ENDPTFLUSH_Clear_En <= '0';
end if;
end if;
end if;
end process;
ENDPTSETUP_RECEIVED_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_Arb_ENDPTSETUP_RECEIVED_Rd <= (others => '0');
a_Arb_ENDPTSETUP_RECEIVED_Ack <= '0';
else
if (a_PE_ENDPTSETUP_RECEIVED_Wr_En = '1') then
a_Arb_ENDPTSETUP_RECEIVED_Rd <= a_PE_ENDPTSETUP_RECEIVED_Wr;
a_Arb_ENDPTSETUP_RECEIVED_Ack <= '0';
elsif(a_Arb_ENDPTSETUP_RECEIVED_Clear_En = '1') then
a_Arb_ENDPTSETUP_RECEIVED_Rd <= a_Arb_ENDPTSETUP_RECEIVED_Rd and a_Arb_ENDPTSETUP_RECEIVED_Clear;
a_Arb_ENDPTSETUP_RECEIVED_Ack <= '1';
else
a_Arb_ENDPTSETUP_RECEIVED_Ack <= '0';
end if;
end if;
end if;
end process;
PACKET_IN_COMPLETE_RD_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_In_Packet_Complete_Rd <= (others => '0');
else
if (a_In_Packet_Complete_Set_En = '1') then
a_In_Packet_Complete_Rd <= a_In_Packet_Complete_Rd or a_In_Packet_Complete_Set;
elsif(a_In_Packet_Complete_Clear_En = '1') then
a_In_Packet_Complete_Rd <= a_In_Packet_Complete_Rd and a_In_Packet_Complete_Clear;
end if;
end if;
end if;
end process;
SEND_ZERO_LENGTH_RD_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_Send_Zero_Length_Packet_iData <= (others => '0');
else
if (a_Send_Zero_Length_Packet_Set_En = '1') then
a_Send_Zero_Length_Packet_iData <= a_Send_Zero_Length_Packet_iData or a_Send_Zero_Length_Packet_Set;
elsif(a_Send_Zero_Length_Packet_Clear_En = '1') then
a_Send_Zero_Length_Packet_iData <= a_Send_Zero_Length_Packet_iData and a_Send_Zero_Length_Packet_Clear;
end if;
end if;
end if;
end process;
SEND_ZERO_LENGTH_ACK_RD_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_Send_Zero_Length_Packet_Ack_Rd <= (others => '0');
else
if (a_Send_Zero_Length_Packet_Ack_Set_En = '1') then
a_Send_Zero_Length_Packet_Ack_Rd <= a_Send_Zero_Length_Packet_Ack_Rd or a_Send_Zero_Length_Packet_Ack_Set;
elsif(a_Send_Zero_Length_Packet_Ack_Clear_En = '1') then
a_Send_Zero_Length_Packet_Ack_Rd <= a_Send_Zero_Length_Packet_Ack_Rd and a_Send_Zero_Length_Packet_Ack_Clear;
end if;
end if;
end if;
end process;
RESEND_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_Resend <= (others => '0');
else
if (a_Resend_Wr_En = '1') then
a_Resend <= a_Resend or a_Resend_oData;
elsif(a_Resend_Clear_En = '1') then
a_Resend <= a_Resend and a_Resend_Clear;
end if;
end if;
end if;
end process;
PE_IN_TOKEN_RECEIVED_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_In_Token_Received_Rd <= (others => '0');
else
if (a_In_Token_Received_Set_En = '1') then
a_In_Token_Received_Rd <= a_In_Token_Received_Rd or a_In_Token_Received_Set;
elsif(a_In_Token_Received_Clear_En = '1') then
a_In_Token_Received_Rd <= a_In_Token_Received_Rd and a_In_Token_Received_Clear;
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
53bb32268fc5643c5ca927b0c8700080
| 0.626718 | 2.929392 | false | false | false | false |
EJDomi/pixel-dtb-firmware-readout-chain-master
|
dtb/lpm_decode0.vhd
| 1 | 5,609 |
-- megafunction wizard: %LPM_DECODE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_decode
-- ============================================================
-- File Name: lpm_decode0.vhd
-- Megafunction Name(s):
-- lpm_decode
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_decode0 IS
PORT
(
data : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
eq0 : OUT STD_LOGIC ;
eq1 : OUT STD_LOGIC ;
eq2 : OUT STD_LOGIC ;
eq3 : OUT STD_LOGIC ;
eq4 : OUT STD_LOGIC ;
eq5 : OUT STD_LOGIC ;
eq6 : OUT STD_LOGIC ;
eq7 : OUT STD_LOGIC
);
END lpm_decode0;
ARCHITECTURE SYN OF lpm_decode0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC ;
SIGNAL sub_wire8 : STD_LOGIC ;
COMPONENT lpm_decode
GENERIC (
lpm_decodes : NATURAL;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
eq : OUT STD_LOGIC_VECTOR (lpm_decodes-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire8 <= sub_wire0(7);
sub_wire7 <= sub_wire0(6);
sub_wire6 <= sub_wire0(5);
sub_wire5 <= sub_wire0(4);
sub_wire4 <= sub_wire0(3);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
eq0 <= sub_wire1;
eq1 <= sub_wire2;
eq2 <= sub_wire3;
eq3 <= sub_wire4;
eq4 <= sub_wire5;
eq5 <= sub_wire6;
eq6 <= sub_wire7;
eq7 <= sub_wire8;
lpm_decode_component : lpm_decode
GENERIC MAP (
lpm_decodes => 8,
lpm_type => "LPM_DECODE",
lpm_width => 3
)
PORT MAP (
data => data,
eq => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: BaseDec NUMERIC "1"
-- Retrieval info: PRIVATE: EnableInput NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: eq0 NUMERIC "1"
-- Retrieval info: PRIVATE: eq1 NUMERIC "1"
-- Retrieval info: PRIVATE: eq2 NUMERIC "1"
-- Retrieval info: PRIVATE: eq3 NUMERIC "1"
-- Retrieval info: PRIVATE: eq4 NUMERIC "1"
-- Retrieval info: PRIVATE: eq5 NUMERIC "1"
-- Retrieval info: PRIVATE: eq6 NUMERIC "1"
-- Retrieval info: PRIVATE: eq7 NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "3"
-- Retrieval info: CONSTANT: LPM_DECODES NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DECODE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "3"
-- Retrieval info: USED_PORT: @eq 0 0 LPM_DECODES 0 OUTPUT NODEFVAL @eq[LPM_DECODES-1..0]
-- Retrieval info: USED_PORT: data 0 0 3 0 INPUT NODEFVAL data[2..0]
-- Retrieval info: USED_PORT: eq0 0 0 0 0 OUTPUT NODEFVAL eq0
-- Retrieval info: USED_PORT: eq1 0 0 0 0 OUTPUT NODEFVAL eq1
-- Retrieval info: USED_PORT: eq2 0 0 0 0 OUTPUT NODEFVAL eq2
-- Retrieval info: USED_PORT: eq3 0 0 0 0 OUTPUT NODEFVAL eq3
-- Retrieval info: USED_PORT: eq4 0 0 0 0 OUTPUT NODEFVAL eq4
-- Retrieval info: USED_PORT: eq5 0 0 0 0 OUTPUT NODEFVAL eq5
-- Retrieval info: USED_PORT: eq6 0 0 0 0 OUTPUT NODEFVAL eq6
-- Retrieval info: USED_PORT: eq7 0 0 0 0 OUTPUT NODEFVAL eq7
-- Retrieval info: CONNECT: @data 0 0 3 0 data 0 0 3 0
-- Retrieval info: CONNECT: eq0 0 0 0 0 @eq 0 0 1 0
-- Retrieval info: CONNECT: eq1 0 0 0 0 @eq 0 0 1 1
-- Retrieval info: CONNECT: eq2 0 0 0 0 @eq 0 0 1 2
-- Retrieval info: CONNECT: eq3 0 0 0 0 @eq 0 0 1 3
-- Retrieval info: CONNECT: eq4 0 0 0 0 @eq 0 0 1 4
-- Retrieval info: CONNECT: eq5 0 0 0 0 @eq 0 0 1 5
-- Retrieval info: CONNECT: eq6 0 0 0 0 @eq 0 0 1 6
-- Retrieval info: CONNECT: eq7 0 0 0 0 @eq 0 0 1 7
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_decode0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_decode0.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_decode0.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_decode0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_decode0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
unlicense
|
5ecddc48353e24a3540dc8382be85eda
| 0.64343 | 3.242197 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_gamma_correction_1_0/hdl/vhdl/Loop_loop_height_pro.vhd
| 1 | 70,872 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Loop_loop_height_pro is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_rows_assign_cast_loc_dout : IN STD_LOGIC_VECTOR (11 downto 0);
p_rows_assign_cast_loc_empty_n : IN STD_LOGIC;
p_rows_assign_cast_loc_read : OUT STD_LOGIC;
p_cols_assign_cast_loc_dout : IN STD_LOGIC_VECTOR (11 downto 0);
p_cols_assign_cast_loc_empty_n : IN STD_LOGIC;
p_cols_assign_cast_loc_read : OUT STD_LOGIC;
img3_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img3_data_stream_0_V_full_n : IN STD_LOGIC;
img3_data_stream_0_V_write : OUT STD_LOGIC;
img3_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img3_data_stream_1_V_full_n : IN STD_LOGIC;
img3_data_stream_1_V_write : OUT STD_LOGIC;
img3_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img3_data_stream_2_V_full_n : IN STD_LOGIC;
img3_data_stream_2_V_write : OUT STD_LOGIC;
gamma_dout : IN STD_LOGIC_VECTOR (7 downto 0);
gamma_empty_n : IN STD_LOGIC;
gamma_read : OUT STD_LOGIC;
img0_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img0_data_stream_0_V_empty_n : IN STD_LOGIC;
img0_data_stream_0_V_read : OUT STD_LOGIC;
img0_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img0_data_stream_1_V_empty_n : IN STD_LOGIC;
img0_data_stream_1_V_read : OUT STD_LOGIC;
img0_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img0_data_stream_2_V_empty_n : IN STD_LOGIC;
img0_data_stream_2_V_read : OUT STD_LOGIC );
end;
architecture behav of Loop_loop_height_pro is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv8_8 : STD_LOGIC_VECTOR (7 downto 0) := "00001000";
constant ap_const_lv8_7 : STD_LOGIC_VECTOR (7 downto 0) := "00000111";
constant ap_const_lv8_6 : STD_LOGIC_VECTOR (7 downto 0) := "00000110";
constant ap_const_lv8_5 : STD_LOGIC_VECTOR (7 downto 0) := "00000101";
constant ap_const_lv8_4 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
constant ap_const_lv8_3 : STD_LOGIC_VECTOR (7 downto 0) := "00000011";
constant ap_const_lv8_2 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (4 downto 0) := "00001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal lut2_2_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut2_2_ce0 : STD_LOGIC;
signal lut2_2_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut2_2_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut2_2_ce1 : STD_LOGIC;
signal lut2_2_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut2_2_address2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut2_2_ce2 : STD_LOGIC;
signal lut2_2_q2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut0_4_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut0_4_ce0 : STD_LOGIC;
signal lut0_4_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut0_4_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut0_4_ce1 : STD_LOGIC;
signal lut0_4_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut0_4_address2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut0_4_ce2 : STD_LOGIC;
signal lut0_4_q2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut0_2_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut0_2_ce0 : STD_LOGIC;
signal lut0_2_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut0_2_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut0_2_ce1 : STD_LOGIC;
signal lut0_2_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut0_2_address2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut0_2_ce2 : STD_LOGIC;
signal lut0_2_q2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_2_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_2_ce0 : STD_LOGIC;
signal lut1_2_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_2_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_2_ce1 : STD_LOGIC;
signal lut1_2_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_2_address2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_2_ce2 : STD_LOGIC;
signal lut1_2_q2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_4_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_4_ce0 : STD_LOGIC;
signal lut1_4_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_4_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_4_ce1 : STD_LOGIC;
signal lut1_4_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_4_address2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_4_ce2 : STD_LOGIC;
signal lut1_4_q2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_6_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_6_ce0 : STD_LOGIC;
signal lut1_6_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_6_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_6_ce1 : STD_LOGIC;
signal lut1_6_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_6_address2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_6_ce2 : STD_LOGIC;
signal lut1_6_q2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_8_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_8_ce0 : STD_LOGIC;
signal lut1_8_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_8_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_8_ce1 : STD_LOGIC;
signal lut1_8_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_8_address2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut1_8_ce2 : STD_LOGIC;
signal lut1_8_q2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut2_0_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut2_0_ce0 : STD_LOGIC;
signal lut2_0_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal lut2_0_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut2_0_ce1 : STD_LOGIC;
signal lut2_0_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal lut2_0_address2 : STD_LOGIC_VECTOR (7 downto 0);
signal lut2_0_ce2 : STD_LOGIC;
signal lut2_0_q2 : STD_LOGIC_VECTOR (7 downto 0);
signal p_rows_assign_cast_loc_blk_n : STD_LOGIC;
signal p_cols_assign_cast_loc_blk_n : STD_LOGIC;
signal img3_data_stream_0_V_blk_n : STD_LOGIC;
signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
signal ap_block_pp0_stage0 : BOOLEAN;
signal exitcond_i_i_i_reg_837 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 : STD_LOGIC_VECTOR (0 downto 0);
signal img3_data_stream_1_V_blk_n : STD_LOGIC;
signal img3_data_stream_2_V_blk_n : STD_LOGIC;
signal gamma_blk_n : STD_LOGIC;
signal img0_data_stream_0_V_blk_n : STD_LOGIC;
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal img0_data_stream_1_V_blk_n : STD_LOGIC;
signal img0_data_stream_2_V_blk_n : STD_LOGIC;
signal t_V_2_reg_444 : STD_LOGIC_VECTOR (10 downto 0);
signal gamma_read_reg_750 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_state1 : BOOLEAN;
signal p_rows_assign_cast_lo_reg_762 : STD_LOGIC_VECTOR (11 downto 0);
signal p_cols_assign_cast_lo_reg_767 : STD_LOGIC_VECTOR (11 downto 0);
signal sel_tmp2_fu_460_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp2_reg_772 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal sel_tmp6_fu_470_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp6_reg_779 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp1_fu_480_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp1_reg_786 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp5_fu_490_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp5_reg_793 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_fu_495_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_reg_800 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond2_fu_507_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond2_reg_807 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond4_fu_519_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond4_reg_814 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond6_fu_531_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond6_reg_821 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond161_i_i_i_fu_541_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal i_V_fu_546_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal i_V_reg_832 : STD_LOGIC_VECTOR (10 downto 0);
signal exitcond_i_i_i_fu_556_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_state4_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state5_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state6_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_state7_pp0_stage0_iter3 : BOOLEAN;
signal ap_block_state8_pp0_stage0_iter4 : BOOLEAN;
signal ap_block_pp0_stage0_11001 : BOOLEAN;
signal ap_reg_pp0_iter1_exitcond_i_i_i_reg_837 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter2_exitcond_i_i_i_reg_837 : STD_LOGIC_VECTOR (0 downto 0);
signal j_V_fu_561_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal tmp_9_reg_846 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_tmp_9_reg_846 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_9_reg_846 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_10_reg_852 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_tmp_10_reg_852 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_10_reg_852 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_11_reg_858 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_tmp_11_reg_858 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_11_reg_858 : STD_LOGIC_VECTOR (7 downto 0);
signal d_val_0_2_reg_984 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
signal d_val_0_3_reg_989 : STD_LOGIC_VECTOR (7 downto 0);
signal d_val_0_6_reg_994 : STD_LOGIC_VECTOR (7 downto 0);
signal d_val_0_7_reg_999 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel1_fu_600_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel1_reg_1004 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel3_fu_607_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel3_reg_1009 : STD_LOGIC_VECTOR (7 downto 0);
signal d_val_1_2_reg_1014 : STD_LOGIC_VECTOR (7 downto 0);
signal d_val_1_3_reg_1019 : STD_LOGIC_VECTOR (7 downto 0);
signal d_val_1_6_reg_1024 : STD_LOGIC_VECTOR (7 downto 0);
signal d_val_1_7_reg_1029 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel9_fu_614_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel9_reg_1034 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel10_fu_621_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel10_reg_1039 : STD_LOGIC_VECTOR (7 downto 0);
signal d_val_2_2_reg_1044 : STD_LOGIC_VECTOR (7 downto 0);
signal d_val_2_3_reg_1049 : STD_LOGIC_VECTOR (7 downto 0);
signal d_val_2_6_reg_1054 : STD_LOGIC_VECTOR (7 downto 0);
signal d_val_2_7_reg_1059 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel15_fu_628_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel15_reg_1064 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel17_fu_635_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel17_reg_1069 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_pp0_stage0_subdone : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state4 : STD_LOGIC;
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal t_V_reg_433 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_CS_fsm_state9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
signal tmp_26_i_i_fu_567_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_26_1_i_i_fu_578_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_26_2_i_i_fu_589_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage0_01001 : BOOLEAN;
signal sel_tmp3_fu_485_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp8_fu_475_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp4_fu_465_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp_fu_455_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond1_fu_501_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond3_fu_513_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond5_fu_525_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal t_V_cast_i_i_fu_537_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal t_V_1_cast_i_i_fu_552_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal newSel_fu_642_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel2_fu_647_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel4_fu_652_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel5_fu_658_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel6_fu_664_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel8_fu_678_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel7_fu_683_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel11_fu_688_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel12_fu_694_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel13_fu_700_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel14_fu_714_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel16_fu_719_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel18_fu_724_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel19_fu_730_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal newSel20_fu_736_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (4 downto 0);
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
component Loop_loop_height_bkb IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (7 downto 0);
address2 : IN STD_LOGIC_VECTOR (7 downto 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component Loop_loop_height_cud IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (7 downto 0);
address2 : IN STD_LOGIC_VECTOR (7 downto 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component Loop_loop_height_dEe IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (7 downto 0);
address2 : IN STD_LOGIC_VECTOR (7 downto 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component Loop_loop_height_eOg IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (7 downto 0);
address2 : IN STD_LOGIC_VECTOR (7 downto 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component Loop_loop_height_fYi IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (7 downto 0);
address2 : IN STD_LOGIC_VECTOR (7 downto 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component Loop_loop_height_g8j IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (7 downto 0);
address2 : IN STD_LOGIC_VECTOR (7 downto 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component Loop_loop_height_hbi IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (7 downto 0);
address2 : IN STD_LOGIC_VECTOR (7 downto 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
component Loop_loop_height_ibs IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR (7 downto 0);
address2 : IN STD_LOGIC_VECTOR (7 downto 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
begin
lut2_2_U : component Loop_loop_height_bkb
generic map (
DataWidth => 8,
AddressRange => 256,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => lut2_2_address0,
ce0 => lut2_2_ce0,
q0 => lut2_2_q0,
address1 => lut2_2_address1,
ce1 => lut2_2_ce1,
q1 => lut2_2_q1,
address2 => lut2_2_address2,
ce2 => lut2_2_ce2,
q2 => lut2_2_q2);
lut0_4_U : component Loop_loop_height_cud
generic map (
DataWidth => 8,
AddressRange => 256,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => lut0_4_address0,
ce0 => lut0_4_ce0,
q0 => lut0_4_q0,
address1 => lut0_4_address1,
ce1 => lut0_4_ce1,
q1 => lut0_4_q1,
address2 => lut0_4_address2,
ce2 => lut0_4_ce2,
q2 => lut0_4_q2);
lut0_2_U : component Loop_loop_height_dEe
generic map (
DataWidth => 8,
AddressRange => 256,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => lut0_2_address0,
ce0 => lut0_2_ce0,
q0 => lut0_2_q0,
address1 => lut0_2_address1,
ce1 => lut0_2_ce1,
q1 => lut0_2_q1,
address2 => lut0_2_address2,
ce2 => lut0_2_ce2,
q2 => lut0_2_q2);
lut1_2_U : component Loop_loop_height_eOg
generic map (
DataWidth => 8,
AddressRange => 256,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => lut1_2_address0,
ce0 => lut1_2_ce0,
q0 => lut1_2_q0,
address1 => lut1_2_address1,
ce1 => lut1_2_ce1,
q1 => lut1_2_q1,
address2 => lut1_2_address2,
ce2 => lut1_2_ce2,
q2 => lut1_2_q2);
lut1_4_U : component Loop_loop_height_fYi
generic map (
DataWidth => 8,
AddressRange => 256,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => lut1_4_address0,
ce0 => lut1_4_ce0,
q0 => lut1_4_q0,
address1 => lut1_4_address1,
ce1 => lut1_4_ce1,
q1 => lut1_4_q1,
address2 => lut1_4_address2,
ce2 => lut1_4_ce2,
q2 => lut1_4_q2);
lut1_6_U : component Loop_loop_height_g8j
generic map (
DataWidth => 8,
AddressRange => 256,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => lut1_6_address0,
ce0 => lut1_6_ce0,
q0 => lut1_6_q0,
address1 => lut1_6_address1,
ce1 => lut1_6_ce1,
q1 => lut1_6_q1,
address2 => lut1_6_address2,
ce2 => lut1_6_ce2,
q2 => lut1_6_q2);
lut1_8_U : component Loop_loop_height_hbi
generic map (
DataWidth => 8,
AddressRange => 256,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => lut1_8_address0,
ce0 => lut1_8_ce0,
q0 => lut1_8_q0,
address1 => lut1_8_address1,
ce1 => lut1_8_ce1,
q1 => lut1_8_q1,
address2 => lut1_8_address2,
ce2 => lut1_8_ce2,
q2 => lut1_8_q2);
lut2_0_U : component Loop_loop_height_ibs
generic map (
DataWidth => 8,
AddressRange => 256,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => lut2_0_address0,
ce0 => lut2_0_ce0,
q0 => lut2_0_q0,
address1 => lut2_0_address1,
ce1 => lut2_0_ce1,
q1 => lut2_0_q1,
address2 => lut2_0_address2,
ce2 => lut2_0_ce2,
q2 => lut2_0_q2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_continue = ap_const_logic_1)) then
ap_done_reg <= ap_const_logic_0;
elsif (((exitcond161_i_i_i_fu_541_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state4) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state3) and (exitcond161_i_i_i_fu_541_p2 = ap_const_lv1_0))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state4)) then
ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state4);
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end if;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
elsif (((ap_const_logic_1 = ap_CS_fsm_state3) and (exitcond161_i_i_i_fu_541_p2 = ap_const_lv1_0))) then
ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
t_V_2_reg_444_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_i_i_i_fu_556_p2 = ap_const_lv1_0))) then
t_V_2_reg_444 <= j_V_fu_561_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state3) and (exitcond161_i_i_i_fu_541_p2 = ap_const_lv1_0))) then
t_V_2_reg_444 <= ap_const_lv11_0;
end if;
end if;
end process;
t_V_reg_433_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state9)) then
t_V_reg_433 <= i_V_reg_832;
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
t_V_reg_433 <= ap_const_lv11_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_reg_pp0_iter1_exitcond_i_i_i_reg_837 <= exitcond_i_i_i_reg_837;
exitcond_i_i_i_reg_837 <= exitcond_i_i_i_fu_556_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_0 = ap_block_pp0_stage0_11001)) then
ap_reg_pp0_iter2_exitcond_i_i_i_reg_837 <= ap_reg_pp0_iter1_exitcond_i_i_i_reg_837;
ap_reg_pp0_iter2_tmp_10_reg_852 <= tmp_10_reg_852;
ap_reg_pp0_iter2_tmp_11_reg_858 <= tmp_11_reg_858;
ap_reg_pp0_iter2_tmp_9_reg_846 <= tmp_9_reg_846;
ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 <= ap_reg_pp0_iter2_exitcond_i_i_i_reg_837;
ap_reg_pp0_iter3_tmp_10_reg_852 <= ap_reg_pp0_iter2_tmp_10_reg_852;
ap_reg_pp0_iter3_tmp_11_reg_858 <= ap_reg_pp0_iter2_tmp_11_reg_858;
ap_reg_pp0_iter3_tmp_9_reg_846 <= ap_reg_pp0_iter2_tmp_9_reg_846;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_cond6_reg_821 = ap_const_lv1_1) and (or_cond4_reg_814 = ap_const_lv1_1) and (or_cond_reg_800 = ap_const_lv1_1) and (sel_tmp5_reg_793 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1) and (ap_reg_pp0_iter2_exitcond_i_i_i_reg_837 = ap_const_lv1_0))) then
d_val_0_2_reg_984 <= lut0_4_q0;
d_val_1_2_reg_1014 <= lut0_4_q1;
d_val_2_2_reg_1044 <= lut0_4_q2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_cond6_reg_821 = ap_const_lv1_1) and (or_cond4_reg_814 = ap_const_lv1_1) and (or_cond_reg_800 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1) and (ap_reg_pp0_iter2_exitcond_i_i_i_reg_837 = ap_const_lv1_0) and (sel_tmp5_reg_793 = ap_const_lv1_0))) then
d_val_0_3_reg_989 <= lut0_2_q0;
d_val_1_3_reg_1019 <= lut0_2_q1;
d_val_2_3_reg_1049 <= lut0_2_q2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_cond6_reg_821 = ap_const_lv1_1) and (or_cond2_reg_807 = ap_const_lv1_1) and (sel_tmp6_reg_779 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1) and (ap_reg_pp0_iter2_exitcond_i_i_i_reg_837 = ap_const_lv1_0) and (or_cond4_reg_814 = ap_const_lv1_0))) then
d_val_0_6_reg_994 <= lut1_6_q0;
d_val_1_6_reg_1024 <= lut1_6_q1;
d_val_2_6_reg_1054 <= lut1_6_q2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_cond6_reg_821 = ap_const_lv1_1) and (or_cond2_reg_807 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1) and (ap_reg_pp0_iter2_exitcond_i_i_i_reg_837 = ap_const_lv1_0) and (or_cond4_reg_814 = ap_const_lv1_0) and (sel_tmp6_reg_779 = ap_const_lv1_0))) then
d_val_0_7_reg_999 <= lut1_8_q0;
d_val_1_7_reg_1029 <= lut1_8_q1;
d_val_2_7_reg_1059 <= lut1_8_q2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((gamma_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
gamma_read_reg_750 <= gamma_dout;
p_cols_assign_cast_lo_reg_767 <= p_cols_assign_cast_loc_dout;
p_rows_assign_cast_lo_reg_762 <= p_rows_assign_cast_loc_dout;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
i_V_reg_832 <= i_V_fu_546_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_cond6_reg_821 = ap_const_lv1_1) and (ap_reg_pp0_iter2_exitcond_i_i_i_reg_837 = ap_const_lv1_0) and (or_cond4_reg_814 = ap_const_lv1_0) and (or_cond2_reg_807 = ap_const_lv1_0))) then
newSel10_reg_1039 <= newSel10_fu_621_p3;
newSel17_reg_1069 <= newSel17_fu_635_p3;
newSel3_reg_1009 <= newSel3_fu_607_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (or_cond6_reg_821 = ap_const_lv1_1) and (or_cond4_reg_814 = ap_const_lv1_1) and (ap_reg_pp0_iter2_exitcond_i_i_i_reg_837 = ap_const_lv1_0) and (or_cond_reg_800 = ap_const_lv1_0))) then
newSel15_reg_1064 <= newSel15_fu_628_p3;
newSel1_reg_1004 <= newSel1_fu_600_p3;
newSel9_reg_1034 <= newSel9_fu_614_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
or_cond2_reg_807 <= or_cond2_fu_507_p2;
or_cond4_reg_814 <= or_cond4_fu_519_p2;
or_cond6_reg_821 <= or_cond6_fu_531_p2;
or_cond_reg_800 <= or_cond_fu_495_p2;
sel_tmp1_reg_786 <= sel_tmp1_fu_480_p2;
sel_tmp2_reg_772 <= sel_tmp2_fu_460_p2;
sel_tmp5_reg_793 <= sel_tmp5_fu_490_p2;
sel_tmp6_reg_779 <= sel_tmp6_fu_470_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0))) then
tmp_10_reg_852 <= img0_data_stream_1_V_dout;
tmp_11_reg_858 <= img0_data_stream_2_V_dout;
tmp_9_reg_846 <= img0_data_stream_0_V_dout;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, gamma_empty_n, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter1, exitcond161_i_i_i_fu_541_p2, ap_CS_fsm_state3, exitcond_i_i_i_fu_556_p2, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter3, ap_block_pp0_stage0_subdone)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if ((not(((gamma_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when ap_ST_fsm_state3 =>
if (((exitcond161_i_i_i_fu_541_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage0 =>
if ((not(((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (exitcond_i_i_i_fu_556_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1))) and not(((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
elsif ((((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (exitcond_i_i_i_fu_556_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1)))) then
ap_NS_fsm <= ap_ST_fsm_state9;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_state9 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when others =>
ap_NS_fsm <= "XXXXX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(3);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state9 <= ap_CS_fsm(4);
ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_01001_assign_proc : process(img3_data_stream_0_V_full_n, img3_data_stream_1_V_full_n, img3_data_stream_2_V_full_n, img0_data_stream_0_V_empty_n, img0_data_stream_1_V_empty_n, img0_data_stream_2_V_empty_n, ap_enable_reg_pp0_iter4, exitcond_i_i_i_reg_837, ap_reg_pp0_iter3_exitcond_i_i_i_reg_837, ap_enable_reg_pp0_iter1)
begin
ap_block_pp0_stage0_01001 <= (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((img0_data_stream_2_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img0_data_stream_1_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img0_data_stream_0_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0)))) or ((ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (((img3_data_stream_2_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img3_data_stream_1_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img3_data_stream_0_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0)))));
end process;
ap_block_pp0_stage0_11001_assign_proc : process(img3_data_stream_0_V_full_n, img3_data_stream_1_V_full_n, img3_data_stream_2_V_full_n, img0_data_stream_0_V_empty_n, img0_data_stream_1_V_empty_n, img0_data_stream_2_V_empty_n, ap_enable_reg_pp0_iter4, exitcond_i_i_i_reg_837, ap_reg_pp0_iter3_exitcond_i_i_i_reg_837, ap_enable_reg_pp0_iter1)
begin
ap_block_pp0_stage0_11001 <= (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((img0_data_stream_2_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img0_data_stream_1_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img0_data_stream_0_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0)))) or ((ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (((img3_data_stream_2_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img3_data_stream_1_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img3_data_stream_0_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0)))));
end process;
ap_block_pp0_stage0_subdone_assign_proc : process(img3_data_stream_0_V_full_n, img3_data_stream_1_V_full_n, img3_data_stream_2_V_full_n, img0_data_stream_0_V_empty_n, img0_data_stream_1_V_empty_n, img0_data_stream_2_V_empty_n, ap_enable_reg_pp0_iter4, exitcond_i_i_i_reg_837, ap_reg_pp0_iter3_exitcond_i_i_i_reg_837, ap_enable_reg_pp0_iter1)
begin
ap_block_pp0_stage0_subdone <= (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((img0_data_stream_2_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img0_data_stream_1_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img0_data_stream_0_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0)))) or ((ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (((img3_data_stream_2_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img3_data_stream_1_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img3_data_stream_0_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0)))));
end process;
ap_block_state1_assign_proc : process(ap_start, ap_done_reg, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, gamma_empty_n)
begin
ap_block_state1 <= ((gamma_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
ap_block_state4_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state5_pp0_stage0_iter1_assign_proc : process(img0_data_stream_0_V_empty_n, img0_data_stream_1_V_empty_n, img0_data_stream_2_V_empty_n, exitcond_i_i_i_reg_837)
begin
ap_block_state5_pp0_stage0_iter1 <= (((img0_data_stream_2_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img0_data_stream_1_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img0_data_stream_0_V_empty_n = ap_const_logic_0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0)));
end process;
ap_block_state6_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage0_iter4_assign_proc : process(img3_data_stream_0_V_full_n, img3_data_stream_1_V_full_n, img3_data_stream_2_V_full_n, ap_reg_pp0_iter3_exitcond_i_i_i_reg_837)
begin
ap_block_state8_pp0_stage0_iter4 <= (((img3_data_stream_2_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img3_data_stream_1_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0)) or ((img3_data_stream_0_V_full_n = ap_const_logic_0) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0)));
end process;
ap_condition_pp0_exit_iter0_state4_assign_proc : process(exitcond_i_i_i_fu_556_p2)
begin
if ((exitcond_i_i_i_fu_556_p2 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state4 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state4 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_done_reg, exitcond161_i_i_i_fu_541_p2, ap_CS_fsm_state3)
begin
if (((exitcond161_i_i_i_fu_541_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter2)
begin
if (((ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter4 = ap_const_logic_0))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(exitcond161_i_i_i_fu_541_p2, ap_CS_fsm_state3)
begin
if (((exitcond161_i_i_i_fu_541_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
exitcond161_i_i_i_fu_541_p2 <= "1" when (t_V_cast_i_i_fu_537_p1 = p_rows_assign_cast_lo_reg_762) else "0";
exitcond_i_i_i_fu_556_p2 <= "1" when (t_V_1_cast_i_i_fu_552_p1 = p_cols_assign_cast_lo_reg_767) else "0";
gamma_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, gamma_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
gamma_blk_n <= gamma_empty_n;
else
gamma_blk_n <= ap_const_logic_1;
end if;
end process;
gamma_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, gamma_empty_n)
begin
if ((not(((gamma_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
gamma_read <= ap_const_logic_1;
else
gamma_read <= ap_const_logic_0;
end if;
end process;
i_V_fu_546_p2 <= std_logic_vector(unsigned(t_V_reg_433) + unsigned(ap_const_lv11_1));
img0_data_stream_0_V_blk_n_assign_proc : process(img0_data_stream_0_V_empty_n, ap_block_pp0_stage0, exitcond_i_i_i_reg_837, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1)
begin
if (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
img0_data_stream_0_V_blk_n <= img0_data_stream_0_V_empty_n;
else
img0_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
img0_data_stream_0_V_read_assign_proc : process(exitcond_i_i_i_reg_837, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0))) then
img0_data_stream_0_V_read <= ap_const_logic_1;
else
img0_data_stream_0_V_read <= ap_const_logic_0;
end if;
end process;
img0_data_stream_1_V_blk_n_assign_proc : process(img0_data_stream_1_V_empty_n, ap_block_pp0_stage0, exitcond_i_i_i_reg_837, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1)
begin
if (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
img0_data_stream_1_V_blk_n <= img0_data_stream_1_V_empty_n;
else
img0_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
img0_data_stream_1_V_read_assign_proc : process(exitcond_i_i_i_reg_837, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0))) then
img0_data_stream_1_V_read <= ap_const_logic_1;
else
img0_data_stream_1_V_read <= ap_const_logic_0;
end if;
end process;
img0_data_stream_2_V_blk_n_assign_proc : process(img0_data_stream_2_V_empty_n, ap_block_pp0_stage0, exitcond_i_i_i_reg_837, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1)
begin
if (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
img0_data_stream_2_V_blk_n <= img0_data_stream_2_V_empty_n;
else
img0_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
img0_data_stream_2_V_read_assign_proc : process(exitcond_i_i_i_reg_837, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_i_i_i_reg_837 = ap_const_lv1_0))) then
img0_data_stream_2_V_read <= ap_const_logic_1;
else
img0_data_stream_2_V_read <= ap_const_logic_0;
end if;
end process;
img3_data_stream_0_V_blk_n_assign_proc : process(img3_data_stream_0_V_full_n, ap_enable_reg_pp0_iter4, ap_block_pp0_stage0, ap_reg_pp0_iter3_exitcond_i_i_i_reg_837)
begin
if (((ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
img3_data_stream_0_V_blk_n <= img3_data_stream_0_V_full_n;
else
img3_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
img3_data_stream_0_V_din <=
newSel6_fu_664_p3 when (or_cond6_reg_821(0) = '1') else
ap_reg_pp0_iter3_tmp_9_reg_846;
img3_data_stream_0_V_write_assign_proc : process(ap_enable_reg_pp0_iter4, ap_reg_pp0_iter3_exitcond_i_i_i_reg_837, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0))) then
img3_data_stream_0_V_write <= ap_const_logic_1;
else
img3_data_stream_0_V_write <= ap_const_logic_0;
end if;
end process;
img3_data_stream_1_V_blk_n_assign_proc : process(img3_data_stream_1_V_full_n, ap_enable_reg_pp0_iter4, ap_block_pp0_stage0, ap_reg_pp0_iter3_exitcond_i_i_i_reg_837)
begin
if (((ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
img3_data_stream_1_V_blk_n <= img3_data_stream_1_V_full_n;
else
img3_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
img3_data_stream_1_V_din <=
newSel13_fu_700_p3 when (or_cond6_reg_821(0) = '1') else
ap_reg_pp0_iter3_tmp_10_reg_852;
img3_data_stream_1_V_write_assign_proc : process(ap_enable_reg_pp0_iter4, ap_reg_pp0_iter3_exitcond_i_i_i_reg_837, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0))) then
img3_data_stream_1_V_write <= ap_const_logic_1;
else
img3_data_stream_1_V_write <= ap_const_logic_0;
end if;
end process;
img3_data_stream_2_V_blk_n_assign_proc : process(img3_data_stream_2_V_full_n, ap_enable_reg_pp0_iter4, ap_block_pp0_stage0, ap_reg_pp0_iter3_exitcond_i_i_i_reg_837)
begin
if (((ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0))) then
img3_data_stream_2_V_blk_n <= img3_data_stream_2_V_full_n;
else
img3_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
img3_data_stream_2_V_din <=
newSel20_fu_736_p3 when (or_cond6_reg_821(0) = '1') else
ap_reg_pp0_iter3_tmp_11_reg_858;
img3_data_stream_2_V_write_assign_proc : process(ap_enable_reg_pp0_iter4, ap_reg_pp0_iter3_exitcond_i_i_i_reg_837, ap_block_pp0_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 = ap_const_lv1_0))) then
img3_data_stream_2_V_write <= ap_const_logic_1;
else
img3_data_stream_2_V_write <= ap_const_logic_0;
end if;
end process;
j_V_fu_561_p2 <= std_logic_vector(unsigned(t_V_2_reg_444) + unsigned(ap_const_lv11_1));
lut0_2_address0 <= tmp_26_i_i_fu_567_p1(8 - 1 downto 0);
lut0_2_address1 <= tmp_26_1_i_i_fu_578_p1(8 - 1 downto 0);
lut0_2_address2 <= tmp_26_2_i_i_fu_589_p1(8 - 1 downto 0);
lut0_2_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut0_2_ce0 <= ap_const_logic_1;
else
lut0_2_ce0 <= ap_const_logic_0;
end if;
end process;
lut0_2_ce1_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut0_2_ce1 <= ap_const_logic_1;
else
lut0_2_ce1 <= ap_const_logic_0;
end if;
end process;
lut0_2_ce2_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut0_2_ce2 <= ap_const_logic_1;
else
lut0_2_ce2 <= ap_const_logic_0;
end if;
end process;
lut0_4_address0 <= tmp_26_i_i_fu_567_p1(8 - 1 downto 0);
lut0_4_address1 <= tmp_26_1_i_i_fu_578_p1(8 - 1 downto 0);
lut0_4_address2 <= tmp_26_2_i_i_fu_589_p1(8 - 1 downto 0);
lut0_4_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut0_4_ce0 <= ap_const_logic_1;
else
lut0_4_ce0 <= ap_const_logic_0;
end if;
end process;
lut0_4_ce1_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut0_4_ce1 <= ap_const_logic_1;
else
lut0_4_ce1 <= ap_const_logic_0;
end if;
end process;
lut0_4_ce2_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut0_4_ce2 <= ap_const_logic_1;
else
lut0_4_ce2 <= ap_const_logic_0;
end if;
end process;
lut1_2_address0 <= tmp_26_i_i_fu_567_p1(8 - 1 downto 0);
lut1_2_address1 <= tmp_26_1_i_i_fu_578_p1(8 - 1 downto 0);
lut1_2_address2 <= tmp_26_2_i_i_fu_589_p1(8 - 1 downto 0);
lut1_2_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut1_2_ce0 <= ap_const_logic_1;
else
lut1_2_ce0 <= ap_const_logic_0;
end if;
end process;
lut1_2_ce1_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut1_2_ce1 <= ap_const_logic_1;
else
lut1_2_ce1 <= ap_const_logic_0;
end if;
end process;
lut1_2_ce2_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut1_2_ce2 <= ap_const_logic_1;
else
lut1_2_ce2 <= ap_const_logic_0;
end if;
end process;
lut1_4_address0 <= tmp_26_i_i_fu_567_p1(8 - 1 downto 0);
lut1_4_address1 <= tmp_26_1_i_i_fu_578_p1(8 - 1 downto 0);
lut1_4_address2 <= tmp_26_2_i_i_fu_589_p1(8 - 1 downto 0);
lut1_4_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut1_4_ce0 <= ap_const_logic_1;
else
lut1_4_ce0 <= ap_const_logic_0;
end if;
end process;
lut1_4_ce1_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut1_4_ce1 <= ap_const_logic_1;
else
lut1_4_ce1 <= ap_const_logic_0;
end if;
end process;
lut1_4_ce2_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut1_4_ce2 <= ap_const_logic_1;
else
lut1_4_ce2 <= ap_const_logic_0;
end if;
end process;
lut1_6_address0 <= tmp_26_i_i_fu_567_p1(8 - 1 downto 0);
lut1_6_address1 <= tmp_26_1_i_i_fu_578_p1(8 - 1 downto 0);
lut1_6_address2 <= tmp_26_2_i_i_fu_589_p1(8 - 1 downto 0);
lut1_6_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut1_6_ce0 <= ap_const_logic_1;
else
lut1_6_ce0 <= ap_const_logic_0;
end if;
end process;
lut1_6_ce1_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut1_6_ce1 <= ap_const_logic_1;
else
lut1_6_ce1 <= ap_const_logic_0;
end if;
end process;
lut1_6_ce2_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut1_6_ce2 <= ap_const_logic_1;
else
lut1_6_ce2 <= ap_const_logic_0;
end if;
end process;
lut1_8_address0 <= tmp_26_i_i_fu_567_p1(8 - 1 downto 0);
lut1_8_address1 <= tmp_26_1_i_i_fu_578_p1(8 - 1 downto 0);
lut1_8_address2 <= tmp_26_2_i_i_fu_589_p1(8 - 1 downto 0);
lut1_8_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut1_8_ce0 <= ap_const_logic_1;
else
lut1_8_ce0 <= ap_const_logic_0;
end if;
end process;
lut1_8_ce1_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut1_8_ce1 <= ap_const_logic_1;
else
lut1_8_ce1 <= ap_const_logic_0;
end if;
end process;
lut1_8_ce2_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut1_8_ce2 <= ap_const_logic_1;
else
lut1_8_ce2 <= ap_const_logic_0;
end if;
end process;
lut2_0_address0 <= tmp_26_i_i_fu_567_p1(8 - 1 downto 0);
lut2_0_address1 <= tmp_26_1_i_i_fu_578_p1(8 - 1 downto 0);
lut2_0_address2 <= tmp_26_2_i_i_fu_589_p1(8 - 1 downto 0);
lut2_0_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut2_0_ce0 <= ap_const_logic_1;
else
lut2_0_ce0 <= ap_const_logic_0;
end if;
end process;
lut2_0_ce1_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut2_0_ce1 <= ap_const_logic_1;
else
lut2_0_ce1 <= ap_const_logic_0;
end if;
end process;
lut2_0_ce2_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut2_0_ce2 <= ap_const_logic_1;
else
lut2_0_ce2 <= ap_const_logic_0;
end if;
end process;
lut2_2_address0 <= tmp_26_i_i_fu_567_p1(8 - 1 downto 0);
lut2_2_address1 <= tmp_26_1_i_i_fu_578_p1(8 - 1 downto 0);
lut2_2_address2 <= tmp_26_2_i_i_fu_589_p1(8 - 1 downto 0);
lut2_2_ce0_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut2_2_ce0 <= ap_const_logic_1;
else
lut2_2_ce0 <= ap_const_logic_0;
end if;
end process;
lut2_2_ce1_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut2_2_ce1 <= ap_const_logic_1;
else
lut2_2_ce1 <= ap_const_logic_0;
end if;
end process;
lut2_2_ce2_assign_proc : process(ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))) then
lut2_2_ce2 <= ap_const_logic_1;
else
lut2_2_ce2 <= ap_const_logic_0;
end if;
end process;
newSel10_fu_621_p3 <=
lut2_0_q1 when (sel_tmp2_reg_772(0) = '1') else
lut2_2_q1;
newSel11_fu_688_p3 <=
newSel8_fu_678_p3 when (or_cond_reg_800(0) = '1') else
newSel9_reg_1034;
newSel12_fu_694_p3 <=
newSel7_fu_683_p3 when (or_cond2_reg_807(0) = '1') else
newSel10_reg_1039;
newSel13_fu_700_p3 <=
newSel11_fu_688_p3 when (or_cond4_reg_814(0) = '1') else
newSel12_fu_694_p3;
newSel14_fu_714_p3 <=
d_val_2_2_reg_1044 when (sel_tmp5_reg_793(0) = '1') else
d_val_2_3_reg_1049;
newSel15_fu_628_p3 <=
lut1_2_q2 when (sel_tmp1_reg_786(0) = '1') else
lut1_4_q2;
newSel16_fu_719_p3 <=
d_val_2_6_reg_1054 when (sel_tmp6_reg_779(0) = '1') else
d_val_2_7_reg_1059;
newSel17_fu_635_p3 <=
lut2_0_q2 when (sel_tmp2_reg_772(0) = '1') else
lut2_2_q2;
newSel18_fu_724_p3 <=
newSel14_fu_714_p3 when (or_cond_reg_800(0) = '1') else
newSel15_reg_1064;
newSel19_fu_730_p3 <=
newSel16_fu_719_p3 when (or_cond2_reg_807(0) = '1') else
newSel17_reg_1069;
newSel1_fu_600_p3 <=
lut1_2_q0 when (sel_tmp1_reg_786(0) = '1') else
lut1_4_q0;
newSel20_fu_736_p3 <=
newSel18_fu_724_p3 when (or_cond4_reg_814(0) = '1') else
newSel19_fu_730_p3;
newSel2_fu_647_p3 <=
d_val_0_6_reg_994 when (sel_tmp6_reg_779(0) = '1') else
d_val_0_7_reg_999;
newSel3_fu_607_p3 <=
lut2_0_q0 when (sel_tmp2_reg_772(0) = '1') else
lut2_2_q0;
newSel4_fu_652_p3 <=
newSel_fu_642_p3 when (or_cond_reg_800(0) = '1') else
newSel1_reg_1004;
newSel5_fu_658_p3 <=
newSel2_fu_647_p3 when (or_cond2_reg_807(0) = '1') else
newSel3_reg_1009;
newSel6_fu_664_p3 <=
newSel4_fu_652_p3 when (or_cond4_reg_814(0) = '1') else
newSel5_fu_658_p3;
newSel7_fu_683_p3 <=
d_val_1_6_reg_1024 when (sel_tmp6_reg_779(0) = '1') else
d_val_1_7_reg_1029;
newSel8_fu_678_p3 <=
d_val_1_2_reg_1014 when (sel_tmp5_reg_793(0) = '1') else
d_val_1_3_reg_1019;
newSel9_fu_614_p3 <=
lut1_2_q1 when (sel_tmp1_reg_786(0) = '1') else
lut1_4_q1;
newSel_fu_642_p3 <=
d_val_0_2_reg_984 when (sel_tmp5_reg_793(0) = '1') else
d_val_0_3_reg_989;
or_cond1_fu_501_p2 <= (sel_tmp8_fu_475_p2 or sel_tmp1_fu_480_p2);
or_cond2_fu_507_p2 <= (sel_tmp6_fu_470_p2 or sel_tmp4_fu_465_p2);
or_cond3_fu_513_p2 <= (sel_tmp_fu_455_p2 or sel_tmp2_fu_460_p2);
or_cond4_fu_519_p2 <= (or_cond_fu_495_p2 or or_cond1_fu_501_p2);
or_cond5_fu_525_p2 <= (or_cond3_fu_513_p2 or or_cond2_fu_507_p2);
or_cond6_fu_531_p2 <= (or_cond5_fu_525_p2 or or_cond4_fu_519_p2);
or_cond_fu_495_p2 <= (sel_tmp5_fu_490_p2 or sel_tmp3_fu_485_p2);
p_cols_assign_cast_loc_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_cols_assign_cast_loc_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_cols_assign_cast_loc_blk_n <= p_cols_assign_cast_loc_empty_n;
else
p_cols_assign_cast_loc_blk_n <= ap_const_logic_1;
end if;
end process;
p_cols_assign_cast_loc_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, gamma_empty_n)
begin
if ((not(((gamma_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_cols_assign_cast_loc_read <= ap_const_logic_1;
else
p_cols_assign_cast_loc_read <= ap_const_logic_0;
end if;
end process;
p_rows_assign_cast_loc_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_rows_assign_cast_loc_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_rows_assign_cast_loc_blk_n <= p_rows_assign_cast_loc_empty_n;
else
p_rows_assign_cast_loc_blk_n <= ap_const_logic_1;
end if;
end process;
p_rows_assign_cast_loc_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, gamma_empty_n)
begin
if ((not(((gamma_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_rows_assign_cast_loc_read <= ap_const_logic_1;
else
p_rows_assign_cast_loc_read <= ap_const_logic_0;
end if;
end process;
sel_tmp1_fu_480_p2 <= "1" when (gamma_read_reg_750 = ap_const_lv8_3) else "0";
sel_tmp2_fu_460_p2 <= "1" when (gamma_read_reg_750 = ap_const_lv8_7) else "0";
sel_tmp3_fu_485_p2 <= "1" when (gamma_read_reg_750 = ap_const_lv8_2) else "0";
sel_tmp4_fu_465_p2 <= "1" when (gamma_read_reg_750 = ap_const_lv8_6) else "0";
sel_tmp5_fu_490_p2 <= "1" when (gamma_read_reg_750 = ap_const_lv8_1) else "0";
sel_tmp6_fu_470_p2 <= "1" when (gamma_read_reg_750 = ap_const_lv8_5) else "0";
sel_tmp8_fu_475_p2 <= "1" when (gamma_read_reg_750 = ap_const_lv8_4) else "0";
sel_tmp_fu_455_p2 <= "1" when (gamma_read_reg_750 = ap_const_lv8_8) else "0";
t_V_1_cast_i_i_fu_552_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(t_V_2_reg_444),12));
t_V_cast_i_i_fu_537_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(t_V_reg_433),12));
tmp_26_1_i_i_fu_578_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_10_reg_852),64));
tmp_26_2_i_i_fu_589_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_11_reg_858),64));
tmp_26_i_i_fu_567_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_9_reg_846),64));
end behav;
|
mit
|
b96f96575e3fd7d4435441ee0ad9f2b5
| 0.596554 | 2.666165 | false | false | false | false |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx
|
Frecuencimentro/CountEventsDown.vhd
| 1 | 1,192 |
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity CountEventsDown is
Port (
entrada_clk : in STD_LOGIC;
reset : in STD_LOGIC;
salida : out STD_LOGIC
);
end CountEventsDown;
architecture Behavioral of CountEventsDown is
constant cantidad: positive:=1000;
signal temporal: STD_LOGIC;
signal counter: positive:=cantidad;
begin process(entrada_clk)
begin
if reset='1' then
counter <= cantidad;
elsif rising_edge(entrada_clk) then
counter <= counter-1;
end if;
if counter=0 then
temporal<='1';
counter <= cantidad;
else
temporal<='0';
end if;
end process;
salida<=temporal;
end Behavioral;
|
gpl-2.0
|
c684db7a371532d9ec22ebae64e96d80
| 0.584732 | 4.350365 | false | false | false | false |
freecores/w11
|
rtl/vlib/rlink/rlink_mon_sb.vhd
| 1 | 2,872 |
-- $Id: rlink_mon_sb.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rlink_mon_sb - sim
-- Description: simbus wrapper for rlink monitor
--
-- Dependencies: simbus
-- simlib/simclkcnt
-- rlink_mon
-- Test bench: -
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 3.1 use simclkcnt instead of simbus global
-- 2010-12-24 347 3.0.1 rename: CP_*->RL->*
-- 2010-12-22 346 3.0 renamed rritb_cpmon_sb -> rlink_mon_sb
-- 2010-05-02 287 1.0.1 use sbcntl_sbf_cpmon def
-- 2007-08-25 75 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.rlinklib.all;
entity rlink_mon_sb is -- simbus wrap for rlink monitor
generic (
DWIDTH : positive := 9; -- data port width (8 or 9)
ENAPIN : integer := sbcntl_sbf_rlmon); -- SB_CNTL signal to use for enable
port (
CLK : in slbit; -- clock
RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : in slbit; -- rlink: data busy
RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out
RL_VAL : in slbit; -- rlink: data valid
RL_HOLD : in slbit -- rlink: data hold
);
end rlink_mon_sb;
architecture sim of rlink_mon_sb is
signal ENA : slbit := '0';
signal CLK_CYCLE : integer := 0;
begin
assert ENAPIN>=SB_CNTL'low and ENAPIN<=SB_CNTL'high
report "assert(ENAPIN in SB_CNTL'range)" severity failure;
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
ENA <= to_x01(SB_CNTL(ENAPIN));
CPMON : rlink_mon
generic map (
DWIDTH => DWIDTH)
port map (
CLK => CLK,
CLK_CYCLE => CLK_CYCLE,
ENA => ENA,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY,
RL_DO => RL_DO,
RL_VAL => RL_VAL,
RL_HOLD => RL_HOLD
);
end sim;
|
gpl-2.0
|
b0b618602a2dbe2de23d83560bb67238
| 0.56337 | 3.572139 | false | false | false | false |
freecores/w11
|
rtl/w11a/pdp11_irq.vhd
| 2 | 4,831 |
-- $Id: pdp11_irq.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_irq - syn
-- Description: pdp11: interrupt requester
--
-- Dependencies: ib_sel
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 use ib_sel
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2008-08-22 161 1.1.4 use iblib
-- 2008-04-25 138 1.1.3 use BRESET to clear pirq
-- 2008-01-06 111 1.1.2 rename signal EI_ACK->EI_ACKM (master ack)
-- 2008-01-05 110 1.1.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
-- 2007-10-12 88 1.0.2 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_irq is -- interrupt requester
port (
CLK : in slbit; -- clock
BRESET : in slbit; -- ibus reset
INT_ACK : in slbit; -- interrupt acknowledge from CPU
EI_PRI : in slv3; -- external interrupt priority
EI_VECT : in slv9_2; -- external interrupt vector
EI_ACKM : out slbit; -- external interrupt acknowledge
PRI : out slv3; -- interrupt priority
VECT : out slv9_2; -- interrupt vector
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end pdp11_irq;
architecture syn of pdp11_irq is
constant ibaddr_pirq : slv16 := slv(to_unsigned(8#177772#,16));
subtype pirq_ubf_pir is integer range 15 downto 9;
subtype pirq_ubf_pia_h is integer range 7 downto 5;
subtype pirq_ubf_pia_l is integer range 3 downto 1;
signal IBSEL_PIRQ : slbit := '0';
signal R_PIRQ : slv8_1 := (others => '0'); -- pirq register
signal PI_PRI : slv3 := (others => '0'); -- prog.int. priority
-- attribute PRIORITY_EXTRACT : string;
-- attribute PRIORITY_EXTRACT of PI_PRI : signal is "force";
begin
SEL : ib_sel
generic map (
IB_ADDR => ibaddr_pirq)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_PIRQ
);
proc_ibres : process (IBSEL_PIRQ, IB_MREQ, R_PIRQ, PI_PRI)
variable idout : slv16 := (others=>'0');
begin
idout := (others=>'0');
if IBSEL_PIRQ = '1' then
idout(pirq_ubf_pir) := R_PIRQ;
idout(pirq_ubf_pia_h) := PI_PRI;
idout(pirq_ubf_pia_l) := PI_PRI;
end if;
IB_SRES.dout <= idout;
IB_SRES.ack <= IBSEL_PIRQ and (IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES.busy <= '0';
end process proc_ibres;
proc_pirq : process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_PIRQ <= (others => '0');
elsif IBSEL_PIRQ='1' and IB_MREQ.we='1'and IB_MREQ.be1='1' then
R_PIRQ <= IB_MREQ.din(pirq_ubf_pir);
end if;
end if;
end process proc_pirq;
PI_PRI <= "111" when R_PIRQ(7)='1' else
"110" when R_PIRQ(6)='1' else
"101" when R_PIRQ(5)='1' else
"100" when R_PIRQ(4)='1' else
"011" when R_PIRQ(3)='1' else
"010" when R_PIRQ(2)='1' else
"001" when R_PIRQ(1)='1' else
"000";
proc_irq : process (PI_PRI, EI_PRI, EI_VECT, INT_ACK)
constant vect_default : slv9 := slv(to_unsigned(8#240#,9));
begin
EI_ACKM <= '0';
if unsigned(EI_PRI) > unsigned(PI_PRI) then
PRI <= EI_PRI;
VECT <= EI_VECT;
EI_ACKM <= INT_ACK;
else
PRI <= PI_PRI;
VECT <= vect_default(8 downto 2);
end if;
end process proc_irq;
end syn;
|
gpl-2.0
|
bfd52c886b81fb36444d6be4f082b269
| 0.55827 | 3.334023 | false | false | false | false |
freecores/w11
|
rtl/bplib/nxcramlib/nx_cram_dummy.vhd
| 2 | 2,403 |
-- $Id: nx_cram_dummy.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: nx_cram_dummy - syn
-- Description: nexys2/3: CRAM protection dummy
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.2 renamed from n2_cram_dummy
-- 2011-11-23 432 1.1 remove O_FLA_CE_N port
-- 2010-05-28 295 1.0.1 use _ADV_N
-- 2010-05-21 292 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity nx_cram_dummy is -- CRAM protection dummy
port (
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end nx_cram_dummy;
architecture syn of nx_cram_dummy is
begin
O_MEM_CE_N <= '1'; -- disable cram chip
O_MEM_BE_N <= "11";
O_MEM_WE_N <= '1';
O_MEM_OE_N <= '1';
O_MEM_ADV_N <= '1';
O_MEM_CLK <= '0';
O_MEM_CRE <= '0';
O_MEM_ADDR <= (others=>'0');
IO_MEM_DATA <= (others=>'0');
end syn;
|
gpl-2.0
|
5101059fd3cdd3dfa8126cf266e9fbb9
| 0.554307 | 3.332871 | false | false | false | false |
freecores/w11
|
rtl/vlib/memlib/ram_2swsr_wfirst_gen_unisim.vhd
| 2 | 3,007 |
-- $Id: ram_2swsr_wfirst_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2008- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ram_2swsr_wfirst_gen - syn
-- Description: Dual-Port RAM with with two synchronous read/write ports
-- and 'read-through' semantics (as block RAM).
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2008-03-08 123 1.1 use now ram_2swsr_xfirst_gen_unisim
-- 2008-03-02 122 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
use work.memlib.all;
entity ram_2swsr_wfirst_gen is -- RAM, 2 sync r/w ports, write first
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9); -- data port width
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end ram_2swsr_wfirst_gen;
architecture syn of ram_2swsr_wfirst_gen is
begin
UMEM: ram_2swsr_xfirst_gen_unisim
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH,
WRITE_MODE => "WRITE_FIRST")
port map (
CLKA => CLKA,
CLKB => CLKB,
ENA => ENA,
ENB => ENB,
WEA => WEA,
WEB => WEB,
ADDRA => ADDRA,
ADDRB => ADDRB,
DIA => DIA,
DIB => DIB,
DOA => DOA,
DOB => DOB
);
end syn;
|
gpl-2.0
|
c4b2b11e488acadc4b194f88dee989b5
| 0.541736 | 3.726146 | false | false | false | false |
agostini01/FPGA_Neural-Network
|
source_files/neuralnet/control/output_control.vhd
| 1 | 5,376 |
--=============================================================================
-- This file is part of FPGA_NEURAL-Network.
--
-- FPGA_NEURAL-Network is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- FPGA_NEURAL-Network is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with FPGA_NEURAL-Network.
-- If not, see <http://www.gnu.org/licenses/>.
--=============================================================================
-- FILE NAME : output_control.vhd
-- PROJECT : FPGA_NEURAL-Network
-- ENTITY : OUTPUT_CONTROL
-- ARCHITECTURE : structure
--=============================================================================
-- AUTORS(s) : Agostini, N;
-- DEPARTMENT : Electrical Engineering (UFRGS)
-- DATE : Dec 14, 2014
--=============================================================================
-- Description:
--
--=============================================================================
library ieee;
use ieee.std_logic_1164.all;
use work.NN_TYPES_pkg.all;
use work.fixed_pkg.all; -- ieee_proposed for compatibility version
use ieee.numeric_std.all;
--=============================================================================
-- Entity declaration for OUTPUT_CONTROL
--=============================================================================
entity OUTPUT_CONTROL is
port (
CLK : in std_logic;
DATA_READY : in std_logic;
OUTPUT_READY : out std_logic;
NN_OUTPUT : in ARRAY_OF_SFIXED;
TARGET_VALUE : in ARRAY_OF_SFIXED;
NN_result : out std_logic_vector (1 downto 0);
NN_expected : out std_logic_vector (1 downto 0)
);
end OUTPUT_CONTROL;
--=============================================================================
-- architecture declaration
--=============================================================================
architecture STRUCTURE of OUTPUT_CONTROL is
-- Signals
signal RESULT_TMP : std_logic_vector(1 downto 0);
signal TARGET_TMP : std_logic_vector(1 downto 0);
signal READY_1 : std_logic;
signal READY_2 : std_logic;
--=============================================================================
-- architecture begin
--=============================================================================
begin
OUTPUT_CONVERSION: process (CLK,NN_OUTPUT,DATA_READY)
begin
if CLK'event and CLK ='1' then
if DATA_READY='1' then
READY_1<='0';
if NN_OUTPUT(0)<=to_sfixed(0.5,U_SIZE,L_SIZE)
and NN_OUTPUT(1)<=to_sfixed(0.5,U_SIZE,L_SIZE)
and NN_OUTPUT(2)<=to_sfixed(0.5,U_SIZE,L_SIZE) then
RESULT_TMP<=std_logic_vector(to_unsigned(0,2));
elsif NN_OUTPUT(0)>to_sfixed(0.5,U_SIZE,L_SIZE)
and NN_OUTPUT(1)<=to_sfixed(0.5,U_SIZE,L_SIZE)
and NN_OUTPUT(2)<=to_sfixed(0.5,U_SIZE,L_SIZE) then
RESULT_TMP<=std_logic_vector(to_unsigned(1,2));
elsif NN_OUTPUT(0)<=to_sfixed(0.5,U_SIZE,L_SIZE)
and NN_OUTPUT(1)>to_sfixed(0.5,U_SIZE,L_SIZE)
and NN_OUTPUT(2)<=to_sfixed(0.5,U_SIZE,L_SIZE) then
RESULT_TMP<=std_logic_vector(to_unsigned(2,2));
elsif NN_OUTPUT(0)<=to_sfixed(0.5,U_SIZE,L_SIZE)
and NN_OUTPUT(1)<=to_sfixed(0.5,U_SIZE,L_SIZE)
and NN_OUTPUT(2)>to_sfixed(0.5,U_SIZE,L_SIZE) then
RESULT_TMP<=std_logic_vector(to_unsigned(3,2));
end if;
READY_1<='1';
else
READY_1<='0';
end if;
end if;
end process;
TARGET_CONVERSION: process (CLK,TARGET_VALUE,DATA_READY)
begin
if CLK'event and CLK ='1' then
if DATA_READY='1' then
READY_2<='0';
if NN_OUTPUT(0)<=to_sfixed(0.5,U_SIZE,L_SIZE)
and TARGET_VALUE(1)<=to_sfixed(0.5,U_SIZE,L_SIZE)
and TARGET_VALUE(2)<=to_sfixed(0.5,U_SIZE,L_SIZE) then
TARGET_TMP<=std_logic_vector(to_unsigned(0,2));
elsif TARGET_VALUE(0)>to_sfixed(0.5,U_SIZE,L_SIZE)
and TARGET_VALUE(1)<=to_sfixed(0.5,U_SIZE,L_SIZE)
and TARGET_VALUE(2)<=to_sfixed(0.5,U_SIZE,L_SIZE) then
TARGET_TMP<=std_logic_vector(to_unsigned(1,2));
elsif TARGET_VALUE(0)<=to_sfixed(0.5,U_SIZE,L_SIZE)
and TARGET_VALUE(1)>to_sfixed(0.5,U_SIZE,L_SIZE)
and TARGET_VALUE(2)<=to_sfixed(0.5,U_SIZE,L_SIZE) then
TARGET_TMP<=std_logic_vector(to_unsigned(2,2));
elsif TARGET_VALUE(0)<=to_sfixed(0.5,U_SIZE,L_SIZE)
and TARGET_VALUE(1)<=to_sfixed(0.5,U_SIZE,L_SIZE)
and TARGET_VALUE(2)>to_sfixed(0.5,U_SIZE,L_SIZE) then
TARGET_TMP<=std_logic_vector(to_unsigned(3,2));
end if;
READY_2<='1';
else
READY_2<='0';
end if;
end if;
end process;
-- TODO!! correct readyness
NN_result<=RESULT_TMP;
NN_expected<=TARGET_TMP;
OUTPUT_READY<=READY_1 and READY_2;
end STRUCTURE;
--=============================================================================
-- architecture end
--=============================================================================
|
gpl-3.0
|
facebf8310a0a8f8ad6b96056250e4bf
| 0.517299 | 3.391798 | false | false | false | false |
unhold/hdl
|
vhdl/example/safe_state_machine.vhd
| 1 | 3,559 |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.state_pack.all;
-- Example for a unit implementing a safe state machine using state_pack.
entity safe_state_machine is
generic (
encoding : encoding_t);
port (
clock_i : in std_logic;
reset_i : in std_logic := '0'; -- Asynchronous reset, default value indicates that this unit can work without initial reset, for FPGA designs.
enable_i : in std_logic := '1'; -- Clock enable, may be used to divide the clock.
error_o : out std_logic;
state_inject_i : in inject_t := inject_off_c);
end;
architecture rtl of safe_state_machine is
type my_enum_t is (a, b, c);
constant my_enum_len_c : natural := my_enum_t'pos(my_enum_t'right) + 1;
subtype my_enum_code_t is code_t(code_length(my_enum_len_c, encoding)-1 downto 0);
type state_t is record
my_enum_code : my_enum_code_t;
end record;
constant reset_state_c : state_t := (
my_enum_code => encode(my_enum_t'pos(a), my_enum_len_c, encoding));
-- If your implementation tool is smart enough to for sequential optimizations,
-- you have to set the appropirate attribute to avoid recoding of the state!
-- This may be a VHDL attribute, a TCL command or another tool-specific setting.
-- Using the state_inject_i input and making it externally controllabe
-- will also avoid optimizations and preserve the state encoding.
signal state, next_state : state_t := reset_state_c;
-- Initial value required for FPGA designs without reset.
-- Disable sequential optimizations for Synopsys and Synplicity.
attribute syn_preserve : boolean;
attribute syn_preserve of state : signal is true;
begin
process(clock_i, reset_i)
begin
if reset_i = '1' then
state <= reset_state_c;
elsif rising_edge(clock_i) then
if enable_i = '1' then
state <= next_state;
end if;
end if;
end process;
process(state, state_inject_i)
variable my_enum_v, next_my_enum_v : my_enum_t;
begin
error_o <= '0';
if error(state.my_enum_code, encoding) then
-- Handle uncorrectable errors.
-- Optional, as only some encodings can have errors that are detectable but not correctable.
my_enum_v := a;
error_o <= '1';
else
-- Decode.
my_enum_v := my_enum_t'val(decode(state.my_enum_code, encoding));
end if;
-- State machine logic.
case my_enum_v is
when a => next_my_enum_v := b;
when b => next_my_enum_v := c;
when c => next_my_enum_v := a;
end case;
-- Encode and handle state injection.
next_state <= (
my_enum_code => handle_inject(
encode(my_enum_t'pos(next_my_enum_v), my_enum_len_c, encoding),
state_inject_i));
end process;
end;
entity safe_state_machine_tb is
end;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.state_pack.all;
use work.tb_pack.all;
architecture tb of safe_state_machine_tb is
signal run : boolean := true;
signal clock_i : std_ulogic;
signal state_inject_i : inject_t;
begin
clk_gen(clock_i, run);
ssme_gen : for encoding in encoding_t generate
ssme : entity work.safe_state_machine
generic map (
encoding => encoding)
port map (
clock_i => clock_i,
state_inject_i => state_inject_i);
end generate;
process
begin
wait_clk(clock_i, 5);
state_inject_i <= (
index => 1,
write => true);
wait_clk(clock_i, 1);
state_inject_i <= inject_off_c;
wait_clk(clock_i, 1);
state_inject_i <= (
index => 1,
write => true);
wait_clk(clock_i, 1);
state_inject_i <= inject_off_c;
wait_clk(clock_i, 1);
wait_clk(clock_i, 5);
run <= false;
wait;
end process;
end;
|
gpl-3.0
|
e14411797223a839f080251ec61c390c
| 0.674909 | 2.912439 | false | false | false | false |
freecores/w11
|
rtl/vlib/genlib/gray_cnt_gen.vhd
| 2 | 2,392 |
-- $Id: gray_cnt_gen.vhd 418 2011-10-23 20:11:40Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: gray_cnt_gen - syn
-- Description: Generic width Gray code counter
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-26 106 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.genlib.all;
entity gray_cnt_gen is -- gray code counter, generic vector
generic (
DWIDTH : positive := 4); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv(DWIDTH-1 downto 0) -- data out
);
end entity gray_cnt_gen;
architecture syn of gray_cnt_gen is
begin
assert DWIDTH>=4
report "assert(DWIDTH>=4): only 4 or more bit width supported"
severity failure;
GRAY_4: if DWIDTH=4 generate
begin
CNT : gray_cnt_4
port map (
CLK => CLK,
RESET => RESET,
CE => CE,
DATA => DATA
);
end generate GRAY_4;
GRAY_5: if DWIDTH=5 generate
begin
CNT : gray_cnt_5
port map (
CLK => CLK,
RESET => RESET,
CE => CE,
DATA => DATA
);
end generate GRAY_5;
GRAY_N: if DWIDTH>5 generate
begin
CNT : gray_cnt_n
generic map (
DWIDTH => DWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CE => CE,
DATA => DATA
);
end generate GRAY_N;
end syn;
|
gpl-2.0
|
6c9f79fa7416bf7c4a5f4a318475a892
| 0.548495 | 3.87055 | false | false | false | false |
unhold/hdl
|
vhdl/rtl_pack.vhd
| 1 | 2,931 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! General purpose definitions and functions for RTL code.
package rtl_pack is
function to_bit(value : boolean) return bit;
function to_stdulogic(value : boolean) return std_ulogic;
subtype base_t is natural range 2 to natural'high;
--! Calculate the logarithm of 'number' to given 'base', rounding up.
function log_ceil(number : positive; base : base_t := 2) return natural;
--! Round 'number' up to the next multiple of 'factor'.
function next_multiple(number : natural; factor : positive) return natural;
--! Reverse the bits of a vector.
--! The Direction of the range stays the same.
function reverse(vector : std_ulogic_vector) return std_ulogic_vector;
--! Count the number of '1's in a vector.
function one_count(vector : std_ulogic_vector) return natural;
--! Check constant conditions in declarative sections.
function check(
condition : boolean;
name : string := "(unnamed)";
sl : severity_level := error) return boolean;
function maximum(a, b : integer) return integer;
function minimum(a, b : integer) return integer;
end;
package body rtl_pack is
function to_bit(value : boolean) return bit is
begin
if value then return '1';
else return '0';
end if;
end;
function to_stdulogic(value : boolean) return std_ulogic is
begin
if value then return '1';
else return '0';
end if;
end;
function log_ceil(number : positive; base : base_t := 2) return natural is
variable climb : positive := 1;
variable result : natural := 0;
begin
while climb < number loop
climb := climb * base;
result := result + 1;
end loop;
return result;
end;
function next_multiple(number : natural; factor : positive) return natural is
variable result : natural := 0;
begin
while result < number loop
result := result + factor;
end loop;
return result;
end;
function reverse(vector : std_ulogic_vector) return std_ulogic_vector is
alias renumbered : std_ulogic_vector(vector'reverse_range) is vector;
variable result : std_ulogic_vector(vector'range);
begin
for i in vector'range loop
result(i) := renumbered(i);
end loop;
return result;
end;
function one_count(vector : std_ulogic_vector) return natural is
variable result : natural := 0;
begin
for i in vector'range loop
if to_X01(vector(i)) = '1' then
result := result + 1;
end if;
end loop;
return result;
end;
function check(
condition : boolean;
name : string := "(unnamed)";
sl : severity_level := error) return boolean is
begin
assert condition report "rtl_pack.check failed: " & name severity sl;
return condition;
end;
function maximum(a, b : integer) return integer is
begin
if a > b then return a;
else return b;
end if;
end;
function minimum(a, b : integer) return integer is
begin
if a < b then return a;
else return b;
end if;
end;
end;
|
gpl-3.0
|
79a3feeca197fd4b66109587da584488
| 0.69362 | 3.319366 | false | false | false | false |
alphaFred/Sejits4Fpgas
|
sejits4fpgas/hw/user/LimitTo.vhd
| 1 | 1,048 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity LimitTo is
Generic(
VALID_BITS : positive
);
Port (
CLK : in std_logic;
RST : in std_logic; -- low active
VALID_IN : in std_logic; -- high active
READY_IN : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
VALID_OUT : out std_logic; -- high active
READY_OUT : out std_logic;
DATA_OUT : out std_logic_vector(31 downto 0)
);
end LimitTo;
architecture limit_to_behave of LimitTo is
begin
slice_full: if VALID_BITS >= 32 generate
begin
DATA_OUT <= DATA_IN;
end generate slice_full;
slice_limit: if VALID_BITS < 32 generate
begin
DATA_OUT <= (31 downto VALID_BITS => '0') & DATA_IN(VALID_BITS-1 downto 0);
end generate slice_limit;
VALID_OUT <= VALID_IN;
READY_OUT <= READY_IN;
end limit_to_behave;
|
gpl-3.0
|
396a02b7322dc3acf95ec2d0f33d9ee4
| 0.56584 | 3.540541 | false | false | false | false |
unhold/hdl
|
vhdl/greycode_pack.vhd
| 1 | 1,963 |
library ieee;
use ieee.std_logic_1164.all;
package greycode_pack is
subtype greycode_t is std_ulogic_vector;
function to_greycode(binary : std_ulogic_vector) return greycode_t;
function to_binary(greycode : greycode_t) return std_ulogic_vector;
function "+"(lhs : greycode_t; rhs : integer) return greycode_t;
end;
library ieee;
use ieee.numeric_std.all;
use ieee.numeric_std_unsigned.all;
library work;
use work.rtl_pack;
package body greycode_pack is
function to_greycode_bitwise(binary : std_ulogic_vector) return greycode_t is
variable greycode : greycode_t(binary'range);
begin
greycode(binary'high) := binary(binary'high);
for i in binary'high-1 downto binary'low loop
greycode(i) := binary(i+1) xor binary(i);
end loop;
return greycode;
end;
-- Same logic as to_greycode_bitwise, but shorter.
function to_greycode(binary : std_ulogic_vector) return greycode_t is
variable greycode : greycode_t(binary'range);
begin
return binary xor shift_right(binary, 1);
end;
-- Simple implementation with least XORs (b-1) and most logic depth (b-1).
function to_binary_linear(greycode : greycode_t) return std_ulogic_vector is
variable binary : std_ulogic_vector(greycode'range);
begin
binary(greycode'high) := greycode(greycode'high);
for i in greycode'high-1 downto greycode'low loop
binary(i) := binary(i+1) xor greycode(i);
end loop;
return binary;
end;
-- Convoluted implementation with depth log_ceil(b) but more resources.
function to_binary(greycode : greycode_t) return std_ulogic_vector is
variable shift : natural := rtl_pack.log_ceil(greycode'length);
variable result : std_ulogic_vector(greycode'range) := greycode;
begin
while shift /= 0 loop
result := result xor shift_right(result, 2**shift);
end loop;
return result;
end;
function "+"(lhs : greycode_t; rhs : integer) return greycode_t is
begin
return to_greycode(std_ulogic_vector(unsigned(to_binary(lhs)) + rhs));
end;
end;
|
gpl-3.0
|
9391a2e0ef7e32b500a3543fa8ba45cd
| 0.732552 | 3.228618 | false | false | false | false |
unhold/hdl
|
vhdl/stb_gen.vhd
| 1 | 741 |
library ieee;
use ieee.std_logic_1164.all;
entity stb_gen is
generic (
period_g : in positive);
port (
rst_i : in std_ulogic := '0';
clk_i : in std_ulogic;
sync_rst_i : in std_ulogic := '0';
stb_i : in std_ulogic := '1';
stb_o : out std_ulogic);
end;
architecture rtl of stb_gen is
signal stb : std_ulogic := '0';
signal cnt : natural range 0 to period_g-1 := 0;
begin
process(rst_i, clk_i)
begin
if rst_i = '1' then
stb <= '0';
cnt <= 0;
elsif rising_edge(clk_i) then
stb <= '0';
if sync_rst_i = '1' then
cnt <= 0;
elsif stb_i = '1' then
if cnt = period_g-1 then
stb <= '1';
cnt <= 0;
else
cnt <= cnt + 1;
end if;
end if;
end if;
end process;
stb_o <= stb;
end;
|
gpl-3.0
|
169fa01a73e9a0fa2a21dfffeb60a909
| 0.557355 | 2.4375 | false | false | false | false |
GOOD-Stuff/srio_test
|
srio_test.srcs/sources_1/ip/vio_0/vio_0_sim_netlist.vhdl
| 1 | 490,683 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Mon Sep 18 12:32:27 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim
-- C:/Projects/srio_test/srio_test/srio_test.srcs/sources_1/ip/vio_0/vio_0_sim_netlist.vhdl
-- Design : vio_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vio_0_vio_v3_0_13_decoder is
port (
s_drdy_i : out STD_LOGIC;
\wr_en_reg[4]_0\ : out STD_LOGIC;
\wr_en_reg[4]_1\ : out STD_LOGIC;
\wr_en_reg[4]_2\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_do_i : out STD_LOGIC_VECTOR ( 15 downto 0 );
s_rst_o : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
\out\ : in STD_LOGIC;
s_daddr_o : in STD_LOGIC_VECTOR ( 16 downto 0 );
s_dwe_o : in STD_LOGIC;
s_den_o : in STD_LOGIC;
\Bus_Data_out_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vio_0_vio_v3_0_13_decoder : entity is "vio_v3_0_13_decoder";
end vio_0_vio_v3_0_13_decoder;
architecture STRUCTURE of vio_0_vio_v3_0_13_decoder is
signal Hold_probe_in : STD_LOGIC;
signal clear_int : STD_LOGIC;
signal committ_int : STD_LOGIC;
signal \data_info_probe_in__67\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal int_cnt_rst : STD_LOGIC;
signal probe_out_modified : STD_LOGIC_VECTOR ( 15 downto 0 );
signal rd_en_p1 : STD_LOGIC;
signal rd_en_p2 : STD_LOGIC;
signal wr_control_reg : STD_LOGIC;
signal \wr_en[2]_i_1_n_0\ : STD_LOGIC;
signal \wr_en[2]_i_2_n_0\ : STD_LOGIC;
signal \wr_en[4]_i_1_n_0\ : STD_LOGIC;
signal \wr_en[4]_i_6_n_0\ : STD_LOGIC;
signal \^wr_en_reg[4]_0\ : STD_LOGIC;
signal \^wr_en_reg[4]_1\ : STD_LOGIC;
signal \^wr_en_reg[4]_2\ : STD_LOGIC;
signal wr_probe_out_modified : STD_LOGIC;
signal xsdb_addr_2_0_p1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xsdb_addr_2_0_p2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xsdb_addr_8_p1 : STD_LOGIC;
signal xsdb_addr_8_p2 : STD_LOGIC;
signal xsdb_drdy_i_1_n_0 : STD_LOGIC;
signal xsdb_rd : STD_LOGIC;
signal xsdb_wr : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \Bus_data_out[12]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \Bus_data_out[13]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \Bus_data_out[14]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \Bus_data_out[15]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \wr_en[2]_i_2\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \wr_en[4]_i_2\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \wr_en[4]_i_6\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of xsdb_drdy_i_1 : label is "soft_lutpair14";
begin
\wr_en_reg[4]_0\ <= \^wr_en_reg[4]_0\;
\wr_en_reg[4]_1\ <= \^wr_en_reg[4]_1\;
\wr_en_reg[4]_2\ <= \^wr_en_reg[4]_2\;
\Bus_data_out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AF00AF000FC000C0"
)
port map (
I0 => \Bus_Data_out_reg[11]\(0),
I1 => probe_out_modified(0),
I2 => xsdb_addr_2_0_p2(2),
I3 => xsdb_addr_2_0_p2(1),
I4 => committ_int,
I5 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(0)
);
\Bus_data_out[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(10),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(10),
O => \data_info_probe_in__67\(10)
);
\Bus_data_out[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(11),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(11),
O => \data_info_probe_in__67\(11)
);
\Bus_data_out[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(12),
I3 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(12)
);
\Bus_data_out[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(13),
I3 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(13)
);
\Bus_data_out[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(14),
I3 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(14)
);
\Bus_data_out[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(15),
I3 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(15)
);
\Bus_data_out[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0000FC0A00000C0"
)
port map (
I0 => \Bus_Data_out_reg[11]\(1),
I1 => probe_out_modified(1),
I2 => xsdb_addr_2_0_p2(2),
I3 => xsdb_addr_2_0_p2(1),
I4 => xsdb_addr_2_0_p2(0),
I5 => clear_int,
O => \data_info_probe_in__67\(1)
);
\Bus_data_out[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A000000F00CFCF"
)
port map (
I0 => \Bus_Data_out_reg[11]\(2),
I1 => probe_out_modified(2),
I2 => xsdb_addr_2_0_p2(2),
I3 => int_cnt_rst,
I4 => xsdb_addr_2_0_p2(1),
I5 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(2)
);
\Bus_data_out[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(3),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(3),
O => \data_info_probe_in__67\(3)
);
\Bus_data_out[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(4),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(4),
O => \data_info_probe_in__67\(4)
);
\Bus_data_out[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(5),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(5),
O => \data_info_probe_in__67\(5)
);
\Bus_data_out[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(6),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(6),
O => \data_info_probe_in__67\(6)
);
\Bus_data_out[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(7),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(7),
O => \data_info_probe_in__67\(7)
);
\Bus_data_out[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(8),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(8),
O => \data_info_probe_in__67\(8)
);
\Bus_data_out[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(9),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(9),
O => \data_info_probe_in__67\(9)
);
\Bus_data_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(0),
Q => s_do_i(0),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(10),
Q => s_do_i(10),
R => xsdb_addr_8_p2
);
\bus_data_out_reg[11]_RnM\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(11),
Q => s_do_i(11),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(12),
Q => s_do_i(12),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(13),
Q => s_do_i(13),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(14),
Q => s_do_i(14),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(15),
Q => s_do_i(15),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(1),
Q => s_do_i(1),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(2),
Q => s_do_i(2),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(3),
Q => s_do_i(3),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(4),
Q => s_do_i(4),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(5),
Q => s_do_i(5),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(6),
Q => s_do_i(6),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(7),
Q => s_do_i(7),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(8),
Q => s_do_i(8),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(9),
Q => s_do_i(9),
R => xsdb_addr_8_p2
);
Hold_probe_in_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(3),
Q => Hold_probe_in,
R => s_rst_o
);
clear_int_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(1),
Q => clear_int,
R => s_rst_o
);
committ_int_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(0),
Q => committ_int,
R => s_rst_o
);
int_cnt_rst_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(2),
Q => int_cnt_rst,
R => s_rst_o
);
\probe_in_reg[3]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => Hold_probe_in,
O => E(0)
);
\probe_out_modified_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(0),
Q => probe_out_modified(0),
R => clear_int
);
\probe_out_modified_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(10),
Q => probe_out_modified(10),
R => clear_int
);
\probe_out_modified_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(11),
Q => probe_out_modified(11),
R => clear_int
);
\probe_out_modified_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(12),
Q => probe_out_modified(12),
R => clear_int
);
\probe_out_modified_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(13),
Q => probe_out_modified(13),
R => clear_int
);
\probe_out_modified_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(14),
Q => probe_out_modified(14),
R => clear_int
);
\probe_out_modified_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(15),
Q => probe_out_modified(15),
R => clear_int
);
\probe_out_modified_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(1),
Q => probe_out_modified(1),
R => clear_int
);
\probe_out_modified_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(2),
Q => probe_out_modified(2),
R => clear_int
);
\probe_out_modified_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(3),
Q => probe_out_modified(3),
R => clear_int
);
\probe_out_modified_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(4),
Q => probe_out_modified(4),
R => clear_int
);
\probe_out_modified_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(5),
Q => probe_out_modified(5),
R => clear_int
);
\probe_out_modified_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(6),
Q => probe_out_modified(6),
R => clear_int
);
\probe_out_modified_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(7),
Q => probe_out_modified(7),
R => clear_int
);
\probe_out_modified_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(8),
Q => probe_out_modified(8),
R => clear_int
);
\probe_out_modified_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(9),
Q => probe_out_modified(9),
R => clear_int
);
rd_en_p1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_den_o,
I1 => s_dwe_o,
O => xsdb_rd
);
rd_en_p1_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_rd,
Q => rd_en_p1,
R => s_rst_o
);
rd_en_p2_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => rd_en_p1,
Q => rd_en_p2,
R => s_rst_o
);
\wr_en[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => xsdb_wr,
I1 => s_daddr_o(2),
I2 => \^wr_en_reg[4]_0\,
I3 => \^wr_en_reg[4]_2\,
I4 => \^wr_en_reg[4]_1\,
I5 => \wr_en[2]_i_2_n_0\,
O => \wr_en[2]_i_1_n_0\
);
\wr_en[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_daddr_o(0),
I1 => s_daddr_o(1),
O => \wr_en[2]_i_2_n_0\
);
\wr_en[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000020000"
)
port map (
I0 => xsdb_wr,
I1 => \^wr_en_reg[4]_0\,
I2 => \^wr_en_reg[4]_2\,
I3 => \^wr_en_reg[4]_1\,
I4 => s_daddr_o(2),
I5 => \wr_en[4]_i_6_n_0\,
O => \wr_en[4]_i_1_n_0\
);
\wr_en[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_den_o,
I1 => s_dwe_o,
O => xsdb_wr
);
\wr_en[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => s_daddr_o(15),
I1 => s_daddr_o(16),
I2 => s_daddr_o(13),
I3 => s_daddr_o(14),
I4 => s_daddr_o(4),
I5 => s_daddr_o(3),
O => \^wr_en_reg[4]_0\
);
\wr_en[4]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => s_daddr_o(6),
I1 => s_daddr_o(5),
I2 => s_daddr_o(8),
I3 => s_daddr_o(7),
O => \^wr_en_reg[4]_2\
);
\wr_en[4]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => s_daddr_o(10),
I1 => s_daddr_o(9),
I2 => s_daddr_o(12),
I3 => s_daddr_o(11),
O => \^wr_en_reg[4]_1\
);
\wr_en[4]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_daddr_o(0),
I1 => s_daddr_o(1),
O => \wr_en[4]_i_6_n_0\
);
\wr_en_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \wr_en[2]_i_1_n_0\,
Q => wr_control_reg,
R => '0'
);
\wr_en_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \wr_en[4]_i_1_n_0\,
Q => wr_probe_out_modified,
R => '0'
);
\xsdb_addr_2_0_p1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(0),
Q => xsdb_addr_2_0_p1(0),
R => '0'
);
\xsdb_addr_2_0_p1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(1),
Q => xsdb_addr_2_0_p1(1),
R => '0'
);
\xsdb_addr_2_0_p1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(2),
Q => xsdb_addr_2_0_p1(2),
R => '0'
);
\xsdb_addr_2_0_p2_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_addr_2_0_p1(0),
Q => xsdb_addr_2_0_p2(0),
R => '0'
);
\xsdb_addr_2_0_p2_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_addr_2_0_p1(1),
Q => xsdb_addr_2_0_p2(1),
R => '0'
);
\xsdb_addr_2_0_p2_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_addr_2_0_p1(2),
Q => xsdb_addr_2_0_p2(2),
R => '0'
);
xsdb_addr_8_p1_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(8),
Q => xsdb_addr_8_p1,
R => '0'
);
xsdb_addr_8_p2_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_addr_8_p1,
Q => xsdb_addr_8_p2,
R => '0'
);
xsdb_drdy_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => s_dwe_o,
I1 => s_den_o,
I2 => rd_en_p2,
O => xsdb_drdy_i_1_n_0
);
xsdb_drdy_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_drdy_i_1_n_0,
Q => s_drdy_i,
R => s_rst_o
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vio_0_vio_v3_0_13_probe_in_one is
port (
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
\out\ : in STD_LOGIC;
\wr_en[4]_i_3\ : in STD_LOGIC;
\wr_en[4]_i_4\ : in STD_LOGIC;
\wr_en[4]_i_5\ : in STD_LOGIC;
s_daddr_o : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_dwe_o : in STD_LOGIC;
s_den_o : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
s_rst_o : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vio_0_vio_v3_0_13_probe_in_one : entity is "vio_v3_0_13_probe_in_one";
end vio_0_vio_v3_0_13_probe_in_one;
architecture STRUCTURE of vio_0_vio_v3_0_13_probe_in_one is
signal \DECODER_INST/rd_en_int_7\ : STD_LOGIC;
signal Read_int : STD_LOGIC;
signal Read_int_i_2_n_0 : STD_LOGIC;
signal data_int_sync1 : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of data_int_sync1 : signal is "true";
signal data_int_sync2 : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg of data_int_sync2 : signal is "true";
signal \dn_activity[0]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity[1]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity[2]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity[3]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity_reg_n_0_[0]\ : STD_LOGIC;
signal \dn_activity_reg_n_0_[3]\ : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_9_in : STD_LOGIC;
signal probe_in_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of probe_in_reg : signal is std.standard.true;
signal read_done : STD_LOGIC;
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of read_done : signal is "200";
attribute RTL_MAX_FANOUT : string;
attribute RTL_MAX_FANOUT of read_done : signal is "found";
signal read_done_i_1_n_0 : STD_LOGIC;
signal \up_activity[0]_i_1_n_0\ : STD_LOGIC;
signal \up_activity[1]_i_1_n_0\ : STD_LOGIC;
signal \up_activity[2]_i_1_n_0\ : STD_LOGIC;
signal \up_activity[3]_i_1_n_0\ : STD_LOGIC;
signal \up_activity_reg_n_0_[0]\ : STD_LOGIC;
signal \up_activity_reg_n_0_[1]\ : STD_LOGIC;
signal \up_activity_reg_n_0_[2]\ : STD_LOGIC;
signal \up_activity_reg_n_0_[3]\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \data_int_sync1_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \data_int_sync1_reg[0]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync1_reg[1]\ : label is std.standard.true;
attribute KEEP of \data_int_sync1_reg[1]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync1_reg[2]\ : label is std.standard.true;
attribute KEEP of \data_int_sync1_reg[2]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync1_reg[3]\ : label is std.standard.true;
attribute KEEP of \data_int_sync1_reg[3]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[0]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[0]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[1]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[1]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[2]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[2]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[3]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[3]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[0]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[1]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[2]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[3]\ : label is "yes";
attribute RTL_MAX_FANOUT of read_done_reg : label is "found";
begin
\Bus_Data_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(0),
Q => Q(0),
R => '0'
);
\Bus_Data_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_9_in,
Q => Q(10),
R => '0'
);
\Bus_Data_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \dn_activity_reg_n_0_[3]\,
Q => Q(11),
R => '0'
);
\Bus_Data_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(1),
Q => Q(1),
R => '0'
);
\Bus_Data_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(2),
Q => Q(2),
R => '0'
);
\Bus_Data_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(3),
Q => Q(3),
R => '0'
);
\Bus_Data_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[0]\,
Q => Q(4),
R => '0'
);
\Bus_Data_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[1]\,
Q => Q(5),
R => '0'
);
\Bus_Data_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[2]\,
Q => Q(6),
R => '0'
);
\Bus_Data_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[3]\,
Q => Q(7),
R => '0'
);
\Bus_Data_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \dn_activity_reg_n_0_[0]\,
Q => Q(8),
R => '0'
);
\Bus_Data_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_6_in,
Q => Q(9),
R => '0'
);
Read_int_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => Read_int_i_2_n_0,
I1 => \wr_en[4]_i_3\,
I2 => \wr_en[4]_i_4\,
I3 => \wr_en[4]_i_5\,
O => \DECODER_INST/rd_en_int_7\
);
Read_int_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => s_daddr_o(0),
I1 => s_daddr_o(1),
I2 => s_daddr_o(2),
I3 => s_dwe_o,
I4 => s_den_o,
O => Read_int_i_2_n_0
);
Read_int_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \DECODER_INST/rd_en_int_7\,
Q => Read_int,
R => '0'
);
\data_int_sync1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(0),
Q => data_int_sync1(0),
R => '0'
);
\data_int_sync1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(1),
Q => data_int_sync1(1),
R => '0'
);
\data_int_sync1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(2),
Q => data_int_sync1(2),
R => '0'
);
\data_int_sync1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(3),
Q => data_int_sync1(3),
R => '0'
);
\data_int_sync2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(0),
Q => data_int_sync2(0),
R => '0'
);
\data_int_sync2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(1),
Q => data_int_sync2(1),
R => '0'
);
\data_int_sync2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(2),
Q => data_int_sync2(2),
R => '0'
);
\data_int_sync2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(3),
Q => data_int_sync2(3),
R => '0'
);
\dn_activity[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \dn_activity_reg_n_0_[0]\,
I1 => data_int_sync1(0),
I2 => data_int_sync2(0),
O => \dn_activity[0]_i_1_n_0\
);
\dn_activity[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => p_6_in,
I1 => data_int_sync1(1),
I2 => data_int_sync2(1),
O => \dn_activity[1]_i_1_n_0\
);
\dn_activity[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => p_9_in,
I1 => data_int_sync1(2),
I2 => data_int_sync2(2),
O => \dn_activity[2]_i_1_n_0\
);
\dn_activity[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \dn_activity_reg_n_0_[3]\,
I1 => data_int_sync1(3),
I2 => data_int_sync2(3),
O => \dn_activity[3]_i_1_n_0\
);
\dn_activity_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[0]_i_1_n_0\,
Q => \dn_activity_reg_n_0_[0]\,
R => read_done
);
\dn_activity_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[1]_i_1_n_0\,
Q => p_6_in,
R => read_done
);
\dn_activity_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[2]_i_1_n_0\,
Q => p_9_in,
R => read_done
);
\dn_activity_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[3]_i_1_n_0\,
Q => \dn_activity_reg_n_0_[3]\,
R => read_done
);
\probe_in_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(0),
Q => probe_in_reg(0),
R => '0'
);
\probe_in_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(1),
Q => probe_in_reg(1),
R => '0'
);
\probe_in_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(2),
Q => probe_in_reg(2),
R => '0'
);
\probe_in_reg_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(3),
Q => probe_in_reg(3),
R => '0'
);
read_done_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => Read_int,
I1 => read_done,
I2 => s_rst_o,
O => read_done_i_1_n_0
);
read_done_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => read_done_i_1_n_0,
Q => read_done,
R => '0'
);
\up_activity[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[0]\,
I1 => data_int_sync2(0),
I2 => data_int_sync1(0),
O => \up_activity[0]_i_1_n_0\
);
\up_activity[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[1]\,
I1 => data_int_sync2(1),
I2 => data_int_sync1(1),
O => \up_activity[1]_i_1_n_0\
);
\up_activity[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[2]\,
I1 => data_int_sync2(2),
I2 => data_int_sync1(2),
O => \up_activity[2]_i_1_n_0\
);
\up_activity[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[3]\,
I1 => data_int_sync2(3),
I2 => data_int_sync1(3),
O => \up_activity[3]_i_1_n_0\
);
\up_activity_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[0]_i_1_n_0\,
Q => \up_activity_reg_n_0_[0]\,
R => read_done
);
\up_activity_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[1]_i_1_n_0\,
Q => \up_activity_reg_n_0_[1]\,
R => read_done
);
\up_activity_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[2]_i_1_n_0\,
Q => \up_activity_reg_n_0_[2]\,
R => read_done
);
\up_activity_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[3]_i_1_n_0\,
Q => \up_activity_reg_n_0_[3]\,
R => read_done
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vio_0_xsdbs_v1_0_2_xsdbs is
port (
s_rst_o : out STD_LOGIC;
s_dclk_o : out STD_LOGIC;
s_den_o : out STD_LOGIC;
s_dwe_o : out STD_LOGIC;
s_daddr_o : out STD_LOGIC_VECTOR ( 16 downto 0 );
s_di_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
sl_oport_o : out STD_LOGIC_VECTOR ( 16 downto 0 );
s_do_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
sl_iport_i : in STD_LOGIC_VECTOR ( 36 downto 0 );
s_drdy_i : in STD_LOGIC
);
attribute C_BUILD_REVISION : integer;
attribute C_BUILD_REVISION of vio_0_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_CORE_INFO1 : string;
attribute C_CORE_INFO1 of vio_0_xsdbs_v1_0_2_xsdbs : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 : string;
attribute C_CORE_INFO2 of vio_0_xsdbs_v1_0_2_xsdbs : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER : integer;
attribute C_CORE_MAJOR_VER of vio_0_xsdbs_v1_0_2_xsdbs : entity is 2;
attribute C_CORE_MINOR_VER : integer;
attribute C_CORE_MINOR_VER of vio_0_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_CORE_TYPE : integer;
attribute C_CORE_TYPE of vio_0_xsdbs_v1_0_2_xsdbs : entity is 2;
attribute C_CSE_DRV_VER : integer;
attribute C_CSE_DRV_VER of vio_0_xsdbs_v1_0_2_xsdbs : entity is 1;
attribute C_MAJOR_VERSION : integer;
attribute C_MAJOR_VERSION of vio_0_xsdbs_v1_0_2_xsdbs : entity is 2013;
attribute C_MINOR_VERSION : integer;
attribute C_MINOR_VERSION of vio_0_xsdbs_v1_0_2_xsdbs : entity is 1;
attribute C_NEXT_SLAVE : integer;
attribute C_NEXT_SLAVE of vio_0_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_PIPE_IFACE : integer;
attribute C_PIPE_IFACE of vio_0_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_USE_TEST_REG : integer;
attribute C_USE_TEST_REG of vio_0_xsdbs_v1_0_2_xsdbs : entity is 1;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of vio_0_xsdbs_v1_0_2_xsdbs : entity is "kintex7";
attribute C_XSDB_SLAVE_TYPE : integer;
attribute C_XSDB_SLAVE_TYPE of vio_0_xsdbs_v1_0_2_xsdbs : entity is 33;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vio_0_xsdbs_v1_0_2_xsdbs : entity is "xsdbs_v1_0_2_xsdbs";
attribute dont_touch : string;
attribute dont_touch of vio_0_xsdbs_v1_0_2_xsdbs : entity is "true";
end vio_0_xsdbs_v1_0_2_xsdbs;
architecture STRUCTURE of vio_0_xsdbs_v1_0_2_xsdbs is
signal reg_do : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \reg_do[10]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[10]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[15]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[1]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[2]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[3]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[4]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[5]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[6]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[7]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[8]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[9]_i_1_n_0\ : STD_LOGIC;
signal \reg_do_reg_n_0_[0]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[10]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[11]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[12]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[13]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[14]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[15]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[1]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[2]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[3]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[4]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[5]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[6]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[7]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[8]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[9]\ : STD_LOGIC;
signal reg_drdy : STD_LOGIC;
signal reg_drdy_i_1_n_0 : STD_LOGIC;
signal reg_test : STD_LOGIC_VECTOR ( 15 downto 0 );
signal reg_test0 : STD_LOGIC;
signal s_den_o_INST_0_i_1_n_0 : STD_LOGIC;
signal \^sl_iport_i\ : STD_LOGIC_VECTOR ( 36 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \reg_do[10]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \reg_do[1]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \reg_do[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \reg_do[3]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \reg_do[4]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \reg_do[5]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \reg_do[6]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \reg_do[7]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \sl_oport_o[0]_INST_0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \sl_oport_o[10]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \sl_oport_o[11]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \sl_oport_o[12]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \sl_oport_o[13]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \sl_oport_o[14]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \sl_oport_o[15]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \sl_oport_o[1]_INST_0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \sl_oport_o[2]_INST_0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \sl_oport_o[3]_INST_0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \sl_oport_o[4]_INST_0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \sl_oport_o[5]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \sl_oport_o[6]_INST_0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \sl_oport_o[7]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \sl_oport_o[8]_INST_0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \sl_oport_o[9]_INST_0\ : label is "soft_lutpair8";
begin
\^sl_iport_i\(36 downto 0) <= sl_iport_i(36 downto 0);
s_daddr_o(16 downto 0) <= \^sl_iport_i\(20 downto 4);
s_dclk_o <= \^sl_iport_i\(1);
s_di_o(15 downto 0) <= \^sl_iport_i\(36 downto 21);
s_dwe_o <= \^sl_iport_i\(3);
s_rst_o <= \^sl_iport_i\(0);
\reg_do[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BAAAFFFFAAAAAAAA"
)
port map (
I0 => \reg_do[5]_i_2_n_0\,
I1 => \^sl_iport_i\(4),
I2 => reg_test(0),
I3 => \^sl_iport_i\(6),
I4 => \^sl_iport_i\(5),
I5 => \^sl_iport_i\(8),
O => reg_do(0)
);
\reg_do[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^sl_iport_i\(5),
I1 => \reg_do[8]_i_2_n_0\,
I2 => \^sl_iport_i\(4),
O => \reg_do[10]_i_1_n_0\
);
\reg_do[10]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(10),
O => \reg_do[10]_i_2_n_0\
);
\reg_do[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"F7"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
O => \reg_do[15]_i_1_n_0\
);
\reg_do[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20220000"
)
port map (
I0 => \^sl_iport_i\(5),
I1 => \^sl_iport_i\(4),
I2 => reg_test(1),
I3 => \^sl_iport_i\(6),
I4 => \reg_do[1]_i_2_n_0\,
O => reg_do(1)
);
\reg_do[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => \^sl_iport_i\(8),
I1 => \^sl_iport_i\(10),
I2 => \^sl_iport_i\(11),
I3 => \^sl_iport_i\(7),
I4 => \^sl_iport_i\(9),
O => \reg_do[1]_i_2_n_0\
);
\reg_do[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(2),
O => \reg_do[2]_i_1_n_0\
);
\reg_do[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(3),
O => \reg_do[3]_i_1_n_0\
);
\reg_do[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(4),
O => \reg_do[4]_i_1_n_0\
);
\reg_do[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00800044"
)
port map (
I0 => \^sl_iport_i\(6),
I1 => \^sl_iport_i\(8),
I2 => reg_test(5),
I3 => \^sl_iport_i\(4),
I4 => \^sl_iport_i\(5),
I5 => \reg_do[5]_i_2_n_0\,
O => reg_do(5)
);
\reg_do[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFFFFC"
)
port map (
I0 => \^sl_iport_i\(7),
I1 => \^sl_iport_i\(8),
I2 => \^sl_iport_i\(11),
I3 => \^sl_iport_i\(10),
I4 => \^sl_iport_i\(9),
O => \reg_do[5]_i_2_n_0\
);
\reg_do[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(6),
O => \reg_do[6]_i_1_n_0\
);
\reg_do[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(7),
O => \reg_do[7]_i_1_n_0\
);
\reg_do[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F00"
)
port map (
I0 => reg_test(8),
I1 => \^sl_iport_i\(4),
I2 => \^sl_iport_i\(5),
I3 => \reg_do[8]_i_2_n_0\,
O => reg_do(8)
);
\reg_do[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000000000000"
)
port map (
I0 => \^sl_iport_i\(9),
I1 => \^sl_iport_i\(7),
I2 => \^sl_iport_i\(11),
I3 => \^sl_iport_i\(10),
I4 => \^sl_iport_i\(8),
I5 => \^sl_iport_i\(6),
O => \reg_do[8]_i_2_n_0\
);
\reg_do[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0C008000"
)
port map (
I0 => reg_test(9),
I1 => \reg_do[1]_i_2_n_0\,
I2 => \^sl_iport_i\(6),
I3 => \^sl_iport_i\(5),
I4 => \^sl_iport_i\(4),
O => \reg_do[9]_i_1_n_0\
);
\reg_do_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(0),
Q => \reg_do_reg_n_0_[0]\,
R => '0'
);
\reg_do_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[10]_i_2_n_0\,
Q => \reg_do_reg_n_0_[10]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(11),
Q => \reg_do_reg_n_0_[11]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(12),
Q => \reg_do_reg_n_0_[12]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(13),
Q => \reg_do_reg_n_0_[13]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(14),
Q => \reg_do_reg_n_0_[14]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(15),
Q => \reg_do_reg_n_0_[15]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(1),
Q => \reg_do_reg_n_0_[1]\,
R => '0'
);
\reg_do_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[2]_i_1_n_0\,
Q => \reg_do_reg_n_0_[2]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[3]_i_1_n_0\,
Q => \reg_do_reg_n_0_[3]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[4]_i_1_n_0\,
Q => \reg_do_reg_n_0_[4]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(5),
Q => \reg_do_reg_n_0_[5]\,
R => '0'
);
\reg_do_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[6]_i_1_n_0\,
Q => \reg_do_reg_n_0_[6]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[7]_i_1_n_0\,
Q => \reg_do_reg_n_0_[7]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(8),
Q => \reg_do_reg_n_0_[8]\,
R => '0'
);
\reg_do_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[9]_i_1_n_0\,
Q => \reg_do_reg_n_0_[9]\,
S => \reg_do[10]_i_1_n_0\
);
reg_drdy_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => \^sl_iport_i\(2),
I1 => s_den_o_INST_0_i_1_n_0,
I2 => \^sl_iport_i\(12),
I3 => \^sl_iport_i\(13),
I4 => \^sl_iport_i\(14),
I5 => \^sl_iport_i\(0),
O => reg_drdy_i_1_n_0
);
reg_drdy_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_drdy_i_1_n_0,
Q => reg_drdy,
R => '0'
);
\reg_test[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^sl_iport_i\(3),
I1 => \^sl_iport_i\(2),
I2 => \^sl_iport_i\(14),
I3 => \^sl_iport_i\(13),
I4 => \^sl_iport_i\(12),
I5 => s_den_o_INST_0_i_1_n_0,
O => reg_test0
);
\reg_test_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(21),
Q => reg_test(0),
R => '0'
);
\reg_test_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(31),
Q => reg_test(10),
R => '0'
);
\reg_test_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(32),
Q => reg_test(11),
R => '0'
);
\reg_test_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(33),
Q => reg_test(12),
R => '0'
);
\reg_test_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(34),
Q => reg_test(13),
R => '0'
);
\reg_test_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(35),
Q => reg_test(14),
R => '0'
);
\reg_test_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(36),
Q => reg_test(15),
R => '0'
);
\reg_test_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(22),
Q => reg_test(1),
R => '0'
);
\reg_test_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(23),
Q => reg_test(2),
R => '0'
);
\reg_test_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(24),
Q => reg_test(3),
R => '0'
);
\reg_test_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(25),
Q => reg_test(4),
R => '0'
);
\reg_test_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(26),
Q => reg_test(5),
R => '0'
);
\reg_test_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(27),
Q => reg_test(6),
R => '0'
);
\reg_test_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(28),
Q => reg_test(7),
R => '0'
);
\reg_test_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(29),
Q => reg_test(8),
R => '0'
);
\reg_test_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(30),
Q => reg_test(9),
R => '0'
);
s_den_o_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"2AAAAAAA"
)
port map (
I0 => \^sl_iport_i\(2),
I1 => \^sl_iport_i\(14),
I2 => \^sl_iport_i\(13),
I3 => \^sl_iport_i\(12),
I4 => s_den_o_INST_0_i_1_n_0,
O => s_den_o
);
s_den_o_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^sl_iport_i\(15),
I1 => \^sl_iport_i\(16),
I2 => \^sl_iport_i\(17),
I3 => \^sl_iport_i\(18),
I4 => \^sl_iport_i\(20),
I5 => \^sl_iport_i\(19),
O => s_den_o_INST_0_i_1_n_0
);
\sl_oport_o[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_drdy_i,
I1 => reg_drdy,
O => sl_oport_o(0)
);
\sl_oport_o[10]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[9]\,
I1 => s_do_i(9),
I2 => reg_drdy,
O => sl_oport_o(10)
);
\sl_oport_o[11]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[10]\,
I1 => s_do_i(10),
I2 => reg_drdy,
O => sl_oport_o(11)
);
\sl_oport_o[12]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[11]\,
I1 => s_do_i(11),
I2 => reg_drdy,
O => sl_oport_o(12)
);
\sl_oport_o[13]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[12]\,
I1 => s_do_i(12),
I2 => reg_drdy,
O => sl_oport_o(13)
);
\sl_oport_o[14]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[13]\,
I1 => s_do_i(13),
I2 => reg_drdy,
O => sl_oport_o(14)
);
\sl_oport_o[15]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[14]\,
I1 => s_do_i(14),
I2 => reg_drdy,
O => sl_oport_o(15)
);
\sl_oport_o[16]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[15]\,
I1 => s_do_i(15),
I2 => reg_drdy,
O => sl_oport_o(16)
);
\sl_oport_o[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[0]\,
I1 => s_do_i(0),
I2 => reg_drdy,
O => sl_oport_o(1)
);
\sl_oport_o[2]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[1]\,
I1 => s_do_i(1),
I2 => reg_drdy,
O => sl_oport_o(2)
);
\sl_oport_o[3]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[2]\,
I1 => s_do_i(2),
I2 => reg_drdy,
O => sl_oport_o(3)
);
\sl_oport_o[4]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[3]\,
I1 => s_do_i(3),
I2 => reg_drdy,
O => sl_oport_o(4)
);
\sl_oport_o[5]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[4]\,
I1 => s_do_i(4),
I2 => reg_drdy,
O => sl_oport_o(5)
);
\sl_oport_o[6]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[5]\,
I1 => s_do_i(5),
I2 => reg_drdy,
O => sl_oport_o(6)
);
\sl_oport_o[7]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[6]\,
I1 => s_do_i(6),
I2 => reg_drdy,
O => sl_oport_o(7)
);
\sl_oport_o[8]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[7]\,
I1 => s_do_i(7),
I2 => reg_drdy,
O => sl_oport_o(8)
);
\sl_oport_o[9]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[8]\,
I1 => s_do_i(8),
I2 => reg_drdy,
O => sl_oport_o(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vio_0_vio_v3_0_13_vio is
port (
clk : in STD_LOGIC;
probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in5 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in6 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in7 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in8 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in9 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in10 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in11 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in12 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in13 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in14 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in15 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in16 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in17 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in18 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in19 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in20 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in21 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in22 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in23 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in24 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in25 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in26 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in27 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in28 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in29 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in30 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in31 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in32 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in33 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in34 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in35 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in36 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in37 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in38 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in39 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in40 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in41 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in42 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in43 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in44 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in45 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in46 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in47 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in48 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in49 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in50 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in51 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in52 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in53 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in54 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in55 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in56 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in57 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in58 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in59 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in60 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in61 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in62 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in63 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in64 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in65 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in66 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in67 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in68 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in69 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in70 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in71 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in72 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in73 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in74 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in75 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in76 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in77 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in78 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in79 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in80 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in81 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in82 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in83 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in84 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in85 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in86 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in87 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in88 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in89 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in90 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in91 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in92 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in93 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in94 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in95 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in96 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in97 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in98 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in99 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in100 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in101 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in102 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in103 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in104 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in105 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in106 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in107 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in108 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in109 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in110 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in111 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in112 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in113 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in114 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in115 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in116 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in117 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in118 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in119 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in120 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in121 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in122 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in123 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in124 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in125 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in126 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in127 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in128 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in129 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in130 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in131 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in132 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in133 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in134 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in135 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in136 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in137 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in138 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in139 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in140 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in141 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in142 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in143 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in144 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in145 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in146 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in147 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in148 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in149 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in150 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in151 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in152 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in153 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in154 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in155 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in156 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in157 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in158 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in159 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in160 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in161 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in162 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in163 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in164 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in165 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in166 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in167 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in168 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in169 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in170 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in171 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in172 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in173 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in174 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in175 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in176 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in177 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in178 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in179 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in180 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in181 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in182 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in183 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in184 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in185 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in186 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in187 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in188 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in189 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in190 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in191 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in192 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in193 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in194 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in195 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in196 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in197 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in198 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in199 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in200 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in201 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in202 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in203 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in204 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in205 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in206 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in207 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in208 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in209 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in210 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in211 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in212 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in213 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in214 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in215 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in216 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in217 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in218 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in219 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in220 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in221 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in222 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in223 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in224 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in225 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in226 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in227 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in228 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in229 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in230 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in231 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in232 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in233 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in234 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in235 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in236 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in237 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in238 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in239 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in240 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in241 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in242 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in243 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in244 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in245 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in246 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in247 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in248 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in249 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in250 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in251 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in252 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in253 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in254 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in255 : in STD_LOGIC_VECTOR ( 0 to 0 );
sl_iport0 : in STD_LOGIC_VECTOR ( 36 downto 0 );
sl_oport0 : out STD_LOGIC_VECTOR ( 16 downto 0 );
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out3 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out13 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out15 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out16 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out17 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out18 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out19 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out20 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out21 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out22 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out23 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out24 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out25 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out26 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out27 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out28 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out29 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out30 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out31 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out32 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out33 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out34 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out35 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out36 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out37 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out38 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out39 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out40 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out41 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out42 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out43 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out44 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out45 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out46 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out47 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out48 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out49 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out50 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out51 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out52 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out53 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out54 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out55 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out56 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out57 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out58 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out59 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out60 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out61 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out62 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out63 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out64 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out65 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out66 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out67 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out68 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out69 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out70 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out71 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out72 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out73 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out74 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out75 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out76 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out77 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out78 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out79 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out80 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out81 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out82 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out83 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out84 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out85 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out86 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out87 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out88 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out89 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out90 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out91 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out92 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out93 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out94 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out95 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out96 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out97 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out98 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out99 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out100 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out101 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out102 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out103 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out104 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out105 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out106 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out107 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out108 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out109 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out110 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out111 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out112 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out113 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out114 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out115 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out116 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out117 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out118 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out119 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out120 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out121 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out122 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out123 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out124 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out125 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out126 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out127 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out128 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out129 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out130 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out131 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out132 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out133 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out134 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out135 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out136 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out137 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out138 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out139 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out140 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out141 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out142 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out143 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out144 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out145 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out146 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out147 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out148 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out149 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out150 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out151 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out152 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out153 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out154 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out155 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out156 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out157 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out158 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out159 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out160 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out161 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out162 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out163 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out164 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out165 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out166 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out167 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out168 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out169 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out170 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out171 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out172 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out173 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out174 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out175 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out176 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out177 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out178 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out179 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out180 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out181 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out182 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out183 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out184 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out185 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out186 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out187 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out188 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out189 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out190 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out191 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out192 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out193 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out194 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out195 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out196 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out197 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out198 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out199 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out200 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out201 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out202 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out203 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out204 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out205 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out206 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out207 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out208 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out209 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out210 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out211 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out212 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out213 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out214 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out215 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out216 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out217 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out218 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out219 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out220 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out221 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out222 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out223 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out224 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out225 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out226 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out227 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out228 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out229 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out230 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out231 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out232 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out233 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out234 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out235 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out236 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out237 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out238 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out239 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out240 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out241 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out242 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out243 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out244 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out245 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out246 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out247 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out248 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out249 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out250 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out251 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out252 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out253 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out254 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out255 : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_BUILD_REVISION : integer;
attribute C_BUILD_REVISION of vio_0_vio_v3_0_13_vio : entity is 0;
attribute C_BUS_ADDR_WIDTH : integer;
attribute C_BUS_ADDR_WIDTH of vio_0_vio_v3_0_13_vio : entity is 17;
attribute C_BUS_DATA_WIDTH : integer;
attribute C_BUS_DATA_WIDTH of vio_0_vio_v3_0_13_vio : entity is 16;
attribute C_CORE_INFO1 : string;
attribute C_CORE_INFO1 of vio_0_vio_v3_0_13_vio : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 : string;
attribute C_CORE_INFO2 of vio_0_vio_v3_0_13_vio : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER : integer;
attribute C_CORE_MAJOR_VER of vio_0_vio_v3_0_13_vio : entity is 2;
attribute C_CORE_MINOR_ALPHA_VER : integer;
attribute C_CORE_MINOR_ALPHA_VER of vio_0_vio_v3_0_13_vio : entity is 97;
attribute C_CORE_MINOR_VER : integer;
attribute C_CORE_MINOR_VER of vio_0_vio_v3_0_13_vio : entity is 0;
attribute C_CORE_TYPE : integer;
attribute C_CORE_TYPE of vio_0_vio_v3_0_13_vio : entity is 2;
attribute C_CSE_DRV_VER : integer;
attribute C_CSE_DRV_VER of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_EN_PROBE_IN_ACTIVITY : integer;
attribute C_EN_PROBE_IN_ACTIVITY of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_EN_SYNCHRONIZATION : integer;
attribute C_EN_SYNCHRONIZATION of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_MAJOR_VERSION : integer;
attribute C_MAJOR_VERSION of vio_0_vio_v3_0_13_vio : entity is 2013;
attribute C_MAX_NUM_PROBE : integer;
attribute C_MAX_NUM_PROBE of vio_0_vio_v3_0_13_vio : entity is 256;
attribute C_MAX_WIDTH_PER_PROBE : integer;
attribute C_MAX_WIDTH_PER_PROBE of vio_0_vio_v3_0_13_vio : entity is 256;
attribute C_MINOR_VERSION : integer;
attribute C_MINOR_VERSION of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_NEXT_SLAVE : integer;
attribute C_NEXT_SLAVE of vio_0_vio_v3_0_13_vio : entity is 0;
attribute C_NUM_PROBE_IN : integer;
attribute C_NUM_PROBE_IN of vio_0_vio_v3_0_13_vio : entity is 4;
attribute C_NUM_PROBE_OUT : integer;
attribute C_NUM_PROBE_OUT of vio_0_vio_v3_0_13_vio : entity is 0;
attribute C_PIPE_IFACE : integer;
attribute C_PIPE_IFACE of vio_0_vio_v3_0_13_vio : entity is 0;
attribute C_PROBE_IN0_WIDTH : integer;
attribute C_PROBE_IN0_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN100_WIDTH : integer;
attribute C_PROBE_IN100_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN101_WIDTH : integer;
attribute C_PROBE_IN101_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN102_WIDTH : integer;
attribute C_PROBE_IN102_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN103_WIDTH : integer;
attribute C_PROBE_IN103_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN104_WIDTH : integer;
attribute C_PROBE_IN104_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN105_WIDTH : integer;
attribute C_PROBE_IN105_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN106_WIDTH : integer;
attribute C_PROBE_IN106_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN107_WIDTH : integer;
attribute C_PROBE_IN107_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN108_WIDTH : integer;
attribute C_PROBE_IN108_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN109_WIDTH : integer;
attribute C_PROBE_IN109_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN10_WIDTH : integer;
attribute C_PROBE_IN10_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN110_WIDTH : integer;
attribute C_PROBE_IN110_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN111_WIDTH : integer;
attribute C_PROBE_IN111_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN112_WIDTH : integer;
attribute C_PROBE_IN112_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN113_WIDTH : integer;
attribute C_PROBE_IN113_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN114_WIDTH : integer;
attribute C_PROBE_IN114_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN115_WIDTH : integer;
attribute C_PROBE_IN115_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN116_WIDTH : integer;
attribute C_PROBE_IN116_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN117_WIDTH : integer;
attribute C_PROBE_IN117_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN118_WIDTH : integer;
attribute C_PROBE_IN118_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN119_WIDTH : integer;
attribute C_PROBE_IN119_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN11_WIDTH : integer;
attribute C_PROBE_IN11_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN120_WIDTH : integer;
attribute C_PROBE_IN120_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN121_WIDTH : integer;
attribute C_PROBE_IN121_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN122_WIDTH : integer;
attribute C_PROBE_IN122_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN123_WIDTH : integer;
attribute C_PROBE_IN123_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN124_WIDTH : integer;
attribute C_PROBE_IN124_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN125_WIDTH : integer;
attribute C_PROBE_IN125_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN126_WIDTH : integer;
attribute C_PROBE_IN126_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN127_WIDTH : integer;
attribute C_PROBE_IN127_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN128_WIDTH : integer;
attribute C_PROBE_IN128_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN129_WIDTH : integer;
attribute C_PROBE_IN129_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN12_WIDTH : integer;
attribute C_PROBE_IN12_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN130_WIDTH : integer;
attribute C_PROBE_IN130_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN131_WIDTH : integer;
attribute C_PROBE_IN131_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN132_WIDTH : integer;
attribute C_PROBE_IN132_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN133_WIDTH : integer;
attribute C_PROBE_IN133_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN134_WIDTH : integer;
attribute C_PROBE_IN134_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN135_WIDTH : integer;
attribute C_PROBE_IN135_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN136_WIDTH : integer;
attribute C_PROBE_IN136_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN137_WIDTH : integer;
attribute C_PROBE_IN137_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN138_WIDTH : integer;
attribute C_PROBE_IN138_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN139_WIDTH : integer;
attribute C_PROBE_IN139_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN13_WIDTH : integer;
attribute C_PROBE_IN13_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN140_WIDTH : integer;
attribute C_PROBE_IN140_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN141_WIDTH : integer;
attribute C_PROBE_IN141_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN142_WIDTH : integer;
attribute C_PROBE_IN142_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN143_WIDTH : integer;
attribute C_PROBE_IN143_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN144_WIDTH : integer;
attribute C_PROBE_IN144_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN145_WIDTH : integer;
attribute C_PROBE_IN145_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN146_WIDTH : integer;
attribute C_PROBE_IN146_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN147_WIDTH : integer;
attribute C_PROBE_IN147_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN148_WIDTH : integer;
attribute C_PROBE_IN148_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN149_WIDTH : integer;
attribute C_PROBE_IN149_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN14_WIDTH : integer;
attribute C_PROBE_IN14_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN150_WIDTH : integer;
attribute C_PROBE_IN150_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN151_WIDTH : integer;
attribute C_PROBE_IN151_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN152_WIDTH : integer;
attribute C_PROBE_IN152_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN153_WIDTH : integer;
attribute C_PROBE_IN153_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN154_WIDTH : integer;
attribute C_PROBE_IN154_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN155_WIDTH : integer;
attribute C_PROBE_IN155_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN156_WIDTH : integer;
attribute C_PROBE_IN156_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN157_WIDTH : integer;
attribute C_PROBE_IN157_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN158_WIDTH : integer;
attribute C_PROBE_IN158_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN159_WIDTH : integer;
attribute C_PROBE_IN159_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN15_WIDTH : integer;
attribute C_PROBE_IN15_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN160_WIDTH : integer;
attribute C_PROBE_IN160_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN161_WIDTH : integer;
attribute C_PROBE_IN161_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN162_WIDTH : integer;
attribute C_PROBE_IN162_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN163_WIDTH : integer;
attribute C_PROBE_IN163_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN164_WIDTH : integer;
attribute C_PROBE_IN164_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN165_WIDTH : integer;
attribute C_PROBE_IN165_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN166_WIDTH : integer;
attribute C_PROBE_IN166_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN167_WIDTH : integer;
attribute C_PROBE_IN167_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN168_WIDTH : integer;
attribute C_PROBE_IN168_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN169_WIDTH : integer;
attribute C_PROBE_IN169_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN16_WIDTH : integer;
attribute C_PROBE_IN16_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN170_WIDTH : integer;
attribute C_PROBE_IN170_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN171_WIDTH : integer;
attribute C_PROBE_IN171_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN172_WIDTH : integer;
attribute C_PROBE_IN172_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN173_WIDTH : integer;
attribute C_PROBE_IN173_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN174_WIDTH : integer;
attribute C_PROBE_IN174_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN175_WIDTH : integer;
attribute C_PROBE_IN175_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN176_WIDTH : integer;
attribute C_PROBE_IN176_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN177_WIDTH : integer;
attribute C_PROBE_IN177_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN178_WIDTH : integer;
attribute C_PROBE_IN178_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN179_WIDTH : integer;
attribute C_PROBE_IN179_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN17_WIDTH : integer;
attribute C_PROBE_IN17_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN180_WIDTH : integer;
attribute C_PROBE_IN180_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN181_WIDTH : integer;
attribute C_PROBE_IN181_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN182_WIDTH : integer;
attribute C_PROBE_IN182_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN183_WIDTH : integer;
attribute C_PROBE_IN183_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN184_WIDTH : integer;
attribute C_PROBE_IN184_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN185_WIDTH : integer;
attribute C_PROBE_IN185_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN186_WIDTH : integer;
attribute C_PROBE_IN186_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN187_WIDTH : integer;
attribute C_PROBE_IN187_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN188_WIDTH : integer;
attribute C_PROBE_IN188_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN189_WIDTH : integer;
attribute C_PROBE_IN189_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN18_WIDTH : integer;
attribute C_PROBE_IN18_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN190_WIDTH : integer;
attribute C_PROBE_IN190_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN191_WIDTH : integer;
attribute C_PROBE_IN191_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN192_WIDTH : integer;
attribute C_PROBE_IN192_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN193_WIDTH : integer;
attribute C_PROBE_IN193_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN194_WIDTH : integer;
attribute C_PROBE_IN194_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN195_WIDTH : integer;
attribute C_PROBE_IN195_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN196_WIDTH : integer;
attribute C_PROBE_IN196_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN197_WIDTH : integer;
attribute C_PROBE_IN197_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN198_WIDTH : integer;
attribute C_PROBE_IN198_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN199_WIDTH : integer;
attribute C_PROBE_IN199_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN19_WIDTH : integer;
attribute C_PROBE_IN19_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN1_WIDTH : integer;
attribute C_PROBE_IN1_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN200_WIDTH : integer;
attribute C_PROBE_IN200_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN201_WIDTH : integer;
attribute C_PROBE_IN201_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN202_WIDTH : integer;
attribute C_PROBE_IN202_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN203_WIDTH : integer;
attribute C_PROBE_IN203_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN204_WIDTH : integer;
attribute C_PROBE_IN204_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN205_WIDTH : integer;
attribute C_PROBE_IN205_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN206_WIDTH : integer;
attribute C_PROBE_IN206_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN207_WIDTH : integer;
attribute C_PROBE_IN207_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN208_WIDTH : integer;
attribute C_PROBE_IN208_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN209_WIDTH : integer;
attribute C_PROBE_IN209_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN20_WIDTH : integer;
attribute C_PROBE_IN20_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN210_WIDTH : integer;
attribute C_PROBE_IN210_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN211_WIDTH : integer;
attribute C_PROBE_IN211_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN212_WIDTH : integer;
attribute C_PROBE_IN212_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN213_WIDTH : integer;
attribute C_PROBE_IN213_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN214_WIDTH : integer;
attribute C_PROBE_IN214_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN215_WIDTH : integer;
attribute C_PROBE_IN215_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN216_WIDTH : integer;
attribute C_PROBE_IN216_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN217_WIDTH : integer;
attribute C_PROBE_IN217_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN218_WIDTH : integer;
attribute C_PROBE_IN218_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN219_WIDTH : integer;
attribute C_PROBE_IN219_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN21_WIDTH : integer;
attribute C_PROBE_IN21_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN220_WIDTH : integer;
attribute C_PROBE_IN220_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN221_WIDTH : integer;
attribute C_PROBE_IN221_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN222_WIDTH : integer;
attribute C_PROBE_IN222_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN223_WIDTH : integer;
attribute C_PROBE_IN223_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN224_WIDTH : integer;
attribute C_PROBE_IN224_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN225_WIDTH : integer;
attribute C_PROBE_IN225_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN226_WIDTH : integer;
attribute C_PROBE_IN226_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN227_WIDTH : integer;
attribute C_PROBE_IN227_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN228_WIDTH : integer;
attribute C_PROBE_IN228_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN229_WIDTH : integer;
attribute C_PROBE_IN229_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN22_WIDTH : integer;
attribute C_PROBE_IN22_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN230_WIDTH : integer;
attribute C_PROBE_IN230_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN231_WIDTH : integer;
attribute C_PROBE_IN231_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN232_WIDTH : integer;
attribute C_PROBE_IN232_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN233_WIDTH : integer;
attribute C_PROBE_IN233_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN234_WIDTH : integer;
attribute C_PROBE_IN234_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN235_WIDTH : integer;
attribute C_PROBE_IN235_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN236_WIDTH : integer;
attribute C_PROBE_IN236_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN237_WIDTH : integer;
attribute C_PROBE_IN237_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN238_WIDTH : integer;
attribute C_PROBE_IN238_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN239_WIDTH : integer;
attribute C_PROBE_IN239_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN23_WIDTH : integer;
attribute C_PROBE_IN23_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN240_WIDTH : integer;
attribute C_PROBE_IN240_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN241_WIDTH : integer;
attribute C_PROBE_IN241_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN242_WIDTH : integer;
attribute C_PROBE_IN242_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN243_WIDTH : integer;
attribute C_PROBE_IN243_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN244_WIDTH : integer;
attribute C_PROBE_IN244_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN245_WIDTH : integer;
attribute C_PROBE_IN245_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN246_WIDTH : integer;
attribute C_PROBE_IN246_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN247_WIDTH : integer;
attribute C_PROBE_IN247_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN248_WIDTH : integer;
attribute C_PROBE_IN248_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN249_WIDTH : integer;
attribute C_PROBE_IN249_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN24_WIDTH : integer;
attribute C_PROBE_IN24_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN250_WIDTH : integer;
attribute C_PROBE_IN250_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN251_WIDTH : integer;
attribute C_PROBE_IN251_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN252_WIDTH : integer;
attribute C_PROBE_IN252_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN253_WIDTH : integer;
attribute C_PROBE_IN253_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN254_WIDTH : integer;
attribute C_PROBE_IN254_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN255_WIDTH : integer;
attribute C_PROBE_IN255_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN25_WIDTH : integer;
attribute C_PROBE_IN25_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN26_WIDTH : integer;
attribute C_PROBE_IN26_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN27_WIDTH : integer;
attribute C_PROBE_IN27_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN28_WIDTH : integer;
attribute C_PROBE_IN28_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN29_WIDTH : integer;
attribute C_PROBE_IN29_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN2_WIDTH : integer;
attribute C_PROBE_IN2_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN30_WIDTH : integer;
attribute C_PROBE_IN30_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN31_WIDTH : integer;
attribute C_PROBE_IN31_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN32_WIDTH : integer;
attribute C_PROBE_IN32_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN33_WIDTH : integer;
attribute C_PROBE_IN33_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN34_WIDTH : integer;
attribute C_PROBE_IN34_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN35_WIDTH : integer;
attribute C_PROBE_IN35_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN36_WIDTH : integer;
attribute C_PROBE_IN36_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN37_WIDTH : integer;
attribute C_PROBE_IN37_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN38_WIDTH : integer;
attribute C_PROBE_IN38_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN39_WIDTH : integer;
attribute C_PROBE_IN39_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN3_WIDTH : integer;
attribute C_PROBE_IN3_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN40_WIDTH : integer;
attribute C_PROBE_IN40_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN41_WIDTH : integer;
attribute C_PROBE_IN41_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN42_WIDTH : integer;
attribute C_PROBE_IN42_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN43_WIDTH : integer;
attribute C_PROBE_IN43_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN44_WIDTH : integer;
attribute C_PROBE_IN44_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN45_WIDTH : integer;
attribute C_PROBE_IN45_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN46_WIDTH : integer;
attribute C_PROBE_IN46_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN47_WIDTH : integer;
attribute C_PROBE_IN47_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN48_WIDTH : integer;
attribute C_PROBE_IN48_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN49_WIDTH : integer;
attribute C_PROBE_IN49_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN4_WIDTH : integer;
attribute C_PROBE_IN4_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN50_WIDTH : integer;
attribute C_PROBE_IN50_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN51_WIDTH : integer;
attribute C_PROBE_IN51_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN52_WIDTH : integer;
attribute C_PROBE_IN52_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN53_WIDTH : integer;
attribute C_PROBE_IN53_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN54_WIDTH : integer;
attribute C_PROBE_IN54_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN55_WIDTH : integer;
attribute C_PROBE_IN55_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN56_WIDTH : integer;
attribute C_PROBE_IN56_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN57_WIDTH : integer;
attribute C_PROBE_IN57_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN58_WIDTH : integer;
attribute C_PROBE_IN58_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN59_WIDTH : integer;
attribute C_PROBE_IN59_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN5_WIDTH : integer;
attribute C_PROBE_IN5_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN60_WIDTH : integer;
attribute C_PROBE_IN60_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN61_WIDTH : integer;
attribute C_PROBE_IN61_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN62_WIDTH : integer;
attribute C_PROBE_IN62_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN63_WIDTH : integer;
attribute C_PROBE_IN63_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN64_WIDTH : integer;
attribute C_PROBE_IN64_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN65_WIDTH : integer;
attribute C_PROBE_IN65_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN66_WIDTH : integer;
attribute C_PROBE_IN66_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN67_WIDTH : integer;
attribute C_PROBE_IN67_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN68_WIDTH : integer;
attribute C_PROBE_IN68_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN69_WIDTH : integer;
attribute C_PROBE_IN69_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN6_WIDTH : integer;
attribute C_PROBE_IN6_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN70_WIDTH : integer;
attribute C_PROBE_IN70_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN71_WIDTH : integer;
attribute C_PROBE_IN71_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN72_WIDTH : integer;
attribute C_PROBE_IN72_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN73_WIDTH : integer;
attribute C_PROBE_IN73_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN74_WIDTH : integer;
attribute C_PROBE_IN74_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN75_WIDTH : integer;
attribute C_PROBE_IN75_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN76_WIDTH : integer;
attribute C_PROBE_IN76_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN77_WIDTH : integer;
attribute C_PROBE_IN77_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN78_WIDTH : integer;
attribute C_PROBE_IN78_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN79_WIDTH : integer;
attribute C_PROBE_IN79_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN7_WIDTH : integer;
attribute C_PROBE_IN7_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN80_WIDTH : integer;
attribute C_PROBE_IN80_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN81_WIDTH : integer;
attribute C_PROBE_IN81_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN82_WIDTH : integer;
attribute C_PROBE_IN82_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN83_WIDTH : integer;
attribute C_PROBE_IN83_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN84_WIDTH : integer;
attribute C_PROBE_IN84_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN85_WIDTH : integer;
attribute C_PROBE_IN85_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN86_WIDTH : integer;
attribute C_PROBE_IN86_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN87_WIDTH : integer;
attribute C_PROBE_IN87_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN88_WIDTH : integer;
attribute C_PROBE_IN88_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN89_WIDTH : integer;
attribute C_PROBE_IN89_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN8_WIDTH : integer;
attribute C_PROBE_IN8_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN90_WIDTH : integer;
attribute C_PROBE_IN90_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN91_WIDTH : integer;
attribute C_PROBE_IN91_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN92_WIDTH : integer;
attribute C_PROBE_IN92_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN93_WIDTH : integer;
attribute C_PROBE_IN93_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN94_WIDTH : integer;
attribute C_PROBE_IN94_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN95_WIDTH : integer;
attribute C_PROBE_IN95_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN96_WIDTH : integer;
attribute C_PROBE_IN96_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN97_WIDTH : integer;
attribute C_PROBE_IN97_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN98_WIDTH : integer;
attribute C_PROBE_IN98_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN99_WIDTH : integer;
attribute C_PROBE_IN99_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN9_WIDTH : integer;
attribute C_PROBE_IN9_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT0_INIT_VAL : string;
attribute C_PROBE_OUT0_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT0_WIDTH : integer;
attribute C_PROBE_OUT0_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT100_INIT_VAL : string;
attribute C_PROBE_OUT100_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT100_WIDTH : integer;
attribute C_PROBE_OUT100_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT101_INIT_VAL : string;
attribute C_PROBE_OUT101_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT101_WIDTH : integer;
attribute C_PROBE_OUT101_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT102_INIT_VAL : string;
attribute C_PROBE_OUT102_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT102_WIDTH : integer;
attribute C_PROBE_OUT102_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT103_INIT_VAL : string;
attribute C_PROBE_OUT103_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT103_WIDTH : integer;
attribute C_PROBE_OUT103_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT104_INIT_VAL : string;
attribute C_PROBE_OUT104_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT104_WIDTH : integer;
attribute C_PROBE_OUT104_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT105_INIT_VAL : string;
attribute C_PROBE_OUT105_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT105_WIDTH : integer;
attribute C_PROBE_OUT105_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT106_INIT_VAL : string;
attribute C_PROBE_OUT106_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT106_WIDTH : integer;
attribute C_PROBE_OUT106_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT107_INIT_VAL : string;
attribute C_PROBE_OUT107_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT107_WIDTH : integer;
attribute C_PROBE_OUT107_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT108_INIT_VAL : string;
attribute C_PROBE_OUT108_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT108_WIDTH : integer;
attribute C_PROBE_OUT108_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT109_INIT_VAL : string;
attribute C_PROBE_OUT109_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT109_WIDTH : integer;
attribute C_PROBE_OUT109_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT10_INIT_VAL : string;
attribute C_PROBE_OUT10_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT10_WIDTH : integer;
attribute C_PROBE_OUT10_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT110_INIT_VAL : string;
attribute C_PROBE_OUT110_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT110_WIDTH : integer;
attribute C_PROBE_OUT110_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT111_INIT_VAL : string;
attribute C_PROBE_OUT111_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT111_WIDTH : integer;
attribute C_PROBE_OUT111_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT112_INIT_VAL : string;
attribute C_PROBE_OUT112_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT112_WIDTH : integer;
attribute C_PROBE_OUT112_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT113_INIT_VAL : string;
attribute C_PROBE_OUT113_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT113_WIDTH : integer;
attribute C_PROBE_OUT113_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT114_INIT_VAL : string;
attribute C_PROBE_OUT114_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT114_WIDTH : integer;
attribute C_PROBE_OUT114_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT115_INIT_VAL : string;
attribute C_PROBE_OUT115_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT115_WIDTH : integer;
attribute C_PROBE_OUT115_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT116_INIT_VAL : string;
attribute C_PROBE_OUT116_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT116_WIDTH : integer;
attribute C_PROBE_OUT116_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT117_INIT_VAL : string;
attribute C_PROBE_OUT117_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT117_WIDTH : integer;
attribute C_PROBE_OUT117_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT118_INIT_VAL : string;
attribute C_PROBE_OUT118_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT118_WIDTH : integer;
attribute C_PROBE_OUT118_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT119_INIT_VAL : string;
attribute C_PROBE_OUT119_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT119_WIDTH : integer;
attribute C_PROBE_OUT119_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT11_INIT_VAL : string;
attribute C_PROBE_OUT11_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT11_WIDTH : integer;
attribute C_PROBE_OUT11_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT120_INIT_VAL : string;
attribute C_PROBE_OUT120_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT120_WIDTH : integer;
attribute C_PROBE_OUT120_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT121_INIT_VAL : string;
attribute C_PROBE_OUT121_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT121_WIDTH : integer;
attribute C_PROBE_OUT121_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT122_INIT_VAL : string;
attribute C_PROBE_OUT122_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT122_WIDTH : integer;
attribute C_PROBE_OUT122_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT123_INIT_VAL : string;
attribute C_PROBE_OUT123_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT123_WIDTH : integer;
attribute C_PROBE_OUT123_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT124_INIT_VAL : string;
attribute C_PROBE_OUT124_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT124_WIDTH : integer;
attribute C_PROBE_OUT124_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT125_INIT_VAL : string;
attribute C_PROBE_OUT125_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT125_WIDTH : integer;
attribute C_PROBE_OUT125_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT126_INIT_VAL : string;
attribute C_PROBE_OUT126_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT126_WIDTH : integer;
attribute C_PROBE_OUT126_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT127_INIT_VAL : string;
attribute C_PROBE_OUT127_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT127_WIDTH : integer;
attribute C_PROBE_OUT127_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT128_INIT_VAL : string;
attribute C_PROBE_OUT128_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT128_WIDTH : integer;
attribute C_PROBE_OUT128_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT129_INIT_VAL : string;
attribute C_PROBE_OUT129_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT129_WIDTH : integer;
attribute C_PROBE_OUT129_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT12_INIT_VAL : string;
attribute C_PROBE_OUT12_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT12_WIDTH : integer;
attribute C_PROBE_OUT12_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT130_INIT_VAL : string;
attribute C_PROBE_OUT130_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT130_WIDTH : integer;
attribute C_PROBE_OUT130_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT131_INIT_VAL : string;
attribute C_PROBE_OUT131_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT131_WIDTH : integer;
attribute C_PROBE_OUT131_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT132_INIT_VAL : string;
attribute C_PROBE_OUT132_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT132_WIDTH : integer;
attribute C_PROBE_OUT132_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT133_INIT_VAL : string;
attribute C_PROBE_OUT133_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT133_WIDTH : integer;
attribute C_PROBE_OUT133_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT134_INIT_VAL : string;
attribute C_PROBE_OUT134_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT134_WIDTH : integer;
attribute C_PROBE_OUT134_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT135_INIT_VAL : string;
attribute C_PROBE_OUT135_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT135_WIDTH : integer;
attribute C_PROBE_OUT135_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT136_INIT_VAL : string;
attribute C_PROBE_OUT136_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT136_WIDTH : integer;
attribute C_PROBE_OUT136_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT137_INIT_VAL : string;
attribute C_PROBE_OUT137_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT137_WIDTH : integer;
attribute C_PROBE_OUT137_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT138_INIT_VAL : string;
attribute C_PROBE_OUT138_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT138_WIDTH : integer;
attribute C_PROBE_OUT138_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT139_INIT_VAL : string;
attribute C_PROBE_OUT139_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT139_WIDTH : integer;
attribute C_PROBE_OUT139_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT13_INIT_VAL : string;
attribute C_PROBE_OUT13_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT13_WIDTH : integer;
attribute C_PROBE_OUT13_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT140_INIT_VAL : string;
attribute C_PROBE_OUT140_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT140_WIDTH : integer;
attribute C_PROBE_OUT140_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT141_INIT_VAL : string;
attribute C_PROBE_OUT141_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT141_WIDTH : integer;
attribute C_PROBE_OUT141_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT142_INIT_VAL : string;
attribute C_PROBE_OUT142_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT142_WIDTH : integer;
attribute C_PROBE_OUT142_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT143_INIT_VAL : string;
attribute C_PROBE_OUT143_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT143_WIDTH : integer;
attribute C_PROBE_OUT143_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT144_INIT_VAL : string;
attribute C_PROBE_OUT144_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT144_WIDTH : integer;
attribute C_PROBE_OUT144_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT145_INIT_VAL : string;
attribute C_PROBE_OUT145_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT145_WIDTH : integer;
attribute C_PROBE_OUT145_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT146_INIT_VAL : string;
attribute C_PROBE_OUT146_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT146_WIDTH : integer;
attribute C_PROBE_OUT146_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT147_INIT_VAL : string;
attribute C_PROBE_OUT147_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT147_WIDTH : integer;
attribute C_PROBE_OUT147_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT148_INIT_VAL : string;
attribute C_PROBE_OUT148_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT148_WIDTH : integer;
attribute C_PROBE_OUT148_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT149_INIT_VAL : string;
attribute C_PROBE_OUT149_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT149_WIDTH : integer;
attribute C_PROBE_OUT149_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT14_INIT_VAL : string;
attribute C_PROBE_OUT14_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT14_WIDTH : integer;
attribute C_PROBE_OUT14_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT150_INIT_VAL : string;
attribute C_PROBE_OUT150_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT150_WIDTH : integer;
attribute C_PROBE_OUT150_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT151_INIT_VAL : string;
attribute C_PROBE_OUT151_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT151_WIDTH : integer;
attribute C_PROBE_OUT151_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT152_INIT_VAL : string;
attribute C_PROBE_OUT152_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT152_WIDTH : integer;
attribute C_PROBE_OUT152_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT153_INIT_VAL : string;
attribute C_PROBE_OUT153_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT153_WIDTH : integer;
attribute C_PROBE_OUT153_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT154_INIT_VAL : string;
attribute C_PROBE_OUT154_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT154_WIDTH : integer;
attribute C_PROBE_OUT154_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT155_INIT_VAL : string;
attribute C_PROBE_OUT155_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT155_WIDTH : integer;
attribute C_PROBE_OUT155_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT156_INIT_VAL : string;
attribute C_PROBE_OUT156_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT156_WIDTH : integer;
attribute C_PROBE_OUT156_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT157_INIT_VAL : string;
attribute C_PROBE_OUT157_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT157_WIDTH : integer;
attribute C_PROBE_OUT157_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT158_INIT_VAL : string;
attribute C_PROBE_OUT158_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT158_WIDTH : integer;
attribute C_PROBE_OUT158_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT159_INIT_VAL : string;
attribute C_PROBE_OUT159_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT159_WIDTH : integer;
attribute C_PROBE_OUT159_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT15_INIT_VAL : string;
attribute C_PROBE_OUT15_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT15_WIDTH : integer;
attribute C_PROBE_OUT15_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT160_INIT_VAL : string;
attribute C_PROBE_OUT160_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT160_WIDTH : integer;
attribute C_PROBE_OUT160_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT161_INIT_VAL : string;
attribute C_PROBE_OUT161_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT161_WIDTH : integer;
attribute C_PROBE_OUT161_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT162_INIT_VAL : string;
attribute C_PROBE_OUT162_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT162_WIDTH : integer;
attribute C_PROBE_OUT162_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT163_INIT_VAL : string;
attribute C_PROBE_OUT163_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT163_WIDTH : integer;
attribute C_PROBE_OUT163_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT164_INIT_VAL : string;
attribute C_PROBE_OUT164_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT164_WIDTH : integer;
attribute C_PROBE_OUT164_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT165_INIT_VAL : string;
attribute C_PROBE_OUT165_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT165_WIDTH : integer;
attribute C_PROBE_OUT165_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT166_INIT_VAL : string;
attribute C_PROBE_OUT166_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT166_WIDTH : integer;
attribute C_PROBE_OUT166_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT167_INIT_VAL : string;
attribute C_PROBE_OUT167_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT167_WIDTH : integer;
attribute C_PROBE_OUT167_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT168_INIT_VAL : string;
attribute C_PROBE_OUT168_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT168_WIDTH : integer;
attribute C_PROBE_OUT168_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT169_INIT_VAL : string;
attribute C_PROBE_OUT169_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT169_WIDTH : integer;
attribute C_PROBE_OUT169_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT16_INIT_VAL : string;
attribute C_PROBE_OUT16_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT16_WIDTH : integer;
attribute C_PROBE_OUT16_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT170_INIT_VAL : string;
attribute C_PROBE_OUT170_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT170_WIDTH : integer;
attribute C_PROBE_OUT170_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT171_INIT_VAL : string;
attribute C_PROBE_OUT171_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT171_WIDTH : integer;
attribute C_PROBE_OUT171_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT172_INIT_VAL : string;
attribute C_PROBE_OUT172_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT172_WIDTH : integer;
attribute C_PROBE_OUT172_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT173_INIT_VAL : string;
attribute C_PROBE_OUT173_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT173_WIDTH : integer;
attribute C_PROBE_OUT173_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT174_INIT_VAL : string;
attribute C_PROBE_OUT174_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT174_WIDTH : integer;
attribute C_PROBE_OUT174_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT175_INIT_VAL : string;
attribute C_PROBE_OUT175_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT175_WIDTH : integer;
attribute C_PROBE_OUT175_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT176_INIT_VAL : string;
attribute C_PROBE_OUT176_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT176_WIDTH : integer;
attribute C_PROBE_OUT176_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT177_INIT_VAL : string;
attribute C_PROBE_OUT177_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT177_WIDTH : integer;
attribute C_PROBE_OUT177_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT178_INIT_VAL : string;
attribute C_PROBE_OUT178_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT178_WIDTH : integer;
attribute C_PROBE_OUT178_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT179_INIT_VAL : string;
attribute C_PROBE_OUT179_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT179_WIDTH : integer;
attribute C_PROBE_OUT179_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT17_INIT_VAL : string;
attribute C_PROBE_OUT17_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT17_WIDTH : integer;
attribute C_PROBE_OUT17_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT180_INIT_VAL : string;
attribute C_PROBE_OUT180_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT180_WIDTH : integer;
attribute C_PROBE_OUT180_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT181_INIT_VAL : string;
attribute C_PROBE_OUT181_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT181_WIDTH : integer;
attribute C_PROBE_OUT181_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT182_INIT_VAL : string;
attribute C_PROBE_OUT182_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT182_WIDTH : integer;
attribute C_PROBE_OUT182_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT183_INIT_VAL : string;
attribute C_PROBE_OUT183_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT183_WIDTH : integer;
attribute C_PROBE_OUT183_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT184_INIT_VAL : string;
attribute C_PROBE_OUT184_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT184_WIDTH : integer;
attribute C_PROBE_OUT184_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT185_INIT_VAL : string;
attribute C_PROBE_OUT185_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT185_WIDTH : integer;
attribute C_PROBE_OUT185_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT186_INIT_VAL : string;
attribute C_PROBE_OUT186_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT186_WIDTH : integer;
attribute C_PROBE_OUT186_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT187_INIT_VAL : string;
attribute C_PROBE_OUT187_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT187_WIDTH : integer;
attribute C_PROBE_OUT187_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT188_INIT_VAL : string;
attribute C_PROBE_OUT188_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT188_WIDTH : integer;
attribute C_PROBE_OUT188_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT189_INIT_VAL : string;
attribute C_PROBE_OUT189_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT189_WIDTH : integer;
attribute C_PROBE_OUT189_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT18_INIT_VAL : string;
attribute C_PROBE_OUT18_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT18_WIDTH : integer;
attribute C_PROBE_OUT18_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT190_INIT_VAL : string;
attribute C_PROBE_OUT190_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT190_WIDTH : integer;
attribute C_PROBE_OUT190_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT191_INIT_VAL : string;
attribute C_PROBE_OUT191_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT191_WIDTH : integer;
attribute C_PROBE_OUT191_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT192_INIT_VAL : string;
attribute C_PROBE_OUT192_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT192_WIDTH : integer;
attribute C_PROBE_OUT192_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT193_INIT_VAL : string;
attribute C_PROBE_OUT193_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT193_WIDTH : integer;
attribute C_PROBE_OUT193_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT194_INIT_VAL : string;
attribute C_PROBE_OUT194_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT194_WIDTH : integer;
attribute C_PROBE_OUT194_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT195_INIT_VAL : string;
attribute C_PROBE_OUT195_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT195_WIDTH : integer;
attribute C_PROBE_OUT195_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT196_INIT_VAL : string;
attribute C_PROBE_OUT196_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT196_WIDTH : integer;
attribute C_PROBE_OUT196_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT197_INIT_VAL : string;
attribute C_PROBE_OUT197_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT197_WIDTH : integer;
attribute C_PROBE_OUT197_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT198_INIT_VAL : string;
attribute C_PROBE_OUT198_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT198_WIDTH : integer;
attribute C_PROBE_OUT198_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT199_INIT_VAL : string;
attribute C_PROBE_OUT199_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT199_WIDTH : integer;
attribute C_PROBE_OUT199_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT19_INIT_VAL : string;
attribute C_PROBE_OUT19_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT19_WIDTH : integer;
attribute C_PROBE_OUT19_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT1_INIT_VAL : string;
attribute C_PROBE_OUT1_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT1_WIDTH : integer;
attribute C_PROBE_OUT1_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT200_INIT_VAL : string;
attribute C_PROBE_OUT200_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT200_WIDTH : integer;
attribute C_PROBE_OUT200_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT201_INIT_VAL : string;
attribute C_PROBE_OUT201_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT201_WIDTH : integer;
attribute C_PROBE_OUT201_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT202_INIT_VAL : string;
attribute C_PROBE_OUT202_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT202_WIDTH : integer;
attribute C_PROBE_OUT202_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT203_INIT_VAL : string;
attribute C_PROBE_OUT203_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT203_WIDTH : integer;
attribute C_PROBE_OUT203_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT204_INIT_VAL : string;
attribute C_PROBE_OUT204_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT204_WIDTH : integer;
attribute C_PROBE_OUT204_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT205_INIT_VAL : string;
attribute C_PROBE_OUT205_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT205_WIDTH : integer;
attribute C_PROBE_OUT205_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT206_INIT_VAL : string;
attribute C_PROBE_OUT206_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT206_WIDTH : integer;
attribute C_PROBE_OUT206_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT207_INIT_VAL : string;
attribute C_PROBE_OUT207_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT207_WIDTH : integer;
attribute C_PROBE_OUT207_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT208_INIT_VAL : string;
attribute C_PROBE_OUT208_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT208_WIDTH : integer;
attribute C_PROBE_OUT208_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT209_INIT_VAL : string;
attribute C_PROBE_OUT209_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT209_WIDTH : integer;
attribute C_PROBE_OUT209_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT20_INIT_VAL : string;
attribute C_PROBE_OUT20_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT20_WIDTH : integer;
attribute C_PROBE_OUT20_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT210_INIT_VAL : string;
attribute C_PROBE_OUT210_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT210_WIDTH : integer;
attribute C_PROBE_OUT210_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT211_INIT_VAL : string;
attribute C_PROBE_OUT211_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT211_WIDTH : integer;
attribute C_PROBE_OUT211_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT212_INIT_VAL : string;
attribute C_PROBE_OUT212_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT212_WIDTH : integer;
attribute C_PROBE_OUT212_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT213_INIT_VAL : string;
attribute C_PROBE_OUT213_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT213_WIDTH : integer;
attribute C_PROBE_OUT213_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT214_INIT_VAL : string;
attribute C_PROBE_OUT214_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT214_WIDTH : integer;
attribute C_PROBE_OUT214_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT215_INIT_VAL : string;
attribute C_PROBE_OUT215_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT215_WIDTH : integer;
attribute C_PROBE_OUT215_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT216_INIT_VAL : string;
attribute C_PROBE_OUT216_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT216_WIDTH : integer;
attribute C_PROBE_OUT216_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT217_INIT_VAL : string;
attribute C_PROBE_OUT217_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT217_WIDTH : integer;
attribute C_PROBE_OUT217_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT218_INIT_VAL : string;
attribute C_PROBE_OUT218_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT218_WIDTH : integer;
attribute C_PROBE_OUT218_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT219_INIT_VAL : string;
attribute C_PROBE_OUT219_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT219_WIDTH : integer;
attribute C_PROBE_OUT219_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT21_INIT_VAL : string;
attribute C_PROBE_OUT21_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT21_WIDTH : integer;
attribute C_PROBE_OUT21_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT220_INIT_VAL : string;
attribute C_PROBE_OUT220_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT220_WIDTH : integer;
attribute C_PROBE_OUT220_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT221_INIT_VAL : string;
attribute C_PROBE_OUT221_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT221_WIDTH : integer;
attribute C_PROBE_OUT221_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT222_INIT_VAL : string;
attribute C_PROBE_OUT222_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT222_WIDTH : integer;
attribute C_PROBE_OUT222_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT223_INIT_VAL : string;
attribute C_PROBE_OUT223_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT223_WIDTH : integer;
attribute C_PROBE_OUT223_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT224_INIT_VAL : string;
attribute C_PROBE_OUT224_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT224_WIDTH : integer;
attribute C_PROBE_OUT224_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT225_INIT_VAL : string;
attribute C_PROBE_OUT225_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT225_WIDTH : integer;
attribute C_PROBE_OUT225_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT226_INIT_VAL : string;
attribute C_PROBE_OUT226_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT226_WIDTH : integer;
attribute C_PROBE_OUT226_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT227_INIT_VAL : string;
attribute C_PROBE_OUT227_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT227_WIDTH : integer;
attribute C_PROBE_OUT227_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT228_INIT_VAL : string;
attribute C_PROBE_OUT228_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT228_WIDTH : integer;
attribute C_PROBE_OUT228_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT229_INIT_VAL : string;
attribute C_PROBE_OUT229_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT229_WIDTH : integer;
attribute C_PROBE_OUT229_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT22_INIT_VAL : string;
attribute C_PROBE_OUT22_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT22_WIDTH : integer;
attribute C_PROBE_OUT22_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT230_INIT_VAL : string;
attribute C_PROBE_OUT230_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT230_WIDTH : integer;
attribute C_PROBE_OUT230_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT231_INIT_VAL : string;
attribute C_PROBE_OUT231_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT231_WIDTH : integer;
attribute C_PROBE_OUT231_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT232_INIT_VAL : string;
attribute C_PROBE_OUT232_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT232_WIDTH : integer;
attribute C_PROBE_OUT232_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT233_INIT_VAL : string;
attribute C_PROBE_OUT233_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT233_WIDTH : integer;
attribute C_PROBE_OUT233_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT234_INIT_VAL : string;
attribute C_PROBE_OUT234_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT234_WIDTH : integer;
attribute C_PROBE_OUT234_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT235_INIT_VAL : string;
attribute C_PROBE_OUT235_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT235_WIDTH : integer;
attribute C_PROBE_OUT235_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT236_INIT_VAL : string;
attribute C_PROBE_OUT236_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT236_WIDTH : integer;
attribute C_PROBE_OUT236_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT237_INIT_VAL : string;
attribute C_PROBE_OUT237_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT237_WIDTH : integer;
attribute C_PROBE_OUT237_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT238_INIT_VAL : string;
attribute C_PROBE_OUT238_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT238_WIDTH : integer;
attribute C_PROBE_OUT238_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT239_INIT_VAL : string;
attribute C_PROBE_OUT239_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT239_WIDTH : integer;
attribute C_PROBE_OUT239_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT23_INIT_VAL : string;
attribute C_PROBE_OUT23_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT23_WIDTH : integer;
attribute C_PROBE_OUT23_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT240_INIT_VAL : string;
attribute C_PROBE_OUT240_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT240_WIDTH : integer;
attribute C_PROBE_OUT240_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT241_INIT_VAL : string;
attribute C_PROBE_OUT241_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT241_WIDTH : integer;
attribute C_PROBE_OUT241_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT242_INIT_VAL : string;
attribute C_PROBE_OUT242_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT242_WIDTH : integer;
attribute C_PROBE_OUT242_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT243_INIT_VAL : string;
attribute C_PROBE_OUT243_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT243_WIDTH : integer;
attribute C_PROBE_OUT243_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT244_INIT_VAL : string;
attribute C_PROBE_OUT244_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT244_WIDTH : integer;
attribute C_PROBE_OUT244_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT245_INIT_VAL : string;
attribute C_PROBE_OUT245_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT245_WIDTH : integer;
attribute C_PROBE_OUT245_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT246_INIT_VAL : string;
attribute C_PROBE_OUT246_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT246_WIDTH : integer;
attribute C_PROBE_OUT246_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT247_INIT_VAL : string;
attribute C_PROBE_OUT247_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT247_WIDTH : integer;
attribute C_PROBE_OUT247_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT248_INIT_VAL : string;
attribute C_PROBE_OUT248_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT248_WIDTH : integer;
attribute C_PROBE_OUT248_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT249_INIT_VAL : string;
attribute C_PROBE_OUT249_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT249_WIDTH : integer;
attribute C_PROBE_OUT249_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT24_INIT_VAL : string;
attribute C_PROBE_OUT24_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT24_WIDTH : integer;
attribute C_PROBE_OUT24_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT250_INIT_VAL : string;
attribute C_PROBE_OUT250_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT250_WIDTH : integer;
attribute C_PROBE_OUT250_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT251_INIT_VAL : string;
attribute C_PROBE_OUT251_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT251_WIDTH : integer;
attribute C_PROBE_OUT251_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT252_INIT_VAL : string;
attribute C_PROBE_OUT252_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT252_WIDTH : integer;
attribute C_PROBE_OUT252_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT253_INIT_VAL : string;
attribute C_PROBE_OUT253_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT253_WIDTH : integer;
attribute C_PROBE_OUT253_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT254_INIT_VAL : string;
attribute C_PROBE_OUT254_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT254_WIDTH : integer;
attribute C_PROBE_OUT254_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT255_INIT_VAL : string;
attribute C_PROBE_OUT255_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT255_WIDTH : integer;
attribute C_PROBE_OUT255_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT25_INIT_VAL : string;
attribute C_PROBE_OUT25_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT25_WIDTH : integer;
attribute C_PROBE_OUT25_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT26_INIT_VAL : string;
attribute C_PROBE_OUT26_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT26_WIDTH : integer;
attribute C_PROBE_OUT26_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT27_INIT_VAL : string;
attribute C_PROBE_OUT27_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT27_WIDTH : integer;
attribute C_PROBE_OUT27_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT28_INIT_VAL : string;
attribute C_PROBE_OUT28_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT28_WIDTH : integer;
attribute C_PROBE_OUT28_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT29_INIT_VAL : string;
attribute C_PROBE_OUT29_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT29_WIDTH : integer;
attribute C_PROBE_OUT29_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT2_INIT_VAL : string;
attribute C_PROBE_OUT2_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT2_WIDTH : integer;
attribute C_PROBE_OUT2_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT30_INIT_VAL : string;
attribute C_PROBE_OUT30_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT30_WIDTH : integer;
attribute C_PROBE_OUT30_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT31_INIT_VAL : string;
attribute C_PROBE_OUT31_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT31_WIDTH : integer;
attribute C_PROBE_OUT31_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT32_INIT_VAL : string;
attribute C_PROBE_OUT32_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT32_WIDTH : integer;
attribute C_PROBE_OUT32_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT33_INIT_VAL : string;
attribute C_PROBE_OUT33_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT33_WIDTH : integer;
attribute C_PROBE_OUT33_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT34_INIT_VAL : string;
attribute C_PROBE_OUT34_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT34_WIDTH : integer;
attribute C_PROBE_OUT34_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT35_INIT_VAL : string;
attribute C_PROBE_OUT35_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT35_WIDTH : integer;
attribute C_PROBE_OUT35_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT36_INIT_VAL : string;
attribute C_PROBE_OUT36_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT36_WIDTH : integer;
attribute C_PROBE_OUT36_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT37_INIT_VAL : string;
attribute C_PROBE_OUT37_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT37_WIDTH : integer;
attribute C_PROBE_OUT37_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT38_INIT_VAL : string;
attribute C_PROBE_OUT38_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT38_WIDTH : integer;
attribute C_PROBE_OUT38_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT39_INIT_VAL : string;
attribute C_PROBE_OUT39_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT39_WIDTH : integer;
attribute C_PROBE_OUT39_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT3_INIT_VAL : string;
attribute C_PROBE_OUT3_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT3_WIDTH : integer;
attribute C_PROBE_OUT3_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT40_INIT_VAL : string;
attribute C_PROBE_OUT40_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT40_WIDTH : integer;
attribute C_PROBE_OUT40_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT41_INIT_VAL : string;
attribute C_PROBE_OUT41_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT41_WIDTH : integer;
attribute C_PROBE_OUT41_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT42_INIT_VAL : string;
attribute C_PROBE_OUT42_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT42_WIDTH : integer;
attribute C_PROBE_OUT42_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT43_INIT_VAL : string;
attribute C_PROBE_OUT43_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT43_WIDTH : integer;
attribute C_PROBE_OUT43_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT44_INIT_VAL : string;
attribute C_PROBE_OUT44_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT44_WIDTH : integer;
attribute C_PROBE_OUT44_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT45_INIT_VAL : string;
attribute C_PROBE_OUT45_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT45_WIDTH : integer;
attribute C_PROBE_OUT45_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT46_INIT_VAL : string;
attribute C_PROBE_OUT46_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT46_WIDTH : integer;
attribute C_PROBE_OUT46_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT47_INIT_VAL : string;
attribute C_PROBE_OUT47_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT47_WIDTH : integer;
attribute C_PROBE_OUT47_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT48_INIT_VAL : string;
attribute C_PROBE_OUT48_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT48_WIDTH : integer;
attribute C_PROBE_OUT48_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT49_INIT_VAL : string;
attribute C_PROBE_OUT49_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT49_WIDTH : integer;
attribute C_PROBE_OUT49_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT4_INIT_VAL : string;
attribute C_PROBE_OUT4_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT4_WIDTH : integer;
attribute C_PROBE_OUT4_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT50_INIT_VAL : string;
attribute C_PROBE_OUT50_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT50_WIDTH : integer;
attribute C_PROBE_OUT50_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT51_INIT_VAL : string;
attribute C_PROBE_OUT51_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT51_WIDTH : integer;
attribute C_PROBE_OUT51_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT52_INIT_VAL : string;
attribute C_PROBE_OUT52_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT52_WIDTH : integer;
attribute C_PROBE_OUT52_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT53_INIT_VAL : string;
attribute C_PROBE_OUT53_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT53_WIDTH : integer;
attribute C_PROBE_OUT53_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT54_INIT_VAL : string;
attribute C_PROBE_OUT54_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT54_WIDTH : integer;
attribute C_PROBE_OUT54_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT55_INIT_VAL : string;
attribute C_PROBE_OUT55_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT55_WIDTH : integer;
attribute C_PROBE_OUT55_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT56_INIT_VAL : string;
attribute C_PROBE_OUT56_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT56_WIDTH : integer;
attribute C_PROBE_OUT56_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT57_INIT_VAL : string;
attribute C_PROBE_OUT57_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT57_WIDTH : integer;
attribute C_PROBE_OUT57_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT58_INIT_VAL : string;
attribute C_PROBE_OUT58_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT58_WIDTH : integer;
attribute C_PROBE_OUT58_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT59_INIT_VAL : string;
attribute C_PROBE_OUT59_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT59_WIDTH : integer;
attribute C_PROBE_OUT59_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT5_INIT_VAL : string;
attribute C_PROBE_OUT5_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT5_WIDTH : integer;
attribute C_PROBE_OUT5_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT60_INIT_VAL : string;
attribute C_PROBE_OUT60_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT60_WIDTH : integer;
attribute C_PROBE_OUT60_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT61_INIT_VAL : string;
attribute C_PROBE_OUT61_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT61_WIDTH : integer;
attribute C_PROBE_OUT61_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT62_INIT_VAL : string;
attribute C_PROBE_OUT62_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT62_WIDTH : integer;
attribute C_PROBE_OUT62_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT63_INIT_VAL : string;
attribute C_PROBE_OUT63_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT63_WIDTH : integer;
attribute C_PROBE_OUT63_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT64_INIT_VAL : string;
attribute C_PROBE_OUT64_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT64_WIDTH : integer;
attribute C_PROBE_OUT64_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT65_INIT_VAL : string;
attribute C_PROBE_OUT65_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT65_WIDTH : integer;
attribute C_PROBE_OUT65_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT66_INIT_VAL : string;
attribute C_PROBE_OUT66_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT66_WIDTH : integer;
attribute C_PROBE_OUT66_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT67_INIT_VAL : string;
attribute C_PROBE_OUT67_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT67_WIDTH : integer;
attribute C_PROBE_OUT67_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT68_INIT_VAL : string;
attribute C_PROBE_OUT68_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT68_WIDTH : integer;
attribute C_PROBE_OUT68_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT69_INIT_VAL : string;
attribute C_PROBE_OUT69_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT69_WIDTH : integer;
attribute C_PROBE_OUT69_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT6_INIT_VAL : string;
attribute C_PROBE_OUT6_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT6_WIDTH : integer;
attribute C_PROBE_OUT6_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT70_INIT_VAL : string;
attribute C_PROBE_OUT70_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT70_WIDTH : integer;
attribute C_PROBE_OUT70_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT71_INIT_VAL : string;
attribute C_PROBE_OUT71_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT71_WIDTH : integer;
attribute C_PROBE_OUT71_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT72_INIT_VAL : string;
attribute C_PROBE_OUT72_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT72_WIDTH : integer;
attribute C_PROBE_OUT72_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT73_INIT_VAL : string;
attribute C_PROBE_OUT73_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT73_WIDTH : integer;
attribute C_PROBE_OUT73_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT74_INIT_VAL : string;
attribute C_PROBE_OUT74_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT74_WIDTH : integer;
attribute C_PROBE_OUT74_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT75_INIT_VAL : string;
attribute C_PROBE_OUT75_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT75_WIDTH : integer;
attribute C_PROBE_OUT75_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT76_INIT_VAL : string;
attribute C_PROBE_OUT76_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT76_WIDTH : integer;
attribute C_PROBE_OUT76_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT77_INIT_VAL : string;
attribute C_PROBE_OUT77_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT77_WIDTH : integer;
attribute C_PROBE_OUT77_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT78_INIT_VAL : string;
attribute C_PROBE_OUT78_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT78_WIDTH : integer;
attribute C_PROBE_OUT78_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT79_INIT_VAL : string;
attribute C_PROBE_OUT79_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT79_WIDTH : integer;
attribute C_PROBE_OUT79_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT7_INIT_VAL : string;
attribute C_PROBE_OUT7_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT7_WIDTH : integer;
attribute C_PROBE_OUT7_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT80_INIT_VAL : string;
attribute C_PROBE_OUT80_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT80_WIDTH : integer;
attribute C_PROBE_OUT80_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT81_INIT_VAL : string;
attribute C_PROBE_OUT81_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT81_WIDTH : integer;
attribute C_PROBE_OUT81_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT82_INIT_VAL : string;
attribute C_PROBE_OUT82_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT82_WIDTH : integer;
attribute C_PROBE_OUT82_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT83_INIT_VAL : string;
attribute C_PROBE_OUT83_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT83_WIDTH : integer;
attribute C_PROBE_OUT83_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT84_INIT_VAL : string;
attribute C_PROBE_OUT84_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT84_WIDTH : integer;
attribute C_PROBE_OUT84_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT85_INIT_VAL : string;
attribute C_PROBE_OUT85_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT85_WIDTH : integer;
attribute C_PROBE_OUT85_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT86_INIT_VAL : string;
attribute C_PROBE_OUT86_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT86_WIDTH : integer;
attribute C_PROBE_OUT86_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT87_INIT_VAL : string;
attribute C_PROBE_OUT87_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT87_WIDTH : integer;
attribute C_PROBE_OUT87_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT88_INIT_VAL : string;
attribute C_PROBE_OUT88_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT88_WIDTH : integer;
attribute C_PROBE_OUT88_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT89_INIT_VAL : string;
attribute C_PROBE_OUT89_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT89_WIDTH : integer;
attribute C_PROBE_OUT89_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT8_INIT_VAL : string;
attribute C_PROBE_OUT8_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT8_WIDTH : integer;
attribute C_PROBE_OUT8_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT90_INIT_VAL : string;
attribute C_PROBE_OUT90_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT90_WIDTH : integer;
attribute C_PROBE_OUT90_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT91_INIT_VAL : string;
attribute C_PROBE_OUT91_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT91_WIDTH : integer;
attribute C_PROBE_OUT91_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT92_INIT_VAL : string;
attribute C_PROBE_OUT92_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT92_WIDTH : integer;
attribute C_PROBE_OUT92_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT93_INIT_VAL : string;
attribute C_PROBE_OUT93_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT93_WIDTH : integer;
attribute C_PROBE_OUT93_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT94_INIT_VAL : string;
attribute C_PROBE_OUT94_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT94_WIDTH : integer;
attribute C_PROBE_OUT94_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT95_INIT_VAL : string;
attribute C_PROBE_OUT95_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT95_WIDTH : integer;
attribute C_PROBE_OUT95_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT96_INIT_VAL : string;
attribute C_PROBE_OUT96_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT96_WIDTH : integer;
attribute C_PROBE_OUT96_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT97_INIT_VAL : string;
attribute C_PROBE_OUT97_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT97_WIDTH : integer;
attribute C_PROBE_OUT97_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT98_INIT_VAL : string;
attribute C_PROBE_OUT98_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT98_WIDTH : integer;
attribute C_PROBE_OUT98_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT99_INIT_VAL : string;
attribute C_PROBE_OUT99_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT99_WIDTH : integer;
attribute C_PROBE_OUT99_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT9_INIT_VAL : string;
attribute C_PROBE_OUT9_INIT_VAL of vio_0_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT9_WIDTH : integer;
attribute C_PROBE_OUT9_WIDTH of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_USE_TEST_REG : integer;
attribute C_USE_TEST_REG of vio_0_vio_v3_0_13_vio : entity is 1;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of vio_0_vio_v3_0_13_vio : entity is "kintex7";
attribute C_XLNX_HW_PROBE_INFO : string;
attribute C_XLNX_HW_PROBE_INFO of vio_0_vio_v3_0_13_vio : entity is "DEFAULT";
attribute C_XSDB_SLAVE_TYPE : integer;
attribute C_XSDB_SLAVE_TYPE of vio_0_vio_v3_0_13_vio : entity is 33;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of vio_0_vio_v3_0_13_vio : entity is "yes";
attribute LC_HIGH_BIT_POS_PROBE_OUT0 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT0 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT1 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT1 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT10 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT10 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT100 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT100 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT101 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT101 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT102 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT102 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT103 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT103 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT104 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT104 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT105 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT105 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT106 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT106 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT107 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT107 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT108 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT108 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT109 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT109 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT11 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT11 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT110 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT110 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT111 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT111 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT112 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT112 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT113 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT113 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT114 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT114 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT115 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT115 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT116 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT116 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT117 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT117 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT118 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT118 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT119 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT119 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT12 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT12 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT120 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT120 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT121 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT121 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT122 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT122 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT123 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT123 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT124 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT124 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT125 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT125 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT126 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT126 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT127 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT127 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT128 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT128 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT129 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT129 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT13 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT13 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT130 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT130 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT131 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT131 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT132 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT132 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT133 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT133 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT134 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT134 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT135 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT135 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT136 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT136 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT137 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT137 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT138 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT138 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT139 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT139 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT14 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT14 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT140 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT140 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT141 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT141 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT142 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT142 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT143 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT143 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT144 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT144 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT145 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT145 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT146 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT146 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT147 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT147 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT148 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT148 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT149 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT149 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT15 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT15 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT150 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT150 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT151 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT151 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT152 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT152 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT153 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT153 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT154 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT154 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT155 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT155 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT156 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT156 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT157 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT157 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT158 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT158 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT159 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT159 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT16 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT16 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT160 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT160 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT161 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT161 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT162 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT162 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT163 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT163 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT164 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT164 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT165 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT165 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT166 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT166 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT167 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT167 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT168 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT168 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT169 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT169 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT17 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT17 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT170 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT170 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT171 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT171 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT172 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT172 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT173 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT173 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT174 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT174 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT175 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT175 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT176 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT176 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT177 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT177 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT178 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT178 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT179 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT179 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT18 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT18 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT180 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT180 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT181 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT181 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT182 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT182 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT183 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT183 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT184 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT184 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT185 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT185 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT186 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT186 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT187 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT187 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT188 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT188 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT189 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT189 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT19 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT19 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT190 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT190 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT191 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT191 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT192 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT192 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT193 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT193 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT194 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT194 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT195 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT195 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT196 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT196 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT197 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT197 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT198 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT198 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT199 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT199 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT2 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT2 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT20 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT20 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT200 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT200 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT201 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT201 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT202 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT202 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT203 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT203 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT204 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT204 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT205 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT205 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT206 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT206 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT207 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT207 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT208 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT208 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT209 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT209 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT21 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT21 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT210 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT210 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT211 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT211 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT212 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT212 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT213 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT213 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT214 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT214 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT215 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT215 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT216 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT216 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT217 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT217 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT218 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT218 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT219 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT219 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT22 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT22 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT220 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT220 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT221 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT221 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT222 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT222 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT223 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT223 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT224 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT224 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT225 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT225 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT226 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT226 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT227 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT227 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT228 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT228 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT229 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT229 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT23 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT23 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT230 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT230 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT231 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT231 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT232 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT232 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT233 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT233 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT234 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT234 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT235 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT235 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT236 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT236 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT237 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT237 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT238 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT238 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT239 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT239 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT24 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT24 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT240 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT240 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT241 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT241 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT242 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT242 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT243 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT243 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT244 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT244 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT245 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT245 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT246 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT246 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT247 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT247 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT248 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT248 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT249 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT249 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT25 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT25 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT250 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT250 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT251 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT251 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT252 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT252 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT253 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT253 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT254 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT254 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT255 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT255 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT26 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT26 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT27 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT27 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT28 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT28 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT29 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT29 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT3 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT3 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT30 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT30 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT31 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT31 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT32 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT32 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT33 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT33 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT34 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT34 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT35 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT35 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT36 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT36 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT37 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT37 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT38 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT38 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT39 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT39 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT4 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT4 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT40 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT40 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT41 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT41 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT42 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT42 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT43 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT43 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT44 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT44 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT45 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT45 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT46 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT46 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT47 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT47 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT48 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT48 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT49 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT49 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT5 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT5 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT50 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT50 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT51 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT51 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT52 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT52 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT53 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT53 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT54 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT54 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT55 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT55 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT56 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT56 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT57 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT57 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT58 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT58 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT59 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT59 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT6 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT6 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT60 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT60 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT61 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT61 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT62 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT62 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT63 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT63 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT64 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT64 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT65 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT65 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT66 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT66 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT67 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT67 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT68 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT68 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT69 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT69 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT7 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT7 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT70 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT70 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT71 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT71 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT72 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT72 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT73 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT73 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT74 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT74 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT75 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT75 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT76 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT76 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT77 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT77 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT78 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT78 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT79 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT79 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT8 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT8 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT80 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT80 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT81 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT81 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT82 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT82 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT83 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT83 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT84 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT84 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT85 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT85 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT86 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT86 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT87 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT87 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT88 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT88 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT89 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT89 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT9 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT9 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT90 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT90 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT91 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT91 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT92 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT92 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT93 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT93 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT94 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT94 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT95 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT95 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT96 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT96 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT97 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT97 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT98 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT98 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT99 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT99 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001100011";
attribute LC_LOW_BIT_POS_PROBE_OUT0 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT0 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000000000";
attribute LC_LOW_BIT_POS_PROBE_OUT1 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT1 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000000001";
attribute LC_LOW_BIT_POS_PROBE_OUT10 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT10 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000001010";
attribute LC_LOW_BIT_POS_PROBE_OUT100 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT100 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001100100";
attribute LC_LOW_BIT_POS_PROBE_OUT101 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT101 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001100101";
attribute LC_LOW_BIT_POS_PROBE_OUT102 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT102 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001100110";
attribute LC_LOW_BIT_POS_PROBE_OUT103 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT103 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001100111";
attribute LC_LOW_BIT_POS_PROBE_OUT104 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT104 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001101000";
attribute LC_LOW_BIT_POS_PROBE_OUT105 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT105 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001101001";
attribute LC_LOW_BIT_POS_PROBE_OUT106 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT106 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001101010";
attribute LC_LOW_BIT_POS_PROBE_OUT107 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT107 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001101011";
attribute LC_LOW_BIT_POS_PROBE_OUT108 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT108 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001101100";
attribute LC_LOW_BIT_POS_PROBE_OUT109 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT109 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001101101";
attribute LC_LOW_BIT_POS_PROBE_OUT11 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT11 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000001011";
attribute LC_LOW_BIT_POS_PROBE_OUT110 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT110 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001101110";
attribute LC_LOW_BIT_POS_PROBE_OUT111 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT111 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001101111";
attribute LC_LOW_BIT_POS_PROBE_OUT112 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT112 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001110000";
attribute LC_LOW_BIT_POS_PROBE_OUT113 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT113 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001110001";
attribute LC_LOW_BIT_POS_PROBE_OUT114 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT114 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001110010";
attribute LC_LOW_BIT_POS_PROBE_OUT115 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT115 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001110011";
attribute LC_LOW_BIT_POS_PROBE_OUT116 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT116 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001110100";
attribute LC_LOW_BIT_POS_PROBE_OUT117 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT117 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001110101";
attribute LC_LOW_BIT_POS_PROBE_OUT118 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT118 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001110110";
attribute LC_LOW_BIT_POS_PROBE_OUT119 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT119 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001110111";
attribute LC_LOW_BIT_POS_PROBE_OUT12 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT12 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000001100";
attribute LC_LOW_BIT_POS_PROBE_OUT120 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT120 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001111000";
attribute LC_LOW_BIT_POS_PROBE_OUT121 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT121 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001111001";
attribute LC_LOW_BIT_POS_PROBE_OUT122 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT122 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001111010";
attribute LC_LOW_BIT_POS_PROBE_OUT123 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT123 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001111011";
attribute LC_LOW_BIT_POS_PROBE_OUT124 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT124 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001111100";
attribute LC_LOW_BIT_POS_PROBE_OUT125 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT125 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001111101";
attribute LC_LOW_BIT_POS_PROBE_OUT126 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT126 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001111110";
attribute LC_LOW_BIT_POS_PROBE_OUT127 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT127 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001111111";
attribute LC_LOW_BIT_POS_PROBE_OUT128 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT128 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010000000";
attribute LC_LOW_BIT_POS_PROBE_OUT129 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT129 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010000001";
attribute LC_LOW_BIT_POS_PROBE_OUT13 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT13 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000001101";
attribute LC_LOW_BIT_POS_PROBE_OUT130 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT130 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010000010";
attribute LC_LOW_BIT_POS_PROBE_OUT131 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT131 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010000011";
attribute LC_LOW_BIT_POS_PROBE_OUT132 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT132 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010000100";
attribute LC_LOW_BIT_POS_PROBE_OUT133 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT133 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010000101";
attribute LC_LOW_BIT_POS_PROBE_OUT134 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT134 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010000110";
attribute LC_LOW_BIT_POS_PROBE_OUT135 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT135 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010000111";
attribute LC_LOW_BIT_POS_PROBE_OUT136 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT136 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010001000";
attribute LC_LOW_BIT_POS_PROBE_OUT137 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT137 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010001001";
attribute LC_LOW_BIT_POS_PROBE_OUT138 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT138 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010001010";
attribute LC_LOW_BIT_POS_PROBE_OUT139 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT139 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010001011";
attribute LC_LOW_BIT_POS_PROBE_OUT14 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT14 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000001110";
attribute LC_LOW_BIT_POS_PROBE_OUT140 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT140 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010001100";
attribute LC_LOW_BIT_POS_PROBE_OUT141 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT141 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010001101";
attribute LC_LOW_BIT_POS_PROBE_OUT142 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT142 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010001110";
attribute LC_LOW_BIT_POS_PROBE_OUT143 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT143 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010001111";
attribute LC_LOW_BIT_POS_PROBE_OUT144 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT144 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010010000";
attribute LC_LOW_BIT_POS_PROBE_OUT145 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT145 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010010001";
attribute LC_LOW_BIT_POS_PROBE_OUT146 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT146 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010010010";
attribute LC_LOW_BIT_POS_PROBE_OUT147 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT147 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010010011";
attribute LC_LOW_BIT_POS_PROBE_OUT148 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT148 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010010100";
attribute LC_LOW_BIT_POS_PROBE_OUT149 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT149 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010010101";
attribute LC_LOW_BIT_POS_PROBE_OUT15 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT15 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000001111";
attribute LC_LOW_BIT_POS_PROBE_OUT150 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT150 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010010110";
attribute LC_LOW_BIT_POS_PROBE_OUT151 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT151 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010010111";
attribute LC_LOW_BIT_POS_PROBE_OUT152 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT152 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010011000";
attribute LC_LOW_BIT_POS_PROBE_OUT153 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT153 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010011001";
attribute LC_LOW_BIT_POS_PROBE_OUT154 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT154 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010011010";
attribute LC_LOW_BIT_POS_PROBE_OUT155 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT155 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010011011";
attribute LC_LOW_BIT_POS_PROBE_OUT156 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT156 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010011100";
attribute LC_LOW_BIT_POS_PROBE_OUT157 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT157 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010011101";
attribute LC_LOW_BIT_POS_PROBE_OUT158 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT158 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010011110";
attribute LC_LOW_BIT_POS_PROBE_OUT159 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT159 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010011111";
attribute LC_LOW_BIT_POS_PROBE_OUT16 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT16 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000010000";
attribute LC_LOW_BIT_POS_PROBE_OUT160 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT160 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010100000";
attribute LC_LOW_BIT_POS_PROBE_OUT161 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT161 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010100001";
attribute LC_LOW_BIT_POS_PROBE_OUT162 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT162 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010100010";
attribute LC_LOW_BIT_POS_PROBE_OUT163 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT163 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010100011";
attribute LC_LOW_BIT_POS_PROBE_OUT164 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT164 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010100100";
attribute LC_LOW_BIT_POS_PROBE_OUT165 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT165 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010100101";
attribute LC_LOW_BIT_POS_PROBE_OUT166 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT166 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010100110";
attribute LC_LOW_BIT_POS_PROBE_OUT167 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT167 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010100111";
attribute LC_LOW_BIT_POS_PROBE_OUT168 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT168 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010101000";
attribute LC_LOW_BIT_POS_PROBE_OUT169 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT169 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010101001";
attribute LC_LOW_BIT_POS_PROBE_OUT17 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT17 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000010001";
attribute LC_LOW_BIT_POS_PROBE_OUT170 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT170 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010101010";
attribute LC_LOW_BIT_POS_PROBE_OUT171 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT171 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010101011";
attribute LC_LOW_BIT_POS_PROBE_OUT172 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT172 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010101100";
attribute LC_LOW_BIT_POS_PROBE_OUT173 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT173 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010101101";
attribute LC_LOW_BIT_POS_PROBE_OUT174 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT174 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010101110";
attribute LC_LOW_BIT_POS_PROBE_OUT175 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT175 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010101111";
attribute LC_LOW_BIT_POS_PROBE_OUT176 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT176 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010110000";
attribute LC_LOW_BIT_POS_PROBE_OUT177 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT177 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010110001";
attribute LC_LOW_BIT_POS_PROBE_OUT178 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT178 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010110010";
attribute LC_LOW_BIT_POS_PROBE_OUT179 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT179 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010110011";
attribute LC_LOW_BIT_POS_PROBE_OUT18 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT18 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000010010";
attribute LC_LOW_BIT_POS_PROBE_OUT180 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT180 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010110100";
attribute LC_LOW_BIT_POS_PROBE_OUT181 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT181 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010110101";
attribute LC_LOW_BIT_POS_PROBE_OUT182 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT182 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010110110";
attribute LC_LOW_BIT_POS_PROBE_OUT183 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT183 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010110111";
attribute LC_LOW_BIT_POS_PROBE_OUT184 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT184 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010111000";
attribute LC_LOW_BIT_POS_PROBE_OUT185 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT185 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010111001";
attribute LC_LOW_BIT_POS_PROBE_OUT186 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT186 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010111010";
attribute LC_LOW_BIT_POS_PROBE_OUT187 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT187 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010111011";
attribute LC_LOW_BIT_POS_PROBE_OUT188 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT188 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010111100";
attribute LC_LOW_BIT_POS_PROBE_OUT189 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT189 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010111101";
attribute LC_LOW_BIT_POS_PROBE_OUT19 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT19 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000010011";
attribute LC_LOW_BIT_POS_PROBE_OUT190 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT190 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010111110";
attribute LC_LOW_BIT_POS_PROBE_OUT191 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT191 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000010111111";
attribute LC_LOW_BIT_POS_PROBE_OUT192 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT192 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011000000";
attribute LC_LOW_BIT_POS_PROBE_OUT193 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT193 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011000001";
attribute LC_LOW_BIT_POS_PROBE_OUT194 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT194 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011000010";
attribute LC_LOW_BIT_POS_PROBE_OUT195 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT195 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011000011";
attribute LC_LOW_BIT_POS_PROBE_OUT196 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT196 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011000100";
attribute LC_LOW_BIT_POS_PROBE_OUT197 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT197 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011000101";
attribute LC_LOW_BIT_POS_PROBE_OUT198 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT198 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011000110";
attribute LC_LOW_BIT_POS_PROBE_OUT199 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT199 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011000111";
attribute LC_LOW_BIT_POS_PROBE_OUT2 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT2 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000000010";
attribute LC_LOW_BIT_POS_PROBE_OUT20 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT20 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000010100";
attribute LC_LOW_BIT_POS_PROBE_OUT200 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT200 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011001000";
attribute LC_LOW_BIT_POS_PROBE_OUT201 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT201 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011001001";
attribute LC_LOW_BIT_POS_PROBE_OUT202 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT202 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011001010";
attribute LC_LOW_BIT_POS_PROBE_OUT203 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT203 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011001011";
attribute LC_LOW_BIT_POS_PROBE_OUT204 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT204 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011001100";
attribute LC_LOW_BIT_POS_PROBE_OUT205 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT205 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011001101";
attribute LC_LOW_BIT_POS_PROBE_OUT206 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT206 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011001110";
attribute LC_LOW_BIT_POS_PROBE_OUT207 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT207 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011001111";
attribute LC_LOW_BIT_POS_PROBE_OUT208 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT208 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011010000";
attribute LC_LOW_BIT_POS_PROBE_OUT209 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT209 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011010001";
attribute LC_LOW_BIT_POS_PROBE_OUT21 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT21 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000010101";
attribute LC_LOW_BIT_POS_PROBE_OUT210 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT210 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011010010";
attribute LC_LOW_BIT_POS_PROBE_OUT211 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT211 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011010011";
attribute LC_LOW_BIT_POS_PROBE_OUT212 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT212 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011010100";
attribute LC_LOW_BIT_POS_PROBE_OUT213 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT213 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011010101";
attribute LC_LOW_BIT_POS_PROBE_OUT214 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT214 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011010110";
attribute LC_LOW_BIT_POS_PROBE_OUT215 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT215 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011010111";
attribute LC_LOW_BIT_POS_PROBE_OUT216 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT216 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011011000";
attribute LC_LOW_BIT_POS_PROBE_OUT217 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT217 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011011001";
attribute LC_LOW_BIT_POS_PROBE_OUT218 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT218 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011011010";
attribute LC_LOW_BIT_POS_PROBE_OUT219 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT219 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011011011";
attribute LC_LOW_BIT_POS_PROBE_OUT22 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT22 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000010110";
attribute LC_LOW_BIT_POS_PROBE_OUT220 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT220 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011011100";
attribute LC_LOW_BIT_POS_PROBE_OUT221 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT221 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011011101";
attribute LC_LOW_BIT_POS_PROBE_OUT222 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT222 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011011110";
attribute LC_LOW_BIT_POS_PROBE_OUT223 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT223 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011011111";
attribute LC_LOW_BIT_POS_PROBE_OUT224 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT224 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011100000";
attribute LC_LOW_BIT_POS_PROBE_OUT225 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT225 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011100001";
attribute LC_LOW_BIT_POS_PROBE_OUT226 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT226 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011100010";
attribute LC_LOW_BIT_POS_PROBE_OUT227 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT227 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011100011";
attribute LC_LOW_BIT_POS_PROBE_OUT228 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT228 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011100100";
attribute LC_LOW_BIT_POS_PROBE_OUT229 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT229 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011100101";
attribute LC_LOW_BIT_POS_PROBE_OUT23 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT23 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000010111";
attribute LC_LOW_BIT_POS_PROBE_OUT230 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT230 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011100110";
attribute LC_LOW_BIT_POS_PROBE_OUT231 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT231 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011100111";
attribute LC_LOW_BIT_POS_PROBE_OUT232 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT232 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011101000";
attribute LC_LOW_BIT_POS_PROBE_OUT233 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT233 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011101001";
attribute LC_LOW_BIT_POS_PROBE_OUT234 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT234 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011101010";
attribute LC_LOW_BIT_POS_PROBE_OUT235 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT235 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011101011";
attribute LC_LOW_BIT_POS_PROBE_OUT236 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT236 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011101100";
attribute LC_LOW_BIT_POS_PROBE_OUT237 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT237 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011101101";
attribute LC_LOW_BIT_POS_PROBE_OUT238 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT238 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011101110";
attribute LC_LOW_BIT_POS_PROBE_OUT239 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT239 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011101111";
attribute LC_LOW_BIT_POS_PROBE_OUT24 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT24 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000011000";
attribute LC_LOW_BIT_POS_PROBE_OUT240 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT240 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011110000";
attribute LC_LOW_BIT_POS_PROBE_OUT241 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT241 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011110001";
attribute LC_LOW_BIT_POS_PROBE_OUT242 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT242 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011110010";
attribute LC_LOW_BIT_POS_PROBE_OUT243 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT243 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011110011";
attribute LC_LOW_BIT_POS_PROBE_OUT244 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT244 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011110100";
attribute LC_LOW_BIT_POS_PROBE_OUT245 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT245 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011110101";
attribute LC_LOW_BIT_POS_PROBE_OUT246 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT246 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011110110";
attribute LC_LOW_BIT_POS_PROBE_OUT247 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT247 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011110111";
attribute LC_LOW_BIT_POS_PROBE_OUT248 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT248 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011111000";
attribute LC_LOW_BIT_POS_PROBE_OUT249 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT249 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011111001";
attribute LC_LOW_BIT_POS_PROBE_OUT25 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT25 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000011001";
attribute LC_LOW_BIT_POS_PROBE_OUT250 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT250 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011111010";
attribute LC_LOW_BIT_POS_PROBE_OUT251 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT251 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011111011";
attribute LC_LOW_BIT_POS_PROBE_OUT252 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT252 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011111100";
attribute LC_LOW_BIT_POS_PROBE_OUT253 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT253 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011111101";
attribute LC_LOW_BIT_POS_PROBE_OUT254 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT254 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011111110";
attribute LC_LOW_BIT_POS_PROBE_OUT255 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT255 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000011111111";
attribute LC_LOW_BIT_POS_PROBE_OUT26 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT26 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000011010";
attribute LC_LOW_BIT_POS_PROBE_OUT27 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT27 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000011011";
attribute LC_LOW_BIT_POS_PROBE_OUT28 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT28 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000011100";
attribute LC_LOW_BIT_POS_PROBE_OUT29 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT29 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000011101";
attribute LC_LOW_BIT_POS_PROBE_OUT3 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT3 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000000011";
attribute LC_LOW_BIT_POS_PROBE_OUT30 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT30 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000011110";
attribute LC_LOW_BIT_POS_PROBE_OUT31 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT31 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000011111";
attribute LC_LOW_BIT_POS_PROBE_OUT32 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT32 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000100000";
attribute LC_LOW_BIT_POS_PROBE_OUT33 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT33 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000100001";
attribute LC_LOW_BIT_POS_PROBE_OUT34 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT34 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000100010";
attribute LC_LOW_BIT_POS_PROBE_OUT35 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT35 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000100011";
attribute LC_LOW_BIT_POS_PROBE_OUT36 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT36 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000100100";
attribute LC_LOW_BIT_POS_PROBE_OUT37 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT37 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000100101";
attribute LC_LOW_BIT_POS_PROBE_OUT38 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT38 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000100110";
attribute LC_LOW_BIT_POS_PROBE_OUT39 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT39 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000100111";
attribute LC_LOW_BIT_POS_PROBE_OUT4 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT4 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000000100";
attribute LC_LOW_BIT_POS_PROBE_OUT40 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT40 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000101000";
attribute LC_LOW_BIT_POS_PROBE_OUT41 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT41 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000101001";
attribute LC_LOW_BIT_POS_PROBE_OUT42 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT42 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000101010";
attribute LC_LOW_BIT_POS_PROBE_OUT43 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT43 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000101011";
attribute LC_LOW_BIT_POS_PROBE_OUT44 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT44 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000101100";
attribute LC_LOW_BIT_POS_PROBE_OUT45 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT45 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000101101";
attribute LC_LOW_BIT_POS_PROBE_OUT46 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT46 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000101110";
attribute LC_LOW_BIT_POS_PROBE_OUT47 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT47 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000101111";
attribute LC_LOW_BIT_POS_PROBE_OUT48 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT48 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000110000";
attribute LC_LOW_BIT_POS_PROBE_OUT49 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT49 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000110001";
attribute LC_LOW_BIT_POS_PROBE_OUT5 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT5 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000000101";
attribute LC_LOW_BIT_POS_PROBE_OUT50 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT50 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000110010";
attribute LC_LOW_BIT_POS_PROBE_OUT51 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT51 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000110011";
attribute LC_LOW_BIT_POS_PROBE_OUT52 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT52 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000110100";
attribute LC_LOW_BIT_POS_PROBE_OUT53 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT53 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000110101";
attribute LC_LOW_BIT_POS_PROBE_OUT54 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT54 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000110110";
attribute LC_LOW_BIT_POS_PROBE_OUT55 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT55 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000110111";
attribute LC_LOW_BIT_POS_PROBE_OUT56 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT56 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000111000";
attribute LC_LOW_BIT_POS_PROBE_OUT57 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT57 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000111001";
attribute LC_LOW_BIT_POS_PROBE_OUT58 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT58 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000111010";
attribute LC_LOW_BIT_POS_PROBE_OUT59 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT59 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000111011";
attribute LC_LOW_BIT_POS_PROBE_OUT6 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT6 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000000110";
attribute LC_LOW_BIT_POS_PROBE_OUT60 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT60 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000111100";
attribute LC_LOW_BIT_POS_PROBE_OUT61 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT61 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000111101";
attribute LC_LOW_BIT_POS_PROBE_OUT62 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT62 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000111110";
attribute LC_LOW_BIT_POS_PROBE_OUT63 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT63 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000111111";
attribute LC_LOW_BIT_POS_PROBE_OUT64 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT64 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001000000";
attribute LC_LOW_BIT_POS_PROBE_OUT65 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT65 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001000001";
attribute LC_LOW_BIT_POS_PROBE_OUT66 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT66 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001000010";
attribute LC_LOW_BIT_POS_PROBE_OUT67 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT67 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001000011";
attribute LC_LOW_BIT_POS_PROBE_OUT68 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT68 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001000100";
attribute LC_LOW_BIT_POS_PROBE_OUT69 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT69 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001000101";
attribute LC_LOW_BIT_POS_PROBE_OUT7 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT7 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000000111";
attribute LC_LOW_BIT_POS_PROBE_OUT70 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT70 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001000110";
attribute LC_LOW_BIT_POS_PROBE_OUT71 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT71 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001000111";
attribute LC_LOW_BIT_POS_PROBE_OUT72 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT72 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001001000";
attribute LC_LOW_BIT_POS_PROBE_OUT73 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT73 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001001001";
attribute LC_LOW_BIT_POS_PROBE_OUT74 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT74 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001001010";
attribute LC_LOW_BIT_POS_PROBE_OUT75 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT75 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001001011";
attribute LC_LOW_BIT_POS_PROBE_OUT76 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT76 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001001100";
attribute LC_LOW_BIT_POS_PROBE_OUT77 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT77 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001001101";
attribute LC_LOW_BIT_POS_PROBE_OUT78 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT78 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001001110";
attribute LC_LOW_BIT_POS_PROBE_OUT79 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT79 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001001111";
attribute LC_LOW_BIT_POS_PROBE_OUT8 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT8 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000001000";
attribute LC_LOW_BIT_POS_PROBE_OUT80 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT80 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001010000";
attribute LC_LOW_BIT_POS_PROBE_OUT81 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT81 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001010001";
attribute LC_LOW_BIT_POS_PROBE_OUT82 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT82 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001010010";
attribute LC_LOW_BIT_POS_PROBE_OUT83 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT83 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001010011";
attribute LC_LOW_BIT_POS_PROBE_OUT84 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT84 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001010100";
attribute LC_LOW_BIT_POS_PROBE_OUT85 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT85 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001010101";
attribute LC_LOW_BIT_POS_PROBE_OUT86 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT86 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001010110";
attribute LC_LOW_BIT_POS_PROBE_OUT87 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT87 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001010111";
attribute LC_LOW_BIT_POS_PROBE_OUT88 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT88 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001011000";
attribute LC_LOW_BIT_POS_PROBE_OUT89 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT89 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001011001";
attribute LC_LOW_BIT_POS_PROBE_OUT9 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT9 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000000001001";
attribute LC_LOW_BIT_POS_PROBE_OUT90 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT90 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001011010";
attribute LC_LOW_BIT_POS_PROBE_OUT91 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT91 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001011011";
attribute LC_LOW_BIT_POS_PROBE_OUT92 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT92 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001011100";
attribute LC_LOW_BIT_POS_PROBE_OUT93 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT93 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001011101";
attribute LC_LOW_BIT_POS_PROBE_OUT94 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT94 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001011110";
attribute LC_LOW_BIT_POS_PROBE_OUT95 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT95 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001011111";
attribute LC_LOW_BIT_POS_PROBE_OUT96 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT96 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001100000";
attribute LC_LOW_BIT_POS_PROBE_OUT97 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT97 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001100001";
attribute LC_LOW_BIT_POS_PROBE_OUT98 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT98 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001100010";
attribute LC_LOW_BIT_POS_PROBE_OUT99 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT99 of vio_0_vio_v3_0_13_vio : entity is "16'b0000000001100011";
attribute LC_PROBE_IN_WIDTH_STRING : string;
attribute LC_PROBE_IN_WIDTH_STRING of vio_0_vio_v3_0_13_vio : entity is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING of vio_0_vio_v3_0_13_vio : entity is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_INIT_VAL_STRING : string;
attribute LC_PROBE_OUT_INIT_VAL_STRING of vio_0_vio_v3_0_13_vio : entity is "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING of vio_0_vio_v3_0_13_vio : entity is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_WIDTH_STRING : string;
attribute LC_PROBE_OUT_WIDTH_STRING of vio_0_vio_v3_0_13_vio : entity is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_TOTAL_PROBE_IN_WIDTH : integer;
attribute LC_TOTAL_PROBE_IN_WIDTH of vio_0_vio_v3_0_13_vio : entity is 4;
attribute LC_TOTAL_PROBE_OUT_WIDTH : integer;
attribute LC_TOTAL_PROBE_OUT_WIDTH of vio_0_vio_v3_0_13_vio : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of vio_0_vio_v3_0_13_vio : entity is "vio_v3_0_13_vio";
attribute dont_touch : string;
attribute dont_touch of vio_0_vio_v3_0_13_vio : entity is "true";
end vio_0_vio_v3_0_13_vio;
architecture STRUCTURE of vio_0_vio_v3_0_13_vio is
signal \<const0>\ : STD_LOGIC;
signal Bus_Data_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal DECODER_INST_n_1 : STD_LOGIC;
signal DECODER_INST_n_2 : STD_LOGIC;
signal DECODER_INST_n_3 : STD_LOGIC;
signal DECODER_INST_n_4 : STD_LOGIC;
signal bus_addr : STD_LOGIC_VECTOR ( 16 downto 0 );
signal bus_clk : STD_LOGIC;
attribute DONT_TOUCH_boolean : boolean;
attribute DONT_TOUCH_boolean of bus_clk : signal is std.standard.true;
signal \bus_data_int_reg_n_0_[0]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[10]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[11]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[12]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[13]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[14]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[15]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[2]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[3]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[4]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[5]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[6]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[7]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[8]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[9]\ : STD_LOGIC;
signal bus_den : STD_LOGIC;
signal bus_di : STD_LOGIC_VECTOR ( 15 downto 0 );
signal bus_do : STD_LOGIC_VECTOR ( 15 downto 0 );
signal bus_drdy : STD_LOGIC;
signal bus_dwe : STD_LOGIC;
signal bus_rst : STD_LOGIC;
signal p_0_in : STD_LOGIC;
attribute C_BUILD_REVISION of U_XSDB_SLAVE : label is 0;
attribute C_CORE_INFO1 of U_XSDB_SLAVE : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 of U_XSDB_SLAVE : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER of U_XSDB_SLAVE : label is 2;
attribute C_CORE_MINOR_VER of U_XSDB_SLAVE : label is 0;
attribute C_CORE_TYPE of U_XSDB_SLAVE : label is 2;
attribute C_CSE_DRV_VER of U_XSDB_SLAVE : label is 1;
attribute C_MAJOR_VERSION of U_XSDB_SLAVE : label is 2013;
attribute C_MINOR_VERSION of U_XSDB_SLAVE : label is 1;
attribute C_NEXT_SLAVE of U_XSDB_SLAVE : label is 0;
attribute C_PIPE_IFACE of U_XSDB_SLAVE : label is 0;
attribute C_USE_TEST_REG of U_XSDB_SLAVE : label is 1;
attribute C_XDEVICEFAMILY of U_XSDB_SLAVE : label is "kintex7";
attribute C_XSDB_SLAVE_TYPE of U_XSDB_SLAVE : label is 33;
attribute DONT_TOUCH_boolean of U_XSDB_SLAVE : label is std.standard.true;
begin
probe_out0(0) <= \<const0>\;
probe_out1(0) <= \<const0>\;
probe_out10(0) <= \<const0>\;
probe_out100(0) <= \<const0>\;
probe_out101(0) <= \<const0>\;
probe_out102(0) <= \<const0>\;
probe_out103(0) <= \<const0>\;
probe_out104(0) <= \<const0>\;
probe_out105(0) <= \<const0>\;
probe_out106(0) <= \<const0>\;
probe_out107(0) <= \<const0>\;
probe_out108(0) <= \<const0>\;
probe_out109(0) <= \<const0>\;
probe_out11(0) <= \<const0>\;
probe_out110(0) <= \<const0>\;
probe_out111(0) <= \<const0>\;
probe_out112(0) <= \<const0>\;
probe_out113(0) <= \<const0>\;
probe_out114(0) <= \<const0>\;
probe_out115(0) <= \<const0>\;
probe_out116(0) <= \<const0>\;
probe_out117(0) <= \<const0>\;
probe_out118(0) <= \<const0>\;
probe_out119(0) <= \<const0>\;
probe_out12(0) <= \<const0>\;
probe_out120(0) <= \<const0>\;
probe_out121(0) <= \<const0>\;
probe_out122(0) <= \<const0>\;
probe_out123(0) <= \<const0>\;
probe_out124(0) <= \<const0>\;
probe_out125(0) <= \<const0>\;
probe_out126(0) <= \<const0>\;
probe_out127(0) <= \<const0>\;
probe_out128(0) <= \<const0>\;
probe_out129(0) <= \<const0>\;
probe_out13(0) <= \<const0>\;
probe_out130(0) <= \<const0>\;
probe_out131(0) <= \<const0>\;
probe_out132(0) <= \<const0>\;
probe_out133(0) <= \<const0>\;
probe_out134(0) <= \<const0>\;
probe_out135(0) <= \<const0>\;
probe_out136(0) <= \<const0>\;
probe_out137(0) <= \<const0>\;
probe_out138(0) <= \<const0>\;
probe_out139(0) <= \<const0>\;
probe_out14(0) <= \<const0>\;
probe_out140(0) <= \<const0>\;
probe_out141(0) <= \<const0>\;
probe_out142(0) <= \<const0>\;
probe_out143(0) <= \<const0>\;
probe_out144(0) <= \<const0>\;
probe_out145(0) <= \<const0>\;
probe_out146(0) <= \<const0>\;
probe_out147(0) <= \<const0>\;
probe_out148(0) <= \<const0>\;
probe_out149(0) <= \<const0>\;
probe_out15(0) <= \<const0>\;
probe_out150(0) <= \<const0>\;
probe_out151(0) <= \<const0>\;
probe_out152(0) <= \<const0>\;
probe_out153(0) <= \<const0>\;
probe_out154(0) <= \<const0>\;
probe_out155(0) <= \<const0>\;
probe_out156(0) <= \<const0>\;
probe_out157(0) <= \<const0>\;
probe_out158(0) <= \<const0>\;
probe_out159(0) <= \<const0>\;
probe_out16(0) <= \<const0>\;
probe_out160(0) <= \<const0>\;
probe_out161(0) <= \<const0>\;
probe_out162(0) <= \<const0>\;
probe_out163(0) <= \<const0>\;
probe_out164(0) <= \<const0>\;
probe_out165(0) <= \<const0>\;
probe_out166(0) <= \<const0>\;
probe_out167(0) <= \<const0>\;
probe_out168(0) <= \<const0>\;
probe_out169(0) <= \<const0>\;
probe_out17(0) <= \<const0>\;
probe_out170(0) <= \<const0>\;
probe_out171(0) <= \<const0>\;
probe_out172(0) <= \<const0>\;
probe_out173(0) <= \<const0>\;
probe_out174(0) <= \<const0>\;
probe_out175(0) <= \<const0>\;
probe_out176(0) <= \<const0>\;
probe_out177(0) <= \<const0>\;
probe_out178(0) <= \<const0>\;
probe_out179(0) <= \<const0>\;
probe_out18(0) <= \<const0>\;
probe_out180(0) <= \<const0>\;
probe_out181(0) <= \<const0>\;
probe_out182(0) <= \<const0>\;
probe_out183(0) <= \<const0>\;
probe_out184(0) <= \<const0>\;
probe_out185(0) <= \<const0>\;
probe_out186(0) <= \<const0>\;
probe_out187(0) <= \<const0>\;
probe_out188(0) <= \<const0>\;
probe_out189(0) <= \<const0>\;
probe_out19(0) <= \<const0>\;
probe_out190(0) <= \<const0>\;
probe_out191(0) <= \<const0>\;
probe_out192(0) <= \<const0>\;
probe_out193(0) <= \<const0>\;
probe_out194(0) <= \<const0>\;
probe_out195(0) <= \<const0>\;
probe_out196(0) <= \<const0>\;
probe_out197(0) <= \<const0>\;
probe_out198(0) <= \<const0>\;
probe_out199(0) <= \<const0>\;
probe_out2(0) <= \<const0>\;
probe_out20(0) <= \<const0>\;
probe_out200(0) <= \<const0>\;
probe_out201(0) <= \<const0>\;
probe_out202(0) <= \<const0>\;
probe_out203(0) <= \<const0>\;
probe_out204(0) <= \<const0>\;
probe_out205(0) <= \<const0>\;
probe_out206(0) <= \<const0>\;
probe_out207(0) <= \<const0>\;
probe_out208(0) <= \<const0>\;
probe_out209(0) <= \<const0>\;
probe_out21(0) <= \<const0>\;
probe_out210(0) <= \<const0>\;
probe_out211(0) <= \<const0>\;
probe_out212(0) <= \<const0>\;
probe_out213(0) <= \<const0>\;
probe_out214(0) <= \<const0>\;
probe_out215(0) <= \<const0>\;
probe_out216(0) <= \<const0>\;
probe_out217(0) <= \<const0>\;
probe_out218(0) <= \<const0>\;
probe_out219(0) <= \<const0>\;
probe_out22(0) <= \<const0>\;
probe_out220(0) <= \<const0>\;
probe_out221(0) <= \<const0>\;
probe_out222(0) <= \<const0>\;
probe_out223(0) <= \<const0>\;
probe_out224(0) <= \<const0>\;
probe_out225(0) <= \<const0>\;
probe_out226(0) <= \<const0>\;
probe_out227(0) <= \<const0>\;
probe_out228(0) <= \<const0>\;
probe_out229(0) <= \<const0>\;
probe_out23(0) <= \<const0>\;
probe_out230(0) <= \<const0>\;
probe_out231(0) <= \<const0>\;
probe_out232(0) <= \<const0>\;
probe_out233(0) <= \<const0>\;
probe_out234(0) <= \<const0>\;
probe_out235(0) <= \<const0>\;
probe_out236(0) <= \<const0>\;
probe_out237(0) <= \<const0>\;
probe_out238(0) <= \<const0>\;
probe_out239(0) <= \<const0>\;
probe_out24(0) <= \<const0>\;
probe_out240(0) <= \<const0>\;
probe_out241(0) <= \<const0>\;
probe_out242(0) <= \<const0>\;
probe_out243(0) <= \<const0>\;
probe_out244(0) <= \<const0>\;
probe_out245(0) <= \<const0>\;
probe_out246(0) <= \<const0>\;
probe_out247(0) <= \<const0>\;
probe_out248(0) <= \<const0>\;
probe_out249(0) <= \<const0>\;
probe_out25(0) <= \<const0>\;
probe_out250(0) <= \<const0>\;
probe_out251(0) <= \<const0>\;
probe_out252(0) <= \<const0>\;
probe_out253(0) <= \<const0>\;
probe_out254(0) <= \<const0>\;
probe_out255(0) <= \<const0>\;
probe_out26(0) <= \<const0>\;
probe_out27(0) <= \<const0>\;
probe_out28(0) <= \<const0>\;
probe_out29(0) <= \<const0>\;
probe_out3(0) <= \<const0>\;
probe_out30(0) <= \<const0>\;
probe_out31(0) <= \<const0>\;
probe_out32(0) <= \<const0>\;
probe_out33(0) <= \<const0>\;
probe_out34(0) <= \<const0>\;
probe_out35(0) <= \<const0>\;
probe_out36(0) <= \<const0>\;
probe_out37(0) <= \<const0>\;
probe_out38(0) <= \<const0>\;
probe_out39(0) <= \<const0>\;
probe_out4(0) <= \<const0>\;
probe_out40(0) <= \<const0>\;
probe_out41(0) <= \<const0>\;
probe_out42(0) <= \<const0>\;
probe_out43(0) <= \<const0>\;
probe_out44(0) <= \<const0>\;
probe_out45(0) <= \<const0>\;
probe_out46(0) <= \<const0>\;
probe_out47(0) <= \<const0>\;
probe_out48(0) <= \<const0>\;
probe_out49(0) <= \<const0>\;
probe_out5(0) <= \<const0>\;
probe_out50(0) <= \<const0>\;
probe_out51(0) <= \<const0>\;
probe_out52(0) <= \<const0>\;
probe_out53(0) <= \<const0>\;
probe_out54(0) <= \<const0>\;
probe_out55(0) <= \<const0>\;
probe_out56(0) <= \<const0>\;
probe_out57(0) <= \<const0>\;
probe_out58(0) <= \<const0>\;
probe_out59(0) <= \<const0>\;
probe_out6(0) <= \<const0>\;
probe_out60(0) <= \<const0>\;
probe_out61(0) <= \<const0>\;
probe_out62(0) <= \<const0>\;
probe_out63(0) <= \<const0>\;
probe_out64(0) <= \<const0>\;
probe_out65(0) <= \<const0>\;
probe_out66(0) <= \<const0>\;
probe_out67(0) <= \<const0>\;
probe_out68(0) <= \<const0>\;
probe_out69(0) <= \<const0>\;
probe_out7(0) <= \<const0>\;
probe_out70(0) <= \<const0>\;
probe_out71(0) <= \<const0>\;
probe_out72(0) <= \<const0>\;
probe_out73(0) <= \<const0>\;
probe_out74(0) <= \<const0>\;
probe_out75(0) <= \<const0>\;
probe_out76(0) <= \<const0>\;
probe_out77(0) <= \<const0>\;
probe_out78(0) <= \<const0>\;
probe_out79(0) <= \<const0>\;
probe_out8(0) <= \<const0>\;
probe_out80(0) <= \<const0>\;
probe_out81(0) <= \<const0>\;
probe_out82(0) <= \<const0>\;
probe_out83(0) <= \<const0>\;
probe_out84(0) <= \<const0>\;
probe_out85(0) <= \<const0>\;
probe_out86(0) <= \<const0>\;
probe_out87(0) <= \<const0>\;
probe_out88(0) <= \<const0>\;
probe_out89(0) <= \<const0>\;
probe_out9(0) <= \<const0>\;
probe_out90(0) <= \<const0>\;
probe_out91(0) <= \<const0>\;
probe_out92(0) <= \<const0>\;
probe_out93(0) <= \<const0>\;
probe_out94(0) <= \<const0>\;
probe_out95(0) <= \<const0>\;
probe_out96(0) <= \<const0>\;
probe_out97(0) <= \<const0>\;
probe_out98(0) <= \<const0>\;
probe_out99(0) <= \<const0>\;
DECODER_INST: entity work.vio_0_vio_v3_0_13_decoder
port map (
\Bus_Data_out_reg[11]\(11 downto 0) => Bus_Data_out(11 downto 0),
E(0) => DECODER_INST_n_4,
Q(15) => \bus_data_int_reg_n_0_[15]\,
Q(14) => \bus_data_int_reg_n_0_[14]\,
Q(13) => \bus_data_int_reg_n_0_[13]\,
Q(12) => \bus_data_int_reg_n_0_[12]\,
Q(11) => \bus_data_int_reg_n_0_[11]\,
Q(10) => \bus_data_int_reg_n_0_[10]\,
Q(9) => \bus_data_int_reg_n_0_[9]\,
Q(8) => \bus_data_int_reg_n_0_[8]\,
Q(7) => \bus_data_int_reg_n_0_[7]\,
Q(6) => \bus_data_int_reg_n_0_[6]\,
Q(5) => \bus_data_int_reg_n_0_[5]\,
Q(4) => \bus_data_int_reg_n_0_[4]\,
Q(3) => \bus_data_int_reg_n_0_[3]\,
Q(2) => \bus_data_int_reg_n_0_[2]\,
Q(1) => p_0_in,
Q(0) => \bus_data_int_reg_n_0_[0]\,
\out\ => bus_clk,
s_daddr_o(16 downto 0) => bus_addr(16 downto 0),
s_den_o => bus_den,
s_do_i(15 downto 0) => bus_do(15 downto 0),
s_drdy_i => bus_drdy,
s_dwe_o => bus_dwe,
s_rst_o => bus_rst,
\wr_en_reg[4]_0\ => DECODER_INST_n_1,
\wr_en_reg[4]_1\ => DECODER_INST_n_2,
\wr_en_reg[4]_2\ => DECODER_INST_n_3
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
PROBE_IN_INST: entity work.vio_0_vio_v3_0_13_probe_in_one
port map (
D(3) => probe_in3(0),
D(2) => probe_in2(0),
D(1) => probe_in1(0),
D(0) => probe_in0(0),
E(0) => DECODER_INST_n_4,
Q(11 downto 0) => Bus_Data_out(11 downto 0),
clk => clk,
\out\ => bus_clk,
s_daddr_o(2 downto 0) => bus_addr(2 downto 0),
s_den_o => bus_den,
s_dwe_o => bus_dwe,
s_rst_o => bus_rst,
\wr_en[4]_i_3\ => DECODER_INST_n_1,
\wr_en[4]_i_4\ => DECODER_INST_n_3,
\wr_en[4]_i_5\ => DECODER_INST_n_2
);
U_XSDB_SLAVE: entity work.vio_0_xsdbs_v1_0_2_xsdbs
port map (
s_daddr_o(16 downto 0) => bus_addr(16 downto 0),
s_dclk_o => bus_clk,
s_den_o => bus_den,
s_di_o(15 downto 0) => bus_di(15 downto 0),
s_do_i(15 downto 0) => bus_do(15 downto 0),
s_drdy_i => bus_drdy,
s_dwe_o => bus_dwe,
s_rst_o => bus_rst,
sl_iport_i(36 downto 0) => sl_iport0(36 downto 0),
sl_oport_o(16 downto 0) => sl_oport0(16 downto 0)
);
\bus_data_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(0),
Q => \bus_data_int_reg_n_0_[0]\,
R => '0'
);
\bus_data_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(10),
Q => \bus_data_int_reg_n_0_[10]\,
R => '0'
);
\bus_data_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(11),
Q => \bus_data_int_reg_n_0_[11]\,
R => '0'
);
\bus_data_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(12),
Q => \bus_data_int_reg_n_0_[12]\,
R => '0'
);
\bus_data_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(13),
Q => \bus_data_int_reg_n_0_[13]\,
R => '0'
);
\bus_data_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(14),
Q => \bus_data_int_reg_n_0_[14]\,
R => '0'
);
\bus_data_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(15),
Q => \bus_data_int_reg_n_0_[15]\,
R => '0'
);
\bus_data_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(1),
Q => p_0_in,
R => '0'
);
\bus_data_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(2),
Q => \bus_data_int_reg_n_0_[2]\,
R => '0'
);
\bus_data_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(3),
Q => \bus_data_int_reg_n_0_[3]\,
R => '0'
);
\bus_data_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(4),
Q => \bus_data_int_reg_n_0_[4]\,
R => '0'
);
\bus_data_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(5),
Q => \bus_data_int_reg_n_0_[5]\,
R => '0'
);
\bus_data_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(6),
Q => \bus_data_int_reg_n_0_[6]\,
R => '0'
);
\bus_data_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(7),
Q => \bus_data_int_reg_n_0_[7]\,
R => '0'
);
\bus_data_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(8),
Q => \bus_data_int_reg_n_0_[8]\,
R => '0'
);
\bus_data_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(9),
Q => \bus_data_int_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vio_0 is
port (
clk : in STD_LOGIC;
probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in3 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of vio_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of vio_0 : entity is "vio_0,vio,{}";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of vio_0 : entity is "vio,Vivado 2016.3";
end vio_0;
architecture STRUCTURE of vio_0 is
signal NLW_inst_probe_out0_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out100_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out101_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out102_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out103_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out104_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out105_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out106_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out107_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out108_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out109_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out110_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out111_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out112_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out113_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out114_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out115_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out116_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out117_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out118_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out119_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out120_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out121_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out122_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out123_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out124_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out125_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out126_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out127_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out128_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out129_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out130_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out131_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out132_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out133_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out134_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out135_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out136_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out137_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out138_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out139_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out140_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out141_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out142_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out143_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out144_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out145_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out146_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out147_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out148_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out149_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out150_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out151_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out152_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out153_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out154_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out155_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out156_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out157_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out158_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out159_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out160_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out161_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out162_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out163_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out164_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out165_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out166_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out167_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out168_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out169_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out170_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out171_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out172_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out173_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out174_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out175_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out176_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out177_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out178_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out179_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out180_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out181_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out182_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out183_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out184_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out185_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out186_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out187_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out188_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out189_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out190_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out191_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out192_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out193_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out194_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out195_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out196_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out197_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out198_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out199_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out200_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out201_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out202_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out203_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out204_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out205_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out206_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out207_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out208_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out209_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out210_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out211_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out212_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out213_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out214_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out215_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out216_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out217_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out218_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out219_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out220_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out221_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out222_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out223_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out224_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out225_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out226_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out227_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out228_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out229_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out230_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out231_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out232_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out233_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out234_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out235_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out236_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out237_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out238_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out239_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out240_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out241_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out242_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out243_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out244_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out245_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out246_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out247_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out248_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out249_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out250_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out251_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out252_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out253_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out254_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out255_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out32_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out33_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out34_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out35_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out36_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out37_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out38_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out39_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out40_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out41_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out42_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out43_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out44_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out45_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out46_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out47_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out48_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out49_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out50_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out51_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out52_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out53_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out54_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out55_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out56_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out57_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out58_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out59_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out60_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out61_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out62_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out63_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out64_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out65_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out66_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out67_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out68_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out69_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out70_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out71_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out72_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out73_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out74_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out75_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out76_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out77_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out78_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out79_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out80_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out81_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out82_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out83_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out84_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out85_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out86_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out87_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out88_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out89_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out90_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out91_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out92_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out93_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out94_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out95_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out96_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out97_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out98_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out99_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_sl_oport0_UNCONNECTED : STD_LOGIC_VECTOR ( 16 downto 0 );
attribute C_BUILD_REVISION : integer;
attribute C_BUILD_REVISION of inst : label is 0;
attribute C_BUS_ADDR_WIDTH : integer;
attribute C_BUS_ADDR_WIDTH of inst : label is 17;
attribute C_BUS_DATA_WIDTH : integer;
attribute C_BUS_DATA_WIDTH of inst : label is 16;
attribute C_CORE_INFO1 : string;
attribute C_CORE_INFO1 of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 : string;
attribute C_CORE_INFO2 of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER : integer;
attribute C_CORE_MAJOR_VER of inst : label is 2;
attribute C_CORE_MINOR_ALPHA_VER : integer;
attribute C_CORE_MINOR_ALPHA_VER of inst : label is 97;
attribute C_CORE_MINOR_VER : integer;
attribute C_CORE_MINOR_VER of inst : label is 0;
attribute C_CORE_TYPE : integer;
attribute C_CORE_TYPE of inst : label is 2;
attribute C_CSE_DRV_VER : integer;
attribute C_CSE_DRV_VER of inst : label is 1;
attribute C_EN_PROBE_IN_ACTIVITY : integer;
attribute C_EN_PROBE_IN_ACTIVITY of inst : label is 1;
attribute C_EN_SYNCHRONIZATION : integer;
attribute C_EN_SYNCHRONIZATION of inst : label is 1;
attribute C_MAJOR_VERSION : integer;
attribute C_MAJOR_VERSION of inst : label is 2013;
attribute C_MAX_NUM_PROBE : integer;
attribute C_MAX_NUM_PROBE of inst : label is 256;
attribute C_MAX_WIDTH_PER_PROBE : integer;
attribute C_MAX_WIDTH_PER_PROBE of inst : label is 256;
attribute C_MINOR_VERSION : integer;
attribute C_MINOR_VERSION of inst : label is 1;
attribute C_NEXT_SLAVE : integer;
attribute C_NEXT_SLAVE of inst : label is 0;
attribute C_NUM_PROBE_IN : integer;
attribute C_NUM_PROBE_IN of inst : label is 4;
attribute C_NUM_PROBE_OUT : integer;
attribute C_NUM_PROBE_OUT of inst : label is 0;
attribute C_PIPE_IFACE : integer;
attribute C_PIPE_IFACE of inst : label is 0;
attribute C_PROBE_IN0_WIDTH : integer;
attribute C_PROBE_IN0_WIDTH of inst : label is 1;
attribute C_PROBE_IN100_WIDTH : integer;
attribute C_PROBE_IN100_WIDTH of inst : label is 1;
attribute C_PROBE_IN101_WIDTH : integer;
attribute C_PROBE_IN101_WIDTH of inst : label is 1;
attribute C_PROBE_IN102_WIDTH : integer;
attribute C_PROBE_IN102_WIDTH of inst : label is 1;
attribute C_PROBE_IN103_WIDTH : integer;
attribute C_PROBE_IN103_WIDTH of inst : label is 1;
attribute C_PROBE_IN104_WIDTH : integer;
attribute C_PROBE_IN104_WIDTH of inst : label is 1;
attribute C_PROBE_IN105_WIDTH : integer;
attribute C_PROBE_IN105_WIDTH of inst : label is 1;
attribute C_PROBE_IN106_WIDTH : integer;
attribute C_PROBE_IN106_WIDTH of inst : label is 1;
attribute C_PROBE_IN107_WIDTH : integer;
attribute C_PROBE_IN107_WIDTH of inst : label is 1;
attribute C_PROBE_IN108_WIDTH : integer;
attribute C_PROBE_IN108_WIDTH of inst : label is 1;
attribute C_PROBE_IN109_WIDTH : integer;
attribute C_PROBE_IN109_WIDTH of inst : label is 1;
attribute C_PROBE_IN10_WIDTH : integer;
attribute C_PROBE_IN10_WIDTH of inst : label is 1;
attribute C_PROBE_IN110_WIDTH : integer;
attribute C_PROBE_IN110_WIDTH of inst : label is 1;
attribute C_PROBE_IN111_WIDTH : integer;
attribute C_PROBE_IN111_WIDTH of inst : label is 1;
attribute C_PROBE_IN112_WIDTH : integer;
attribute C_PROBE_IN112_WIDTH of inst : label is 1;
attribute C_PROBE_IN113_WIDTH : integer;
attribute C_PROBE_IN113_WIDTH of inst : label is 1;
attribute C_PROBE_IN114_WIDTH : integer;
attribute C_PROBE_IN114_WIDTH of inst : label is 1;
attribute C_PROBE_IN115_WIDTH : integer;
attribute C_PROBE_IN115_WIDTH of inst : label is 1;
attribute C_PROBE_IN116_WIDTH : integer;
attribute C_PROBE_IN116_WIDTH of inst : label is 1;
attribute C_PROBE_IN117_WIDTH : integer;
attribute C_PROBE_IN117_WIDTH of inst : label is 1;
attribute C_PROBE_IN118_WIDTH : integer;
attribute C_PROBE_IN118_WIDTH of inst : label is 1;
attribute C_PROBE_IN119_WIDTH : integer;
attribute C_PROBE_IN119_WIDTH of inst : label is 1;
attribute C_PROBE_IN11_WIDTH : integer;
attribute C_PROBE_IN11_WIDTH of inst : label is 1;
attribute C_PROBE_IN120_WIDTH : integer;
attribute C_PROBE_IN120_WIDTH of inst : label is 1;
attribute C_PROBE_IN121_WIDTH : integer;
attribute C_PROBE_IN121_WIDTH of inst : label is 1;
attribute C_PROBE_IN122_WIDTH : integer;
attribute C_PROBE_IN122_WIDTH of inst : label is 1;
attribute C_PROBE_IN123_WIDTH : integer;
attribute C_PROBE_IN123_WIDTH of inst : label is 1;
attribute C_PROBE_IN124_WIDTH : integer;
attribute C_PROBE_IN124_WIDTH of inst : label is 1;
attribute C_PROBE_IN125_WIDTH : integer;
attribute C_PROBE_IN125_WIDTH of inst : label is 1;
attribute C_PROBE_IN126_WIDTH : integer;
attribute C_PROBE_IN126_WIDTH of inst : label is 1;
attribute C_PROBE_IN127_WIDTH : integer;
attribute C_PROBE_IN127_WIDTH of inst : label is 1;
attribute C_PROBE_IN128_WIDTH : integer;
attribute C_PROBE_IN128_WIDTH of inst : label is 1;
attribute C_PROBE_IN129_WIDTH : integer;
attribute C_PROBE_IN129_WIDTH of inst : label is 1;
attribute C_PROBE_IN12_WIDTH : integer;
attribute C_PROBE_IN12_WIDTH of inst : label is 1;
attribute C_PROBE_IN130_WIDTH : integer;
attribute C_PROBE_IN130_WIDTH of inst : label is 1;
attribute C_PROBE_IN131_WIDTH : integer;
attribute C_PROBE_IN131_WIDTH of inst : label is 1;
attribute C_PROBE_IN132_WIDTH : integer;
attribute C_PROBE_IN132_WIDTH of inst : label is 1;
attribute C_PROBE_IN133_WIDTH : integer;
attribute C_PROBE_IN133_WIDTH of inst : label is 1;
attribute C_PROBE_IN134_WIDTH : integer;
attribute C_PROBE_IN134_WIDTH of inst : label is 1;
attribute C_PROBE_IN135_WIDTH : integer;
attribute C_PROBE_IN135_WIDTH of inst : label is 1;
attribute C_PROBE_IN136_WIDTH : integer;
attribute C_PROBE_IN136_WIDTH of inst : label is 1;
attribute C_PROBE_IN137_WIDTH : integer;
attribute C_PROBE_IN137_WIDTH of inst : label is 1;
attribute C_PROBE_IN138_WIDTH : integer;
attribute C_PROBE_IN138_WIDTH of inst : label is 1;
attribute C_PROBE_IN139_WIDTH : integer;
attribute C_PROBE_IN139_WIDTH of inst : label is 1;
attribute C_PROBE_IN13_WIDTH : integer;
attribute C_PROBE_IN13_WIDTH of inst : label is 1;
attribute C_PROBE_IN140_WIDTH : integer;
attribute C_PROBE_IN140_WIDTH of inst : label is 1;
attribute C_PROBE_IN141_WIDTH : integer;
attribute C_PROBE_IN141_WIDTH of inst : label is 1;
attribute C_PROBE_IN142_WIDTH : integer;
attribute C_PROBE_IN142_WIDTH of inst : label is 1;
attribute C_PROBE_IN143_WIDTH : integer;
attribute C_PROBE_IN143_WIDTH of inst : label is 1;
attribute C_PROBE_IN144_WIDTH : integer;
attribute C_PROBE_IN144_WIDTH of inst : label is 1;
attribute C_PROBE_IN145_WIDTH : integer;
attribute C_PROBE_IN145_WIDTH of inst : label is 1;
attribute C_PROBE_IN146_WIDTH : integer;
attribute C_PROBE_IN146_WIDTH of inst : label is 1;
attribute C_PROBE_IN147_WIDTH : integer;
attribute C_PROBE_IN147_WIDTH of inst : label is 1;
attribute C_PROBE_IN148_WIDTH : integer;
attribute C_PROBE_IN148_WIDTH of inst : label is 1;
attribute C_PROBE_IN149_WIDTH : integer;
attribute C_PROBE_IN149_WIDTH of inst : label is 1;
attribute C_PROBE_IN14_WIDTH : integer;
attribute C_PROBE_IN14_WIDTH of inst : label is 1;
attribute C_PROBE_IN150_WIDTH : integer;
attribute C_PROBE_IN150_WIDTH of inst : label is 1;
attribute C_PROBE_IN151_WIDTH : integer;
attribute C_PROBE_IN151_WIDTH of inst : label is 1;
attribute C_PROBE_IN152_WIDTH : integer;
attribute C_PROBE_IN152_WIDTH of inst : label is 1;
attribute C_PROBE_IN153_WIDTH : integer;
attribute C_PROBE_IN153_WIDTH of inst : label is 1;
attribute C_PROBE_IN154_WIDTH : integer;
attribute C_PROBE_IN154_WIDTH of inst : label is 1;
attribute C_PROBE_IN155_WIDTH : integer;
attribute C_PROBE_IN155_WIDTH of inst : label is 1;
attribute C_PROBE_IN156_WIDTH : integer;
attribute C_PROBE_IN156_WIDTH of inst : label is 1;
attribute C_PROBE_IN157_WIDTH : integer;
attribute C_PROBE_IN157_WIDTH of inst : label is 1;
attribute C_PROBE_IN158_WIDTH : integer;
attribute C_PROBE_IN158_WIDTH of inst : label is 1;
attribute C_PROBE_IN159_WIDTH : integer;
attribute C_PROBE_IN159_WIDTH of inst : label is 1;
attribute C_PROBE_IN15_WIDTH : integer;
attribute C_PROBE_IN15_WIDTH of inst : label is 1;
attribute C_PROBE_IN160_WIDTH : integer;
attribute C_PROBE_IN160_WIDTH of inst : label is 1;
attribute C_PROBE_IN161_WIDTH : integer;
attribute C_PROBE_IN161_WIDTH of inst : label is 1;
attribute C_PROBE_IN162_WIDTH : integer;
attribute C_PROBE_IN162_WIDTH of inst : label is 1;
attribute C_PROBE_IN163_WIDTH : integer;
attribute C_PROBE_IN163_WIDTH of inst : label is 1;
attribute C_PROBE_IN164_WIDTH : integer;
attribute C_PROBE_IN164_WIDTH of inst : label is 1;
attribute C_PROBE_IN165_WIDTH : integer;
attribute C_PROBE_IN165_WIDTH of inst : label is 1;
attribute C_PROBE_IN166_WIDTH : integer;
attribute C_PROBE_IN166_WIDTH of inst : label is 1;
attribute C_PROBE_IN167_WIDTH : integer;
attribute C_PROBE_IN167_WIDTH of inst : label is 1;
attribute C_PROBE_IN168_WIDTH : integer;
attribute C_PROBE_IN168_WIDTH of inst : label is 1;
attribute C_PROBE_IN169_WIDTH : integer;
attribute C_PROBE_IN169_WIDTH of inst : label is 1;
attribute C_PROBE_IN16_WIDTH : integer;
attribute C_PROBE_IN16_WIDTH of inst : label is 1;
attribute C_PROBE_IN170_WIDTH : integer;
attribute C_PROBE_IN170_WIDTH of inst : label is 1;
attribute C_PROBE_IN171_WIDTH : integer;
attribute C_PROBE_IN171_WIDTH of inst : label is 1;
attribute C_PROBE_IN172_WIDTH : integer;
attribute C_PROBE_IN172_WIDTH of inst : label is 1;
attribute C_PROBE_IN173_WIDTH : integer;
attribute C_PROBE_IN173_WIDTH of inst : label is 1;
attribute C_PROBE_IN174_WIDTH : integer;
attribute C_PROBE_IN174_WIDTH of inst : label is 1;
attribute C_PROBE_IN175_WIDTH : integer;
attribute C_PROBE_IN175_WIDTH of inst : label is 1;
attribute C_PROBE_IN176_WIDTH : integer;
attribute C_PROBE_IN176_WIDTH of inst : label is 1;
attribute C_PROBE_IN177_WIDTH : integer;
attribute C_PROBE_IN177_WIDTH of inst : label is 1;
attribute C_PROBE_IN178_WIDTH : integer;
attribute C_PROBE_IN178_WIDTH of inst : label is 1;
attribute C_PROBE_IN179_WIDTH : integer;
attribute C_PROBE_IN179_WIDTH of inst : label is 1;
attribute C_PROBE_IN17_WIDTH : integer;
attribute C_PROBE_IN17_WIDTH of inst : label is 1;
attribute C_PROBE_IN180_WIDTH : integer;
attribute C_PROBE_IN180_WIDTH of inst : label is 1;
attribute C_PROBE_IN181_WIDTH : integer;
attribute C_PROBE_IN181_WIDTH of inst : label is 1;
attribute C_PROBE_IN182_WIDTH : integer;
attribute C_PROBE_IN182_WIDTH of inst : label is 1;
attribute C_PROBE_IN183_WIDTH : integer;
attribute C_PROBE_IN183_WIDTH of inst : label is 1;
attribute C_PROBE_IN184_WIDTH : integer;
attribute C_PROBE_IN184_WIDTH of inst : label is 1;
attribute C_PROBE_IN185_WIDTH : integer;
attribute C_PROBE_IN185_WIDTH of inst : label is 1;
attribute C_PROBE_IN186_WIDTH : integer;
attribute C_PROBE_IN186_WIDTH of inst : label is 1;
attribute C_PROBE_IN187_WIDTH : integer;
attribute C_PROBE_IN187_WIDTH of inst : label is 1;
attribute C_PROBE_IN188_WIDTH : integer;
attribute C_PROBE_IN188_WIDTH of inst : label is 1;
attribute C_PROBE_IN189_WIDTH : integer;
attribute C_PROBE_IN189_WIDTH of inst : label is 1;
attribute C_PROBE_IN18_WIDTH : integer;
attribute C_PROBE_IN18_WIDTH of inst : label is 1;
attribute C_PROBE_IN190_WIDTH : integer;
attribute C_PROBE_IN190_WIDTH of inst : label is 1;
attribute C_PROBE_IN191_WIDTH : integer;
attribute C_PROBE_IN191_WIDTH of inst : label is 1;
attribute C_PROBE_IN192_WIDTH : integer;
attribute C_PROBE_IN192_WIDTH of inst : label is 1;
attribute C_PROBE_IN193_WIDTH : integer;
attribute C_PROBE_IN193_WIDTH of inst : label is 1;
attribute C_PROBE_IN194_WIDTH : integer;
attribute C_PROBE_IN194_WIDTH of inst : label is 1;
attribute C_PROBE_IN195_WIDTH : integer;
attribute C_PROBE_IN195_WIDTH of inst : label is 1;
attribute C_PROBE_IN196_WIDTH : integer;
attribute C_PROBE_IN196_WIDTH of inst : label is 1;
attribute C_PROBE_IN197_WIDTH : integer;
attribute C_PROBE_IN197_WIDTH of inst : label is 1;
attribute C_PROBE_IN198_WIDTH : integer;
attribute C_PROBE_IN198_WIDTH of inst : label is 1;
attribute C_PROBE_IN199_WIDTH : integer;
attribute C_PROBE_IN199_WIDTH of inst : label is 1;
attribute C_PROBE_IN19_WIDTH : integer;
attribute C_PROBE_IN19_WIDTH of inst : label is 1;
attribute C_PROBE_IN1_WIDTH : integer;
attribute C_PROBE_IN1_WIDTH of inst : label is 1;
attribute C_PROBE_IN200_WIDTH : integer;
attribute C_PROBE_IN200_WIDTH of inst : label is 1;
attribute C_PROBE_IN201_WIDTH : integer;
attribute C_PROBE_IN201_WIDTH of inst : label is 1;
attribute C_PROBE_IN202_WIDTH : integer;
attribute C_PROBE_IN202_WIDTH of inst : label is 1;
attribute C_PROBE_IN203_WIDTH : integer;
attribute C_PROBE_IN203_WIDTH of inst : label is 1;
attribute C_PROBE_IN204_WIDTH : integer;
attribute C_PROBE_IN204_WIDTH of inst : label is 1;
attribute C_PROBE_IN205_WIDTH : integer;
attribute C_PROBE_IN205_WIDTH of inst : label is 1;
attribute C_PROBE_IN206_WIDTH : integer;
attribute C_PROBE_IN206_WIDTH of inst : label is 1;
attribute C_PROBE_IN207_WIDTH : integer;
attribute C_PROBE_IN207_WIDTH of inst : label is 1;
attribute C_PROBE_IN208_WIDTH : integer;
attribute C_PROBE_IN208_WIDTH of inst : label is 1;
attribute C_PROBE_IN209_WIDTH : integer;
attribute C_PROBE_IN209_WIDTH of inst : label is 1;
attribute C_PROBE_IN20_WIDTH : integer;
attribute C_PROBE_IN20_WIDTH of inst : label is 1;
attribute C_PROBE_IN210_WIDTH : integer;
attribute C_PROBE_IN210_WIDTH of inst : label is 1;
attribute C_PROBE_IN211_WIDTH : integer;
attribute C_PROBE_IN211_WIDTH of inst : label is 1;
attribute C_PROBE_IN212_WIDTH : integer;
attribute C_PROBE_IN212_WIDTH of inst : label is 1;
attribute C_PROBE_IN213_WIDTH : integer;
attribute C_PROBE_IN213_WIDTH of inst : label is 1;
attribute C_PROBE_IN214_WIDTH : integer;
attribute C_PROBE_IN214_WIDTH of inst : label is 1;
attribute C_PROBE_IN215_WIDTH : integer;
attribute C_PROBE_IN215_WIDTH of inst : label is 1;
attribute C_PROBE_IN216_WIDTH : integer;
attribute C_PROBE_IN216_WIDTH of inst : label is 1;
attribute C_PROBE_IN217_WIDTH : integer;
attribute C_PROBE_IN217_WIDTH of inst : label is 1;
attribute C_PROBE_IN218_WIDTH : integer;
attribute C_PROBE_IN218_WIDTH of inst : label is 1;
attribute C_PROBE_IN219_WIDTH : integer;
attribute C_PROBE_IN219_WIDTH of inst : label is 1;
attribute C_PROBE_IN21_WIDTH : integer;
attribute C_PROBE_IN21_WIDTH of inst : label is 1;
attribute C_PROBE_IN220_WIDTH : integer;
attribute C_PROBE_IN220_WIDTH of inst : label is 1;
attribute C_PROBE_IN221_WIDTH : integer;
attribute C_PROBE_IN221_WIDTH of inst : label is 1;
attribute C_PROBE_IN222_WIDTH : integer;
attribute C_PROBE_IN222_WIDTH of inst : label is 1;
attribute C_PROBE_IN223_WIDTH : integer;
attribute C_PROBE_IN223_WIDTH of inst : label is 1;
attribute C_PROBE_IN224_WIDTH : integer;
attribute C_PROBE_IN224_WIDTH of inst : label is 1;
attribute C_PROBE_IN225_WIDTH : integer;
attribute C_PROBE_IN225_WIDTH of inst : label is 1;
attribute C_PROBE_IN226_WIDTH : integer;
attribute C_PROBE_IN226_WIDTH of inst : label is 1;
attribute C_PROBE_IN227_WIDTH : integer;
attribute C_PROBE_IN227_WIDTH of inst : label is 1;
attribute C_PROBE_IN228_WIDTH : integer;
attribute C_PROBE_IN228_WIDTH of inst : label is 1;
attribute C_PROBE_IN229_WIDTH : integer;
attribute C_PROBE_IN229_WIDTH of inst : label is 1;
attribute C_PROBE_IN22_WIDTH : integer;
attribute C_PROBE_IN22_WIDTH of inst : label is 1;
attribute C_PROBE_IN230_WIDTH : integer;
attribute C_PROBE_IN230_WIDTH of inst : label is 1;
attribute C_PROBE_IN231_WIDTH : integer;
attribute C_PROBE_IN231_WIDTH of inst : label is 1;
attribute C_PROBE_IN232_WIDTH : integer;
attribute C_PROBE_IN232_WIDTH of inst : label is 1;
attribute C_PROBE_IN233_WIDTH : integer;
attribute C_PROBE_IN233_WIDTH of inst : label is 1;
attribute C_PROBE_IN234_WIDTH : integer;
attribute C_PROBE_IN234_WIDTH of inst : label is 1;
attribute C_PROBE_IN235_WIDTH : integer;
attribute C_PROBE_IN235_WIDTH of inst : label is 1;
attribute C_PROBE_IN236_WIDTH : integer;
attribute C_PROBE_IN236_WIDTH of inst : label is 1;
attribute C_PROBE_IN237_WIDTH : integer;
attribute C_PROBE_IN237_WIDTH of inst : label is 1;
attribute C_PROBE_IN238_WIDTH : integer;
attribute C_PROBE_IN238_WIDTH of inst : label is 1;
attribute C_PROBE_IN239_WIDTH : integer;
attribute C_PROBE_IN239_WIDTH of inst : label is 1;
attribute C_PROBE_IN23_WIDTH : integer;
attribute C_PROBE_IN23_WIDTH of inst : label is 1;
attribute C_PROBE_IN240_WIDTH : integer;
attribute C_PROBE_IN240_WIDTH of inst : label is 1;
attribute C_PROBE_IN241_WIDTH : integer;
attribute C_PROBE_IN241_WIDTH of inst : label is 1;
attribute C_PROBE_IN242_WIDTH : integer;
attribute C_PROBE_IN242_WIDTH of inst : label is 1;
attribute C_PROBE_IN243_WIDTH : integer;
attribute C_PROBE_IN243_WIDTH of inst : label is 1;
attribute C_PROBE_IN244_WIDTH : integer;
attribute C_PROBE_IN244_WIDTH of inst : label is 1;
attribute C_PROBE_IN245_WIDTH : integer;
attribute C_PROBE_IN245_WIDTH of inst : label is 1;
attribute C_PROBE_IN246_WIDTH : integer;
attribute C_PROBE_IN246_WIDTH of inst : label is 1;
attribute C_PROBE_IN247_WIDTH : integer;
attribute C_PROBE_IN247_WIDTH of inst : label is 1;
attribute C_PROBE_IN248_WIDTH : integer;
attribute C_PROBE_IN248_WIDTH of inst : label is 1;
attribute C_PROBE_IN249_WIDTH : integer;
attribute C_PROBE_IN249_WIDTH of inst : label is 1;
attribute C_PROBE_IN24_WIDTH : integer;
attribute C_PROBE_IN24_WIDTH of inst : label is 1;
attribute C_PROBE_IN250_WIDTH : integer;
attribute C_PROBE_IN250_WIDTH of inst : label is 1;
attribute C_PROBE_IN251_WIDTH : integer;
attribute C_PROBE_IN251_WIDTH of inst : label is 1;
attribute C_PROBE_IN252_WIDTH : integer;
attribute C_PROBE_IN252_WIDTH of inst : label is 1;
attribute C_PROBE_IN253_WIDTH : integer;
attribute C_PROBE_IN253_WIDTH of inst : label is 1;
attribute C_PROBE_IN254_WIDTH : integer;
attribute C_PROBE_IN254_WIDTH of inst : label is 1;
attribute C_PROBE_IN255_WIDTH : integer;
attribute C_PROBE_IN255_WIDTH of inst : label is 1;
attribute C_PROBE_IN25_WIDTH : integer;
attribute C_PROBE_IN25_WIDTH of inst : label is 1;
attribute C_PROBE_IN26_WIDTH : integer;
attribute C_PROBE_IN26_WIDTH of inst : label is 1;
attribute C_PROBE_IN27_WIDTH : integer;
attribute C_PROBE_IN27_WIDTH of inst : label is 1;
attribute C_PROBE_IN28_WIDTH : integer;
attribute C_PROBE_IN28_WIDTH of inst : label is 1;
attribute C_PROBE_IN29_WIDTH : integer;
attribute C_PROBE_IN29_WIDTH of inst : label is 1;
attribute C_PROBE_IN2_WIDTH : integer;
attribute C_PROBE_IN2_WIDTH of inst : label is 1;
attribute C_PROBE_IN30_WIDTH : integer;
attribute C_PROBE_IN30_WIDTH of inst : label is 1;
attribute C_PROBE_IN31_WIDTH : integer;
attribute C_PROBE_IN31_WIDTH of inst : label is 1;
attribute C_PROBE_IN32_WIDTH : integer;
attribute C_PROBE_IN32_WIDTH of inst : label is 1;
attribute C_PROBE_IN33_WIDTH : integer;
attribute C_PROBE_IN33_WIDTH of inst : label is 1;
attribute C_PROBE_IN34_WIDTH : integer;
attribute C_PROBE_IN34_WIDTH of inst : label is 1;
attribute C_PROBE_IN35_WIDTH : integer;
attribute C_PROBE_IN35_WIDTH of inst : label is 1;
attribute C_PROBE_IN36_WIDTH : integer;
attribute C_PROBE_IN36_WIDTH of inst : label is 1;
attribute C_PROBE_IN37_WIDTH : integer;
attribute C_PROBE_IN37_WIDTH of inst : label is 1;
attribute C_PROBE_IN38_WIDTH : integer;
attribute C_PROBE_IN38_WIDTH of inst : label is 1;
attribute C_PROBE_IN39_WIDTH : integer;
attribute C_PROBE_IN39_WIDTH of inst : label is 1;
attribute C_PROBE_IN3_WIDTH : integer;
attribute C_PROBE_IN3_WIDTH of inst : label is 1;
attribute C_PROBE_IN40_WIDTH : integer;
attribute C_PROBE_IN40_WIDTH of inst : label is 1;
attribute C_PROBE_IN41_WIDTH : integer;
attribute C_PROBE_IN41_WIDTH of inst : label is 1;
attribute C_PROBE_IN42_WIDTH : integer;
attribute C_PROBE_IN42_WIDTH of inst : label is 1;
attribute C_PROBE_IN43_WIDTH : integer;
attribute C_PROBE_IN43_WIDTH of inst : label is 1;
attribute C_PROBE_IN44_WIDTH : integer;
attribute C_PROBE_IN44_WIDTH of inst : label is 1;
attribute C_PROBE_IN45_WIDTH : integer;
attribute C_PROBE_IN45_WIDTH of inst : label is 1;
attribute C_PROBE_IN46_WIDTH : integer;
attribute C_PROBE_IN46_WIDTH of inst : label is 1;
attribute C_PROBE_IN47_WIDTH : integer;
attribute C_PROBE_IN47_WIDTH of inst : label is 1;
attribute C_PROBE_IN48_WIDTH : integer;
attribute C_PROBE_IN48_WIDTH of inst : label is 1;
attribute C_PROBE_IN49_WIDTH : integer;
attribute C_PROBE_IN49_WIDTH of inst : label is 1;
attribute C_PROBE_IN4_WIDTH : integer;
attribute C_PROBE_IN4_WIDTH of inst : label is 1;
attribute C_PROBE_IN50_WIDTH : integer;
attribute C_PROBE_IN50_WIDTH of inst : label is 1;
attribute C_PROBE_IN51_WIDTH : integer;
attribute C_PROBE_IN51_WIDTH of inst : label is 1;
attribute C_PROBE_IN52_WIDTH : integer;
attribute C_PROBE_IN52_WIDTH of inst : label is 1;
attribute C_PROBE_IN53_WIDTH : integer;
attribute C_PROBE_IN53_WIDTH of inst : label is 1;
attribute C_PROBE_IN54_WIDTH : integer;
attribute C_PROBE_IN54_WIDTH of inst : label is 1;
attribute C_PROBE_IN55_WIDTH : integer;
attribute C_PROBE_IN55_WIDTH of inst : label is 1;
attribute C_PROBE_IN56_WIDTH : integer;
attribute C_PROBE_IN56_WIDTH of inst : label is 1;
attribute C_PROBE_IN57_WIDTH : integer;
attribute C_PROBE_IN57_WIDTH of inst : label is 1;
attribute C_PROBE_IN58_WIDTH : integer;
attribute C_PROBE_IN58_WIDTH of inst : label is 1;
attribute C_PROBE_IN59_WIDTH : integer;
attribute C_PROBE_IN59_WIDTH of inst : label is 1;
attribute C_PROBE_IN5_WIDTH : integer;
attribute C_PROBE_IN5_WIDTH of inst : label is 1;
attribute C_PROBE_IN60_WIDTH : integer;
attribute C_PROBE_IN60_WIDTH of inst : label is 1;
attribute C_PROBE_IN61_WIDTH : integer;
attribute C_PROBE_IN61_WIDTH of inst : label is 1;
attribute C_PROBE_IN62_WIDTH : integer;
attribute C_PROBE_IN62_WIDTH of inst : label is 1;
attribute C_PROBE_IN63_WIDTH : integer;
attribute C_PROBE_IN63_WIDTH of inst : label is 1;
attribute C_PROBE_IN64_WIDTH : integer;
attribute C_PROBE_IN64_WIDTH of inst : label is 1;
attribute C_PROBE_IN65_WIDTH : integer;
attribute C_PROBE_IN65_WIDTH of inst : label is 1;
attribute C_PROBE_IN66_WIDTH : integer;
attribute C_PROBE_IN66_WIDTH of inst : label is 1;
attribute C_PROBE_IN67_WIDTH : integer;
attribute C_PROBE_IN67_WIDTH of inst : label is 1;
attribute C_PROBE_IN68_WIDTH : integer;
attribute C_PROBE_IN68_WIDTH of inst : label is 1;
attribute C_PROBE_IN69_WIDTH : integer;
attribute C_PROBE_IN69_WIDTH of inst : label is 1;
attribute C_PROBE_IN6_WIDTH : integer;
attribute C_PROBE_IN6_WIDTH of inst : label is 1;
attribute C_PROBE_IN70_WIDTH : integer;
attribute C_PROBE_IN70_WIDTH of inst : label is 1;
attribute C_PROBE_IN71_WIDTH : integer;
attribute C_PROBE_IN71_WIDTH of inst : label is 1;
attribute C_PROBE_IN72_WIDTH : integer;
attribute C_PROBE_IN72_WIDTH of inst : label is 1;
attribute C_PROBE_IN73_WIDTH : integer;
attribute C_PROBE_IN73_WIDTH of inst : label is 1;
attribute C_PROBE_IN74_WIDTH : integer;
attribute C_PROBE_IN74_WIDTH of inst : label is 1;
attribute C_PROBE_IN75_WIDTH : integer;
attribute C_PROBE_IN75_WIDTH of inst : label is 1;
attribute C_PROBE_IN76_WIDTH : integer;
attribute C_PROBE_IN76_WIDTH of inst : label is 1;
attribute C_PROBE_IN77_WIDTH : integer;
attribute C_PROBE_IN77_WIDTH of inst : label is 1;
attribute C_PROBE_IN78_WIDTH : integer;
attribute C_PROBE_IN78_WIDTH of inst : label is 1;
attribute C_PROBE_IN79_WIDTH : integer;
attribute C_PROBE_IN79_WIDTH of inst : label is 1;
attribute C_PROBE_IN7_WIDTH : integer;
attribute C_PROBE_IN7_WIDTH of inst : label is 1;
attribute C_PROBE_IN80_WIDTH : integer;
attribute C_PROBE_IN80_WIDTH of inst : label is 1;
attribute C_PROBE_IN81_WIDTH : integer;
attribute C_PROBE_IN81_WIDTH of inst : label is 1;
attribute C_PROBE_IN82_WIDTH : integer;
attribute C_PROBE_IN82_WIDTH of inst : label is 1;
attribute C_PROBE_IN83_WIDTH : integer;
attribute C_PROBE_IN83_WIDTH of inst : label is 1;
attribute C_PROBE_IN84_WIDTH : integer;
attribute C_PROBE_IN84_WIDTH of inst : label is 1;
attribute C_PROBE_IN85_WIDTH : integer;
attribute C_PROBE_IN85_WIDTH of inst : label is 1;
attribute C_PROBE_IN86_WIDTH : integer;
attribute C_PROBE_IN86_WIDTH of inst : label is 1;
attribute C_PROBE_IN87_WIDTH : integer;
attribute C_PROBE_IN87_WIDTH of inst : label is 1;
attribute C_PROBE_IN88_WIDTH : integer;
attribute C_PROBE_IN88_WIDTH of inst : label is 1;
attribute C_PROBE_IN89_WIDTH : integer;
attribute C_PROBE_IN89_WIDTH of inst : label is 1;
attribute C_PROBE_IN8_WIDTH : integer;
attribute C_PROBE_IN8_WIDTH of inst : label is 1;
attribute C_PROBE_IN90_WIDTH : integer;
attribute C_PROBE_IN90_WIDTH of inst : label is 1;
attribute C_PROBE_IN91_WIDTH : integer;
attribute C_PROBE_IN91_WIDTH of inst : label is 1;
attribute C_PROBE_IN92_WIDTH : integer;
attribute C_PROBE_IN92_WIDTH of inst : label is 1;
attribute C_PROBE_IN93_WIDTH : integer;
attribute C_PROBE_IN93_WIDTH of inst : label is 1;
attribute C_PROBE_IN94_WIDTH : integer;
attribute C_PROBE_IN94_WIDTH of inst : label is 1;
attribute C_PROBE_IN95_WIDTH : integer;
attribute C_PROBE_IN95_WIDTH of inst : label is 1;
attribute C_PROBE_IN96_WIDTH : integer;
attribute C_PROBE_IN96_WIDTH of inst : label is 1;
attribute C_PROBE_IN97_WIDTH : integer;
attribute C_PROBE_IN97_WIDTH of inst : label is 1;
attribute C_PROBE_IN98_WIDTH : integer;
attribute C_PROBE_IN98_WIDTH of inst : label is 1;
attribute C_PROBE_IN99_WIDTH : integer;
attribute C_PROBE_IN99_WIDTH of inst : label is 1;
attribute C_PROBE_IN9_WIDTH : integer;
attribute C_PROBE_IN9_WIDTH of inst : label is 1;
attribute C_PROBE_OUT0_INIT_VAL : string;
attribute C_PROBE_OUT0_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT0_WIDTH : integer;
attribute C_PROBE_OUT0_WIDTH of inst : label is 1;
attribute C_PROBE_OUT100_INIT_VAL : string;
attribute C_PROBE_OUT100_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT100_WIDTH : integer;
attribute C_PROBE_OUT100_WIDTH of inst : label is 1;
attribute C_PROBE_OUT101_INIT_VAL : string;
attribute C_PROBE_OUT101_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT101_WIDTH : integer;
attribute C_PROBE_OUT101_WIDTH of inst : label is 1;
attribute C_PROBE_OUT102_INIT_VAL : string;
attribute C_PROBE_OUT102_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT102_WIDTH : integer;
attribute C_PROBE_OUT102_WIDTH of inst : label is 1;
attribute C_PROBE_OUT103_INIT_VAL : string;
attribute C_PROBE_OUT103_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT103_WIDTH : integer;
attribute C_PROBE_OUT103_WIDTH of inst : label is 1;
attribute C_PROBE_OUT104_INIT_VAL : string;
attribute C_PROBE_OUT104_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT104_WIDTH : integer;
attribute C_PROBE_OUT104_WIDTH of inst : label is 1;
attribute C_PROBE_OUT105_INIT_VAL : string;
attribute C_PROBE_OUT105_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT105_WIDTH : integer;
attribute C_PROBE_OUT105_WIDTH of inst : label is 1;
attribute C_PROBE_OUT106_INIT_VAL : string;
attribute C_PROBE_OUT106_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT106_WIDTH : integer;
attribute C_PROBE_OUT106_WIDTH of inst : label is 1;
attribute C_PROBE_OUT107_INIT_VAL : string;
attribute C_PROBE_OUT107_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT107_WIDTH : integer;
attribute C_PROBE_OUT107_WIDTH of inst : label is 1;
attribute C_PROBE_OUT108_INIT_VAL : string;
attribute C_PROBE_OUT108_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT108_WIDTH : integer;
attribute C_PROBE_OUT108_WIDTH of inst : label is 1;
attribute C_PROBE_OUT109_INIT_VAL : string;
attribute C_PROBE_OUT109_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT109_WIDTH : integer;
attribute C_PROBE_OUT109_WIDTH of inst : label is 1;
attribute C_PROBE_OUT10_INIT_VAL : string;
attribute C_PROBE_OUT10_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT10_WIDTH : integer;
attribute C_PROBE_OUT10_WIDTH of inst : label is 1;
attribute C_PROBE_OUT110_INIT_VAL : string;
attribute C_PROBE_OUT110_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT110_WIDTH : integer;
attribute C_PROBE_OUT110_WIDTH of inst : label is 1;
attribute C_PROBE_OUT111_INIT_VAL : string;
attribute C_PROBE_OUT111_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT111_WIDTH : integer;
attribute C_PROBE_OUT111_WIDTH of inst : label is 1;
attribute C_PROBE_OUT112_INIT_VAL : string;
attribute C_PROBE_OUT112_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT112_WIDTH : integer;
attribute C_PROBE_OUT112_WIDTH of inst : label is 1;
attribute C_PROBE_OUT113_INIT_VAL : string;
attribute C_PROBE_OUT113_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT113_WIDTH : integer;
attribute C_PROBE_OUT113_WIDTH of inst : label is 1;
attribute C_PROBE_OUT114_INIT_VAL : string;
attribute C_PROBE_OUT114_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT114_WIDTH : integer;
attribute C_PROBE_OUT114_WIDTH of inst : label is 1;
attribute C_PROBE_OUT115_INIT_VAL : string;
attribute C_PROBE_OUT115_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT115_WIDTH : integer;
attribute C_PROBE_OUT115_WIDTH of inst : label is 1;
attribute C_PROBE_OUT116_INIT_VAL : string;
attribute C_PROBE_OUT116_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT116_WIDTH : integer;
attribute C_PROBE_OUT116_WIDTH of inst : label is 1;
attribute C_PROBE_OUT117_INIT_VAL : string;
attribute C_PROBE_OUT117_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT117_WIDTH : integer;
attribute C_PROBE_OUT117_WIDTH of inst : label is 1;
attribute C_PROBE_OUT118_INIT_VAL : string;
attribute C_PROBE_OUT118_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT118_WIDTH : integer;
attribute C_PROBE_OUT118_WIDTH of inst : label is 1;
attribute C_PROBE_OUT119_INIT_VAL : string;
attribute C_PROBE_OUT119_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT119_WIDTH : integer;
attribute C_PROBE_OUT119_WIDTH of inst : label is 1;
attribute C_PROBE_OUT11_INIT_VAL : string;
attribute C_PROBE_OUT11_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT11_WIDTH : integer;
attribute C_PROBE_OUT11_WIDTH of inst : label is 1;
attribute C_PROBE_OUT120_INIT_VAL : string;
attribute C_PROBE_OUT120_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT120_WIDTH : integer;
attribute C_PROBE_OUT120_WIDTH of inst : label is 1;
attribute C_PROBE_OUT121_INIT_VAL : string;
attribute C_PROBE_OUT121_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT121_WIDTH : integer;
attribute C_PROBE_OUT121_WIDTH of inst : label is 1;
attribute C_PROBE_OUT122_INIT_VAL : string;
attribute C_PROBE_OUT122_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT122_WIDTH : integer;
attribute C_PROBE_OUT122_WIDTH of inst : label is 1;
attribute C_PROBE_OUT123_INIT_VAL : string;
attribute C_PROBE_OUT123_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT123_WIDTH : integer;
attribute C_PROBE_OUT123_WIDTH of inst : label is 1;
attribute C_PROBE_OUT124_INIT_VAL : string;
attribute C_PROBE_OUT124_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT124_WIDTH : integer;
attribute C_PROBE_OUT124_WIDTH of inst : label is 1;
attribute C_PROBE_OUT125_INIT_VAL : string;
attribute C_PROBE_OUT125_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT125_WIDTH : integer;
attribute C_PROBE_OUT125_WIDTH of inst : label is 1;
attribute C_PROBE_OUT126_INIT_VAL : string;
attribute C_PROBE_OUT126_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT126_WIDTH : integer;
attribute C_PROBE_OUT126_WIDTH of inst : label is 1;
attribute C_PROBE_OUT127_INIT_VAL : string;
attribute C_PROBE_OUT127_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT127_WIDTH : integer;
attribute C_PROBE_OUT127_WIDTH of inst : label is 1;
attribute C_PROBE_OUT128_INIT_VAL : string;
attribute C_PROBE_OUT128_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT128_WIDTH : integer;
attribute C_PROBE_OUT128_WIDTH of inst : label is 1;
attribute C_PROBE_OUT129_INIT_VAL : string;
attribute C_PROBE_OUT129_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT129_WIDTH : integer;
attribute C_PROBE_OUT129_WIDTH of inst : label is 1;
attribute C_PROBE_OUT12_INIT_VAL : string;
attribute C_PROBE_OUT12_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT12_WIDTH : integer;
attribute C_PROBE_OUT12_WIDTH of inst : label is 1;
attribute C_PROBE_OUT130_INIT_VAL : string;
attribute C_PROBE_OUT130_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT130_WIDTH : integer;
attribute C_PROBE_OUT130_WIDTH of inst : label is 1;
attribute C_PROBE_OUT131_INIT_VAL : string;
attribute C_PROBE_OUT131_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT131_WIDTH : integer;
attribute C_PROBE_OUT131_WIDTH of inst : label is 1;
attribute C_PROBE_OUT132_INIT_VAL : string;
attribute C_PROBE_OUT132_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT132_WIDTH : integer;
attribute C_PROBE_OUT132_WIDTH of inst : label is 1;
attribute C_PROBE_OUT133_INIT_VAL : string;
attribute C_PROBE_OUT133_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT133_WIDTH : integer;
attribute C_PROBE_OUT133_WIDTH of inst : label is 1;
attribute C_PROBE_OUT134_INIT_VAL : string;
attribute C_PROBE_OUT134_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT134_WIDTH : integer;
attribute C_PROBE_OUT134_WIDTH of inst : label is 1;
attribute C_PROBE_OUT135_INIT_VAL : string;
attribute C_PROBE_OUT135_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT135_WIDTH : integer;
attribute C_PROBE_OUT135_WIDTH of inst : label is 1;
attribute C_PROBE_OUT136_INIT_VAL : string;
attribute C_PROBE_OUT136_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT136_WIDTH : integer;
attribute C_PROBE_OUT136_WIDTH of inst : label is 1;
attribute C_PROBE_OUT137_INIT_VAL : string;
attribute C_PROBE_OUT137_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT137_WIDTH : integer;
attribute C_PROBE_OUT137_WIDTH of inst : label is 1;
attribute C_PROBE_OUT138_INIT_VAL : string;
attribute C_PROBE_OUT138_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT138_WIDTH : integer;
attribute C_PROBE_OUT138_WIDTH of inst : label is 1;
attribute C_PROBE_OUT139_INIT_VAL : string;
attribute C_PROBE_OUT139_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT139_WIDTH : integer;
attribute C_PROBE_OUT139_WIDTH of inst : label is 1;
attribute C_PROBE_OUT13_INIT_VAL : string;
attribute C_PROBE_OUT13_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT13_WIDTH : integer;
attribute C_PROBE_OUT13_WIDTH of inst : label is 1;
attribute C_PROBE_OUT140_INIT_VAL : string;
attribute C_PROBE_OUT140_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT140_WIDTH : integer;
attribute C_PROBE_OUT140_WIDTH of inst : label is 1;
attribute C_PROBE_OUT141_INIT_VAL : string;
attribute C_PROBE_OUT141_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT141_WIDTH : integer;
attribute C_PROBE_OUT141_WIDTH of inst : label is 1;
attribute C_PROBE_OUT142_INIT_VAL : string;
attribute C_PROBE_OUT142_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT142_WIDTH : integer;
attribute C_PROBE_OUT142_WIDTH of inst : label is 1;
attribute C_PROBE_OUT143_INIT_VAL : string;
attribute C_PROBE_OUT143_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT143_WIDTH : integer;
attribute C_PROBE_OUT143_WIDTH of inst : label is 1;
attribute C_PROBE_OUT144_INIT_VAL : string;
attribute C_PROBE_OUT144_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT144_WIDTH : integer;
attribute C_PROBE_OUT144_WIDTH of inst : label is 1;
attribute C_PROBE_OUT145_INIT_VAL : string;
attribute C_PROBE_OUT145_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT145_WIDTH : integer;
attribute C_PROBE_OUT145_WIDTH of inst : label is 1;
attribute C_PROBE_OUT146_INIT_VAL : string;
attribute C_PROBE_OUT146_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT146_WIDTH : integer;
attribute C_PROBE_OUT146_WIDTH of inst : label is 1;
attribute C_PROBE_OUT147_INIT_VAL : string;
attribute C_PROBE_OUT147_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT147_WIDTH : integer;
attribute C_PROBE_OUT147_WIDTH of inst : label is 1;
attribute C_PROBE_OUT148_INIT_VAL : string;
attribute C_PROBE_OUT148_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT148_WIDTH : integer;
attribute C_PROBE_OUT148_WIDTH of inst : label is 1;
attribute C_PROBE_OUT149_INIT_VAL : string;
attribute C_PROBE_OUT149_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT149_WIDTH : integer;
attribute C_PROBE_OUT149_WIDTH of inst : label is 1;
attribute C_PROBE_OUT14_INIT_VAL : string;
attribute C_PROBE_OUT14_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT14_WIDTH : integer;
attribute C_PROBE_OUT14_WIDTH of inst : label is 1;
attribute C_PROBE_OUT150_INIT_VAL : string;
attribute C_PROBE_OUT150_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT150_WIDTH : integer;
attribute C_PROBE_OUT150_WIDTH of inst : label is 1;
attribute C_PROBE_OUT151_INIT_VAL : string;
attribute C_PROBE_OUT151_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT151_WIDTH : integer;
attribute C_PROBE_OUT151_WIDTH of inst : label is 1;
attribute C_PROBE_OUT152_INIT_VAL : string;
attribute C_PROBE_OUT152_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT152_WIDTH : integer;
attribute C_PROBE_OUT152_WIDTH of inst : label is 1;
attribute C_PROBE_OUT153_INIT_VAL : string;
attribute C_PROBE_OUT153_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT153_WIDTH : integer;
attribute C_PROBE_OUT153_WIDTH of inst : label is 1;
attribute C_PROBE_OUT154_INIT_VAL : string;
attribute C_PROBE_OUT154_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT154_WIDTH : integer;
attribute C_PROBE_OUT154_WIDTH of inst : label is 1;
attribute C_PROBE_OUT155_INIT_VAL : string;
attribute C_PROBE_OUT155_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT155_WIDTH : integer;
attribute C_PROBE_OUT155_WIDTH of inst : label is 1;
attribute C_PROBE_OUT156_INIT_VAL : string;
attribute C_PROBE_OUT156_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT156_WIDTH : integer;
attribute C_PROBE_OUT156_WIDTH of inst : label is 1;
attribute C_PROBE_OUT157_INIT_VAL : string;
attribute C_PROBE_OUT157_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT157_WIDTH : integer;
attribute C_PROBE_OUT157_WIDTH of inst : label is 1;
attribute C_PROBE_OUT158_INIT_VAL : string;
attribute C_PROBE_OUT158_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT158_WIDTH : integer;
attribute C_PROBE_OUT158_WIDTH of inst : label is 1;
attribute C_PROBE_OUT159_INIT_VAL : string;
attribute C_PROBE_OUT159_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT159_WIDTH : integer;
attribute C_PROBE_OUT159_WIDTH of inst : label is 1;
attribute C_PROBE_OUT15_INIT_VAL : string;
attribute C_PROBE_OUT15_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT15_WIDTH : integer;
attribute C_PROBE_OUT15_WIDTH of inst : label is 1;
attribute C_PROBE_OUT160_INIT_VAL : string;
attribute C_PROBE_OUT160_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT160_WIDTH : integer;
attribute C_PROBE_OUT160_WIDTH of inst : label is 1;
attribute C_PROBE_OUT161_INIT_VAL : string;
attribute C_PROBE_OUT161_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT161_WIDTH : integer;
attribute C_PROBE_OUT161_WIDTH of inst : label is 1;
attribute C_PROBE_OUT162_INIT_VAL : string;
attribute C_PROBE_OUT162_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT162_WIDTH : integer;
attribute C_PROBE_OUT162_WIDTH of inst : label is 1;
attribute C_PROBE_OUT163_INIT_VAL : string;
attribute C_PROBE_OUT163_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT163_WIDTH : integer;
attribute C_PROBE_OUT163_WIDTH of inst : label is 1;
attribute C_PROBE_OUT164_INIT_VAL : string;
attribute C_PROBE_OUT164_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT164_WIDTH : integer;
attribute C_PROBE_OUT164_WIDTH of inst : label is 1;
attribute C_PROBE_OUT165_INIT_VAL : string;
attribute C_PROBE_OUT165_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT165_WIDTH : integer;
attribute C_PROBE_OUT165_WIDTH of inst : label is 1;
attribute C_PROBE_OUT166_INIT_VAL : string;
attribute C_PROBE_OUT166_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT166_WIDTH : integer;
attribute C_PROBE_OUT166_WIDTH of inst : label is 1;
attribute C_PROBE_OUT167_INIT_VAL : string;
attribute C_PROBE_OUT167_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT167_WIDTH : integer;
attribute C_PROBE_OUT167_WIDTH of inst : label is 1;
attribute C_PROBE_OUT168_INIT_VAL : string;
attribute C_PROBE_OUT168_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT168_WIDTH : integer;
attribute C_PROBE_OUT168_WIDTH of inst : label is 1;
attribute C_PROBE_OUT169_INIT_VAL : string;
attribute C_PROBE_OUT169_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT169_WIDTH : integer;
attribute C_PROBE_OUT169_WIDTH of inst : label is 1;
attribute C_PROBE_OUT16_INIT_VAL : string;
attribute C_PROBE_OUT16_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT16_WIDTH : integer;
attribute C_PROBE_OUT16_WIDTH of inst : label is 1;
attribute C_PROBE_OUT170_INIT_VAL : string;
attribute C_PROBE_OUT170_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT170_WIDTH : integer;
attribute C_PROBE_OUT170_WIDTH of inst : label is 1;
attribute C_PROBE_OUT171_INIT_VAL : string;
attribute C_PROBE_OUT171_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT171_WIDTH : integer;
attribute C_PROBE_OUT171_WIDTH of inst : label is 1;
attribute C_PROBE_OUT172_INIT_VAL : string;
attribute C_PROBE_OUT172_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT172_WIDTH : integer;
attribute C_PROBE_OUT172_WIDTH of inst : label is 1;
attribute C_PROBE_OUT173_INIT_VAL : string;
attribute C_PROBE_OUT173_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT173_WIDTH : integer;
attribute C_PROBE_OUT173_WIDTH of inst : label is 1;
attribute C_PROBE_OUT174_INIT_VAL : string;
attribute C_PROBE_OUT174_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT174_WIDTH : integer;
attribute C_PROBE_OUT174_WIDTH of inst : label is 1;
attribute C_PROBE_OUT175_INIT_VAL : string;
attribute C_PROBE_OUT175_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT175_WIDTH : integer;
attribute C_PROBE_OUT175_WIDTH of inst : label is 1;
attribute C_PROBE_OUT176_INIT_VAL : string;
attribute C_PROBE_OUT176_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT176_WIDTH : integer;
attribute C_PROBE_OUT176_WIDTH of inst : label is 1;
attribute C_PROBE_OUT177_INIT_VAL : string;
attribute C_PROBE_OUT177_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT177_WIDTH : integer;
attribute C_PROBE_OUT177_WIDTH of inst : label is 1;
attribute C_PROBE_OUT178_INIT_VAL : string;
attribute C_PROBE_OUT178_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT178_WIDTH : integer;
attribute C_PROBE_OUT178_WIDTH of inst : label is 1;
attribute C_PROBE_OUT179_INIT_VAL : string;
attribute C_PROBE_OUT179_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT179_WIDTH : integer;
attribute C_PROBE_OUT179_WIDTH of inst : label is 1;
attribute C_PROBE_OUT17_INIT_VAL : string;
attribute C_PROBE_OUT17_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT17_WIDTH : integer;
attribute C_PROBE_OUT17_WIDTH of inst : label is 1;
attribute C_PROBE_OUT180_INIT_VAL : string;
attribute C_PROBE_OUT180_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT180_WIDTH : integer;
attribute C_PROBE_OUT180_WIDTH of inst : label is 1;
attribute C_PROBE_OUT181_INIT_VAL : string;
attribute C_PROBE_OUT181_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT181_WIDTH : integer;
attribute C_PROBE_OUT181_WIDTH of inst : label is 1;
attribute C_PROBE_OUT182_INIT_VAL : string;
attribute C_PROBE_OUT182_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT182_WIDTH : integer;
attribute C_PROBE_OUT182_WIDTH of inst : label is 1;
attribute C_PROBE_OUT183_INIT_VAL : string;
attribute C_PROBE_OUT183_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT183_WIDTH : integer;
attribute C_PROBE_OUT183_WIDTH of inst : label is 1;
attribute C_PROBE_OUT184_INIT_VAL : string;
attribute C_PROBE_OUT184_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT184_WIDTH : integer;
attribute C_PROBE_OUT184_WIDTH of inst : label is 1;
attribute C_PROBE_OUT185_INIT_VAL : string;
attribute C_PROBE_OUT185_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT185_WIDTH : integer;
attribute C_PROBE_OUT185_WIDTH of inst : label is 1;
attribute C_PROBE_OUT186_INIT_VAL : string;
attribute C_PROBE_OUT186_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT186_WIDTH : integer;
attribute C_PROBE_OUT186_WIDTH of inst : label is 1;
attribute C_PROBE_OUT187_INIT_VAL : string;
attribute C_PROBE_OUT187_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT187_WIDTH : integer;
attribute C_PROBE_OUT187_WIDTH of inst : label is 1;
attribute C_PROBE_OUT188_INIT_VAL : string;
attribute C_PROBE_OUT188_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT188_WIDTH : integer;
attribute C_PROBE_OUT188_WIDTH of inst : label is 1;
attribute C_PROBE_OUT189_INIT_VAL : string;
attribute C_PROBE_OUT189_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT189_WIDTH : integer;
attribute C_PROBE_OUT189_WIDTH of inst : label is 1;
attribute C_PROBE_OUT18_INIT_VAL : string;
attribute C_PROBE_OUT18_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT18_WIDTH : integer;
attribute C_PROBE_OUT18_WIDTH of inst : label is 1;
attribute C_PROBE_OUT190_INIT_VAL : string;
attribute C_PROBE_OUT190_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT190_WIDTH : integer;
attribute C_PROBE_OUT190_WIDTH of inst : label is 1;
attribute C_PROBE_OUT191_INIT_VAL : string;
attribute C_PROBE_OUT191_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT191_WIDTH : integer;
attribute C_PROBE_OUT191_WIDTH of inst : label is 1;
attribute C_PROBE_OUT192_INIT_VAL : string;
attribute C_PROBE_OUT192_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT192_WIDTH : integer;
attribute C_PROBE_OUT192_WIDTH of inst : label is 1;
attribute C_PROBE_OUT193_INIT_VAL : string;
attribute C_PROBE_OUT193_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT193_WIDTH : integer;
attribute C_PROBE_OUT193_WIDTH of inst : label is 1;
attribute C_PROBE_OUT194_INIT_VAL : string;
attribute C_PROBE_OUT194_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT194_WIDTH : integer;
attribute C_PROBE_OUT194_WIDTH of inst : label is 1;
attribute C_PROBE_OUT195_INIT_VAL : string;
attribute C_PROBE_OUT195_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT195_WIDTH : integer;
attribute C_PROBE_OUT195_WIDTH of inst : label is 1;
attribute C_PROBE_OUT196_INIT_VAL : string;
attribute C_PROBE_OUT196_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT196_WIDTH : integer;
attribute C_PROBE_OUT196_WIDTH of inst : label is 1;
attribute C_PROBE_OUT197_INIT_VAL : string;
attribute C_PROBE_OUT197_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT197_WIDTH : integer;
attribute C_PROBE_OUT197_WIDTH of inst : label is 1;
attribute C_PROBE_OUT198_INIT_VAL : string;
attribute C_PROBE_OUT198_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT198_WIDTH : integer;
attribute C_PROBE_OUT198_WIDTH of inst : label is 1;
attribute C_PROBE_OUT199_INIT_VAL : string;
attribute C_PROBE_OUT199_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT199_WIDTH : integer;
attribute C_PROBE_OUT199_WIDTH of inst : label is 1;
attribute C_PROBE_OUT19_INIT_VAL : string;
attribute C_PROBE_OUT19_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT19_WIDTH : integer;
attribute C_PROBE_OUT19_WIDTH of inst : label is 1;
attribute C_PROBE_OUT1_INIT_VAL : string;
attribute C_PROBE_OUT1_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT1_WIDTH : integer;
attribute C_PROBE_OUT1_WIDTH of inst : label is 1;
attribute C_PROBE_OUT200_INIT_VAL : string;
attribute C_PROBE_OUT200_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT200_WIDTH : integer;
attribute C_PROBE_OUT200_WIDTH of inst : label is 1;
attribute C_PROBE_OUT201_INIT_VAL : string;
attribute C_PROBE_OUT201_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT201_WIDTH : integer;
attribute C_PROBE_OUT201_WIDTH of inst : label is 1;
attribute C_PROBE_OUT202_INIT_VAL : string;
attribute C_PROBE_OUT202_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT202_WIDTH : integer;
attribute C_PROBE_OUT202_WIDTH of inst : label is 1;
attribute C_PROBE_OUT203_INIT_VAL : string;
attribute C_PROBE_OUT203_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT203_WIDTH : integer;
attribute C_PROBE_OUT203_WIDTH of inst : label is 1;
attribute C_PROBE_OUT204_INIT_VAL : string;
attribute C_PROBE_OUT204_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT204_WIDTH : integer;
attribute C_PROBE_OUT204_WIDTH of inst : label is 1;
attribute C_PROBE_OUT205_INIT_VAL : string;
attribute C_PROBE_OUT205_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT205_WIDTH : integer;
attribute C_PROBE_OUT205_WIDTH of inst : label is 1;
attribute C_PROBE_OUT206_INIT_VAL : string;
attribute C_PROBE_OUT206_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT206_WIDTH : integer;
attribute C_PROBE_OUT206_WIDTH of inst : label is 1;
attribute C_PROBE_OUT207_INIT_VAL : string;
attribute C_PROBE_OUT207_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT207_WIDTH : integer;
attribute C_PROBE_OUT207_WIDTH of inst : label is 1;
attribute C_PROBE_OUT208_INIT_VAL : string;
attribute C_PROBE_OUT208_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT208_WIDTH : integer;
attribute C_PROBE_OUT208_WIDTH of inst : label is 1;
attribute C_PROBE_OUT209_INIT_VAL : string;
attribute C_PROBE_OUT209_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT209_WIDTH : integer;
attribute C_PROBE_OUT209_WIDTH of inst : label is 1;
attribute C_PROBE_OUT20_INIT_VAL : string;
attribute C_PROBE_OUT20_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT20_WIDTH : integer;
attribute C_PROBE_OUT20_WIDTH of inst : label is 1;
attribute C_PROBE_OUT210_INIT_VAL : string;
attribute C_PROBE_OUT210_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT210_WIDTH : integer;
attribute C_PROBE_OUT210_WIDTH of inst : label is 1;
attribute C_PROBE_OUT211_INIT_VAL : string;
attribute C_PROBE_OUT211_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT211_WIDTH : integer;
attribute C_PROBE_OUT211_WIDTH of inst : label is 1;
attribute C_PROBE_OUT212_INIT_VAL : string;
attribute C_PROBE_OUT212_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT212_WIDTH : integer;
attribute C_PROBE_OUT212_WIDTH of inst : label is 1;
attribute C_PROBE_OUT213_INIT_VAL : string;
attribute C_PROBE_OUT213_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT213_WIDTH : integer;
attribute C_PROBE_OUT213_WIDTH of inst : label is 1;
attribute C_PROBE_OUT214_INIT_VAL : string;
attribute C_PROBE_OUT214_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT214_WIDTH : integer;
attribute C_PROBE_OUT214_WIDTH of inst : label is 1;
attribute C_PROBE_OUT215_INIT_VAL : string;
attribute C_PROBE_OUT215_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT215_WIDTH : integer;
attribute C_PROBE_OUT215_WIDTH of inst : label is 1;
attribute C_PROBE_OUT216_INIT_VAL : string;
attribute C_PROBE_OUT216_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT216_WIDTH : integer;
attribute C_PROBE_OUT216_WIDTH of inst : label is 1;
attribute C_PROBE_OUT217_INIT_VAL : string;
attribute C_PROBE_OUT217_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT217_WIDTH : integer;
attribute C_PROBE_OUT217_WIDTH of inst : label is 1;
attribute C_PROBE_OUT218_INIT_VAL : string;
attribute C_PROBE_OUT218_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT218_WIDTH : integer;
attribute C_PROBE_OUT218_WIDTH of inst : label is 1;
attribute C_PROBE_OUT219_INIT_VAL : string;
attribute C_PROBE_OUT219_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT219_WIDTH : integer;
attribute C_PROBE_OUT219_WIDTH of inst : label is 1;
attribute C_PROBE_OUT21_INIT_VAL : string;
attribute C_PROBE_OUT21_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT21_WIDTH : integer;
attribute C_PROBE_OUT21_WIDTH of inst : label is 1;
attribute C_PROBE_OUT220_INIT_VAL : string;
attribute C_PROBE_OUT220_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT220_WIDTH : integer;
attribute C_PROBE_OUT220_WIDTH of inst : label is 1;
attribute C_PROBE_OUT221_INIT_VAL : string;
attribute C_PROBE_OUT221_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT221_WIDTH : integer;
attribute C_PROBE_OUT221_WIDTH of inst : label is 1;
attribute C_PROBE_OUT222_INIT_VAL : string;
attribute C_PROBE_OUT222_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT222_WIDTH : integer;
attribute C_PROBE_OUT222_WIDTH of inst : label is 1;
attribute C_PROBE_OUT223_INIT_VAL : string;
attribute C_PROBE_OUT223_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT223_WIDTH : integer;
attribute C_PROBE_OUT223_WIDTH of inst : label is 1;
attribute C_PROBE_OUT224_INIT_VAL : string;
attribute C_PROBE_OUT224_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT224_WIDTH : integer;
attribute C_PROBE_OUT224_WIDTH of inst : label is 1;
attribute C_PROBE_OUT225_INIT_VAL : string;
attribute C_PROBE_OUT225_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT225_WIDTH : integer;
attribute C_PROBE_OUT225_WIDTH of inst : label is 1;
attribute C_PROBE_OUT226_INIT_VAL : string;
attribute C_PROBE_OUT226_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT226_WIDTH : integer;
attribute C_PROBE_OUT226_WIDTH of inst : label is 1;
attribute C_PROBE_OUT227_INIT_VAL : string;
attribute C_PROBE_OUT227_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT227_WIDTH : integer;
attribute C_PROBE_OUT227_WIDTH of inst : label is 1;
attribute C_PROBE_OUT228_INIT_VAL : string;
attribute C_PROBE_OUT228_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT228_WIDTH : integer;
attribute C_PROBE_OUT228_WIDTH of inst : label is 1;
attribute C_PROBE_OUT229_INIT_VAL : string;
attribute C_PROBE_OUT229_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT229_WIDTH : integer;
attribute C_PROBE_OUT229_WIDTH of inst : label is 1;
attribute C_PROBE_OUT22_INIT_VAL : string;
attribute C_PROBE_OUT22_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT22_WIDTH : integer;
attribute C_PROBE_OUT22_WIDTH of inst : label is 1;
attribute C_PROBE_OUT230_INIT_VAL : string;
attribute C_PROBE_OUT230_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT230_WIDTH : integer;
attribute C_PROBE_OUT230_WIDTH of inst : label is 1;
attribute C_PROBE_OUT231_INIT_VAL : string;
attribute C_PROBE_OUT231_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT231_WIDTH : integer;
attribute C_PROBE_OUT231_WIDTH of inst : label is 1;
attribute C_PROBE_OUT232_INIT_VAL : string;
attribute C_PROBE_OUT232_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT232_WIDTH : integer;
attribute C_PROBE_OUT232_WIDTH of inst : label is 1;
attribute C_PROBE_OUT233_INIT_VAL : string;
attribute C_PROBE_OUT233_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT233_WIDTH : integer;
attribute C_PROBE_OUT233_WIDTH of inst : label is 1;
attribute C_PROBE_OUT234_INIT_VAL : string;
attribute C_PROBE_OUT234_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT234_WIDTH : integer;
attribute C_PROBE_OUT234_WIDTH of inst : label is 1;
attribute C_PROBE_OUT235_INIT_VAL : string;
attribute C_PROBE_OUT235_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT235_WIDTH : integer;
attribute C_PROBE_OUT235_WIDTH of inst : label is 1;
attribute C_PROBE_OUT236_INIT_VAL : string;
attribute C_PROBE_OUT236_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT236_WIDTH : integer;
attribute C_PROBE_OUT236_WIDTH of inst : label is 1;
attribute C_PROBE_OUT237_INIT_VAL : string;
attribute C_PROBE_OUT237_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT237_WIDTH : integer;
attribute C_PROBE_OUT237_WIDTH of inst : label is 1;
attribute C_PROBE_OUT238_INIT_VAL : string;
attribute C_PROBE_OUT238_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT238_WIDTH : integer;
attribute C_PROBE_OUT238_WIDTH of inst : label is 1;
attribute C_PROBE_OUT239_INIT_VAL : string;
attribute C_PROBE_OUT239_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT239_WIDTH : integer;
attribute C_PROBE_OUT239_WIDTH of inst : label is 1;
attribute C_PROBE_OUT23_INIT_VAL : string;
attribute C_PROBE_OUT23_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT23_WIDTH : integer;
attribute C_PROBE_OUT23_WIDTH of inst : label is 1;
attribute C_PROBE_OUT240_INIT_VAL : string;
attribute C_PROBE_OUT240_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT240_WIDTH : integer;
attribute C_PROBE_OUT240_WIDTH of inst : label is 1;
attribute C_PROBE_OUT241_INIT_VAL : string;
attribute C_PROBE_OUT241_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT241_WIDTH : integer;
attribute C_PROBE_OUT241_WIDTH of inst : label is 1;
attribute C_PROBE_OUT242_INIT_VAL : string;
attribute C_PROBE_OUT242_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT242_WIDTH : integer;
attribute C_PROBE_OUT242_WIDTH of inst : label is 1;
attribute C_PROBE_OUT243_INIT_VAL : string;
attribute C_PROBE_OUT243_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT243_WIDTH : integer;
attribute C_PROBE_OUT243_WIDTH of inst : label is 1;
attribute C_PROBE_OUT244_INIT_VAL : string;
attribute C_PROBE_OUT244_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT244_WIDTH : integer;
attribute C_PROBE_OUT244_WIDTH of inst : label is 1;
attribute C_PROBE_OUT245_INIT_VAL : string;
attribute C_PROBE_OUT245_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT245_WIDTH : integer;
attribute C_PROBE_OUT245_WIDTH of inst : label is 1;
attribute C_PROBE_OUT246_INIT_VAL : string;
attribute C_PROBE_OUT246_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT246_WIDTH : integer;
attribute C_PROBE_OUT246_WIDTH of inst : label is 1;
attribute C_PROBE_OUT247_INIT_VAL : string;
attribute C_PROBE_OUT247_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT247_WIDTH : integer;
attribute C_PROBE_OUT247_WIDTH of inst : label is 1;
attribute C_PROBE_OUT248_INIT_VAL : string;
attribute C_PROBE_OUT248_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT248_WIDTH : integer;
attribute C_PROBE_OUT248_WIDTH of inst : label is 1;
attribute C_PROBE_OUT249_INIT_VAL : string;
attribute C_PROBE_OUT249_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT249_WIDTH : integer;
attribute C_PROBE_OUT249_WIDTH of inst : label is 1;
attribute C_PROBE_OUT24_INIT_VAL : string;
attribute C_PROBE_OUT24_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT24_WIDTH : integer;
attribute C_PROBE_OUT24_WIDTH of inst : label is 1;
attribute C_PROBE_OUT250_INIT_VAL : string;
attribute C_PROBE_OUT250_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT250_WIDTH : integer;
attribute C_PROBE_OUT250_WIDTH of inst : label is 1;
attribute C_PROBE_OUT251_INIT_VAL : string;
attribute C_PROBE_OUT251_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT251_WIDTH : integer;
attribute C_PROBE_OUT251_WIDTH of inst : label is 1;
attribute C_PROBE_OUT252_INIT_VAL : string;
attribute C_PROBE_OUT252_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT252_WIDTH : integer;
attribute C_PROBE_OUT252_WIDTH of inst : label is 1;
attribute C_PROBE_OUT253_INIT_VAL : string;
attribute C_PROBE_OUT253_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT253_WIDTH : integer;
attribute C_PROBE_OUT253_WIDTH of inst : label is 1;
attribute C_PROBE_OUT254_INIT_VAL : string;
attribute C_PROBE_OUT254_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT254_WIDTH : integer;
attribute C_PROBE_OUT254_WIDTH of inst : label is 1;
attribute C_PROBE_OUT255_INIT_VAL : string;
attribute C_PROBE_OUT255_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT255_WIDTH : integer;
attribute C_PROBE_OUT255_WIDTH of inst : label is 1;
attribute C_PROBE_OUT25_INIT_VAL : string;
attribute C_PROBE_OUT25_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT25_WIDTH : integer;
attribute C_PROBE_OUT25_WIDTH of inst : label is 1;
attribute C_PROBE_OUT26_INIT_VAL : string;
attribute C_PROBE_OUT26_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT26_WIDTH : integer;
attribute C_PROBE_OUT26_WIDTH of inst : label is 1;
attribute C_PROBE_OUT27_INIT_VAL : string;
attribute C_PROBE_OUT27_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT27_WIDTH : integer;
attribute C_PROBE_OUT27_WIDTH of inst : label is 1;
attribute C_PROBE_OUT28_INIT_VAL : string;
attribute C_PROBE_OUT28_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT28_WIDTH : integer;
attribute C_PROBE_OUT28_WIDTH of inst : label is 1;
attribute C_PROBE_OUT29_INIT_VAL : string;
attribute C_PROBE_OUT29_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT29_WIDTH : integer;
attribute C_PROBE_OUT29_WIDTH of inst : label is 1;
attribute C_PROBE_OUT2_INIT_VAL : string;
attribute C_PROBE_OUT2_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT2_WIDTH : integer;
attribute C_PROBE_OUT2_WIDTH of inst : label is 1;
attribute C_PROBE_OUT30_INIT_VAL : string;
attribute C_PROBE_OUT30_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT30_WIDTH : integer;
attribute C_PROBE_OUT30_WIDTH of inst : label is 1;
attribute C_PROBE_OUT31_INIT_VAL : string;
attribute C_PROBE_OUT31_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT31_WIDTH : integer;
attribute C_PROBE_OUT31_WIDTH of inst : label is 1;
attribute C_PROBE_OUT32_INIT_VAL : string;
attribute C_PROBE_OUT32_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT32_WIDTH : integer;
attribute C_PROBE_OUT32_WIDTH of inst : label is 1;
attribute C_PROBE_OUT33_INIT_VAL : string;
attribute C_PROBE_OUT33_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT33_WIDTH : integer;
attribute C_PROBE_OUT33_WIDTH of inst : label is 1;
attribute C_PROBE_OUT34_INIT_VAL : string;
attribute C_PROBE_OUT34_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT34_WIDTH : integer;
attribute C_PROBE_OUT34_WIDTH of inst : label is 1;
attribute C_PROBE_OUT35_INIT_VAL : string;
attribute C_PROBE_OUT35_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT35_WIDTH : integer;
attribute C_PROBE_OUT35_WIDTH of inst : label is 1;
attribute C_PROBE_OUT36_INIT_VAL : string;
attribute C_PROBE_OUT36_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT36_WIDTH : integer;
attribute C_PROBE_OUT36_WIDTH of inst : label is 1;
attribute C_PROBE_OUT37_INIT_VAL : string;
attribute C_PROBE_OUT37_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT37_WIDTH : integer;
attribute C_PROBE_OUT37_WIDTH of inst : label is 1;
attribute C_PROBE_OUT38_INIT_VAL : string;
attribute C_PROBE_OUT38_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT38_WIDTH : integer;
attribute C_PROBE_OUT38_WIDTH of inst : label is 1;
attribute C_PROBE_OUT39_INIT_VAL : string;
attribute C_PROBE_OUT39_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT39_WIDTH : integer;
attribute C_PROBE_OUT39_WIDTH of inst : label is 1;
attribute C_PROBE_OUT3_INIT_VAL : string;
attribute C_PROBE_OUT3_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT3_WIDTH : integer;
attribute C_PROBE_OUT3_WIDTH of inst : label is 1;
attribute C_PROBE_OUT40_INIT_VAL : string;
attribute C_PROBE_OUT40_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT40_WIDTH : integer;
attribute C_PROBE_OUT40_WIDTH of inst : label is 1;
attribute C_PROBE_OUT41_INIT_VAL : string;
attribute C_PROBE_OUT41_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT41_WIDTH : integer;
attribute C_PROBE_OUT41_WIDTH of inst : label is 1;
attribute C_PROBE_OUT42_INIT_VAL : string;
attribute C_PROBE_OUT42_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT42_WIDTH : integer;
attribute C_PROBE_OUT42_WIDTH of inst : label is 1;
attribute C_PROBE_OUT43_INIT_VAL : string;
attribute C_PROBE_OUT43_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT43_WIDTH : integer;
attribute C_PROBE_OUT43_WIDTH of inst : label is 1;
attribute C_PROBE_OUT44_INIT_VAL : string;
attribute C_PROBE_OUT44_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT44_WIDTH : integer;
attribute C_PROBE_OUT44_WIDTH of inst : label is 1;
attribute C_PROBE_OUT45_INIT_VAL : string;
attribute C_PROBE_OUT45_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT45_WIDTH : integer;
attribute C_PROBE_OUT45_WIDTH of inst : label is 1;
attribute C_PROBE_OUT46_INIT_VAL : string;
attribute C_PROBE_OUT46_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT46_WIDTH : integer;
attribute C_PROBE_OUT46_WIDTH of inst : label is 1;
attribute C_PROBE_OUT47_INIT_VAL : string;
attribute C_PROBE_OUT47_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT47_WIDTH : integer;
attribute C_PROBE_OUT47_WIDTH of inst : label is 1;
attribute C_PROBE_OUT48_INIT_VAL : string;
attribute C_PROBE_OUT48_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT48_WIDTH : integer;
attribute C_PROBE_OUT48_WIDTH of inst : label is 1;
attribute C_PROBE_OUT49_INIT_VAL : string;
attribute C_PROBE_OUT49_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT49_WIDTH : integer;
attribute C_PROBE_OUT49_WIDTH of inst : label is 1;
attribute C_PROBE_OUT4_INIT_VAL : string;
attribute C_PROBE_OUT4_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT4_WIDTH : integer;
attribute C_PROBE_OUT4_WIDTH of inst : label is 1;
attribute C_PROBE_OUT50_INIT_VAL : string;
attribute C_PROBE_OUT50_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT50_WIDTH : integer;
attribute C_PROBE_OUT50_WIDTH of inst : label is 1;
attribute C_PROBE_OUT51_INIT_VAL : string;
attribute C_PROBE_OUT51_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT51_WIDTH : integer;
attribute C_PROBE_OUT51_WIDTH of inst : label is 1;
attribute C_PROBE_OUT52_INIT_VAL : string;
attribute C_PROBE_OUT52_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT52_WIDTH : integer;
attribute C_PROBE_OUT52_WIDTH of inst : label is 1;
attribute C_PROBE_OUT53_INIT_VAL : string;
attribute C_PROBE_OUT53_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT53_WIDTH : integer;
attribute C_PROBE_OUT53_WIDTH of inst : label is 1;
attribute C_PROBE_OUT54_INIT_VAL : string;
attribute C_PROBE_OUT54_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT54_WIDTH : integer;
attribute C_PROBE_OUT54_WIDTH of inst : label is 1;
attribute C_PROBE_OUT55_INIT_VAL : string;
attribute C_PROBE_OUT55_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT55_WIDTH : integer;
attribute C_PROBE_OUT55_WIDTH of inst : label is 1;
attribute C_PROBE_OUT56_INIT_VAL : string;
attribute C_PROBE_OUT56_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT56_WIDTH : integer;
attribute C_PROBE_OUT56_WIDTH of inst : label is 1;
attribute C_PROBE_OUT57_INIT_VAL : string;
attribute C_PROBE_OUT57_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT57_WIDTH : integer;
attribute C_PROBE_OUT57_WIDTH of inst : label is 1;
attribute C_PROBE_OUT58_INIT_VAL : string;
attribute C_PROBE_OUT58_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT58_WIDTH : integer;
attribute C_PROBE_OUT58_WIDTH of inst : label is 1;
attribute C_PROBE_OUT59_INIT_VAL : string;
attribute C_PROBE_OUT59_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT59_WIDTH : integer;
attribute C_PROBE_OUT59_WIDTH of inst : label is 1;
attribute C_PROBE_OUT5_INIT_VAL : string;
attribute C_PROBE_OUT5_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT5_WIDTH : integer;
attribute C_PROBE_OUT5_WIDTH of inst : label is 1;
attribute C_PROBE_OUT60_INIT_VAL : string;
attribute C_PROBE_OUT60_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT60_WIDTH : integer;
attribute C_PROBE_OUT60_WIDTH of inst : label is 1;
attribute C_PROBE_OUT61_INIT_VAL : string;
attribute C_PROBE_OUT61_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT61_WIDTH : integer;
attribute C_PROBE_OUT61_WIDTH of inst : label is 1;
attribute C_PROBE_OUT62_INIT_VAL : string;
attribute C_PROBE_OUT62_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT62_WIDTH : integer;
attribute C_PROBE_OUT62_WIDTH of inst : label is 1;
attribute C_PROBE_OUT63_INIT_VAL : string;
attribute C_PROBE_OUT63_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT63_WIDTH : integer;
attribute C_PROBE_OUT63_WIDTH of inst : label is 1;
attribute C_PROBE_OUT64_INIT_VAL : string;
attribute C_PROBE_OUT64_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT64_WIDTH : integer;
attribute C_PROBE_OUT64_WIDTH of inst : label is 1;
attribute C_PROBE_OUT65_INIT_VAL : string;
attribute C_PROBE_OUT65_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT65_WIDTH : integer;
attribute C_PROBE_OUT65_WIDTH of inst : label is 1;
attribute C_PROBE_OUT66_INIT_VAL : string;
attribute C_PROBE_OUT66_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT66_WIDTH : integer;
attribute C_PROBE_OUT66_WIDTH of inst : label is 1;
attribute C_PROBE_OUT67_INIT_VAL : string;
attribute C_PROBE_OUT67_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT67_WIDTH : integer;
attribute C_PROBE_OUT67_WIDTH of inst : label is 1;
attribute C_PROBE_OUT68_INIT_VAL : string;
attribute C_PROBE_OUT68_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT68_WIDTH : integer;
attribute C_PROBE_OUT68_WIDTH of inst : label is 1;
attribute C_PROBE_OUT69_INIT_VAL : string;
attribute C_PROBE_OUT69_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT69_WIDTH : integer;
attribute C_PROBE_OUT69_WIDTH of inst : label is 1;
attribute C_PROBE_OUT6_INIT_VAL : string;
attribute C_PROBE_OUT6_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT6_WIDTH : integer;
attribute C_PROBE_OUT6_WIDTH of inst : label is 1;
attribute C_PROBE_OUT70_INIT_VAL : string;
attribute C_PROBE_OUT70_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT70_WIDTH : integer;
attribute C_PROBE_OUT70_WIDTH of inst : label is 1;
attribute C_PROBE_OUT71_INIT_VAL : string;
attribute C_PROBE_OUT71_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT71_WIDTH : integer;
attribute C_PROBE_OUT71_WIDTH of inst : label is 1;
attribute C_PROBE_OUT72_INIT_VAL : string;
attribute C_PROBE_OUT72_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT72_WIDTH : integer;
attribute C_PROBE_OUT72_WIDTH of inst : label is 1;
attribute C_PROBE_OUT73_INIT_VAL : string;
attribute C_PROBE_OUT73_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT73_WIDTH : integer;
attribute C_PROBE_OUT73_WIDTH of inst : label is 1;
attribute C_PROBE_OUT74_INIT_VAL : string;
attribute C_PROBE_OUT74_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT74_WIDTH : integer;
attribute C_PROBE_OUT74_WIDTH of inst : label is 1;
attribute C_PROBE_OUT75_INIT_VAL : string;
attribute C_PROBE_OUT75_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT75_WIDTH : integer;
attribute C_PROBE_OUT75_WIDTH of inst : label is 1;
attribute C_PROBE_OUT76_INIT_VAL : string;
attribute C_PROBE_OUT76_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT76_WIDTH : integer;
attribute C_PROBE_OUT76_WIDTH of inst : label is 1;
attribute C_PROBE_OUT77_INIT_VAL : string;
attribute C_PROBE_OUT77_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT77_WIDTH : integer;
attribute C_PROBE_OUT77_WIDTH of inst : label is 1;
attribute C_PROBE_OUT78_INIT_VAL : string;
attribute C_PROBE_OUT78_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT78_WIDTH : integer;
attribute C_PROBE_OUT78_WIDTH of inst : label is 1;
attribute C_PROBE_OUT79_INIT_VAL : string;
attribute C_PROBE_OUT79_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT79_WIDTH : integer;
attribute C_PROBE_OUT79_WIDTH of inst : label is 1;
attribute C_PROBE_OUT7_INIT_VAL : string;
attribute C_PROBE_OUT7_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT7_WIDTH : integer;
attribute C_PROBE_OUT7_WIDTH of inst : label is 1;
attribute C_PROBE_OUT80_INIT_VAL : string;
attribute C_PROBE_OUT80_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT80_WIDTH : integer;
attribute C_PROBE_OUT80_WIDTH of inst : label is 1;
attribute C_PROBE_OUT81_INIT_VAL : string;
attribute C_PROBE_OUT81_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT81_WIDTH : integer;
attribute C_PROBE_OUT81_WIDTH of inst : label is 1;
attribute C_PROBE_OUT82_INIT_VAL : string;
attribute C_PROBE_OUT82_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT82_WIDTH : integer;
attribute C_PROBE_OUT82_WIDTH of inst : label is 1;
attribute C_PROBE_OUT83_INIT_VAL : string;
attribute C_PROBE_OUT83_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT83_WIDTH : integer;
attribute C_PROBE_OUT83_WIDTH of inst : label is 1;
attribute C_PROBE_OUT84_INIT_VAL : string;
attribute C_PROBE_OUT84_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT84_WIDTH : integer;
attribute C_PROBE_OUT84_WIDTH of inst : label is 1;
attribute C_PROBE_OUT85_INIT_VAL : string;
attribute C_PROBE_OUT85_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT85_WIDTH : integer;
attribute C_PROBE_OUT85_WIDTH of inst : label is 1;
attribute C_PROBE_OUT86_INIT_VAL : string;
attribute C_PROBE_OUT86_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT86_WIDTH : integer;
attribute C_PROBE_OUT86_WIDTH of inst : label is 1;
attribute C_PROBE_OUT87_INIT_VAL : string;
attribute C_PROBE_OUT87_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT87_WIDTH : integer;
attribute C_PROBE_OUT87_WIDTH of inst : label is 1;
attribute C_PROBE_OUT88_INIT_VAL : string;
attribute C_PROBE_OUT88_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT88_WIDTH : integer;
attribute C_PROBE_OUT88_WIDTH of inst : label is 1;
attribute C_PROBE_OUT89_INIT_VAL : string;
attribute C_PROBE_OUT89_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT89_WIDTH : integer;
attribute C_PROBE_OUT89_WIDTH of inst : label is 1;
attribute C_PROBE_OUT8_INIT_VAL : string;
attribute C_PROBE_OUT8_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT8_WIDTH : integer;
attribute C_PROBE_OUT8_WIDTH of inst : label is 1;
attribute C_PROBE_OUT90_INIT_VAL : string;
attribute C_PROBE_OUT90_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT90_WIDTH : integer;
attribute C_PROBE_OUT90_WIDTH of inst : label is 1;
attribute C_PROBE_OUT91_INIT_VAL : string;
attribute C_PROBE_OUT91_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT91_WIDTH : integer;
attribute C_PROBE_OUT91_WIDTH of inst : label is 1;
attribute C_PROBE_OUT92_INIT_VAL : string;
attribute C_PROBE_OUT92_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT92_WIDTH : integer;
attribute C_PROBE_OUT92_WIDTH of inst : label is 1;
attribute C_PROBE_OUT93_INIT_VAL : string;
attribute C_PROBE_OUT93_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT93_WIDTH : integer;
attribute C_PROBE_OUT93_WIDTH of inst : label is 1;
attribute C_PROBE_OUT94_INIT_VAL : string;
attribute C_PROBE_OUT94_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT94_WIDTH : integer;
attribute C_PROBE_OUT94_WIDTH of inst : label is 1;
attribute C_PROBE_OUT95_INIT_VAL : string;
attribute C_PROBE_OUT95_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT95_WIDTH : integer;
attribute C_PROBE_OUT95_WIDTH of inst : label is 1;
attribute C_PROBE_OUT96_INIT_VAL : string;
attribute C_PROBE_OUT96_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT96_WIDTH : integer;
attribute C_PROBE_OUT96_WIDTH of inst : label is 1;
attribute C_PROBE_OUT97_INIT_VAL : string;
attribute C_PROBE_OUT97_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT97_WIDTH : integer;
attribute C_PROBE_OUT97_WIDTH of inst : label is 1;
attribute C_PROBE_OUT98_INIT_VAL : string;
attribute C_PROBE_OUT98_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT98_WIDTH : integer;
attribute C_PROBE_OUT98_WIDTH of inst : label is 1;
attribute C_PROBE_OUT99_INIT_VAL : string;
attribute C_PROBE_OUT99_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT99_WIDTH : integer;
attribute C_PROBE_OUT99_WIDTH of inst : label is 1;
attribute C_PROBE_OUT9_INIT_VAL : string;
attribute C_PROBE_OUT9_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT9_WIDTH : integer;
attribute C_PROBE_OUT9_WIDTH of inst : label is 1;
attribute C_USE_TEST_REG : integer;
attribute C_USE_TEST_REG of inst : label is 1;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of inst : label is "kintex7";
attribute C_XLNX_HW_PROBE_INFO : string;
attribute C_XLNX_HW_PROBE_INFO of inst : label is "DEFAULT";
attribute C_XSDB_SLAVE_TYPE : integer;
attribute C_XSDB_SLAVE_TYPE of inst : label is 33;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of inst : label is std.standard.true;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute LC_HIGH_BIT_POS_PROBE_OUT0 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT0 of inst : label is "16'b0000000000000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT1 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT10 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT100 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000001100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT101 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000001100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT102 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000001100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT103 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000001100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT104 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000001101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT105 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000001101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT106 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000001101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT107 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000001101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT108 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000001101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT109 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000001101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT11 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT110 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000001101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT111 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000001101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT112 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000001110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT113 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000001110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT114 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000001110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT115 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000001110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT116 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000001110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT117 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000001110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT118 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000001110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT119 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000001110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT12 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT120 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000001111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT121 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000001111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT122 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000001111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT123 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000001111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT124 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000001111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT125 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000001111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT126 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000001111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT127 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000001111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT128 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT129 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT13 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT130 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT131 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT132 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT133 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT134 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT135 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT136 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT137 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT138 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT139 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT14 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT140 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT141 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT142 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT143 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT144 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT145 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT146 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT147 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT148 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT149 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT15 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT150 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT151 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT152 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT153 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT154 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT155 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000010011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT156 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000010011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT157 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000010011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT158 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000010011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT159 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000010011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT16 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT160 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000010100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT161 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000010100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT162 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000010100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT163 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000010100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT164 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000010100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT165 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000010100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT166 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000010100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT167 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000010100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT168 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000010101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT169 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000010101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT17 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT170 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000010101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT171 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000010101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT172 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000010101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT173 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000010101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT174 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000010101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT175 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000010101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT176 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000010110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT177 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000010110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT178 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000010110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT179 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000010110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT18 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT180 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000010110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT181 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000010110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT182 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000010110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT183 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000010110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT184 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000010111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT185 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000010111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT186 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000010111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT187 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000010111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT188 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000010111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT189 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000010111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT19 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT190 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000010111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT191 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000010111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT192 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT193 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT194 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT195 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT196 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT197 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT198 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT199 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT2 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT20 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT200 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT201 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT202 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT203 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT204 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT205 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT206 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT207 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT208 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT209 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT21 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT210 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT211 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT212 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT213 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT214 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT215 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT216 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT217 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT218 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT219 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000011011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT22 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT220 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000011011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT221 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000011011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT222 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000011011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT223 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000011011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT224 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000011100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT225 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000011100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT226 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000011100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT227 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000011100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT228 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000011100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT229 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000011100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT23 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT230 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000011100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT231 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000011100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT232 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000011101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT233 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000011101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT234 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000011101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT235 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000011101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT236 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000011101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT237 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000011101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT238 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000011101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT239 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000011101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT24 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT240 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000011110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT241 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000011110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT242 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000011110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT243 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000011110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT244 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000011110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT245 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000011110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT246 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000011110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT247 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000011110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT248 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000011111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT249 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000011111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT25 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT250 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000011111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT251 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000011111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT252 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000011111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT253 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000011111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT254 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000011111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT255 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000011111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT26 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT27 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000000011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT28 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000000011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT29 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000000011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT3 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT30 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000000011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT31 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000000011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT32 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000000100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT33 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000000100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT34 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000000100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT35 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000000100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT36 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000000100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT37 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000000100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT38 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000000100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT39 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000000100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT4 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT40 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000000101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT41 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000000101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT42 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000000101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT43 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000000101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT44 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000000101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT45 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000000101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT46 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000000101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT47 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000000101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT48 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000000110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT49 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000000110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT5 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT50 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000000110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT51 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000000110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT52 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000000110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT53 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000000110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT54 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000000110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT55 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000000110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT56 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000000111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT57 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000000111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT58 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000000111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT59 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000000111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT6 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT60 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000000111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT61 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000000111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT62 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000000111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT63 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000000111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT64 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT65 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT66 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT67 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT68 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT69 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT7 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT70 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT71 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT72 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT73 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT74 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT75 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT76 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT77 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT78 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT79 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT8 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT80 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT81 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT82 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT83 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT84 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT85 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT86 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT87 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT88 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT89 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT9 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT90 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT91 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000001011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT92 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000001011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT93 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000001011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT94 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000001011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT95 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000001011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT96 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000001100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT97 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000001100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT98 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000001100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT99 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000001100011";
attribute LC_LOW_BIT_POS_PROBE_OUT0 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT0 of inst : label is "16'b0000000000000000";
attribute LC_LOW_BIT_POS_PROBE_OUT1 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000000001";
attribute LC_LOW_BIT_POS_PROBE_OUT10 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000001010";
attribute LC_LOW_BIT_POS_PROBE_OUT100 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000001100100";
attribute LC_LOW_BIT_POS_PROBE_OUT101 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000001100101";
attribute LC_LOW_BIT_POS_PROBE_OUT102 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000001100110";
attribute LC_LOW_BIT_POS_PROBE_OUT103 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000001100111";
attribute LC_LOW_BIT_POS_PROBE_OUT104 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000001101000";
attribute LC_LOW_BIT_POS_PROBE_OUT105 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000001101001";
attribute LC_LOW_BIT_POS_PROBE_OUT106 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000001101010";
attribute LC_LOW_BIT_POS_PROBE_OUT107 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000001101011";
attribute LC_LOW_BIT_POS_PROBE_OUT108 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000001101100";
attribute LC_LOW_BIT_POS_PROBE_OUT109 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000001101101";
attribute LC_LOW_BIT_POS_PROBE_OUT11 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000001011";
attribute LC_LOW_BIT_POS_PROBE_OUT110 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000001101110";
attribute LC_LOW_BIT_POS_PROBE_OUT111 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000001101111";
attribute LC_LOW_BIT_POS_PROBE_OUT112 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000001110000";
attribute LC_LOW_BIT_POS_PROBE_OUT113 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000001110001";
attribute LC_LOW_BIT_POS_PROBE_OUT114 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000001110010";
attribute LC_LOW_BIT_POS_PROBE_OUT115 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000001110011";
attribute LC_LOW_BIT_POS_PROBE_OUT116 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000001110100";
attribute LC_LOW_BIT_POS_PROBE_OUT117 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000001110101";
attribute LC_LOW_BIT_POS_PROBE_OUT118 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000001110110";
attribute LC_LOW_BIT_POS_PROBE_OUT119 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000001110111";
attribute LC_LOW_BIT_POS_PROBE_OUT12 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000001100";
attribute LC_LOW_BIT_POS_PROBE_OUT120 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000001111000";
attribute LC_LOW_BIT_POS_PROBE_OUT121 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000001111001";
attribute LC_LOW_BIT_POS_PROBE_OUT122 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000001111010";
attribute LC_LOW_BIT_POS_PROBE_OUT123 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000001111011";
attribute LC_LOW_BIT_POS_PROBE_OUT124 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000001111100";
attribute LC_LOW_BIT_POS_PROBE_OUT125 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000001111101";
attribute LC_LOW_BIT_POS_PROBE_OUT126 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000001111110";
attribute LC_LOW_BIT_POS_PROBE_OUT127 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000001111111";
attribute LC_LOW_BIT_POS_PROBE_OUT128 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010000000";
attribute LC_LOW_BIT_POS_PROBE_OUT129 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010000001";
attribute LC_LOW_BIT_POS_PROBE_OUT13 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000001101";
attribute LC_LOW_BIT_POS_PROBE_OUT130 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010000010";
attribute LC_LOW_BIT_POS_PROBE_OUT131 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010000011";
attribute LC_LOW_BIT_POS_PROBE_OUT132 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010000100";
attribute LC_LOW_BIT_POS_PROBE_OUT133 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010000101";
attribute LC_LOW_BIT_POS_PROBE_OUT134 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010000110";
attribute LC_LOW_BIT_POS_PROBE_OUT135 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010000111";
attribute LC_LOW_BIT_POS_PROBE_OUT136 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010001000";
attribute LC_LOW_BIT_POS_PROBE_OUT137 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010001001";
attribute LC_LOW_BIT_POS_PROBE_OUT138 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010001010";
attribute LC_LOW_BIT_POS_PROBE_OUT139 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010001011";
attribute LC_LOW_BIT_POS_PROBE_OUT14 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000001110";
attribute LC_LOW_BIT_POS_PROBE_OUT140 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010001100";
attribute LC_LOW_BIT_POS_PROBE_OUT141 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010001101";
attribute LC_LOW_BIT_POS_PROBE_OUT142 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010001110";
attribute LC_LOW_BIT_POS_PROBE_OUT143 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010001111";
attribute LC_LOW_BIT_POS_PROBE_OUT144 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010010000";
attribute LC_LOW_BIT_POS_PROBE_OUT145 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010010001";
attribute LC_LOW_BIT_POS_PROBE_OUT146 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010010010";
attribute LC_LOW_BIT_POS_PROBE_OUT147 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010010011";
attribute LC_LOW_BIT_POS_PROBE_OUT148 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010010100";
attribute LC_LOW_BIT_POS_PROBE_OUT149 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010010101";
attribute LC_LOW_BIT_POS_PROBE_OUT15 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000001111";
attribute LC_LOW_BIT_POS_PROBE_OUT150 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010010110";
attribute LC_LOW_BIT_POS_PROBE_OUT151 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010010111";
attribute LC_LOW_BIT_POS_PROBE_OUT152 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010011000";
attribute LC_LOW_BIT_POS_PROBE_OUT153 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010011001";
attribute LC_LOW_BIT_POS_PROBE_OUT154 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010011010";
attribute LC_LOW_BIT_POS_PROBE_OUT155 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000010011011";
attribute LC_LOW_BIT_POS_PROBE_OUT156 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000010011100";
attribute LC_LOW_BIT_POS_PROBE_OUT157 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000010011101";
attribute LC_LOW_BIT_POS_PROBE_OUT158 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000010011110";
attribute LC_LOW_BIT_POS_PROBE_OUT159 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000010011111";
attribute LC_LOW_BIT_POS_PROBE_OUT16 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000010000";
attribute LC_LOW_BIT_POS_PROBE_OUT160 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000010100000";
attribute LC_LOW_BIT_POS_PROBE_OUT161 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000010100001";
attribute LC_LOW_BIT_POS_PROBE_OUT162 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000010100010";
attribute LC_LOW_BIT_POS_PROBE_OUT163 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000010100011";
attribute LC_LOW_BIT_POS_PROBE_OUT164 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000010100100";
attribute LC_LOW_BIT_POS_PROBE_OUT165 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000010100101";
attribute LC_LOW_BIT_POS_PROBE_OUT166 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000010100110";
attribute LC_LOW_BIT_POS_PROBE_OUT167 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000010100111";
attribute LC_LOW_BIT_POS_PROBE_OUT168 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000010101000";
attribute LC_LOW_BIT_POS_PROBE_OUT169 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000010101001";
attribute LC_LOW_BIT_POS_PROBE_OUT17 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000010001";
attribute LC_LOW_BIT_POS_PROBE_OUT170 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000010101010";
attribute LC_LOW_BIT_POS_PROBE_OUT171 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000010101011";
attribute LC_LOW_BIT_POS_PROBE_OUT172 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000010101100";
attribute LC_LOW_BIT_POS_PROBE_OUT173 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000010101101";
attribute LC_LOW_BIT_POS_PROBE_OUT174 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000010101110";
attribute LC_LOW_BIT_POS_PROBE_OUT175 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000010101111";
attribute LC_LOW_BIT_POS_PROBE_OUT176 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000010110000";
attribute LC_LOW_BIT_POS_PROBE_OUT177 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000010110001";
attribute LC_LOW_BIT_POS_PROBE_OUT178 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000010110010";
attribute LC_LOW_BIT_POS_PROBE_OUT179 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000010110011";
attribute LC_LOW_BIT_POS_PROBE_OUT18 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000010010";
attribute LC_LOW_BIT_POS_PROBE_OUT180 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000010110100";
attribute LC_LOW_BIT_POS_PROBE_OUT181 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000010110101";
attribute LC_LOW_BIT_POS_PROBE_OUT182 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000010110110";
attribute LC_LOW_BIT_POS_PROBE_OUT183 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000010110111";
attribute LC_LOW_BIT_POS_PROBE_OUT184 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000010111000";
attribute LC_LOW_BIT_POS_PROBE_OUT185 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000010111001";
attribute LC_LOW_BIT_POS_PROBE_OUT186 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000010111010";
attribute LC_LOW_BIT_POS_PROBE_OUT187 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000010111011";
attribute LC_LOW_BIT_POS_PROBE_OUT188 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000010111100";
attribute LC_LOW_BIT_POS_PROBE_OUT189 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000010111101";
attribute LC_LOW_BIT_POS_PROBE_OUT19 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000010011";
attribute LC_LOW_BIT_POS_PROBE_OUT190 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000010111110";
attribute LC_LOW_BIT_POS_PROBE_OUT191 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000010111111";
attribute LC_LOW_BIT_POS_PROBE_OUT192 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011000000";
attribute LC_LOW_BIT_POS_PROBE_OUT193 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011000001";
attribute LC_LOW_BIT_POS_PROBE_OUT194 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011000010";
attribute LC_LOW_BIT_POS_PROBE_OUT195 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011000011";
attribute LC_LOW_BIT_POS_PROBE_OUT196 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011000100";
attribute LC_LOW_BIT_POS_PROBE_OUT197 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011000101";
attribute LC_LOW_BIT_POS_PROBE_OUT198 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011000110";
attribute LC_LOW_BIT_POS_PROBE_OUT199 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011000111";
attribute LC_LOW_BIT_POS_PROBE_OUT2 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000000010";
attribute LC_LOW_BIT_POS_PROBE_OUT20 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000010100";
attribute LC_LOW_BIT_POS_PROBE_OUT200 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011001000";
attribute LC_LOW_BIT_POS_PROBE_OUT201 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011001001";
attribute LC_LOW_BIT_POS_PROBE_OUT202 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011001010";
attribute LC_LOW_BIT_POS_PROBE_OUT203 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011001011";
attribute LC_LOW_BIT_POS_PROBE_OUT204 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011001100";
attribute LC_LOW_BIT_POS_PROBE_OUT205 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011001101";
attribute LC_LOW_BIT_POS_PROBE_OUT206 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011001110";
attribute LC_LOW_BIT_POS_PROBE_OUT207 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011001111";
attribute LC_LOW_BIT_POS_PROBE_OUT208 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011010000";
attribute LC_LOW_BIT_POS_PROBE_OUT209 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011010001";
attribute LC_LOW_BIT_POS_PROBE_OUT21 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000010101";
attribute LC_LOW_BIT_POS_PROBE_OUT210 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011010010";
attribute LC_LOW_BIT_POS_PROBE_OUT211 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011010011";
attribute LC_LOW_BIT_POS_PROBE_OUT212 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011010100";
attribute LC_LOW_BIT_POS_PROBE_OUT213 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011010101";
attribute LC_LOW_BIT_POS_PROBE_OUT214 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011010110";
attribute LC_LOW_BIT_POS_PROBE_OUT215 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011010111";
attribute LC_LOW_BIT_POS_PROBE_OUT216 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011011000";
attribute LC_LOW_BIT_POS_PROBE_OUT217 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011011001";
attribute LC_LOW_BIT_POS_PROBE_OUT218 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011011010";
attribute LC_LOW_BIT_POS_PROBE_OUT219 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000011011011";
attribute LC_LOW_BIT_POS_PROBE_OUT22 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000010110";
attribute LC_LOW_BIT_POS_PROBE_OUT220 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000011011100";
attribute LC_LOW_BIT_POS_PROBE_OUT221 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000011011101";
attribute LC_LOW_BIT_POS_PROBE_OUT222 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000011011110";
attribute LC_LOW_BIT_POS_PROBE_OUT223 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000011011111";
attribute LC_LOW_BIT_POS_PROBE_OUT224 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000011100000";
attribute LC_LOW_BIT_POS_PROBE_OUT225 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000011100001";
attribute LC_LOW_BIT_POS_PROBE_OUT226 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000011100010";
attribute LC_LOW_BIT_POS_PROBE_OUT227 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000011100011";
attribute LC_LOW_BIT_POS_PROBE_OUT228 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000011100100";
attribute LC_LOW_BIT_POS_PROBE_OUT229 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000011100101";
attribute LC_LOW_BIT_POS_PROBE_OUT23 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000010111";
attribute LC_LOW_BIT_POS_PROBE_OUT230 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000011100110";
attribute LC_LOW_BIT_POS_PROBE_OUT231 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000011100111";
attribute LC_LOW_BIT_POS_PROBE_OUT232 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000011101000";
attribute LC_LOW_BIT_POS_PROBE_OUT233 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000011101001";
attribute LC_LOW_BIT_POS_PROBE_OUT234 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000011101010";
attribute LC_LOW_BIT_POS_PROBE_OUT235 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000011101011";
attribute LC_LOW_BIT_POS_PROBE_OUT236 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000011101100";
attribute LC_LOW_BIT_POS_PROBE_OUT237 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000011101101";
attribute LC_LOW_BIT_POS_PROBE_OUT238 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000011101110";
attribute LC_LOW_BIT_POS_PROBE_OUT239 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000011101111";
attribute LC_LOW_BIT_POS_PROBE_OUT24 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000011000";
attribute LC_LOW_BIT_POS_PROBE_OUT240 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000011110000";
attribute LC_LOW_BIT_POS_PROBE_OUT241 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000011110001";
attribute LC_LOW_BIT_POS_PROBE_OUT242 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000011110010";
attribute LC_LOW_BIT_POS_PROBE_OUT243 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000011110011";
attribute LC_LOW_BIT_POS_PROBE_OUT244 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000011110100";
attribute LC_LOW_BIT_POS_PROBE_OUT245 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000011110101";
attribute LC_LOW_BIT_POS_PROBE_OUT246 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000011110110";
attribute LC_LOW_BIT_POS_PROBE_OUT247 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000011110111";
attribute LC_LOW_BIT_POS_PROBE_OUT248 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000011111000";
attribute LC_LOW_BIT_POS_PROBE_OUT249 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000011111001";
attribute LC_LOW_BIT_POS_PROBE_OUT25 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000011001";
attribute LC_LOW_BIT_POS_PROBE_OUT250 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000011111010";
attribute LC_LOW_BIT_POS_PROBE_OUT251 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000011111011";
attribute LC_LOW_BIT_POS_PROBE_OUT252 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000011111100";
attribute LC_LOW_BIT_POS_PROBE_OUT253 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000011111101";
attribute LC_LOW_BIT_POS_PROBE_OUT254 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000011111110";
attribute LC_LOW_BIT_POS_PROBE_OUT255 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000011111111";
attribute LC_LOW_BIT_POS_PROBE_OUT26 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000011010";
attribute LC_LOW_BIT_POS_PROBE_OUT27 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000000011011";
attribute LC_LOW_BIT_POS_PROBE_OUT28 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000000011100";
attribute LC_LOW_BIT_POS_PROBE_OUT29 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000000011101";
attribute LC_LOW_BIT_POS_PROBE_OUT3 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000000011";
attribute LC_LOW_BIT_POS_PROBE_OUT30 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000000011110";
attribute LC_LOW_BIT_POS_PROBE_OUT31 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000000011111";
attribute LC_LOW_BIT_POS_PROBE_OUT32 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000000100000";
attribute LC_LOW_BIT_POS_PROBE_OUT33 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000000100001";
attribute LC_LOW_BIT_POS_PROBE_OUT34 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000000100010";
attribute LC_LOW_BIT_POS_PROBE_OUT35 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000000100011";
attribute LC_LOW_BIT_POS_PROBE_OUT36 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000000100100";
attribute LC_LOW_BIT_POS_PROBE_OUT37 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000000100101";
attribute LC_LOW_BIT_POS_PROBE_OUT38 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000000100110";
attribute LC_LOW_BIT_POS_PROBE_OUT39 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000000100111";
attribute LC_LOW_BIT_POS_PROBE_OUT4 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000000100";
attribute LC_LOW_BIT_POS_PROBE_OUT40 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000000101000";
attribute LC_LOW_BIT_POS_PROBE_OUT41 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000000101001";
attribute LC_LOW_BIT_POS_PROBE_OUT42 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000000101010";
attribute LC_LOW_BIT_POS_PROBE_OUT43 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000000101011";
attribute LC_LOW_BIT_POS_PROBE_OUT44 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000000101100";
attribute LC_LOW_BIT_POS_PROBE_OUT45 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000000101101";
attribute LC_LOW_BIT_POS_PROBE_OUT46 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000000101110";
attribute LC_LOW_BIT_POS_PROBE_OUT47 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000000101111";
attribute LC_LOW_BIT_POS_PROBE_OUT48 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000000110000";
attribute LC_LOW_BIT_POS_PROBE_OUT49 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000000110001";
attribute LC_LOW_BIT_POS_PROBE_OUT5 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000000101";
attribute LC_LOW_BIT_POS_PROBE_OUT50 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000000110010";
attribute LC_LOW_BIT_POS_PROBE_OUT51 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000000110011";
attribute LC_LOW_BIT_POS_PROBE_OUT52 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000000110100";
attribute LC_LOW_BIT_POS_PROBE_OUT53 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000000110101";
attribute LC_LOW_BIT_POS_PROBE_OUT54 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000000110110";
attribute LC_LOW_BIT_POS_PROBE_OUT55 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000000110111";
attribute LC_LOW_BIT_POS_PROBE_OUT56 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000000111000";
attribute LC_LOW_BIT_POS_PROBE_OUT57 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000000111001";
attribute LC_LOW_BIT_POS_PROBE_OUT58 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000000111010";
attribute LC_LOW_BIT_POS_PROBE_OUT59 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000000111011";
attribute LC_LOW_BIT_POS_PROBE_OUT6 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000000110";
attribute LC_LOW_BIT_POS_PROBE_OUT60 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000000111100";
attribute LC_LOW_BIT_POS_PROBE_OUT61 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000000111101";
attribute LC_LOW_BIT_POS_PROBE_OUT62 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000000111110";
attribute LC_LOW_BIT_POS_PROBE_OUT63 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000000111111";
attribute LC_LOW_BIT_POS_PROBE_OUT64 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001000000";
attribute LC_LOW_BIT_POS_PROBE_OUT65 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001000001";
attribute LC_LOW_BIT_POS_PROBE_OUT66 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001000010";
attribute LC_LOW_BIT_POS_PROBE_OUT67 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001000011";
attribute LC_LOW_BIT_POS_PROBE_OUT68 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001000100";
attribute LC_LOW_BIT_POS_PROBE_OUT69 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001000101";
attribute LC_LOW_BIT_POS_PROBE_OUT7 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000000111";
attribute LC_LOW_BIT_POS_PROBE_OUT70 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001000110";
attribute LC_LOW_BIT_POS_PROBE_OUT71 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001000111";
attribute LC_LOW_BIT_POS_PROBE_OUT72 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001001000";
attribute LC_LOW_BIT_POS_PROBE_OUT73 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001001001";
attribute LC_LOW_BIT_POS_PROBE_OUT74 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001001010";
attribute LC_LOW_BIT_POS_PROBE_OUT75 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001001011";
attribute LC_LOW_BIT_POS_PROBE_OUT76 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001001100";
attribute LC_LOW_BIT_POS_PROBE_OUT77 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001001101";
attribute LC_LOW_BIT_POS_PROBE_OUT78 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001001110";
attribute LC_LOW_BIT_POS_PROBE_OUT79 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001001111";
attribute LC_LOW_BIT_POS_PROBE_OUT8 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000001000";
attribute LC_LOW_BIT_POS_PROBE_OUT80 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001010000";
attribute LC_LOW_BIT_POS_PROBE_OUT81 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001010001";
attribute LC_LOW_BIT_POS_PROBE_OUT82 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001010010";
attribute LC_LOW_BIT_POS_PROBE_OUT83 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001010011";
attribute LC_LOW_BIT_POS_PROBE_OUT84 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001010100";
attribute LC_LOW_BIT_POS_PROBE_OUT85 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001010101";
attribute LC_LOW_BIT_POS_PROBE_OUT86 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001010110";
attribute LC_LOW_BIT_POS_PROBE_OUT87 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001010111";
attribute LC_LOW_BIT_POS_PROBE_OUT88 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001011000";
attribute LC_LOW_BIT_POS_PROBE_OUT89 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001011001";
attribute LC_LOW_BIT_POS_PROBE_OUT9 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000001001";
attribute LC_LOW_BIT_POS_PROBE_OUT90 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001011010";
attribute LC_LOW_BIT_POS_PROBE_OUT91 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000001011011";
attribute LC_LOW_BIT_POS_PROBE_OUT92 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000001011100";
attribute LC_LOW_BIT_POS_PROBE_OUT93 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000001011101";
attribute LC_LOW_BIT_POS_PROBE_OUT94 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000001011110";
attribute LC_LOW_BIT_POS_PROBE_OUT95 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000001011111";
attribute LC_LOW_BIT_POS_PROBE_OUT96 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000001100000";
attribute LC_LOW_BIT_POS_PROBE_OUT97 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000001100001";
attribute LC_LOW_BIT_POS_PROBE_OUT98 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000001100010";
attribute LC_LOW_BIT_POS_PROBE_OUT99 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000001100011";
attribute LC_PROBE_IN_WIDTH_STRING : string;
attribute LC_PROBE_IN_WIDTH_STRING of inst : label is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING of inst : label is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_INIT_VAL_STRING : string;
attribute LC_PROBE_OUT_INIT_VAL_STRING of inst : label is "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING of inst : label is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_WIDTH_STRING : string;
attribute LC_PROBE_OUT_WIDTH_STRING of inst : label is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_TOTAL_PROBE_IN_WIDTH : integer;
attribute LC_TOTAL_PROBE_IN_WIDTH of inst : label is 4;
attribute LC_TOTAL_PROBE_OUT_WIDTH : integer;
attribute LC_TOTAL_PROBE_OUT_WIDTH of inst : label is 0;
attribute syn_noprune : string;
attribute syn_noprune of inst : label is "1";
begin
inst: entity work.vio_0_vio_v3_0_13_vio
port map (
clk => clk,
probe_in0(0) => probe_in0(0),
probe_in1(0) => probe_in1(0),
probe_in10(0) => '0',
probe_in100(0) => '0',
probe_in101(0) => '0',
probe_in102(0) => '0',
probe_in103(0) => '0',
probe_in104(0) => '0',
probe_in105(0) => '0',
probe_in106(0) => '0',
probe_in107(0) => '0',
probe_in108(0) => '0',
probe_in109(0) => '0',
probe_in11(0) => '0',
probe_in110(0) => '0',
probe_in111(0) => '0',
probe_in112(0) => '0',
probe_in113(0) => '0',
probe_in114(0) => '0',
probe_in115(0) => '0',
probe_in116(0) => '0',
probe_in117(0) => '0',
probe_in118(0) => '0',
probe_in119(0) => '0',
probe_in12(0) => '0',
probe_in120(0) => '0',
probe_in121(0) => '0',
probe_in122(0) => '0',
probe_in123(0) => '0',
probe_in124(0) => '0',
probe_in125(0) => '0',
probe_in126(0) => '0',
probe_in127(0) => '0',
probe_in128(0) => '0',
probe_in129(0) => '0',
probe_in13(0) => '0',
probe_in130(0) => '0',
probe_in131(0) => '0',
probe_in132(0) => '0',
probe_in133(0) => '0',
probe_in134(0) => '0',
probe_in135(0) => '0',
probe_in136(0) => '0',
probe_in137(0) => '0',
probe_in138(0) => '0',
probe_in139(0) => '0',
probe_in14(0) => '0',
probe_in140(0) => '0',
probe_in141(0) => '0',
probe_in142(0) => '0',
probe_in143(0) => '0',
probe_in144(0) => '0',
probe_in145(0) => '0',
probe_in146(0) => '0',
probe_in147(0) => '0',
probe_in148(0) => '0',
probe_in149(0) => '0',
probe_in15(0) => '0',
probe_in150(0) => '0',
probe_in151(0) => '0',
probe_in152(0) => '0',
probe_in153(0) => '0',
probe_in154(0) => '0',
probe_in155(0) => '0',
probe_in156(0) => '0',
probe_in157(0) => '0',
probe_in158(0) => '0',
probe_in159(0) => '0',
probe_in16(0) => '0',
probe_in160(0) => '0',
probe_in161(0) => '0',
probe_in162(0) => '0',
probe_in163(0) => '0',
probe_in164(0) => '0',
probe_in165(0) => '0',
probe_in166(0) => '0',
probe_in167(0) => '0',
probe_in168(0) => '0',
probe_in169(0) => '0',
probe_in17(0) => '0',
probe_in170(0) => '0',
probe_in171(0) => '0',
probe_in172(0) => '0',
probe_in173(0) => '0',
probe_in174(0) => '0',
probe_in175(0) => '0',
probe_in176(0) => '0',
probe_in177(0) => '0',
probe_in178(0) => '0',
probe_in179(0) => '0',
probe_in18(0) => '0',
probe_in180(0) => '0',
probe_in181(0) => '0',
probe_in182(0) => '0',
probe_in183(0) => '0',
probe_in184(0) => '0',
probe_in185(0) => '0',
probe_in186(0) => '0',
probe_in187(0) => '0',
probe_in188(0) => '0',
probe_in189(0) => '0',
probe_in19(0) => '0',
probe_in190(0) => '0',
probe_in191(0) => '0',
probe_in192(0) => '0',
probe_in193(0) => '0',
probe_in194(0) => '0',
probe_in195(0) => '0',
probe_in196(0) => '0',
probe_in197(0) => '0',
probe_in198(0) => '0',
probe_in199(0) => '0',
probe_in2(0) => probe_in2(0),
probe_in20(0) => '0',
probe_in200(0) => '0',
probe_in201(0) => '0',
probe_in202(0) => '0',
probe_in203(0) => '0',
probe_in204(0) => '0',
probe_in205(0) => '0',
probe_in206(0) => '0',
probe_in207(0) => '0',
probe_in208(0) => '0',
probe_in209(0) => '0',
probe_in21(0) => '0',
probe_in210(0) => '0',
probe_in211(0) => '0',
probe_in212(0) => '0',
probe_in213(0) => '0',
probe_in214(0) => '0',
probe_in215(0) => '0',
probe_in216(0) => '0',
probe_in217(0) => '0',
probe_in218(0) => '0',
probe_in219(0) => '0',
probe_in22(0) => '0',
probe_in220(0) => '0',
probe_in221(0) => '0',
probe_in222(0) => '0',
probe_in223(0) => '0',
probe_in224(0) => '0',
probe_in225(0) => '0',
probe_in226(0) => '0',
probe_in227(0) => '0',
probe_in228(0) => '0',
probe_in229(0) => '0',
probe_in23(0) => '0',
probe_in230(0) => '0',
probe_in231(0) => '0',
probe_in232(0) => '0',
probe_in233(0) => '0',
probe_in234(0) => '0',
probe_in235(0) => '0',
probe_in236(0) => '0',
probe_in237(0) => '0',
probe_in238(0) => '0',
probe_in239(0) => '0',
probe_in24(0) => '0',
probe_in240(0) => '0',
probe_in241(0) => '0',
probe_in242(0) => '0',
probe_in243(0) => '0',
probe_in244(0) => '0',
probe_in245(0) => '0',
probe_in246(0) => '0',
probe_in247(0) => '0',
probe_in248(0) => '0',
probe_in249(0) => '0',
probe_in25(0) => '0',
probe_in250(0) => '0',
probe_in251(0) => '0',
probe_in252(0) => '0',
probe_in253(0) => '0',
probe_in254(0) => '0',
probe_in255(0) => '0',
probe_in26(0) => '0',
probe_in27(0) => '0',
probe_in28(0) => '0',
probe_in29(0) => '0',
probe_in3(0) => probe_in3(0),
probe_in30(0) => '0',
probe_in31(0) => '0',
probe_in32(0) => '0',
probe_in33(0) => '0',
probe_in34(0) => '0',
probe_in35(0) => '0',
probe_in36(0) => '0',
probe_in37(0) => '0',
probe_in38(0) => '0',
probe_in39(0) => '0',
probe_in4(0) => '0',
probe_in40(0) => '0',
probe_in41(0) => '0',
probe_in42(0) => '0',
probe_in43(0) => '0',
probe_in44(0) => '0',
probe_in45(0) => '0',
probe_in46(0) => '0',
probe_in47(0) => '0',
probe_in48(0) => '0',
probe_in49(0) => '0',
probe_in5(0) => '0',
probe_in50(0) => '0',
probe_in51(0) => '0',
probe_in52(0) => '0',
probe_in53(0) => '0',
probe_in54(0) => '0',
probe_in55(0) => '0',
probe_in56(0) => '0',
probe_in57(0) => '0',
probe_in58(0) => '0',
probe_in59(0) => '0',
probe_in6(0) => '0',
probe_in60(0) => '0',
probe_in61(0) => '0',
probe_in62(0) => '0',
probe_in63(0) => '0',
probe_in64(0) => '0',
probe_in65(0) => '0',
probe_in66(0) => '0',
probe_in67(0) => '0',
probe_in68(0) => '0',
probe_in69(0) => '0',
probe_in7(0) => '0',
probe_in70(0) => '0',
probe_in71(0) => '0',
probe_in72(0) => '0',
probe_in73(0) => '0',
probe_in74(0) => '0',
probe_in75(0) => '0',
probe_in76(0) => '0',
probe_in77(0) => '0',
probe_in78(0) => '0',
probe_in79(0) => '0',
probe_in8(0) => '0',
probe_in80(0) => '0',
probe_in81(0) => '0',
probe_in82(0) => '0',
probe_in83(0) => '0',
probe_in84(0) => '0',
probe_in85(0) => '0',
probe_in86(0) => '0',
probe_in87(0) => '0',
probe_in88(0) => '0',
probe_in89(0) => '0',
probe_in9(0) => '0',
probe_in90(0) => '0',
probe_in91(0) => '0',
probe_in92(0) => '0',
probe_in93(0) => '0',
probe_in94(0) => '0',
probe_in95(0) => '0',
probe_in96(0) => '0',
probe_in97(0) => '0',
probe_in98(0) => '0',
probe_in99(0) => '0',
probe_out0(0) => NLW_inst_probe_out0_UNCONNECTED(0),
probe_out1(0) => NLW_inst_probe_out1_UNCONNECTED(0),
probe_out10(0) => NLW_inst_probe_out10_UNCONNECTED(0),
probe_out100(0) => NLW_inst_probe_out100_UNCONNECTED(0),
probe_out101(0) => NLW_inst_probe_out101_UNCONNECTED(0),
probe_out102(0) => NLW_inst_probe_out102_UNCONNECTED(0),
probe_out103(0) => NLW_inst_probe_out103_UNCONNECTED(0),
probe_out104(0) => NLW_inst_probe_out104_UNCONNECTED(0),
probe_out105(0) => NLW_inst_probe_out105_UNCONNECTED(0),
probe_out106(0) => NLW_inst_probe_out106_UNCONNECTED(0),
probe_out107(0) => NLW_inst_probe_out107_UNCONNECTED(0),
probe_out108(0) => NLW_inst_probe_out108_UNCONNECTED(0),
probe_out109(0) => NLW_inst_probe_out109_UNCONNECTED(0),
probe_out11(0) => NLW_inst_probe_out11_UNCONNECTED(0),
probe_out110(0) => NLW_inst_probe_out110_UNCONNECTED(0),
probe_out111(0) => NLW_inst_probe_out111_UNCONNECTED(0),
probe_out112(0) => NLW_inst_probe_out112_UNCONNECTED(0),
probe_out113(0) => NLW_inst_probe_out113_UNCONNECTED(0),
probe_out114(0) => NLW_inst_probe_out114_UNCONNECTED(0),
probe_out115(0) => NLW_inst_probe_out115_UNCONNECTED(0),
probe_out116(0) => NLW_inst_probe_out116_UNCONNECTED(0),
probe_out117(0) => NLW_inst_probe_out117_UNCONNECTED(0),
probe_out118(0) => NLW_inst_probe_out118_UNCONNECTED(0),
probe_out119(0) => NLW_inst_probe_out119_UNCONNECTED(0),
probe_out12(0) => NLW_inst_probe_out12_UNCONNECTED(0),
probe_out120(0) => NLW_inst_probe_out120_UNCONNECTED(0),
probe_out121(0) => NLW_inst_probe_out121_UNCONNECTED(0),
probe_out122(0) => NLW_inst_probe_out122_UNCONNECTED(0),
probe_out123(0) => NLW_inst_probe_out123_UNCONNECTED(0),
probe_out124(0) => NLW_inst_probe_out124_UNCONNECTED(0),
probe_out125(0) => NLW_inst_probe_out125_UNCONNECTED(0),
probe_out126(0) => NLW_inst_probe_out126_UNCONNECTED(0),
probe_out127(0) => NLW_inst_probe_out127_UNCONNECTED(0),
probe_out128(0) => NLW_inst_probe_out128_UNCONNECTED(0),
probe_out129(0) => NLW_inst_probe_out129_UNCONNECTED(0),
probe_out13(0) => NLW_inst_probe_out13_UNCONNECTED(0),
probe_out130(0) => NLW_inst_probe_out130_UNCONNECTED(0),
probe_out131(0) => NLW_inst_probe_out131_UNCONNECTED(0),
probe_out132(0) => NLW_inst_probe_out132_UNCONNECTED(0),
probe_out133(0) => NLW_inst_probe_out133_UNCONNECTED(0),
probe_out134(0) => NLW_inst_probe_out134_UNCONNECTED(0),
probe_out135(0) => NLW_inst_probe_out135_UNCONNECTED(0),
probe_out136(0) => NLW_inst_probe_out136_UNCONNECTED(0),
probe_out137(0) => NLW_inst_probe_out137_UNCONNECTED(0),
probe_out138(0) => NLW_inst_probe_out138_UNCONNECTED(0),
probe_out139(0) => NLW_inst_probe_out139_UNCONNECTED(0),
probe_out14(0) => NLW_inst_probe_out14_UNCONNECTED(0),
probe_out140(0) => NLW_inst_probe_out140_UNCONNECTED(0),
probe_out141(0) => NLW_inst_probe_out141_UNCONNECTED(0),
probe_out142(0) => NLW_inst_probe_out142_UNCONNECTED(0),
probe_out143(0) => NLW_inst_probe_out143_UNCONNECTED(0),
probe_out144(0) => NLW_inst_probe_out144_UNCONNECTED(0),
probe_out145(0) => NLW_inst_probe_out145_UNCONNECTED(0),
probe_out146(0) => NLW_inst_probe_out146_UNCONNECTED(0),
probe_out147(0) => NLW_inst_probe_out147_UNCONNECTED(0),
probe_out148(0) => NLW_inst_probe_out148_UNCONNECTED(0),
probe_out149(0) => NLW_inst_probe_out149_UNCONNECTED(0),
probe_out15(0) => NLW_inst_probe_out15_UNCONNECTED(0),
probe_out150(0) => NLW_inst_probe_out150_UNCONNECTED(0),
probe_out151(0) => NLW_inst_probe_out151_UNCONNECTED(0),
probe_out152(0) => NLW_inst_probe_out152_UNCONNECTED(0),
probe_out153(0) => NLW_inst_probe_out153_UNCONNECTED(0),
probe_out154(0) => NLW_inst_probe_out154_UNCONNECTED(0),
probe_out155(0) => NLW_inst_probe_out155_UNCONNECTED(0),
probe_out156(0) => NLW_inst_probe_out156_UNCONNECTED(0),
probe_out157(0) => NLW_inst_probe_out157_UNCONNECTED(0),
probe_out158(0) => NLW_inst_probe_out158_UNCONNECTED(0),
probe_out159(0) => NLW_inst_probe_out159_UNCONNECTED(0),
probe_out16(0) => NLW_inst_probe_out16_UNCONNECTED(0),
probe_out160(0) => NLW_inst_probe_out160_UNCONNECTED(0),
probe_out161(0) => NLW_inst_probe_out161_UNCONNECTED(0),
probe_out162(0) => NLW_inst_probe_out162_UNCONNECTED(0),
probe_out163(0) => NLW_inst_probe_out163_UNCONNECTED(0),
probe_out164(0) => NLW_inst_probe_out164_UNCONNECTED(0),
probe_out165(0) => NLW_inst_probe_out165_UNCONNECTED(0),
probe_out166(0) => NLW_inst_probe_out166_UNCONNECTED(0),
probe_out167(0) => NLW_inst_probe_out167_UNCONNECTED(0),
probe_out168(0) => NLW_inst_probe_out168_UNCONNECTED(0),
probe_out169(0) => NLW_inst_probe_out169_UNCONNECTED(0),
probe_out17(0) => NLW_inst_probe_out17_UNCONNECTED(0),
probe_out170(0) => NLW_inst_probe_out170_UNCONNECTED(0),
probe_out171(0) => NLW_inst_probe_out171_UNCONNECTED(0),
probe_out172(0) => NLW_inst_probe_out172_UNCONNECTED(0),
probe_out173(0) => NLW_inst_probe_out173_UNCONNECTED(0),
probe_out174(0) => NLW_inst_probe_out174_UNCONNECTED(0),
probe_out175(0) => NLW_inst_probe_out175_UNCONNECTED(0),
probe_out176(0) => NLW_inst_probe_out176_UNCONNECTED(0),
probe_out177(0) => NLW_inst_probe_out177_UNCONNECTED(0),
probe_out178(0) => NLW_inst_probe_out178_UNCONNECTED(0),
probe_out179(0) => NLW_inst_probe_out179_UNCONNECTED(0),
probe_out18(0) => NLW_inst_probe_out18_UNCONNECTED(0),
probe_out180(0) => NLW_inst_probe_out180_UNCONNECTED(0),
probe_out181(0) => NLW_inst_probe_out181_UNCONNECTED(0),
probe_out182(0) => NLW_inst_probe_out182_UNCONNECTED(0),
probe_out183(0) => NLW_inst_probe_out183_UNCONNECTED(0),
probe_out184(0) => NLW_inst_probe_out184_UNCONNECTED(0),
probe_out185(0) => NLW_inst_probe_out185_UNCONNECTED(0),
probe_out186(0) => NLW_inst_probe_out186_UNCONNECTED(0),
probe_out187(0) => NLW_inst_probe_out187_UNCONNECTED(0),
probe_out188(0) => NLW_inst_probe_out188_UNCONNECTED(0),
probe_out189(0) => NLW_inst_probe_out189_UNCONNECTED(0),
probe_out19(0) => NLW_inst_probe_out19_UNCONNECTED(0),
probe_out190(0) => NLW_inst_probe_out190_UNCONNECTED(0),
probe_out191(0) => NLW_inst_probe_out191_UNCONNECTED(0),
probe_out192(0) => NLW_inst_probe_out192_UNCONNECTED(0),
probe_out193(0) => NLW_inst_probe_out193_UNCONNECTED(0),
probe_out194(0) => NLW_inst_probe_out194_UNCONNECTED(0),
probe_out195(0) => NLW_inst_probe_out195_UNCONNECTED(0),
probe_out196(0) => NLW_inst_probe_out196_UNCONNECTED(0),
probe_out197(0) => NLW_inst_probe_out197_UNCONNECTED(0),
probe_out198(0) => NLW_inst_probe_out198_UNCONNECTED(0),
probe_out199(0) => NLW_inst_probe_out199_UNCONNECTED(0),
probe_out2(0) => NLW_inst_probe_out2_UNCONNECTED(0),
probe_out20(0) => NLW_inst_probe_out20_UNCONNECTED(0),
probe_out200(0) => NLW_inst_probe_out200_UNCONNECTED(0),
probe_out201(0) => NLW_inst_probe_out201_UNCONNECTED(0),
probe_out202(0) => NLW_inst_probe_out202_UNCONNECTED(0),
probe_out203(0) => NLW_inst_probe_out203_UNCONNECTED(0),
probe_out204(0) => NLW_inst_probe_out204_UNCONNECTED(0),
probe_out205(0) => NLW_inst_probe_out205_UNCONNECTED(0),
probe_out206(0) => NLW_inst_probe_out206_UNCONNECTED(0),
probe_out207(0) => NLW_inst_probe_out207_UNCONNECTED(0),
probe_out208(0) => NLW_inst_probe_out208_UNCONNECTED(0),
probe_out209(0) => NLW_inst_probe_out209_UNCONNECTED(0),
probe_out21(0) => NLW_inst_probe_out21_UNCONNECTED(0),
probe_out210(0) => NLW_inst_probe_out210_UNCONNECTED(0),
probe_out211(0) => NLW_inst_probe_out211_UNCONNECTED(0),
probe_out212(0) => NLW_inst_probe_out212_UNCONNECTED(0),
probe_out213(0) => NLW_inst_probe_out213_UNCONNECTED(0),
probe_out214(0) => NLW_inst_probe_out214_UNCONNECTED(0),
probe_out215(0) => NLW_inst_probe_out215_UNCONNECTED(0),
probe_out216(0) => NLW_inst_probe_out216_UNCONNECTED(0),
probe_out217(0) => NLW_inst_probe_out217_UNCONNECTED(0),
probe_out218(0) => NLW_inst_probe_out218_UNCONNECTED(0),
probe_out219(0) => NLW_inst_probe_out219_UNCONNECTED(0),
probe_out22(0) => NLW_inst_probe_out22_UNCONNECTED(0),
probe_out220(0) => NLW_inst_probe_out220_UNCONNECTED(0),
probe_out221(0) => NLW_inst_probe_out221_UNCONNECTED(0),
probe_out222(0) => NLW_inst_probe_out222_UNCONNECTED(0),
probe_out223(0) => NLW_inst_probe_out223_UNCONNECTED(0),
probe_out224(0) => NLW_inst_probe_out224_UNCONNECTED(0),
probe_out225(0) => NLW_inst_probe_out225_UNCONNECTED(0),
probe_out226(0) => NLW_inst_probe_out226_UNCONNECTED(0),
probe_out227(0) => NLW_inst_probe_out227_UNCONNECTED(0),
probe_out228(0) => NLW_inst_probe_out228_UNCONNECTED(0),
probe_out229(0) => NLW_inst_probe_out229_UNCONNECTED(0),
probe_out23(0) => NLW_inst_probe_out23_UNCONNECTED(0),
probe_out230(0) => NLW_inst_probe_out230_UNCONNECTED(0),
probe_out231(0) => NLW_inst_probe_out231_UNCONNECTED(0),
probe_out232(0) => NLW_inst_probe_out232_UNCONNECTED(0),
probe_out233(0) => NLW_inst_probe_out233_UNCONNECTED(0),
probe_out234(0) => NLW_inst_probe_out234_UNCONNECTED(0),
probe_out235(0) => NLW_inst_probe_out235_UNCONNECTED(0),
probe_out236(0) => NLW_inst_probe_out236_UNCONNECTED(0),
probe_out237(0) => NLW_inst_probe_out237_UNCONNECTED(0),
probe_out238(0) => NLW_inst_probe_out238_UNCONNECTED(0),
probe_out239(0) => NLW_inst_probe_out239_UNCONNECTED(0),
probe_out24(0) => NLW_inst_probe_out24_UNCONNECTED(0),
probe_out240(0) => NLW_inst_probe_out240_UNCONNECTED(0),
probe_out241(0) => NLW_inst_probe_out241_UNCONNECTED(0),
probe_out242(0) => NLW_inst_probe_out242_UNCONNECTED(0),
probe_out243(0) => NLW_inst_probe_out243_UNCONNECTED(0),
probe_out244(0) => NLW_inst_probe_out244_UNCONNECTED(0),
probe_out245(0) => NLW_inst_probe_out245_UNCONNECTED(0),
probe_out246(0) => NLW_inst_probe_out246_UNCONNECTED(0),
probe_out247(0) => NLW_inst_probe_out247_UNCONNECTED(0),
probe_out248(0) => NLW_inst_probe_out248_UNCONNECTED(0),
probe_out249(0) => NLW_inst_probe_out249_UNCONNECTED(0),
probe_out25(0) => NLW_inst_probe_out25_UNCONNECTED(0),
probe_out250(0) => NLW_inst_probe_out250_UNCONNECTED(0),
probe_out251(0) => NLW_inst_probe_out251_UNCONNECTED(0),
probe_out252(0) => NLW_inst_probe_out252_UNCONNECTED(0),
probe_out253(0) => NLW_inst_probe_out253_UNCONNECTED(0),
probe_out254(0) => NLW_inst_probe_out254_UNCONNECTED(0),
probe_out255(0) => NLW_inst_probe_out255_UNCONNECTED(0),
probe_out26(0) => NLW_inst_probe_out26_UNCONNECTED(0),
probe_out27(0) => NLW_inst_probe_out27_UNCONNECTED(0),
probe_out28(0) => NLW_inst_probe_out28_UNCONNECTED(0),
probe_out29(0) => NLW_inst_probe_out29_UNCONNECTED(0),
probe_out3(0) => NLW_inst_probe_out3_UNCONNECTED(0),
probe_out30(0) => NLW_inst_probe_out30_UNCONNECTED(0),
probe_out31(0) => NLW_inst_probe_out31_UNCONNECTED(0),
probe_out32(0) => NLW_inst_probe_out32_UNCONNECTED(0),
probe_out33(0) => NLW_inst_probe_out33_UNCONNECTED(0),
probe_out34(0) => NLW_inst_probe_out34_UNCONNECTED(0),
probe_out35(0) => NLW_inst_probe_out35_UNCONNECTED(0),
probe_out36(0) => NLW_inst_probe_out36_UNCONNECTED(0),
probe_out37(0) => NLW_inst_probe_out37_UNCONNECTED(0),
probe_out38(0) => NLW_inst_probe_out38_UNCONNECTED(0),
probe_out39(0) => NLW_inst_probe_out39_UNCONNECTED(0),
probe_out4(0) => NLW_inst_probe_out4_UNCONNECTED(0),
probe_out40(0) => NLW_inst_probe_out40_UNCONNECTED(0),
probe_out41(0) => NLW_inst_probe_out41_UNCONNECTED(0),
probe_out42(0) => NLW_inst_probe_out42_UNCONNECTED(0),
probe_out43(0) => NLW_inst_probe_out43_UNCONNECTED(0),
probe_out44(0) => NLW_inst_probe_out44_UNCONNECTED(0),
probe_out45(0) => NLW_inst_probe_out45_UNCONNECTED(0),
probe_out46(0) => NLW_inst_probe_out46_UNCONNECTED(0),
probe_out47(0) => NLW_inst_probe_out47_UNCONNECTED(0),
probe_out48(0) => NLW_inst_probe_out48_UNCONNECTED(0),
probe_out49(0) => NLW_inst_probe_out49_UNCONNECTED(0),
probe_out5(0) => NLW_inst_probe_out5_UNCONNECTED(0),
probe_out50(0) => NLW_inst_probe_out50_UNCONNECTED(0),
probe_out51(0) => NLW_inst_probe_out51_UNCONNECTED(0),
probe_out52(0) => NLW_inst_probe_out52_UNCONNECTED(0),
probe_out53(0) => NLW_inst_probe_out53_UNCONNECTED(0),
probe_out54(0) => NLW_inst_probe_out54_UNCONNECTED(0),
probe_out55(0) => NLW_inst_probe_out55_UNCONNECTED(0),
probe_out56(0) => NLW_inst_probe_out56_UNCONNECTED(0),
probe_out57(0) => NLW_inst_probe_out57_UNCONNECTED(0),
probe_out58(0) => NLW_inst_probe_out58_UNCONNECTED(0),
probe_out59(0) => NLW_inst_probe_out59_UNCONNECTED(0),
probe_out6(0) => NLW_inst_probe_out6_UNCONNECTED(0),
probe_out60(0) => NLW_inst_probe_out60_UNCONNECTED(0),
probe_out61(0) => NLW_inst_probe_out61_UNCONNECTED(0),
probe_out62(0) => NLW_inst_probe_out62_UNCONNECTED(0),
probe_out63(0) => NLW_inst_probe_out63_UNCONNECTED(0),
probe_out64(0) => NLW_inst_probe_out64_UNCONNECTED(0),
probe_out65(0) => NLW_inst_probe_out65_UNCONNECTED(0),
probe_out66(0) => NLW_inst_probe_out66_UNCONNECTED(0),
probe_out67(0) => NLW_inst_probe_out67_UNCONNECTED(0),
probe_out68(0) => NLW_inst_probe_out68_UNCONNECTED(0),
probe_out69(0) => NLW_inst_probe_out69_UNCONNECTED(0),
probe_out7(0) => NLW_inst_probe_out7_UNCONNECTED(0),
probe_out70(0) => NLW_inst_probe_out70_UNCONNECTED(0),
probe_out71(0) => NLW_inst_probe_out71_UNCONNECTED(0),
probe_out72(0) => NLW_inst_probe_out72_UNCONNECTED(0),
probe_out73(0) => NLW_inst_probe_out73_UNCONNECTED(0),
probe_out74(0) => NLW_inst_probe_out74_UNCONNECTED(0),
probe_out75(0) => NLW_inst_probe_out75_UNCONNECTED(0),
probe_out76(0) => NLW_inst_probe_out76_UNCONNECTED(0),
probe_out77(0) => NLW_inst_probe_out77_UNCONNECTED(0),
probe_out78(0) => NLW_inst_probe_out78_UNCONNECTED(0),
probe_out79(0) => NLW_inst_probe_out79_UNCONNECTED(0),
probe_out8(0) => NLW_inst_probe_out8_UNCONNECTED(0),
probe_out80(0) => NLW_inst_probe_out80_UNCONNECTED(0),
probe_out81(0) => NLW_inst_probe_out81_UNCONNECTED(0),
probe_out82(0) => NLW_inst_probe_out82_UNCONNECTED(0),
probe_out83(0) => NLW_inst_probe_out83_UNCONNECTED(0),
probe_out84(0) => NLW_inst_probe_out84_UNCONNECTED(0),
probe_out85(0) => NLW_inst_probe_out85_UNCONNECTED(0),
probe_out86(0) => NLW_inst_probe_out86_UNCONNECTED(0),
probe_out87(0) => NLW_inst_probe_out87_UNCONNECTED(0),
probe_out88(0) => NLW_inst_probe_out88_UNCONNECTED(0),
probe_out89(0) => NLW_inst_probe_out89_UNCONNECTED(0),
probe_out9(0) => NLW_inst_probe_out9_UNCONNECTED(0),
probe_out90(0) => NLW_inst_probe_out90_UNCONNECTED(0),
probe_out91(0) => NLW_inst_probe_out91_UNCONNECTED(0),
probe_out92(0) => NLW_inst_probe_out92_UNCONNECTED(0),
probe_out93(0) => NLW_inst_probe_out93_UNCONNECTED(0),
probe_out94(0) => NLW_inst_probe_out94_UNCONNECTED(0),
probe_out95(0) => NLW_inst_probe_out95_UNCONNECTED(0),
probe_out96(0) => NLW_inst_probe_out96_UNCONNECTED(0),
probe_out97(0) => NLW_inst_probe_out97_UNCONNECTED(0),
probe_out98(0) => NLW_inst_probe_out98_UNCONNECTED(0),
probe_out99(0) => NLW_inst_probe_out99_UNCONNECTED(0),
sl_iport0(36 downto 0) => B"0000000000000000000000000000000000000",
sl_oport0(16 downto 0) => NLW_inst_sl_oport0_UNCONNECTED(16 downto 0)
);
end STRUCTURE;
|
mit
|
d42a6cfdeca3bd50543a3ddc3257178e
| 0.697377 | 2.991258 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.vhd
| 1 | 8,280 |
-- $Id: sys_tst_rlink_s3.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_s3 - syn
-- Description: rlink tester design for s3board
--
-- Dependencies: vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rlink/rlink_sp1c
-- rbd_tst_rlink
-- vlib/rbus/rb_sres_or_2
-- bplib/s3board/s3_sram_dummy
--
-- Test bench: tb/tb_tst_rlink_s3
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-12-22 442 13.1 O40d xc3s1000e-4 765 1672 96 1088 t 12.6
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-22 442 1.0 Initial version (derived from sys_tst_rlink_n2)
------------------------------------------------------------------------------
-- Usage of S3board switches, Buttons, LEDs:
--
-- SWI(7:2): no function (only connected to sn_humanio_rbus)
-- SWI(1): 1 enable XON
-- SWI(0): 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
-- 1 -> Pmod B/top RS232 port /
--
-- LED(7): SER_MONI.abact
-- LED(6:2): no function (only connected to sn_humanio_rbus)
-- LED(0): timer 0 busy
-- LED(1): timer 1 busy
--
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- DP(3): not SER_MONI.txok (shows tx back preasure)
-- DP(2): SER_MONI.txact (shows tx activity)
-- DP(1): not SER_MONI.rxok (shows rx back preasure)
-- DP(0): SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.s3boardlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_s3 is -- top level
-- implements s3board_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32; -- sram: data lines
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_rlink_s3;
architecture syn of sys_tst_rlink_s3 is
signal CLK : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv3 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal STAT : slv8 := (others=>'0');
constant rbaddr_hio : slv8 := "11000000"; -- 110000xx
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
RESET <= '0'; -- so far not used
CLK <= I_CLK50;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio_rbus
generic map (
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp1c
generic map (
ATOWIDTH => 6,
ITOWIDTH => 6,
CPREF => c_rlink_cpref,
IFAWIDTH => 5,
OFAWIDTH => 5,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 15,
CDINIT => sys_conf_ser2rri_cdinit)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ENAESC => SWI(1),
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
RBDTST : entity work.rbd_tst_rlink
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RB_SRES_TOP => RB_SRES,
RXSD => RXD,
RXACT => SER_MONI.rxact,
STAT => STAT
);
RB_SRES_OR1 : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_HIO,
RB_SRES_2 => RB_SRES_TST,
RB_SRES_OR => RB_SRES
);
SRAM : s3_sram_dummy -- connect SRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
DSP_DAT <= SER_MONI.abclkdiv;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
LED(7) <= SER_MONI.abact;
LED(6 downto 2) <= (others=>'0');
LED(1) <= STAT(1);
LED(0) <= STAT(0);
end syn;
|
gpl-2.0
|
a7385391256d5a1c03ad2c53a435daa8
| 0.498792 | 3.215534 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd
| 1 | 9,815 |
-- $Id: sys_tst_rlink_n2.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_n2 - syn
-- Description: rlink tester design for nexys2
--
-- Dependencies: vlib/xlib/dcm_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rlink/rlink_sp1c
-- rbd_tst_rlink
-- vlib/rbus/rb_sres_or_2
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: tb/tb_tst_rlink_n2
--
-- Target Devices: generic
-- Tool versions: xst 12.1, 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2012-12-27 453 13.3 O76d xc3s1200e-4 754 1605 96 1057 t 14.5
-- 2011-12-18 440 13.1 O40d xc3s1200e-4 754 1605 96 1057 t 16.8
-- 2011-06-26 385 12.1 M53d xc3s1200e-4 688 1500 68 993 t 16.2
-- 2011-04-02 375 12.1 M53d xc3s1200e-4 688 1572 68 994 t 13.8
-- 2010-12-29 351 12.1 M53d xc3s1200e-4 604 1298 68 851 t 14.7
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.2 remove clksys output hack
-- 2011-12-18 440 1.1.6 use now rbd_tst_rlink and rlink_sp1c
-- 2011-11-26 433 1.1.5 use nx_cram_dummy now
-- 2011-11-23 432 1.1.4 update O_FLA_CE_N usage
-- 2011-11-17 426 1.1.3 use dcm_sfs now
-- 2011-07-09 391 1.1.2 use now bp_rs232_2l4l_iob
-- 2011-07-08 390 1.1.1 use now sn_humanio
-- 2011-06-26 385 1.1 move s3_humanio_rbus from tst_rlink to top level
-- 2010-12-29 351 1.0 Initial version
------------------------------------------------------------------------------
-- Usage of Nexys 2 Switches, Buttons, LEDs:
--
-- SWI(7:2) no function (only connected to sn_humanio_rbus)
-- (1) 1 enable XON
-- (0) 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
-- 1 -> Pmod B/top RS232 port /
--
-- LED(7) SER_MONI.abact
-- (6:2) no function (only connected to sn_humanio_rbus)
-- (0) timer 0 busy
-- (1) timer 1 busy
--
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- DP(3) not SER_MONI.txok (shows tx back preasure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back preasure)
-- (0) SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_n2 is -- top level
-- implements nexys2_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_rlink_n2;
architecture syn of sys_tst_rlink_n2 is
signal CLK : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv3 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal STAT : slv8 := (others=>'0');
constant rbaddr_hio : slv8 := "11000000"; -- 110000xx
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
RESET <= '0'; -- so far not used
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => I_CLK50,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio_rbus
generic map (
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp1c
generic map (
ATOWIDTH => 6,
ITOWIDTH => 6,
CPREF => c_rlink_cpref,
IFAWIDTH => 5,
OFAWIDTH => 5,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 15,
CDINIT => sys_conf_ser2rri_cdinit)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ENAESC => SWI(1),
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
RBDTST : entity work.rbd_tst_rlink
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RB_SRES_TOP => RB_SRES,
RXSD => RXD,
RXACT => SER_MONI.rxact,
STAT => STAT
);
RB_SRES_OR1 : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_HIO,
RB_SRES_2 => RB_SRES_TST,
RB_SRES_OR => RB_SRES
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_FLA_CE_N <= '1'; -- keep Flash memory disabled
DSP_DAT <= SER_MONI.abclkdiv;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
LED(7) <= SER_MONI.abact;
LED(6 downto 2) <= (others=>'0');
LED(1) <= STAT(1);
LED(0) <= STAT(0);
end syn;
|
gpl-2.0
|
d1fab7bf80ee1b0b1c574e70e8ddcadd
| 0.503719 | 3.124801 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_fx2loop/nexys2/ic/sys_conf.vhd
| 1 | 2,118 |
-- $Id: sys_conf.vhd 453 2012-01-15 17:51:18Z mueller $
--
-- Copyright 2012- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_fx2loop_ic_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-15 453 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 2;
constant sys_conf_fx2_type : string := "ic2";
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;
|
gpl-2.0
|
db57198ed316757472899700eb997ad8
| 0.65203 | 3.830018 | false | false | false | false |
unhold/hdl
|
vhdl/gearbox_tb.vhd
| 1 | 2,235 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.rtl_pack.all;
use work.tb_pack.all;
entity gearbox_tb is
end;
architecture tb of gearbox_tb is
constant a_width_g : positive := 4;
constant b_width_g : positive := 3;
constant fifo_depth_order_g : positive := 4;
signal run : boolean := true;
signal reset : std_ulogic := '1';
signal a_reset_i : std_ulogic;
signal a_clock_i : std_ulogic;
signal a_data_i, a_data_o : std_ulogic_vector(a_width_g-1 downto 0);
signal b_reset_i : std_ulogic;
signal b_clock_i : std_ulogic;
signal b_data : std_ulogic_vector(b_width_g-1 downto 0);
signal pll_lock : std_ulogic;
begin
clk_gen(a_clock_i, run);
pll : entity work.pll
generic map (
multiplier_g => a_width_g,
divider_g => b_width_g)
port map (
run_i => run,
clock_i => a_clock_i,
clock_o => b_clock_i,
lock_o => pll_lock);
reset_a_sync : entity work.sync
generic map (
reset_value_g => '1')
port map (
reset_i => reset,
clock_i => a_clock_i,
data_i(0) => reset,
data_o(0) => a_reset_i);
reset_b_sync : entity work.sync
generic map (
reset_value_g => '1')
port map (
reset_i => reset,
clock_i => b_clock_i,
data_i(0) => reset,
data_o(0) => b_reset_i);
gearbox_a_b : entity work.gearbox
generic map (
a_width_g => a_width_g,
b_width_g => b_width_g,
fifo_depth_order_g => fifo_depth_order_g)
port map (
a_reset_i => a_reset_i,
a_clock_i => a_clock_i,
a_data_i => a_data_i,
b_reset_i => b_reset_i,
b_clock_i => b_clock_i,
b_data_o => b_data);
gearbox_b_a : entity work.gearbox
generic map (
a_width_g => b_width_g,
b_width_g => a_width_g,
fifo_depth_order_g => fifo_depth_order_g)
port map (
a_reset_i => b_reset_i,
a_clock_i => b_clock_i,
a_data_i => b_data,
b_reset_i => a_reset_i,
b_clock_i => a_clock_i,
b_data_o => a_data_o);
stim : process
begin
rst_gen(reset);
wait until (a_reset_i or b_reset_i) = '0';
for i in 0 to 2**a_width_g-1 loop
a_data_i <= std_ulogic_vector(to_unsigned(i, a_width_g));
wait_clk(a_clock_i);
end loop;
wait_clk(a_clock_i, 2**(fifo_depth_order_g+1));
run <= false;
wait;
end process;
end;
|
gpl-3.0
|
13a5eea9067a3fa4943836ba5a6659d7
| 0.603579 | 2.405813 | false | false | false | false |
Vadman97/ImageAES
|
des/DES/ipcore_dir/constants_mem/simulation/bmg_stim_gen.vhd
| 1 | 13,009 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (7 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0):= hex_to_std_logic_vector("0",8);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (1023 downto 0) of std_logic_vector(7 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"constants_mem.mif",
DEFAULT_DATA,
8,
1024);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>1024 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(9 DOWNTO 0) <= READ_ADDR(9 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ_REG(1);
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 1024 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
|
gpl-3.0
|
0561583e5fa7cf3f0032073cfa851333
| 0.529633 | 3.695739 | false | false | false | false |
freecores/w11
|
rtl/w11a/pdp11_core_rbus.vhd
| 1 | 15,962 |
-- $Id: pdp11_core_rbus.vhd 553 2014-03-17 06:40:08Z mueller $
--
-- Copyright 2007-2014 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_core_rbus - syn
-- Description: pdp11: core to rbus interface
--
-- Dependencies: -
-- Test bench: tb/tb_rlink_tba_pdp11core
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
-- Revision History: -
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.1 now numeric_std clean
-- 2010-12-29 351 1.1 renamed from pdp11_core_rri; ported to rbv3
-- 2010-10-23 335 1.2.3 rename RRI_LAM->RB_LAM;
-- 2010-06-20 308 1.2.2 use c_ibrb_ibf_ def's
-- 2010-06-18 306 1.2.1 rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
-- add ibrb register and ibr window logic
-- 2010-06-13 305 1.2 add CP_ADDR in port; mostly rewritten for new
-- rri <-> cp mapping
-- 2010-06-03 299 1.1.2 correct rbus init logic (use we, din, RB_ADDR)
-- 2010-05-02 287 1.1.1 rename RP_STAT->RB_STAT; remove unneeded unsigned()
-- 2010-05-01 285 1.1 port to rri V2 interface, add RB_ADDR generic;
-- rename c_rp_addr_* -> c_rb_addr_*
-- 2008-05-03 143 1.0.8 rename _cpursta->_cpurust
-- 2008-04-27 140 1.0.7 use cpursta interface, remove cpufail
-- 2008-03-02 121 1.0.6 set RP_ERR when cmderr or cmdmerr status seen
-- 2008-02-24 119 1.0.5 support lah,rps,wps cp commands
-- 2008-01-20 113 1.0.4 use single LAM; change to RRI_LAM interface
-- 2007-10-12 88 1.0.3 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-08-16 74 1.0.2 add AP_LAM interface to pdp11_core_rri
-- 2007-08-12 73 1.0.1 use def's; add stat command; wait for step complete
-- 2007-07-08 65 1.0 Initial version
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Address Bits Name r/w/i Function
--
-- bbb00000 conf r/w/- cpu configuration (e.g. cpu type)
-- (currently unused, all bits MBZ)
-- bbb00001 cntl -/f/- cpu control
-- 3:0 func function code
-- 0000: noop
-- 0001: start
-- 0010: stop
-- 0011: continue
-- 0100: step
-- 1111: reset (soft)
-- bbb00010 stat r/-/- cpu status
-- 7:04 cpurust r/-/- cp_stat: cpurust
-- 3 cpuhalt r/-/- cp_stat: cpuhalt
-- 2 cpugo r/-/- cp_stat: cpugo
-- 1 cmdmerr r/-/- cp_stat: cmdmerr
-- 0 cmderr r/-/- cp_stat: cmderr
-- bbb00011 psw r/w/- processor status word access
-- bbb00100 al r/w/- address register, low
-- bbb00101 ah r/w/- address register, high
-- 7 ubm r/w/- ubmap access
-- 6 p22 r/w/- 22bit access
-- 5: 0 addr r/w/- addr(21:16)
-- bbb00110 mem r/w/- memory access
-- bbb00111 memi r/w/- memory access, inc address
-- bbb01rrr gpr[] r/w/- general purpose regs
-- bbb10000 ibrb r/w/- ibr base address
-- 12:06 base r/w/- ibr window base address
-- 1:00 we r/w/- byte enables (00 equivalent to 11)
-- www----- ibr[] r/w/- ibr window (32 words)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_core_rbus is -- core to rbus interface
generic (
RB_ADDR_CORE : slv8 := slv(to_unsigned(2#00000000#,8));
RB_ADDR_IBUS : slv8 := slv(to_unsigned(2#10000000#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_STAT : out slv3; -- rbus: status flags
RB_LAM : out slbit; -- remote attention
CPU_RESET : out slbit; -- cpu master reset
CP_CNTL : out cp_cntl_type; -- console control port
CP_ADDR : out cp_addr_type; -- console address port
CP_DIN : out slv16; -- console data in
CP_STAT : in cp_stat_type; -- console status port
CP_DOUT : in slv16 -- console data out
);
end pdp11_core_rbus;
architecture syn of pdp11_core_rbus is
type state_type is (
s_idle, -- s_idle: wait for rp access
s_cpwait, -- s_cpwait: wait for cp port ack
s_cpstep -- s_cpstep: wait for cpustep done
);
type regs_type is record
state : state_type; -- state
rbselc : slbit; -- rbus select for core
rbseli : slbit; -- rbus select for ibus
cpreq : slbit; -- cp request flag
cpfunc : slv5; -- cp function
cpugo_1 : slbit; -- prev cycle cpugo
addr : slv22_1; -- address register
ena_22bit : slbit; -- 22bit enable
ena_ubmap : slbit; -- ubmap enable
ibrbase : slv(c_ibrb_ibf_base); -- ibr base address
ibrbe : slv2; -- ibr byte enables
ibrberet : slv2; -- ibr byte enables (for readback)
doinc : slbit; -- at cmdack: do addr reg inc
waitstep : slbit; -- at cmdack: wait for cpu step complete
end record regs_type;
constant regs_init : regs_type := (
s_idle, -- state
'0','0', -- rbselc,rbseli
'0', -- cpreq
(others=>'0'), -- cpfunc
'0', -- cpugo_1
(others=>'0'), -- addr
'0','0', -- ena_22bit, ena_ubmap
(others=>'0'),"00","00", -- ibrbase, ibrbe, ibrberet
'0','0' -- doinc, waitstep
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, RB_MREQ, CP_STAT, CP_DOUT)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irb_lam : slbit := '0';
variable irbena : slbit := '0';
variable icpreq : slbit := '0';
variable icpureset : slbit := '0';
variable icpaddr : cp_addr_type := cp_addr_init;
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irb_lam := '0';
irbena := RB_MREQ.re or RB_MREQ.we;
icpreq := '0';
icpureset := '0';
-- look for init's against the rbus base address, generate subsystem resets
if RB_MREQ.init='1' and RB_MREQ.we='1' and RB_MREQ.addr=RB_ADDR_CORE then
icpureset := RB_MREQ.din(0);
end if;
-- rbus address decoder
n.rbseli := '0';
n.rbselc := '0';
if RB_MREQ.aval='1' then
if RB_MREQ.addr(7 downto 5)=RB_ADDR_CORE(7 downto 5) then
n.rbselc := '1';
end if;
if RB_MREQ.addr(7 downto 5)=RB_ADDR_IBUS(7 downto 5) then
n.rbseli := '1';
end if;
end if;
if (r.rbselc='1' or r.rbseli='1') and irbena='1' then
irb_ack := '1'; -- ack all (maybe rejected later)
end if;
case r.state is
when s_idle => -- s_idle: wait for rbus access ------
n.doinc := '0';
n.waitstep := '0';
if r.rbseli = '1' then
if irbena = '1' then
n.cpfunc := c_cpfunc_rmem;
n.cpfunc(0) := RB_MREQ.we;
icpreq := '1';
end if;
elsif r.rbselc = '1' then
case RB_MREQ.addr(4 downto 0) is
when c_rbaddr_conf => -- conf -------------------------
null; -- currently no action
when c_rbaddr_cntl => -- cntl -------------------------
if irbena = '1' then
n.cpfunc := RB_MREQ.din(n.cpfunc'range);
end if;
if RB_MREQ.we = '1' then
icpreq := '1';
if RB_MREQ.din(3 downto 0) = c_cpfunc_step(3 downto 0) then
n.waitstep := '1';
end if;
end if;
when c_rbaddr_stat => -- stat -------------------------
irb_dout(c_stat_rbf_cmderr) := CP_STAT.cmderr;
irb_dout(c_stat_rbf_cmdmerr) := CP_STAT.cmdmerr;
irb_dout(c_stat_rbf_cpugo) := CP_STAT.cpugo;
irb_dout(c_stat_rbf_cpuhalt) := CP_STAT.cpuhalt;
irb_dout(c_stat_rbf_cpurust) := CP_STAT.cpurust;
when c_rbaddr_psw => -- psw --------------------------
if irbena = '1' then
n.cpfunc := c_cpfunc_rpsw;
n.cpfunc(0) := RB_MREQ.we;
icpreq := '1';
end if;
when c_rbaddr_al => -- al ---------------------------
irb_dout(c_al_rbf_addr) := r.addr(c_al_rbf_addr);
if RB_MREQ.we = '1' then
n.addr := (others=>'0'); -- write to al clears ah !!
n.ena_22bit := '0';
n.ena_ubmap := '0';
n.addr(c_al_rbf_addr) := RB_MREQ.din(c_al_rbf_addr);
end if;
when c_rbaddr_ah => -- ah ---------------------------
irb_dout(c_ah_rbf_ena_ubmap) := r.ena_ubmap;
irb_dout(c_ah_rbf_ena_22bit) := r.ena_22bit;
irb_dout(c_ah_rbf_addr) := r.addr(21 downto 16);
if RB_MREQ.we = '1' then
n.addr(21 downto 16) := RB_MREQ.din(c_ah_rbf_addr);
n.ena_22bit := RB_MREQ.din(c_ah_rbf_ena_22bit);
n.ena_ubmap := RB_MREQ.din(c_ah_rbf_ena_ubmap);
end if;
when c_rbaddr_mem => -- mem -----------------
if irbena = '1' then
n.cpfunc := c_cpfunc_rmem;
n.cpfunc(0) := RB_MREQ.we;
icpreq := '1';
end if;
when c_rbaddr_memi => -- memi ----------------
if irbena = '1' then
n.cpfunc := c_cpfunc_rmem;
n.cpfunc(0) := RB_MREQ.we;
n.doinc := '1';
icpreq := '1';
end if;
when c_rbaddr_r0 | c_rbaddr_r1 |
c_rbaddr_r2 | c_rbaddr_r3 |
c_rbaddr_r4 | c_rbaddr_r5 |
c_rbaddr_sp | c_rbaddr_pc => -- r* ------------------
if irbena = '1' then
n.cpfunc := c_cpfunc_rreg;
n.cpfunc(0) := RB_MREQ.we;
icpreq := '1';
end if;
when c_rbaddr_ibrb => -- ibrb ----------------
irb_dout(c_ibrb_ibf_base) := r.ibrbase;
irb_dout(c_ibrb_ibf_be) := r.ibrberet;
if RB_MREQ.we = '1' then
n.ibrbase := RB_MREQ.din(c_ibrb_ibf_base);
n.ibrberet := RB_MREQ.din(c_ibrb_ibf_be);
if RB_MREQ.din(c_ibrb_ibf_be) = "00" then -- both be=0 ?
n.ibrbe := "11";
else -- otherwise take 2 LSB's
n.ibrbe := RB_MREQ.din(c_ibrb_ibf_be);
end if;
end if;
when others =>
irb_ack := '0';
end case;
end if;
if icpreq = '1' then
irb_busy := '1';
n.cpreq := '1';
n.state := s_cpwait;
end if;
when s_cpwait => -- s_cpwait: wait for cp port ack ----
n.cpreq := '0'; -- cpreq only for 1 cycle
if (r.rbselc or r.rbseli)='0' or irbena='0' then -- rbus cycle abort
n.state := s_idle; -- quit
else
irb_dout := CP_DOUT;
irb_err := CP_STAT.cmderr or CP_STAT.cmdmerr;
if CP_STAT.cmdack = '1' then -- normal cycle end
if r.doinc = '1' then
n.addr := slv(unsigned(r.addr) + 1);
end if;
if r.waitstep = '1' then
irb_busy := '1';
n.state := s_cpstep;
else
n.state := s_idle;
end if;
else
irb_busy := '1';
end if;
end if;
when s_cpstep => -- s_cpstep: wait for cpustep done ---
if r.rbselc='0' or irbena='0' then -- rbus cycle abort
n.state := s_idle; -- quit
else
if CP_STAT.cpustep = '0' then -- cpustep done
n.state := s_idle;
else
irb_busy := '1';
end if;
end if;
when others => null;
end case;
icpaddr := cp_addr_init;
icpaddr.addr := r.addr;
icpaddr.racc := '0';
icpaddr.be := "11";
icpaddr.ena_22bit := r.ena_22bit;
icpaddr.ena_ubmap := r.ena_ubmap;
if r.rbseli = '1' and irbena = '1' then
icpaddr.addr(15 downto 13) := "111";
icpaddr.addr(c_ibrb_ibf_base) := r.ibrbase;
icpaddr.addr(5 downto 1) := RB_MREQ.addr(4 downto 0);
icpaddr.racc := '1';
icpaddr.be := r.ibrbe;
icpaddr.ena_22bit := '0';
icpaddr.ena_ubmap := '0';
end if;
n.cpugo_1 := CP_STAT.cpugo; -- delay cpugo
if CP_STAT.cpugo='0' and r.cpugo_1='1' then -- cpugo 1 -> 0 transition ?
irb_lam := '1';
end if;
N_REGS <= n;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= irb_err;
RB_SRES.busy <= irb_busy;
RB_SRES.dout <= irb_dout;
RB_STAT(0) <= CP_STAT.cpugo;
RB_STAT(1) <= CP_STAT.cpuhalt or CP_STAT.cpurust(CP_STAT.cpurust'left);
RB_STAT(2) <= CP_STAT.cmderr or CP_STAT.cmdmerr;
RB_LAM <= irb_lam;
CPU_RESET <= icpureset;
CP_CNTL.req <= r.cpreq;
CP_CNTL.func <= r.cpfunc;
CP_CNTL.rnum <= RB_MREQ.addr(2 downto 0);
CP_ADDR <= icpaddr;
CP_DIN <= RB_MREQ.din;
end process proc_next;
end syn;
|
gpl-2.0
|
5c0d6b8e930db8e1c45fc278552c5a66
| 0.454517 | 3.653468 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/w11a/nexys2/sys_conf.vhd
| 1 | 3,842 |
-- $Id: sys_conf.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2010-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 1.2 add fx2 settings
-- 2011-11-19 428 1.1.1 use clksys=56 (58 no closure after numeric_std...)
-- 2010-11-27 341 1.1 add dcm and memctl related constants (clksys=58)
-- 2010-05-05 295 1.0 Initial version (derived from _s3 version)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
-- valid system clock / delay combinations:
-- div mul clksys read0 read1 write
-- 1 1 50.0 2 2 3
-- 25 27 54.0 3 3 3
-- 25 29 58.0 3 3 4
package sys_conf is
constant sys_conf_clkfx_divide : positive := 25;
constant sys_conf_clkfx_multiply : positive := 28; -- ==> 56 MHz
constant sys_conf_memctl_read0delay : positive := 3;
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay;
constant sys_conf_memctl_writedelay : positive := 4;
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
-- fx2 settings: petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_bram : integer := 0; -- no bram, use cache
constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB)
constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte
--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug)
-- constant sys_conf_bram : integer := 1; -- bram only
-- constant sys_conf_bram_awidth : integer := 15; -- bram size (32 kB)
-- constant sys_conf_mem_losize : integer := 8#000777#; -- 32 kByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
-- Note: mem_losize holds 16 MSB of the PA of the addressable memory
-- 2 211 111 111 110 000 000 000
-- 1 098 765 432 109 876 543 210
--
-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte
-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte
-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte
-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte
-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte
-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte
-- upper 256 kB excluded for 11/70 UB
|
gpl-2.0
|
851874525845ef10bfac0f8c4ee7e096
| 0.608017 | 3.564007 | false | false | false | false |
Vadman97/ImageAES
|
vga/ipcore_dir/ben_mem/simulation/ben_mem_synth.vhd
| 1 | 7,077 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ben_mem_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY ben_mem_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE ben_mem_synth_ARCH OF ben_mem_synth IS
COMPONENT ben_mem_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: ben_mem_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
gpl-3.0
|
c29d83291af3cda912bf686987e7b92e
| 0.558711 | 3.76236 | false | false | false | false |
freecores/w11
|
rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd
| 2 | 4,020 |
-- $Id: ram_2swsr_rfirst_gen.vhd 422 2011-11-10 18:44:06Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ram_2swsr_rfirst_gen - syn
-- Description: Dual-Port RAM with with two synchronous read/write ports
-- and 'read-before-write' semantics (as block RAM).
-- The code is inspired by Xilinx example rams_16.vhd. The
-- 'ram_style' attribute is set to 'block', this will
-- force in XST a synthesis as block RAM.
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-08 422 1.0.4 now numeric_std clean
-- 2010-06-03 299 1.0.3 use sv_ prefix for shared variables
-- 2008-03-08 123 1.0.2 use std_..._arith, not _unsigned; use unsigned();
-- now initialize DO to all '0' at start
-- 2008-03-02 122 1.0.1 change generic default for BRAM models
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity ram_2swsr_rfirst_gen is -- RAM, 2 sync r/w ports, read first
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9); -- data port width
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end ram_2swsr_rfirst_gen;
architecture syn of ram_2swsr_rfirst_gen is
constant memsize : positive := 2**AWIDTH;
constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0');
type ram_type is array (0 to memsize-1) of slv(DWIDTH-1 downto 0);
shared variable sv_ram : ram_type := (others=>datzero);
attribute ram_style : string;
attribute ram_style of sv_ram : variable is "block";
signal R_DOA : slv(DWIDTH-1 downto 0) := datzero;
signal R_DOB : slv(DWIDTH-1 downto 0) := datzero;
begin
proc_clka: process (CLKA)
begin
if rising_edge(CLKA) then
if ENA = '1' then
R_DOA <= sv_ram(to_integer(unsigned(ADDRA)));
if WEA = '1' then
sv_ram(to_integer(unsigned(ADDRA))) := DIA;
end if;
end if;
end if;
end process proc_clka;
proc_clkb: process (CLKB)
begin
if rising_edge(CLKB) then
if ENB = '1' then
R_DOB <= sv_ram(to_integer(unsigned(ADDRB)));
if WEB = '1' then
sv_ram(to_integer(unsigned(ADDRB))) := DIB;
end if;
end if;
end if;
end process proc_clkb;
DOA <= R_DOA;
DOB <= R_DOB;
end syn;
|
gpl-2.0
|
c61763b8c7ba05244ff1384a21ee8579
| 0.564677 | 3.608618 | false | false | false | false |
freecores/w11
|
rtl/vlib/rbus/rblib.vhd
| 1 | 7,646 |
-- $Id: rblib.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: rblib
-- Description: Definitions for rbus interface and bus entities
--
-- Dependencies: -
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 3.1 CLK_CYCLE now integer
-- 2011-08-13 405 3.0.3 add in direction for FADDR,SEL ports
-- 2010-12-26 349 3.0.2 add rb_sel
-- 2010-12-22 346 3.0.1 add rb_mon and rb_mon_sb;
-- 2010-12-04 343 3.0 extracted from rrilib and rritblib;
-- rbus V3 interface: use aval,re,we
-- ... rrilib history removed ...
-- 2007-09-09 81 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package rblib is
type rb_mreq_type is record -- rbus - master request
aval : slbit; -- address valid
re : slbit; -- read enable
we : slbit; -- write enable
init : slbit; -- init
addr : slv8; -- address
din : slv16; -- data (input to slave)
end record rb_mreq_type;
constant rb_mreq_init : rb_mreq_type :=
('0','0','0','0', -- aval, re, we, init
(others=>'0'), -- addr
(others=>'0')); -- din
type rb_sres_type is record -- rbus - slave response
ack : slbit; -- acknowledge
busy : slbit; -- busy
err : slbit; -- error
dout : slv16; -- data (output from slave)
end record rb_sres_type;
constant rb_sres_init : rb_sres_type :=
('0','0','0', -- ack, busy, err
(others=>'0')); -- dout
component rb_sel is -- rbus address select logic
generic (
RB_ADDR : slv8; -- rbus address base
SAWIDTH : natural := 0); -- device subaddress space width
port (
CLK : in slbit; -- clock
RB_MREQ : in rb_mreq_type; -- rbus request
SEL : out slbit -- select state bit
);
end component;
component rb_sres_or_2 is -- rbus result or, 2 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end component;
component rb_sres_or_3 is -- rbus result or, 3 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end component;
component rb_sres_or_4 is -- rbus result or, 4 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
RB_SRES_4 : in rb_sres_type := rb_sres_init; -- rb_sres input 4
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end component;
component rbus_aif is -- rbus, abstract interface
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_LAM : out slv16; -- rbus: look at me
RB_STAT : out slv3 -- rbus: status flags
);
end component;
component rb_wreg_rw_3 is -- rbus: wide register r/w 3 bit select
generic (
DWIDTH : positive := 16);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
FADDR : in slv3; -- field address
SEL : in slbit; -- select
DATA : out slv(DWIDTH-1 downto 0); -- data
RB_MREQ : in rb_mreq_type; -- rbus request
RB_SRES : out rb_sres_type -- rbus response
);
end component;
component rb_wreg_w_3 is -- rbus: wide register w-o 3 bit select
generic (
DWIDTH : positive := 16);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
FADDR : in slv3; -- field address
SEL : in slbit; -- select
DATA : out slv(DWIDTH-1 downto 0); -- data
RB_MREQ : in rb_mreq_type; -- rbus request
RB_SRES : out rb_sres_type -- rbus response
);
end component;
component rb_wreg_r_3 is -- rbus: wide register r-o 3 bit select
generic (
DWIDTH : positive := 16);
port (
FADDR : in slv3; -- field address
SEL : in slbit; -- select
DATA : in slv(DWIDTH-1 downto 0); -- data
RB_SRES : out rb_sres_type -- rbus response
);
end component;
--
-- components for use in test benches (not synthesizable)
--
component rb_sres_or_mon is -- rbus result or monitor
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type; -- rb_sres input 2
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
RB_SRES_4 : in rb_sres_type := rb_sres_init -- rb_sres input 4
);
end component;
-- simbus sb_cntl field usage for rbus
constant sbcntl_sbf_rbmon : integer := 14;
component rb_mon is -- rbus monitor
generic (
DBASE : positive := 2); -- base for writing data values
port (
CLK : in slbit; -- clock
CLK_CYCLE : in integer := 0; -- clock cycle number
ENA : in slbit := '1'; -- enable monitor output
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end component;
component rb_mon_sb is -- simbus wrapper for rbus monitor
generic (
DBASE : positive := 2; -- base for writing data values
ENAPIN : integer := sbcntl_sbf_rbmon); -- SB_CNTL signal to use for enable
port (
CLK : in slbit; -- clock
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end component;
end package rblib;
|
gpl-2.0
|
aae40ac2063575ded894a3abd5682398
| 0.512032 | 3.713453 | false | false | false | false |
freecores/w11
|
rtl/vlib/rlink/tb/tb_rlink.vhd
| 1 | 23,804 |
-- $Id: tb_rlink.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_rlink - sim
-- Description: Test bench for rlink_core
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- genlib/clkdivce
-- rbus/tbd_tester
-- rbus/rb_mon
-- rlink/rlink_mon
-- tbd_rlink_gen [UUT]
--
-- To test: rlink_core (via tbd_rlink_direct)
-- rlink_base (via tbd_rlink_serport)
-- rlink_serport (via tbd_rlink_serport)
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 3.1 use new simclk/simclkcnt
-- 2011-11-19 427 3.0.7 fix crc8_update_tbl usage; now numeric_std clean
-- 2010-12-29 351 3.0.6 use new rbd_tester addr 111100xx (from 111101xx)
-- 2010-12-26 348 3.0.5 use simbus to export clkcycle (for tbd_..serport)
-- 2010-12-23 347 3.0.4 use rb_mon, rlink_mon directly; rename CP_*->RL_*
-- 2010-12-22 346 3.0.3 add .rlmon and .rbmon commands
-- 2010-12-21 345 3.0.2 rename commands .[rt]x... to [rt]x...;
-- add .[rt]x(idle|attn) cmds; remove 'bbbbbbbb' cmd
-- 2010-12-12 344 3.0.1 add .attn again; add .txbad, .txoof; ren oob->oof
-- 2010-12-05 343 3.0 rri->rlink renames; port to rbus V3 protocol;
-- use rbd_tester instead of sim target;
-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining
-- 2010-06-03 299 2.2.2 new init encoding (WE=0/1 int/ext);use sv_ prefix
-- for shared variables
-- 2010-05-02 287 2.2.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- 2010-04-03 274 2.2 add CE_USEC in tbd_rri_gen interface
-- 2009-03-14 197 2.1 remove records in interface to allow _ssim usage
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2008-03-24 129 1.1.2 CLK_CYCLE now 31 bits
-- 2008-01-20 112 1.1.1 rename clkgen->clkdivce
-- 2007-11-24 98 1.1 add RP_IINT support, add checkmiss_tx to test
-- for missing responses
-- 2007-10-26 92 1.0.2 add DONE timestamp at end of execution
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-09-09 81 1.0 Initial version
------------------------------------------------------------------------------
-- command set:
-- .reset assert RESET for 1 clk
-- .rlmon ien enable rlink monitor
-- .rbmon ien enable rbus monitor
-- .wait n wait n clks
-- .iowt n wait n clks for rlink i/o; auto-extend
-- .attn dat(16) pulse attn lines with dat
-- txsop send <sop>
-- txeop send <eop>
-- txnak send <nak>
-- txidle send <idle>
-- txattn send <attn>
-- tx8 dat(8) send 8 bit value
-- tx16 dat(16) send 16 bit value
-- txcrc send crc
-- txbad send bad (inverted) crc
-- txc cmd(8) send cmd - crc
-- txca cmd(8) addr(8) send cmd - addr - crc
-- txcad cmd(8) addr(8) dat(16) send cmd - addr - dl dh - crc
-- txcac cmd(8) addr(8) cnt(8) send cmd - addr - cnt - crc
-- txoof dat(9) send out-of-frame symbol
-- rxsop reset rx list; expect sop
-- rxeop expect <eop>
-- rxnak expect <nak>
-- rxidle expect <idle>
-- rxattn expect <attn>
-- rx8 dat(8) expect 8 bit value
-- rx16 dat(16) expect 16 bit value
-- rxcrc expect crc
-- rxcs cmd(8) stat(8) expect cmd - stat - crc
-- rxcds cmd(8) dat(16) stat(8) expect cmd - dl dh - stat - crc
-- rxccd cmd(8) ccmd(8) dat(16) stat(8) expect cmd - ccmd - dl dh - stat - crc
-- rxoof dat(9) expect out-of-frame symbol
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.genlib.all;
use work.comlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.simlib.all;
entity tb_rlink is
end tb_rlink;
architecture sim of tb_rlink is
signal CLK : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RESET : slbit := '0';
signal RL_DI : slv9 := (others=>'0');
signal RL_ENA : slbit := '0';
signal RL_BUSY : slbit := '0';
signal RL_DO : slv9 := (others=>'0');
signal RL_VAL : slbit := '0';
signal RL_HOLD : slbit := '0';
signal RB_MREQ_aval : slbit := '0';
signal RB_MREQ_re : slbit := '0';
signal RB_MREQ_we : slbit := '0';
signal RB_MREQ_initt: slbit := '0';
signal RB_MREQ_addr : slv8 := (others=>'0');
signal RB_MREQ_din : slv16 := (others=>'0');
signal RB_SRES_ack : slbit := '0';
signal RB_SRES_busy : slbit := '0';
signal RB_SRES_err : slbit := '0';
signal RB_SRES_dout : slv16 := (others=>'0');
signal RB_LAM_TBENCH : slv16 := (others=>'0');
signal RB_LAM_TESTER : slv16 := (others=>'0');
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv3 := (others=>'0');
signal TXRXACT : slbit := '0';
signal RLMON_EN : slbit := '0';
signal RBMON_EN : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
constant slv9_zero : slv9 := (others=>'0');
constant slv16_zero : slv16 := (others=>'0');
type slv9_array_type is array (0 to 255) of slv9;
type slv16_array_type is array (0 to 255) of slv16;
shared variable sv_rxlist : slv9_array_type := (others=>slv9_zero);
shared variable sv_nrxlist : natural := 0;
shared variable sv_rxind : natural := 0;
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 10 ns;
component tbd_rlink_gen is -- rlink, generic tb design interface
port (
CLK : in slbit; -- clock
CE_INT : in slbit; -- rlink ito time unit clock enable
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit; -- reset
RL_DI : in slv9; -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : out slbit; -- rlink: data busy
RL_DO : out slv9; -- rlink: data out
RL_VAL : out slbit; -- rlink: data valid
RL_HOLD : in slbit; -- rlink: data hold
RB_MREQ_aval : out slbit; -- rbus: request - aval
RB_MREQ_re : out slbit; -- rbus: request - re
RB_MREQ_we : out slbit; -- rbus: request - we
RB_MREQ_initt: out slbit; -- rbus: request - init; avoid name coll
RB_MREQ_addr : out slv8; -- rbus: request - addr
RB_MREQ_din : out slv16; -- rbus: request - din
RB_SRES_ack : in slbit; -- rbus: response - ack
RB_SRES_busy : in slbit; -- rbus: response - busy
RB_SRES_err : in slbit; -- rbus: response - err
RB_SRES_dout : in slv16; -- rbus: response - dout
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3; -- rbus: status flags
TXRXACT : out slbit -- txrx active flag
);
end component;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 6,
USECDIV => 4,
MSECDIV => 5)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
RB_MREQ.aval <= RB_MREQ_aval;
RB_MREQ.re <= RB_MREQ_re;
RB_MREQ.we <= RB_MREQ_we;
RB_MREQ.init <= RB_MREQ_initt;
RB_MREQ.addr <= RB_MREQ_addr;
RB_MREQ.din <= RB_MREQ_din;
RB_SRES_ack <= RB_SRES.ack;
RB_SRES_busy <= RB_SRES.busy;
RB_SRES_err <= RB_SRES.err;
RB_SRES_dout <= RB_SRES.dout;
RBTEST : rbd_tester
generic map (
RB_ADDR => slv(to_unsigned(2#11110000#,8)))
port map (
CLK => CLK,
RESET => '0',
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM_TESTER,
RB_STAT => RB_STAT
);
RB_LAM <= RB_LAM_TESTER or RB_LAM_TBENCH;
RLMON : rlink_mon
generic map (
DWIDTH => RL_DI'length)
port map (
CLK => CLK,
CLK_CYCLE => CLK_CYCLE,
ENA => RLMON_EN,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY,
RL_DO => RL_DO,
RL_VAL => RL_VAL,
RL_HOLD => RL_HOLD
);
RBMON : rb_mon
generic map (
DBASE => 2)
port map (
CLK => CLK,
CLK_CYCLE => CLK_CYCLE,
ENA => RBMON_EN,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
UUT : tbd_rlink_gen
port map (
CLK => CLK,
CE_INT => CE_MSEC,
CE_USEC => CE_USEC,
RESET => RESET,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY,
RL_DO => RL_DO,
RL_VAL => RL_VAL,
RL_HOLD => RL_HOLD,
RB_MREQ_aval => RB_MREQ_aval,
RB_MREQ_re => RB_MREQ_re,
RB_MREQ_we => RB_MREQ_we,
RB_MREQ_initt=> RB_MREQ_initt,
RB_MREQ_addr => RB_MREQ_addr,
RB_MREQ_din => RB_MREQ_din,
RB_SRES_ack => RB_SRES_ack,
RB_SRES_busy => RB_SRES_busy,
RB_SRES_err => RB_SRES_err,
RB_SRES_dout => RB_SRES_dout,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
TXRXACT => TXRXACT
);
proc_stim: process
file fstim : text open read_mode is "tb_rlink_stim";
variable iline : line;
variable oline : line;
variable ien : slbit := '0';
variable icmd : slv8 := (others=>'0');
variable iaddr : slv8 := (others=>'0');
variable icnt : slv8 := (others=>'0');
variable istat : slv3 := (others=>'0');
variable iattn : slv16 := (others=>'0');
variable idata : slv16 := (others=>'0');
variable ioof : slv9 := (others=>'0');
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idelta : integer := 0;
variable iowait : integer := 0;
variable txcrc,rxcrc : slv8 := (others=>'0');
variable txlist : slv9_array_type := (others=>slv9_zero);
variable ntxlist : natural := 0;
procedure do_tx8 (data : inout slv8) is
begin
txlist(ntxlist) := '0' & data;
ntxlist := ntxlist + 1;
txcrc := crc8_update_tbl(txcrc, data);
end procedure do_tx8;
procedure do_tx16 (data : inout slv16) is
begin
do_tx8(data( 7 downto 0));
do_tx8(data(15 downto 8));
end procedure do_tx16;
procedure do_rx8 (data : inout slv8) is
begin
sv_rxlist(sv_nrxlist) := '0' & data;
sv_nrxlist := sv_nrxlist + 1;
rxcrc := crc8_update_tbl(rxcrc, data);
end procedure do_rx8;
procedure do_rx16 (data : inout slv16) is
begin
do_rx8(data( 7 downto 0));
do_rx8(data(15 downto 8));
end procedure do_rx16;
procedure checkmiss_rx is
begin
if sv_rxind < sv_nrxlist then
for i in sv_rxind to sv_nrxlist-1 loop
writetimestamp(oline, CLK_CYCLE, ": moni ");
write(oline, string'(" FAIL MISSING DATA="));
write(oline, sv_rxlist(i)(8));
write(oline, string'(" "));
write(oline, sv_rxlist(i)(7 downto 0));
writeline(output, oline);
end loop;
end if;
end procedure checkmiss_rx;
begin
wait for clock_offset - setup_time;
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".rlmon" => -- .rlmon
read_ea(iline, ien);
RLMON_EN <= ien;
wait for 2*clock_period; -- wait for monitor to start
when ".rbmon" => -- .rbmon
read_ea(iline, ien);
RBMON_EN <= ien;
wait for 2*clock_period; -- wait for monitor to start
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when ".iowt " => -- .iowt
read_ea(iline, iowait);
idelta := iowait;
while idelta > 0 loop -- until time has expired
if TXRXACT = '1' then -- if any io activity
idelta := iowait; -- restart timer
else
idelta := idelta - 1; -- otherwise count down time
end if;
wait for clock_period;
end loop;
when ".attn " => -- .attn
read_ea(iline, iattn);
RB_LAM_TBENCH <= iattn; -- pulse attn lines
wait for clock_period; -- for 1 clock
RB_LAM_TBENCH <= (others=>'0');
when "txsop " => -- txsop send sop
txlist(0) := c_rlink_dat_sop;
ntxlist := 1;
txcrc := (others=>'0');
when "txeop " => -- txeop send eop
txlist(0) := c_rlink_dat_eop;
ntxlist := 1;
txcrc := (others=>'0');
when "txnak " => -- txnak send nak
txlist(0) := c_rlink_dat_nak;
ntxlist := 1;
txcrc := (others=>'0');
when "txidle" => -- txidle send idle
txlist(0) := c_rlink_dat_idle;
ntxlist := 1;
when "txattn" => -- txattn send attn
txlist(0) := c_rlink_dat_attn;
ntxlist := 1;
when "tx8 " => -- tx8 send 8 bit value
read_ea(iline, iaddr);
ntxlist := 0;
do_tx8(iaddr);
when "tx16 " => -- tx16 send 16 bit value
read_ea(iline, idata);
ntxlist := 0;
do_tx16(idata);
when "txcrc " => -- txcrc send crc
txlist(0) := '0' & txcrc;
ntxlist := 1;
when "txbad " => -- txbad send bad crc
txlist(0) := '0' & (not txcrc);
ntxlist := 1;
when "txc " => -- txc send: cmd crc
read_ea(iline, icmd);
ntxlist := 0;
do_tx8(icmd);
txlist(ntxlist) := '0' & txcrc;
ntxlist := ntxlist + 1;
when "txca " => -- txc send: cmd addr crc
read_ea(iline, icmd);
read_ea(iline, iaddr);
ntxlist := 0;
do_tx8(icmd);
do_tx8(iaddr);
txlist(ntxlist) := '0' & txcrc;
ntxlist := ntxlist + 1;
when "txcad " => -- txc send: cmd addr data crc
read_ea(iline, icmd);
read_ea(iline, iaddr);
read_ea(iline, idata);
ntxlist := 0;
do_tx8(icmd);
do_tx8(iaddr);
do_tx16(idata);
txlist(ntxlist) := '0' & txcrc;
ntxlist := ntxlist + 1;
when "txcac " => -- txc send: cmd addr cnt crc
read_ea(iline, icmd);
read_ea(iline, iaddr);
read_ea(iline, icnt);
ntxlist := 0;
do_tx8(icmd);
do_tx8(iaddr);
do_tx8(icnt);
txlist(ntxlist) := '0' & txcrc;
ntxlist := ntxlist + 1;
when "txoof " => -- txoof send out-of-frame symbol
read_ea(iline, txlist(0));
ntxlist := 1;
when "rxsop " => -- rxsop expect sop
checkmiss_rx;
sv_rxlist(0) := c_rlink_dat_sop;
sv_nrxlist := 1;
sv_rxind := 0;
rxcrc := (others=>'0');
when "rxeop " => -- rxeop expect eop
sv_rxlist(sv_nrxlist) := c_rlink_dat_eop;
sv_nrxlist := sv_nrxlist + 1;
when "rxnak " => -- rxnak expect nak
sv_rxlist(sv_nrxlist) := c_rlink_dat_nak;
sv_nrxlist := sv_nrxlist + 1;
when "rxidle" => -- rxidle expect idle
sv_rxlist(sv_nrxlist) := c_rlink_dat_idle;
sv_nrxlist := sv_nrxlist + 1;
when "rxattn" => -- rxattn expect attn
sv_rxlist(sv_nrxlist) := c_rlink_dat_attn;
sv_nrxlist := sv_nrxlist + 1;
when "rx8 " => -- rx8 expect 8 bit value
read_ea(iline, iaddr);
do_rx8(iaddr);
when "rx16 " => -- rx16 expect 16 bit value
read_ea(iline, idata);
do_rx16(idata);
when "rxcrc " => -- rxcrc expect crc
sv_rxlist(sv_nrxlist) := '0' & rxcrc;
sv_nrxlist := sv_nrxlist+1;
when "rxcs " => -- rxcs expect: cmd stat crc
read_ea(iline, icmd);
read_ea(iline, iaddr);
do_rx8(icmd);
do_rx8(iaddr);
sv_rxlist(sv_nrxlist) := '0' & rxcrc;
sv_nrxlist := sv_nrxlist + 1;
when "rxcds " => -- rxcsd expect: cmd data stat crc
read_ea(iline, icmd);
read_ea(iline, idata);
read_ea(iline, iaddr);
do_rx8(icmd);
do_rx16(idata);
do_rx8(iaddr);
sv_rxlist(sv_nrxlist) := '0' & rxcrc;
sv_nrxlist := sv_nrxlist + 1;
when "rxccd " => -- rxccd expect: cmd ccmd dat stat crc
read_ea(iline, icmd);
read_ea(iline, icnt);
read_ea(iline, idata);
read_ea(iline, iaddr);
do_rx8(icmd);
do_rx8(icnt);
do_rx16(idata);
do_rx8(iaddr);
sv_rxlist(sv_nrxlist) := '0' & rxcrc;
sv_nrxlist := sv_nrxlist + 1;
when "rxoof " => -- rxoof expect: out-of-frame symbol
read_ea(iline, ioof);
sv_rxlist(sv_nrxlist) := ioof;
sv_nrxlist := sv_nrxlist + 1;
when others => -- bad command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
next file_loop when ntxlist=0;
for i in 0 to ntxlist-1 loop
RL_DI <= txlist(i);
RL_ENA <= '1';
writetimestamp(oline, CLK_CYCLE, ": stim");
write(oline, txlist(i)(8), right, 3);
write(oline, txlist(i)(7 downto 0), right, 9);
if txlist(i)(8) = '1' then
case txlist(i) is
when c_rlink_dat_idle =>
write(oline, string'(" (idle)"));
when c_rlink_dat_sop =>
write(oline, string'(" (sop) "));
when c_rlink_dat_eop =>
write(oline, string'(" (eop) "));
when c_rlink_dat_nak =>
write(oline, string'(" (nak) "));
when c_rlink_dat_attn =>
write(oline, string'(" (attn)"));
when others =>
write(oline, string'(" (????)"));
end case;
end if;
writeline(output, oline);
wait for clock_period;
while RL_BUSY = '1' loop
wait for clock_period;
end loop;
RL_ENA <= '0';
end loop; -- i
ntxlist := 0;
end loop; -- file fstim
wait for 50*clock_period;
checkmiss_rx;
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
wait for c2out_time;
if RL_VAL = '1' then
writetimestamp(oline, CLK_CYCLE, ": moni");
write(oline, RL_DO(8), right, 3);
write(oline, RL_DO(7 downto 0), right, 9);
if RL_DO(8) = '1' then
case RL_DO is
when c_rlink_dat_idle =>
write(oline, string'(" (idle)"));
when c_rlink_dat_sop =>
write(oline, string'(" (sop) "));
when c_rlink_dat_eop =>
write(oline, string'(" (eop) "));
when c_rlink_dat_nak =>
write(oline, string'(" (nak) "));
when c_rlink_dat_attn =>
write(oline, string'(" (attn)"));
when others =>
write(oline, string'(" (????)"));
end case;
end if;
if sv_nrxlist > 0 then
write(oline, string'(" CHECK"));
if sv_rxind < sv_nrxlist then
if RL_DO = sv_rxlist(sv_rxind) then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL, exp="));
write(oline, sv_rxlist(sv_rxind)(8), right, 2);
write(oline, sv_rxlist(sv_rxind)(7 downto 0), right, 9);
end if;
sv_rxind := sv_rxind + 1;
else
write(oline, string'(" FAIL, UNEXPECTED"));
end if;
end if;
writeline(output, oline);
end if;
end loop;
end process proc_moni;
end sim;
|
gpl-2.0
|
a468e9cf54e37fb99ed58b2900ca863f
| 0.477357 | 3.712414 | false | false | false | false |
freecores/w11
|
rtl/ibus/ibd_kw11l.vhd
| 2 | 5,638 |
-- $Id: ibd_kw11l.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ibd_kw11l - syn
-- Description: ibus dev(loc): KW11-L (line clock)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 9 23 0 14 s 5.3
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 8 25 0 15 s 5.3
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.1 now numeric_std clean
-- 2010-10-17 333 1.1 use ibus V2 interface
-- 2009-06-01 221 1.0.5 BUGFIX: add RESET; don't clear tcnt on ibus reset
-- 2008-08-22 161 1.0.4 use iblib; add EI_ACK to proc_next sens. list
-- 2008-05-09 144 1.0.3 use intreq flop, use EI_ACK
-- 2008-01-20 112 1.0.2 fix proc_next sensitivity list; use BRESET
-- 2008-01-06 111 1.0.1 Renamed to ibd_kw11l (RRI_REQ not used)
-- 2008-01-05 110 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibd_kw11l is -- ibus dev(loc): KW11-L (line clock)
-- fixed address: 177546
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- msec pulse
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end ibd_kw11l;
architecture syn of ibd_kw11l is
constant ibaddr_kw11l : slv16 := slv(to_unsigned(8#177546#,16));
constant lks_ibf_ie : integer := 6;
constant lks_ibf_moni : integer := 7;
constant twidth : natural := 5;
constant tdivide : natural := 20;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
ie : slbit; -- interrupt enable
moni : slbit; -- monitor bit
intreq : slbit; -- interrupt request
tcnt : slv(twidth-1 downto 0); -- timer counter
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
'0', -- ie
'1', -- moni (set on reset !!)
'0', -- intreq
(others=>'0') -- tcnt
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then -- BRESET is 1 for system and ibus reset
R_REGS <= regs_init;
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.tcnt <= N_REGS.tcnt; -- don't clear msec tick counter
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, CE_MSEC, EI_ACK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibw0 : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr=ibaddr_kw11l(12 downto 1) then
n.ibsel := '1';
end if;
-- ibus output driver
if r.ibsel = '1' then
idout(lks_ibf_ie) := R_REGS.ie;
idout(lks_ibf_moni) := R_REGS.moni;
end if;
-- ibus write transactions
if r.ibsel='1' and ibw0='1' then
n.ie := IB_MREQ.din(lks_ibf_ie);
n.moni := IB_MREQ.din(lks_ibf_moni);
if IB_MREQ.din(lks_ibf_ie)='0' or IB_MREQ.din(lks_ibf_moni)='0' then
n.intreq := '0';
end if;
end if;
-- other state changes
if CE_MSEC = '1' then
n.tcnt := slv(unsigned(r.tcnt) + 1);
if unsigned(r.tcnt) = tdivide-1 then
n.tcnt := (others=>'0');
n.moni := '1';
if r.ie = '1' then
n.intreq := '1';
end if;
end if;
end if;
if EI_ACK = '1' then
n.intreq := '0';
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= '0';
EI_REQ <= r.intreq;
end process proc_next;
end syn;
|
gpl-2.0
|
0eacc0a7f28f67728b230f573ffd57d1
| 0.517027 | 3.471675 | false | false | false | false |
freecores/w11
|
rtl/vlib/rlink/rlink_sp1c.vhd
| 1 | 4,888 |
-- $Id: rlink_sp1c.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rlink_sp1c - syn
-- Description: rlink_core8 + serport_1clock combo
--
-- Dependencies: rlink_core8
-- serport/serport_1clock
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ifa ofa
-- 2011-12-09 437 13.1 O40d xc3s1000-4 337 733 64 469 s 9.8 - -
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-09 437 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.rlinklib.all;
use work.serportlib.all;
entity rlink_sp1c is -- rlink_core8+serport_1clock combo
generic (
ATOWIDTH : positive := 5; -- access timeout counter width
ITOWIDTH : positive := 6; -- idle timeout counter width
CPREF : slv4 := c_rlink_cpref; -- comma prefix
IFAWIDTH : natural := 5; -- input fifo address width (0=none)
OFAWIDTH : natural := 5; -- output fifo address width (0=none)
ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RBMON : integer := sbcntl_sbf_rbmon; -- SB_CNTL for rbmon (-1=none)
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15); -- clk divider initial/reset setting
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
CE_MSEC : in slbit; -- 1 msec clock enable
CE_INT : in slbit := '0'; -- rri ito time unit clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
RTS_N : out slbit; -- request to send (act.low, board view)
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3; -- rbus: status flags
RL_MONI : out rl_moni_type; -- rlink_core: monitor port
SER_MONI : out serport_moni_type -- serport: monitor port
);
end entity rlink_sp1c;
architecture syn of rlink_sp1c is
signal RLB_DI : slv8 := (others=>'0');
signal RLB_ENA : slbit := '0';
signal RLB_BUSY : slbit := '0';
signal RLB_DO : slv8 := (others=>'0');
signal RLB_VAL : slbit := '0';
signal RLB_HOLD : slbit := '0';
begin
CORE : rlink_core8
generic map (
ATOWIDTH => ATOWIDTH,
ITOWIDTH => ITOWIDTH,
CPREF => CPREF,
ENAPIN_RLMON => ENAPIN_RLMON,
ENAPIN_RBMON => ENAPIN_RBMON)
port map (
CLK => CLK,
CE_INT => CE_INT,
RESET => RESET,
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
RL_MONI => RL_MONI,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
SERPORT : serport_1clock
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT,
RXFAWIDTH => IFAWIDTH,
TXFAWIDTH => OFAWIDTH)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => ENAXON,
ENAESC => ENAESC,
RXDATA => RLB_DI,
RXVAL => RLB_ENA,
RXHOLD => RLB_BUSY,
TXDATA => RLB_DO,
TXENA => RLB_VAL,
TXBUSY => RLB_HOLD,
MONI => SER_MONI,
RXSD => RXSD,
TXSD => TXSD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
end syn;
|
gpl-2.0
|
3fdc83a21fd9c207412aadb6fd207081
| 0.52946 | 3.728452 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vhd
| 1 | 11,787 |
-- $Id: sys_tst_rlink_cuff_atlys.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_cuff_atlys - syn
-- Description: rlink tester design for atlys with fx2 interface
--
-- Dependencies: vlib/xlib/dcm_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_demu_rbus
-- bplib/fx2lib/fx2_2fifoctl_as [sys_conf_fx2_type="as2"]
-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"]
-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"]
-- tst_rlink_cuff
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
-- 2013-01-06 472 13.3 O76d xc6slx45 ??? ???? ??? ???? p ??.? ic2/100
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-06 472 1.0 Initial version; derived from sys_tst_rlink_cuff_n3
-- and sys_tst_fx2loop_atlys
------------------------------------------------------------------------------
-- Usage of Atlys Switches, Buttons, LEDs:
--
-- SWI(7:3) no function (only connected to sn_humanio_demu_rbus)
-- (2) 0 -> int/ext RS242 port for rlink
-- 1 -> use USB interface for rlink
-- (1) 1 enable XON
-- (0) 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
-- 1 -> Pmod B/top RS232 port /
--
-- LED(7) SER_MONI.abact
-- (6:2) no function (only connected to sn_humanio_demu_rbus)
-- (0) timer 0 busy
-- (1) timer 1 busy
--
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- for SWI(2)='0' (serport)
-- DP(3) not SER_MONI.txok (shows tx back preasure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back preasure)
-- (0) SER_MONI.rxact (shows rx activity)
-- for SWI(2)='1' (fx2)
-- DP(3) FX2_TX2BUSY (shows tx2 back preasure)
-- (2) FX2_TX2ENA(stretched) (shows tx2 activity)
-- (1) FX2_TXENA(streched) (shows tx activity)
-- (0) FX2_RXVAL(stretched) (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.rblib.all;
use work.fx2lib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_cuff_atlys is -- top level
-- implements atlys_fusp_cuff_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_USB_RXD : in slbit; -- USB UART receive data (board view)
O_USB_TXD : out slbit; -- USB UART transmit data (board view)
I_HIO_SWI : in slv8; -- atlys hio switches
I_HIO_BTN : in slv6; -- atlys hio buttons
O_HIO_LED: out slv8; -- atlys hio leds
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end sys_tst_rlink_cuff_atlys;
architecture syn of sys_tst_rlink_cuff_atlys is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXSD : slbit := '0';
signal TXSD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXVAL : slbit := '0';
signal FX2_RXHOLD : slbit := '0';
signal FX2_RXAEMPTY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXENA : slbit := '0';
signal FX2_TXBUSY : slbit := '0';
signal FX2_TXAFULL : slbit := '0';
signal FX2_TX2DATA : slv8 := (others=>'0');
signal FX2_TX2ENA : slbit := '0';
signal FX2_TX2BUSY : slbit := '0';
signal FX2_TX2AFULL : slbit := '0';
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
constant rbaddr_hio : slv8 := "11000000"; -- 110000xx
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 10.0)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7, -- good for up to 127 MHz !
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXSD,
TXD => TXSD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_USB_RXD,
O_TXD0 => O_USB_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio_demu_rbus
generic map (
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_HIO_SWI,
I_BTN => I_HIO_BTN,
O_LED => O_HIO_LED
);
FX2_CNTL_AS : if sys_conf_fx2_type = "as2" generate
CNTL : fx2_2fifoctl_as
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
PETOWIDTH => sys_conf_fx2_petowidth,
RDPWLDELAY => sys_conf_fx2_rdpwldelay,
RDPWHDELAY => sys_conf_fx2_rdpwhdelay,
WRPWLDELAY => sys_conf_fx2_wrpwldelay,
WRPWHDELAY => sys_conf_fx2_wrpwhdelay,
FLAGDELAY => sys_conf_fx2_flagdelay)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_AS;
FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
CNTL : fx2_2fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC;
FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
CNTL : fx2_3fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
TX2AFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
TX2DATA => FX2_TX2DATA,
TX2ENA => FX2_TX2ENA,
TX2BUSY => FX2_TX2BUSY,
TX2AFULL => FX2_TX2AFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC3;
TST : entity work.tst_rlink_cuff
port map (
CLK => CLK,
RESET => '0',
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RB_MREQ_TOP => RB_MREQ,
RB_SRES_TOP => RB_SRES_HIO,
SWI => SWI,
BTN => BTN(3 downto 0),
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
RXSD => RXSD,
TXSD => TXSD,
RTS_N => RTS_N,
CTS_N => CTS_N,
FX2_RXDATA => FX2_RXDATA,
FX2_RXVAL => FX2_RXVAL,
FX2_RXHOLD => FX2_RXHOLD,
FX2_TXDATA => FX2_TXDATA,
FX2_TXENA => FX2_TXENA,
FX2_TXBUSY => FX2_TXBUSY,
FX2_TX2DATA => FX2_TX2DATA,
FX2_TX2ENA => FX2_TX2ENA,
FX2_TX2BUSY => FX2_TX2BUSY,
FX2_MONI => FX2_MONI
);
end syn;
|
gpl-2.0
|
cc8bd88e9bc020e0d1b0c251cbcb2e49
| 0.503521 | 3.154134 | false | false | false | false |
alphaFred/Sejits4Fpgas
|
sejits4fpgas/hw/user/BasicArith.vhd
| 1 | 12,635 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNIMACRO;
use UNIMACRO.vcomponents.all;
Library UNISIM;
use UNISIM.vcomponents.all;
ENTITY BasicArith IS
GENERIC (
OP : integer
);
PORT (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
VALID_IN : in STD_LOGIC;
READY_IN : in std_logic;
LEFT : in STD_LOGIC_VECTOR(7 downto 0);
RIGHT : in STD_LOGIC_VECTOR(7 downto 0);
VALID_OUT : out STD_LOGIC;
READY_OUT : out std_logic;
BINOP_OUT : out STD_LOGIC_VECTOR(7 downto 0)
);
END BasicArith;
ARCHITECTURE BasicArith_Behave OF BasicArith IS
-- BEGIN DSP48E1_inst_1
signal MULTISIGNOUT_DSP1 : std_logic;
signal CARRYCASCOUT_DSP1 : std_logic;
--
signal OVERFLOW_DSP1 : std_logic;
signal PATTERNBDETECT_DSP1 : std_logic;
signal PATTERNDETECT_DSP1 : std_logic;
signal UNDERFLOW_DSP1 : std_logic;
--
signal P_DSP1 : std_logic_vector(47 downto 0);
--
signal ACIN_DSP1 : std_logic_vector(29 downto 0) := (others => '0');
signal BCIN_DSP1 : std_logic_vector(17 downto 0) := (others => '0');
--
signal ACOUT_DSP1 : std_logic_vector(29 downto 0);
signal BCOUT_DSP1 : std_logic_vector(17 downto 0);
--
signal CARRYCASCIN_DSP1 : std_logic := '0';
signal MULTISIGNIN_DSP1 : std_logic := '0';
signal PCIN_DSP1 : std_logic_vector(47 downto 0) := (others => '0');
signal PCOUT_DSP1 : std_logic_vector(47 downto 0);
--
signal ALUMODE_DSP1 : std_logic_vector(3 downto 0) := (others => '0');
signal CARRYINSEL_DSP1 : std_logic_vector(2 downto 0) := (others => '0');
signal INMODE_DSP1 : std_logic_vector(4 downto 0) := (others => '0');
signal OPMODE_DSP1 : std_logic_vector(6 downto 0) := (others => '0');
--
signal A_DSP1 : std_logic_vector(29 downto 0) := (others => '0');
signal B_DSP1 : std_logic_vector(17 downto 0) := (others => '0');
signal C_DSP1 : std_logic_vector(47 downto 0) := (others => '0');
signal CARRYIN_DSP1 : std_logic := '0';
signal D_DSP1 : std_logic_vector(24 downto 0) := (others => '0');
-- END DSP48E1_inst_1
constant DELAY_ADD_SUB : positive := 3;
constant DELAY_MUL : positive := 4;
--
TYPE iBus_ADD_SUB is array(DELAY_ADD_SUB-1 downto 0) of std_logic;
TYPE iBus_MUL is array(DELAY_MUL-1 downto 0) of std_logic;
--
signal ValidsRegBus_ADD_SUB : iBus_ADD_SUB := (others => '0');
signal ValidsRegBus_MUL : iBus_MUL := (others => '0');
--
COMPONENT logic_dff_block
Port (
D : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC
);
END COMPONENT;
BEGIN
DSP48E1_inst_1 : DSP48E1
generic map (
A_INPUT => "DIRECT",
B_INPUT => "DIRECT",
USE_DPORT => FALSE,
USE_MULT => "MULTIPLY",
USE_SIMD => "ONE48",
AUTORESET_PATDET => "NO_RESET",
MASK => X"0000000000ff",
PATTERN => X"000000000000",
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_PATTERN_DETECT => "PATDET",
ACASCREG => 1,
ADREG => 1,
ALUMODEREG => 1,
AREG => 1,
BCASCREG => 1,
BREG => 1,
CARRYINREG => 1,
CARRYINSELREG => 1,
CREG => 1,
DREG => 1,
INMODEREG => 1,
MREG => 1,
OPMODEREG => 1,
PREG => 1
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => ACOUT_DSP1,
BCOUT => BCOUT_DSP1,
CARRYCASCOUT => CARRYCASCOUT_DSP1,
MULTSIGNOUT => MULTISIGNOUT_DSP1,
PCOUT => PCOUT_DSP1,
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => OVERFLOW_DSP1,
PATTERNBDETECT => PATTERNBDETECT_DSP1,
PATTERNDETECT => PATTERNDETECT_DSP1,
UNDERFLOW => UNDERFLOW_DSP1,
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open,
P => P_DSP1,
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => ACIN_DSP1,
BCIN => BCIN_DSP1,
CARRYCASCIN => CARRYCASCIN_DSP1,
MULTSIGNIN => MULTISIGNIN_DSP1,
PCIN => PCIN_DSP1,
-- Control: 4-bit (each) input: Control Inputs/Status Bits
ALUMODE => ALUMODE_DSP1,
CARRYINSEL => CARRYINSEL_DSP1,
CLK => CLK,
INMODE => INMODE_DSP1,
OPMODE => OPMODE_DSP1,
-- Data: 30-bit (each) input: Data Ports
A => A_DSP1,
B => B_DSP1,
C => C_DSP1,
CARRYIN => CARRYIN_DSP1,
D => D_DSP1,
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '1',
CEA2 => '1',
CEAD => '1',
CEALUMODE => '1',
CEB1 => '1',
CEB2 => '1',
CEC => '1',
CECARRYIN => '1',
CECTRL => '1',
CED => '1',
CEINMODE => '1',
CEM => '1',
CEP => '1',
RSTA => RST,
RSTALLCARRYIN => RST,
RSTALUMODE => RST,
RSTB => RST,
RSTC => RST,
RSTCTRL => RST,
RSTD => RST,
RSTINMODE => RST,
RSTM => RST,
RSTP => RST
);
validReg_ADD: if OP = 0 generate
begin
validReg_ADD_int: for i in 0 to DELAY_ADD_SUB generate
begin
validdffLeft_ADD: if i = 0 generate
begin
valid_dff: component logic_dff_block
port map (
D => VALID_IN,
CLK => CLK,
RST => RST,
Q => ValidsRegBus_ADD_SUB(i)
);
end generate validdffLeft_ADD;
--
dffOthers_ADD: if (i > 0 AND i < DELAY_ADD_SUB) generate
begin
valid_dff: component logic_dff_block
port map (
D => ValidsRegBus_ADD_SUB(i-1),
CLK => CLK,
RST => RST,
Q => ValidsRegBus_ADD_SUB(i)
);
end generate dffOthers_ADD;
--
dffRight_ADD: if i = DELAY_ADD_SUB generate
begin
valid_dff: component logic_dff_block
port map (
D => ValidsRegBus_ADD_SUB(i-1),
CLK => CLK,
RST => RST,
Q => VALID_OUT
);
end generate dffRight_ADD;
end generate validReg_ADD_int;
end generate validReg_ADD;
validReg_SUB: if OP = 1 generate
begin
validReg_SUB_int: for i in 0 to DELAY_ADD_SUB generate
begin
validdffLeft_SUB: if i = 0 generate
begin
valid_dff: component logic_dff_block
port map (
D => VALID_IN,
CLK => CLK,
RST => RST,
Q => ValidsRegBus_ADD_SUB(i)
);
end generate validdffLeft_SUB;
--
dffOthers_SUB: if (i > 0 AND i < DELAY_ADD_SUB) generate
begin
valid_dff: component logic_dff_block
port map (
D => ValidsRegBus_ADD_SUB(i-1),
CLK => CLK,
RST => RST,
Q => ValidsRegBus_ADD_SUB(i)
);
end generate dffOthers_SUB;
--
dffRight_SUB: if i = DELAY_ADD_SUB generate
begin
valid_dff: component logic_dff_block
port map (
D => ValidsRegBus_ADD_SUB(i-1),
CLK => CLK,
RST => RST,
Q => VALID_OUT
);
end generate dffRight_SUB;
end generate validReg_SUB_int;
end generate validReg_SUB;
validReg_MUL: if OP = 2 generate
begin
validReg_MUL_int: for i in 0 to DELAY_MUL generate
begin
validdffLeft_MUL: if i = 0 generate
begin
valid_dff: component logic_dff_block
port map (
D => VALID_IN,
CLK => CLK,
RST => RST,
Q => ValidsRegBus_MUL(i)
);
end generate validdffLeft_MUL;
--
dffOthers_MUL: if (i > 0 AND i < DELAY_MUL) generate
begin
valid_dff: component logic_dff_block
port map (
D => ValidsRegBus_MUL(i-1),
CLK => CLK,
RST => RST,
Q => ValidsRegBus_MUL(i)
);
end generate dffOthers_MUL;
--
dffRight_MUL: if i = DELAY_MUL generate
begin
valid_dff: component logic_dff_block
port map (
D => ValidsRegBus_MUL(i-1),
CLK => CLK,
RST => RST,
Q => VALID_OUT
);
end generate dffRight_MUL;
end generate validReg_MUL_int;
end generate validReg_MUL;
OP0:IF OP = 0 GENERATE
-- OP = 0 => Add
INMODE_DSP1 <= "00000";
OPMODE_DSP1 <= "0110011"; -- (Z=C | Y=0 | X=A:B)
ALUMODE_DSP1 <= "0000"; -- Z + X + Y + CIN
END GENERATE;
OP1:IF OP = 1 GENERATE
-- OP = 1 => Substract
INMODE_DSP1 <= "00000";
OPMODE_DSP1 <= "0110011"; -- (Z=C | Y=0 | X=A:B)
ALUMODE_DSP1 <= "0011"; -- Z – (X + Y + CIN)
END GENERATE;
OP2:IF OP = 2 GENERATE
-- OP = 2 => Multiply
INMODE_DSP1 <= "10001"; -- Multiplyer Inport: B1 | A1
OPMODE_DSP1 <= "0000101"; -- (Z=0 | Y=M | X=M)
ALUMODE_DSP1 <= "0000"; -- Z + X + Y + CIN
END GENERATE;
run : PROCESS (CLK)
BEGIN
IF CLK'EVENT AND CLK = '1' THEN
IF OP = 0 THEN
A_DSP1 <= (29 downto 0 => '0');
-- Pack RIGHT input into A:B
B_DSP1 <= (17 downto 8 => '0') & RIGHT;
-- B_DSP1 <= (17 downto 8 => '0') & RIGHT;
-- Pack LEFT input into C
C_DSP1 <= (47 downto 8 => '0') & LEFT;
ELSIF OP = 1 THEN
A_DSP1 <= (29 downto 0 => '0');
-- Pack RIGHT input into A:B
B_DSP1 <= (17 downto 8 => '0') & RIGHT;
-- Pack LEFT input into C
C_DSP1 <= (47 downto 8 => '0') & LEFT;
ELSIF OP = 2 THEN
C_DSP1 <= (47 downto 0 => '0');
-- Pack RIGHT input into A:B
A_DSP1 <= (29 downto 8 => '0') & LEFT;
B_DSP1 <= (17 downto 8 => '0') & RIGHT;
ELSE
A_DSP1 <= (29 downto 0 => '0');
-- Pack RIGHT input into A:B
B_DSP1 <= (17 downto 8 => '0') & RIGHT;
-- Pack LEFT input into C
C_DSP1 <= (47 downto 8 => '0') & LEFT;
END IF;
--
IF signed(P_DSP1) > 255 THEN
BINOP_OUT <= (others => '1');
ELSIF signed(P_DSP1) < 0 THEN
BINOP_OUT <= (others => '0');
ELSE
BINOP_OUT <= P_DSP1(7 downto 0);
END IF;
END IF;
END PROCESS;
READY_OUT <= READY_IN;
END BasicArith_Behave;
|
gpl-3.0
|
02d65e45c6e916393f604a80e08766ca
| 0.425473 | 4.256402 | false | false | false | false |
GOOD-Stuff/srio_test
|
srio_test.ip_user_files/ipstatic/hdl/srio_gen2_v4_0_rfs.vhd
| 1 | 292,667 |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
NtyLCYL5/3rfRWX3XIUWoCyJypNOH9cIu+d+Hqwx6gD9tTUVuLJoOBkvN/BbGHIv+gHzbebnGJ07
gT9c2od1Nw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
gOvt00Uo43u2bKjWtQoTcla6e9cy8DigekFHOAFvmHLARM0er2069D0sJrV+Re+Z0pNJyi6G8RrG
7xF3eUwAm2HM7vum+Ypx+PLpFTVtAE3qcos/KdoFVruQ+2KR4xm6ct5GHE7I4I7kHpb47V1n3A7m
KsVZ9Q4Gj78XZiTnAcI=
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
ezxkbRJZF8baEvYrEgt01fk39VlF4Vy9oPkF/Tcr/ZSXWZrN3Ny/64ZRk5rdp3/Rw4mQWdsVpddN
NR61Y/lHKqyzIFy5av4Fc1hvtJ5QrGu7jT0itvr42t0ZsKBOir24UhbMtyEqR3CR5fLeSQGsmFTF
dv3KWzF70ty9bmZVSQA=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qGx0a/xTrbWGkdXtnErSWmLH57NqWqgsuujHfQ7lkXQ/8JEV7zaMMf6MlTKUSECLGX+Hvc0If1o2
8pSBoaczpNUPnVU68eGXWinC4mD31mx47odaV1wlH8fsVQbGMdBKqBWy9TuX5hg0WgT32g0BqluF
Ofaj+TwzvjOXbyxmTJFJC6smWfhzgJpDMFRCbwUgDfK0WLgNt0hs7vmOlNiRXaaxSMTGYh92RFiS
NxDABUW6vw4h+bGTVG3JhrkJ5qwKlmYlO4SD/jiqQmKrtaue8mcj0lTSTYM6SCCabd0uW94N/8tu
lzw529SU01QAq4RGqkkbg/FyEhRVNeYtMYy67g==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
g0cGT4TvnX48hcFZPn8fyr0BfDW/3mBT+7tkdfyWZShlmQV898cMKehzh5fGzmgpbgvX00nKxBTj
WeqyMahjKMWih08yRdHR3vNUJnu+cL6RFX9ce+T45X4jsmlXx/3XSRkdmnxonh8czuQZQRxMS6Qf
ofXembsqKBHB1Mfw0IzbD7aczjkxwFftGUuZ5OCU3B2FYe98Uxzn8zJLzvzLLD6qQ2ZHMoZA/Twb
InQ/RCbLhXp3ETIjJwF0wkbmIOXTthHHlTDEzXaE4esRBAX05vSi+2cCAm8ofWSaUHrEc0c87M3K
dgyF62TnK+GOK+n/yPM+tHzqnQJ/S1y5eCwMhg==
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
XJM5nAzNvkSjBrtMy6mR1RzFhNDHeLRKo6RsiRuAYypLrtq9GNYqKE+wyYP+Vo7xVBHdMLdP/8W+
MnvqKQLx4Vam4wQ7/3p6kO6JOKSLHgO7ujNfnfqKtGP5+wiWMQ3ayWgmNFExkMDOh15tsG7/M+BC
kP250ud6s5Rg3PFm7qO0LeVdlNevnOWFcNZmchQ4swQ72GBoyxzYh71u7WHuvzvMmFL6nu5Ag6sT
g2+Tuyl0MjRDJ2cHrBEG9/s/oPnSR3A8+jIaMFQDUdNMGg/gKLbDe0nvtFEwcxj3UItyerS1gTi1
knhxeuAu+zuveWwBMOLo3qGmEy9ucUl/jCOSWQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 214512)
`protect data_block
4QbAj4C899pCydbwSo3MApfZlt+OVDAX5womdmM5R9edtN8JrW6aHg6hviO7xS22cRUPnfYeeLxf
ymD3Usr6TCsYtRw//dvnxfYHnC8QjVGcmtBlDUD/B9sSMIIRc/o9xPOA4xgeW21riptMefWAEDcK
jtWq2QRzsHXSi7n85m+Fc+qNC/D8NY3X56HzHFYzUiVHpYAfwfNb6oZBi2GL7J7yhcs4pQ5i7YZH
PQ1I2Yz2x5XlEvsivfpD7jiSBF6CJl0rkhbpcc8PnGMshq1nFU3oKvFgmnknjoRBll5UsTv7VljK
7sCEzhTUYDkAiXSWFapX/VZUzGSQDaBluApKBmSrlILQ1SzgNJK82Syi9Uq9/s9efRSxBA4lwE7l
Ig0YSOtcNTwJvbpWXyCcO4pxzEdwSCHoODnPcVmyh/e9Emn385VmZjMmaaKlHJL6JCL/9wclnZZm
7kgGTOW08s5h/uXobZgplwJ8VN6U+OdS5sk+/+YXZQ87W5xufaFrlkZqawqArI7BDVf/mw2cvLmX
kUdKPih7X5/y5G+a/ka8gSl4ctUxeMZyM/DCXzestufh3zjQlkXIOSdlkGayv1Q15Q6VKrlQ3GsO
k41ivNtUeeqmSS40Y31m4mVBKJ9fUyIx0GvaYQgvX9+BsJv0uxh8sQf+7irIp6lmJAIkotFj3UQl
JLrFZ4Ciwv4u7E8P6vhlrAQD7jSadT4GiDBWDWdqsKmRQX7tndk8cJGU8txjPZoPNDcEWNBEhzNl
w9ewLLRUVWOvyziN51KQ08TIviVOsp/DWQAVgrK/qbb7hgsgxgCShej84zszGaDPf8598L+F0AFB
PukPCREMpuVcprD1Ez2JisanWPbV7X2VbOkJXNSdyXEiEp8jSDm0AdXgk94YfGFge8m2PDR2irNl
/dvfJSDQ1YFdEApnDdnZPlg5mpyEQZsTpzT4AEKsUJzgaBTCtAubRdirWzrgtG4jsNxG5NJEFnJE
OSyEzimTp8Oyjp7dAxN+pln6+Oww9Q4+1lQ8lugKvp31vxzIxPP1b5hSSgBdMREDEmbW9QeyW7za
gVI8S3jNsAJDvyNMXuBT3oNGWMUHTywi9brHxMAhV1Bq6XSA5Qe/ADzD352NQqnAVENt5noppzgM
NYqiD1o5W3GrZ99EXoNO7idq0uzdyDDgJx7XpSV9gVKRxmP999Znhslu+wb+ebu343V0s5R6sV8g
hoF7GTqx8LbNAOyumo/yZyTxy4z377V1clkFzLExQP3aakbmWYhDDltVXQ0aV1N90fqopyaStOSx
JKvoVFvAXu8bZ8meZozUoX9TLuAe6+shxeOCRpqo3cLVWasgtCc4/EK48wlRbqzNrvtudG9DwU0M
JZEzfNe1Aj+qw6zDrt0Qqq3+D6aTut2gVyHDsA38wa8naANrX61KUOTDX3vcv8sXrhKsC7Slhjn5
nMsuZpXwDmR5OT0/E8zC67TqlPeAljQArPET2ML+pjbc0ECkzSdB+utFsjIvkVu3RJTfnk5a4YV9
IJEV8d/4zpn/sMvS2Jvuojt10j15LWGOnNLJF+bSMUV6EAmL8DoZmMDVi+baP0rL8jDD4+k35jQZ
ks150zBcrO59ClgdekpGOYAJQ6ue8Db5KyCZ1FxUWIxc/fC7HSHb7Sfw3Yl3YbIDZIh5FRCpn3si
z+Qf4yTTbRKDTcxxYFfcpw9pEmcueKqruZFz889/9D4S+KpkzDuug9SshB6yr5GPG6nXDMP5ffiQ
LB2Zxgx/uK5hvcFVi5p4LTxJwOFgr+wA8Zo0nj7XWLFTpQ/DjVf6YUcGceXZF3VMfIYZkrKlHl04
7O2Le2cCon7MzFaywiYovL75Aip4XP8LnXOqqNBEn2WiQpFjWZh8uwhoOWSW0FZTdrkcDln8IpUs
B1svJm8n5OmMR3K1vdYhUZk+nJulWa63sJua/+lFPbAGiqmzS5lEe0/Hfy+ADp31rMFlr2pgW3Wa
AxmPBgSAUxKSzhmBqU0oK1TrS4unOMlPiH9ZOjDT1YEaUl7l0eDgnbgwaQFQ9X/xKqv7rGBB/NMW
VBRvyWIAchmOXd5+6YhzI7cAnq4Rxa4Tq7SCW2thw6Z/+AKvAQ4yqtz9qub+2KKIYVMjpee85nZJ
V4YYFCz5/oRIeQdXPXKw05LhCzabyBVxOG/BdUoRDD5X6efGE/H/TycDQ+T4BGJO0DxHwi+Kx2/q
9oeZqXlRnYY9r3QMxr0JchwYGNP37pb6MlIt9VE73IoMaiffXhAcLqhjS4S18pLb2WVRFMWmh/DR
28rxUeiJgjOko1W/4kGnCpp6Hl9SVT2UTMWdYUm7fgy+SqV+VbF57dxqvyWADXjs2/ngi3C8R2a4
dS3XsVQKGiaqD1odvZ2MlHbpwP4SQM+vEdVH+HRFcjc1sGXkMc+BnqxltxBHTSe9Os4HKfAYBP7W
X0ngjP5r167XCajFKfcW07p+bydKCaomjr6VDmn45LsgIPdOAqRMoOGrbiljHpKzdyJku8cS8fD9
EH2Um666LOJ16REd1ag4hAHUXh8sohYGClCy8WhQ8/rBTSwV7vvieZjuT39YaSnh0MOZbiXkijPy
1FbH95TmsuMqZ6kGXmjBZ2E3Yo7uLrisQiIRUXj3XI6EL7+zaT3vhpML85bLJbGcBeuJVfZdN+SG
yx961gOVrzuQkJg69TWf6Amgy/ALH0h6K4l6qOneXq449Au8CporjBhjvZ320aQhfdge96jN8jo7
J/dcwUUiQfsFe4kkpbxjpcCqrcEOjwGp8ivLgliURDLYs/E8unqidzS//A+valYy5yklm1r7OsQo
SbthRSYSVNRktQs118Cv/E5r89aR0wS1VN+QJBKWOAW6KNKoo18iClYQ4XGbLYSX/AxR9HWUNI7s
1SpTlfxX/doO0yWkCT339pqiLt0TfukUiRG0ogaTrVz9PTZghnueT03mH2zOHa82E22/5nTcvvBn
ng23WVhYFmpt4KdZBAoyEv5rU/OMdSzKcP280v/mOEtbA0FitXQUCIWpJsdRz32ieoFNlYauQawl
myQRC3Ii2c++H9u+Dv4CbhT6EhijSMtY4Ez9qIQwXDc4Ky3SpUmTzDju5db+iPPFaJuPZ14JUWu8
aTeNOCa642FETd+OU3eQHpzRqoZ9Aqlqwe4FPx0ss4hmR1sIih4kzomILpQ506t4ffuDXyezgpnE
czH/cX4FVtpmNTUNlc3Kcniq2aspRCASHi3oCPeN+zkxS445kSyoci7jXwP1N5h5bTRFgpLSeLFw
rX32YPYKquuh5/Y6THBEJrJl07ILOHfmTQbiMGIYs8CTq8zR9Jkvxd/z8Lzu1B1/OVsQ1kJN1DqZ
do3Acab+nVG620PXCaCrfdHxE7AIHdakx/IKkHWHBTUmwFhNgfuSH2EDk7O93DjFRq9fWw/02XAU
tpAQSVv7BA3ZwuA8AVrB0ystkggQNsk9sCHcxV0uC76LIMwF2bsJPOCHcU6CjWbASz37g3xjNR0z
eOgcj++RZBxrwxzrj7rJELuug4dQ5MpNjN47AHB7KXisWq8YSFiKHy6/Ep4/kuNwO6BJhlTkWCZl
y3PC3bftd0mIlE38EinYk9HiZT8krsBRYTd2qk82kjrA4DKV/1KRhRGU5iT2fAQ2gtUKqnh7tLFR
WinAvveK5zstAekBqo3J1mLLTVpmfYBbc5002pAxC8zT2YTzyVN3t0Np/bNb7cANLDq4fdKsScOJ
GnWv+JaA5+HMuxqEVzEjiicKtitdDe4LxZUSCWTSeRnzb/Vyyjy1bDzl0g/qhG4i/si/kETpsg2l
9zGVG62nc0GVHQmEVD7FCxSKnpfbtHg+4IhY5tGqqGIPAzYMKfgYu3HSk5TFANeENb72ArdnZZRo
F9u16frugntj6L8gfu+rbMIju6FGiDqOwY9oZkW0+DjGobuDNcuHjctm8Ht0QaMOJw9NFMyMMUQi
H0IHtsWVy9DwpB227tceEe/RLnlWaS4F4KZ4eUE9WWpUwXlI3xM7KR1Eat0Yjm3j7LC6g+BadGGx
jCtfhudKpya3tD4W2oxO4LAgony02HS1ibbm959pStWqhvhpAQExkEhN9dHcSrL9GhQ1CkKtTnyv
OB0kPKFtlDZ/+4qGlxb+j3yGoRaqKej+Iw6+SRcVWZCPmNtm8O+qx9VIR92/WdZKCDB5lgZ89mFl
pAl0AsZ+G4/BvXqTNhB3x67e4xio8utTzkwjrX0zn9P05imB1VL0Zu5lWTqCFeIqRH5/6jmCuLbh
gA799XQ0Z4kXRVVhLTF0FD2qJbDLTzGvL0p2K8ObMhKRkbS60DFLjTmTnK00BE/R4Z7xr43b6frs
OOMi7niaDBU7dNLrNuOq7Vptm9wWk1k9Sm6r5glnzfGNvkIF9GOFqYQgOCphqVJACUkJvusKDGxy
S1VVAZAVRVtH76ZyBEtkifTCQsUismJ47xCrRVHoY0xECqS/sHo83JO5XcqqORtYGUqiq48LAexa
JVhWKnGmqCPNDzTFxHpzeWP6WNLYKbD3T2G06k//8+yd8T0d/PFdH+7Xxflukj6aiiYEklXqqBYF
c/DBeFWvZcz98CvvkV4SuaCwBhRq5LdlZEmbGbG0KnHoJrE+mwWsYUals17Didkvr+fDbKX0ps+T
3IdzvH3BG7O2ex4MVYWXHUaI193euBFSwmLbze0tCKR7MZw9oM0FWMZS65djuqozPRIXSi1dRh/k
EbPpUy8lQVtP0RRFv1Wke137M0ODHKzfmjNcMV76Dqi4vmaKlnku4C4/FVHm73zGrICryGkmOV0Z
PVFF17317oFJZuyQ5B2h2zO9DbKsVZg6a01VQaYdZO46kMytS40ibo+qq/PauDB9WA3iS472ZtJ/
45bWchQJEuNpbR/p/mN61lMGWtftd3398Hp0tJzndggaWuixRMyqy57/9/1HdOl3SkCu6LgLJ5DH
gtnk0D7Xt6DlctjvdGH5jB6smHOWxK/AE/92Sak7dkoPCj+uBsKycpy4U6y5EnWpB3uJ2p4KzQSF
yiN/gcXol6tLr1R/QMX/hsSnA/VxeI6dKpsgUeCK3fujbjpcQCkzsJEC3VAsu2BVRRoIIZYIocl3
VaR/wJTNp4YbI04H0ZKKYYhdp9rZbJ9EfJ+JX21wZmaO6mW4LCTDzQv6ZItNjpIZBqKDBcyCKO4O
tW7lj1SbEdkQ3AqHNEZWc6Bo+Z2Qrm+B1O4n90mFGLHbPtf1CiNBxcYt8ZLiePgEjI1b/xFo5xsq
2pRRSZqW7gk3B4Qr5eQBdoPDerINUPfb/VfA42EDLf1G+Rq66zElejoVLRVLK67PEGvGdS5ngHP/
MMi1FSkpkLuz5qkf8Wf9vjYUOTqz4JnX44L89ryCLePn0zDmKlMgvIP00e0fo7g3cBuT/qsHnWNe
dBsXS4/t9FWQRY5AQw7/QxB2MSIXA/QR7J8GfG/nNCSEcsVQdEZjQ5Wj2FimjSoKio5QBQ8Fl6K0
WvvO/63DcdVLaOeUW8VwssI6sdLvr/Xku409FNaXe3Oe0KYBwcsjuTgAx5fZEkpWQNFr8iywOnXY
gUO0IJD6l4ADgGAp4N+eBecBL2R7xIIDzKM/pjcow1KWCN0MUe4oe4hPACDoMUT0RWtoSC+cMICi
RDtdJqeudbtrhXlo3RFRPMr8dedie2SgHdjN7qA3fzgHT500N1+FPYHeYOaHEBFG085r8zBdWs0P
9Aqm16deE1936jtwsS+ymSGHBtJ+IHqnzdjJtrGUZ35A7Cu3e9gbXw8QPBZGZaD9HWnfEEIuGzhT
xkkzaVwxwwBEWPUygOeBHCTmrCaJ1C0jIb3IJ1tBvdT8Khc+iQhVSUM7p41zjQcckA57AgZt2FBw
e6x2+qWm+bz4nbJmC3JnO6vfTxfks7bPaGdma29VDtBfdu9857SVvrlSonmhgihy1E3F3RktD9a4
cLnrpXanSnfvZIozQCkK2hTmfaBp0nMJHurZbgQOgAJkduL76SpfbVs28OnxZL54o+VVtXWE2GGX
tD4pnbQVg/GY530qUh+RsA4UGMVeiBK8AOfmedYZfn2VUYQYS7avik5ErbP4ka3kjPzoSu8xwbcT
5G65hBqNH2Tc9tuA/Z8pCKD4TBrITdcGgPSkdBXFHxurwM4djQwvzl6iPYWCjVv7R2JW4K2D1Njt
W2Hr4XHoz7cIlB9+8N5cKOR6WMS/bu+ewj1P6hKvIB7KoTUmJmvp1Npgvb6DbvJj+PU5OIvSHbz0
ZCqDd1sgQhuBDwLThDvuWPM5EoG4PTyPiJhBbQ35xRcP12zQPEs+FozyM1nlegIzEmze/5AhWHjQ
qPw2ZffhwRdw4A6vQaquzAvLOWpfwv1wfLn1RjVi3Mp53tzWy1jVYos+aiR1U5JeYtJf660JY9al
lItPqrEt0Zt7Dh0Y1xzpYfAJgJ8zgsIBdYJz81AKMlHObXaKqgf7mvJuo67vDIKglRc7a1C6s9/K
hJ2L5oJ/Q2RW87cqYo9pE6Fwz31TKira4D/MB8wNa0pKUqe1na6d3AdQxuFMuqNfROPNCgTJgZVp
1eXtVLHGw7U0c1ao5pvI1zRj5/JFiY0Hj5HzB0S84km4/4+Q3jGr2ffvsvmUarxBHV+tXmC1ssjT
nbj4cD3odrL5bQDYbKXd+Q0QAM9HLiR6ZrxH/w/yaLx8EGNrlUp7VgKFFwR0JMxi2ivTaKMr+k4E
GAAxfRDljyGlMg5K7iKyYeRZ9emwPUh5CJCI4xw2aLDy2pyyZjzxz5cmGjd5xHpfHhLeNNMmUn2F
WzD45sPLqRF/jZymMcSWabFAZBMCg6BEJ1HpisJMMWAqojOsHrHeRVEFJ1WJIHB8X2B38DNjmPFR
SOWNUDNtTXnMXF9FZtAFBBQcRRxzADiJgttwP6haMhjgkYR6Xgo34ozSmhgUnpGmmAmpoA6PbXu6
YI3EkvCOz6ZvnBznX9l6uLjP6AzMinVlZgq5PZCGnl/CaD/kfbl61sKTSKyYvl7x3fvAtld8br5R
5W5sKdEP+kC/6ODof/jZ25M6MDq/fxF8wwB9TCi9tOPiZI94c9uYg15Lx1i1q+BtCi1wbUKvhqNS
bo/TAvVGF5dIAYIUdgIopQlhb7RACHX34hlNGlzsxZrt4StgXajRoP9kg5F4nR8kosIp30w1LZTe
bxgxhRV+MJx5hGvjx/nhzN3nQe5rmEpaNGzXJeinh3G9wcMSi0Ybsd4ywRW7/yZgtCBW17x9LU36
H4PvirIyrW00R1l72lnLRX2xX7STbMCuvVHI+EFEsbJenYapcYrW0wC18FkiVHfSkobpn3ZHPMqp
PTIQUeEs+j9D14+HYWkCjxQjJyfQ8RO3mcqRguf1byOxIm8mLSNykmQhD8LwsYWkYUSBfinMs3Ze
NfpTN6U4WEkV4R2bv9E8caTVBbtK2EPxEJEOqA06U73Jf6kvoedLLSDkZgZaMWoNJjmjguJGNCvv
1gMz198S+Ppa+jaxbECWOuelgDv7IwN+cpzWyiMe8ZPdxsj23VPuCN2nPhe+a8/FMbkF0Uxqbzap
mhyC7CSQXO7tzwQm9ygEulMiSjS9qlouiw0HHUiV3T1qGCb+h3g9+3vFpV3q99pssSUVJNMRCDm4
EQGrlpCTXC9g4NUHyxxhlLp+Ud/kt3hQlVFA8fiOUTcn4FOLAe8kVM6T4tc7R3ea8NcqMX7+mhhq
QdlOO2yC7Tr7aVUE+1qnc4THouVGMxH3Wq1N3hcwNUAhqZS76/0UHzOkNg893jLLAU3YP6UtgioG
gNvctQA/Hh4sxgk/Mj95FHzrI1y9dpVSMi76v8mfNYz7h891sYsWd8NrcXumtzCDjQm1JAsB2j1q
hwaAVqFLy0fDdHvIKio1oVX6HG7dygo8t3CbjroF+/+mPD7u2DuWNH8dCtAKO6RDHsTqXdY44g/d
/Pmgaxt8fLMQlCviNtQItgy2AlqOJnRa8PyVjNb9S7ukCIPF8qm0CHk3TpDkiv57L0jh5xjGg+pI
B385xS1D0NFCy0LcA8VM3bBZrZovfhh0Pc8KbR5IWUC8lMGHgl4frE6NTaujaqedx569yGbGNuDP
7ILVFud7546vaYtjiFqupUkBZlwtgrD+8RN84Hb602nI4a0RtDDfp2GDL9nd8Iuxb5llGhx/Ep8S
cZxEAg8reFvD4DAVGLalnKAYWgcc2Mx9rHloz9MTURHmIwIXwJDdCTRqzQW7uea3JqF1vTpQXkR3
ZUvLubrYEgRqByiDQuzFukWaBj2xCgd996P6a5k95cYdtf3MZ4pwUuTAC0P9bT62ffhsTWH5xiue
OoanYyNXzpDXBxWS4MBLkQw8cX5dnBKrmG5jCJVIY/Dhq5ok9zDcE6RKSo+aVtadahpA3g7leXlZ
6LU7qPFbk3ZnLgn9zaZcff2uw1ROMdrtGyZL7JIy1pGOU4UB7KVr7teM4tBG/zhDBPhmqUDehl7x
Xe0Erc9HUMrM+jl5P8Q1jnGLp0MLkTfOpupR/HP/uBdFkiKm2N7d3gwNv1lynKc1AtoFfb4aQUN7
J8/k4VeZK3hG48TpfWM/chmfoWgPWy6/oJkbouS0exOa+efceVdrxh4VOGr9Cva50wEiO7qu6WEt
6eQp7PoGbV9lALc+u8qd6CFjBb1LjvqOfzr3QU3NuzRUIfrDh2MKs9kZaDYpSvj2qDiOvdvxaRG4
vdKTXXKOEs3R6uBySN/uwRzSgQRovKxILDXkoqwmo065X9kT/6OX6F5PVzX8uXD6v53rDh5svZbO
qeMqIwBjqIwDtWzX2pceVvCYr2HJ4yfQDSaDL48gF2m0x1/ZK8nP/sGvL//q/eVDyOLO30e40tFV
WixgLejAa108EkwoJ5L321gmNcJS96cZC/oppoBVTTEIskoNw0qUItV9EG4TSgr4jAwNHX+N+3mP
AgLVmR3J7jK+FNqDe05I6cYmwLX8IJ4mRV3c10y2mx3o3MGdb9vnKWzMtiiLlHxszpjvXLRxIcGh
rCcBis0d3Rc6297Gh76WkxhT2OPpKBn9eOCVXmFuCMcFxTsYKs+SJka3i0rswkHj7JW41z52tJqh
xo4YBvCRMA2PgAaBmqZTzmgUqgx2JCwmTqOmGFyuKhffkNpr10mU5Fb918DAfAjkLEX8NHmch94F
0rz/Ce6cWT27cKMOXRZYeupLjGF0F0KhAhUUWdiumANdsTjwZmH1iWI5TUpdM7ZD2n0DbNTTpsUW
bkPLxuvjkcrm7AbhmG8CxS4GMheeJd5nvwjKMIRWuy/NYUi7jnEW+9rVXLTOyK9Ef5saYvzWbXgk
otjJpPsCi7B+EPLfoH0g2hgK4JgF92FPhsJ1iOpjAhJjiJJw1MCj9H6t527oyn+SYIOlyMz89fhz
Qmgqtkr5fNO7TKZLxWhkSxrgZA18VUDAbsLXTg13+bTR4gRPhHMLp8xT3EcLeQlVrGB9UMZTTwhe
uEVxBLDvXk6P5MFWadnRIWlGO8yYh8Xl7FXlhE1qlNGSYBvtHHnfVm1rMSDClLU1BNNfBLz/3zKA
lDhQNz53Gw0YrxwI43fxvXSDgMfN3cAg9JMkWyNPN1TBzUvRVPauObbXh2ikbXjq2slOka/IfYdT
gK+cl7+cjY5F6Hsk1Mb6gcIkKH09Ji8qXcMuxL2gV+LQ/FR0rU+WGPjaLDhzNp0nhBDqVDLjTcEM
geByZzWi9b7+2W2HaYTiRV1kBlUEHbhxJ2SgKvu4nPg+snZVK8qIvv5uKzmw6awTizPB+nKHmKsv
q5tEGba2Qd5diaQlsDi8Ccrv1IPjvhEb7cRyaVSPSl2QyQJhwINDRh6W06QKjhMP00F9I3hUJqJ0
zsbHpS3p+dP7r9n+olb8nLyZsxgzZXfnAPsBP+hTyOLa+sfNn/5arYAsBROSg64/6+rsX3J4tKpw
Mg8RsTqpiGnLPPwNRLITrmzwQ9NQAh7vnavilOB5yFVHlbm8qwZIo7J7Nkcp7iEyYMSCd26jKUou
JgOdHIwYP75sIqfqvuwg8YqZ9yucpSBNXBmQ8g3Ahfy5suw7og+FPKBZy3rAmZVY/Ak+ZBQKsdoN
JYpl0yB8vnA+A8zrCfslCYMgHsQmdJVKYKzNyeeLFf4fCdFlwQXtwPDN/Arm67lxF/hM10Fxr7MY
6x6uEaJTIXrOSfNyinuQTtSp1uzROg6wPi+QtR0srDDrsbGETB0I43V7CIs2k/ae7G+l9oMhEZLq
c5vSwsLpkx5jc1McTTlLxhgttrRZ6t79+CizWN2piKuw2/Qo8I1GPy7LcheBngSxdypR3tCUWRLs
+MisiR+TRY9Q/8HhyczI6nMKgRaG1kWsWdP2KIfO+WYDVw/yM85uY1LApf//wXvGgMwGUpd9qFdS
l5bQacYwUcuEfraozGNp5aWzUhQ1Hh57NkCnWztSskTUv3z86JWrc1Y051/GuFanJkFQ6GH2qmOh
NvWIy5sk0QsGzNCLOVqX4IRQD4zxYqWA8NFLcaKqfqmWIPv5julcUTQBG8l9EnImHCB4Its9n/eO
9EJk3rEvL6w73lmoMhXiluMg0AFt4G7G4/1ISnx+bVYgcIlERX7CocUe47dJDStXeKWnZnuwnmwG
Ro+1i2bZREebdUSvY7iTGN27qGF4qEQICGQZEaDPZolzPrCkjAtwBxwvpJMIc3qvs2LplyHV5uA9
OuggCzqmFISn4kmC1JViYqHUtJgPsfnWEsD404Z5N/gVDT/vJdCLJOOOhPgTptEJrdtQhOnmnqDW
3R05ZwfQiesK1+0XGVwHkZVMOfvm+baKfvmqriNQPnQTgU9HSsHOyuqhfhnePl742zDB6atoHLm+
5+QPOIBssTHLq2Lo6IERRRPIN6xAglvtcfZnespSJyIs9HvtUMuBm9M2PQpXOQYi0Ky1S5H1wzPL
O+pn9gjmP4hrvaKrEu12ACCsL5csuOIeNLoZm5M7U6bO5mNZgvBXf39qx3IIQJHiqUITOnutKvQk
A90zfQqboLaZ46c5mvh4xUC2tHvGOFfWm6UtKV14ADGKKNd/xGZ8gamO7t15ASNN+cC9xtWoZY2P
98zHzg9l/ELwFWL26kBDHytrFDghrWOorWqgJ+hBtUleKuTu4fR3iFYKoA1jnSYORCUmHmLaVaBq
7lsuvmKfrodtcGV7Kdo6n1peiPhk0mTTlVTOY+kUFehkEnkYzhpJQUp4vfvibPFpiEs2OpSC7UeV
Ozot/7V11C+iSGeASqo4c8SBRB211l4LRd+P28NCHR220ZcKsGAMGMGAhewP7JknjmsX7y5/RUkJ
7Obto+ezbllRXmoShZNNpAXb6Zovh03a8uFaus+qSfrAPNp7hlc3u+zwgjQwSlUttFtJirhcQIuO
dSBni9CX3JVD8+RI1y81V480UfG2NfQ3ZO04fGi6byospP6TmlDnDYMlst7sWflxOV6cOSVB8yKd
cVt8LWbYpkTBfzSPgBek6GNhQy8orUj3FZuXMII10letTl3bTVI7YXNxfUCy0CQirzx583r8CA7+
BlL5ZYywFTKHEm1ady1AEh9tbwUraFU6Ix9FVMMWKhVMNdDxCBnt+MXVhfENDjhWJfPLoOm5OCTK
sbelsKJpaqhBiFRFSEuBmhTItk3iFMBmvM2ayskKsa6n86KQacN3/Ulqbg11vsifa1iH1xx4gARE
u+cf32uP30RAYW3n5G3K9W0pgF9LvSxMcYrrQQpQLTEFWjQxPJ6UFIA0VNtLHUH4a3X7bPv4I5HA
x1Bd5XyUZfhEtZGIH4THkqorW4seLsxQfDq08QrU0Dp7T7jSUcbdfQmQcOuLXUt9AER9LRRal+ww
rX7OhcDzINtSglVBWGfd0NXrE9NfciYtG9AncTN1Zum1pjmZxyQyFlFP60ih1WcBvj1QfzcAu05d
gxg+FtMrA6jInVFk/a+NlI2Prg8iBUP3D5KqNmXIbbnhjcB2X0vMO6ltToab+NpNMscUBr6CezUB
zCKK0oOAgFwOAK9zQKSRay+n74eBuo/g0GWylH7UNpMyTDRyDiSlWiO82gT7QaIiXv3LwK/+FLWd
PBNVSOKf5Kq0aJ0ioLR5FhjpuxZNKmoenjSW7luzqFls+y7DbFQ7ul7+OL4IBIcG5bxNDGwhJH2L
lpDR/QLqTC3B+OtB3850JBbeYTmHlU5rS+4R19kYHHbHUzWiLdsdMQzfHwXlBsVr86cxUB5TyKPI
P+0S9h1q2xZp4QrsQ7oqFD5YIM5la+iVSbgz33lCqt8oZZQCDTT7JuCNCNeqE+HNtjgs5IhqsO/q
I4aafARQhdYNbm2dOKqJ1Chg5tpwQInUkLBkwD+U5qnHXozPjeAnlOsJVxhhc5K6nNfD/xaK5BAu
dTkSiOgF/U2uDDyDKrVS5W8cwy4xhT8H1W5/CL95V28XCId+3XzYhDUfU7sHCuCW80mRofV1cdno
JC8fP9A04gA1pZxoYKkIxYh3XTgxc6r5rVmGD/0eH02cFtcGxBTaORpDvZmnTMy7znCBfd5FhlTo
x5gyj1ORxOQ1E8BXLCYu3SwO2RyN2eSQMZha9gKrThDzdj67RMpu3OQ4kfQprr2GS88Yj50NY8Dy
vjhvqtbrBe1ZFpN70rTIx9yaJy6PzM540YjX46bDdb1Bj6c9Kf2il6mRbhDl46sOHA7LOUNEYM4E
2TgfHFcXyu+h/vdL6/iTRP7GLRnmkniPu3PMI3IYr9sWsy6tqDJfIRsT57B7wHkaMjGvUdhuKQ5p
wSOriS2yxxRrxVbRTnB1wE1UFO1GcWdverMEIRGbv7L9Ch00VZS2l8wgooutIEVX8nsO1hq0xklK
b2hIv8lAKwaSvAk+32VQMNykNt4z6O63hlh2Rf4HA+uLpINf66zO144G4zssX0JVfIDWxtGgluQa
nUB/6AQvdqPMsR66s2mcpfGwG6hGHJ7Us+cdh/u6LxaNol3/gD7/KBsX1CIsDOFxN0KfAxSG0kWk
55TCYSJtDZhKhf6OzZXj+OhJcpHwVIxmgqHEzLeMoX8Rd2Tlw55s+jWEmNf7DjB7hxFCcP3dDbOQ
ufFcXMrKzVapO0HZ2Njd7v5biOfq5kdgaDgyHE7V1yAi88mQUKZX+jGF9whMmINM1xAbLxM7QIsx
ET14SHxKeLy82kZoySOhY42CwbmXpUjMYryUWViwfvWE6LTTzuWJ+6MIX6vjz349KN+F043gqTKs
pVIn6c4c0et95OFg417e5goQVzjh+11C6bNa177543QhYsWT4g3nAa+/qREQLVDZpDuoSqVKO6El
5HavKf9wzXvS2UsrkJIUZlFBa5Wy/9C3wHIry/uDnnKZ1xggm+rIW7mgdimZhKb+6I0u/WAj6fe7
4m/k0KTHCsT4W/iWrbe60dGB70B1xBEMQh45zhfSsGVS2nGR7HEzmYEnkY0XsSo6HPrR80QCPwCl
d8Lw6qyCWFFzqt9sJPZQD3HDP8twQITVY0G8On/OhOIy45WhLfwBtw9Fh44b3vJP1dzRGjFWgiBM
KxePh3hx5BA/Rl/p5llBKXhrFyL+06zn6bUYoDuvvvi9Rv/c6g+NqB08Abzq6wZEPZRnSh8sLzYw
sCnbE3gduPjYR3WHzPhsZ3VJZqM1Z5B3J1xycK0aStRW/3Al8FvHxvu93zj/ew/WqJm8PN4y1M5G
XzH/UIvRMWFjsiiHedqrBRiS8XeM8/bLNCIYXHqFAVbZj89dkS9i2MhFo6Hjsh7HAAasV9HiSLIP
JU5qsoWg/VpeS3N/c31YjS8WFJMrWIKeyXrKCHGmsRU909zad6QroGMH9Xamj81lvsR9unbZ6NEy
nWINWl8zp2HnJGite9rOYv35XThtFVTzdpoFZXuImddWy9pKo9060c7G6obJOTi1iYdIn79MtWMB
foN7kRI+PhH3NH8E8xA/2eeh3oA/CzERhhDAQSKRJdP7Neot6+fKdcQYV0FG+8QQh019ROsRYwgR
XQt5nnNhetKxqhH6R0U+0BJLwMdbLU1WlgUeP6J5XNU8odhOw66ztuo5wkSuL0B5qMcAzNdkRB/1
kB6cDuwMAp5cIZYePxp4Fq2YU7YYTjlwGrh+z5bsccPyIYa0ULFsDDw7le3x61Ljpf88MFHEOPBo
PVA04ypttwK7lohyNfV7dApjMuYxVzkugA/LOKgPnUEyIPkZqWzmLjyVF7CoZ06IJsn0jhTK9UxM
JbNWxGvcB7tjFPdDNfLcIMLDUd0EX3hJ7792VhSSS+I2jCkGwixknP9U97bTvM5f+3dKfL8FgSh8
mjAcBw3SbGEvuP41TSR9uaLVNccISk+qpWP6Y/AesWWQs3BQ73gwh0DoZ0OSF5eymWNWFl3PWF34
ndRJGtVMzrLWsa3/qfy7Gajw5hZUTcKDMARs31Rky2ZiE/Qpi56c/AG7PLBpSF20zZL/YvVFk7wK
HQ/NUKdKcOyC7Sk0il6vUvbdV2wr0nFASXMtl080jD5nhgBWRW4nHm0JDOAzWbqsFvII5/tdBmx7
0vaAQqxgr1JzS86njr7HOyVEjcJ0Yfxi4FEmfGZ22MTl8PcgFOgCDtzE7pUk5WW1+BnPae9WN69G
CX7F7T+yQdl79/V8xv949QJ8gcm+NbzKoBFsfs8hwMcMebJ8RlTmKbQne9pxnZ4Kz3D1heZCVyAG
TdC0yxAqSYk9acN3RxPiMsomy5kcdUNtB5otYtnoy8ZI9rf7NVkf/m72gW0hLPZ6fNyYFcyJqrcr
7Q1iqGGqbOWeQvhqjRKl77xsErBLB0FkCvdFxKY0ybwby2IvsCSsCd1ml/NHIsqib+pCIMpNWW/u
QhcKAXRMDIYAk/N3bnXWDXyAuWdA34z1Jnqo3yL52y2m51538XbpeNBYbW4ynAg+QlUEqOWtu7ry
fsqx3/BnAeVi2icf9T7SCcgKINh2y5TThibDCHlrJzu514akYoQN4S+cxsUdHsuxyNW8GW47yBf7
OcQc8yOKB6WUx8e3oRr4EnJOWvdlpaElS8D6zSxqdI1ZWlkTz3abg9Wm9vSSvioGxL1ir3Vt4i9B
LRSj6ZqSjkSJmF8PBd4JkpVCTp1AE4RqhQXD/53BxdN4vgo80vZlChCFygmw+dJmhbcH2aREh+4o
KmZgc15wxW/Vqc2If3/ShymrxZcwjWFJ0wBU216bW3VgPXD9FEtH0P3wmfW7LRoT6L/wwdtug8TA
jy3uWRi9YvNcjqLox52ErD9d2GOeyRLpsnenyo7quU2e3x1yRDSR3ghtJlpIADf3pYaqbPpx/fGv
+Vqm6wU0hBOKhDsuQh0XkaxrgPLmx6LicSGfpqSIBVaVri1vTzpQ25XhRFWLltuSkacQA8tXn/F/
q1DfTwRGomkqzRrg2caLK7lCfn8gv2sTK4nGFBxkF3YVs5m1fSQ8BQBpmAc59PE6QXPrafbIZnhb
pDjxgHruOqs/6QDVcmGtWrBaFTRP/xpZHgdEDwgYWfNxDXMCnLdMRDxevjDYe7NIKX1vbsdqegNM
y4GzJUdVyJiHZeE75tJpos4EfZ9kcphIppQBqzenUvHFfgVMkKK+uYrpyu63uHkWvTxD2zf7cfCP
BwkIucx3W6gC6yjMD8Kr4kuVDtqWjBlYb/sGXmW3jIRxFqdzMPRf/xqeWSNpA9uUYTLmh8BScXD4
WlVzaLDZWlqc5txzu0IQeG7zOA7maV53WhncpEQZesKtt7YirGaZjxJWAk/7EJ3H3X/9KCd3h1Ij
C2jG2XgYKb7X51pGC4bxY09RxnEr+BqGM9Q5FHw1HyCW2zQuhBqyk6vy/++e66JGsHyWwuIsxCV0
tKF30BGUzlIei4qjPQk0epAYukyPSu8vPyts2xC1kWu4ZyKoXcbY+gvrHKV6v3e7yufDI/WSvL2k
evOoYRM2KPbugzL1b60AiDywHLxJ7zqSu2wkeDxp+w6OBCy9rzI+vXCCksN7iV4VnBMwDmNMjmwm
3AnqZBXUWpQKog6s6FYgefgUTqWiVvBNox6CXT6i71nLtIwoylS6EXOvCC/yMqC0OgiUokSQNxxN
ycmOHdjRdMYKmTsPgWdSkvXGwvXo6CpHiNxPR9f4pcfULnzU5FNnE4TPlJidtbuUVQ8/r+k4qdcC
Lk5C24ICQmVyx7B68E8yp0fZE4f/ztp/FWPQcyeKOgHOMglYUzkBRLOKnpU8NjOkxUB/PNzHVF0e
0OG/wdyf2HUHpcLYIH+K4uAHuiIpij/S6Xrq7FzEVrQgNVJhucj4auS0lky43i7SlirwUhjU7LrQ
SOex0+bxBJBwc+gfyG0J8wqwbtc36YdrCjhhbPQ0pt9yLkZMkRxhSRBasklCJhnUGycfcVj2gP0i
w/FDaM90AwjRaX1mzDSAMwMtFHTzGUr5Bh5BXqwtMk5MrCdicq7j9A1m/vhUgoFnIliyE++st3mQ
8YEjq2BFh1U8UZnlj51S814CBia8w8KC1qvdL+YpVwIpZQrPaFyPmD+a86RHeuenr9hGv2WKXQMV
L4lYEME5OGIvTsF5KwA7UQgECaoDdIwQOWEGMkrVpFSoc9IBVGROXeyj6cAmLiL/t2ndDmBVtuKZ
RebSpqKyS8zJXqG06v+a6jn4Yt7qzxDt9OKmGKgPXcIZxtyrY8QAbA60fT0+vZ7o7GXD1J9C1gJ3
nxF5fmxRqG7ZdhroolJrhMZSvOivGgjLIjKDabN4ZHkMTW8kcDyJSaDizPDbmR5cDTL13sTd8h6j
kDixWlY+W4stRkiJlhdB9iYgnlPTld5Ks2fQak6lzhS5QuunjfEP88o+viNVJ28rlhCtSZ26ywMb
j5bKIAItRcAGZpIQpKDhssmiUUjVT7M7qwZ/UooOJlO0twtXvh2J8zKei90Zo8jKxLMdNCB6JifS
/G8CyLxiMalBGeFp1rAPon6Q/9lxBpThsIo1Kdj6qD46FZzbqoIO9KU9UENYZtJLkFJDNtVj1NuD
SHpBLYC9RrbRUDGWclPFZsYJajSUwAbqkCKd+dLy/B0j+c99woryJp4TF0AVNzWtTh3imYC72fUg
PwN+syJehvwzusdNTqAII6b9XSfKIkg+MZ18S3HI/F4GZhaSCRINzET+dtHG2EFLRao5dIZskD+9
r2FPKvhsRhxiIE09yZWyBz0xmliGADxCa2plemQyDuxfLc8qlDcbT9wrc13/CtzW0riOu8JIw6Ss
oqEFQLJlCV3rMb5BGCxjP3dQBWOiEG4/ATd1oM/XBDmZW+vmW0xGg2cYv2sjWN/kMFuAP8iKJG/2
X4XWSqgwuLyNElFZeUaa15wNZe1msSgXFwKjSLGISZohrasADzdGBHq+Bhav/eifTJzG/lL04xck
/cMzvZvmwOtFFAqhTzCsC7wyRqzrALZsQkkazWst0ZJKJ5IjXBvxWkP2QrnrzN8KmalkoEexDgIg
rXIGf4nIMrOr9DW+bGS8Csf/p6RixqP9s9cE7gEJzNg6vZ6y74xfUTLgN/xwwuBhUcAlrRRHgM8c
WXFiXBH5OtD6+SrsWa/rrqxYb7lXMyU3/Z6ZubqbUK9eM2/yT0s4QyNMGh3wm8L+wagCuCPnNcK9
szsw1HtQ9X1b9e2+ubPLYzEB4aE7qwHs2fCevUFndTNhSubUWE9oKdArYPmEKVgFWgI6tVnncZsJ
tU+z4WJ4TPRYwGEKSBF7S8mwzePqPId5IupJopMvagETXNO6PATGBLFogh/kkCKVNe5s6fnZKUax
qKPfLHt6zNZtHYz5yGLv+kndoFEyEMOyc/nQjEozqcKIk/Otg/sC/2FwZITfHqvcDXsRLIdZd/d9
fEtwtxEGyN9BVsIu5Vlq2/MD/qgXRqjgYGFgg/LLYKyJltJ+mzKpc65fS20OwjAHRvTURpmHAZXq
i85hgM6D3uch/ScViEGgx22Y/l5tUgFV4SeLVATXU7o0qOutiKurYB5d1o+iwS3k6guIwP2hdLzA
2puPq1RHDSTGzljJG6z6JEA0/bH9lSyMWwtSrazyAaWVCuZ+eLCrkzx34qH6gaX7shO4scVYDyYX
YbR616DCSgsCJexeYslizlg2GylaWpAUbIBFbnVExlUAq6bU8xFtGXKOfIa/RZ1mJcUaeBcO1VWU
37lOvr3HnE+BhZIz6wE0yH0gkEb2rix6TEjsBlkOekMQ6IXhvYLeY1V/nexlX0yp+ScUEch6XACX
PTt6jP74xQLdf7APa/8BWYBaJzP6dr9ztm9a2QLULSgJ51KDRsmINkpMsoyws2S1V7e5uWm3crf+
zyz4DNbxSXW5KogO+olITySdZDsuzRvP0iIQMNHbTDU3Ohc+/c7Pjgt0+75o7VV4aJ4C9Tsph4Te
ZzbVBqKiWvNBhUDaXYRanlKdm3Kj+0qhMCBLeaAX4mtcoGsDHkf9/k6CmGRnhcBEDFqMc4ax03HG
uDb/+LpiIhz222GC+bYbQh5yIv8NZeup9ck9XkenUb3X1hCNmqhfTberA2Q4F1tMvfAIm0ThLfgu
9MVSfKiALpbOgXiXpU3JN6bJDmc7HBoL7byoDNtlFkilkVhL6PUUcnYkoE7LoBJSJ3rpGUHriXC2
AMnD9+ilno6LdESvoN0nVZUkmXpSAzNXU9AU7dP/3HEtlGJlBi2DfFnpKvntsjIeHzyOZWm9FMWb
Hz7OnTz3hxsHMmSZ3/CZJvRyWdHMpE9b/r2v7piKsvVLKJNSIPZRkJ9PxBaBh5ORX32zeEayD2Vs
SPphSfbhOxZ0UTaxEreHg8YU1kVQbrgWG19vNpYfjbLA0gow9p/tYWTZMpwamOJ1P6mQjiN2jHDJ
0L1HtP53YBtyfOtYShr8W1sFDP6JBEgWnxKYeo0wx+ZFBp+6nY+x4kaNmbut9rKPFl5hn2LgPzEf
ueshzJbnkecp/TY7iy3eGJKYuQwUTTyF0EPnRd/VkEt88KnWReX698rYj2hjnrmQriAy+CVoJ4+I
LRI/m4lDI0IfzijCnbU8JJ+DtOCu06lo0sTNS2OzU8y33sUNPTz/Dw63OSATHsIJWKaYy8ADuzFt
mIORi4XF1Wl5nduk8WoyTXN6e6m7Um/gMtyTWPJISeXcSIk2L1HIQOV8XTo7cC1b4bmalTu88UXA
+p2/ADKa6/jmKz+FropXnbeHjcnJor/jzAVr/VFB9M7qDbUQYnR4o6Eo3Qd2dJUViH7LXwlcDjrv
eI81hrBJK/yFAPr5JQScCNeiUlYo+DiIJuKzNtiZVWK9sJ7Hd1Gm+lvpJNA7czc9nchUKlbwDcZZ
MFllvZSRsqFPuaXbe6YXli8PlC1i7aV1u8MMvO1QwOhdtRjwWVMtqjeSQVsY+iNRFZ+s9JJUUAW3
RQShvEaqYiAhzTAuRpu7X42moyiXSSA6UZVvNLD+H/QadG8MoUZ9YqOBwdoqowWCd/bKkkxv03JZ
Ng7lyLBGEa6JzxKW7yhBKTazsowmO2/SWdBXS64pLQrGFCJihFdjuixyFwBQkTFxaDpyr6u+ESLW
tNdsz62M/tqTbLT8ykn3fZwAufh4vxZ+K9xfRfkEj7IhSktwBCxxYPLAhWCjkvT8Xa3A9iHQ0KTS
YDfwxXghUA6K+B3Ifh17Nwj7XOS1R8KHVG8TWcG+pms6+P4LAbGM4jkyG5Uk89o6lJ3CeDAzJ1Jn
tuQ5UtJ9ArtJCTQ7Bgdf0ljs09LlnML8d5CYLMofa8zs49JgYVkD211e0IjaZdWZ1OmNw1ScgOqZ
uiq8iUm5dO/olCjvHIvhOjWv+wymdsCMzkUsolV5rbTS6vhsueZilwwQrWr8OqBUm6UTIDUExwMV
C957sNa16TwboLLqg+hkuW2HU/wIlsu43u0rAc2G3gwDkCYBc+rcT25k9WsdEL6cSm4+5b/7sCQE
zsfXG5his8g8TSPzF55oKrYCO5wwQQr0q+F8tBBJGEmUBHw7UsKUq2kaTXqnpKXfDNcxh4h2XW3w
nUjudLOn+r6I2siLpynxmbbg0Pzz/6TEFTn3ny0pmKH9vbCEtZoX65rUEgykiDyHgZpCo5SKuhgB
5I+kooudDIi4bh3U9KvUz7g77GSeZZ0KQubgznaukpibOYALe/wrs+MocojxR/f8KFF7z99pVh/r
jezRcj6Z2/BOQW+SDI2RasPW4POY7Nn3S21CBa3nS7tTdO19DDZnFe9J/plT7V/VbwNnz8GDtjJA
uK6Bf7oRd7/rz6gL+6Sg1BB4q2RTBNYjnSa1x5bdnBND2EBVCqbH3f44FVqXodiCKFdzDAlZNWNq
O1jdE0/mkPn7y5D32dmPpz4AWzyS69vRQtqv2ogeEGdXZ/b5N99Igar8gnZg1xea7NC5wfj8zhM2
e+YEzObV0QXISufaeQM0iv6hxy+kAkkgvIyCj+vJ6cQCGBYr3ubUbGMzNxvoQ/ZA6QsnjjtXXtbz
t+8ljPRhxhT4or7eqViw3YGjzp/Yb6DLfYfcFHvSWGci14fuAgTjAT0qAdSYhHwRRYsXNimLTAlR
qOEUyp3H/mpE5Xpe+Pi62fQRsbcJnTEPkVVBdllOwvP8GRxpbVTzCOVYE1UAaNNwZg5WVCxS2FK6
z5RU77U9S+euUBScL0P5zNbUTLiSE36AFoeG0AaVR/GIXNnUmpxt22qIccOyP+dhfHStfMAuUay2
IxXwORbXKYaIsEFR9iQ0wzxMIxuxeblONShA5MNEg0bjOsTjjxpaYATWC65ANbPfJ/o85nn5oR+O
PH89WH5amh3plKiiojRSi35no2SLqBFBg2nYYMUTXVN0B5cK/NDA9nL0ewHaHPnyMz0lyEfb5U3j
KVR9B5WQOWadXx1Fx9vf+SmvFmEcIwIYI6RFQsm1/vaxT8I6jn06xfJb3zNpdKOWEHVoV1Kyheuq
oMpD5nUsVXf+6wCbi5Q0WsK/xjxe+nEhR7tVv6e8s8RfKLjRTYNNXP0rNa+T7fFk42BRaXmxOp8j
EG7uEvHftj9Uk74iEW1Bp17lAnPONwO36fHcO0yRXnQRzhH/yTxSt+CRY6gb+OU+7wG/20NQ9LrL
Zwp6q97PFX3LKEq6/m++f3dblxNUx9LOcelUK7G4HPCmIBM7z9MQGj4sT6gFU8fu0c8RGQFBL3UU
Tw5v/QSUhFIjyoGuTv6bCH7rZTkv1WyVCwePCSTVk8E8K2J73M8PefOb3W6YPOOec5xtzcSKpT7c
Tm00vkjNMr1oqQLrAIfVSn4v1Gzyi68GQEqd1PMDCfpu7SeU943mSP+6MfEna7Nmd/5pVfZ03tBu
MM7fQdpsNvLM566sRtVcaheaUWgTsQEbQrfaHtZBWvo9wTCBtLzOVCyajmRrF/7072XjdNu9yCDj
e2obfUyHBcVqz+v8M2WZnaGs9l0yJEUayRdF5KEdS9alPRI093uJuuThlHK+0+yTI+TIw2Ehxttf
VYVZnDOJu86fo4m1X5X0P+LwZ709wDUSR+CxUBkbk0cTqJl6cuTv1V6S5phbb+R7NoL1/RQcYiN5
2cXvqsbWh/Znna+VLPaXmATF5jeQEbo/RNdDEIr9GULUnP72PLEEBS9HXb8PWN5qg09gDi+OS5Pe
efYCjgXRzCrAiB+L8Luo1M7yL8lKzpEfp20D6db5xerik2xWCi0dpLPGtgHd/p0RMSKPypuNB+Mv
93fAHpVFW3D+d+oGNjjDeH3fhw12qqIaGoCSSm16zu+cLQb7kog1GcB29Am552GBXYHNj0MNwuFL
cixKzERKwSnmi1TXIhJQkVpsPsEMBHAwdYFm4M0LieWwMwljT2YRKwmpa7N4fOhf5BBLsSE27rIe
Nrs48m58vJI6qgNudeEiQGCKr9RXoqstkJ3B+k10xWVFdTnR8X7TDyUICmthMPYtnc3lr+diex83
QojIW3l15/y69bGYcQs8RSRKUWV/TAfGWu2mbU6Ry4az1bP75MITJCkt2J0DjfXK8osrh5R25FQJ
Ms993JxOOaJnIrzw8A1kyk3QrQuV/R1fKAz6b94RCJR+lKaIqiIDEGMClINDa73uWKEjvUCXx8Os
QnPXXTDuDROpQSy/O073/oB81vlW3nbesYRgsbWzRyNH8/5LWq5p9yE+wbdb4B4pV5VTOV7lpctq
luhm5QpG+DNU/B6npHynQu3P/uGRdPfRrBWwiwRe4CTi/EcOrJQzh2ROEsWjGHY+v2j6ODC84nN7
GElpbJwZoka5l0EuZQpKUu1r+vOppSxh5BYPykFIP6ceqsF33b/L0N4NTEFUDKRJGo596vCQ5eU0
gDjakteZqLZqLRXx3DZNlyYa+Ek4+eqG1ml8Xy0xSh+LthGCnYBkQgy/FbFx8KsYl9hMXY6E8ciM
1NfYzLMIBTn6/0r4rNxJqXRilC8q5ZUIk4St7F2ffXAc33ydfsuOpq1qAO/bLlqpyasj7wzuq4Na
RojVOW+qgRWatg2vlbwI4lQH8YkwXPTpOvYNn6Gcve1jcIGEWfx7M7/HzPU0Wn4tzYCnxBtmvM1a
AH1Tm0TIjfnr57WJlMMb2yf6oHp9njPD2XO1+MhY/1Aoxd4EL9MGrWn1KVkj1eKK6dxcvpoSok6G
KQcvvcNNGkaIjPRvakhpH8/sevjiVrhibrK5PVmGsIPJaMd69gUw0rfRyX3nWYxvEMhCguCANgk9
zfrC9nUl+iJnE77ZYQCpNQiU1xP/xy2Ge6Z9sZs7Y5aIsWvjaN2LLOYJDbtk347uWtN4vkg1ToeF
fupPGWjnVayUstSYn/W0m+TVUbBo6SxWM4fIq7zbTl4qBYRM01TlC9+aBdc4mNYx9c95tFD1r0Lw
vJpyUjKXmYnjWzHP6G5gLnsNdcKLRLb+pVbfvUp5mlw0kaYuLviKBzwNERxyCrlxvFJ0H4ZwVRo4
AT1N2bFo1umRbtg26SvACunSWTo0PFg5QpO2FNeHGGPicSpCGN2HY8Bc39a7NNzB9IJ0zhckhSEx
OA0bHm5/6ImuSiDnjjYObwWYEQYT48hqdA1nDGr9YbvcUOre3h5E4XNF051oqjUSsLQJn4jlKe3o
V7lRibkwU8CQu2g41/t9uhFoW6hr8XlSHGXfX7g0/Y82VtPiEn6n6f0PRJjWk3GuKYKlZ9TlW8GT
WUSQTMwMxqHSNLqaAIHVH1jqK27HRzL5w5OfshgJBxg6qvV8JnH7V6RH/JnAluZmoHFoo9dYhfOC
PMg0WGVtDA+ngUwSrG9YDf55AfAH8RdEFMV3x0SlTjcswyn6cr2PvqrVmx9pAGOoDxUZXncpZQqm
e0WD8wIjry2hZWwSwSIAwHrcVrILwnYGmgoBR4tXRwq0PtrmcNJ0OKDsUBk7NUB0dtb/GqP6DTyT
lFTLXou9p0U1jBsvRdXnronySijiVVpD+xXLiLmm9G1h9vOuACIxZn7m+harhl0WCEBaEcam4zEi
VcSCHWJtQp641MIu6kANNXA7I2qLxAkQBuBSNo7Bbh/g2I9fkbJPGkXxfNW4p+2Wua8vGFGeduWQ
ifts8eK5XqiutyViepcWQ7ZxJYhANbAcBzDVMqU+VCCCGY1o3b/53bR0+K9/TAO9qDdmv+P5COSD
jQbwZ42wapSd1bOCLmmTHxYUqKuuN4DoLwsrmHKIgkWgnqIzDTj6Rf6g61sZMcZVz6umhoL+myeL
5x8kc7agGdx8D8Ry38VUfn+oSXd56rZGWj2ytI827aDOKkSLbdGNjg8JHi1T/Z+66d/kjVrZLfy5
8zte0Dok/2GVHUCbpw2OkSU6lQvSXibngw9scnlHxDU0ZBA9khQ/RgiWlkeZxMTGNYywnKHPHrku
RWCbpRRX+yS45na/A2YejOSezoTSuyzsEOJO4i7ygu7hGhptN9p1dlH8kE7HSF76WfY02U0hSica
EetUatqYvXk+lDs4nSeM0MmYQufw8hHBgDWZMlavQwPcaNIs+ZwU8q+0nLTeKpms0wJhOmfKw2bI
Id40lKZMbRm49d1mr96AFvuPANnGOtGjSeWp8HP3F5Ob/hcDH4aDZomicIBfF+PMzZMk1YJK4QSb
QZduojmipgJbKK9KrjD3Q/cCbP2ZdhWQQaG5kA/GlDoKArPMlWOCybltWGFFDt8+HrCxSTWJivos
FPkM+ZOVp2CSY2USG+7YIwgzEiUosvB6cqpATmaQOoWRS/n6wVMrolAqV58zMVEVdXar83yU9eYX
T+FjpWsK9osjBQ+Ue4aFk+nioaEJy/ipG5HMtw3avnkTFlcdY0bVlzUnyrfBJUWmY/F5LD3F1KUP
tMkRzk3otnO1hrvyc2duGA7u+0ZokWfFfd0zh7vJZzIx4cWVMbM29PQDHDmSOXtSKWKD++1imA3b
Qfi7Qbikeivv+WKurdluoS/69VQDQ7LBaFk2KxMsId/S0+ne6fy6JG4cJJ501OdJdateU4ceZfcD
TkUimbsE9H1AEVp/K012702ZxkqydIJcPSAC/AmFMsUvdJvVdG1vEAb4awZddW6l61vSCNiiDqFE
/59Yx3eRpPtk+StI9Olqq9sZAyk+CcYvkQvQGM6iGbbl6kHqlt1CgCkjIAfkeQaeReaknoUTqS8t
ZM6d5TPJG0xwhsEpqJhOkwEkGUKgrl6cVJp4W72RE5Tgcz0GAV5wNgUadcPOi9kPqUEwRqEyZqP6
F90qg8+7dZzGGbkheQc2eZwVM3lTTjFtmA76d4MuC7n5du6ipZVm4Nd8d8IkZK2uV9QczyfNnMxj
4dmPJDUDoeYI3HkROBHlboJvc0ht8MOXiK+iqiDQx+NXRFKiWnvwl25hMlaMEVG6qUBhpMrAObR7
Yb61NFFc/KT0v9aSFhT4OZskczvWFXDLXHTHgjZPQuCl5YfV3L1GhtmmM9rXrYTzSDMaw8kDrL3M
RBMCkntSiZh09CPWb2MSHm7s/ofE/xXxzF/ynPYIA1oUjqpPvYqefbZMP7gqr59iFdrKz7Vnm1Cu
mIueuwnwpl2yip/UTy1reH9IEsAccBYmp5rzAHv6+XNl7EMeyACBMsJbxGIIuUTJYQnlziIeqb1T
xf9f8joje1BwUMoMwg3KhtY6NTojiE0DpCUVtCFqTqgr2vJ8ilNv+HrKrQGH8FWvFssljnvdoMiG
4zfPO7INtM5Jkw8Nh/N1lCINveSmAb+/avrChpXvQfXJFZCHOa4Q5jOUDxkH2ZFgBu1WvQRk2I7K
YVFPPRb3PvKbPD1F5KZBzwkjNMA34hoa9kNkO6/+JiQO5KR3mnC9jjX1dfVMxpfuz7F8vO231ysu
OS7d0dCOj3z5FiDg3s5aZB+3esuJqN2Ctp/2hdDU6fkpk7qEtoREC0CHCzNxuv9Jv+0rhn65dOFy
tbf5SAy30+173ho8bsIOXKIr60cQAz00ixMr1Eb2AQSPPpyG6qa1pRA/sz7VfCgqfjFZbOGOc0oY
SdMZzt6I6IO6iQ9W0M0pP2DkP+lFONs7DVeC5w+22Ys/1mG4NJcdL1qoLhjAoinAEYwN/8vGqM62
QT1xhNlRqxP4c0xjXimdWE8aaN0xgSlcA0byU2G3ogpuuLGlaCSFYwGXADm9uqqGhM+nEpGlqDsw
ZA5tpHUNCXGwPBBLw33Q9Z+qY2PDno0YyQKqpGIVyqXF6nVn7n6jG3wE5Txnn1pYsUXq5fTHfAg3
yJTfd+/DyeHOE5pm7fwZKqJH7FVKtIjjYSo6n8XdMnFrNclwY/tPJdAmIHsuwERVzVIwA9ILQePq
u+Tm8ZRKf6owvOolFGaVgHxK6v9XE9C3Zrkfuc0CVmtBBjcdNY6MZz58HalBNAbDZngEE1Wq1Eqn
ukA7MGEIpKDOdPwBFlMLK34UaV7onU1lMSsvhmX4E9eTRpaaF69h4+3x6X8Plrenpa01GL8W6O5E
4gg+ll+Dav7tdXuL+h3Kpe7TvQICy74EqUKHFkizPNzQLt+uPYossYkKZHf7cGYTIcnB+N105tA8
PPjpm6EPzJwyKSRyoPUYBbmupD3/eta4PmqlWw9fi1Y9P0U6iPR0syCNHeHqYRIUjbj1weGZkxYh
ySwfl+loajhvxJnPqqViUs2s8/D4q7rb5NwHAVZb0GFyLNg6D5T9GDdl6ONs00wWMLTO54P9t49r
ufX4L08yRd/VdQ3xqW4iD85Rt/vBcjQ6i14IT1BRKi0OdNkiER2PQDCFdKZnVz5o0ZnFnulA1LCU
Xi8wUMAtpyVf37l2rSQM0P0rlOB+l2xrfHyPgMsZ83f6j/ESxi7It2cHNRzCY3musNqyD6ycIwAf
m3QgTYqri8y70048B/svCMcPxmOmYwzONtWTfqfqsGMs2oUllTkbGzvkKerETzJm3m35mlT2cl7p
5JWMBD8QRDbuRtZBNYQUsO/7nT97vK42zKTAmsk9FfzplEg2sdkmUnp/ulspgfjdZcl/pxF2vIgS
v3dsMhDXnFCC9QadJktPc9+t5dsCIffkNxIPbbitAY0BG9tDhJo/RtZjcksvIn7qRkfh5GmD+aS1
zFPQIwMR2RINrz9b1TRicW6obcu0igcIeptKKveUQrga3lgzbHgznCa7hqbxrR7OhKT86Ay1cpqv
wYB8Oc9a8tKQhgZ1o6QjDM/CBo+X4rCYwNEw6fkNT4Am1A4hrSrqczOWGd0/mdKng3+B+LAwpEhj
0+Il/MVwS5XKr0SpHMW2ay1/WFVW+12BW2cvdzbZhEiQMpHMY3mEZzNmcITe7Q1TPMvgQ8Cp2znP
FPwQKJug16ip30BB/AAQ+6KZ4E0XvlqFhwMa9olkIynka0Q+oXo/8E0QK1OJB4nUvfUXYVxuO7IS
i4b5ZeXYiK2GHiZCKljQ9XSPi7xkK+6YaHShFAnscH+06IEjelylMHi8zQ1/xqew/CxbPX/GIE6K
xr+pAHZHESNg1y5kUIVq2xW9w7KJkrAKfFLX5gANKrNUGNk+mL47FW+DzO72bbm3TcK5ny/raH+W
KNOtYn20sKWlBJCNo9xykJgO75Jr1wuwP0jactqg9yHYisCmFRSMBF+2O3N9iAx9F/prvlUh8DEM
1b4cv3VGv9+JMD4aQ+yl6M47D1JJiaz6HgV8HJl2EVS+KcRsHE1w6DQPsgF2g7y23CS1kZ3NLRKy
CMmHsdR+tdZWgzYEacCt2LBx9iOEvPcvY32lqsY1u3nvhB4ojLDDLC+RdVvNJj9KGTDz4jklplUF
fFcoj8VGC2np6alwnNWwJhrNo1HDLyHaLutygYNl5xzgxLdkn94CV6uViNne1+cSB+GJzg2S7tw1
1QIUZxrK9Aw4VILJ+fpoAoAqfSMkG8urTSI/Y1Nr4P3B8/J8D++hsBhjmwlTa/mC4gBMf7ROMIP+
D59OxInvM3lDiK+zEXxp8h721iC2ZavOrjOn6Uy0H5xnfDew2OtBQe3jmgGMexyLCZNGshD5ysM4
0uwouSg4KxEhd+80nf4ay1+Zq6ICr0kSX8CBHbCspgyD8GwlO6kDSMgoJffGVIMlgpD+JyJrIgEZ
OX3dAdRW0uiblAL1Qj4pBVMrXahyvXLyWMr52QAtdU175yuqNdVk8qbjiU8SH4gwRSC1vf3ZWBR9
l1VsL1RulezvipKCe8zHwX1eIEPqMLarYXWW6cAUiq/6tzDYTw0gTHjLaQ95gR/e34EydOE7mIFC
QGb7CECr1IlSW1D4a0ImizvmElOaiWNkSp0Jc/5ZUnjNPW17UfQ64Mweo6wiBit5t9GQ/A+2ZVjP
Qhe1uHLJEcwtYy1lc5KO4HmX0oBOGVWHkZXvIAW+BR107YClba8oxmJyoiC4sG3Lh8Fj1iDXzEPg
YLu0bCQcxEIw0v8cNL0BQapzX84qoWN6QyqXwtdtPvap2BV3DKtCFWkHki18odGFW6XPEpvu5uE+
svGFI2WTVB0jYhW0xISEVEa+AZggwV4Pl/GppDsao9PIerFQl+siNvHY1x1CD8saNEOSV8wSinmE
NMIZfZ0+jidvlBFc+ck1XejuFjV2ovdD//xIjnmqZqjhp2e03c0S3DFoUwRyGaUxNGSKVIcrBcVf
Dd1I26+nnkx/SQUrkvfKGGb/0BxY3OUvvZp8+aykHFJY/TvkqNi79VqAUeVUlVrSgmSuw+Tfg223
jaY0rkrF6QjDZgtlxv/xAVNtqTkL+g6KWals/nF4+9ULvQbL/849QoAG7K7uTG64cEr7BSmhLlKi
NjC38RXSCaElKecTeSTNA3il5s+Sfpt9UXY7ICDcg+ts+zCvVgPfsy/vU8nEw0fQfz1CGeiFT2U5
HqFBjJaJCKB9SiW2fheuN5JFBdjFFzJBhG0SxJTx30uyKlBNxjzUW9JdniaX7CTv+pZ5cdgaMQbV
u8wu3XTxotVILNl7FNSe+WPhjtlm7NY5228E4prYRBdLZxCQyQIOQk239PqskN1FYMU+nZ7xQGNi
/xhkwVfAlYm9ByvpOQxVvRC8/X9Ua+u7wPLLUIFEnkxOOd74jj0NDajvUKdvNNjimLOTfeBLtBGT
g673vRn/B1N+VYloyICtpRWyMpjUxCNf2JhJeRwuEtyg7Fk6JWTQn3xFz2hv5vIQauU5n4r3TfEX
Z/z12oXQ1OepLC9DZobE0mo1SSAu/sLmiHeK9NkJWaivlrjAcepmSI/siqyd2LowEy9MXELFfEVi
GD+O+lhKFGXEh69Go3BsuQt1EWs0oTa/583epiVO1d6xBW3Qbn21qm1O/8ugwyUn65qUUXpW5+11
E1/T9HPZ5WoIjZJKRyVs5p5VWtPvCbFa3SEBkoCctYRSpVA+52yJhcSxQ1cSlagMO3l58SoOa6i5
TBUUr2DEKDnrVJ2E1Cnkr/GXTYRGplKMCDOG9+z3MbRyontJDU0Vbj8Nd7MLDapL1kcTowJGE2sv
q0L78sJ8RdNleW+53Okns/Ofiqv3UregvLvcNsfIFDHEk7Sxh94GBviMNLmkdGhZ4bSvLlh0P/kU
1fIDHH7YC9b591xqw+nzbtC51UdE9O/qebnAU96h2Xx4Msqy+URsdgZ+hhqDk+0ukhQ9EH6pd8WJ
JA2PZKJZNmjS/S21yU8aknt4+aXPGNKaFOPMYxXfYbSZf3nWZWXcGQNJiYEjtPVHahAEHGDnoS5x
Osad4UAI6IaNIe5SNZLdMrUItd5HqU/PKt1QdIKum1JdW8xElJ6Lg+Y3SFqSzqOUpq0zrMx9+hj4
tub/sy3/757QZQFg3vEwS/KNPqi5z0hRiFNPWQOibNVcR/oQHtWvLkU9gKDqZ7gjl4HuIGqSNBwk
i/U4SJ4cPssyddoe3RplMmT7fVHKVcniWlKRl6Z609Ug5fuvyZN7xzgYVwM4MHrlD/WVIQCXt+NA
JmfdKKJpaTOidaHrpp/6B8h/xJL+4/fPBkQPqxW9DSDvOEjF/W5l3uvotnhNtorhNk9PAtRNaPIc
OmFU/9zuQIZCYpbIQLPLdPDqbdJHe/pKZB9T9akPOc8aZ5L2pqxqjPdHgAASJoD04sbRb5LL/0s2
Xm9U5oeT7i5yAMW+yoYHQwf63ngDkKDk/IFPbUgUEgU1t5c6fIdirHAhfa5ZoHQNNW0qFs7H4Dhn
IV13NC8epRLqHEJq0VJpPWsgf1wi4N2gmiql7tHsSwq3OR5V/ldi21rkQeqOorD02kDaRdlH37f7
Kgz8r1RT5RNt3LcjmvsPirFxG0PuAn8SAfU7+TrCYwEgjpvsQ4rhJj+STEPsBbRxp+Z+tsDztSw9
ckykMmMBI0BIZfDNCea+fWewhnlSRcfRml6+XjkPTMP5+Hhvo4c6I7q8EJyYn7OSLDeEI/n6CqMt
uqNVlMghiyUs6ewBWxdiyclOowNkb1jcU1envaoCT8qWP0By8Py4dNtTPNudHX4iKkKmHPFUPOnB
gdblBWHKyBgpIa0Uhvfy1XeVW6PZT1WcX2EG+3mKKVIggt+olqJrl7OOosuS1iub53yBE/OijGWT
d8pW3rcS7DE4hptZWQdNuPDBqSpn+BVxHyvAiRMlY1oy2J6EacSISka3mkCG9MKaBXAqi6r2CtCP
n87nWJXrJRRq+mgl08qCYHLOVEqQQ1fLwD+5zGMMTCIGoMgjsP8nkSh7m5NKQDgrDg+ZF4EGifpy
lA4etbHVhComUolLLIfoEhy2kyMaggz3UzZsbF46mvSiV8ZM6hB1uUDZTkMfZgho6xuDwDGpOfAi
iFRoCyKx5vAFguufG5io5aJbqOEsd1JeyezYpmH4eaWBTDWeAm5q5st3PL2NunqOlpqzuRm7XoxY
p85ThK4unhbVxYPQfcx1cVWp9HT9ldT5sfSbXHbO65yK6TJk8wEdJrMbuYaef0Sh2dvwCkJqGBlS
qQdUMahxDa+C/tim4OoCHOLV0HzuI7v6U5FH5UtP20yWUlsM6JOHYL0AF3fzaRxa0a4cDr9UIW4c
DWJROLfT1LQbx3LMSqflBjcyFY3VGPttGOtQU47jK6EEpbJm/ffr3zfFEFodnZeBNP1bqW3FvcGe
XW7NzSVCYDF6ie2fPyufIorFrImCTIiH8yx1UEN0WDWcZi3M6XBv3RvijpZu9xP6QDttsjJAyBF/
b806SqmSmCzrla8QZ9Nqm9QT4BHNVeoGrviCMJ1raN0JUB3MKGsTHlAksOBYql2tdY0mogH6r1NX
0Fw+mJglfgJXfoe/WkKFhCE+NTH2Fp6IAhbDynMucKo3z3E0FALwoEMZodmXBI2UdDAvN78Kvf3y
0aobGcm8GDSd1mF0d0k9j+IRxWLQf3p7H484vJ/qKItjfpu2pFizVLleXJv7RLQXvZ0R1J/kobLV
Y0DZKhkwX4RgE1eRnnJKwuHiXhL3q8t1H3i+w61t8p4GtrEAMCSKGMajxJyOtsUpZk0xAP8an3vK
7ghfxZgmLPwrLPNhX2xXYmJVd4EKWuMgZrUOStco/0QZrGM1wn21WdW4N+9tGY2kIGBfnolQcY7Q
r+uQJgylxiK1uTbWo+SJtc6FOg1hfcNsLZCCjxzd+7ZSEIwXPLrQ+Qvq3WYgm5p+d+zZ5hg76GJF
A34dYHkpeNmLm78hs3BATjlzEEZx8265rMnOH+yasawmeN1rmQBzjsCdWi5afKc+62+6mtLA2K2X
7w//WCiv5BbKpU5QJFacaU9BGuaEQpPw3RFh/WilB7xs/XBb5bPxiQ6LutCgcMBdqOM/j62QuqZF
H82Cj+kIRQnNY5SMnrLV43/cgTlfkNWTTh5OUe4L8JhYUYodSTu3eLoM4kjmRFFhKy9USAGONd/Y
zm2prQI/FHOLW4fr5n2AdZF60uPueW3+8Y9zWod6J9HlApuhHVxHp1gWSK2vxwcFq7uF7gTO0R/b
lBb/Av7cHZEsKjtHn3tNcXgGpgeTVDKMIzpj1vSBanMUhbe5sIskoYHI7VHeP39HLtQ/jr9+5Lg5
hJo3dNk/g0kknjXrgMr0QctFR8/5UCycOSeYwY7VivCLAmyira81WkUQrzUYRkDCbYEuRtWlAczr
B1aUjyEvShrHNE+gc/CoEX2qjHZ2mLvmNR6DJBwAgYNIhAZp3QZStt6qU8Vm2BFAeJ9NH1o19qyL
Fnuivtt3r1L43ZuACoNnShdJyTgs3wpBm4eZjg/HhyTng34zvB7DUcx162lP8xRqKWdT6noFKdmr
yuxId5VjXTxaLUnI8I6WLoyRMCzvjOJv/GlSBS5Da16WxTVNf/fE8naEinH/3e0yUG2P+ZRk3kIx
OP6owTNsl9wmdFoE5qFX7vwM/ovvI8Wa4kQW03LWZnq82p7YDf8N8W6TIhmKSKA15BQsjNlD06Hf
3o+ZcQea34+epXzzYb4sGK/8/sUv5yaslosU5zruAC9mWjE3JVauq1kc1AoU+Sf41OSq3Ug58RAK
LuZqRp61M9Q0EcpjDf0LeYO330DqICxm1K1VDLj8zbhlDqXuIxbKc/z0EcpLF92VR/GPUCvc+uXm
eWlf7HCzWpUqVMThOJNHUUdZ+x5rtLanm9eyYfXI45x3NrQNqr2Tby6CZF/lNDOFOUbq5ONG5HfD
IcvgKIVZh9H4w9g3G/1SlXUzzL57uN1qWW1mmfFiHeXODouyd7GaT5kEI7G7p2Dpo7WeFmFtLsLe
T2SvnEzH6vRyYTKJWvf6JYWhH8kM9plxeNokeMA4nPrdpU1MXDIv4BIb5cea+uJ58yDEnaDrd5Tg
FQGcxh/E0d7C71j4YD+bxb77/v+R8lAOdJqBXytBmzaS5p3Be6tvWwvFydPJjgI24Xy8cUHRE+OZ
KrZ/VbiQMDE0iWfvvYhUI2ruOiKIfYdrFwrgULB8lBmpE5oEYf7bIJyRqEbPj5aW79YYWdWH1zrF
4OuW+zDL/ywtdbXpHIoMbigFzfvzSLYuYwxJrcA8GznECQoT9uh3OD7hrAi62wJdSjW4J9LDf/E2
/o7tQo3K8/nO2KnPPkF9W0ikcF+ItUjuxa3BCS9bOWWNVanYufNSixGquT2+5bfjNhYtcTM0U/E8
nF1EW7qG54EXrGZ/X+TmD97UdNOGrBTgXBPfCAO24lRzdT5xV83ddETFRCCBE9Vtqv5j4G+NOkNu
bYwhWeeGQIjxHuP3zGI9IAjmNhCCXIgo0HXZ5hIEVUe33A5UDCmoR5OoMCdeTb0G17WPpZHvAuaj
86/bdALdtE3ZW+efzxz4iLKiHWrKPdDN9WFPl2RFQkm5ex6LesknqmKY1E1hG6YY0Wwpxgj0xJrl
CwbRDqU5sVFG3Xg4pRHOe1koiQofXlnNjWtbmdyRsZEBVQb3DFrgduxEt551WgBLA6Asha8a9ezG
+UqBQSvC2UNQ/i3mS8MfkuIZ9Ikil/bMaCsdrrWFiWGkNExzYOL2mxLSRxinHvb3zv9/ybPQnxBg
eJC9obsAUP65cXJVADneHSU0QlSthQQnwVp1PNpD4xkVbzo3PmTWMTDAC837r9j+EoywbSWKDKrl
P3GlhIyAFeM7BP5M8c+tArRlLG7YUGQh38Yq2qLJqyofVzyuvzR+ijI0BOeIyVRySD1AfQ8PlzwC
uL5da9h8KD1anRNSyPSbPPkkhVgLdBU4MXMZb1nE4aGxytVJi6b35b1aCbHC4JRWWzlu8ZZuQgmc
NpgQ/NQHMBjDIE7hQy/FYvILq9wu+S7H3714ruAZH2Wy/s1G/eBHIKWD2N75/MDmmpys+FIThxtp
hX3T4ZNWUD94kKg3InZJXraMBgk+3Og/neW7GgW30ddnjrSF+XvdH2LB39P6wF+wFV77An3R8Ljv
rHZ/MZ5zPAGGkNXRBKAKwNA1jdPJOpWUoXI5TtcMIROE4/rKoytKRrgHq9RbJYnfATzBU4Ze8y0N
cwRywH6ka/MsmWXKYbmMXRHOdXHokewVx9R3A4uJHY5pUdLs6vXIR9Hi6Tpc2dmro19gVASEglDe
RGlpqjJAFLGvuFSU/aOkDgIiukvF1ktFhE8Wp2Um2z0U4JuuXZ96MArVmV1r6/8sq57X22Ye69ZW
EfhYGo6A2xTkDzLIiZeyhY6vChtF9nXSIVms4XIgmNRetKdXnjGAeUh9T2J0/mB+kELxBsokGOvG
ZbiSEPiXOLQ2d9BjT/dgsxNNWP/oMYs3UYNifwpSKKHcPnXGQkDxPdEUPo0ZaxS7ckoHcQ42xvCu
WfQemg4oPiRbynLL2HnVSwalezd2zyoRXSBK/QdwbTYWQ2LlGuAvaQoZbBAxKeXwujPa7PNkEhr+
rKkMZxxBx3fENo6HQikzyDUSeh7rAIPtkid47a3KYqLgA3wlIQdOpLI/evt858EcU8SKIsnRAt5y
EM/b+/3vkYHTclkBTeZ3LwC8gMuS6baUQ+talKb5dHwi03jXWjK6Sv8eaKf2aQu7y2a0FNphmKke
qM2m8AMQkW1LE3x+DBCxfhCgpb4XzkOq9LQim6MCfIlmnpt/tFa03viBgXPM9NAg/GxqaxJlDDlq
uJH8JLAok3pRWK8/V8LB12ZAe7Sh7HikmiHEuRqFExkebfXCqqZ+h6yDGac4q1UWXMNQaLCqCYlH
UmNJ6elk7jWAOyNZAWJVqeT6MhsFJGGrrm4rrtEw2gY4hnYn5yPnNnYd7bpAY8Q+9OVR/4GcCIvL
4dsCe/MDH/b5LmsYnEMTB9N/zZ7khoLW6xtzSnbX7fctVfb3TIrOiCTHglbRwGw/HRl/FSk/WArw
F78A6qY1jWNxVGLj2/hrlxvkbJ8y+4X+vohg69esc9+JwgufnvuC+86PQBYubK5g2y3IxA2qChjO
Y8rH6iYxDl/X3pSkfY4egwPnOCIeLcdhaclgzjRq/GnNwLk54SnLhTgxyBN5UbWOJoncsqxWrAoJ
ognBFYX6Z+gOJng/JToNp+TZuILaR+WFC5Wko+fy6o2X6finvWN+/+16/9kfSp9r85cC3wRWtpaB
XFF4b2FlWl0p9qx6OnEKhjDFaDi6NFOKyFY7rUefrKjvua76OmqUCwsaqgrsdHqbSlMwZOmJ8eur
g0n3ePxdkMrNOi2H58/MgBUynEaA5uFnilojN2z3IoN8aoDqPQV2Xj3AGQTW9nBQ42yW4b4zuDis
UnafGvXQEvQR4Ct8XQEujpYOOrodxQwUuqxSt27LpYl90IVkQvl0j95lNdMOGE/0m5npmZrIpovv
RI/UmV4RyeP/G5WA/Qz+MAcAuhvzuJ6eyM7sh155RDn6lgHZv3bAqptUxLoCdgqWPSRKYsfwgQlb
U45Ye1W2WpRSmGZXcKvArK68+hDYRYZNBgdhhWddOocrnhaZBLwiDhwdsffP0S5xSvM3E8zkL1cb
pEt2LSwuI8W9m5RxPjYBu8XkXkUSwvTt9KpjzxNYJGewZCups8FPsqpV4OlcIOqtNSYRlCgDohxN
Ahlza9C2rZnjhqPu95XUgcrF63uhkvR6vaFGsPCvFdx4koERUqvAwYUldjtK4VXGirNShCz/TOQv
ZFBp9ZKToihThGPNC+0KOh03szyd2vOxwmU6WCuTOpdPcQukBn74/dyQ6/33OTUBDRxy4ANtoSV5
7ObD3zo7YjEpFmKPqLhy+1KUof92qIQrhK2K5htSnE0+MokUWYHa2NAnMB9I0FdS4aDf4E46L1Ms
OOp5Vndhloege+FZAr4L2YfXKOXA5AR6/EKCA5agdFpsXNdbaMLiQufulwbGBVqTk4JAK7W33TT9
1hsbC34/nLzKjSfzwpz6Gn8zJ4nl+DVAy5JM+T4KCD7e1jqMDGgYDCnJCvzX7c5QZG/wBx9ycDsH
vfrvHdBJgG0h5VIfuCsCV60Q7AcMUZT1d3GvpjkiUBvm3iJWYGfFaMWAHilOSNeku5UWXYEEMN2n
SX7JEbTdiCu0VTv+NJGpzOiRI9vVrk1X+yCMcOQ/Um3Ae8iQ7EQodkbmFckdYWDYXPE3RnxF5Sc5
cB2XnudIQvSS0Gq2r+CoAQkQwYKN+NnpESOEPwSkGUuEGR4+n3aC22Q+75SE+FuF6KtKkgi8IAko
6o1C5WijBKGzZsLWXdb9sPbSAwJhid/D2odO8PAiqt/FD87d6nEuouf2LGwyphYHYPvg3ohH/EhB
HyW71hR2NICy3ivyXePUftA4UHTwjmHpo26ic4DriE6d3f6GpLjOyIKvEL5I4GqyvP70IEg3YQcE
UA//gH7/Q25xOKWPwjbjqEFBIQOlMyMI6EeRA5t2de47P1nXm9SP5rucjjZrwMe8Ftrj7AHBa/VR
fXM8kKZQUZJ4X/y/MmUuZ9DsS6VUgJX+9R/BonqTEDyWuGJYjx8A2LPAa+pJRk6pGhQTlQ8sR0dm
9T2jb059jfQaLDufpoVOuDKqK4429DB/wv8pE2QfjNnpftqP9u6C2vOqIa6BuV6twXwYMMddDfLH
VXWpSxKRCB+XfhBLbg3XMkeP15hkh/kcbnVvR+445W6lyOtKk1Hn7yBC5sdoISPJ4RyJGAlwK9QC
fd0WEb7h6ZmzAqCFybwHQDLIozC4U+66VdFBB86vrflZyRqRM+i5gY9uy+b8MLO3YfrlEDdCLNAq
zRjsnkDjQ/ArX7WeIQA9P9a4LIt3w3K5TFpq6/Dr8SvVUSBeZS6qRCkgwWDRBZk6RCUqJnSDqtBZ
ZljK/kjF0L/CFrdqeEW8s4dWgrkn1eYLoohBGgxPQ+WIRQmZDMzW/zanmiiOZeCqMBMMbRHztCqv
+5PtuEPOIweI86HSialVo+l0S1wfCaPs/urI6EUGcmirVqBLvQmgHwRomA69NuRRp3hPJDwPgQlI
3wnh5yMGhR4kqQBbfvIeYsOYpqQDvY5iMAYe2Mu9V0hW/YOviAOyfBM0M3YWbXwe/fPKm0WI+w8Z
UXWs19IK4UokUlWKj3nlGgVo5qFIF4v6HfcTkkxkY7MGv/i0L8k9uZv4x0wVTrQpy3hiWbdssFyq
x76CYPsAiAazlDENJ9jG+9cJgXcB7KzNOn9VFKBig2rQrJ86xNG3a5B/dBMkXzugIn4pMga7HDGU
KC7BoID1fedRw0ISE95AIFgETttKNAzeAg00X5RHFyAwaqI13AtgcLRXGq9lqyrHvL7skvG9HpfL
yTftm4/i2OM/OhIVl1MMyf0DItqlKAdQVqdR5kglJt7UDuHrXA/NM6ITRkSonIqsWrmT31L53uDy
x9uDXHfJv814pWc4WYf/F3JOU4sssyQ7Xx1LfabG5QLvwjVurzPI+y62dySrr7VplUbX/FrfqIy2
ugOMPQ6suDeJxvScYAZ032z2knvj8jzJbmhx4EmfgH2LYQGRucTxLPmAtMkjyBAuavmoFyNJOsiZ
U7SaER4MDYO4wfugtXjLAuBKa5CRgsDmOHj3Xlo/yEK3iWc8YcIyONErbhlNLqXsR6erUMV+xmX+
QucTf/hab8+2hlQZ3rglZnmLaZt2FPKp08SVv38BWepI7mNen4xTUovoVI0apo70XUjcHvv+2aWV
2ODiok2FOVQNQdg4EOsY5AUizrx8xRZMkwmz6aeU3FoIZpImQ5tt0DYakDoj+zk/dMYs4/aB4Axq
Je0iAsY05LonGtYuNWdjIt5iDt06JzqksZ7D/1MW8C6iP3l7P1H4gR2SX3Jlh73DOl1NKB+mp8Oe
ij6jRJpwtQzy0FAoxgGQv6hJEmeq6B5KMHPPlKHCoh+gwA+lJqZffOmRk+/Kda/Q/tjyHJo0bV/m
yDYByS7vP35Cxm9qw0RGLVym4MsqUXU8CieX35SXp+yV2QkGCUwNCpnn5BBdxzkO/VboQICy7IV7
ow9ocAFm55oX8831zlAH8X7Z55/6zdZGgXLESkpbYPzO3Il/MhcFa1mPz5s9qp0NwggrPhgImc+i
vKNhg85N9R2xZEG0RiegFQCd98nsQPiVSfDUpzUeXna23OlO4V6cnKBhtkLzAYzrPTIaY5LEL49Q
OaizvlDAHcyAbqqV98W5VR45JxZXicKzBafKERfCbuuoJYgrG31LMRCJ40beFCVIAoEUpbxH6CKx
yEjnfU/iczXvAIcSk/bnFfXX/xWe9bP7qLREQB6dKCL9ZTapHNGto2THbjejXzQOKvlvXgCd6E2w
AbxR+7Cfe9H4J2D0vjh6n6hgmEkwnTvOq+lWB0CPn+HGGlqujV/U0coOP6d4SMpdihHDNDdl+Yxg
sXXvF6bLKHCfyoQ7NWagkj6X1mAX/M8I1rPp6IBCQPOl1wzax2Ig2dvKLhsI3h4rg1nmjE8UTB89
uU5ejbrbrkCH70egKLY6A2L5Xsgg4zlAgd72/mMpR0i7VlwHeQ/EYIRr8x1ievJBmd0JBCk8SklV
SLAK/NJhB/9dSu2Mlp+KQT2EFTt+xQovfxvYeQI/WN8zNS3DVtazPtTh6+fYLaOaffQU9qaXIxIe
SfX9lComs8bIH9NsE/SiPF83APNjGxUjIk/qo3xUOv+BBmkAYa0QIf9KcmwvtXez9lIYWJkfjPvE
ax3IsfmlU/89HKzS7kDfYi/LbAmnDb0YMVzR6CEea7r0LYN/gZdHci2qMY9rQoq6cjJ3geuSpR27
/VIBUA+GRyAYz/+MIDiprlrSrQU8tKLENwk6cgRx6A0F5jXyLAR233zhiGJYRLsl8wpiLRpEIS5+
0Rr5zLDjHdZifoabQzZRF65PEjiLLYCaPJxEABpqHjqwH2um6jKgERioa1foQ0FYDhNa5s9wt+ra
rFK0YV4Y1+6UhuJ1ftkIu8g/50W/o2eXfPJu/a2HpN7mAj52SMJ1dmQhFMih6DIpPLadA4t0c4JL
A7Pq9MaixxA4opvDwE+RcibXbMJWcbiDgbqfRc6z89LPvZlOw+t9/d7o9sdM60egE1rcYG8H3Vy9
R71njh4ThsKyiTTq31BhwWq3w3jMgJMT57iHwKhFNfMROeiHvVQC9l0Iiz0XOiyy1e/VM5Hx/Ity
quBIPNhx1sSTEXDv6NK/0B9ewN/udRW9xpqEDuvE2y656IJbnAyc2iAowZzSDnPh9xGHCPhcjiYV
Nwo6psaGfcg0UIx0stjzidZkC+fWMCx1lEaz/AV6uslpHcBGNbBsNUPEzJettUMgcc0C0vvrhMnG
YIaag/UH+o/3UhFRF5iov37AOmAp8nUfxoVE2tq/HmWI9k6TPMvO7+SR8uzNe0d8D3O9KjYLJ6D/
pbb8cf6sFBFq1S1uahNoWCt9rU5+0veUdp9JN5z1LE0gH5Que1z3cVkuxQjn14SiTWUvvU/cr8g3
1JaTwQi117zsFlm8aDLovnJBqWJ4IJewwdZ9c7OCdSGi61FYxfM6Z2+0YaiErkfcAxdO/m4AI6i4
Sf4r8h5ov1VTjWRhX/elnPjuXpYti5C9zEGqX7TuhzeSUkK6PkTsn8PzwDAav8AUYJ5rSJsKActW
Vh7/Mcg3Oqyvy/jQl2u2PRWJ8x3pqwHGsH37yXfuE5f6sWTqF6FS1b+IcILsImn8lSBF8XVZCIO4
wa8xi54b1v6vx5cnCBoTA7ytxfImts9myZkCDg6LfhPBxQKIud+FVDHZKHWXVEC6d8PxBKEgub4L
yPo9mXYZIVhON1n2eXNvzti9aiUK1IKvQ+nSNDDQVorVzHQ0rOEcl+4dnOyTOjGZuNWqykzI1GRb
DY/6IKA0IY0SMS618SyrBBYPSVVumSryLz3ba3XWB1hfAskuHHMdxDDsx7Rsv2Ydx6KOAIe+lido
qm//QZnZ2SOPLIDpfjV9Gsv65QEfDHbjJdROQsKjAiCVVoMzoDuWu02kj24ZOSSm2v/+iV5IKaa3
Rwg9MqHgH7exT8FFmjVHxKDJnQe+zC1YU4BL2v6XldrpCuhxK4TDctwKnlY729I1HVOZLUg40YaX
zvAPpM2bwSEgXwshOlZUc7cycN+P0yUCivkntQxIawCtPOfdAnjMrcC5VGQ7SEeXRN1xVkPFJO8q
b1eWgerac/5myZa4QijNnunND9x1Dlc+/4kgyYpRk7itntNFwNwh+vFOMy4qbclYiTr0/MMRpnZz
/EpQqMfk+C8CtWVyuSblRG+gkV0EkCtQpSVcraoxfXFo/+tPwwBAzmDv07pVKbbnjABXw1pATYr/
o5MaaUMlDwbW4oD9SVNKDsc0q3o6QbTQjogFz1digX+FtZs5EWALmaIrcK5eVOanJ3+vusjEXrj/
FRsqXKlGGHZE/05iGURxdOTJdqPYACvOfYJ5N5HnWICNJ+Kr2IVNTF4cpKGoRErkGP0cPpV0TnBf
N6ya36pKwwzQlgThJFTPNFQbb/WnF4ZgNt03PoZCewRSxAKWrGc3x/imRl1W+E239n5bJvUHsDge
rdpnM2IPXUv8/BzErThw/W8ZMNS34FOqb9j9iozQY9/o6WI8i76Be46b1NrWkc8UCFSaAtIIEZng
9O+jJCQc5uu89ZuCl3cydav43OOp7xRzcVNeF+19YVMPhUvTxANPmKgDN5Qz3ntKcXyrcHDCcyKJ
5yxYXak6bIFtsm7A+aqXSef6MQ5d3s5APrM+jajuT3TNlrXCAu56yKErGFGkKvfrRI6G38vhjVaD
cSPAPF7dvjhChJI77k3Kwy3wwMySE4INEdhizBVLU/IyBL0LHrI/zTjqiiGr6A7ey8/QwufnPshh
rSVd/s5Nm3oFBxyRmxOw63yx8HD4n1UopFIu7nFP7FRbzj0poMmzykCb2FfaNhX3b+hTliHaQ/8o
PbyrTHGm2LMiEc1A7RTpigSsR+zL/MHqWKLIPNvMfhvNHppkyQxLJEnoGZvGWEloLgUlzNLnQUKv
57edZ7O5tVCyzZV2M2TIRo+axQ0YMnalupFPljFUpOIwxUwhtq7Y03cGm3KDON3v56rvivXddA29
1BLxMOgsmPtflgA/W/3RIFZh9ey6yi7Joaw9bg5jBnNnk9wZeJdIwi0ZwutiZPVM8V3PT33zS9KY
J9V8RwQdmz8s11BaWd9ZCAvFUuOOPovY4YfQcswttYY5a1SoVMk1M+tapFhDxJ+P90eewSwHQTKG
rtl1M+2TliOYYZAewliZzr2pxXS619co8Z5U+Dtv1/Qj/uA5Etlu2hf8KLB644u3oDPcdsGPHtb+
1ZIjgQABR17sh5U/JzOprfzAkat/RRa1BWo7TuMxX54f2y/DpW+EWGmSYAkNdspAy15ItRllW1rI
qvFBr6SNcptrVLZEyCoWdt6gTDKve9fOCwVeW8sztlzP3X3u7sZuQJs1m+LQPz+H5NOUOpEm8HSN
66NlWX0evkOiyM0YxHHFeMoqecBjATZo8jQaKxYTn8COBA0hNaI4hD66onAg0VKw1DXj8l/43fCS
2Ns+MVRQDIHvUWlVdwpU7mjOgS4sOxdu3bmoqlSFnRehyCrAWtiDUKVs/4Q/7xgA/ji36jCYNWap
naiV5K6+D6P2ezGENh75jmlji0wStgVvxmX8/Kdtyw7fHXlyha1s4UWn8PweLRO+VNk19SGPWC7Z
7/75nCm8FAmvyZkwxCmZ46GG/qsEGiFGZP+QXorMtWIPY8dKx0BuTVOBdEBKSsRZP6guw6VKg/cY
iSOfE8q05xQvEOoQDxNAI2MsfnZZedZhbBzJz2Oa5dOIUYfJG0omfrLO2tIzDIxyQfGi4An/7cKD
42wVvvcSZMnuEfHx3L5daALSxRgV/s//O6aCVpAth2ZbNrviylQBSGRUhVW2Ky1T438htCi5HaPu
CxztkLH09P1Arf0/pRQ1/S5e0vU39ootFBolsQDDwSXIIJwcoqPaaHCbMjao6AaPJFYc/NCXCuzT
84HewKsi+QR3OD1t/dLSFqsZvnhnrnCBgCtCLL/r1MAnPKKAL5xYMNJRznpWQ81n8qiHtMEUMYOv
2FKzZj8aEhReGPfFkgEZ/pkJAjq4mwky0oMvnDyXTedmmsPxKj41R6OO5ov/yGVuRHDiFdz2KtgJ
18a4K5J12zsViiuQ1+5q6t96n2i0BZCmvM1qvKVJNHwGOXByWN1Qu99WhTFEytSdYFm62x/aYmCF
ZfpkhZHYHmpuuLkXVSosKyQozCKFF0ZDstctP6PybHUbq3S/29G2SKW1kQEbW5+TZ5JFuh9JZryn
BCyp78Z4qtKUWfF0vUNZKwwmtdn6OsqHMhy7Tlgr+slViezM/as/RXhjLdQimunn/D6TAg+5tXVx
3lTvgbtCunjZzFJABiowh26A9Mmgln3VqJacw8VGEA9/s3LQxzaly8Lt1eeYPBBmm3PR1x2VuQuT
yP+yEFIuIKxiCts+P3GXrK/SE8nhNcOWWdT3QSsZKS82Lxc7+2v9aw6jQZQvmjwLc/IJGBNfFQPA
wbEaUrPmPC6pxYRCFTn2VftDUoSgJawAHCrcW98EGcH1KlX0Q611IghJJirS4o9rNhbYuOAMtkBL
2YnnpDJaBPqgPJ5o2IgQe0KbdDRk1nOQllIw6HZ8Fd1o/Nq4LTlAU++5e/WiVbQLfErSHalgrfcE
2i2cdgkBY6CNW/aAQiaOhQTAnULBwRUrMMfb8YPQaKbVK59AXUSXRj8Y7+fVHK6cXwkeRTjp6131
ydvLeklEAKTMAVI/INJ3MJyNUZQcgtR1am2EcJJpImWlPpkxeZlpBz3REFlGMtCzyNwys5wGwFjr
syjuki1iIYHnGEnbMXS6VfMCWiunvHElnF5JA2FyD3yHXC3lrkHc45EImXnGqjS9nsUNJxyT7o7D
KVeS5ejzEbtpQ3ChIIND5fY0BAs7QRYm5YJ66Halp3JDtrmhOmCUSmRKhWHd6Lf8rRYV5U640wQ9
bWxVGb7x89WiCMsjISGLr9ZLjs30Zp/U0jsckVAPy3YZoj1TplhVrcAW+OAMee/0OK+wrjeW2POx
3V3WDaGu//56968x1pgrW77HgGGCKVvIvwBU4fzNjeekCwp6rUp8/ADYred6Ug+/iNj8+d2Wat9l
Ba8x2QXTk490S2ruEtD5MJba6rGtnL3Ca/gH6rDHESxc3wYYsDLSWd+mmlqeQlCSSoG0A/700bGB
+aQ/IswsMmjNl3OA+qzGZ2O3EslKw/00n9/2PE6tR/ygZpRtHIIJV08EAKdYIFX5cp7xCVoa3U55
P/mylUeXJOxFUURRWdD4BoFGQrcq247u6YF6d1SCNMBtAWajj/n3mV1sjvsgQ0tXKVM3an+tF6C+
YW7B0TcuxrWTHhkn9qQkLVywEVqiESErubySyaF2tfxMSeV1vgM6xpLNI1X+I9WYTLh3ocvkFmlp
lD1yPMsiVxh114hJjAOSQrgPsysuPBgbmLioJSH9bmsA9ZDGiIzJt3rJJz8mIWadiiKGvyn5XjwB
/vHnOS7L3wTbH6yY+eqOX81l+iHIo3bChETVKC97Y64onONmchdqygocs+5ZMv5h9LDAYrHWthhe
RHA4+way+3O0ZVbvbg2J80Wpp9/5KaPUnUjCMs/eR34oPDLscW81aTlQ0VC5dEQdMykA1q/QOaLP
6zjIdehT887nXgu1q7ms1e3ZJcDUJb2VfbbMFXQlt326ABHRtOOzZYJ9jqb7qG1r77DOAAisprP+
oROuU7qQL29Xa6cc3NC3vaZWkCgdjGUcKpXU5wJ1+6icrgFCBkG9X0XDQw29ThEY8TCW+rRfqj1q
SwoIhUzzjjnC6LpsemWP+hpXb0SeWa0HlR6c9mYg0k2niQ73EYYWjOkt2QE77/mKG+Ubb+iKJKve
90/dtun2XCB9g2twrDTS36r51rtzPoXq6E6Sx5eUUMSDV0SwiKyFnHtmcWSwfG/ClKBhp8C7YP3h
4iExfdcXPcMo6R/spUX2szWTACk8IsojtpjLRpkKuK8NTxi5bJDbN2DPl4GgoA2N/xPmAb6+b9ff
gxSb4+F8Xk8KyBv/L4ZrDXTtphdeV3gDnOYJEAQs3+dGFwgoodgPGKlFh3SAY+fDh8k90POir5BN
Pi2tv/9Lt91i7Y2zboQ5B6NuGr7D3tz6Beubfy4oxwfZrb4ld7EjlmGu/O0S6sA45aJGGPkdAUzc
PN0F49mY/VIt8BxFYaMed9pnmxzAop9bRQK4R0KLsz0edHB82I78cBfYhZoX9VV5DWGwKvA436YH
rnx3gD4axS/SY1mJuQWD1o09JGTy73Xr20Ld1KQL/2cVOe33BPX2OmTb1Uru3mzDx8+qaiEUyZWS
4wXLvHYAiAcY6rH7YBwZqqZw0ork378CVC5YAj5TqipBomca0r8mlDyIVnk/fZnZjEduk7HT2tbc
RhLYKMLfOFCV7V/m3MWcjhp1e++3jJ8DGaJoVO/C9JepLZMNiGbTR86u0d1hqOExHNQjWwyKvZJ0
CeKrrWdf/yHm9BqyAYiVXhb3O6tJuw4d6Trf5xHOPYVJkHag6Fz8ey8H4OjguGwhLUuZIQcFJirn
ezT5aKCYm98tu24jwCqdIOTyVNFqlGHA0+UwEgSDckXgE99GVKeUNYt1X9TMPRnZU4ef215FTKJh
yvxY3kt3rL/wwe8XFiFqmWO0CGhbKNdVBEmULBN1saz9H6MOI0anGK3MKI9jlQJqz6XX3BXRKSfB
cd6uK2cQI1xSzRQ1dZ/UyTLIMBLdY55C/UO4oj2yoJk2FI2qfvwq6ux35fxceNs/7+ZJj9iNN5Gt
jkF8ExO5/qr5lp90ZlkkDZ+PRnnyawNBNKWhCL7rbZScoLRLWZ1Yov0n2bv2oOuHBp5O5cEUIzn6
SVGQUmivMOXw9fK+jLeBpAMl1yMEgk09lxTvVtZuAHKDqdM1gu06Q4TCH4s05/tWfs1oXJcWCZy9
woIEgFCVxxGDng2pVFA0QH5n1ZpsM6vAZwLtOTGjYFs7qTlNDTfTXGAFgO1EDjWhHSdwWZdUMg3D
pUf3OldYKOVo8XbtVQ3mpStSZKVANjj9swjb22gLU5pxhjx8rvYC7vvtw1dtb0oYL4p31KE/nObA
Xu8MdYKpz2OGV2u/uNoe34F69taZio9Ai5joazTtAXO11ZHDbtiKKOcn9tqOMzHklsP31ZqWXGzI
B9H3+HusFmtr0OoPu2deIZnMTH7Bx6nEQiKyEwpfT0hLl3keQUj++V66gW3ibCqA4W1c7ks+UArZ
y620yaH5unZfYq5DZzPYe1YG9HWlv0LEyyKi+I6W8VDkXR05uJF5lT9KWd3wNus3m/8jub741z9s
l3DLBKSS9x6wxKGhT3u7nj/QilT7/80wfctf7ZF0+nFUenou0DVfJ+RN+vHb1B5blevOrk0oEDyb
cnRe9KEKMXzdOzWsgEwBw70g+5ks8/uMFVUvukLPa0WJ0GvNTKkkXzaG2QJUmQwuGxrC0stzI6LB
ad7hTG8eJPyqaGijg/uNrZDnyW7KfCzkBN27mpa4LUtyZgg0Apv/CYmtjZRQ8cM5Hqc+F4Gy0NCv
DLZSU6kbDgiOBJzWBV+0NtfJ2BsLHeCfXTya5IsWjQT+qCSa4ejMJJjwz+6TvheBCaVuiiy/nxxZ
5jP8/uxNnlfVkg00SrNS52rM6aTTi5a9fXNr6N1/7aeZMISlnYwQtvaIoWFEG5R+CUe/K90novE+
PEoZnRBmGWbddiGRvLp0W7up2iel9IkEnc2kivIvjIo6rHiz6GG9PD7tn5fMXkm5SNRifeHmCVU0
R8uC6SB5lp/ZLKP55CSW8jKdr87R3EBLMgjDcqk9e98HE9MBKVWpRpFYQJF9p5Q6GmxukYOyslYf
PoZFbHj47M0c+vweLCHi68Cg93Jrf6VKs/nxYOfDbG82yntmh5PHji6n+4ZqdaBa7K3uw5JGR/7s
V/XacCpeWeuXP9MSGCrdph+c/Sd1m+UsuyAbztFrsER4SG6+hYGwLxvxavlovfsAFyerlIgLu5be
k26Wg3ZRS7U50o8nY8fjaw3gu1hstXpHTISIG4dryEfsATWM6VszvNw3+UGqQdHq6j54fAnqGo5a
j3haYQyBWvgqzwm0aeZ/USqW1jZJNKk7MLsb9WehPadYVhlxxFn6gDiBwfu3Sqdi2oBgyv6Q5XeL
TcYTvLozAIVW+CupWvfGmg+7QZLj9SCM49YJvLAVbifbeYBpjaa8OFHejLC6U3H4xpY37N1UCnJq
yG+/qsnYuC5HAsrcP401MsCReaR1z+OzmB6zHJaRZ5i+ShKFnE80MyX/DT9MbJRJiy9S3sU7qigJ
rsDN8DVadhvNNTj9xI0hNtR/h5jVS+9fD16SsKJhJ7rWEi3rhBiY0oCezHGFjw+mKfbX4z3/GPSo
ZZkMDyKSOy60/QdmlMJZQRSYq04+GXCXAOpyalPJsFLGrgHcGVLrKa9fw7U4eDbuaMlhk3Jj5RMu
CeKgbCOZZXI98wjA6SCE486mhhS7fllWgdA18TFRVB9V7D+jK9QYswTAS5KHIueUr0C77lI3KPUB
XtYXVWT5fyj0B0ZSphPQO86Dr6iQbIlFYCQiRwIk92dvAu1GttUee33u6CcWclKaj+rQi7lsgwTb
/jLEFosqpBI4AOySZNAqvos2wDDDXB3BmAuVjdqtAsolje3gTEvVdIRbTILO07S3wvi3wrFgdG/J
u6firUTweoPVZwQzoaGFARCXCYrVXa6+Ku9I1Irsj6O0s+TaZ9HZXCCjceAAarIRbmwKoqlsncHW
2Npar9aHKd01v1vrRHOT3V4aXAPgwz8ETgDavUOHAuWaqWOqJpke4cek61pGqYwe5Nd5G/mtgWZr
zM4/BlNePgG/gOqesWdgB/g8kF2o9SDPzc8EyVrddvIHFyhx4TGDUwnKTQTeQDUeghgCkCIrPyI5
tIi3dmkqVX0l2hFWUAijltYr2ZhfJta39kCazbgRj7hXTALZVM7KXpSg7f5et7N+VXXA9JJRxXXZ
s+izcnO/MwMzgFNHfUEYiYt6DppaMF+0Tk4uSS2lrmVJmAgsYduwCVOrh+la5bcdUjMLT80sQZu3
n2Q1upGo5unAURXgr6An23cQo4iE+Htv8MsmZ28pW4+D3pqJa/bqDnI/Pcs3Kd64mjtYD87VyJyc
pGHvxWczc3IAhlhO5cf6C3+DnExbB4Mu6hYP8zTNz9MRX7aAEHrCHQ2XlEev5CBzUrBfE7jq0HAc
SNhbScI1jOqd2VxcXDvVwlwJ33QqPafKuyWoEPN8i8m9TL5E/mvOkXmoTu5a2/11kAK1qLS2TRxA
sV8CeyvOO54zYpnoiSIVDsdEq6MyrVVJDRjU9wWugYP3eMdtb1rxFh1yjIcEJJePJRlghVaZoIYr
0dHcg3Xqj/3HtTxdo+RaTJ+OfKrCRuNy8Ckl8sTMhM0AD74t4XsxPvl7ZOO0eDcWaiEAZLF1fHYq
Yv+JET7IhVkSydRO0klsyWJMghn+cJOk2qvMIWbkuj2gixhPlQ6PJQpfxnkLuIc7M//hVGI4MqWo
bSjsRqYgWECcbtHk6qonThj3AWMZCwqSNigK5LSA80xoB/NSq/GdwRlBODgon7r182/BbsIze9sA
R46rSuJAUYLO0a+7sdiJUb7wULpKZAoMShKWPVkN7Ma8dFIIkrdTpJX3PFb8dcMmWtjX/hb5kckg
KWgB7Lzqu93EaFgH+vgnK/XGzaI3uZmcFMy/qXtvFhNJEung2UaPtoYVqtKiSjkC9wo0V7Mf1bUh
aPtDwOkln3tlOoVFw5DUgMRS8e+habKlrVSO7X7/1KklwUoq0zatCNhBjMIyPHuB+TsZKDmEvyib
ek8glwhi90C0rSHoaIuKomPVFpY6xqL89gzglvYTwgg+BmhxKcqdUuIAbB+2AAZn8pPXUIVWERYk
H4RFNCoWr6RxiJd0P9UzMnLU3ikicgJjsrQf2gQ8Rq5Sj3hQnzsWFjw9x3L/tQUDYQ4/K7VYdOVk
A1sLohLu4xkvfPHuzY+Paxq3WA5JSBR8McTPpsuNMZUFmqvWYgsFFlYKBdy7EZ8QxfpAUXb5JRgo
9p7U2XPwDfVk7q17HdZ/zP6pnHtcIH1IatZ6TacX9+qUPD/UWZAA4XnrFkIPgz0fz9mNKvh27Qeg
ivMAo8sTbMV30Iv7VNjdlHbX1ja5+0fg2h/R6/xrZcpuFL0LuRFe0xBfAQZe1Yv5WA/oGX8vg/WJ
m9szMLyP9x5lqMDalJa4KbCP1ikmOnZeOtEl75MXikknyAcJDOld8dR7S11X5qzWMKLt300Ho+N1
MbyqDb7snSh2aZe3QAC7YUqe88IbkL4kto7klTK0Oftsgko5ytRUHScx8afLfR6RBelhdqimkfdB
UAlIyq615L/V6LBdkDRhEoL+Q3VqRJCPiTdQ3LmXaK0vGZyzyYMCvIvT0ZGp/jPev/vHX1FtYSSX
ijhaYRFu+883bU6nmxGJh7KrqR2foLjUwQRXqDm+eBKps7lQdyt3dGO8lHuh8oXtETxduQWbQz58
ATqMQDWFgMSQOxB1PUtX18ZKQnhIPtHQLlr4DxsQBmdeJh9SyOEsA+3VaAJdCIbq0V4wgzlFlO5U
iSxZ2bnBH8R85mQwHhue5g7OGoUop+5adhv7V3XpwSoS455/zRKsGdmVRLrs0mzLZU1tYjubmTOK
8ZfqgXvr6e7A6asjo2mb8i8ncOjiTS8S3mFnnuLVQFhT+/4DIIlHJJ3aURfN/tLI50RQPi+J9XYv
fuA893binhOYyEo1xOCduMzhOh1Huj2pgcWPw4HCcXW8UuBy5WE2GTRJ9ZwiNO6E3ce/+5RvXQO0
I8+eFm5Pmbj8PE5VElJ49RnX1chMHzpywh0/LGn6cskNUvD/Sd/2kLcBRAFksK9+bze/LRA7wTee
rPd6x8hEAC/vsAtlBYaIB4sSiEmqd3W1dJ/gIKovsmEKUQotxi1e1sHIyuppV7NZxWCSgtWJHbA8
F9pSWUZdeiI7Pq58oftu80BHq/CyZQd22CflSAh3LSqnAF8eTCtknul912DXyKGKqaaHJLejguXY
v1CsDAXvsgQE0LE/Rx05q5ficeQurqFG1Ygyi8WoaiSj6UYPvaCAwvKl4QadvRIMCou86rFw2H68
P2VLn3XDVLfhz9jLMsMqE6vCOm5bt6sRF+su2thChQbvePTHSRa4JX5kgsWQQaKFsNGBTG+t2OAm
bpuAczuIA9yO94BRJTdzEDALnQj0qAY7BRag55CZUjPAGmroZaGSTSi0l+QteBAiRW8Hyo7Gd9za
oauGYDOBHRjD5Ya7E/fwoPYBjeJETHXbj7Dic8w7ZfeObYUTVHoj2qhfPwbZL9E7AaPti0hkYQT+
WyfPY3QyjrC9f4LzroWs22j6CN3+iHf9muSBgzaFCknfgO9M+cXx6v1hgHgKGlcZTUej3moWsIZz
8IKXp/APxOq8bBmCPw+CPfU/bBR8TEBZdWO10uygseEBHH6hytu0ZuZ8ENXTYJSUrleIeqdTPAUF
Y5rK5k2uYAwbSqEuc9h8rhbyCS5M9psTfQS3e1y7Xz8FalohNqSqh7rYr+EO9HJQ0LKFP+wH1CJ3
edAHQwne7Bfh4zgEo2txzBc22qvEQi9UrFqRXS8b8Q8FCEl6X61cpw29Ff9CSR+ZwkFhDIn1WVqq
0pf2N2k5+mX/QJj0IFer8yLCYUpt6K9bjPua4igjKQgaXZRgNbF8Viv1ghE+w2SXmN13K6/A7Sd4
wXlkOCaGCL+VI2gPpq9cYvc3EKrzOR/lD3QyIfZUgxTdLD8oWUNTqqT7bzVIrJxQBrBxUzo6eg/K
fbHMhLFoKQPfWxOFJuQVccKGXGMTdZ9enFNlTOrpnO1MMhpC+HaXjVKGOQGPNs5v11igEnJDKkGA
6gAUqg3KoUtLrG/Hd36tjTHaaZT6Fnh6BfdeGtWjIMTzvB6WQIvjS1TySQfADjC+7HCjln6vOvCj
Z9PbceS2KRPJ3lfSt3Ht5rSa8JJ18HbBdnUqbo/HaD5hheiXU5/WqRskZxnEO9yulTs1qdk2rMKr
ZUqlMXwZqE6Xkg7tbV09m7LJH8nS0HXFToPVCa8ZkcIemQQZ8NOq/U3so1fuv2OjBvjnviWXFtnt
7JWdLDXlpeIYUDccgc7mz86cQXXalmlKBAiYAyuM3J4yi7tTBGry749ixky4QPZI8lF8nHyngbGL
mqrq5G90eEfbf96UAYCl2fOTdlBdus9+tnWy9IRJAjuZG3kT1uJ3A2kyRDyA6XoDO7+O2g5VxEx8
CH5Lz8cMHDXfaAT98nUPukA22PxQnooVf+N9kY92z4V6L4jL+dYCJW/+w0JWPt5tDxcUvNnXcFfB
3KSdO5Ci1h+zgT1WYKieL5Zrg9VN8x/dQSUMNJR7vk7o0n2suy/8YGEb8GGZLvybdUb3/fYYHd+n
BdoDEkjVKHusPQrCL8A7K7iNKzzozONiDBeNkTxYhQXMLuM0YBDTxYKvPOGzTOJocUAZGFdrKZox
jkxTQeGw8zZbIOjRHL2iWqHuewOJMa788acB1BNW8XJ7t8tAbhsn/zdyRPjaB99hgdDMUUJDxB5z
H4Yb/WDIJNEnGP9aGhsQxMON/gqZFeY4ZjJ7jSOiiGpGN/hOInGkFFYIKH35dvypXigTqd5s+YAE
ct/WY/IWTNFDERiAI5KcrC3MzyEA1ElE2h97FQOrKuQ5DCK7ar1ZxiFYdzA4yRDR5LPyP7h3C5fc
awniDWNfNxRMoC9lHBmMJav0x5N+Vv39WwmmBuv8eDfbCwIgMgdCNlyJNOGKHziS3VBxz8hOUdeh
tBTdNKQxwOPR1ey7pjHWtGWfVN/obU/LoxQyZsaqIycGhcMTwr/Bpw5NxS56kzCIvqc3eTh1dDnW
vgfZ+O4QH9RlOXTS6ausQir44RZyayV7azSnhOpy8Qv9Js8/D1GsxuNq0UQl8HCOvt2OjIWxR9tN
Ar2XiWb7+eCSYSqTe/3Io5wcaoUKi5/Wb7+Wivu6JGvGQUMeeCCDitcXCkxNIgx0blGiyYu8pbRG
e1RD6TPckEiKV1pnWTW0ngomc1hMS36AvXjYlM4evQvO3xmnsr/aho0Lt/8htLtTEWeU51wJDR9l
bn/BiXfpW41neiuJYVN7ITP9LbJrEGocCjadEZA/uGhcXvvoBQ8ACIQDqVd0cYj+RSb9RUk2N36E
8qbe26lvAL/08zZskWcGBx/GyfMxJUMDqQkeoOG0HLsQIm2/fZ7ZhK4fWbfFYV4x+jooKIWIzgkU
VUM77G7m1UKyBMSUe13AnBUJXEKeFj2MtGouBIRdIr72uakVi2E7kT4J8RgtUB+NvfQm6rFdzcwy
iUx2kkogkHISM5LtRXThHDM1U/ZmzSoM+hpWZdo1fu3quSQPMttczIkx0eHzoaG5TZ0OixD6TXGN
6bJ5JwjE4AbpL//2YqwaAzK5ay+7iGvqN14CK+Mr5+PYZQ0/V8fSG4RfzyTKjWHu8+nrHN0y+aur
qLIZqizHvH0wEuCJtVyYK/NOF16gZOG8vgrKn/J7MH8Ag/S8wKUbAyEhJlIh2MZpPTxlbCoZBhaI
q7hSCaGLiT3ulWQVIsAvcbQhZ8LkmraHEo/6mI/aGmj0ljuooqGPaVpHI5nEoxRrN2zvyZnMSSek
V4HMQR1IJhquAkYmRcR+Jb2c0qZRB54xudcbOIHHxspK4XlqX1asUSDu0KVeMLJ2X2rgjEj6Xmzq
pvng1ZiTGq93FwUZgg1PCHfA2FJOq17yPWKKwm8apFM78w5vXXQ4XuLuj9eHEuicfiEULTggBOqF
Nn9/z70DTY6A7Y88fkKpkoKd6jHKhjrkGY07Wii4LPR08Xqmu7rVCH0D0FDtHY4dIkvfsKWg0wIO
QsvGu3qOJKc11oj6nDiNgBCbFdiTwr+SLdPJjTGG/in9sN+cGZ3FsCvlmhmduaqCFDD+o4QBAF7Q
L4A+yEP93StmG9g4pEU2PMpyj1O98GvpTgohW2cp9VnLK/USnl3jW6ag3OfvG//pSIuvzSEeBEck
4x58UypdmNvVwQhf52K0s4hUqVlcy76f75RQgX46Ynh2hBdNPVuIQTmNeKw3Mm6LHVN7szQtQvIt
MIbZPGklGD0hvdHmnekNa6lBIfkNee06X4AW8e7zIo6Ugz0Vt9KoNju5r4RkrMKz4XpUK8GVcuiJ
HYlawVdfo4lxJWvIx8D0m5uz2U63OMiTIfxnHpQbjQ73VAmaDnn2wt8CyiCGMU4Mm+uOGNB5ldhk
7YYgPgjMlSyY/YcGVSefigLigjHEmw+a55oRK+eCiLyyZfhovzkfR7sGnU+xAx/nwOVMek03zSNE
mvqIfYodFf/ojEwzWXwVkfaJA4tD9TvKzhCAgnZbkwGTiayNbqQWu6fOw0MKo8p3fyWTW0RPCKPj
XssbWnNLR6ridrT0lddBs0vcb5PR5l7VpmgXAbTvdTHYkDTrLgb/QF6eBgQC38R00Sf/7hhdTWur
6XsEi5KuLnf3FZdsNhgUs7Ixoi9xEbh8WCBmUprYdVNSU0NZlQhNrwGovpU4N1FWpCgQIlunz8OO
hcoZe8xMCpOBvdwAsnZCX6fKOk4o8pnUhHAjkLytSCb8iJu5YRTvl1GXaXCs6wZxSlBJptmHB96d
dKqXkLlErSydSwBGujgcwAPkKO/apMNxpwuhlW9+lO833FgVgYMqTflv44SzH428bg+atWTgDjCQ
OLO7cBfrQqwL8vkUsEf8+qVcVPzC2nDdwaI4YY5wUQhJCtRCekGYyCl4Gum02QJgrlqGtDPf0Xyd
5H9GJ8WOFC9KQU88iqJgem9OHB0HWu8zB4QdapOnYKBL5DDB5fEtmObNVB/gcjl1/t5CrSiSEyxH
+tflNdePvI9ADUOGWSlC8WXe9p8u+S8AH+Cpil2ZgUSm4fsP+uDkIk5dCuWUvGhCtTF//iTM5vFz
Z1QJTvJEAGpjmg9BjWFF2NG7+X8YHljFRmGhgbpc/KVq2LHfjHlxFGdDjaXJt9mMNGA5G3QL6cx+
WNzQmz/QE6rMpCK5QpVpJNrz0tfgmSbmCJBtvDnhPITF/hlapDMOqD7R6j3rANQTC8P8rsWZOvfY
9XLSN7id6v1vodNbux/XrP+Af98lZcPbzufgaiv4D+ZtpX26cjY5fx1Cjl/FjIVUD0GdagCcDoug
ak+JTvmFzYTo7fd6Zv1L5ReehxgzacEZxiwRm2aZT3aFkmzJh22iO7AgHPiT7CKC79PFSI2zqrCG
+rKqS4lLtRNhnYBeFAQSELWYFWSKyPM+CTOpcT+CXdIE/pyZg/AvN6ar0ktrSQBGBQgJYiAAFIeS
Xjo51ZEqD/qgE2Wyq65cW4Z6OnH4kDtib8Yn3HXfqtvgy09ASD401/1zxKZ0PNwbeQS0Wk+SE2Fk
4xKDNlxhdvYFp30iYQyNmZLZGtTh+fZQ9R9OXWgonzM0yw1mj+eoEzejQPRdb2P2x/RhIMgXn982
w5HjCQBbn0F1qRd7Co7q34e0zyv3+E3f+Zw/mdm6euqL5B7Oxrt/dmOTBnWic6R8OocwK8GfNHQW
Xc6fArXr3OqbNG3OzULz0m8E0k6N/2JAK5TrMb8gpC3iCDv85lQKr0xqcPhElDvrOsNMQgmLxCOk
XXKxW8gLfKqfPAExL9nixjBs5DeMP7FhxtW8tJL9r4A0EAupQJIkV3QrOMUxvvTjoXH8ypzdbEJX
pitPZzJakSMzjBiLXN2hDFDpTnEfSMzW/dhcsvzynKn75/Y22gRbUvwJNpb+GjgnPQD7nTabF6iz
d9s5MU+NV8a6Nw2czYeHAkSUs91FZV+9PphfGsnHp8zKHVZfTUrtWa9EZiNINGY3LS3xkTgKzVTz
WMjznlMrNU9f31pQB1yeb/eDMUv0LQi2rfviwmUmJKR4bJQtUixWeednCuSBTbPkTlVP9HJfGZFn
Xrx9S0uDo891ppxNvmk6ikEJWyCemsRbX1pBKMswnuUQ0FSJE4y/QQI+rtHJo9vpX0AvLtev8+Oc
aJWJhRh+CsveKw9JLq0wQ/ZXtmFNBLb8+62DgxPpwroV/rridL/N9CWn4qTPePlqCzyBklbEK3XO
NsbZM+OWL3nI50+ku3lE4QYkvpWgdRIGbt+OqkIHbLJ6KswqGfBFplucQYRxLlQXAZLFBnPbhvY7
S9q3tludKfQQeuxccqLPaK2JCTvioqIeUg4KabJumFK9cKofF8CusfzfDMBEWYfGFAI7MSMrgy2h
s6yMIMZfD1lYvBFyWHh9NzIzGeg3CQKb04c7jaG4eygbWBWyfBpA5+/NbU35dtsTS6RB6lUllpJm
nAc1eah4fTKVEuI/VSQ5vewlEeSHWC9RfQLMIfnOu9lvy4+AqeRsRawOUN+nDEikr089jPqTPXUI
Dq0lxShuuF8aLXzRGOMHyFUR8mmXR+1AOXG94S3leKYfyKILBl6tOMe9u4H3XTMyG0bupUAnsQ49
MhvpRu++5TipDGHqi6tuXsBLHrwUwsjZdbOqQLE3B4CrjtqA+j7c2xyZcGGSfMPBp16Fv6fin8F8
IqGnLr0JRbHqqo+j+VNAXlyuSPvkGXxKZ7Yhs/MyjPHC147nMGVMZlz6Q8oGQQZ79M/jfeJ9V/vs
M3oorkiGtqEK+wi0AR8Hw/0MfOTsNs9+L/avEftoHylTCvc6SP4he+35//IUMe66zjM+WebVR/hK
H+lIW8tHVwavNSJmZ1AOCu6O5AQ3t7cKqEv5IQTLfneffwFo0q2m5Nw0WqMdFbu9qKcS+9hFv/k5
Y9G5CeuddMcIZHkWiuSmY+oTIS90ILr8Y7JQoRFtoC/r1dixp1ny61olSmBPEyokjrKVx4V2tjix
hBe5oc93HNSB6H2e4PGiaoPEA/bx8DxHdiSQI1zg4rBgrbJIqKF4TBS5Wkdt83ivXjZPCXf72wYf
JMl3nB3/t3rlNYd79Yoouo4vUvGKU9783LD5U48SJfKGbm/TPGQ4kf7MMUjBRprCm2myQ3fBs3vw
QvMj7UQKANe5ExZ7KUIjR3StIL+YQH+wms6UcicKRecFumFeYDqBdrWhrSh4EhoLAKtuYx/pqeYJ
d32vI11TCXRonlF6CLNVa96Ge6FohLnRj5j8prt6BUIJ5fTqdHI5Ja3NSvcZkPxCXrrfEw+d7d5u
fBJEyoRIzCsMJqFyCXPfV2r7Xu05PbdxOs/vV7TTOg3lywdk8rR4jia0fu03rUY4yZmUF1Rj4V37
xMr3POdLLYJ6fZ9HNlxGX8DtilErPE8vKbNf4hNqb9/fwWJE57OGPIEX9GK+fY8GQACNxGeYlRLd
IVEZZnUIKY/CSKgdYG3mvjOwelmQfEJusZlPY2QOqKVfsCJulRqnFarm3vuOk4N/jjgFyZLn/x54
VvfLRtMTeYLbRfYHExvdWWwfkM8+8ywpstYn/SiTA/XOuXWUK6pYY+/gPxBB/Gcl6xbi7PajJNId
V/rTtgOyyZOkPpFGuC/0fpV/WRxYS15NvfzB/FRO8zA8njZEY5ibfESwl58t9PdCJIAACifq4auc
+gT3iNQVH9FNtjCxmucdCHephLSb8od6DPB/nhXcxQwk3EClm8N2JEKYXOCKiKPFyctylifMcKop
DDCqe0dapbRvJxv0KBE/kOEFPHFBf/UK3pE587cUJUz1sNK/2le3k0vC+D+RVbTBPDgkZHpHPbe+
6C3Py+4S4hZ0NmzB2Uo6j63YSfvev7MrOsYGLeNn3Sr9TD420HDy8RKDTGbgEPosQX7UQYSf4LVe
zkrW4gaRq6818rD/4sF13LEhu1wXhtAjmBKkduSojZruEOxVKdV84M4A/Bj0H9tgzCsNcIqL0Gfu
zUZU//1/5FWkjgw4NRzXWDp5M33X7Bd9eMRs3EHEUPyxTQCN58e/FNztgDSIaMvhPREV4F7eSJNK
/rcUjkFIW4dHNNeNj0OK9VsHJJBFk7X3OGQ9vavjzDPYLFwj+lz2xsun0JHtvr9NyfHK7b9rwT/B
QYdA6wxhPZYPVjy6RwKXhdQfKb/SBmu/43dir4u3wzSZPwUyaWTpv302wu4Eyj8fm44Qyqti5+lH
gHaZdJkDh1YZ53oihv/TSRPg6miL0Nv69OZ7d8OQXLJEackI3sMdwExtPQKioS1t5JK8tFxZkRNa
ruRanvVdeD1qVnxAJtS3ZKCzmvWFYsYXr1Cyc7SgsQyzkmHZ3jLzZWc9MtqSMyyYP2usfjlht52L
xSev58bqgig6bz8cfxWAldOV0PcHaHUBPRqcEPpWzs1q40cNOxxeHCCF/tr08qiF++Y95rvMqVJL
B50xC5ecRqrF90JLwJ5WZVrM2WUgCHKgr8B3PVBoFWAMKuHtvTuvKbi7aMIfPDRG3CFm+p6iLTl1
VUzPv4yUZGpG+TyIsuiRzgk72GgNj5cYMz3nI5BJMWFWd4kl0mDzDZ2WF3N9dh9jRhx0vvpZUUQG
s7IeJBSSWqvL9jbii9wWdkc5PS8+2tHaSe+gduHjWXJfDji0doLSsXimRp2uhZk19tvtyDjeyN4u
pGSVaSj++FDP3Y2VbC1TM7ILf3mGAxX0ONA0WWAr4f64mvACXiJui8T6mzXcyF2sgkHl7X66nzYw
23a09trzMu5ZRZH1nhbQaLwmqoibCbduwPDQDFvq+0Cbcjxv77+JmVueBvhkntZUYpSjiM6tD9e/
uA9jdt4eWyWinCXaCVZz05dJfd9TVtow3YBZug3briptAIF4pgS4K8jdGIyiJS0Odx7fxmwROpeo
pEWoBKrWowpd8IxeCv8QClZBFdcWtG3jA4OWMRwpITuG3/IMwLZtONEYELBWiP/4JtP6t3zjKfs5
aPg2XPzAR5XcErcxxy1a+Sp15BgnR0KY3AaOd1NM0SwPirpkj9iEIUhdL9ErXqKSE0qS88aIjJho
QEHAajCBQ8R9O/bK6KkPp1vNcSiabEYlWg1FnuQ663bk+r31rrQopZIEfu6nY6VL5wDwpPdlItwA
wnTG/0EaxY76vEQk+MvvJasrMp3p+7BZJ7vbPYmkp7MnBncMnE6/+aawMeXltbjID9/vVPB8mnDX
32p3Y4jc3uc1gktRlBceltvtpq2c77tzykMW4FQZvQMo24sqc29ETIztS+4QZLlJCpID52ci/73c
6NiagDii7fFticbIhanEtyi0SbEc9WoLX+yUxiiF6K4JdhOGN4St6kY7chZsQipW7uH1Vn50ciW+
O91KFJBzsfnPf8b8QnW7it4+VCBPAPosO+/E4Huz1jKcgg8Y4k4gKBBN0aEYeAs7v6mLR8dpAmiE
aQKoQxmDQkucfEuhEybjtezf0pJele2G8DO9eezS+HEDjSmHpakke3V1jI8GdlJsZPNJ+quwB+SH
PpEU1Ipio4LYmTC5J9VZfrshIoO/FcSE82/gwko16aa1AG9e3HwDhv28O/ZVtd2sB1cjUgYT1HWj
A1HdP9+XL7aQEHAFQTsPK6oMXcZJVqiluew/CmRl7f+3e9QJAPb32xiwJ+8gSuNYAXzIsfYcZuvl
0Rdzq9ewV4EYwmb9gUnlwEYU6ZkEoDIDlxgOIjXWUnog6bCHUOkWYH+mMAkTt4k23qZyoHqVRCwd
kxJ6WdOgAKzDj60tHY71y8ejTXr/5XxcmC4xy0OThYglm/Gpf1pWUcSZst+RJqTvnQQ/o0dhkm3G
jVRRvbGuoGwrBY2CDjuQnii2pmU7Tsl+y72X3kH8+nulNc5ye0pGzeDIISKVjWNHsHUkJRFgsXSH
47o0SGqkr5x+ajhlL5q+c+UEtIqcsd6dZJh6PGZ6YYogTNZ7TlWibK/CpH+0I+1EinQEFhlG0iqU
ygSed2ggemua7w6xDWS6upl4YNL+VR3MLcaNSF8zlCjkL30jfnxIO3kjtjpFa4x/Zvjc7MXu+eQN
7/JFgk8Qc9j+RUcnaYEAyI8bSKQdfqfA17yIYwRCnTSKfhEWWNOBsBeezQ0ACZaKKdNzIE3N49IY
5MQ2lG8TlJpRhFcnOKgoFLj95xe0WASDr6UaDjWbtbngRrj9/9yOp+nuEIh2B1Io8FwopExPiyFt
gq3/LbdB9puJMMiMi1eiYmcXNmmino4feLx39w9sBt9ozPq3ObzBV491Fux4kUDQufSGbhAG9a7O
qcdTLDh4SA9GluBZV0v2VskSvWYk81rdxGU6o+MdXIvICitFLNO0bs9SKVB+510O/GP37C5sS6NH
1XIWBbefjvtc1XAb+CUjTmLZP1vRdEUNsc74IkG185YQ/eO8KHqpNpSyzCpc98Qq4QIy45gHv2QH
LPmbU/VnrMWGzWQHHgqlQtyw7On+6Iabb77vRFo/ecKOVE54UVe7i6AY4ChY26zMlL7PZB6i19uu
GIxliN1fjCMSLVsfrRD+OCMx7bT/BW/Zb19N/CCZUY1V52rcUXV0WLRItq+mVk52DHwnKAdIqv65
TZywHZ+M7M80+s0wuqwITc9XKmuj7NjcFsV192NcEQVfZamyRDrWQaCJU4c8lyMZp8gPuyHN6G6c
+gCWXoC1JXqK17ktdHdWSbbMezQKawFeUnP4ZqjJgUqHCMICBwokDdES4pL9qry3V6vFS3ST96yy
qA0bZQPxKtjLMJXjKyPN1moItsT+bmiF5cG/3RlhUehvCx8OdlA2hs3hR+PujVI4Tl45qA9JOG6B
/97Ju+ymlEqe9j0y2XUwVgFHq21cou0zk/MQy4v7vXJ1zhvWZXiZz7PtX9zCq6ReihMFNVmw9/M+
bNyfQSmY8PWvxvw3tip6Re7eVNgiIwt29E5qy9mX62/1csOjwHqz4hX69viYSUNPlaJQXeQQF5ND
D5y4o3PxVmm5Uwv54aVoIxmYSZZjsGPbrFsFqe+XBwmofJSj4NUpEi5L43xq1z63Q4eWx0dD4GAM
DyJLAO9wOIYRoQR7jzItPhmHtWfPh/AjeI7d9ufVrV7T7LmKTCOmVnwgE4+UAkeBqN+CgDUxL42J
f5K/JOUtLtCS/wfWSfsNaI7IvAYlsOhO2SxFU3d+w/NIP6AChMYfuseUj+ugrKtST6oSP25+veGK
0nO+DjmTq8O4Ps44jXcaiHKuMiXP891CB6EEdYV7jsIlGHpFhKVCT5u9y/YQxLllL49DSQAXVv6c
wqRMYzBkGTs6JzkbrdH1fgTP24Ia5c0Ld1hs3gQZLcznSV7YNppXT/aK0sRWKawQzv3lPoLZ9ZTL
Z4haWXTEhHZNjOxl5vhzDB6A1UwcbcftI4Z8mOgQ4s9494son3AI7OaQ7o4CdSBqXYeGJQSj1md9
loKUC5Yd27BzEbriz4iy5fYWFQfKFtBgvNUxBRJMM8gEWZEGOdxsGNIYFMD/DvK/Y0gbbb+jndxn
zN7FVKl/hybJrTPUDWa4QTr93R9y/TQygmkVOKgj6vKRRVLhkPciaorD7dI2AfBHqIPn7dJf1/BR
dCPmqqBq6X5Aee9uIpj0GZADf486RzDdER0nQ1f5yWcWeaSwKkoBbrs9CaZo8tTtNe+lzrelpRBN
zIOUKbfw3WbEb/kzLYsBXzHnTS6TPLa+Yh6i1MnksNBdX02WhJtIUQXiXwnH9l+n15w2SQfyc7ZM
588XiCmqrVgnmBm4soRhntim47j0W9RkyRkErtrxP/bnBeYXseUgzAs5Eu/aSRIwkLR2q/HmAr+T
Lvi5eP9zcO7lesgvzcXoNIDB4CpWeuebDYU43nXvlAkddk0ykPsm5utsVaF26Cz8RmZaQ7wyKWkv
0dtDFBGm1XOUMJcFjeVVstS8YEzsExwhW8lFvd7tmzSjSmseNtl+UpVe2rdQK89VutFXwgSzZsc0
+8DItwo2Vupv9rAusqPMl9eJWC1SkLp2QwY12eTdKk3qrdgeXfbH5sD0frE+OGvyKgVWqer0cS8I
iLuiSV8YonW2j3oyuqO1grxpQloV1imtoAXoymv5zvgJVNNZxltv8i+/Zk8foYbtX+XpaPHZ5B3Z
qFScMdBya3aLj57cLtLlcDj79/h4gaW34gp2TbuJ2Rs+OEEvfEj8pVt+WzIUnp8i3cjQ6trNYV2U
1jAX5m6qlYCjfn5ne45/lPh1dsvYX8C7ym7tVDTS08gVL/E5AmREshm2Wp41lz0boLszD1AFMhZU
gABPwgkbuEx52jIno8RgFyWcweH3w/MOnUGESvlnzqoXz9CCGZ9uPsCW+BtEBTZOsELa6Qz8+Jrk
573ZwqGbS8XAfkHp+UmZ7sSCM4bPJq//Q6Xt/UAO9VSVp/59VvvXltQgA1M4kVx1K4VKAm1cOU05
+vbthRFmfS4ztjVT5QrJBmEq5Ns03w25m7ly3nuDgOuaqMH0S8SdB0Ydo6VL7Jk7Qrzuj+qXRZ/v
3P7cVKb1MP8EMCF16gfxlKENjL4sBxbmV+IEdPB4gH0cWGhCV79Kk8ZJvGCq+sMFnDEjpKBNSSwZ
EGvqfycZHCkJ0AzwJOrIqyW976eLSbSDNnqNzMpaZYRbj3knyuEv2SHrFR90xYOliwlCaEjJ5jsu
zuEQRkWSSd7YM76cNzzbdMk3PHTLYOdGbdKm4AyCwc4fTnUJn7hy80JM/UW8Ca8AembkkfsIOfP1
4KCuHHzand+zG0GeJE040oTcNQ5napnZTRSo/b1s2HIEY7E4uYeF/2c8fO2xw94NYin8F1zpxBUp
J4Q7syajY9sJNUiBx+OcVg3H2J57Frzif0P1flEkimgMaA6R9FQfAXmTzHL0n1NFN+MZLl8zUETW
WXC0cGBSVJLLxA0EuBeOjTt05Mx4hEhmU4zGqw1RZ7Xz7D3iGYSV1cdhJL22qxwuQM1r4qHw9onO
jsKsLF3vhKIDE8EgW1si/NQBMDc+wRdLVRdbpz7LQy/MvicYNwDEbumeIR3er2hzSVhHjYsHZL+o
+RiqzKTHRRfCR8abmrwWhYo0DxoN7FH59MnlEqXD5yWbqRymKdWpu6VABTa44alNeYTXngtkh20C
n2/xQICwm+X1hbwffLKMVTIsQN4sCZhaUKWHW3zSsSGJeHkYY8EFVJFAabtUzwWdzejzqJkAaZFv
008RaKDnY3A9OLNPd57z10/KEVe45E+LRM8o8wfqW2uiK9GXf9CE2MtmF42RfNkCauXeRZebdGy6
uzYQwlla9DBHsKr386NmoelRfU/DGEwDuoae+sjlkjJwffkXFCXrKA6KYqQT2Wsafzi9LMEvw+NH
BpoZ2LfLOkrAtothURVR+uGAcP+8EszSRkhgs+OeMRMZZqS/H0L32iAO/WWRjJEA9lwABhgJDJRp
rLIr41b8T438BaLIqtwhCXFAQNCQqeZiQiPewryk1J1hPi8hhBujwkHOKSqoUnLw5UexmIaypUe6
9z3aOMUn7XG17Fni7YLHbsLPo+XPat8kzQ/019jk00iPSAWX7f6xe9clrWDj1zYtM/pcX/qqtLTw
qCpDY7Gzh7uvkUN21nKocjJAKBcEB0rfoD5cWVxkr+EwY8/JUZVXuVAF71djm447McL2H9L95oU1
yVGDc9SNyeoUCpdcGrurK3/gpkAfI8CU4s0666B4rIzNV8XWec8R88T2I72j5jMK1G4RtlP+h7Ja
1JeHbrrf+FprAZ5WOfzePjBH1ZcbfRqMp6HGFuAa0bwiEwAUzVgJhGzB9Q7RAmqg210a5L0xqO6J
F/JNJbYCUF4qrGqADwAMJBnJxKm3YyAoCp6jZWzH8E4ZZmKLGy8VT5g70+9a1e6PdvoKbLVX/Jgj
fu2C6OS5yyAyd1EUcS7mqmgO1jOTpR4LzVt4MglQ2T9YZRxFqnRTGpS516SgociAex9WxX9qguiq
FO1ClzMU5nDIMySebHOJjI+f5dEt2Wr5cIa2+ZDrF1EHiAJ//PViPymNfGRiYXSNVu79rfr3p7oD
DEpl9xDD/5Zt+s37OHscjsh8PXMEplQv6kLDfoGTMLG3kwplvN/O2pP/nvaJBbPOiqDHpFQ5n12y
1NJ3L6oIMn6tnQvZ0MR4hDAzJn0Fjb92z88RJW9ZebUztNLlxv8u6tCULXw412NJYsEXie3QzkEu
wMvXx0YoGxZv9hmfJkonyOGKds+HpJ7mbialoFcHwM7g9qfxzy0QydpgLYSeuimo9PKp+FvwKaFW
c93rQQGpC+erBptWEoDM1wNa8rAQJQ8ySgfTr1T5Y+MxCFQkwX9YvnNa22mJNcCNwQRNGP/Dwf2D
WWMci6tY5MSFzf2vwrkvKsQvibDZrQ/2DbWMc6oF/i3lnJKS0dIKd72hvWJwnSfiqIvY84YHsppN
Fw+TvVwOlMy/DP2yjq9Ei1g0i7tiCJ4yhTuB9SfGsdcGpGsiquSUf+5iRRQ4JbiInw+ZQ2PjmKRw
gbMlBG2aXNRHi96WODbst8gCUvz5NDHxbouVlxmJY9rcwI3aT9pQBjZtJtDs7VoZibjKYP72aMDR
AXl8rbQFwP3NsAs/hfYh4cLVCeVAOQpQ3kJtfiCgwnLYXgtqT+AJS7+llmRg/x/cVjxZEquZSMaC
lFjhQ5SPNERZph3pSvTSZISJInzT6yH+870rNpYgW1I6m5qT04KNThqPpEn3mGS7KSNh5DibM6Yb
A55SEE/KchUi+lMXlBhgL1GsTrNJE/vg+VnewBojB9MlFc1BgvWewA1ntunLMiNfsi4XBMpSxeIT
WLXk/YHIV/MB+PP4wcw5k4fBPuUpRpPuxI5PTDVX/hq7m1PLFEyhStdTbuXrxGeMPHaOf04vkN0N
4cyTp9+4OeV4X/bHGg4A7cJsDE7R+ZbESvYVUS0pps8D65O5e6EmRnogTmT+4Bfq5e0lir6I1/Ur
DZNl0+mYYyWpCkix3EgntYjs+mn761+qks4iepNM+Xwni9YNxn290CMmpoMdrZQmuSBrBgp2nPR8
jYHWLZJ96OTtkXdl6E6kDuZ5P0RhbS1VM8w5Gz2gqJRnRWpe8XAVo/uFGbzHGhjzkZKDrjI8V0Cv
fSWxmeVvutA2lTUlrzjMEkDsDABRCXdBMyEti3N1WzP1duF5hDCY5rIpdxADPdS+ivSAMNypwOjM
CzOQtYfFovHV9kbdZn3ooEt9+Mb1d75gTXHQlgHdGnIiS9FK3X6QGhIXBztnbdJrb86dbaQZ3ozf
fof+z1f90s9FQ37tW++5aoNpjWEkkMiaGFJC+cZaGmxKWTIrAvkkT2W6z65KjMn6r2eg2YA4PUSo
k0PqkCoDno3Rx6offHFNGS997O/ELVXDBdJ1Ehspr8dxlhcJPo+qHP6vjXfyE4vVMgqdUe1D2/gV
d+Ea2FJsSZPEDUt6AhaWWf6BhL7o/t3+5lp7/ETUOvgYZaE1B5nQGWAOvkJqPFOmsQHAz9Oj0o6J
wCRo9VpODQ1sLMQyGu01GChGaPPjq06nQpRmEMAtrPE5zO/Re7L47LqyS0TTCMtufU1alp4Sdxni
oDp4TzG6LOKPoDRzV0jWNEa3b3CT5mciI8yAPdOXWQ0rocD56AV06KFtohVqoxX6qYcnGe6wSWL7
JGoSV7IDnOwqh/7/MpyVJ3ZKcrWDA2z2ZUCPioxKxSNvjQ1BiRkXLZIaZ8VXweP18H1q0TF5sV/+
ADzIM6OdQtB7cNfyMm+2SJHu5hrtga3WvOxQzwWFslJqZYksBLT+ld3Y4Q67pIXdi5C0A8ouGRlo
Vi8dwNuCvLfJpNWyNYeY6Pmpbne7wcga+cz4BHPVCbyNbNV3CoEB3A8dL7tYkrycwW79qi4TWD/S
1QwUUJ2bxfYnJSmynNEfr0P5fgVRPMnSCtUISbmHuWP0qy/re9HESb5gjkysFmic6noJ+HX/6BCT
kfG1klsYcH6CjNJ58VcnMU9CcIXGqSzndUUfSVW0TPnsnnfFDl1pku8MEv9cpmWrrbwk1WCYsYP5
gyrmkuVX5T9418K/QeCFgNbeGnauzynLpkgZuCz/qhp0gI7Y2sTYB0fz2hw6HYrkGHjgbBBjq9nz
FSapqQaqF27PR+W3u9jdspOddXxlMDYgncPcAn9iAZ3R4aOlXAnI28WBCaW+GyZ0Bjm82SmQLT7M
kXxiyd+fK+wwxuhrrtsrft73YrDUSjdRH2XM7qHTYNTNs8wc8LQQwsPiymaSqcts8Na/VOkUrNl4
5snX+DPytqwSJ3+DizFXT/akWXKAz7qZC9BC7/HrYQxByEjf3l4vTvVRfS8dpXfXYzhl5g+KCr9o
abJootS32EAM9icmhY5Ie562wOVD/TI8IpSv62kjQzpHQMHX/P3H1QUik/LQ+E3cxHwfW5nutGY+
gJgBRsIG28ZTFr3zqlFIvJSd8fbxHpA5lcH3xZwkhB29Iz3vZnf5Oqcb6AVD7b8S5upbbh7ZdhBv
G1h6E42g4f8EfNupsz1IsbiXDFn0dfnUu5i/c5AGA1FgdNdANijMzL/OHCthcJU6T+R7yWc4/3r8
UZsDnOGJEvgWQsZ9hBXBOYT7d253hnL861onRW2w/bOEBeCyg40fsGZo2oYPhNelAC6vhUb7RYks
os4z6IZC+AZT8XDwxbQsurAWQL9QQBZenUVGwXJf5msx7b2P3f2JtP3JWSeJ0Zxjg8Gt0h+vB3b6
9ewI3O5PCR6ORxYvH+w9B9E+gEptav/STL6jxdYrm4KUd27mVNti6tJ/ABPEujzsXQM7el4EmeQT
LDFw8WSvDhQpcVSEaVGo5ywoOL4Eu3MQw2osgZmKT+i999FP5RjLa8LwLgZ+aM/Fk/pmREnLNBXK
98DjM2PcraMXdBMZdvL6d7pHgSgB71siLuRTyb2o3ZLgTEl62jejmgEnHqg+Rbbx7CIW5tyUq9bt
pyZyJtSw19BWE829Z5SEyvNyLL8y3Leto7V+7ty2IR6stOZDHjz6kw3zqWaXcVPNl4BL4Dqgm8Qe
qGQSxAjank40lunur6BwKBzYTWQUBKoG0fPmOOE1ETAce5MMSH7sbLuOWxpA256TD3wc/LrsWJbM
NZXmw50PGA7lqE9IDdaSWf1qrUJnPCae1B70NaHZcOXFWVjenSOYHol9EWE3HucxckkGrCbfsLI0
2hZhHcyOF0Q5UCWyOeF7zkszddbDWifrA9yqw5w364OjbMUQu3M3j/aDG8eW90XK5xGi7C0X476o
DsVAvRbXOiapXNyWvGddDmXOTnCGFqmwTK9wZq6wX5eRdKstPV09zZQR8Sq2RLLPSJyXqVPiWx/n
TUjB1a+m3AJ1JvnWnkvUU5jYLfIjEBmzDnk+rHCag4FFgCUtMKsrpDKWTZqYJii+0p9cocA6bC1C
GwdnNr/xYaRPdNq/vfBzxaj2AFfDT6wCRphVJrk4G1TB73i3QBF8APkkg3YBPm0xd7oiUqaJGdMi
/H+thHFi7dWb0Rm3S0u0epSC6c5CcnbuQmN2QgH6W5du6ug8zlQyGevTtzgev2S+4n5t61eDiWC+
/c3+D+WMh9uF/oRAzCihfEuAbVFjgYGWU1Qbs1M6xSvCVm0K4QeZbRbRft2/1xXMruKeEy27XHQZ
TbKLmP+aRA3e+l90HrdoengfXPI5IWVb37+9EhMZZWNCKLmFzw4388/tnU4GSNh6IiL61bJjtPxB
yc3XLreZhSYgBNiSN8xJIeYt+iIzZvTp2lpW2nfkOj+k9mfzSHICPsHRcxk2qQR7Yz92pLhM725Q
DO4f6hRWBRqupUFXKuaaVSgimMGX9bhMj9k4ZT/fyDpAHyLXGJhtr0GhZVcHxuc98PhsusE8EnN6
GqL9pw3jVhrEgwMPqFA4jhz0tbwuO1ULOzRwR+v0ChUtjhAuX39yy8v9iIUN30b/O/fxjvDI/lh3
BYwgv6uG+sUtGx2N8yW2zVukKsnNmckaOGGHM8sRvNtfuFZ3+ov+PHgrzS/rDxOLQfCnkqcAs96g
k8vydJDD4l7rR60FOZHbVwuL/MaHzPf/2lHF9/W8Gsflepe+PmJNLbe7ZlDG18HTBF/B5Pkz/Ahk
bO1m5vs/5Dg61hTCBVwO538UKusHPfmFu8IpE4ED48kEhDSfdkMAnTThBoMbZQoDvP7ef+AsKblU
BSkqAkDMpt8iCioTYBwmsjVIVpoh0iI4arxAGixU2QcL1pfROe/CxPHUKo/xGa4r3Cy1BKXgK5dx
OVi7mmfvDmUl4/QXF+YdOPtEoxWuQOXcBLbE9AJfikbcTcV1c5IcEiUgs6k0EgN1EbkHiylB1av+
eQXx4OdDkpruF/GBaDGFXu1PqKnQlVp56Wc6tzYfKZjc1in4rz/3yLXJYSmR53Dh9ObIwOst4Qlc
YQk8HCYrRRMamuC6LTQQKv0mcL/3D6tnQ/+3NolcIrR0c+FE4b8p7N468v9H8pCKSrpJj5QsKBz2
HEAMIVlvLIOkfyMRMBUkiQX3POODyy36ZlhMYfduEBPg52+aF0EwBPi9B7qZNnDz0DKoh3fYMHK3
JkAlZzivLn+TFPmrQ/D62JAwIuWZmblu/1QPyztYFVXrjJ+KpoZ6i5E6uPiUmfdxqKxmfs+TSqny
gMK8g3Y6pnTeFXsePkXYJtnYsNkJELS1LhZF2ZC5QbGKMk33R+NFCsM+6zGOk2zh829Hjp2XPDWw
ZzslSg7iIl2HZ5LlDsUo6SkGuENe323byHDisO7IV86WVubP8rgUFWgaw6vlBIZ7rTmHQcRN5LVw
EN3+Y/GJjycgqbYwxyvmFANt4Z6Req8M/nIWnZ53M0df5bWTnicqi1/8IprYzbA2OdMxLgmkFbIE
3fq+g9AwIKXPwGC6zlMIbdAa+NLJAcCoSLhyDU37/EkRN43Nx9pR0npdeRuNziBaA/PjPxOMMSya
bzxfKuj34JAW5LiZb69jXy4x/4waR044uHswu55MttFcrXm4HjSmYk9Bbfs5O1GJCMzb1PGYlDCd
kwx/iV9s7t4ZDMRW/iBZ8iQtp9aCECixk/V9HBml66wKMCD3rmvnIGxlYBFOlSZUHuRE+a1lDKLu
UF8W3YSz/G+O8xMYxoKX7mzld/BP2eOJFZLp82i46aq3QZtdmO2afAH0QcLRAZOgtJK4Dsnt4oLt
FulX5tG9UzzXvZUT6GdTz/2QMZbfTzKk3ZuQMEc4PmeqDJn/Nl7L2SnyeQof0q85ZpOutcKWiMY3
iy0/7SjaPgUzx3DJ9hF5ozcJ49BTmU2qM7aGMvxP5e6sr26AGLXiCQV/YvXf/pjxMroBDpa/iwMq
jWpAHfOs+Ly53HxvA4FgfQh/inu5C+Sb2HBz5SsoIFAVwGkSDFfOvIX0fZ+cF+tUEHbc/0KBSqmG
0+zy06jvaeoO1DMGGoZO4WzhkR8lYrrJnCCADoWxoZm5fWnwBL/nUJRgtgPgdljvGhTJh0f6CG1q
liNnVhWmAdPJKkznes/AqB1BSTTRQtw2UlDyOVkHadQC7g2NrqmTYRqmeiyvq1WYozAVp7KIgbRW
F7ONvosynMcd9dk70Ga/+iKMih/gqptW4BeFHxvQyHiT4KeBoLebWceC1Rjz9aztxkxOrv+rLCLs
uO9uHpec+TWnHFWhKUWUDmcGWkBPXCGFxqrkcn21Llv+CmlMV3IVWIN/zfebnwL+dWHKt3nOZqlp
4/4H4YQUlR2tqHvOa+mMUw2X2dCWhWxHQzjbkGcxi7wODdSwFK6emvRwzxe3ZlAA1zq8fQLhICbs
4PQJVOio5bvDk/GM0BgHMJfdU7JZyojvsOagjNuCOuEGxSad4vafCAN1jlHfD+1gbTuxqx2kGIRE
ril9fg6YIcBtZ1YdZg/cpAeae/wz3eDxK8KhyOpa/6qiYML4VHb89nYlp3XufEdXaRBMHMBoyf5F
UrkVumVL1turoZhnYnKAJKTng0At4cFxsRWVbAspk6rUoRR+jIWUDcvKp1TcS77lS7pDiFoE39Bs
Q4PE6YOrxCNWhRFGnQtCu5JdLCVKo/WSj3T6UTdq/u/KVgg8Pzj6SOb6MN3fHdGrajdwQ3BSj1nc
aMMSJz83TJ/H+LWhZGzP/KchHGjS8RuALqD2h19rSEUzak/tfGOVpRQsWmo9KfRvTFYYdghl1AJs
H56zJNvsEqKzfusaCyLd3QC/OjaUXqCaNpuEZmwr0dNjZfAsQmjczHKCAdA/zAEL03Cw87/b8n97
kDqNN4f303dULYxXC8Egkg/L9D9HYetLRWf9uJu2PBvjKaP6MUy10bXa4yOivb7G49YKGlAjnoCL
045dArc6/8ydsLYR/JLBcTtQlg4rS8RPdADy7juHPu970Ei9IgdqkHxPQ0uUi6JNtKpulanSrSPy
aOuTnWE8AzGuCo1wj0hx2F/GG7Pxh9C+VjltVliRapIN0+hUbd1+CTkYaO0hg8HhUej7s9m9I8l/
jepy9ivPIQ3Ph5AaKz5Vmtp49TB/SKwnEAU2aOXtS9s0dMHuOfR47pKMjh5TRZvYUyWqlPpB/1Fb
mWvrRopde5Y8PpRQyUPVeyKf+SADz2l2K9RI/zDFEqwM92Pbnkd6RItA5iOWBMl8qC8Hca7NI/ku
d44TaxJxot2sKmku6ICSrP0kbEuYHUotEPaJkE4iKuG4muMexdlZMp0Nokje9EXG8HS565CRTKNz
otTbisFj0bzPs1D0jPEEqvzpP+448MDlxVne7qd99G+36XQwIGI+vUvMD+NnawarB7P/9CyNkMYJ
vi/NjnTZD3xBITEQSh25a69CVUOhoK57gbgIPuwh0TBG/Xw7/wXM8w+FkIDnWKlACEKEgybImTOP
bJNm0glb0Ko8O1mS0DLjlSRo8mZ239MAZ2jkT+tjDH8gcEetuvozHWg+knHW0iuB3nqWcFm3efqO
xKr56osDqNCULCl+2SEk6KQHIDAbCzliJqLl3XrE7sXAtlzCer0SaqfU2JIdT+aqxo2NCV9USMrj
bSXGHeOHSnoxGL392FRK7IO1sfNerIf8NBhuSYVwnCxcoZ9k3BSCqV1hVX28PuRKbOdfyvw7zDPl
S6mOT9pz59hEU/KyWgcYQs8pwO34+TPHEJEj4HCH+CHc8zBa7tBiKWXLQLRFonZvLhnBFDVN13x/
mkadpS9MsShLE9zo52baFU5XaaiNAddtEcnz4zFfsqLwTpcJzP8yUT0tv7AjOayS6QNrBeApsfot
xvuc/sVMxo8s8TfOOY9Z4SmcIwPRRYFsD4NwPODkWS7T+8gFySonxJjut/j7nNwU8NBYyqInSA8g
w7ZVD5x/iNX30dFbicD8uM+RviURIVA1JtLufs1KdvmTi7u8fsyOnROyxp/pFFTRZcevuO/xw91B
sco+/TsYksKg7TUXmUUAj5ZAuyB3OoQMr6WxlJQOL5HqWXQ/0/XMPmRhuTmjdo2xyWCNxMvK+zjl
nDsmGGm2Xvoj5ujd5OGjySVxlKlXxZTEPsiPPH5x4mrE3QlvME4yVkfadyo4jHTovDLV6kce57nF
TFAHjPyRzRYrXcaep2rkOzHYwUU5vUXbpNNkAWy8YNsArDC1v7igRyofZUqY+PkRpml7ZP57bvoa
4TKrHVlAP9CxuDRZdyK7afL3yXFdMQDXj4ilpv4igt87gQFxUwcv8cEIkflzf0ED9pn2sA/pIHpj
dNRdu353CAW+BItiQw5RBkzj9BuoCZPJREnv/4YduChfkQ5tR5GyNsnzwXmO7jt4dXkwI8bN9aaE
Fndw96h2oCDyW5HC4IEYdI/SU1jBq06e+CS96wl4c6ZzG9vm7npJolMeDuw9jkUdvjxv9dbtU8U7
dfCAV7eQHdE8nLaApAwLvdSPBWBGa/wQq0kYjnl8xewAcVmfOSYfBcemgQwPLbdztyL+dYJ+cCv8
nM6077sxah36EtEQiPbsCfNcFrAk9miGqQvUDXmNn1iPPqL+O8rO/aJOX+PWPBNok1z4PdEtoBf6
QwMxBWalGvEnZlHEHvlIWGW37R/aIUOUxOLIwIGpE9OvcpiLE3jmpcMjpQS+ZPshtdPz/FB1rhT+
ow3/OuMw5awBL8psI+d8rHyCWrgLZP3H+jhy1Y9C4Y5G12lC+yr6x8xwAsyAkVox9Qf7SpbeLpjX
A9CKCIXkwsyZ7DA0aadnjrZr64JKFTHUYgAFjx6XBxVWnv3yKujdNM/aP5BZAl3Xi21x4ttzk8TW
SaOUd+kZ/SlBdi24nmse5MIlOqADGKHRWUCJvxKhFFabPUi7F+JQgA1I6r/gwp/qkFWoY5s+TyGk
7KxpBMpUr6CCOT9OBHPqpBTkNNS7ipV8CqqMOHjjVuj9yZ15lAox+ipfz6JqfqiQHfNvsbHRBTN8
gd4XdXWQlhXG3crYK3M+NJCklLJdRTgNbahq3w0Q0wPhhza/UbwOYesz+art/5iNs61Yq6rlStGA
wzXSErrb7lup9Pt89JlfGSGVxo0Qb3h6XWQ8qqmBig8/pGqzPy7F9PRqQsG47WhHIX9CKTXeUW1Q
jAjreQoxMMkrwduBj3aKmiWedaXE2dSGoPKr7v8oMWotphGj2iGdJELV+cD2AFDyruH6T0Et9hBS
Aw7CgirPya8leTUgc1cAPcVXZUocI6ljreK7vJKjvj3+CTiFPrLqZjPURXX37n8F3CDdm0Pxv+Qb
jximUg5rDFJSFrlKvECyrY2PAHu2Wo7D/tf7mcdB+RRhJpCHwh8AVo+Yg7prvprC95Y9wIrkfy48
vTpAM5F/ErUddGtfiGQ1ftuDsVE7AYz+BPp4au/z7lSoSM6rC7OQ2KNr8KvF7UClD9UBkpsNHM1F
8+lnxVqko3t82QrMV9pTaXHufMZZfO/9yc4roZcUcC1je319MLr4rXqyOvC46K0LLyQ8T+P7vP57
woRMKdHU66eIMIHIdqvx262jbELoFWqCQ+s6MsPCJ35RdkgI8z4a4hOUfDLShtj8+/n6agW8Qe4F
TY7hEKDzV2dh2fVpJPogw9s259a2UBwLw2DgxhH14iZ8Rk4R4w53rdp6jtviP9OSz7qqPb/SiGpP
GaHJhvstPGVfARL927edwQyCNjRqd6eXqonHC3kD0ag7QhAWusbOpMiIVNM8Gix5xa2xFc57efhF
DNLKqm1QN/+EMr22DFuvpdYUchwONXEJjuq2DSNSMXGbRzDHxp6dcHKZuffDNzl+NRg7uRt0kNyf
B6kZ6i7IjXBoRNdbx/Umrrzk93NP4PVjPjmlCFJDaBs4RMZF1sLTxmjPnd6FuTaJh2T/rLaF4oYb
HeZ36vpqZlRxFo3EFjwos1pV5kcB5drj1KNpM3zYInpaYVQghHmnyLL+Su72zPPlULQOkXb32Obp
MFs3ZuUauzbqeo9trrZla8k+Eoz4B5snZ2m+rYfLbTryHF8hVdv3d4LbHmCLYnws++yfUI2NIogE
FQuul2Lw245fl4tBDGmw8UrOMUvroANLNDubZ55xTG9tfDgXdp4jCQgviDul8P1Z+IwF2dWU+kC8
JH5qwLRaOU+mWyp0KE2+S6OoD0pR6Sm9fbpr9MQqeqsXxSBJHmV9qlvYznl+ShBdKpSGIk9jQtCR
zZYyF4mxp1PLbid1A5RAkTMaH3OhT2zwLvJgDWWKCoqyPURB+lTVEb6rYNH5bWNxdPPHeO3IYlXX
fXDhBRCsiE+JotQEGf0UhN/o0N1xHz7D4gw+tTF6jiYuGy33ZbaM8WVIfB1sRo3TNkvi6KuzMdpC
w/DjY72MD3nQDpKgWQh3uDFMKx1T/Lzzy2Mr3ie6srwBrqq682njYeU8qd3PXcZJTEv9IPoJyoMd
pUylGAJP7WCWoeYDUTQQGU3tlGW6N6yGNpsZ7GGgHxqgJLHh2WyUl6m5OeGBkJZ17vFTNsnGyssl
1/wmOVh9Nkl+bTNyuD9bByRZDKRAidQ44TRjmyMaUMSXTyVI0ZQ7OOW0CH/sAFHWOflRNHniPrf7
Cish04DsWIN44hXU49lKEBQGsmLQW8l0asGfHAAHEb2AF2cKXf94/Dl12OVPxQVx+k3S44czKZiQ
FKflJq4JTbnxlu9LJ5FAZHDDqZyelg3iQx+N/9sWsfXQgwTnLNxNW0T3zlAQfjxstJ4vMaaMuPaE
2YEK34qZINWITuWeBULN/XQkFgs+XycxTHvC/ixjLriHSzcrwuqTxeoqIVO5sPMxc7pXa+fz63hO
Sjo+H4tq+K6lHxhYUAT2hhGA7S4FVZoW6iyCUpOBRq7auiGckWZn2RwevWZ4C3aLBaBHo8rdRc5m
XvZ85zWSKrwQv7s8L491rt+p8t4kWaIW/Os3ExZE50NamFAh6Q3R3EXaaVWPCHn3BOlraY/xxEDY
EZl8LvD3ZUEOeahUC5tH9jgKrXsRfnxJJP/cQeQe8/hX+4ScROiwu+WKXYE99otz7uGh5FRtQA1e
J5fEq2YE9PhTQPixzIxlIjDRawbZ9VaIxJzx2tV0Bahbp/EoIVedi1RLrZGfMNku2G5se6Y88OJj
V7NLGCReiqQIZhRKHpZiQ4edwofoAUZ/VvllBtsnYnXV7ksKSVCGokzNjUKgn7polsDe6U7nEKkm
dz2QNQo+xtY6CqvkLOfbYM+gCALFE1qOXADwuIiJ/469Mkp3Y+xnh3HAJI4RHtU7+amS2rfTJEyk
F40ybquvdJfVTFww7HLdE+9/WLmB2a7uuRxZEF3G9G7YcC2k3tA317+XGuZMgVVzllb1R/D8lXCS
zxAP9zHi/5/7J6RwICigM4L9yoFuRwV1vYqBEiQBB3AqO6tCMt+R1nFSyi2953KnWVcRAsKD2hHw
zbdl4R5sb3bVkpNp0FdCyh3eYnCH2cC0k3oicav+nB9H8dZR2F7+pE0O+Wwyrjn69s3VEdPhUpNH
BvZU5Z5GihzXt/yRjVUv9Lo4PVg1iyK0eSVt5a6KsgG6loLsDUnPGdME7AnkOybLsxfPb7b+sABO
lQzL6TxKRG0zlr+rfn3Fd7gkWJzqlM80rxHuSCMHVrlZtMLJRUzc09RWbvQLOF671DSc3BXyxOX7
a7bug8Z9r8grGuyvbGPipkcS/2VTpM5ug/9RNgVfUdyaLWYY+ioHTOmmOiw8VmrH1L7PjfXjigEu
xu6F+nEnbJMdTNm+QjDQpqJr2WZyyAknos5Tc3UP2KGEEtL6w2dF2svwEozt3VvudMKxydlu6Mtm
Dq7/sy5lECPmgfaJeHDwHYDT1PJikxPSgx4WMRrag13KuzwcpK+rHCiuRk+lOL7HU2erJUP3el26
xUD9fkbSyJno2YSj5p52lnNSQTZVzpomuk6ROJ5395Vfd5CPizU6lhoB8qqz3YPtcwDvTaAwDGQI
QF29UAvVUwXtzUHDDPgk/HVCTs5/DzIVQyiwp5yPdRqqMRRzOyd8Eb7UD3HBlf4ZPjYpQ/mAStUQ
m1Pix5806R2RvTG//Pmey4aGppf2uB81ztBNBCHQ6TnSK1MJcQuonKxBoFvqou9PFeS8EIwKE7bK
upP553liGIlIUKyLhFyAmK6q5QOXueo2E9vR7RaFLngfhC1OvnNtuSxBT1aajM1pRSGYaou6/YI8
+pGV+qzlZmciFmWK9kUt8ffPudz08ADD4XQBwNXbxPyMRyXLVAPWCr0dyVxrg4qwaMALkP0g/NaU
clcXFrP9koROTLbQV67q/Qx51VdGMB8qyyRslxrbImlaKVCMz9p54FehqJqwAwUb3K2z7gBsMmJK
vAglygyaIcHi709NCdN8RF44nqEJc7NWbyJd9gV++OWE3vXnh95VKkyfT2jHMPP1sBXlbvCpprlu
WVTUSJ1Ef/r6sx4zmEewfcufNIZ/JTdFYyPKvq7pcJNVOPjribKqIvDaXhwvpe7d4lPHQJfu+mO3
JvRexHlckialGxHIpSb3BJ4kXNC6CoQUi9dk8V/0V5wNZIKfYm3NNyzhd7/QOQTQ9QWV6r/Q0akb
lHoP8E+AA0i1pKhNbC00hqh+tbKrNgTF6vXtjQClSoErVVeXSvUnZZvkdtxR97sNEalQp8TTdq3j
IIhk9wfeWXGVFk49hPHhaKPmftAcL8hUeHkqLA5w53pYRImAMRQI12D5Cz6PvoZbqxswxCvk/Vcu
F2KJXZZFLNARc4QHaQN2tUpaSsLTUamjxJXGV7+qFfrLZnhy3q9DdXONz0OyOp1CZzOOjdsRp523
1XfMZZy9dnvaVKANLKuakCldYegR8GCWXiuefDIPbJeKQhab4c/xxxpgm8OiKG6xkwNCpa7uNI9Y
sSof1X1+DHEZtFVephQXHuUcgiuOpYk62sTbM+afjWZZhBPEDmT/U9sSQ6jyKIsavwqC2EGVcNpD
YO+PzKV/a/X9zsdHRabBTJ5Nc1iuBi248eqkjOQLBq7A/GhhFamIXiYdAamvSc2VvIIpn4pX/sRT
nN5zegwg7BQ6GWvykjyRXH6e1tA+tkgbVbXbEPNhs5sZIoFEyNwPqx7j4GyAJC2Wtmw/+415tv0b
3L1Lh/H32SAQDiYL+D3a+HQmfwVYwnTCI8lqPIUSYoiPPLr85lfZcp7cAXlsyWfWkhzkef6L7oKJ
xB1V/alJ5A3mZtFcyeqsFIm5Sk9B9FzhSECDlf7RHZQNOvp2mEZHWAKrGe7qcUV06xtCrrTM+qTI
241Th7K5f8gIyC3iCTVjoucmAVCLMa8QKEbDJYYmOrg0qBmk9pmJ25KbMmEiyoDJbJYygw0InFxM
/g1cxGrPQFzBIpiEMpDZx2HgJb+ZxCrASfJesBKHX9N9Gkb1jfYoVy9F9XSek6I+vAxviGCSsbWo
IFtq64SGbH89ljISnjKVA/D3+kTko2sKwToGILjroWTR3jqn6drzXSLwjT7H8TUyfuaxIr+sY+o9
WjV77elPzDTzMz1IfzdaDbU/W2F+yfJukzAfM5YJEdPkwSbSbHoyxVVT58a0ScoxIL+vl8ICGhYN
kU57VZ8tM5gqulKQqX0D/+jzoYU0wL07p3CH1r8xDf8ZMUr1l+1z+IxcxC24w5X/7aueAhYj/rmG
6VXz7/U87Hwmkc9ynTnSytzqqVjGqUqer2JMYsBLLNWPeHaIkZExV+sW5Kgr8dNNN9bTvT9KnzT0
jaJpyv8quZjEIOwHczr+bms1joOONd5YJOlyauAnLEjiZTByRgBq1lHtU73QxAe2fVNbOzLojvk/
ogXhKnbseemJ3+aWxiN10xNxIej3ed2mFdDRVBbzbSfsqNx59qPxbHWYwhuvpxbKI2TCoWs/bO60
EL3JbV5xzqr6x/tYsoh9SBTVs2OrR7/abBxyMmsXtf2bqfsxiBTORMZ/Z0sOvNql0NpOpmc2pTnB
jwCwxng/WG4acTz8dP5guqwCpfqAhAvYd8EJBQfTEBAfjVi+C2y70Jp8m4xuPE1rCV2xWRDHM7s/
0txhNff4MaNwyT0VNP7l+QSjFnoUmcTk70PrOu0G6iCVnvDZNJRloTWWDDf28jmpplUunWM9fBbq
hWP+eYXnOXRdOyDmBajW/CFKWaSkgQiDyN5GMidJ/mjnHLdduk303oVenZRjytL2qQh5KwR2HXi1
vmGvYJdO1budhzEVZDaum98pCg+0ZXlLYSVB/8N/rFMqRVGNJzwmHzqeWdgRTdQVHn9/zZCjEGeA
oMQ6zzj0ImgzjTMNH/e792/yBr94cI00EEB8eWBE36psZ+VMA4LV76g7MUtsTJgDOyZFJZzROTwU
e5Zs2Lmk7585si/J1hPVONAsZJ6sj0NugFYuvenBWIu1FL2vOrmJYEHBAMNu6NATVAQwXfAzkEnv
WxKVdGxcryHkbxy1de+jTdMu7EqXBecsGFSTHko6UdWor2af2bOl3A5OzFGAgqJQDHOc4y9I6jMH
zl+EzpNwCZphIrVI8ZxqRhNbmE+aDEZDfkRvMi6gLLHx3p1QMbEz0wk9+I81pxCkjKxR2JC6JHam
dAfBRn2xOu2wxOnD1A0pka9ZKajwOhgtsCkYWze8v/hZklpXoGsxGWZPOFB4sANZ5dTw6/p2RNEc
MzRcFTuQie6pyG5DHh+SX8YXy/BOdI6XJzWjgAy0WfxZaX/QPfoQAd7OVg7TWQbVMLbX88INgPCo
5zPuOuS4p5+7P/jqsK3sl2rNhIWnJc34D5/VF6O/9KApl7yDjwBZ1Ph6DPbJnA48vszQzQQ79oLf
0HuNTlWkloIHBVchAEQveRykkig8DELf5oFIdgrf5SUeBdDtsbLuqrhcpvk5noemTnpjyE89Bk2e
XEkYRHr2CxRBB64zm2iR2W/4DIAr5HV03Tvyh3SHf7mv/pU2+UiIY4cOgiiEcEhkcRGsGRsIg1oF
UzM08H9uY6OvCIMLgZIwM4IGY4uptRFMnPl1tZ4+rt2WYkgiUGMHCYFPsMPIEgumIgBDVu5uCik4
E+CZj+DKs7fZ0UixEmvMeC722eIp/L6JRf8YiXlwqK17GYGZCH8upoh3sGbvSX4KGJV9TnUs5ID0
O1Kd5HZ1EiyRlTpqx5m2VYfkE7BEIl8O0hgnlV3iR9kjb/Mhi6IYWH2K8XxAVdSUcN+1LSrZN8yx
+BmZRYjNBiuEfZrw9rGfWRtlYoAUk2BEM9L6XiiDa5UOm3HteOtT5bkhTlJp27wOp7YfASuPWLGE
XiJqFWvTvH/gDg5saa1XVwbHD+W1lIfvbRakeTc08y8D2srlOsQc6Eip0K8nIwapvsVaVEELgcI5
O+VbumEliNe4Oe6nW6o53z/qClmgWzGjUICKog5BFGTdsiTZh7AVF4cBqPlKURzcYqUy/oDduZVA
ff2ZBknMKB596JXSV7p/0ZeuFxz2EdY2y1ZGYC2RWGRLoDCx0meeTk4QjTVwJb76zrq4ZuBq8eUq
CD1tEMl4mXUuAuI9XNJhgrfMnBNvIC4PkqEoEvqleSDUtWESvdl1txpjG7mO9fgMfWEb6fIk8h0r
fXf7xSI8oN3+bn/AWOt2Ecvt/UQa48IOOzhDBSVfOIBhQw93Gm6bXH/ReDjoLv82Q6IvNid/5L8p
bAv4PITRGEvhhuTBXmVvYx0OyGNYCyPDXuw4cO+5v16VjilyQ0BDhESJHz1+CdBSgBr10HJpkJrE
0Pmo3CAAf18KVV3f4mWIePguhp+rL/dW06kBykJM+OdhC/ouENAM/gnSLZOn3YP+iu4o4gqKe+Hw
xh/ywNM7CpZU+HWRxPVggIvnpk13XIOEGgaMYcDLq2ymus9myrbQHvnK91nVvQykiA5OV+uHKiMQ
SxFDhX6mIaV+I/yer0GM8Mcn26BdlBCDPvT2gNrU2PZOmqj3BUpDUv/axSEZdxP8PWBqbfG2C9EG
ITXIp/3xR/+aF+bPdFC7hkcA1t09Y8lPa8QC3Q44/3oVU/VQN6yE5Debz48118tZNvhmYsVqIYy7
8wmQUUlTVsVOaiRNnajOUJtxcb/CeoaudB1b4S3s9ygBBOY3Q2SkGlHcRMJgdGSjptpH0nJaKi1E
51kQxmIY4ey6sF4zcDnyT/lYGBvraRKCsv5tE6je5GsDFqZo4JQl8l3aMA2Y/Gaxi7nK1jXfmof4
b2qlfXDIDm4L01Xl2nWM/i9NADmGiTximS57EjBZ8n4jftg0nPUtk666cgvSFHiUwYx4z9SfUCQn
0aF142aE3Lq+t//E+KKoU9qHO8F/8+FYkJEb1trylTBLW5Bc/aF4FixA/JXSLphBoKtqjgTaGoXo
+Rs+JbAR5IS4ecBIuXt948dvnsn3dXoRdD3zI+wmp/phqwM9Pzwrpg1nbQoTu87qj99ivxIbIWv+
DG8cra8y/yxVBscsSXVCsDsU9Z9oXS/vKa9/ToBfIwFx2sVnVmSw+KFvX1trP/1u78szSBhPFxH2
BLb1cZH7gA9111ir2a311g5Ry0Iemms6kSBWJsOuDaWQzfV5yyaw7s99JCOP+XjUtz9IfotUY8UG
5P3Nz5SruZYh5ZeeVPHBXNDIz7LhG7tLGKj5uZEIOUWpEEmWdi4E2XXiacGbf1Peo4yngs2Bke6v
S0VQ+sVT5AeMv9cievE7OkWMBxnszR8ax2woI+JLZUTjiOpsf882dqjqHJZibhvTh3Q8KIkXmfK9
AuWdW7fd79ZK3M6sSsabkIr3pbLWf4ErVDXfWCLVz6ftBCVnhosjWVwoMiUVuiL+2ZfrWolWWZqD
YRxrF1PPb3AaUex4u8sGeoNtgO21KGjrZ/rAUzQCtA9TKFlY87EZ4mO8nZ8c2DxlQLHIGMIyY6h5
zf0hYzG3IAhRPhhWMymRMkbuQBQZSgr5skZLlnRGLUCe524jGg2Rfdp1fdSfH4BvfJ1y9xjt/qpu
AVCb93+WD0+gQzil5H+UbiG1mW4YKxnvLIPXONlZIZ+H87bNJmTUWs1ew4Q56nRLOfdbXNvW9IiY
HCW3FuyMSCf36QNiuPVmbqqGxIaz7vMoyOr+ClK4KGFh0bTH15Zh7uWR7KU5Tm0EyJQEG6prEZpJ
f6lDgVFuTfMAgmYwHeRXLPdna9PzOYpQdRDryBNLY30kZ2Emnftyq80FRRjF5WikdQ+Eh/YPGpWV
Kq9dfxQ6IhKdv/uk/XjPf5PS59wVALhXN2y6dPvEv21XEIlSxISk+WoGYQ2D2tl+8+LKvZbREFLo
5TLibmIjMTliR5TG+fwY8j+sq1xVPOkGSKfLblsS3Iq8gFCQYAxsxGYKbQSPUPcbs7sq0NsrD0UN
Ezi83B176x/n1suahL/8VfK8ni5j6K2MUVyIWz3RI9W46QLGnHqmpHr5io88eNEf7iwb5uP1zNjl
v9s2LAPpajYhVh8XOn/aiF5hqS09rVV3/BPGsKVd7Y5JZgmFT4E/kO245ZdyLb27+SVwpP1sO6UI
G3yRst9iER7tXKdrUJiLlZziBknWDmZfeU7xypgOl+Bz68PFRWtnNqSsZEw2L/F+/sTOilBbKvI3
pm3uiQKqAFfKW7QSQsbB5c6hGvVDbKE292KdofgaB3pPrt10ddLxC/OLWW/DN/CaMAjWvDYx6LDs
peVv0/4J+ADDDK4UBhJarrvnESwzYAMieYJGbf8BIvBig4xYD4nQ2gsAmyVihnQM5Fh8+TMwB+5Z
HQZgAabYIlyDbJUXtlPIJYfzYeAGhoq3Sy24D1+KOtNq6ErDTp833LvQkxELbB+VEevAlrMP4e94
fVj3aZQI2qd3KeDWor62jSJfhj5OD7X3rODp50pqGhJ3efnKLh1TwN9vZiq2gU01CFbGZl9+cEi1
dT/r/MsG2FBE0wTIjebxTvVlLllGXeqbV0Pe472za6l4USrSEUT1+H4/HUD2rw0woF9e3cUaDPTf
KODqHt22z5g0JOG/z3A8q5hYC+VjSTEpYlxQdDiNvVsUuSlemSyR7fDew4MW+dX7aVV4BKr/R+WB
T6P8CBWVXgdC0JpOkHUjYFGczKgbQFGMomEQsn+XsIoKOnBkdmYbieTOIeBRFGxFqcGJ8okZ2gFU
pJErzLnAYSnXmZwmUzMqLjdPeiGcUnSnEXEO7s+9PoxhJlanJgeCK9yAqCujYz3eby22Z5vJsX5G
yVsUVQRyiyVonlAVjdxKAl8jhNiu1uGnjyAmv+p1Vw96SaWzV5ztgXKmtT7TSnTZsNfHvqTFI45C
PDP57mXs8BYLQVAfp3zpejj+HQs973d1xbYh0/2I2vhsghx5V2zWH37g0b1UYEc0miSgOGZDUMUr
yl/s4NB0EpWNtPYINOWZBgCtlTbxf2smE46zI+pT2XOwUu0ZlD13dTDoJ0TkSGOgcp8VoQ1ALoW8
U4K2KWie8TJIOjAs1QZ5T/dvrMq7emMq//k6yzzqW+SIgeuQznVmQPfubPtfuQ3JPg4Jz/yqOx5C
S2fi9/3fdGlEFEkxUNzH0Z4qeuHndfAL1BowwLjsWyRDFdeui8PBTH9P7e3VD+PxoENjCgmqUJiS
t9FNmUAWxX2qP77kK817hYTjUwzZFfmPoLUEkMKyQl5fUdDXBWG9hdHgegvwCVkBpQVR6WnDpPyY
z6w/THHoB28pk/PlbZwSqG3m5DZLI1dyqjKpXyV9/1uyc0vMXsTdDstG3CpUGz60pDrVtA2srACj
mVwoZClHRLNSQNl4kgY2Ofk3cZ50VpvPLhWkjR607yVjqn4Y401HzcvCpPM3GRn6DYn4dknbGxKi
fNRHGT024WHjDp62IFpf2c2r715BphIZmdl0CZcP4Fau7ZwQTTVkoV3tVuboR0IRaOhQxctDZam0
bKnzF8846KC4PgOoinYqzkPSXuX9r+iJyslC3kYZdham8gp93BzwShL1nwHrN1xCTxuAyIfzDMWI
BsX730B1QMEwgEKHxmDncwHKU/VfdmYgiE5XZZqgSEW+DiVn9Zwyi+IwFt4fmzgk5e6Vkq2tZwp3
WlNpKkLSzE+Odkk6DPd+lnwh/JvfIgQe7PKzJhGQtyDYQoxwHVMwExkNPHQdHpm7TQjIUqNlZ7CW
z3U1/CwsRCnLqyVIPoXYDbR1HQ+/TfJ4r1SJahLRaRZSmb5szRivxRcwQT1YZEFE/4ocEKj5I4gV
rv0nGycktfda+PU1nMrG/QxlkQqyBJYYHjapsK9rzQ+o8gLqdV4LzxfLiNKwupmSO8IipmGzo8/W
Jsw6vDLIu+ywwhuAOUdLZ+QVw0Eq+5RXFVPaqCN64BaUWlsABtnr/mSuqMviR6ewnGcfSA2OqQCK
KPPpbR8aoWbUgmN0fu2OG34aE91G9+5NUYo2RAnDo20O/lI8JAPx2y0or9+P9qsPu96dPG/2V0ok
f5AjKFXXob4AuuNyE2q51iOVZ73i23VGPiYGT2SXECiquW4PpOUraSueT/NVfe4p20JTUaKdp+sd
+Ks2BIexMbCDD85zNj4sXLrJwnvlvOmyTXA0QYEjSt9RsLHrxOOdi8ulDZEH2C15EXNnJNfPkJeG
9qh+fUx+xY2lytkGXnW5Gov0qiqa+W+TP6YfEu/n6yZ7jQaZZbtYUJ+j+LY9KhItfRU2ljbbnc6l
YxbJGPxSlGV2CcullPVEyMmbYmaggGWuR2n3Fb9uIxcnuGlDQMEnI/aA7N+/eTHbfHygpwQknWpI
4bolYeJRoRm2rliNH6xfC0KNYemsmU1eTpkf+9o/LKkgvyM2hHt/CRQn+h9vC88LYiTtj5fPJYoU
neB1trJI20kEtyBSTpoI76JwyY17Sw5/B6QeBllIg8T0EAuS5vxWlEj9WkKCnmCFaDeUNTz4xbk+
mmZgp4dkBbXCV5dHlh/ZxOHmtIE80GdOpg6rgnUik5oV2LfNOeLPx3G0HC3zs5gL/pUjGlUDD9UX
qz/ANz5ECdQzKOelBV8p1juIms4lC6BLJXPwAP1nRkT5UQ0tapSkKOehuvK4aS5S77eVFO1KEx11
rJEGrqQv4600jhJoldKD5Qmc6s5PSZzZ6ZziWGrZGxO1ywps0erLC4jT4eQwZFSM3FbopQOih1NP
HUyJ08aUD1Uam1Imhsot4LeZSIoIHLt+e4AGYeNwLE1pr0Lwh1W6jOnOgvO0tjIuW5Xh6j8yUGfC
1rIh7WtW3M8MYfrS9KMxbzJFV7YWoMdOfrcTenkeCMdR4/BpdmakPcPaaOjuFum/HXXGgypeBdni
vrXuHYHVIfP2lEjb/sd6oHrYS2q1WW1NYWYJCL7aapgvGEhDfUrp8wu377dFh4Wo6kkrz373qEKv
lJs+y6hP6tKLFaXtTVd+drZXBDEayyON07OTRKJU143qr80Bdph2U9awKt7yKdoRrMNTjvqfRMxp
9hGwnjFXPDDXuuX2DRceCgqcWJc4TQrstkeHDBVdjTfLBiucB/9liMkWuxStl8d6GPZTu+wvUz6C
k3aNA6q7Unmim+DiAJfZnXFHM2NHT6Pgm/2LfNJc2uNoC3D9VLIgRM5uIzXOC1dZCmob+TtzS7TJ
t35Xgk562sonZmtlUo24axqvgrluSZVQaX1WS9hGEU/L4nhKNRKOb+kxVs1I//NvqMvrfqSyfyKC
BSPp6glH+5iS8YSZ5xR1LOuCz7P7zSL58ET5ymfCTmJQ2CS0S9Or8f0lZbe1CZ3llMoID75jZMBn
mX1ABrvZp32ubKV8h1H64gy5J2hqEW52HwvdChVenDgduNTFRHMuZK1Ciji4Z1pw+2yOSoawu0PI
c0Kzdg8jk50WCtSkcYadPMKmv8WW6bcod9GN5e5k886rwlWpzuomtVjNAp4XZMIZFCakAd6C4KSk
wCs4WSqKzaVzIRn7t6AA8PNdkBtK4gYEl6xwselKuqF3zc3QC/wx35miZuZ1iiVcRHIjkLLIvX8I
Z11Ppz8XWl2YYR6am91ffCj0YCklh2RFA/+uHmN1XtbRVFQeiapJd88Tyh9uHNWtcj5Fel55QZdV
99hMv5bdLgjKcCtSFarmDzTTuT4BPkj7h/SCBePQmx/fgkiHRrqH69jEwNt52Qyt5YD6ljz14/iD
HlNyf3Isuxa1c6yb4irfTrbYLtxAh2v3glATsZ5LGYixlMIL+KyhhYlRZ5hq6MW/A206Dzm6kGB5
oF/9A3jid6TPmlsTQDN1T+p6pkhf2IC6EMO06fNiIMzvqLbs+lwBnmNxFrGhVTqOIHiOp/0RR0s+
Cz1vQ6YOI/iNDygANhIC4M2l3DEQG1fPPtxaO+LynUhhMguVNqIaxggraswNO+CfubS2EvuJNS7d
a3acjYFGvSN0nv9/F3xzGo4ZEj1KXvFtQKXf8J5dX+ohpXHX8mz7W/qcXquqQlY1zPEqBDktxpCF
sdUQgLcOBjPva5iFHPXPxl1uOcUNrw4SQ8pVgHgmmi6pouJM1359nWTr8rlLzBx+1FI9J82nhXQC
DHEiGNuuwNX0LygdMO+pilqfjPMxOiavCSmIaK+MGO+ZMqvh2wKhKTnMNDagCnGkQE/BpwiP5aEm
TxwZkPSJSUAlcMYi4m+IevsaUVOiJJxDwuWIXpQYlV7BxzcOHqJn1njUuaoU211lCAIg6e8PW2cc
4d5/DthR1W2dTc50KQJVePsQhSHZulqawNGMsjgpiVJAQkXpygcEfoVNfa/E1tmWCsUd5qZejVRz
C0UgQOBH18FRdaqQxIN5JOqMFHOD9CVfJ2JjEBKGT3qXYSgH2Q00YW+L8agDMhFLblLAw2EHCJt4
1T1LrrIEz5nPzw8/rMAq95XUZPHf4pXjdSx6DO41u4SAnMCpzHIWkkP8PNu6PrlHJbf8EpmfKrix
6pzbkhmPIDeNfJoIVSNeF888yLmtXEsqYIMSccsiKelIQXUW6HwmMkGcrMc35h6g+HVLvjNp7NVT
NFwR0nNnQ5aTN/q0Qbj0aQRyVh3XS93eOwfXqVJ/lh7rPGD7A4t7HAQoWfid9oUR8UH522+qlEbM
RZsR60+pnaVwzGbxnKF85CppPhut5zsYzzx5B19lYDBtgWwK91DTI/9WEOcnXlW/8gqxIIB8jWnJ
Y2TDTKetxwFt+qkOiFnkG8C0VSX8TfJ9AGVmbIyOB/pETJuaMZj5Zc3+H2aGTRiF2+TBD/JpKa1E
Y6HVN7In+GG3c9Wc9ud+dM1/7YLOhqjR9+O1m9XBp6pYnXAxC6LJFa8ud1u4ZXLqPuCMZc5Maxl0
u6zQbRZF4/UqQG714oK1WB3n1ayA8KsvmE6TlQ38TviapTJV/FSKYJpubWpehrMn/bRswO63eYxD
3eucp0e3cQ+jDWmM58JIYsNQgDXbvkmNg9nVH8SGQGZL2eU5b+vHE13roTgx1/roTGdkW6mQRRfo
S6qtT07E4FHB0Hs7af6alaGsd5/Kbh6rRVxqzmJeuYDT+rXAT2ZkR9TGY+BfBvO5hGOIf3BsoRLh
aYcOKEgSqAMIRrAy+aCbZyKsU29ZBUJvjGmN/yGCj828rfpjVkRH00MnT8hkqhNNC7FyGTBXr91S
u4PhkKZY4TFR/NKqdRI+ggL+7mQSaqRD139V/e08NYN8Ynl5aWDTRMQrOazWaZCJVAtYoWCY9JlJ
JrRRdnh8sU03uz9EaKoYF2IOSyzJrBpO9li4BY+JZLnpdRWwOPgA7JPVneS7Y4B4nouM1VINFiaH
wpMYRjRnxsaFpvX24FQ1Hlfp8hNCa8s4J9MhlIvoHYyFdbubztTxNeukys+z4he1R7ivRXK/75oP
7kmxkuQiGA8SkUx/FUrqGj6wgYq4vwDJe9sElJyyif4hNsCzWR33d/s+ZGOc2cWKs3iBRW4oY4xo
clkN29MgTkOe74eV5byid6ipkJd3cHfOSnGLcHQ3fOHG8P+euldHP9ahKwD/YEe6j5PdzEgI9yxX
r2fRWYDsVuKoATN3yXjFJndd1I0jWgrzjPODNs6TvML5sQjCKutuka/0xj5a/0pE+2Q6LKzVhqYI
VSqxGC3r3cdru+/p7h0Yy1eQ3mnrYiTlD204g6jCE6BHnW8r28ttdD2uhV38M2lBr+tc5HnxKNzB
VxFUeO7GIS3tLA1A8KbjeB+y7pzl0cEWoN0jBVwk6nCHGqe5/OLe4ZD/lUWXs1yak4LsKD/eUSst
PLgw9ejm7H2F53xTHjXNirU+2oBlz3O0VNlAZmz3zmCRfVhkGj36KErPpgP4O16/I4wHjzgkxJWj
YrgzyCNkUgVifPZ9VbqSuOwbsCBni4uj2I/hhNi2xk+cA7IrnQ3Jl2FZD+RqiX0sONZ49b+lVfgk
R4+npxAlYukwDQx5RDTxRrs/enWQcAkyTvQcCK7P8lPYyGzqqq+o1+I6Eps4KvMuyy6qeW+0xlrH
auaKX6kNknbBrioD/o5F+DmEa8h+Em2kXyJJn+Ikd+3P81G+4zph+Ofiwc5XK02Pzv3ofQSlkyQt
Vhm5z8GYXqwcAdGVUibWzcu4py//OvlJV4vipz0Z80Gm1hWtGHYblqFNYAsZOQOLpwHRxwa59V7f
IhHs1cogSFejidTU4A6iPJo4me/rsXavEa49597N0N+z36mwhR3pOmhgYQKPGVZKU/vDqKbUZMQf
EF8yfGWwfw1xM4RZBqTcLK6VKwkuKTs/RrqsU3mG6te13vO/JYPRqvZHUDzUImyXxyDYO6mNrn+L
tJKZH008SdK1T57m5Xt2CWKsZFQ4Q/YS6W+whIvrwou+9dqyYr9GX8kP5olJwuq6IPc/vwTUa5pe
mhkj6D5305cyess7Q6z5C0aF03zy/OxbiBGqGybmYF0VTohpZoyjx9jFffRljU2/yT7I0PVl94FB
UZqd9zGCLnGZvIrgXhGibwIuU8vSV474Dr1P3AhamTue0GdEFzzQSqSgCrJ3z0GL+rL2xY15AO7Z
WgXsnc+V4QIV4FXdFoYZdN8e7OqsnxGQvNJc5zI43NN0wtUKeSXVAgdbi+J8THmeInFVd2kKzLZw
2Az6XMPPr38+wnLV19D/4c2m+233lKxDIMKlrN+s6AVcYx02vVUAhciGwJqnsu7kzOFsMu5pfwRR
UNWVPKUXn8j6GNhLbPlya7nfrlNA9voXyPfVZX5Wv9YY4eQ76nENcOvc0sXPfKtfLXjLgo3v06oE
g3PP08hpP0yBsQkiKLf6VRABoxQsAxPbAEMIlroFjqLlz9NOMnIDx59j9VDLkPrxNj1EXdeTErK0
WNxtbU6MzNFxNKDa86JTruDKqekh9LwNMx/LFuF3UGuGbDdBJUCjnYDICdgT5LdMBEeP/EyiIgkv
e1MogmyiO2qBjurCkqsi2uTQ/8o2KrE6bCs/TQ+gTLI3cVhvMx0STkwkIaVG4xr8+yAoBKzjF+rx
JltGmkh4iGU5ufDyUtbytozGDXniWUleZlKOTtvTuUQj9+VgbOSXsui4I3qox+eEwH+eH53G1wzm
y+rIumB+HEn50qr4Km8jq8s3PcMR1shmrUERmYoESKeGLOOScKrWBXSJR73ZuqmhTZsQYZb3fqkl
Dv/wnqan+qBJ0cnTRQv4M4Qu+NX8AeZ/cc4I5xPAaGAlT7okFaeHOY6GLz2kFjnJ+EC7Qx2bup2Z
l7RmdGfbaLjA3CaL6UAGsIYNZToLYTclaqU27GFmNI4xA47TZ5YrA7gMtVQ9duU4Jjv4kNF3/uc6
vTQL0Mipa8tx7sYihQO8CU240SsxLZYvPqea2Kzo87dH9QDPc1wCLH4OzR2nBoU6ahXz2naXJf85
LLqgDEBlU3NzUR0tIEOC0tpB1NyIz8995Cu69rQ10zJpRMVRxHCwDfxX5BFp/M/SOD/Bbdc3FmiB
TvfBdVf58XRlhCejJMxgudCU0qkLMGQiHtKopbDV5T/3Y6lm2j5DVXiYCLv1f4oF4eU3zh2rSooP
9lvemcpQWX4hLUYMWw916DTSIMTfju6mgQczr5Q5it+9/x8R0JOlrkZigsXjtPZz3N2QeJ102/wC
bucYZoorMikbMZ9KzRS24EVuJlF3nyF6F4Wx3h3lj7eLGvzklaLhPTvyLWRweW5aKvZ/ebZ7qcz4
ZW/KxV8HZf9HcgxWTd+YDcDsGIWkP7FKT2vCvbJB9VW158o56miUPwSDMJpkyzOsvUtAqodIRX//
g5aGHTxqgSjsfLNMv60u5dom0OzDFW4lVzCL7I0/KgUoYkdXdaGSGODUuBxxyPjUlHua5bWX46Fn
uZYRxavUH+BdwqdTLdfh+6PtDwXsShFRrsa9O5osg+GdmTDnJii0sZKCu25B88+R6jkmZj7ytoYJ
6RaDTYRx5iyDqehfiRMQriE1iwvmX4TgyUmY/mkwpzMss2iTpldIf0CfVxXDJ6hGC7UUexRLYFP1
7D+/taRVE9oWng9vRxhD+n5VKNI/yShXWWVt3gMtWG3ptUYilkwlC7R+xkscoXH2xZfEHC69donC
htlqaQPMRKLAs670+9QMYZr77jrdrJJ3c0GIVpxnkzHXXk3jKwC1KbR0FoaN+maHiOM+oenPi3mx
Tjt6Yj/JCQgHoH6aH+2VEASJnAO8AkCIsQ8NcqK25ifG/XtpgmzmyKGbdBAUmnuvgShJC0UsSQ7s
spXlLQWs+N9KZJ6n9DuD+SW5foQEVlzSWI08tMC+83rQvm73Uhg6/D6e9gwS0QbIKSfuXvRPPnNL
2H7FQ7R97tNPdosMCHoMbRR3q0Fdr/BCghz2JHDfEVxPufldrVtjGNrsf14R3ZAD/bZZU41JFq1q
kTIgRcrkqo11ZDWjpNYDajejPsk7cx/i50H7v1HmH7W1zk8kaLI6+/h9COj7NTcGpVxrCBQ3eSgh
qUOJqR9VuXQBjKxxFyTSQ3BkE3mHG0c+VkuQTB6GTALQwBAOuYZfiByLewlVKU3cLSZ8GwfvryBf
I+6jZzJSykBi6muW2V2mguVTTutvofYngLJiZK2zrTwZnrqqhwgEeQno8/6z+FgMgrzV3VJlszAa
YOYIENsHrh+4DYPLsk86SnSGrSYHkf3KOfI0o1uktwJsMqHa6HcWr9ONQF4hSOypy0jGcmPYz3dU
TAh3OWscrAD5TssVTuiQL2H9tBXqkrm+MxWLH1Hs3h3U6agDRFz//gsFMwyTmuZu/zdnhpRExojZ
tiHU9FHYOW9lze5uVnJGR9ziebftqy0Zqt7/uzQTGxrYtNfcu0n6151cqbLkVwgs5SRkvUBDTdXp
NFMiHuljnh18o8PVtH0o8SZgWRh5klky6pzEUzsgVJyRCituPq3yd/bcgH4FSBwA2lEzuGHHQ5L0
k4MzD040ZCUSg3wYFgoiCIxtiSCnm0oqLxI+lg0DuHBoVTcBxIT6qyGn84sHvEv90h5yuDk3NLUP
tr2KUs9OHI1v05pGfASBoTDGokp7GD+S7LfK80ODdaLLjaRaih27B3Dz3XSVxsSAUGMmkIjJJ+O7
lDrPfco4wZFXvY/t1mekMoxPwDw8I3JF0bF+0l86QGIh1l1BqxkiJFKi2SxYelIJvaK+lh5cQbj7
g4d2+rTnnYQK5kV8LTAMT6d56aWH8/iP0EEiUgNnulpmy93asjQsncBFcPI2uj4vDVlu/lUQnHNt
VUk+LM/ea1am5BY0ZpUVmpkj0CcA7DdP2/ZmCmPQ5PmO2tboL2C0EbE47jw/BZgNFtwAFx7Lof2Z
ENRRxIi7xNE/Xw3e5kDtPwO/VAn7D07kty7Pm1aIq2em+6ayNh+S7x4SLA0y4AWgzCy5Ni27HcRM
QpMPtpywfx0/MgWqEhM4mqs0zgeQCQqJBA8N4cJgIbbLF1k+L0NWmpHpxGS5y3aqrNhboohf+GcI
W1jX94w8aV4o+xYKhr/dn6O053Qmp6uujPWY8V4yUymJpp50gmN0WKEQiy7++SQoBNt6DBHbRQmP
hEcjV2d+3ixmOQU9ubRxcwthwvjlwLkdRtTNCPTlfJau0ja2FEG4bWOjmYbEV7oc1e0JTbwvpXeC
OGXPqSLNOagryZ+6sLxF+8C+6uYqfnqPq+uQTmGVphFrsv9QfXBU6/Cun32dNRsilcTqwK5GIjN5
EVQxXUcAJQ5JEFilMR8dbFk7JrO4D+LTXDaUxoNlYB1UeZNrzqoP+K6C9EF8l+l007v8A0WiXYUL
9MVtU/zGYV2/r4mN/uEtnEcw3zO3+Ety8OPPRXE/Ul24ZoUCMcqfv722WB20JL+GTO/dpar87XRd
EUEzcW1fz6GeJX2y/ahsr6SJ2DcexhGsuLxfzAGbPwhyNe0s7AgOqVHk9I3AR4XkQrlcosMpfwMC
VoKT5l9UoyxF5aVqYC1ryeNLy9RUS+LMXS+EAT36PY1jfiNb+P5RMKE3NYA8iokx7pcSER16sRlX
it4wR3Pgk/crubMcrCORn0735uiMGwNDRgj/IXqtor4qfMLkyWAWltCZ4oEO6BbPVNNz7LeyZ7ZD
WqPHKpqoqcLccw1yGzVxjspDaLaX+SFaxxANuxG1TQYzwMiqXXclzyZ+E3nyE6/bb3uZ+egw5Hk6
ojhi0syKpBcQiak/a5+JEj+ret+BCbH3YjTOp/SBii0HP1LrRGGhiCyqXVZ1HkRQZhoyORQAoIo0
EX/ZLhqrJ9ecJpTIE5QjaSGISIUfjCVUv/vtrQYlckBsvKPOqm22/pIRvLaqO2odTd6QOPoG0Cxr
1ylVSGSj16fSYcTp9w0hQmcdTcgKD6mgIyXedIvCTCbRQywzAAqdUc0vSFEoTGUms40Zqpn7IOBb
VPcPsOSKE/Lxrc6Kn+XA64kjbw4L3+qHBpptjxBH44RfUTawlqKrK+5p4rDOYQ2jy9H3qIRW5iAN
LzrGlzVs0nEvWnDtHyvZgOFaKOLdvRpu1nGrqT7a0+NezVE+gvIyrNqHwCNRBHovMdADH6sD2VDP
NJZdkayRYg1EvDxoupSewF9rd3gel0ntgPbm0EpMSbS7omtdBhKONihNeQtUHHwURvOTqayW6lsV
UwbdvnNTt8Wu3/NPIY5uNjYQjORl0ZdIWx16dttKHDUVRoMO3nIfRp6eP1RkwxJyHGuAlJQ+6cXM
ox9fxr+9CePnr5PtVoUED0ZMcIRPqbNS8LHxiBxSv5M/azFFfoPPhDaXVz7zNTSAhjoz6LSwuriN
FCclcejc7SMTSoMFawQ6Gk4pAq8xhL9PvQApMnZtiJJnbTZzefqu3cEKazlcFtiFyKHU3n2gFGwm
pu7eOmoUeBmOUlFLiwub1oOOVfUsl/VbL8YcLbXOvIRpyK6zyMSif2pTWWpOEmm5i0eBWfRmLFQ0
6NYrsmWb4ElGEdHhSF6Q63Y1HhgZGxmcVKtiCmPmz4YF/mAXSUdb1uxHEmjglUf3qIrXK5h5eM+f
r82ojb7Q7LqpqUSC3TmL+UrIsRLALXbCoOXsolXYNPa637vVWJXnXUpsXW0h1dy2YdZw1Zao9naH
sg/gkzonXFUIrxbafkIdzZUleTS1Vq9KRax+uQxhafzvJvlrWSHdAjfKzsxgBCnD7Gr+WG1a/fW8
jm+8kD5tovAOHSjuoPvW7jWDFxpK4djPJW0Ex7XbzA3lyIIqDDFv+6hfcx8HgzNcK8SGdYMIeALi
XRIiP4MDLKhy8x/B7+mf/7+w4E0w1XRjx8yrR9AvGDxyYRM8Es/fi21f/QQI3EQRFP8VBbfEJD7T
quHdYhO2c+SfkOZeYF7P8qzcdKrdSLn4RMjXO95Uzyj5ImVMfCwxmVFVfgjMiepdBG9KZ9vsYH2q
b/UYPbcIbfdDm5XOMHgVfVN7QAEj02TOzo04ZGBnifWA4mTMiMNB/n3oydj9vXtLs0KbA82kI1/T
/RhO9EWWdiM33voO8A5NqSpL4t3tj2FfezV43naXobdce66OiZ66q7JE2THpyIIZBNfnZPoDUtZ3
oIWFdI7WzIURRuMxfZNIQUtcIPj78PilQ6CEquthZ7WZ390BFEM/+zT+ZqCBZVZiWtgcvlhBCdhD
JJc2gz4P/cdskTTBMECnIZo/jMjxtr1v0sAt9IVAMPM+gV/Lpw/heQLPYDqWqvFPVzL8PKdrhhEi
582wmpCCQzW53DRrORhPX+P0QMAaXp/mwtrzn1lt0Js6DXRMXMScZ26K8ExpOzq3slbnSJmoM1xh
5WGZRL8OtzHlwpjkkO1GKcPHohSRBQLI7WtRF8xcSZss0ndGMNGPQdlwHnBtXlFztxIlvfjwAdQN
Rt8qcNQc1FvkrArRcFkrZxOK4Mk4oL90dN6tvf1IVRJmxWmdQIcJ/iAqEcmpa/WEEUCW0GTfO97V
O9agCRAKRfV/Z9mMOxI/ts0kGMwNISXbpaNk6eFg6P7gq48SN1FhlaGj7Lnkxic3L7JT8mDT7Ro2
4LEnZLCXLDsnsrQTjhxsrTsI6T2qnrWSIgcMe/noyaXBtULvnPaOE9PK0WZF07DyMgoYG6vJZ14x
4N5awItGuH94vDmNx96iQnFYDXskxqrmviF+5zdilvGZUpNOa+p4H6a8BtJJBddguwVvSq1hqqef
Yai3kULYu7q5ZGOvFM+i9c6/IutSVKYa1yGsS0nFI4/G0tmORUoFInWaXzhZPTphHDeDReOiskqW
ClipkILGdo0BKmIuGBj/SVjcS6yS2yZzo5VFBGxH2AZwphCavQYELDeV+pNpeBHwOf0yshMGJHcd
+TMD6p16mszwq1TfWKr1ROF2IUW5HDqV982kpQJfN0XppGmVCN6pHGo4iwVv6Fuin/DOPDt67KQB
pWKKNONbEoXwD7g50E1UwhfS5BVGS/jWKGHJSN77HW9KCKqoyskkcoadH2uybulnQFYRT5ZGG/g+
j4UhlfMzz029wAUWe7lGUOYfeoYd4RDz44uaBm87WJ/y0BJ5OkeJ+zzFyoXT8/UXhcnYScGIMPf4
FLkLtXwtk6uX9oObEKjdaCdPqrk4/W7wruvAc1owbes4P/h3X0/3APBD6G+ZvntSgAnZFb/oSyKY
SUUUPdmKXowzsgiW0GdBTykWs7JRQmNyzm6kt9/2NI436y3oieR16azyAA58eToz5pyFhgXc0wDs
UlB1YByLKiEsic+t4n7GhkHfhrBSXp5qrj5GijjfHy17qwZWJEJGHI26OQ3hBaAukHdW+i5XeVgG
9GVm/UdsGGsWKSqXUl6+lGg4mbs9PsiPSOMYQ13rRltjpZc+tKf6xp1ThwBYqEDxTaAVhGY020Mz
Y+zgPetxx+o8GfXR7DZLrgjbfniK292FWA9SOrxJHjFmentzXxcn/xbdo7ZgXCCvb9BWG2dJxfjI
c7CEbkMt8NHETxm8GPkPIrAVI6FuqWKSR91Pglt4Q80q9Vos/vIB0L+w3hGhq9z7GOy8AoNcpk9u
weMbHzLtrpfmpO4FyvZSEK1ZfBZOfYKCSzVKfd8jEdDz6KWV78w8ncLtNOhLuBEzZhYzZkGomUjW
eeUbos90e40MjbkdVYt7egG/tRF+ng1wwxF8+IaGWx7CLRZ8bUyZlao++b9eFQioJylgyUAWecMv
50k6HCespdPESIS7AItGKoidtujcYOnYXSlzHJA/8gJaIuEwX2LLX5J2HuMFUM84RvUGTXEmNg28
TM+8FMjXrRXz5XfJh0mUIyHCOQ0FTnALumuxdGnU7Ov+a6YtRExlNPKpVSul2ZsEuD4UBhdBX4Dr
E/1NGmbTD1QVtzDOFoRExXLcoVAhgHiTUNa+LAd4P8TuQS+5MGeTPbl5Hr5k2yQUVblX//e+h2dv
XzwrnYxetqvtU0EYmqInpVeStgbYED1e+OXS45bf+uyllKCc8ap2GK3pSFtz+pki3pEIXj4MHIBM
q+YlCIKYDoKWE9SUQyJkfTtCygsBnOXiDbwkK2ZjRoHE6uFO4Vu6k7i8olVa7/PtuHaGelOg09lK
Eniy2bkgJ70XpUXSdhSf9ZrDrGDVJ7K9giJgOs/7QMF8joMncxpzEeXmI8KdztphV587Vb5jGXlw
KZON+FVseXburxJ3N+4FAtOjw7AVUjlP831qm5+PJ61C5M0rjzimVAXIn7jiFaoaSltDd/ZhNRqG
RXa7LSFQ/dunrQcp6A06+Xmj4IfAuGqBSPOa4gUuIsdq/8PtIDZ9dXSnqNTVz4KnHHPNU2WVVt1Z
14L4ob2c95MaKh1tT0L7hwhsYklheFsG4vEyvBvdaXmIvalixfkRqfo2wnAMlkyw7OgtwPl86RSW
+wTFglOWsuuIrUdeWgwm+bgHDuboGk1pRI/7+AqCA2LdYeWw5EwVnb8E39d8fYQ0cpH3FYLUPvcJ
nA/cHWjyjNzH5mydSRmhE/Zu7+mXjiQl5gzxNSKJaE+RPOYAvDAg74a2sMyhg4Eq1HfOVU/MMxIQ
0pIO9UoyYgy1JSP4PgiHqBXpnq56hvIlpPBFCLM62wTsBhlccN/0LuOgKI3u5Wh6wFo+y69UuMPT
DnEwD/ihxdzNMMQhVPZ5MHOy2GJvUGFZY0NgM3RDr02/p00jH3QD+6QOTinEEvAXGtajyBENR2ih
UTv+gXFDn13XIT5CthR2iXGDdv5hFXp4z98RO0zg+iDYnjlVJMqMe4KXJu6QWxaWJdvI3UUASftk
VvQ93Kh97D+S2WHmlPHWNNVE1VAi40AgZyVnaavurHUaX9lp+Y9MTr9fFB86ZbPqkrGd1h3k0lv1
AyXR7+mykjkqq4IarcvewQlK6sbb75SEDEJlmFu6PHaraXygVpNYU/lx/8/FtSYOlnlCklWXzo2o
1z77TXnZr+t90Ur4nRtdmuX7mm6z4i0cbXIqC5U3ue+ApyBhweZsfl9x9l8N5RDOw3241oilEW9O
QdrfWge6PwV6/er20YnehFWtEapAb+CwT/w1pJWBEc4A6Hza6yJ8M3OPRecR4mmRF2GkkbymVc8P
7RKcotRoqIUex/+0f7LFGlu1sCEcVgvH6OfvTR3+ZGeHRiOrdnkniGAcO6GSsCZElWq83dR54lGs
D/qYDPrQxydgxwqEO848mduYB3Bl/V0s9GQeJT8WBU7iqh1tGCJ7pxTx/blvjRFPkObCbAlUXVLw
8J+F61z6VCiTRKpFplh+b2eO4z4zhzC8GA9pmasHRjusOMlcn2B1YE6Jhs4uIoQor4Eu0hnDoRGs
VmKWLHzFbYrMx8/UCCF1P1v/YGjUFd+h2CYoROy3wbu22K6JS1NkM8HEh0p0gYbwM5UJMBMwqGU7
7t2jcoM63Tp8DZczoMgA79fDdWLZjTJN2heALxd60WaBaOuVdzhEFpdtC+cfS9BU/OA6didm4OIh
iI1IeJzRP+/8nl/7z9PD8+C+leJ8QlpSmX+sc3EHQkmoXP/I59/vfU6QH6zhNuprYejoIg0zMGT3
5Cq/vQQcZ9EJaNgUx095NjF0/XIfUpcH6QMLerEf7rep5hktb95NiQ7sYT3YHRr+Oi8IKSM6odMN
oSEP+4kTn85WOpWpDlclR7jXJ+SW82l37NEfN0Se/S2Agpsw39eojoJzR4AJyHpJWwHzzRudoWH+
xmbrzpX0IMUEPPvBW1cRrpUftCzw4D9FwYUktQJkKKkuL4CHJRMFt24znA1Zy3yDs5RpmlXz+vwF
C7jT3+eMe0ymUXENgZpdTPjxcmNvJ7vlFMB3o0xtqvQT90NdqgOoQjudYgKc6v6YJ3sHVxKn1BIL
dTsx0NYZwpwPyhh6nMrL1xraL0tXayMb+W0S2IvShl6Bj10eFBKvFr0gcUY2W8B3sxZR4J5mSEf2
dA3SmNGh1sesmOLt4FfNLdCt3desp3nJr5B26m1npbKTqt5oJPQCsdAZMmjtvDgMNQwOoCvlFZrO
gLEL82B7A6+PtxY+/D/YqkJET6X6wYuvD3PZ5Pvhj22SioKIGwn5bGIQbTqMJCpy1cqoT5nZw1hx
d19f0M8i90SKizdKMzQD5wru+mTmo/NLMhIkEu83FxXTkR+rhnesqNbyDn5Tr1T9goHYdbrpyQDR
4G8WDeZCukEAk1UFR5kyLNY/MlQqCopvfHcqs42VCG8+zdFDpeYWW7ART+bOLVb9/c9UBuKYrAXx
nLfPz5johrx4aUCi4nvSts+e6jNRBZjOuNh3RW2Sv2SArDi6CQnIl2goaV5EyDSrKKDKmqoikPJR
twUC8lpI8iSzHAdrP+AD/pOhriPh/tubeEu0T1I9Qg4gPldXds7LeYPXIw0FcTBZcYbfhNs4CPE8
oQNG3QrWiROOPgerAyRUnnNZanwpWo3uXWfPOvUS4AOXDsgEoghQ+OOEmiij8wQBa0TOHwKd9IPK
TMoRFDtlBH0n9JFBorqY8STA3CdDEEUDPknoIyscgt8IKqX0sySEem2OGBC8/qSiGF6CmJ59vtIn
impoJ7Yhxz1yrDtwIsLUriHvcvFjqbsi21Tin7P9psXEtYT5EwU5xN/CYHa7wwPrSjdrDQK6aRje
8YfTupnjWBys6K8FJnWjQRyZ3qXPFB7luLSRku9byp8snSS9k1cBrp1V/IzX/kqDk0FFGZ/TMpcr
V0ArKUv+AFPexIzSeUc2UFslVNDBcaJJWvj1I445M4bi9JBaU2IrHbWObzxZJCc9RCJ2WUZqup+g
ye/naEpGQE6NkvxZDUdAc2+V0mWVD6PMom/+Ln2JkeXC+YmlCjjg9vQjzy2msgGULQzR57cToafx
3TAPdDoBoLXf2oc/uSM+Bwp3qtp6hBkTIT7GLWGZacn1TbsfxFeKObET1vkCMSzrOrhFIosGj6eW
h0FK6mXUqqsv/B2TEpDVR7KBP8h0CwaOt/bOOjvlCYjLrEnx0v55WjH46xyZR8eNarMwbKU9+73u
/5wSK+o6+dSx1S07yFa0TILj+X8ewoIRfk3aHdvHEGNF3AiqfG4C+0V2cb6p+XaL47Zhh0X114bL
xQKF5vaElvad1TlHn5uLSFJ2v4DLy6z70O6QGUlMa8Ya97KJBuo5a7CprTs0rani4OhR7OoCBwPY
OHwM4TxBPb/nbwdshYJUwxn2U/jck7W8Hm9mXN2c9FoLKARcE0ms8J0Nmvt8eZCIkoa7nMuPzYnl
AnrgVWNbtCKa2wC/gWZiOW4FlI2onHk/zPVORttgPVNaVy8/Ivz8/Kr7zlyyn23TGCAZnn7sW7Df
uhC5hURub9ahwPWaXOliTr66nXhOrK406a/ZAJUzuAOfuzKbsmpun2jYMGkL33O4IjqJVugsZkSI
tqSZxsyET2ZLjnf3Po0WDDvyIFpp2Rj1QOP/8YSOwcIXw94Gb0MyzlwTnf+RjduWEzfALt462SCD
lAwnDWS4/Te02WqtEhsI9ZIX2rL0unp90utzqV4952cHHCet5w9fYcCXsp9AhipcTsaUAKiiAu0X
pCGstflfgmD5OGSQ5r3WvFeYcpAjqZZOykhl3mcrIEqKW94CZIoX9cTZr8usJXtujgO1pZ9HGd0O
AQZnzBEwytpjo1IQpxcRfJC6R9DkMu8ITvJkPdH2kkkHB/BQVt8XplvqHFGWAWvUGmyv/3Ej6eTo
aY/VY6PogcJAl9rInW/aacx9KjG78aQtczHr0Qhojjn1VsmGWowllikfGr3MsGvlbh/8PGiXueTh
3dj2XJRYDAGjlvwwtGHLr3G52SWa1DxOkeptMC92WCoBGtnIV68ICMGx/W96sMfRf9e1fdiAzuv3
zmDGANIpVsnAlmDNGFQZ5D5zQ/Pe+NmynfAHCZtVLnLOVPjSD49pXU01WGziMKnxY5aAoC+DqHRZ
RKyj2z4bb25o/KAPhMibB2N42bVolIHc1AC5giWX1MSyUgNxgs5WT++NshIZLeFzPJiiiY54qaVj
LN15k/EUJnnO2vDc5pfCinoUAFg1wiSx/q3QGPGbYQK9r653qjdgd8N/I9o7nPNWTan48BB4D+c4
LbPUIbc5qSHjfPGXA3G/8PEB5jteOBBgcCqX7rq0P7Fzbc44WLHc9roRlkWPVaEmefrMgIwrqrZi
CtDyHmwmW6V4gvmDXk5FngWI0wtSd8BcaZTr9aedJ/wxvTF62VpZZd3kuBvU3wutsY1UAXW2ceoI
6l4wSEloEOIoGvgnX6XzpYrhblladJGT4Gv8tEVbyZ6yeHvMF1MIM5RshKQETjv1TIibG+a6OzOG
AgUS03dKhqlZXGeeOqBA0jOUF7JdDt87EKrOsptHMhhazP71W1pkiq5mjmDwqMlJdQ2ReXys7jzM
/K5OBoMj5QYSq/mlc8TkTR2fYmEvXikBmW6FOEUklgu3RTxdY/xGKv8maKTkRXsZcqRKY4Y6KPUs
gG0qlpm/DQkI2cwWaDcIv9MjC4AmIDity5xmi9+G1fB13eY36gdBC1UBIdhI4m4T6LcajbmOlyYA
pkM5LMLPqqa1zIsfDxuVYy+8tOU09ZdYNPrGg0Iqk+Z/O/6UmbfXW3GL9T1bK1cbSQEPxcMxdTs+
ffwTta5wTVNmnMxe+3ni6FASLBal6UMAUK4mPYaa/9clu+9Ff+Dkf6jnm3WyxbTWcyhhkIp8OIuA
N7dPOEsS7k/QiTFVnz04tSHkRMLP399JlBI/pkiCVc4FtvTLViGyr99M5Vs6ygh4foN0sQAl8cii
oNrD2wn/lMnWfNvNofI7+BiMnZ6UpZ/9ItcvAFwYKkDST5kqbmrWWK/V+UxcdKSviJpAUw5BW7wA
rPb0M18wbkDDSMPdNqR4ueUZ35h0v572DfpUc52d5cRZDje/ZxGAe5u+KhEbyrjEwr3R20NtGu0+
4VtLBLqNsnuLiZmqHQ/BkmzFWYcnnvy4vobssVv4dah729bM8fq8JrwZwUZUWFKk4anWqekyTISm
9WOdgnuXcR0gUfSVb+cbtoiAj37NVZOZLgUTvLVvdLrKJpsS1Mom0RankoX12vYt0BHrvse0G2w3
6xCNqpMvg1had3hc7wdTWolVVctONX2tE2DPQRPSqBPknCAYpUE1RNke1osj+bMLDf5XBb0CtwKp
y74qf/1z5x+GfKlOJzjAcOxMv+QQcFVWYg15e1QmjMLcl/rxx2Vnfojb7Yh9dPlERFglnySQ5vi7
It604S/kJ+9Vvy0kdv7EF9SZunTnIAulWfwKCLAcrqiW4NtypE/AYxNNo05r4PCMlLXbLK1aRyXw
uXCGrRg/EkkBQDWy37YUGT0cL2oNvFR2efElbrY1VREn1uHq+H8lAsvfO/Xv0cekVLwrFSCvo3Ui
fcbeNX4/2DltcIwCCJRlxzEDXY75CC31hxutqGD4a22VH2qX8hj1jhPUQkSaN1Bw3MtsFPvPovzM
AWtG7gOcslzGxdI+xcDau8Dxp1rZQmAtAg1br8k7EJBNZVk8HlcVnM22S+mUoJNAm8tvLlyPv77J
qvRmLYIZXlzoOIwN3em1MshMcjT4yzU4lKOG86y8/kpHc8XsXgPJZJ+uw0DqJciXVKyoR+vUSmTQ
A2Q+e0GwFGpozD9om89G8I2OzH+i6sttbNV1LAMpsX2pdjWXXecrYT541+O1mYEi4CznSz3UL+of
H5X3qyKCMHWYFshp7EesOssZC1Y4svqvlL+83gKQZcQKwl8fj4xw633A5ujKRoZcuggMlJwtKxl5
LZ3S4V59TlM95QO9QegTPdB/A2hAMZ1dqVloKdlu+0lyNMsgATbfRTApn+OxBer5Gtf5pGyDd0bI
YRPA0FUv6vPu8scrCY2Ngz4Zy8oFpRmEFjquvvp8H4aIea96cquyINNblDG/xS2h0kGmtPwN0HNK
+qn0IX6jrslCpgNoRVABXpIbcI9WnmltYflTXEG8OiYOwjraV5XmkawK042zvqit5NAFu7wDynPw
JvQ8XKYV1qEnf+qgSFbrIldege4H92Zjb8xI00UBwFdchWyIsrOARQvOEiFlYz7rU1EF1kAbYP3I
5GvH3n2LbHIovXAwagg6USet9AhMQAd1hZLSRd95zrSL3fSFji3lxQoCiYFPSd1DCHC91+cV3dHU
m+qNxlcM45fE37RhzRlv0uZrlI+IPuOchHqHP42ro48f0H/ubbVQYmswO29mTs1g3P6HGtMUefUt
Hhrs+mrL9vZrn+tssGvqr44b6vyasc7Y0wQjl4hFudIiNgmx6oiNbxOfGf0dT+w+0s0jYGODBdWa
e/XLDo8ypBacbzZEiC8KI7h/0zHrlBFb2GkxdxHVE9SoKMB/i7y0+VtbFNW62PyKkn7LVjfa081a
7l/sTBY1q2JM5QHvYoDjJxI+JeCb6s7LVzivnno2eqF9ByePAsRyWYYdrMBxmUPlC9nzyZNVIvJR
q/+cKt0Eq5sO8V8bvpMDjycPEamgWQWG4dz9Aa3/AYnhALwC48P2bufTteu3P3c7VmkMEAKEmbte
PbrmdQbknRhlocQjjcryKS87g3BFk6jcZVwM09C3SZw1BZR/CYwc37FyU5j3bGm2EhAkHbJ4SDUj
DlFuy8ZxC77kJ3M2tyJPrPaoXIXlnjSLLnynpiK5d651FuGa6HOpZJtowJe9mAz3LhFKIXtb7n35
SvCkdhnjQGmRjbjRPP8B8mgVxor77gMlugKsTjhhpscnvWrQibmE9BEMZk7jQ8rmZHpFL/NsWcFg
b/P9SQRXDnAeEHuZ3CV5kvAr/0qvb08PSickd9qknv9BK4Kwnxt/lIk0Rul3XK4mNqp1rwLhRbMG
ou2R2vWBaWryJmpm0KNucELjWI7w7UADydZQbk60DZxLF8ojiqZHyAjCpHUekl7tw6rj2GYHp8Si
BF1sw4ElA36/pw4fklb9MM9u5FtV7dk9gzuCRNlclXTvgCJA3wEdC896gzl5UFMTuk2vPUPTnQgM
0e8BaXtWaYuNRfCnylfjSUSDttFqnSTbUdbO3+aJEyjku8B2yY8Gcrayc5YIVRevu+iaZUN7KvuK
fjwNPaO+EgDjEBN0I1GaqEoDjc+PRsLJoZ4NZ+llZSHWCcO0jTGVQlMOYj+piUCt9TkQGwKDPgCo
Cr6gC1sKdwyanRGcqU/viXtsFIrHwBpFM6PbjS8NIC7BVt9HMwroORqtfWf93zvc/bDD2KmAAYy2
NwOD5CURQKd3LNAk/2rew8sLgBsp5U4GTnY3PNIxp3mtB3e+zy8g+g+SAeQVutE2c0/t9bQezeka
/ppM7+g5zPi8YQtCdYkAu6gKNOEwE2CnyQQ3+8CH4e/leXGUBaQ/dnzuE0hTN8FkaQA/5gvVTdZf
JgWHQBdYo91CaTlSy7A8dCBXeq4iFPrkAmq+njVmIN3nr71/Db6Jiue/TUi4KtUyAsQIdoBi+TEh
S/ljqTgEtdr72kT5ADwvTKHDHyqGfHuIXGl9gfJ7JyAdx0yk0++er13sUMU6RrnKFbhcnmNEfR//
48vBaw0FC8u8KjX8HISke8kXyfTl96Ni9oRyvPtrqTmAuD2jSfK+EZ2lBj3dzLGsrCte6U/TvLws
sN2wLUZ/Ajj4xHJa5/Z/Hx+jYGKBAPtrHsmseuUdKTSGB7a/jk0gp3llipi7/RR4cRl1Y+XSUiAd
ZvSOJB/TvVPKGcYEkQgRJpFEf9v8RlFe/ql0YEB98FRenvaxfvEJCl/uwGoeh9LpqjmKYnDmRUSR
2wAstjzPXH4c07UQYF4QnW9jHWkayNQw5r3O4zdpXZNTg8olcVosoWecX+Ne+R+xwS8nE0mknmgn
bxJR2WsvavRFCYgqPgWroC1Lw4yBjN0+RTl0yYBIZskR3b6XIdDiSgNVBcsli5rdkaEDtDl4C4s4
dCF6/SIyqpKt0h2iZzKy/sJhISEEotL1+QQRkFI9v4l9e6SACHDScBeE/LDsbcgkLCFO0uIlTtKK
X8m9W3710+LIE8QEvaw1gH4Jvak9roWnlaggCiTvQd+PzQhuvv8dDEJp86W5T2NrsWvDwH6ziY9Q
XICNAXadEV2Oz62/ZNWqF1iBRCAz8XmdIyk7Y9p2KJBDHXkSkUX2vgfYeQb4Zsm8IcN6VlmvDCby
h7RysOg5aaNouLy/gg2hLfAwsyg8Tp2LQMTbsuFjbnunIdD8CUnhiiWg06VdQWRy3jNiJUdvqXZ8
H7xmhD8lEfThdycwnou7OhDyJzw6vU5qm0z/IpE49akujVo2zETFSnNy7By3SdoQcbRZHPK0bP+y
WK4wJMLEUL/ehVDMArBT+5yawVYLGeaSwE9Yr3vVt8GBIrEMWcXTOrk7TkSOuovyXqH5Co2VqEyX
va864v5KY9eujZR7VsW2wEI1+7F3pIqfC1rs8PfcOoYX/QjhYqGfvgz6LbqXdJ3Eit9IDZ4RHX2j
lLdlVdooKJbmsVXvKGefEYANAk0zxyRopJ8Z24BhNo8znfBRyFKkV8yRiB16E4O148rK/PiA7hW2
jN+vl7yad3r64pXvru6H2lwOf+4HYgD3BG+T73V1hfLgVlGuhLJevUaQ67Q0O6Al4DS02XcHu49N
6/2YvrpfkmZO74sSYWqD9uwvPMabMoGUXeL6yZPtB4A6h2XWU8r+qrsXFW4ImhPO4X7LzD+O7W3p
rQgwvggaVyUgZv5SPc0EC7H1LK8JqZPAV4uHuK4Jac0RQf66USwLb9wXor4d3A8ybmHMvWwSfd+V
eK5Z/2CeYQPcJ1ZeqmspYNwPEXh42Cd9HTijnlF77WsJDto/H2+ZM0XUqlJVvSPMJ2OSQwwugH+q
cVHEBuI0rpj5TxDZe2uiNur+Hi95YfhNN3XDeQNXUpH5SB85P5K2/AOhYuc9AyNcYxZ2gVoRR34b
btoyowBgiQgKMwhBGRfXJhBKscWVC5Qw368Bds6eUoZzx6rMdfz/0m9GxmRQlFBhDNXpUqlmN/WA
ZSyjRl8QT6e/uasjjv/unHYmX1JmqoR4ECqGEl5gHyjbwWFMfstXnDkBj6c5rnAgDzyRC387UVpM
S6gbwrAAF4yanlR0UwiD59Qk57pswhPFTHzz3KPFN4FOEY0DszQOYbtIEWHmpBo1rfPJLh1LJeGD
XhZxYCMwUHXny6GRYCEr74qO/GNgTlkHkx5UCSIv7sXljM/8MgjSI1f0AZ13W6jH45svSKwHgKIk
52izmzeiH4zOmjwS60auTokYOCz/j2xdHD8wlGZha63FcN/qdXUAmUnqCj72CpE9yWsXTK3MgiII
n9Yzh7E5uv1F/xRpsA2XXGdgyQmER0hU1fUcy0+T/XTcO56QCgxI2Dj8EEd3vND7rK2VkL5Tbfqf
/KKC5UGZJbx/jkf/1JarD6xWZFA+g9V7VPIgajAMjLeeWIUYQqnVyZpQ6ZXoM2B2CwfzWWihKEbr
/WlT95YFGPacysbUyN6QO8aJcPQ1vDZ5VsCcUTQZ/1cDqy9flMm5H5a/gezbgBNyivGpaDHzmBEG
ZnUOtc9WgTXX2omqUxWdcUdaaC4VkISUXfB8VL+ofitQ8/0fm1Hxq+JRzFpez5XuwE3lJ/fkeyqT
tpuB4vl7ElByaRUU7SbNUq5v9log+BqLr72s/tw9LvkTtE7g6LhsuZ/ELwvKpRzUSChkgz8fgesv
tZ8GEjc/5itfPzVQc8wMQXLl4chkvsptoEgpsI/R+vhy53oawdZqKI1wUCCZI3t5QNOWsJDlFqIh
AqmHxK61nEXpjuKrYX9dJgbwe4UL53KAqXhOQBImQlGVY7ZhY+t9yr+/JWZ2KHvWZo3ScVapFviX
3oZl9kQyD5v++YkS00SZ/hQxwVewn/dmfUdjCPsCF8EHTnEqnJwMPAFeD397V3J6VfjJks3mKYDe
5kzNiflxuADGapYEkV9Z4ZTcQFw3pusTZO0NIHBvPy3r5hXBfb+gRYytKxLoSkEzFQ9lWBs+/nzl
knOGjG3Hp8GKNO9ghryFMbyH1KNIxiSSb+8XIyZ8ngRcj51/7N7aSRgIYB409x0Ya7Iv+BEGTw3q
QX3QcvmKvpHasEFwvpxrhuX2yl8LBMBh6Mz2LnLEaFW9W422qcWev+BzEVn8Mgw0jAyDbkEl2+D8
wBNuww47k3iI5IqZiKOXGKvOYz2Br6aqGojMYKn7qQ3jYd9b1JxFGNgXRWK1UZtyTk9UjDxD2QBU
BsFRJdjPhHqAahDxdrTVjLninMU9BShnjs1unSNGMuKLvt6RxP+FrFfwPaMdJLSj5P9tUX2uonar
FpueZSCCjnQpZtDxTlvFTpDX7OOf+RclRlOaXuS96ZyzUFAebk3/mn+4ffIWBkLzWubO5knSazk6
CA+OIZA5+UAKKjO/yhZq6Q7kCn3Jk+FishAjRA/L32xa8R+GCZMl8zAuaUF1JR4CP5f5MCCmm1qG
3Dk0OP5lc+DfiwRseeVzSeWLecyBGo8Y9FBIcljGg/YOumIwlkxEPBnmrlExBdozu28MiJ4ZCitx
GNiMCOGDuA3AaRc0oBdwdWss/u5O2Ez587Lpq1YXIdnR+UkR73zTuEJiETDKAgp8V7VI8F3r41Rk
UER7qEuOgaWEs5fo83ryI+YBbDdSIh0sDgO/GmaoWJkgmHY6wF25s9qXd4qNVni+WEgQxV9hWqRd
o1wjpv6NHh8rtuOn7Fq8UTXvKjQcHupJ+YN6juyMloyRGrzKGzvDusa7gGCX+K3DQv9gi6cUw0In
KHuATun7xNqn05/iCrKNhpKsPsNjqJlHdFE8PkNMSCn1qHG4E7qzBo9AKQuD6/HHMH+c/ma0fpqs
R3vk2G0/CxIiCRic6Isr1HvsLT6aDrk2va0GDmfFTFrhsuAsstYq2ppqaggT/LIcHLjDEhcjYxLC
f96JT3ZJNHaHfbvcHoL09M2d5mfoEfEMSGrHN2t1yJXi1zOXYBCBI6QTH6UZOqC9059Ln5wgCls8
PFHet3nWSXngZm9IYmiVV7MTH4m0Qgne/ES3NHXcSSbHKqHE/n/1mZh9L01/CMkTgwMdKzuU/oCA
eJUsZDk8aWYiQTtHmm+Jl05k+pWvNtdNHs69Fo3U2jp9QhcTpAAOTSnS7Q60cy7XOz6Nlf6urCdU
nUlMcHeX7iaxTxhxaUP3U6HU16XO2ArsOZIWOcR+zdgqMxpQ+RCnG+/nna/Pvyz6TFWLF6OZ3laO
BMmkQtVuRkscF8CbQfBLtMJG5QWShPh9DAfSY1dKJxWoYZzDSmgDoWioMQ7NVUvvwzsNsRiwp7EL
odQxYh9HGrlIBcZjIkBmSBiTBCblPixVjThaeOM5av9gZnMTs5HcRwOxC259M+7a/amn39kot5oM
D3sJNJOLn4k2DF8apBAAsHpFseoxyQPPmk8o35PklIIt6kiDuaTKHtjw3O/6yF+DC5phrXyKibDJ
Ex8VhtRQnIA+SLbH7ZrPUbBgFY8CJMWDOHm8trF8/1vXdy2k9cz5X7cUWwdQKRA3tq9lkMCTd454
96Ghq5sgLsasEmRUjexZiYVepqwWkZ4Op/GX1HvSrzYcJ6J3HimruCBHm+ip8iP+KBDDQdLt1xsz
yl77mAblBS7W1d5LFhTvO8ppMJuC0xtun+oP/+G9D96y8ibMfb9yMU+ya+lh3ySSp3wS6TrO3YZj
zyXtilXL9EH1lT9BDs6Fws0wNlJevd0HnkttEAm9K9xs5RntspySH0LZwOH1fhtdmrTbUgGooly6
Jkf2Bk7z2b6TBRPo8ZJPD5vEli/+AWqDMuonCPwF9fwP+/tW/8LdNtkJZXu9Zn2ZpcY/9OWHx+T6
0WqoK69vZxYj6aWoVtl4i3vxpYHqZiRCm1wmCsNdJo9OOtvDpeze3bNbYCwraRfum8VeNUeC9zGK
BUKhiZ9gwfNFMnPeI5QH7dy9CpPLHmJYkjZ9sVdCMlCpPQ9TSwJPk3fxwRbV4jCSXZiedW4CWbTB
rqvh/wtfL05yrrD7KMV3nk9JvOD6azZLpLze2xcgYzcPhmgaD3ShTueacu/VrvRgswTYHgxuiz4M
aed8eu/5vCJwvhuSS0PHcL0uhHrT8PHoL4sfXRO1/HCRQl2j0aX0PW5sOtfhqdUxvzGBxI+SvfgI
Irw54iVxbj3x5aiVoN252NaO0BzVM4/xakNNMf92n36gzhQO1IUnLBHwRWvGpwLk3I1dL1RPEHx6
r+NSYXRMp9M/3/uUchhQazmESH2uADdjA6yEVYLGeia1TjjmRF+U2tBcMGHV/q17C34Z2y6IwbZl
trP/BJGjnuhkf5g+NrxeQfaMmKMWRrguV9ZWdmI7MPxNwthijSgcY9a/P1cpazYC6WBhYMysfeig
SGheWCoyTKm5AkG5MAyLgvvGOI9mz8twQW61YYnV4ZU4BrUthN9h2/Cv2T2IivQC/lhLyHmaWuEC
r1jIpEf1dQjyOYCuQIFIRnH6xp0aZRALD8B2j1OolVMxf5DIUeA4jXEk3Wu/2tNV7eq500njSMkm
ewqCX/BYAF50OjOgyBOhi8qHEj472K96b/rfTC2AZmzu0QrIW8gAU2fDYEhUa22exaDF8plqBKpN
0a12q9z3weo0ETd0mELjyuaLHDuSlcFnV0jKemCMNZYbWJE1V+6EyA4OifseOzIeoo3znTSyr/73
UzK1qmRCUNTpAbTPgXhUw6aYqB4sFRw7eYBn6OrXq2j6IKHIXbH+WXkfmGes6gs/F2AYa+ZQqLYd
sVgzvWurbyDR+Di+wjStgTEegK9PgcRY40h0ky56XFockMtsi6xCs06v78hUmHE3ZQiCHz86rp66
0/tScgwCTxizrqD5ht9mqqRhCyQ6+6KgMNqikg5wmh3QtS0lfxAQuzyajpkR7kOYAk0VGPFcAgH1
1wxIewNR3/g2Edb84IzI/ygFZw4IvNqPyythlGXVOmoaNJNiMbHdVXbAcMfPieIC/tWavlpalkJK
6O34uRVStvxR4i/SNfBx1elBuUFe8DvssLY8QTrrYND5SiWieqK2KJZhEmCpsW8fPhdA+PLPkB/g
LBfFGQ1j2AO8YoOVSexf56Rko2xxHSS3x/Qp9M2+Ei65yYbEV7cGjziZamQ/SeW66xrKKWc5iwTf
EZGYHz3OK8NmlQK+6kB49lBF1T6rOMalN3yOlr54XZIsdp/iV0gbuUtSEqg51/NHYgnp/0xYyndR
nE3kbM2dBMlmQLYBevCQZk5HU6VtVRu5PY8zOdw6Ubwxf1jLc9153zQHFFKRl2eA15EPLWGl3Kkg
3kf6AgFexKpoyU296enQwn/LSiUq3pWk64UL5J1n9DbohH0nimsSrRpvSG6/8NVTfc48jCMFViM7
KlDL4dzj+QY/Lr1JN0SeJEq6GnFyE0D9IVR/EzgCvLYYYKpIhzhL5uu5CdoDeBc1w4lEVuAezw9i
Ot1fWj2CsfdvHLha9N0Uiq0p4ZERDZfMxRALbLe+aLjyCZM23Yq/E4WzZfHOixlonMuFiIigwPGm
vHM1BLVXJt8A5dJCxyWDHFXexued4gMVn2PxVE+pLzF3V8GZ/1Cy7XoCWxKXgy/YJyUxO1Wv2E+Z
n8sLDGYdD+nXuElUxnw6di2bodOiy9DZHyZyBRb6lrUBm65y8kcoWQxzlJvqN/JK2cfn92r6eW+m
Qbp4ylRwgcNoCTtKAOqN+u2nYqnO0rMlkBil3IbIC3R5HNN9l296rnNrDzBTBC5Hl3YTxs2NmMY/
oNH0kQUP2RGo+KLMLYKmUsDDs2wei2wL+CecVxV2ihQ/QCKNLy0sbS+Bp/jI33MN1CNE76osaach
7oemWTjkc2WkDcM7igZDH3vViyQf6pwstZ3QZ0Y90DxFHuTd7DzbISyxaSmEPMf4ptgrt6hYALav
6ZwL0nx7ASFOczej38eyYIT2n/D/8uDan1CfNTLr/V1sCOtzZUG+uPl3YxyzbP6YkFFObeypcyJq
JRmmL/kGWYDkua1JwPoDpCFuhmB5jwOVorqH2j7FS0yyeai09dA7VsD5H/IM0w3oMSzQIOsS8PPh
wxNx11MQfcly0pYGT4K+CPuOiSovB6oEygOJGzXci0ts/USW5KsVvt/bNSve+djkosd2LciW9fPZ
UQFJ7CP66xMl2fe2bgqx1x6xE8UFI/l6vjkR21TCzyjJ/6LGpveFP6WTt5xEARCGGgNN5bjvhOkt
WZfnvvFzUADCGbH/yNoceHyx6tkE99kKcISpLcVn+954RDqIV0iQGbDvcEqFiLIq11KXpy5a1TyP
KglcdxjDgMTtP7LvxvVDiFvU2lSawKdRq6xcrPCnI0vaTtOpjEredy/m7C3wBevTJkSAxMKSu3Sp
MM/r3x4cXbHv5judn5vvifH1wEJMlOlV51VrC5zBt/IX7KEg85xZvNQA13J+8+PK3l7Z1ZspYJYL
cTcKLNCGrlar2hqpx04HZOwKADreBQyKBke0N+lu+V/63dOCOJzA7XAHYGfBFdQGNsnOy2OpEhUN
OGuUW2PiAEqKBFDR3uqGJbTEVv5V3+x106VsEtIeTwzVPpCS2FLbfYSi6aMzd4D9XeWnAjir8dUK
1lkSKv0ySBn9l3fbLTQNnO0V8E7KdHkmHJCugRc+WpBD5dPHqAB/7TfGL4N0nAbc34G1BPqBYmhk
MiFYb4fdwaDLZo42RRevCrZQEECDGBRUPxExxktPg4znWEo/+el5ZkAzWB7flQkovfhzAaGA0NkJ
G+W7/qa7lxz034zQOE4Vfq5xaUtopFoRrHrkf7TI6loUXr4Exw6Uyo1fGI2m4G56UG1nnaZcyEi9
JcszMNYUpM6W+bvVZrLpnZXOmpVybxRKsjPEWo7QMM4dIWgMX5WViTMe+PSMAzL22/2eiN+g1DtO
hznrAWsomXCfgw7stGB3/GhkMzVVchiYmz6Tm3comvucGWDWd/00h9k/4z+clfh1HaHpxF8gQ1H4
IyOcp22MDp4dBV67CPVJOkxOoRU36t2vbNsKsoq8zKNnitrIJX7X3agOwNkDaMVsL2xB1JmVaAmv
2QualGZGeKNyuxCIDYs4uooxV0CWyIJMgfoM/nLwIHBzybDijsp/nduQNyvs4t7yXsVc4lA9+jsu
Z1vobjE5mTR5PUwD35KVQfg603c0KHZV5h4K3H1JTJnSIQWo+H/a5qKrWZ8DXHdkLU9Wn2Fj35r+
CHD7rKEOZhK10B7h/he8HmgTPI1x8b00NuCVUKsmlx/aDR0r/uHdgjgw3tQxmZ6jbB1EPJRb/fGO
2OHBNxcQWUMnEWyK3x6fOXnnbtHPV+ZvSZFwVxmb+p2Hg2bgCpvoOaiEnQoySkGJGZBzL3Q318NT
LSjsAZizXGHoMBQ+lLKBGYFwznQafXqpWmFaYcU0DQuJjNb/qI66U1RQgiXewOJVC44jcEyRYJCV
KoFDHaqwuxVEl5mEmo2Sy+FdKz4nTRtaSDJlpKoF3Sxw1wJi1J+CGJoNdoUapPbwLHa36nug4tS3
l6wVpowPQpBIfGizHYAt2H8zsTMsjn/YVGouILDB2uxA3VdF5AoMH9uiY39aAkhm4NGM+Uce5oV2
HangSBF0zbHFxmeNgC7x4U3FvYJhdoxYv3S0XfeYuXiFTZSxto8QYeRQauc5KxfBGPn4a1KBacEL
TTi/fBHAh7c9BYy62xMT1ge/eGyYi1XKvJjWNVTa63IqFgoRadz+X3Y4vkvhE6aTk1TOZkPGA1bA
0xwdc9cH4ZUVOTFIHXu9bYM3iauSPGs4kTUgOp3LJfK/Mj2Wf2qCpyJpXcOKCVI2xUbYzFebUoED
TtqKexuL4su3Cm9PTHvg9s2QnUWRW2RU8TPCPMUEs+mpcmIqkmIByOJEzbqrpz4rsjdgrrOK8Zd+
ZjPWGyoTR3wCfyvtLv864jbuLLAMRylUd1wtIDB1kqm6vWDlBmWapc6o/ZEi0+wc6C5MOQUhMD2T
10lALzP8D4Vs/uZvrYpV69IRwz/jfJe2AfEJ6AHWBLlpcLtl29riVniC5wav48vfEsqrIRMZlapF
YIDOKkyUUPiRD98JcNMexZljyzXnImgME+ZkPk5FTd+Y6q7P/lD6Y82ReLKpn4trn+1wkmPupOgW
/Au6LLglOA7aOIPJNddsK9Fz2jwLXd2dBK4XXasJ0TdSHRc6iaY7Oc1GxKUsH3raH/91CPqXlfre
WOh+J4H+QPna5dd7gXgh/NVODy5xgDhHtCb6TLSCfP7Q/lbhs18zSYa+WI5yIu+06Upq5m0SzuOC
S60BBG7rWg3Cg6ttUW7ZAZyWWeguY8QppkRcbLUn398rJu7iixIyNEunFPP8u2pF7ymlsD6g2uVQ
YT3KuU5FS/tjrG0PYMLT9Ti5DZcljy0FanzwixCdWa0P1Eurkix7K4Xi8EF5OYGnk0YewvkTQ3Nx
CszpKeA3sSu1azxW95I3Rjs5+2wscsqI89bT99B6cIhO0YOBy0FfCft6C5DJr6ANkC5rB4QWWoyL
SEli/LGd70VYTQcNCdGqg42caLiBZVozkdEQQTXXXtz32HhTWOIlDCwr7nYrBw48Q3YyMDZamjbl
Ay8v4oQETvzTl0vo3JIjQ7B/Gevhv3xJ2C/0Unl0Kg90sLhWDzKeIpb7XxyAPjNA2G8d8RMJIUAn
Oqh6GUlrLSC4KRs3CVksRyA5nht0pSo71IBBOdicvkqVv5x6MgdHVjGwbbULZYdPTk4Fq5cBq4XD
GLohls0LIIfOYICNmetMIt9rUaeEwPRG45pr2Y+HSy+aN9BnMALTTiqSqgrbxNJXC7775aIhxYnF
mfS4RGeLCcwlr5BC6IRfzI0AWnkv+PUapZJlVK4V8egSczum/W76UBiYp474ozdjaXu7AE+K/l0x
3ZtD5574DhePSB8NO+2lFSN/3+6BHyCZ+y99uc8b5xyExpoKzg2zdF1VAHOeoqrUI2nfF7ofJM5k
lTjwHPRbp/zTx1oeUIArp0UZkf1l//QtI6vtc6AiOcEwP/LXUsGTGM6xL8H7q8XculnLOQNDBchy
X4w6r1Bv7NC17Ah37ZI10k4zhP8jIAypHAAZlvovakW+ucweBk1UYEGbJwXPf+/FWqRcIaamable
uYXwp5G2nwY17IrfVMb9YIfofl4v/+02+7MWXxHwuetWavybxlF4fZvhfqrnOBcmWVZuo01DCEhw
FE7PdXtgtLJfb2VosfrE26wd1VfQ7apM7XqCqD0EolkUIa113bpuFemXlIrYO5CLJM3NGMQycbEx
k4tXvWWl47HGr/q9U+i072CYfnZIc49ZIDvdT9Zjqoq3BxbF6cG3qfL6PWpUG1zUszgK2xUEQazY
0s4RbCKthwmi2alTaj4A3/7crZ5XE2pXNdKxmK94JWRLGPyyPwblOTE24jLdtk+zwMWEbZhekSmd
rKVcDci6FSXaloGy9ZxLMgRQouzyegelYAAz6hzfvw3JRSe1RQJ/WJFDc6N/AnAlZDxqxAIL8JNW
0mqUv9HQOIptMri1sUXDDoRN0gl3Fm1MSVadaPPVGcEI+Dn1gQ9w6wuecusPzZ59paWAF1jBhs0u
d+0GiM6JGjqHz0CPLCswSsQDfTpWTAkLJo2Voq9DK8qdoJjGXg3TwLu2Ac1TE7MBCgOqJa75l5a1
qBJn/8aD5T1z7BS36IaR4k9cpMhPPw/lHullmxyWTma2ZlGaW4Hehcxt5J5V9ytk6OFAuJOP0RDM
4cLRXj3rMb9NOa4EXzJh0FyhlTV0+GO4A8hcnQZzsW0jlGwDJFgaIvpN571jUB9KQZVcizAROGXh
nE5qaMq1l1aiT/H8M2G+V9SwOBvXjB1VZIh1QSL3XepISHKhzLGNtvxZuJhRibpwApRcT0c+oKWC
MJ2ldJSE5XTV54t9oaXO4t5VLb0VxbikX0w0X2O7jmdECxeGXLsyLjItWr58hYiSDu0mz2K+Lz4M
EUUR5hLmMci5yxq33VBNHoZIzYshBikeXTYwH/NQ14tH7PA2IlJgZZt7/zIAz9PkpxFlMWynL5xu
W4/jRvHm3F6kk5zlAemctiWaojryvnR3myJFneRJcaSUtpYE85NB3yHKAfM+M09JIpHYB/G66/mW
hW8R8gfu5LxM1dnbY+kDyWyolmPGnDG6SECUg/v+Un7cb9NYxfr/lCuCfO9T2ALyyVwJPttv1vvZ
HtuXHwAUusc+Bd4+yH7WMe+tiHZhkAv+8TKei793gH6axZH2EOEyWJ8yulyQ8FgS52vSjKJN+QdW
2dhtMKJrt+ymf+Nq1YLNBv5xkxLrng6wD2xwr5S+cCAvafGfGpZ/5FRuUaDPuP0izOKYC4OvFWJ2
d+bB5J8BnRXgbRoCipieb9kTMflRlcBve30Hx8iBelDFLxqRGcmqWEEfnbdYm/X7t7Iv3MrErlwV
Q97+JoUKzgwBRmo8cUvQ4FluJQVfH9tLO+O/fHHSUkRKagatn1iwuU7uStPfn6SHQL4NstQBxM6c
dI9jSQi4WAq9uasWH2L200iMX5TWGgGn1p9tgOW2XXWYgmtE8gn7qQz5sNu/wM5gcMQlutqUdvnw
l9fN0ZxRWN4gPeidTivlwNEr4nULbbbCysb9Ga4SVrXuRq8Zq0z1RDXmM6Bac3qd5XTaj7NTQVpj
aW5zKYgZl4J53FFAEYPKz9I2I1KTmCPMcIkRPpc+Q7vlXOCvlIezIk75h1P+pTsbNNEh3VJjkOBr
1HmMtP8+YofU31MrbKRihEUcI9BDCjBAT7zS8KLqM/8hn82L2azfPJ3m2hcG+EErf1USXWfFgcEE
tVkXfnNxIPsnZ9TTs5tDq8YK4brAheZxqFP3fPBDEyeLXEqkcI4wAu8IkSGAhz9mc1iKjS+e6/+m
2Uj4cqUp1xfnGqFKlUr9FXitbXrE6ORZtyDHL1ird510Wa+sr3XmWs7DPFer5/bjW/Qwjn/CG8Sc
1k/hUiAr1WxQOvGhSUb7WkSdFVIFjDCEkrgjLmC9kpSVuLu/H08aap39CRlUOZGgVstGhC2wIYFe
5R3r5OLnnsfkJjRmF0zbj7+Fum0Qg1foiPl2V0GE2XYrhBu03IOlGx4okbgjraU3aTuBW92yeCVH
RjBL/0nKUjarObq03MH0d7devOgdf+EyDtCgNBCkQDznwHjmJIxC2kJZYkZWu4MXYXp+uWe9/gd/
yP4sBUtAIrH6zBvIHayLI4aL44zsoIPtnXKsvEqsDjp/kSZFlmMtUSJ2gD+dYidNCX9EI61ecQFg
mT27d2OGuMC92Bkv/IqJvXEZkcbcqFRrE+Ip5V3H4IFTGeHwkAxtV0L4nL18pPnM9z5yMZD8EcNg
Jnp0NI4Wnn1sEUXzHlohYYMc15mKPJqc/9izsnFc6+jpV6wGDbWX0EitTZhc0oOk7YxPKoig/B3M
2LPrV1sIKnkE5UkDnmmcd3u0zx9wMLlYkZ+7U3kvmrvx7PWryVna+sNzI8Xc0Lzt10rlnNuFtCMQ
TCG19KSCdtqm7jNB4Z2y7t3wY9y641YdjLOm89HkUgJ9xA9gqR85O3TydoIyQuJ0PWkTzrnQPM8B
FeLmZeDQh7cpW6rEyL0qPZbRMxSuyq8z5KbMRJ/7SVWOLl3H9kYZwzONdaUtYNtgL6I105P4sy5e
GM8RF/G7LsbbwQFtGFUutI3cmt9JI50d/hxHrfOMKPd5OJajYxczu7GCIoIhpHIGJxPGMAPihGVk
iBLl/ntYeP6Acayyg+Oe9C34vUkcqYncL59Bf7oVKYdA4O2SMs4vHN1cVZPY3SGeh+aL09LjI12P
UagzaPpFSaeTwIAhrFYIzpeK8dGZlDQDjDKGh7cJStnYH2g2yq3ZEKSgqcBCPgDNGBX3VNW4R/er
zRGTuLNIDCgNr3Q9tv6incI297SeJ0wMu1UuIU0TMWkWydusMNWp1q5nwOr7iO+PBVAYL/W1d1S7
V3QXU/07GLYPS9YuPzMWMAMWdLlne+FrWvbZ+WFR0BJpnjZ3AJvDaFmIeBPabkD/04kBWT45WUdE
PvkurO+IC7VnWrxGwsVQ9NibB1w3zZWu81obLN66/Lf9mXz6fKn57ICtwdy1zJ7i6ejaw+Pp8t57
jitcuWhMObNPl56F7VZn/iXlda0s3iGZPBSZI4w/aQ67ZuSdMo1i8W4+G314wiuPHy4UuN6/mItF
psKB62uhbfgnAtixLKr3N5x3jRwFuF62m1/WFKOlOE2gM3UbQfb5BxQVHpUNtstGObp9gNEg0Vtj
zGkAGJhfgCTMLdZXaH0481s5J696zaZDOcLOvUiUgEIE16w9VdwqyJEEqF0YqnxxhVnyO7FkEvgu
4fXzrw+uS/uMBsF0/W+9cwJ7Yndx29cpv3ZEJ7nES4xOGj6VtIY29TKaMwKYUBQhshXooEBIXlV9
46aPd+0O6pcR70oxLafCcsxBLkUCWzSUORdMDlx9DrmVc++Ngne2sPlGjPZml+Td06Pa/p3IAdxT
a7rZoOIQ57okF1VQ58AU6FWBcEotdOf/i/CfmSpIXzdVyjp2iK2U00vZdwS0W3n1aGQN3+X2T7Bd
I4gqB0RC/Cmh7NpYWrpaRjMQBz+73Spq4IBNWVJTWjrZGlYiN/eXlD28jlFvK5c31yhJqvzFPMEL
fUeSYVBHxNK5tYyf/VZkx5RRTW9T6s4VLlpLOMj8UKN/CBMRh1/7JMrR0kjt0x/vqSH3qFPD47Of
Wayg7zdJmtf3ZTgr1jddsEhllqbySNoJ2gXnQl0czi9WFGCA1aWmX6FyUvoWXuOwXaGidsUfWNsz
0HPlMTfDDb0/My7awwLisNYIpeq/q5r1duW3OQ78i8a/nqP44WXj5CJms2J0KUlaT9vjva/mMhWM
60EhMT7RRJWVdG8XE4y5wWv8Kocbg5C/RFM8oRY1kL6BYd03rhKEk2IDYkG1GFNGzBMMNfEQuZ0T
Q7sMigkvEUBE3m94kSNbwXTYFZSd1yuRpxUJkA2NipueK/Aulu0PNarOviFth9EiDILkBz2B8wdH
pWhIBJr5oTRe0rECOdQwmBv7G7h223lgLLvA3WVyqWKMwZKzDirvpDC7xWkDHajDbeiHWeAkXjRv
y6XzY4xwhfvFGdd+CGGAAN1XgTs7PyXXa0PAu6im8WGROUj+ffFQRooh55OUFPzlin9v/oCIYNdf
HuKIiCSlSeTIlXaFsXM7rMT6fDuXpaprUgwyXHriyOavz8qszwSjWRwwT59i6xI6Nlhwly3cgctG
MIp+YSViA7TIvZ3reQO5G5AzroCbqrSug95A5WZV99qiCVkj1A3cF+8p9cTdYWGzrFYXFNhKs+y8
isGNmjHFJ+UBVO4SX58NiLArEq4K8Cm28xHx7cX3uoC+aWJ2tn+EmXKWpTmQgh+LSWCLvy2SUpMO
decOJRQyWngePco9HCAaPwiYWZ1V5mQfL0WFvfli8WWO9wF+N8BQvFVYQ3P0dAJ48f/yGdb06K5L
jZ3Y7cDR2QfIAoTVOoCWabz5Rb3SHffJ0htJwpK7u9wDI7BTU/l4H6uBL5RvTGsh6Yu6s5oiC7DW
XPCBx1EY/9UeFFc828XUzHGIAxI9uDYipa2cjGhLxQCtwfRSAhqemJXvCsMbm67tGh311rBYjza2
9ZMJqOb63z2jzNsavtEmMcrPxxyJnOHkAkLw1R5skDlp8iYVoBOh+9tGCR4761O+XeIrAH3KbdE1
eOX/M0lt7Gx8lbktvyABQ8qjPLD3LC1sWx/Rm37gVFi5MZUa7ztWW/PuU+S1GTfaDnageC/4Ih6F
akP6xTSikVhWUf3lCksurKd13dnWday2Q5iXo43hm44QD/B6LF9e4cw6xv2lVKv+xLkWR5PPx+7a
kfVZu1BCJU4qWLKnEvD8G/t3Bl5oLjMijoGQJqp/rlXgl46hUR+s6xRr5Us8OILzxhRD4nueCNgA
doUUFsKuQEgQESt8dc+xYLOAuGaPDQuKslCdkko/IS0NuBnllrbtVNvNo8pBtSevyscWJQWbZhqr
x+MNRrj4UsOyRIyQKsfK76BH8ojMZCiknv8K4bBeyFFPAteFaXBr2sFg0dO1CaxSGD1+YFHx8aJ5
nT4QnrbwmB6ykSXk3T/O2Qng9DQ3C1w9VB6E9dbq9A8arhji9KI2/14Fbg+XRapLzsS4d8zDVZ1w
qZexg6RcTOBRT/OWN3/0WCsokEZOpdC+LdEbYX/W1M77Gzvu+zQmQvBD8NJI5oOF9em4v63pwVeL
jipS5Id0yjgws+mZyKa2V3BCxITuohfmmP8RstT4ymCYsCva5njSh6JlDWyUawz+LhPF0MAfmG4u
Gl/77LM/YSLrfmw8kxgYCs7SwG38kfuXJCakfIy7yvJI7Rtw8QqeFvpBU5m+tztntwDP4sPUbsWS
cJWLEdU69tbJzEBs0M7TQcD/AWsLOvfN9o3y730XGFqh++ZYeWHeav+FUUr2QoSDka81ELaryUdT
LXcgHh04aE4INVnLOPOpYyCBL9e3xdvphD5Si7Xxgmu2chbamOvUp2cX863IO12xAxw8ikI53qiB
H6Dvr+jRINF1pySnM363oAfSL8JEQT1wfK6QzZfvJCx0K2CV+bHm0iIx/ppwfzAttlW7emI5ZdjY
FnJo8fHyfpn403yASZJbm0iukE9FjYPNYvRyQjYH9uAZc7/QeP+xhkY1ja3zdkYqp5ncGDA9Xsgq
DWdMXprA4nbvIwDm12PfQCVC1aqVhIFhGdjtYGCMZgOEqkLwQtVUVseHLRaKgdt2PBn/X4hT5fM0
9jmvt+mMgABrSxW6ChGy4utvwPx2FM/qBvoNN34TdM77hL+nsi5r60g+7zp/rkAgA3PD82b/dASC
3qFWQdZgaFPo4pVS1rCz+PIdn81yzcjyXl3KwgWNsdnnTsl1DD7PY6Es2Ezj1VW6+6lGoY75mqPf
G24h0z4l8maxrrNWrXZznCy/qatrN/puxC/aCi3CPTO5YeFbZcqAQEMFofnDXXXjnuNPnZeycbCC
oCGQedYrxWqF6L9ucolmc/G8aXzH0pY4QMc3sWhYpdZdcfpeqa6IMusXUeJSx+ACym7yvpx0KjlL
16YTT91Xeph5sY0ih/iaHNjDUwUxa8ppdwkLJtA0uCezvQ6Wjo/wA4g4FuW1K0sHRN/b/o+JktDA
ZyrY1LRn/0UVeDBiygAysAknupiQLZJE1HpzuLSZZZbI9IqCUkyKMRWaNw2MAxIbgXeDWd9V6Air
G6ydejdl1MNFLINW0FHwx4pkXz59ycx/Uc84B7b/m1fGGHh5zOqWEXdiYSBpQWJ3rKR/zXJBLVAu
xhVsJgw+ypMtSJOF9Lreb5+B3SqlzC53hy8pYNzrQEzcjnKdq5iOxy4yFeTrWJDHqM22SqU8OpeP
JWM3vrpNTsCnX96ER6kBRiB/OiyUu64S47GsuS+7LS+HvIl0rSHULgCmaJZW62wJJwFaX8QvRR0S
6sgLLgYldWno6KPuIy1WAa7a+pY/FMUF8nuVE0TsFbK8YpVG3v7fZP746JAg3kFa/VIlqNNHOkc0
1agEYk6PTNAqcOQFGIewlPab8GtwiaA5klOZyFXH4r/Wtc2tazmQdJbeLWvWQ5vEDw1CIPIIqrfo
ba6+peVRwxSL3UPHFgNimgeDFRti01UdfoVxM4xkrfuHxpvN5YZEeFxzmhCsfsVRjDG99Yq8oxdO
caK95Uj0c48iJTVs5Rr0Zu+ICc32gxoj5Y3wEyFdJEMZxREc6owHOkAiXyV3QB8+47aX974wr6QV
f4TJi944YHPrhi4IEnfAOdHcAc6aSZnykJX0jzaycOi723EyltQPcM4mOZO47Bpxu2Seuduaamfi
VZRIDYrKDJnrQ2Bg4YEygy1kpCmDNzYK02K8yMZsWsGtymU3cfEZ8BIDUrK37PPo4sLVa90+K1pq
lej3wbdyQCXb4dty15JWHnSlpStzIGZUheuayuJIWSsf2fE63RyK8PVbNGlaHtiRvsu1mkrN2hAK
9McxCGXy9cAPDVb99QXR96tlSJ43OXsBvo7NdrqCQUfRpg/KiCshmswEYW3XsciANUejOVAZ0fAW
pEJtA0OmOLSWbjWUX714dz1ReMKtY8sUAohKzgtfUVwzO0/imqTHb5O7N+XgzMQJDxLFWXOIOOdQ
jq4fEMKQA3816wmImD9nU+CXOv7Ryc6W09MLtArLzpQUK5450ijb1vOzJByFZZiGcUwG+q33Cawk
+LZE0jdBBhKqOTKmz6bm1zgk3dvaS6hvwbWy8lWp8mvj6DNQ7UuJHduTVEu8tSNKjNKShG3ufuaJ
cIQda9phS8/Lm55SXPVpa/zouSXDzTPxxbaVAjxzxRXkcF0d/HQln4l9g6VJrXzvUSNVORHK/9rJ
MmTtJ3Mbf+KNz9uKY5kNC07aGP2Q8EarhjMX6yHGzrX1mp/kj8S47/tWKa7sa5uBfoQPxihIOQqt
DNnDakWuHQoSKxK7gzQWzpmMSVQ5EfxQiIriv/68Z98zb4zgEi2zfs3A2YwnE7gg7+47BvMJH5HF
cCVCao/qO3CAfufrhS+x2FhDgVvT5sWtdNrQgbGNKnQ1IejqDiC0UQ69mUCl3NEJGULWl5T0g6zj
H/2Tj3L82242BVjxuoQB2uGZ1eTKI0J8MNESn71ItLKARCvOupIt7ES5/6pf/U1h/XJrDEVPIjQL
NA3mYKG4SUZVYEvQiHsvTdzUaYaHKwcMbACWPvwbQdGyiX5U0HQybuYlr1dyDZCIoUAYJzc90fW/
o6MRgulDDrpzEUuxFYBwwgZQC7g77h9ss70/8f+Y8GixWV7PkjlBYUF03Rnzk+jeYN38FW6w4ABf
ND2suoJjAsS/1Jl3PWZabJqRWiqPcJQ0Y+WeYF/HbyARMHwNY1DBtRVORfzpX2NVwPWPFGRvSenL
qfaEld6KjuexsQea7wda3jp5zsCWz/coPjjJfD4vQlNNb9AlBARI4op8Jwa7P/MwS60r4Wg9m12h
t1pii+dFu4MqesCb+AHt4N1j5NBDRG24FjCd65pzeQKyiIqRtBi7cuWWnOy9zGjdsymfiLIu+iE+
2VUZKRnyAMdVYyJldne2TxJrZNS+ZPW82BEHRyOiD3ll9wXMSBkcRVarFLErq7mPtrONR3LGOBWm
eiVNoksvkZCfIcXFmybt4axG7eZz42Zcv9ROfTY5VlzGlwHInf4l1VPXZrIQKDfNsitWWbdZwnWw
kzGqAP31R6lkC8n11eIgwo+z8N0jRmzl+rfxVaIo2ZWwmcCOM1hl5XnkOIsalRtn6i08fQO6fUOr
d00Ui3Z+UwHVlmZgP1vX+DXccezOX5zFdM4oM2AkfYfMTslo436WbTYWZIHx37p5z8eahl+bF+1i
2hfsS49xwoBEcKbl+m4z7crV3Nd7QSRKN6AFQEK73NCzFRNpkwd93bHEwBoEQ9R6TntoT9VyHmHl
/LVKnW9Kj9DXHLTS6BuKVCF8HEUMx7Q444XQ4aAadWCLWN6BMVjDKGEN87f6J9ek2sJdtsRC2SmI
kcwTcmENzHSrv98fBtfBI+CJGWS8iFCq3VMba8IPyQjKv9IOjOAwV9vTOZd6scVaTlVJQQi1/L8d
tJxDB4ZrMfkskR2YCD8G1dldy8zLopcSO7vGN5QawsrbTqUrNmkmNl8ifEUsYHpZC1L/fe/ysmdM
5ZkbS8S55kKZBXF12fZMxTSJ38xFFNTlLSByBpKIPW/4ssHLpkIflaHxmHnrvuhLFzqW36j1+DQO
WV3T/zAX/wKPt3+AkeI7ExJlmk0aVSZiDzUJQPLbPqQha8nxQrGhdrzzzQ1c4jOHh/c0izozBhOO
GqNOlRYQA00qmsbwDHug6lbxUeYUxa4s0XkDaXH0UFGSthjBhRAyUDtLdSOvgEjzLRDd186Uo1+X
tAqtAWubIGdzlcX3FMLPtLIj6pFO/RZNgFauWViZW5r/voyJ0ChTozfbcQmxiQTBxuLXmv0Mq1IM
7Faz5Ayfas3SDS9mX9lebkQbHIj4s+ycciEl4u+6KVosIztFUDAgIHoHGdB0z9msgrlXhw6t2NOz
OQLdB2uOgE03qeaYfDPqm5HcI5bJzJr2/ltX1Zioe6Vg7rd1g7djp4fHzbSaHkB8BSVpqyusouPv
1JAr8DkPy0FU6REBndn/BH3Xko4UEtiXWa9nieWA63WSSWPhHKr09nTD4y7qaSQvnuczbHiAQjO8
lNnwUbbeiRymvYFtA0OTV6J05AFvwQwNiU147ZVixlkfxvGh1vfSWtjnzcRP8BYF41BYeyjOGDxJ
Se5sGaBPq8ik7B6Lxsiuk1gwG4LmiEpWCsxeyrIRrjXJ+Rd3sKrsVu2iNnewRMzjzbGmwK/2Y6Xa
2I8tw7AY0FuIQchSKhbxAwAI3P4O/jtnbZx961JbAKWbiBz2m3ymcG/7ImRxWV70fZl6jzQzlrIN
DMqXHOy0rzVkSLjJvPbBBpAkt6vg7SzpUDqtxN9PJFtEGEEo1eMsaCL4RNcrFC5dSgzwS3wNq/Kz
B2smGgdw/3ERzWsoLi+GhNvXwPjxVCmxvd/ujEX32sMhcfUwzSfuCqNUMudSOgZK3yoGBYvNHeoc
GGiXcFB3qD7GAjRQaUM9V/a2A1caAETzXHmGjzuxisiX3j1vauI1JF3J9MQZiGZby7A0VLXjbHFL
UpswDKOnl2vK6dsYz2SrCNIi5H3G+CPDWG2l9geoCKCvUiIYOWSvOI2VGokMUqc2uHSCSYawA10P
hx35LLMcQzEy5YqZqQIJ5B1opOMmrliELVDrLIAJ3SPWciJZMV/zUFNirJZK6tje0FPF4fkd+akQ
eaYfkll8V/gc8/gxdIXeWu42h8hpo0aO+UL1m7sEX7fWKuhTLyUMhl0tSkHD3Q9yRloOri421L5g
/G+4t/Ha2CqfTQvHwsG4AiHiz6rPe4Hns9UZgsoY65h9JiITPOg2yAThy7vrNrzD9R+H1LooKjlC
GGDKB/1GP65oh0dCM/+S3AtfntAKAExkN//UnsSXwlWqnoAbRlYFxOtsNr0dMxUsKz5YlByMvui0
rP7WW7/xRfhTSns6m8M5v4Zg5jAGihD8/wEZ96jqTExjSx04+f2yhT9gjlQQRrqJysxi5nsxCiGR
4tV0DJgr4bfHTsJEw586na4yCuWL4lj2zqYZVD0HLlJEniPDFpE+3z0jGt7lSi6DlzYRZbyjnUbW
aYl0tdzcOB9aAOvzaNr8jUPhtgotC87kig3JaAHCXHRZpfHFYXCX/WlyCqsrsDReJu9IKP93ejlF
2tt0xKUdHSzgPDLMjEukoAsSA2f4uNITrw9GXXf6zr3LhHBXQrzhviOA5jwxj8t+fOKnldmNazKp
czNPxmArNYRDXWl5R1bhXNIpQU1uncJpLARmNa2+r4u8NKfdHx2F1EB78A43aJz8F5a5X82xyB6s
qHDaG9UheoHUgBbbVyuO27xS4kzhleBsh+jx6tjCX9o2aq8kMhTzyiuFJe5WpzTmlE2la+BhJ8pf
40cq2tCp/EIgoBml/ATSS3+l8HU3muNJKdWvOG2ESqM0Gt0ktw8uqRo0x/L9rRK2LbbBlwuIbnGI
jyjX+kpkn35fqfuEtHWhH56T1MtwP8YGTsI+IM9O3xfIQayukIW+3Q/U1beJtqt0c46cVbtaoZRY
fGIuv03DHmb+hKrCk2gCPhSHX6dsxglfbmhhE9RFi0QIfFgO1W3zGnHhry3D4oDruKoDH+4W5aU7
kNIDc70dTM54ZZU2YvZBMlqaHOeMJkeTqLpfnaPlIQ2d2WEsSKaqtEYpPdklREJDEy41DbP12hKz
PWgLAgGmr3LlwpC+wzL2tHH61mxOiv7ohgWdEp5u/gsa5xPE1RodPC0G8IPytuQ5fjCw1hyQpY03
Xn3CpojzUHz1myh2kYKKeaRkEwO3+FPNVXTmV3xiKjVyzl9Jlk5tmfprTTEuxn5TwxzjM/SI8C5Y
QyvKOVxyguk6neGevNZh41MzzNY84v1uDkl7RVFQiCZbuyqv6FpLyC39hiDzx7cSlxlbQIC78JN6
Kd/Z1myuvPQDDjoQfjEwV6gIvfcqQFg/LUJtYJbuxKqY4tbqDsWFlGsyW75UUgpDLt+YVu7P+/16
/Ctnba1orO0mVjluCmvWJmmWCGMRxKjODibMvnmdH0v9PgqORdMH430eshTB5x6qKBTEnI2BW95Q
+bH4JhZO94YP7dzf+Is7dcyD2nl5AK/2D5Cz4DV0dxOI2mbaZ2OylcIyymDCI/65j8N1V2PwttcA
UWZuyI1DYmmk+LXLF5tHpj0KqraLXKXnXZYfu4L7Jdpb0lv4NkSshu6yKHI0Ybbt4g6Q6PP1+v/I
bclvT0YirHNEAVz/YhiB64p+jxDEMWfnkaIcrU1ATdaFmdq5NiMhSXGhBdZ/dQhs/RqxMqhkDc04
52BkF3V0PGrY91hwBQ7OIgsHkupUs8Q1ak48ms4rOgzeDpKYxiaPnC+Cd3btnM8R4c05V8FbsEef
BGxd3kkTeusuRl8Tm6gFv/i19N/QLlblCFeJ7+1r/05iO2Xf/S/sK+1czyQctOwl+T1hAXpUa9VD
pLq/PhzSp/HVnZvqc9p9nc7P5ZX058vv26CF05H+faJOjdLA7hnzoxnj28jw6q+V5TeUrj8B7JwP
n4q6EVWn0uPTUenB0OjVJ3hTGX1O2fZmRaErGvt+vziqRtdw4kiowUbtXU59/psl9XLz4/lKpDwX
xSJg7vzI7g1O8RMWh7O6lMP5GjTjfzxZROr84YBQj3LJzDAlTohVKu5uTCk9RG0S/0TT3sCMKbnf
7fS8iZf3KcUiBzfzUG6Jt1zzVXG54jEgqULwOPg3Je+wqM7t54TeXy7H4hdxSpbxbVMP2Chd3rId
T2xqRcABfVf1M+k7abfnNrnlnyFjNXmHwvj5uw8Rzd+GzkSyHycU5mkmsbuxdQ2PUan8AZfTs4jj
RQ0pYb7+ij9Pa7l9DA9/XHBl5LkafEyDzvv+v3NvM4NYmbVeoiz4Pt3l9lWRtEwTOX1PZEh3KoAE
P9wjNyhvvPxb1LFz+bOaIT0gkKoztr5oUMijjgTIWqqQCS/bEjwfE7lAHpylPgw6kcoxXCo1picC
eagR4oQHjk3UiDwkfaMxuQ2UpO7BTqei8XhBKO5+a3NbDpNdvUbNT1YDIigISvjzNC5VceoDZBFm
6v0tmmUc2KvSnH5NTbeTJPMBqMMsU1mzSKPJIvR47jHgfY38XXf/OskgzeIYWl0mA+I3mtL7gfI1
3XDvzAsANPN9X1dbMiwKud0S9ZyLne+m/n5JKq+8aNNA4/2o7IeuPxCdVymV8WsWKUTeLeuZW9OH
KlMOJjqqkFwL+LHLmsPYPFXMUReuGvu3Oz6HPAChEk4StgHDadqIDyjy63aV/LTFwyQQixeYPSDN
FomuOjiuagNv7Y5n05+YNYMyxt2tv+gsAd1FNpc9C0yoM7QcqGLqras//C//TuVnUV/ej+G9740v
29D8mw0q33rwFwNiYDMOqxSQv05LvLEpsEK8vts+Ktuy+/ax6G6tB4P4Hjhffd3I1uIbffnivaEJ
HJqO9OFOmlL5FbVx1CVNXwMFbKzd87nvBMl9Dm87uteRhDhUA2eb1bUtOXg5kt2D0ktZtRIpQgRT
3Ztdy0ckPXWXvVVyqOo/WLlH28eT0zYXCLhTi5B1S9Z638ZK87ou6yCZSRG5HE0Myu9hLQJvQ5Su
mLkQMEa49orTrWG8es04MIwGVEcdMM8dpDnc2iDa7NzcZmNlISOrbk/PCHH/u5b3CsPveny3rNYc
EzDNWsvdODHyg2y7Q5DW+nnXhZgM8ROfGQiWgLscqxniBNYiqU9GZ7Yq5IdYt3N39goeUuzFfzKn
+DvjYJky+kUy0kwy8IsaqwtaLlU6H51FwqsjM9y1CycRiACOJDfMrdUiAZf5l+RYfcQuQhoC5+me
f8FmdxNxCxN89wH/tXiprF5dzVS1fWu7hBGVhZE7NzImWw2LicoP1YGL6Y+mMOR0HsXQZBNyESDq
jXgMWxtkISaV8N3alp5wpbraC24cux+n23Psg1TazPCNJ5EqXSHtadOTpCvjqh67OEzGPfJhrD8l
yJFcNd2PXVaIlsPwHQEsEgqmsMoCer8y4eC3Q2eZfQ0/rGEEgbcQTT0/Ft2lp+6R8oHWtdxvc/il
qCg05oNhR28DM/ydbZ7bXcIwumkjFcQWVS+D1eu5laow7fhsuJXWq1HD+vqIJ90R9Kp7hY3WkJVa
oahKx5zXCbBZw0TdU1w+RIm4V5s8zBdEruS3/T25YkRHSzAv8S2JZBlTkBjMjkeraGaR3RVnSlyq
kCZXTGylIndNV2N2+0ysWoovMTmrNT9Vyytf/1LUpLI0ewLfpEwOgYJuRVPzTTLdhogWeNRSzWcn
7HnkvH6QTbX1VLkz7oeDO9aETkm7sb7VbbQFCrMz9P4t0BTamfRa1IE6EbTc/4SdAhS1/bN/fSPj
Cp871q15OSrFqIgO4vXFTjU+9hJILHzGE0WdWUMmQlJHMZYEjO+hk5DelXgiO6wK26Ja4q8+eeZa
n6smK37UyxEUxZOUg4Q8HsgXoNY753pvGny8j/qx/fTyMVMmJr34K3EPuhiAgtJgQhM1dXtz2AQ0
Whpn5xYeTdZB0FeFoO108BlzPkajY9PwBwl7qzK+DEFEuzNB/i93xbdX1NXSPN0diLZ9AQbB9Yhc
JwWyWf9uODW5YwAODutWON0cV39Qm8RXB76a9qo4j5e55uEYUN/lPYvC06w73pkUsHOjqiP3qeWM
II3DLlM4C5sCA7+lJcGDYvK1FZ7n4JYwJKij5DqRAnYgk6WG5S8v05TArb8DhAitri/dJv2OKJh7
yrKIHFM80n/+fz/xqo2OGsjO6rW1HpVjwCY+XtXgwwIuidy+yIwm26u3DG5cJFfZdvwXooK7yT2t
ezHxiXxCsC4opn+1SGYZNjgjZC72LOuBPW+rJCS2KC/PaHzPB4vPw2+9d06XO67Q+a8CBckMzulP
5thUkUboETtnmMTq8CJjIt0ttiBB0i6grhZdW8G72jLk/N3Uq0X2V6JmGwGeL9Ipc+aPvoPtgaT2
fPekSMCJ6t62XzCrnbJqAmTKgVyjKfN8WMC5TcvsTaukergMJGGyjLzywi4Y10gANVjG/4BWn8G2
1K+TuqI57nkhu8v6ZGjGm7d6cxnARg0G5/sdfG5JAipQ+FYO6TCcRavCKAIgGmgNP1+CTxKBoyGO
afWiYkJW4D9lc2CQrtY9ANPs7jIcQ2nxywqS89Z15BoSVdgAqqwjdUtOuu8r6Jj8ssiysHeoVV6k
SLaOWe0OPZzGVQDrqXmqkCr3i6vk2n44Gs/ORRR97aIAtgSc79XThFA+JwwZp2LFTWsWLHozQGhv
I2lMiU0YV4fjtSXWfsmGSkTeuVD95janNyMLCCG8/38k8BFLdjdGZzO/6U6AP9KKltqAPXmHYxlT
y73ZAUqI6JP5vO+jWGt8FlN+QTBh0JVNci+xbtlGoJWEXYBKF8BoseI24dK552wBwQICBHz4uxTK
iCvnsOPaH3uEYwSQ6teXqfVtwPTHplKbiXGCCjI9/8N+2Emj8P0FB+7sEMDpS6ELIUDM/kB0DHde
gfejb3QSKhLm3yNvMhtxeVblZ/TIXZxGdAUYTP5qZqdPkhdV6rQDwCleUmJTvbTYJY9Huz/vb+L7
CzCGAyrO2bMkGy9XzyMDq2c9IqkZXTu1w8IWwfwswb7a7qqCYPTbY8GhqXCPMDg/UFo2p0cjc0ql
6PGiaQla2imr0rqebBBmFVWnqL3Iy9lnxH206NauvwUrtQATpePoIdPJDnv8D8LRe2hSDrpYuFtF
UoJTLMK30bQiBUvTPr0n+Tr8FGt/uwk4iU+Mf13FPtFgW6FBHAO4pp3hPN1vdoyBgiqb+Qs02oWp
TQo/DUzwPoymDLlj8r6/cRYxE8UOvshuv7Qle6kJ2/ObyAx5cnXPc4p254Qg0AbUOt98lC4f4Gb/
Juq5lSjkvAnnIYWxqOTktkI/tDmDsuZOHZSQktkltPRtWXQY8aB39BkAsspBrpqd0a7aRpZiFGZG
pRxaiAg4hn6QAD7z8YdD5BPxxqFvz4fYysQVWoD+CciQPz/2ZlKGUe2CRrHatAupGYhK2zVuoSlw
PF5zglkd13lmlGjErZ3pSwNytvhHBEQrhEL3T9R/MFIKtxbwqHwz6dRiXXCB9wQE5IevZfj9zUl8
i/SyYulkpu+4bDTs074Z2zCBjxmamfZyV5fef4xPsqaMVYxkEx4BZurMvZrFsmqe8Xm56AwPMA9z
735Dd9n3bAZFQYZ2OhC6ORIII2AHV3RH5HG06cU/W3OfsBeWxi2gFJYxZq/C8hmxWfGeRLf0cftx
oBXPh+ttXo2ixVbH+rN9WAhv4YSSFtxisUwDA4Tnuc+XtkbEGVWk4PPlEjoSc0SBTzPVjdQqg7K7
NsMPsFLR4JFWWfOUC2bcmgVOoeIxn32o/ZfaCP6FeZnrlbGHXIg2WqTNmihsJA51W9ivD8YLxL2L
ojqRpBQM/sQgskFSpLF9CaDa02QHMQIIv2i0P7kOzB16tyRrJAg272fdgR+hf31CsPpbTsww1wln
/xGcKdKfFXJXa42uQsbS6nIPDhazxqo4MaeFQg4O2qQjW68RD+inPgE+RBfzUOiH5sdSlXd5m7yS
1LsItCqy/ceVq64lkFCdt5OEHZEYNU9uIlN/7l3ODj96rLsqXqeYkZmsfDvOhLiSlJ6m4mpyCkPq
e9/8euiM9qN4YH5bK2PJV4gVPO+Ara22FChBmJKEw2aWAcwsXLv0nvv3kFlHTS1reSI53XnKZix6
Eki8r40ieO6NYuolMWUEPjNheXqCVB2iSoeT8s+7gGXNX7DHLb1RZlHHI6pSFvjZl5l6+iJD7oZ8
Zcgb+8vA+VGDKj/EPC8eVUCC6fprVMsa2LK5SGjFrH4c9EwIW+AMoE0m6P41cvD7cGuuMjgBJqhu
oLUon7mVGuS69JXyed7FtPSUlMFaJPgnlvmfOnbXwDWGcZ2gkp8kVTzRL6yTlo/xAyDXXf9r/ii9
HzYUKpwTDJUE1Ju8Dpy5kBXKnoZLSjVmRwStWx4UImApWowJYOLhXbNYZDtQORTgm1UwqiGjCy0o
PX/dEr0wyIfTWwcCe1Wa5VSmRKYP35f3denyAwhImQBmUs4tECGJi0Zi/prOxthWHjeUXikFY5Yi
jgBCCK8YdFipCnLN4T6R2GI9MPH1ZMcrSjnyEtkA/rxHHt2cUa+oqs9UVHCb1hQIIld1kmXCIGOj
n+Jdr8cbEKAXQHlsR8RDgmAd3GHUVA5tmG9z9tQO8+gw87kB8zjV3zUfFtkEsyJ2hrEMV4BhZr6B
Icu3IoErshTL4kCDTtKyLn+7EPaC4z4+vR+ZF4eGAXyBcwduNu8+wNgyreRSJjTRmRTX3hXJvx3u
RSzRxkQqujZ+aygmrYRVrVkQ3AVLr/nqMWQRjktsBYl82d2Ju9Y4GOMKRmCEtkhf4vJgdmmViuXm
DdnNcjgWdKnHLJ1hRuDnpsuw62Mz+xFZqzAoZboFsGGZgnjY5w5XNvLTZ51L2OBt6ItduZndYPYo
zyno0ktxdlw7rD/JPvE1cbsYBKwu8qwpmJecopsxK7/CZNoFxUgBxbQdklTGPsmKZHbRaOaHAbkn
FxzFOvCIWIe20+X9gNp7UVjMt6klyUJc4fyRRs8jbhlNBNbYZ4gRTwECtV7fWWUJ8h8iWRlQEBni
sRAtSpIGXtPgIhAJIoxJSu+3sSGmI2KTNz2Op2xNkXyU95pPB8pf21Rw2cIDHDiqDUTPjylyMK8D
S8u6L96mpBmVCMILhMVIW2pUaqzBSO6nKRGat+nlYo1lkjogy6oZ1FIvh4UAh+WDvMKMKXqb4ice
1WHV4kX3yk5z9r1jG7wDCFtoc/Q3JyYkMsybheYBGx4eN4jh6QoboKjB8DmLPWlk9hNA4usON5Xl
F5DaNXOakf2jYB4ZaNohlYJv2FKz99aIuTa266OX2ZlPFV47Tv8lGx/ZykO5V4fEvrT81oShMZBI
e9fhICfGm5YsomBb4bYtz+DvFZNDyD9jsTwQOD+szwAYMwlnAB0FH8vBlIOvMb6tjDg1OBfq4vD+
r5hFQZ1hkSYI4HsaIQjdZPUvSchODUJ3qYnsuv4zQpfB+R3vs0mtTXuVnTr9MRd+MhYMan/i4hVy
O9jkgFRGTByCaiGPmaX/6KK9Ct1Tjn9nW1Sh29EdltvfC7jfcfCnhnVimxFTna4ibowy9FbPu/3n
LYd3BWSYdpWiD1NrfUqxlZ0d75wZc/btKWAzqSiF5fRIZ673A6MV7e4mqKgyzNdB7IxZb6X/HWGh
sAI84lER+tV/Psg8j3LMgVcPlrODUHzoDy+uh01qNLLrF3W9ZvInsK15ROmiT17YQNHFFsCHbJjn
cINq9zcUuYjOe/lPdACOyc4G0cBjjnxwR+6BTXqpaxGJ6c2afTmMMPCdbJ0Rrv6ZVlgbzmGAMn/W
oX/FroDW/up7rUMIOnfgs35hnkd8XEiiPHIfEaTQaHkWTPyPrMOPz8O9Wti+LSOhXYKyxLhRPWzP
brcVS6d++ptNUa/VstgBfMxOZATsMEgy3EThfc7KFXQW/6dd+hbW1ikccuJuhtcmtUq4L/eHz6wL
4h2Eny5uEIGOizLeSfvlJe/wzr7Bkykhd6wLJIWunxOcXebJaALbGUIU2jH8DE6iJYcjsIzYdvVy
DAK84WiXkbph3HKW90HbQgVvSyFhCNcj8k0amm+GC8o/MbWfLfGyauPPJj+X4jGdivgtqpAWMFoi
dVpBfgsDBn6Rhn6IxbxTOpd8NoerJ5XNAAEaHgumMovjARpm477nQ52g0dX1ThyHCuGs6XFYRuN9
GZoPi7oNTkJHvYKsdHyc0N8vsPnJmZD6TMaPBPbI1BTmqEmrqEOS79fzyJd/zrAhhpAiYVBZFtE6
lP7aEcbPwL8HkoVn/HeAB96HLn8R9BpiDZh/ZD0AdwptMxwljYYfeME33VArQOUZSfXFsUUvMcLG
qqkk6OV8G5uYUtxyfKN4Se1LPSPbmx/XpVWJ3LCv+zQKAlGioUvQLSxeVX1j3aeCfNrj2/3WVMWf
TFtafsR81MR2oPGRuIm14wg9dJ/EG7IFrViWrkbh8FfjrYioxqyM/Wn3Na5Oi/CSiyC8TRMJ8IHQ
C71Ztx9l6dIzQFwRwJgJiEy6N6UZxD75yqRfd6qzQUgc8bD+23PdAH25oEVBwjvVj2xr+lqaZ6ty
4opNU4/0vZsJZQ51cpzLnUyN5bBVG1PA8eQThTF72ygOO5mDaJ/A7pdcXiQWMaL2sZvAmrblFmkl
YkYc/MpU9ftg4rA/ZPV9dlzY61iixuqFaI8V83bn955IMdKJyV3FDM+CEkzicYHKdZYUS+Z94OR6
DlJhSprSvtDdTe0YsTIreWPj4d2klGXPSWessaLLLOJWjSuSRKddt+8d6IO8rsDdo1TNWxe4LSXR
8L2Kzl5K4hcOLl2xZAnXnyVZD8jKOTA5/hEcw3s6IpKzP0WXDUw5d86H76iho4chUrB9T2idk9Cb
2nDEP6adLVVSMFPwXOSa/aMEM8Be2cMZIwunrfY11TXLLku+krGXq4tRUm7a7HRXthpo0bjo4TJg
IA3rS/tn0L8U2u5IO7cl7JspbISR4U3+KP73wCQH72ppjMGwpIkt2A51Ul2viuEVpf6Ycc/qofS7
jFdTdqs1Iw8nr0neZGrTfnLLxnd+fHkNsu/XL0aowLfpV+QPZpkPJOU1Fi/gXh1BThVT6ae7mtPc
Ce6nNjPcgwvG9xXp5sFmOfPg/Uk2tJaTPCh2yKMjdJV+BvEHR/nRu9VnwEMZmri25FCYJhpT3fBq
T2BiA9BqkVjvgFUNZq8MG1vVOA6BqOERYs1p+eozPzS+tVDSD1DzJo6HwMR+JNDc+sG8RCHpLg20
JJlC8eish02lz7ZG529YhpWiCeBl+dRSMUBaUiuhWqtqDhGpsDWGITtaIJPr2dzgaJoOPsnDV6Ay
sKfG1nYLlI57zOu0tXQjIliCg/msHbtRO87zHn6JwhW9GDh0nuTw1u6H4HXCg4Xn/2mftGVCVkYQ
xTBBioCbvfBD39aKImLl2wm66Db1Xd8RenYu//V4kCBKEXJJre4iculMzBEoFJ21eSuazDNic7N3
D3EkNzaDSW8Qmucshr+J2azD7jRT1+V2ZSn8qw0+4Ez5KxMTrB/T6zFVfndm9OEW+ruGPucY9UHA
/azdTrZmprgqLM3NDdCoFeBUbpQYAhosjmIj5nrzT3UgT1D82jhOAORRQwMGgkrUnrnoID30cIos
V9tFIpgtFGMJIwj1zrgyu1Gzj4vhfW6Xx4LeqEY5v6xPWk3HeXHq4AiB62N4qNOAXsgiJy5v126H
58LVO9dE7sxOV97LPe+Xe2k/kwtO+Rja5nNF3Shl7glACY2x3bw0o06W2xhe7IhzU22b3uqiuL/i
3uH+WLQPD15Gu2/Nqhz5RuIxcF1dl+e328YviPuM03ZJKrLdI9D/VaRwLjLYgnPa7XLGLCeq77Rv
bhWZ0eTpnbSJ5Uzgi79vZzMW8vRbTsb1y4H1uz3Qc/oKRKG9PNTHk6NgInEfI+FApJmsax8z4xln
vaQ9rNujKZfETlF2d7ezrfcHZNOy2tnTViU3s4AXxo5oXQ4KgtV2WM6FJSh2GukwhC8aT7DSBfQX
uY8es2QvrWXaao/Phky5f0DZJVYHmR4yr8C2fMR3CbUfRzw38fO4IbsymocBG4JuDj7/4D6Felq1
0EsQ7lTlq7Kqpr/kcPWSzIi0wY4vvzT0QAhfXinH+oGV1wfi8Ak/Cwbr9JcszkhEm+v04QLI4USF
mZg8TSTPAPu8VjG/UaUcOs+8QltaGk5r/5OrVKoWwEY+DGWhsdKHqy25cQgBymX036iLQNKoOHdF
SFasOBj6ObsVmIpciFxVnFfS1gwLWySW3A5tCwiCvkKkMi20lSaVI9k/jR8s9+EWiuuUh2FcP6hd
FHQHB0ywaC1Wa8v4lTcwni5vCsFqfT/9Ga8HViIcBv+BsIr3XT2bexOkNw5PZ2Z9SC3MGIMTF8zr
sPuOndPEjZgx6StVXrdfuIZdKesWet3+7Ho7JjAt9/G5qNQ4Tos7Uydd4W8tjFzU4a5/R3xE0oX1
vYFmI4l8QMopS4XoBeR5pAJezp/Z2lV8Uxsb7i7zv7VsQSzryuPsvATevkeGVNbsVgrc+1gtFuIB
DJACKH8OKUlvPitjnBf6M8B6izbxYOySI63ED3E10s/a7F97FaIafny8usvIRqrgU62siP213gk9
W1LozL1+44bHPzx8SH6d+MMYAx8ahtKvLoWRraMY+X5JBq8TnwsZ3mKoKjK983YATT8723hiPvZu
xvOgtc7IFv/AefTyDdRJ77tbpOu7Buk6ZiwT0BF1eIZWgzCsT8y6esoRg9sSdz+UMV74+ifVHgSY
Q6iP8uKwBEAeUD3RfCkZy9bdmS2KoJ6LyxmUvnziOvvq/OG72P2roUI1Ze6Uoh7UBG8ZaFK+4VdZ
E5+6CZZv51KHze48zPvY1COZii4TpJXK0nW6GoEOTqAj68IgfYtt5AU46bogg2x+DFszpn4I1v2h
4svsgZFSxpiqU2u0GFiQVgBBsgZkcNy+j7XSFkPQjlBZ9MNBM5q5DsAAQazjwsq33oghdJzE5/bO
TLsDyNJrEd7Vjcz6lhuFhR7UESmsL/kx5rkcmFLhlKdodyb7eSkYF3M/gGqAtHIvsQJz5KaMMIp2
0nhs1JTRKvJY4VSMZsOh9O8RZGqGZoBoeRRpnrz6GompW6tsz4vePBLk+yYFjXV9T7Ggi7uARhOh
8OTlXlE28k7fY4tEMVIWtOMXhiPiGsJjz6A5maH7BaCMWbllGbYQ2ze/cXE3fUQLZSrKvQb5iH17
OvGDNoWZIVJeDCBJ0Mb/5QySjCf9jThgOx5qeZx7EPlD0dmUIp3sXJXuV3RXGN57BRA6OE1bnl5D
ctgobCZu+Z0nQYcmr3srYuwuv/vO6snNECJLOxiIMVq5BaLqmPCQCtbj+imiQtd5omwNXjymNiFd
tIBcOSlx0TtUG46d4ptR4ZFsJrr9/WiHTxthnmCiTKUx0MG9cQfBGU7gyKPwPhZPN+7cbTnxVtyQ
dCU+yIjQYyMhEJTYB8Xz14sH6Q1JVN1YyDW0Vpr7EVBArKpV8CVD8q/zhUZAh4VWBspmVmpgTUoc
H0hGmB9sU4gUlE1RxO6sE6eDggBtQ9AZbAHOvAGeK6NPt/ci9pKlqEaRJlyKdfQ4/hG/rl7BpqIP
JU+3sPXnooNpWLvc1rbBOFuaH4X20JnezTY/V8cu0R27q2yDXFihqAkyFcyUXpjrsj6VSik4RGQI
QMP4HgQpW58gJk7jxhrPz4UYsYTw6lNFfXihgeJLOBqs03n+ASmNF36bTtPsH+REEujUd9M1u5q4
xPyfBC75NHWoVi/rGdNqv4yYoybhfSn7ohYWhVCBmrqYVNJu0O2pQptBS0Ks6TDM7Bf8rIddPt07
3qlu+1PxC2QVgg81zBD2UwA+AKmdovsNZhUnkI4B0DdPtqUdxweKKeUjdmUVv06try++gWu7lCrT
VgMi3/zd5eBRh/R7arWsaqfuCoqZLaPolLGxdhDEuo/DIephqJ0vZLRVjtEQ8pQPpz2XYR01xCQP
qjJYbNnWPkXegTMptPXwGwbe+4a0G+tjcVYDpXqRdvlnMNJ+h6s0pniImJEmhq7ZD9FRVCaSxbM9
rmBM6Qdc1MUv+Csd1bEDVwfkO/Ti1mVU0t2++UeSK1XjLY9RZpM41knFXjQlptnYL2mInJGZeQWs
jlaeBNwDlB/b164pfyVK5ZrYqubarG8lPbtXPyW8MMG1IP3csYl7E1S0gP9NSYbhxuJOYx3YrqUZ
k3hcSIAjWy7qf/wcSvNk0aKey5UB7nHWSnld1mfjty1cs9i5xENmrDadlqpSEbrXR/k2Oczi5fMv
SShVkJ5G45I0RUFE2jxU9tTnfZbD1Plxx0xy9Mg3GAMMBnXcmUPBhC2fQaHcCUTv2JcQNhSTBQo9
wj/rYM9ujs6zXx7iAWLQrc6PaOu3zB+SZXZ0TZHBfCzgmAGhbLOZsKgh5Iiue1p1L1xfXtfTUlut
13BgKE8sRuUu0kLhIn6J9O7NBptsI0cK7E79P/XUzvctQ3p4UTeSOjrVV01pLwaCOdlb9IQQuJ3D
XtdkVgKEIVkB01L1jGk7/u3craSfYzdWmJcwmCdzJHgK+vFRrsReyMeRQnXEJafojxZ0zFPGB7jT
zxDAze091qT/DB2ecSJ6sAhp6/ro8gfwI9llIjR6AJPQeyErc8yGblvMtf7qwV5hKKx3corHg+Jj
KsIdEcPrakIc2rtGMnRfOx49EeRwWr1MsQX91OXm4N3ABV/dm2Ymv/eCO6rUm4fM43dzrELwmoLg
YTpQLccMqwmN4Ddp5vz6ykPmOek28nj/8anOTyK+CmR39s2bVJDdJjkZ4PANsqud/treIibQK0U4
8A3XGhHL3C4xs8caLONeFGDY7dMnh9MNpxL27uPnAcAfdAs7HTJnXDxVh5t4SKfv5gXF1XfBQMJL
H1x6G3CcTFjnixW3kFYJnaje9xlNwp+4HmIl7m5cPGSAIJhND+WAiGplNB/2RtByiOT+jFBEFdZm
C+r43npzV+fTFf9WI8j2Qp3DT0XYkh8p5u2jTYbRmEtHevOrVZHMh6xwPDQnNdHxf41Z6Lr1xuV1
wr7mJf5/wpupRTTc0z84gtS54lXybxD9Wsq5Prqbba3gNac+8TSSEDhnn1nQgzo1gZt6BI0TupGd
qm8Lwnt4uliZOHHGy1iNAWQDdOnNR3DWnmPJm0uk0hxsEunHeBefiuR1kPrhettt3PvLJ2DwoZ6q
+k9+A2xbrF05/Qr66h4pRsuGaj4TROi+re64UeEiPCgQd46vZZR4524uZ59+eCKFU03TgvfOMPXk
vIAGUSJGHRIxCSCVGKyFMZHjquWd+E2IgKwlfB2txnXc6YZbQf5r2gSCywOeNcv0P2Jy4BJtprkS
zYVrmYNjdqgv4fvlfUiwdEGgXl0G6/w8ywIkzSQYbyAyNdgY040LRZLHY2/9UGXgogSNfL7VP2Y8
BH0M6OXkgEvBHJiLc4i9drW43Y/VrTMZb7SHMiy0hhXY+x3QDIn92u7FHj+Lv2uWxCDOa3ezxLGY
XwF64xdyCFeV7QdKaPcvyk1r8hXcf4UeB76if7/ULmj2874TpEWQLWUbSocCjoVS81XHuwdiZr2K
NkLuQ9Zy0b+HKJEyu5TeWhy3yPHxxzNgE7HLXZEUS9940uFc+kJ+IhMrcOtj22UTH5KKV83cI8tL
YSs9B8XxrtVEeGRRjHQhxnWPfnxmIaC3rkie2ozyxIExR7H7pPjLcV+ScT5nJn5x1/FsQAEAdTF8
wCQpSpsTrdfhHucJm3S0FGq+7w7vXiXEfganrNnLKTplYQAgGyQM07sOXP1y4fY3un2Vvh0/6Kpz
ZQVDqD8V2FQ6DdNDB7z+nbab3b5mad+9nXayxXoZZcfmUbm1XGdDZ8o//ddPChaubWo2/Kj6wvRL
FxnVqu2tvmoeUR+p6x3tnTWuyt4KvH9zDbvC8mDAeOexS52cK5ecSlPpVSVSwGZYck5KlFE6a3D7
5UYZXmMbygFy9roFuKwJhHRKcVkHPH4Kgt+hBN4R0M7CRwhdZCzsQ9gXjaY+OiBfH3uvWQ5+zkSH
/N6R/zKUq8tohj9MBNrXx2gfJW0UW2o9x6BibHaI3VRoOtSw0oVVh1dUyf7TMwpOTuUDx9gFuwak
vi6UAg/reOzJHw6LSRwjn7YqzPW6t1MzbMR9S0kiwm0E98IOX272GtEMN1DMkyAhQJgbrzrbMtE0
jlEkFPYc4us0akxHPxRWCDr/bErqzp/dHuRf0tTFQkrDxWS446IQOLY7PiT8nPcQSzv1QnF9TY+q
bwYpWUAofhrWLsM+EgtreIckPPSABiIiek1w6oc+ubYEDxpn4LMjJseXCTcHfBKBMAavsF2H/5u4
1PJWDl5htvD2J4Zdaxtkg6BBUqThHxFc6XIlYcOCbv9/toDrfXt1KvTCbILfssRxjij9up6QvMf2
dKL8sJmwZ28PETfi1Yp0QuTXooeOeBzXxc0SSqvg1kHcarH2r9MU274QzDI21Zi3wi/Kdki7y4Xr
Pt3YupzGosVVjPnZMHzmqdzTa/18oS2mkj2LAdvaM9409XWhMAbIsYSuQYmM9Ka0GKa5hDImDRzV
g8gnD7KoW4ymdRojJn/UbuhnEqB+fV70piFLn3Z3BHzQCqmvmul39otEmGUY4/g1muxhjpFKCWDw
91bys49UE9fVo+BYJY3pRuM9+bf5ZaRo38vCWbLtCOFrvV0VhsNKDjaa4YF7v3HyXCfIg1uS0Bsy
YyKp6twx2zu2qryxuwJSfO54GE+8sgTvNZs1dzHgOnCr20U63r3I5j2ZEjvxcTdysTtZnQeJUuZ1
MQHtfbnZqzqLBa/ycFFH3ZGcuAnMaSilCzFkFKZ9Y8ZSY24cO1Y6Zc28H6ubE6GbBWRcPmcohLiF
ZwhwSIQkjFmx5o/mH2te+MRL46jhOlxguIzd1knEEbAgMu+LQ+PeJvguTxggJqUB+ZMas5kvA6Ah
qMNlUg7tri8DHlbLtwJ/03p0TGM0tUI/ToLHceMvv5lRqsMZEefqIO+hd23PHfaSPpNomXBJwn80
pXPLFgzWjM87lABwxqdhpAitlu30E6Df82CN01LGi5J/zyM3nZrqIPd+TpmZs+3Qo8yeJOS8FXo+
wpX5vGQxXQNqLZewzjC/l3Bu5SO+CNYCnHoWm7oykG1pjNmbn4ywL59MoDMDGgf2J+SMlImjaXJf
tu2lRJd6WYTEsWVn/kALjsKARqLaK3K6zMLnQDb6qxNsN2BWGXYqlTlSenEsZdbFULCuUhZf6k9w
Zqp2/9IfqQkH1kKGH320ydIdJ6iCAUp4k8kWs9Xy/EgTp3rvXwdd4lUxg1HRMvdDD11dQymgrKYo
gBWQ2Q/jg5Ui36N3Av3GPePW0tnAuxVu1MUTvm1phxsFauYuGKMvvgYthfigwRPWlXdDfpEjVGBb
Ej+FcRQhSeN8ugHLN3hVnci3xwejXEMPl80yD1lDm9X1UykZIK2Qe+/9+3/J5l1nLoZWtnpKqq04
WlCcJzNgrN9lLpYuS2wQIClWdbE/otgM5mJ60ey3mFgH3WBHSgttHMYmIZ9CvEOTWULt6lUJk+58
v72FP6tAxDEQGnIUE30k3tQY+Pp9Ncttm9Vb+F9AbsI/csKFwY18I6bCR8rKgAzPrhvhGk47/hiJ
t1SgrBMu2pQ65kKIHQn31yGKm3ql5uPi20uPrXxTZZqW8EgCXuQYgbNByZazHm2ofb9uIwz1vfms
nUlSiGs720pnZmLsLF8kwUdvvkXtQVwetUhIHHGf6ZwQxcKXGMJfEAitX4bKilVAV9qxhLfZuafo
TybILg4D9Ajm6BFzovfNDy+M3xgxNn4QxPDTZiCuRTOwnpG+k/1Puv2K0sqNM/YEP2Pl20fzw/rD
ZG3ojpQI9O+nGcxlqDfcfIG/oEU3kHfpXsgcOSwzMCP8wqqzXU6zG8tC2+fEvWZNJ4xueDZp8OAq
ZAfVWobfyvA307lCyMGfyF9Hjp577DPU1DHBl6iE/cnoFU8wuLTpt2qyWZR5Y+8czbx96bEDsHSA
tZ8H/9pfksAcQY9OkPvdYwfUXiQYNcZ4E2UxxTZ+md6TPw+YomV+pOFlFj1C8qt58EFfhuBTIhyb
DTldZyu6zpqjmghG+vUvXsd27w7lAm748MTfA78l9bhU0XCExdWxRtyBvKLma0qKwvwZulCGIImM
RGiBmWEAMYnjJTTxbW+w7NiRKaf3nx/CJ3LG/dk9v2RvLRw4VxGn+soAceCOztdT+soEFpZ0zjBI
hcgqfiTEyaeMiORQCZsKszccicwcCTLF+O4TN5iIslv3Udwv3hf2ANookvpKZnFgOgv4UiThKjPc
GwUt0nwxLHnkP4L3KJh9XicfBm9lI4cyOEBt5gBvvC2aI2xcXuFl+Hb+jXW5uKhxvA5YCaFJD0jo
cKimDG9vhYvI32s1kIZTs8xP5Zxducwf8RqbB9lquiY1e7cKf+72AicAtS2K8beNufp6Hl/K49E3
wUfZS91IW1QqcK1iuQu8R7flsoECICM1kJf9P7/6KTO/33f+S10/MIBMKg9gUvkPyw/WpxWrRW5G
5WapewnSYtW6Qd8+qklImDNtUFFeyFM9F7gkD827LFHXVQoqszWxGCjUfxRdwyaVElMqeONSaOBf
Rf54+nDBPTrN+opDZ2VSs2NHZwVa11v+OXgyqeoPuQcQHc/vLDkymdwBFtvSHHbD6syOs0nHel4f
ur2G2lDQ3akNmM12Ee/oIqbhOrKqi92r4SYWHV3NMNDZUS9qDnQEXiRmu24uNsYdJ6x4m+wMJI0D
Xm7IuvRgPtfmOGBalZ1Yd6VXm72LqlGO+AhuOdRQVZy2n+IRXkwHsihYDw8OY+/YnukyL0HoGUGV
wcZlu94B0rqBrCkvV+6/ycW/LwXEpo0RBWX1IIy9WeorwzeDxjoCy8dnjWCczKfnLuT5IFBnIj76
BURbRyAIfKrQPxzzUGkYl6cIxJgkph23sGYHcTtvhIWXYm9HyvLwPZUP8ks3IFtV82v4/LnReG3C
afxNmXzKJhQMsSBfP4j3iDfGwwviiu4zVCpP3IknDmAz7PQEn8izMpX/PCROlvpZlaKdU3zYpejH
CxbFafVP3yjcF1c8TDlgDr7VmrdnU/RIt5gYSbqh1CRgFZsPJtrP3pbShHRxN+3QKBuo1UWv9zu1
Dow8s0sacSMlRbO0ex/TwEh3Pw4WqwmkpAddWyr1J94tOsWKi9VMmMlSQdyjDSNqNc7FAQ5o4YvK
AwB+Kr8TD46b1xdaYSJpzbOcADRMEmcdHMIDTMAkM4FgP8+0cUGmSrejZMJJiHwBhxy+1TBiIrmX
Qu+sTcIiQNStcUx/og2kSj6aZh4/Uh0OY80uomlPkelOeOxDfXb5UyjsYwl7e0ih5wg3kTTTup1U
RCohzdVvLxWSO5xfQ/4TM2Ak5awI3XloBlu3i2M1C53O7QtJAopZOgsjOFWSHZPE3dkMTa0Zefbq
lqyyik7tU55BsaDhCBS9JvRuR/0BuubnDNwOUfQX8UHUdfb68/oNJ3L+OeffWBjKWLoMeQUQPv0l
4ECqwKGGDvT68IxqMFFLKo7HgItOj6S49zLzxP9jyKufdCcggp8Gr7/w4oCq1BA1dvv9E2TA6/6O
ATFWrj4ekc3ruQPTOUWF9a0/A61Pq0de8BCHII+RcrktBTIpXaulg8DmrBHT+0QMiarIREmxtEWJ
vAufVBVSCWIGPz4/IIt3Pz+42wRi6MxtNK3SDW5+bEg+Wr7oYoizFec/Ob40r2xAxRc/SBuhy9Qg
1iEHe6bC+UpXjlW2Fw9rnQE+cYup3gTZPsGOAQAHzeG1AuYuUDvbfx7c3SgxAR9xueNkLGJc26ng
TRnNTlp+q/59bXusxBeSx/a51x3hLTxvbVblNuX+QAmbiAS5t5vBM5dYZyKal3AptyM8/QNFeXrG
nkbm/7JU/yfFYC3w0/c3cvJTPp2cedBAvNboF/tU548w+A3LpAR5oM7Tlv/EfaVzuJCrhm/CABPI
NVmasEYaT27ttLu3Q8N68NELayCm63Alkxgs3QY4i6Yo1/5HQ0iJYxwHZGHiqiQJIlAiTn7DNEwi
YJbBNPGC3zNsuHYKddcOXxQfTH78v8gsSpQHvNaPd3Vi9fHe8+spnybeTVkZnrCCVdUK5Wen5r6M
k5B4WGgv9jwhufqtg3BcL4PuAafZ7o1FoTabVNzVZbw7pSTb0RmN0RZT7ldJgPa9qL9/CEh0k+0S
etpgY6hedko0l89Y8W7Q+A9gIBExzYKTBYzMWtmBNlSvojKRpl1kAgkLUiKbJJMVqWHR36yxRMRM
fknVS7XuTV/EKYOkTF9BpMLYGk1CRKNLTAzmjv9lyRRbH4HK9tDy5FKBn1EamI5Zj7EqZN3FEM2k
TTWDdOLoTrH+LFqyBz08rYngB13c0cqwlNbC/Q741/oCaqaKNC/t5rXe29W0NOIpHkome8+6FRCD
hkolL4SgNgPbyqOoRccnbjMt4BG0d0X7MxRm0huSkNozC3ALv29XDFyioRNyYpoSwOwsSNp1wurD
fTQPCncpo/Jqx3O3m1sKiWZV3orzcaVu4OPeyFbW6hmAVCeoD0+UOMfcBBypJUP5nqI0nmHDviMY
ITg/BS9Ubp9N8Q+I0GANFO9X3dsTvGWdg+WTXh8UYedYpXifQpjHT2yVYn4ynkitvbqIgzCatDS6
gDnaI0lM2eyyf5nBbwaxtZhblk4PP1zas+H5J12YkDE5P/ewj34hWgbg14A0b8bOUMG0CN0mEPdr
5cseN5UQtMrv5mdnEnWxZODvUjk4X/RLQn2qNdTybsD5zdKgwEQam0nIefXuS673MQIMySEcy2TU
4yMgGO5tnzBJ8braLcs8p/3c56I3pYTIsi4OHSvxsvmMXSZwfgw1ES57MqfE5mOVpM6kmtR6jPjI
fXAqhhU4HX/L5G+KGwKmyhpou65G97Pf9bp81nnPWQ1J3o7EVJwlOn+SYIge6YBPpGV9+OowMk2P
go/rK969GctgWWyrIcoYDy9UmbwTvFvBqgUVOK0B0laTYjSbKChec1Hxe7Uf6AIjGOD3hpOn8jOF
kKFo9uKfRYjD1hppSJ68U9X6nQqR7wCSOkBwUX8nRehXg6+19JAJPqBnhviEgTWZS15ReqbBtkSf
QAK45O2Enjb8PLJ6GM+7bgiecVllt4jJyQvygK5E0QsgbbF6uKoErhsogf3P0ETJoAWBcV+gz/fQ
v2TbiHgG6gbvbJhBadUzzqmsh5b5bNEZKE8znd5/TmDF9kDV2brJs6fHBHOud/cPnkKH9mKeh+7g
ZYdDah2byzHV7j0AywuwRaDjw2/m4Wvj0uWGPCsg0PziKoGZfn23XsYQrafa8yEK4+2ccr1LKGzO
Gfuq9nseN+AgSQ/VgdbwD72UibcweS63y+lRLc1MCG4zNCK9pjYoUGERsksFKn61F2OiprWo++dH
BplQACzU5J8MFhYyLxO9hZwsU55ucZ6sdZ1fmPu+zPDUuKyd4bMaAjdRlBhdjZc7LhcR8eTIfq7J
u0Izv98hs1EyaBfcu01cIPaPCScOKXj8HOR3YLJbbiCLDkqeGdwwKSgo+ZMKsoUsteTo1oTMa+Zw
s1cnMflutKEDmg5sIIMaOx9N7qmDeWDlsFlUrFvVGv9/75IVOBqH8XIeEgcT0tht3g6EaUTWiLGx
p33MImeHvcy1dYZtYK0cc+gCcittQ3gXBg0/ohLhbXNN+Do43cIzuQb+w3GKvl436LaPAK7sKJmH
CfZ+caR6xXKIZXwSTiLRsmdHY+Myo34b19/hNfYJ/oeHbxx8/khSy/jWrfZL0W5OgxyFnZ+5jVms
F/RZy5tiwkODq/PK72qS2od2katmzyCM/wLHU/djuLz9fHPhSDufrPVDvSfgmN3QxPAWk6y4UpWI
6eMJzHMexegXaKOBq/aW3Of9YCaOxr16GCaf31b05BvWWkQ1p3Y9mTyPKHrkqZGgo7zVPUM9x0tr
PNBZfAo58SWV8TLQkBih8/A7Bw8vTNLQGsMcd0Iob/mxEMIP77V1Bt/KOPK5vm/qmX+mzWYyTc4C
MXTXPCGz4OK6yVKVCmJre7uRf8VPi27fG6B2M7c3HMdylzPcms6U98hWtEodyMTbHeG149cXZ6dV
bRjI8Mdr4p2c8JcdRUnIoJmSHRbqrfDnHThUWy4oXjVdC0nfkprW0TZg+0lY26y8c1DEakP45yy0
KrDYMQZkyPMGoZEidMVHK2kg5LHa1YLqyGooEi1HiCIyJ9bmrVHbm0tVi3TFH1VOmJ8utKpB7DgO
qEpd8b12Y6cdsigNK9wgMa1xGZW0n0ourZ80uRV3tyr64agnpUMEIX42mK6bYzhcGufsXSPLPHgu
lQomhBOiALcQyL2INWEqD6g4dgXESy/oOYT3+1PP1P4ReOreV/81YaQafJ3EDNEMeBU9Bn8MtST7
eOZPKn/kD+b49hiNGKzD+OKutk2JASNuTlEjivdL3LrBTJtx7Wx6cVG49EBORneTTYQluYyYgkAz
+i1752l/1iNT4QeN079BM3Gi1jxNP0YrFINSUscC3sGfdQATFHRnk/3GUXekd+GTD3E1YRAVgtN8
fnRXw75m6tXcHGTSZXH5bcAQlkLHRvaHSwpTxB33g0Oafc80FTsm+7xmEuBYJldUmiER8042avux
YEPpn+Mhd5ABA1n0Ygvo87YFhjx4b49Ru+h4XPUPNtNRkqk6bonRKiaqNukcwRjxfG+opp8HgI8J
W7KWkgjcTCEJXk6D6Umnxdqd5+CzJz9MwI3g4nXbkOIn4ddBD0GIx8px0jeg6tPwKYGas1HvyOM1
CVKPaMixjy4HgHSbA+PbXHWVUcQrh2t7AdS+sph4qYBcEl2mNoa/Q10IVPjzkS+tdXXw0BwVFsMB
yl+6naF97MlurjYGTe5j2al1HLX0c0g13TUBCRGU09uzvskstP93XK4WXPbyIpNA6b0EVtFXqZce
2ObqY4CwkliX0AcUN1H5e7cTIoA9AffII8DqfNBSvFkHHbxSgGxaqiXgg2CVHr6gcgVjKgkbaEXG
l4UhfO9mZThEkrGt3qO9L0EqQFoA6VME2VH+pwJI6zMc8z9cWvoHo1QaJXC+gkHlA3ShFnB4tJ+K
/eBWYrtRdzVFI9OcGrzZF2uwdUSIlwHdk7FAJML3kt6foSz/CYOgIwwYKrxkYXsIgpj02Yl4Tn/M
z+ayLwPJRN+uWxGMz3gtSH/ctGJULbKSEOUBdP156/QBEKcnY779eVPfRyvQFM8iBPvpc48wDeC2
BS4ByL+HG6D4wFtct7RVdAIkIwiuBbTCaVchFlTK2UtMXAYY3B0dVojTawss4FieMo47m/jwJcKf
OeDRae64lHp31bbN/NZftLrpdX8Gt1LklEr/u2nVhM7S4+h6ZRldAZWn8xT/U48+7Y2i7QeoDrxD
AElp0JnYvCgHswAKYSclcjPlC5VldqAV8eJwr97PFm58rw7FJISZtycCPNT6v4bzEZeX9tOvgN7u
zKN7yj7jgF/qChSeP+I0yEM1oiH74pPvGYZpgPYevZ2zFV2AuwxEqODS1VKs1u/SX6qpm9s0Al9l
7IAa4/Bq6Jw9+wMzm03Qe4mCj9QlLBhcFsMmjAlJ80O4PK1ZHRcE7s4BJvYslImKLQG4BmbXB4/D
kFjJWgNPgUZNzAME2gsMPA6H2Dfs/xdZ9TCG6Ppe73uvq1gpb0GXB107tNQJme6aPxlcmgIzPGJg
KA0kZhWnt3m7ZWD8hy//I2deHQTObW4gTBShbycKcXDfT4Mjxye1wE8Lsx5e9JV55nHaHPyPvYd/
16CamHcbzDJRQ/UpChkaTAsT604ZaT6a3yl70+QGW/iqAxKO7HKkJfFnI/sKSp3GoViONbEMhUYu
3RvBLbLYJU9VLHDj3krJjvXf/QeET0cDcfnUvX8Yo3jv54ZRhlpPAkW03KMpZFa5Fhftp6PqieBz
B7xMqF1b3yInxk0tI8StzKOK7YQ2iuH2g96UVeyvhVTSASARs/K506/oMsNSIeSeR0U3c4KnDeRV
5BTyw+TACfpFXKHxRVAzwpxFsOlcJSybMAuAupP9kgdPIjefoJ1bA15cjLsVjSfoisGbiBRmKriI
dHvUHYZBuZhtqOOvkkT2MoIS7OCduVRoAsAaZthk4KmhOIDlbFIwvRJMhTMPTheEh4xcTUqSl6a9
byxk1Rp0tHvaE191uKBoZ/OuZQEWQ/pJR9NlR43lLSpQ1i0Az7KLPBYrpkM3Z8CtkctmX4Wcc+kP
EilVrFIxqEy4URuBaXC6BPheavzjDaBT44gJthU2eGt1ODlW+r9F9KSqu1Fjo3oqgmHUhKX/LHDB
8d/i1Ly+xLw5bObhj5HqCjOioW+l7DPxvyuJR/gIUh8ggMrlN6S2ctbrOwOESG6C1njC6OQm5Ly9
32w0U1nfeHsrv3yNk8QsXFrUBnjgIZQp6zf6ULF2DyX+rBBg8QLqYNLy0Bu8Gj7VLlRaR49H3/uy
T9LOtlRbxiuYAbllrwAWd5l20fWPN6diel/i8UoN1qApgrn0flQlXWqN9QnE2T0TnPc+ewpbpOIH
HjvjntQFA1iMzqSNabi2B6Mwap1noydWX0FCQ9TWng/v06M5ebF0F8ZIAVvl95dV8MwKS1Ukj0lS
hqIDL0b0kS9CCA/iFf5djroS5k5F+/11zH0OzV3tKgjcZroxmNhGhH9TGOc5vDfiw97540P+nvi1
JbxJXX/P3MqXma5W7UUHfCZRiq4SATXarMH+LnPLV7qzCl4TNaYFWS6noHsttVlrQRobM1LRiys2
AfAxUQXs3f9Mj8zCJqz6Fw/t+YEbjksgXFODIPeaI9pEi4uKmZLOeFhmlyxEEMmTZbSCbQ09dniQ
NMb5WUhNGqhaSPbXjMErr+4NpdHH3JWI2N5hsuMX/JvxSVkZucRyFuJJH7lQ05BtSFX1nr5yXcwy
Oz78Q2TobkGeg6VlTmI3HQ8Banv5uLwPJSZRbB7ePe0D/uIk1wLxtl34Qwrzxji1C5VrnY8Iuyjp
jvsjBXt5+8SuJ6sk9fVCOZSxcAuJba7oclFtXmAVYTik1W8X48Wk45Gx4NNv6M7zi4X46AdnmGyn
hqHv2hl0B1SEptF6BbcqXJvu5X5m+xr6kGVZL/bLQa6EMywYXz5+csPcFIj6I9GJC46sEqF0DaEI
rv6OGwfD95nlPv8lchGQpeqxyXjOLjbfWchVLT4ZKl096jJn45bV5+l1Inv0O+15be+BjRp37tpZ
XjtiJ0KqAX2p0bjhDnweW6Yn/8mz1gg7IbGyR5xmSkpOKhxe24FSFIg32QrLa6MIEKxoN/w6r7OB
uEBOmnJ7sTRYu+ThzBhcDluh3k/IH3UXzCMlMIoCNQvRnqoa4xworSAOL1DQp140mn6hbkLS/qGd
0OYFz0wldESURt5DY58/eoAUldTFMrMXdlmP60kuvDbLGIZjV7rxeWBd1Qh94J7No1f0KpbJB8h2
Dw2WAY1thJs9a7DUFUm5uoGS7dBPsi+BjMIpbmFi2YiCFhpNHXE1tYNjQdceYUgir6e5vjI1B9yq
A65tIKO18L0Yd8xbf4Z+xaYshThoR/OytqYj7+HO4gARDfwv5KBaBcBvsC9cd9ZiuohF9hr9pLnX
RXU3c9UmfI51ZRL2z/MxYsOebSBJgX2pnViD//tOfLgM+kciaeLV6P7gm31F+lgM/N6mps68wHVF
xmwuTLK6fm+DTD/GIbp12N74WUXfhyv6eeNbcMbYp5vG47xNHG+DXPju+wtiPoSNn8C2FQ4oC2qH
ODwBK9rYD3Otj0gaHiXddiWW/g0PALvgjhOP1qO4fXzQywuS2x90nA8KYumYaIx+xXF6fL5mSvhz
0cp9VY96vVxR5Ks7e/70j9zg5vFBSaoEMjmu7OVT/IZft+vbkv+HqaFvKjB+ufTE84aLwsDP+Wu2
V5kTgAzg1zAIEEOJW5eu7LO/fzDcKxF+BMqLVleTNNF4TabQRXmmP73VWlXV2uYUwGXS23wKxoSG
TUnydNFtbSpUlECh/5Flb6YMiOcbdiwBRiazyPkrC+znvaHoE4QDPZMDKNnHqKm1NfCcfZMHlyIk
g1zChTw6OAKsj6DID0MOvnqHD/cZx1BKJayaNskmVfVjTy/vF+g0uSTXBjJ9UaI/8y1ypal0S33/
ah5qPbcGL7ivzkwznbtodYwJQT64pvZ1oIyYBTtcrc8F+pfLj4PkUqtAglEaSyFzNm/Vyv1c1aO1
tM6V20eO370d1nFj1UtS+W4YHjJ0wJlmLaIRNenn5KMQaQflYFXW+f0yE4GnWjb8HRIyXTW440PG
MSqc/t5AUd/0+HVndx6XChzfU3o3b9k86Nd2kH+RR52Y85/PQV0sb+mZxBQT4T8aRQsT2Gs1jr6F
Enah2xSiIaerk+L/DW2D/1op8k1/OBmvDSwhgm/h9oUmawH7c5XWI8JWNIks2H7m5g52TxqlSC+3
GV+z0UxX1XA9etNhlyq/kXfLB/6HySBbkhlrWhJiphmOSZSzoxm3a1mYYsWMSvHMb9Ld3IrZKHna
Uvn/0hGGcXgXnnoPGpnoBZh5wP8YoufFOq07raNE/7gIe31MIKdrBwu7bOZC3T14j5fDsEWiXSmJ
OlU7GJN9FzzDYxWDw/052Wo8OCzt3D0a0hzxpmRz+cLwO6dtYF9kHPWArMZ+WFO65WyrQr9Xp5yo
qfsh5vjXr3i1hPSAskTSWLWCVzS6X5Jhdep54kuHq8yyMc8NlNK7zeY7v6pNGYqGFnvqilWBMhze
ME16q5ST31ISnpq0hUPkePR1GV3wZZ2AyhoZaaC3/Ne732KAYZK4lZpLn2DtzDlRmFOPiyTiFcBB
IcmLn5KgWPqBMFL4E1pgHzZSkvjSCG1eFzFz6s/YDuVId7lk+Djkd9NxEQJ4LPF8bm0FDWt709w8
Zt5LAXIefy7K/TEEMBR335BBXGhtC2zzquwuKMQYWdZlgDPtLf6IZLzJslf3z9CM1qJm6JI0slTY
HQyRJW0tNamcFFJ89Fgv/GQx1WIEuhhAKskY1jQUeyHS7wdqTzZyutkIE85+4L8lJLBuEfXHkfn+
Cj0CXAAGEDFK+SmKUQyAhpbjcX79hY+iwIVw/s3K96yOf4zMkhobnIqfs5XhrmCryYjoBpyPN95R
vKQXGVltjRQChfRRcyM1ma6vkTTK8Uurh5HOQPWBWIpBNeJYt7Fw3QwpSAnPDT++95fNqxmw5UVz
kuC08vFmTgGCpde3Le7T6/lXmyZWTJBgQ1n+NEFIThk63Km0qPXdmdaUgX89OxcuIMyngJHX14pk
zQaMKZmEZ2oq7VR38wD7jBKmj9JIbT1KCki1ypSfYsSUyZA+Av6sGxVuN7BKZZE8hWqohBfAQkCX
sGXXoAhHRaovQSMiLGqlzdJ2D5gc8/BqxIDezgb5o1Ej3XKVZ9C1L+au4HgJGL95RpCGNKeqrEVQ
SH2RGeZNJBR5MXSrLIPJgcOujnafgPA01f5fyipIPf5SuEqpRc+KUz+JCvylDhnHDIumVqgaSDDB
LEy9xme8x/KjJ52d9ImfMFv9hjzGPCG0qgo6IJd+i8Dayy0A5OcNWiDwX2T5UjQbsFAqgRWnKhXd
JXu2sYAK1cvgZxnrg2xn2mM35HJOFKd2rDSDcEm7FnzQBSKUkgc3Hkdo74GZIGnIsWurAagRU2gW
HtPX7rFqyCgG2wjzG0vqy7jfxYREQeY7OYpk3eN7i5afXGOlt74k4fCXuwHpHHtzojWY8davXHbe
YH/pM2wfx0cylfrX8/X8DoleR2GiH0jVg1NCorat0y851rv4w1Rhdp/G3jCn5i7s8xGm2e9GqY8b
aywJf/9FgJ/s8j0A59x85BRQrwBU0Z7O2x4ESM3podMEl+tlbcgTIN+MM8RLSEw6nPDAhvdB+LEZ
n7PLs2IqaWOzvmemopbE1qYc7DwkxV8p0oy1vhqu0mxUaGxmsHmM9QNoSHwTIrR1zhr9XB9aacnG
p9mPCebLttMLB4dLkYYZqAkZuyCy72WbcVaT3VqRUPEW8fXI49wGj4oqv6lKFoWJA8rxrXQK+096
wnIAXxWdPov59AZrLsI8FWBgsL2yTP7SBAviUsjSJfMs2xyMCEganlYE8zf3mgAtANDaJuFW0HlL
n8y9oy7Y6C2U3ZuJd/R/lFyCxaM7vhj2bGrRpVhCDfiX8s/bkSYFGk1k26eUn4J5x4M4pHFhIyp4
wghcGJEGb/oNbUQU+5+cebzELKF6g8Sk7BMgdxW05l9QnYm9CZba4wiWFo7AHGeiUbsaAsUbPvK+
UzwR3Y0EXBXMhvnIjYbXQPmY1cOzm7Fpb9c/oSX6bjHXLjAIaNgLybhNlNzCAo8ALgkLgMZm21cc
fUVfm7HfvSUbAnb4BMb6Lgb9Kis9Njgy1TJ4mdlYzU5zFU9b2KiFbyrGZw5DtlZjFVjAESpeTtgO
SVdlhdcXLYN2TCSIt1Sb8HVsb46GzRQueKb3mrjAZY9PZIk/t46MLZSEBysCnlhAVC5sxhY98KiK
ofuU8CspwyrDUaHK48U6WLk2qEES7WBD5Yyq3JH95thHQXgHVbXujsaM2eLnY1lRssgVGH8Z0jrW
NCxMU4qQs5XNqY8eRVSyVAXSlWU+bGSBKnru78vy4iXQgDe2U2s5fS4WMG0C4cq0pRsgGC3WQlto
ZkWZ1SoJbR8EdLAxCOHsz9dvhiS2+pOaGp+EfbyJs8AcMCq0d331S5a+nZH8uYf2g1rn46b6DKQ4
Ajyulr/lwwCizumfPsnLgA1HiKAfdiyRemMAJzBzHR5yxcZJ5MYDdI5TynQSeowdsxppgeKh9hFr
qH/tNRGWqi/oKzOJFVikGDZuMQuUvLibTg5zAksH06eOBXziLcMPBGlZf4oHoXUZRXni8rFCnEW4
jeozrzgtFNb477rfxAM9jJ/pbH+c/l4Q45uAl9sNByDMOEJOOTNLNyc2hWwXGYMAotJgr+01E0+m
1VcbaCc0gfNcorURGAah6ZlK7w7/8y0VTZjxbsx6alamF4r84C55Ut4A5uO0bi1PKPN+ViWyfkB6
gBnGbbEIgQuXHJJNSJAwq0SfWCwYK/XHHdte74URRsON6f+faAGxzhT+1Gz4K9QpeGrsuZGvMbMT
0qo1yDQUIfYBaYd3UF8qKh1EL7WwC6+4pf9TrXOF8Edd1IG4fAopFG6iLibIkh1nIxg8Soa0pvxY
vf21ptYJLfXGKWtj7pis6DtcpRSWdVHV2srvgeNzoKt/fe3gSdFlVB9CB+SCYWUUNrNuTw3qBBku
33w1ufXccp+8ROscf4yKfJNrOsrHlm1gKMN66LG8RZj5kOvEijEiZ4+9IBGQjXDM3PNwxA0G49Vz
/+TEmXwB+n9ivGcaAZR4QeZX75XowROWxUQCIENtWJ/wk4TfPvNAtQvP/yTDgRUe/5WyfFQQxVf+
zabL3o8+e7I3oq2lPD2xvQCrTaB/GHhOOKXZQfwWPFw3WDk+13WZk0MApAzLm46vDCEttd8jeUma
Ys7m6sPhYDPVV0gOwxJbRa9RmGZOZgim3/YY6HDzVOq96FQ3DyBd0WTpHAtNs31rwcAK45ZewAvF
G9Ghd/RqzwoWmiHuKf/EAECdEP5/zZtwcI+HeIzPHze0jYO0hNLPn2EPcI3wv8RaKdSiDrmYsjgm
aMli1LUudMTwdaDWcCMF6jHz4acl+ViGE72oU62vfErqajb9y+GMLLCPq4i5zaCE1psI36758YD/
4+drODtUWn1mVvXjb+bR20FO11Dwd8CwtU46uYT4a4LjXVz1z7EIUFeY13kDOAJKNl8alA++O9SY
iGE2MsZZaJ78MfItalJSKjnyeeGIiKPeKoFfO3b8lj1xyp7rXrQHBZQXlBDBOPWUznaCDdd7QoAr
HvtJXc+gpaYIOpi8+qQ3gpQtCU6cebPKehFC9udUpGvrzRAz2yrQPXpQQdfEH3vJ+KwT7oBq7Yfc
wZ2rwy2LH5gn8v6KZNcdW2GHh/Rp90Q15HDW70QCK+MhhdSVs4is34t2Cmf6ZQMDiRi8fxk5o6+/
SAPNTEpm20QauDGdgXXMugUUydPOlrj7Dug9/dZTsMEcF1APgxSLdFnblDzMzAZ5F50RDDlOetex
uxcrqn/EHqlhToQbdMj/CPBnlg7gRFRw6O03+3CbSwkNvkWFuj2bJSk13VXyrmv+8ONYQvce6EMQ
nDtQoQzZVsFPxtWhWZyLLcxdrGxGou62IYB62QXiMSjJmLqSRj7Jc7moO/6yrTyJymITEF4K2tdz
qjmRCKj3j4KA2XFd9En89QyioxphWSM9pMAiY4CIUl53kXxP+Luit00QvDx8lsZ1TWufd6SkwkCr
bV16VI8DuHHILzrjiCXZdCdt3vCuA+HtMSZ5Rz+ptAHZkhpNpDzVGLi3UPAolphkJBTMi9yOX4RZ
mQDLxBo+Rr3s6gxpehWidnQ8R54iTuquYRvL+VON4EVgOlI9crh+Jx+AUEfia/EPo/qHzd6DtO6e
HkA9rjY0pGi7C0GP2UFAxi8V033NIU14KMr7buyAKdkvzBVndzjIoSkKg+B2nPskZF9VwmYzUkO2
vhY5f5/a2qBJOWlLStYu8mhd+K3NSgXBRYK2fXvsaxeAnuL6VepreP5nRWd+ytnKH9hP0Yu27Som
VPy8x8Dwqhl2RSqGtul7EF7RNG/wyJ6xR/X+ipHvtSSbdQJoVNZRPZViPoFuWRZWdFyWZbhh0ZhG
oBp8z2IcNfjYEY6CNQLv5XSbhezHS7ZcRePyk06PfNaaru4RwymeibqXYMGeD8PoQ7/ZPc3YuWiJ
ZH+er7C7UMw6IIuf+fEkVRjiMnOGTfgtfuRmu0j3T1u4zZoRY3HPtzvctXemybJt2ot6AF9S+/S8
LBt+oSYvHlQqR4l1hOnrLCIS0yH+QWK9mzb14cdM427uvocFfnpG1AZjR/lvzudq5tq33HFK3anN
ZWaIDwXl6ZOSYSi+7W7TVBwJfJiYs5msAqqGLC095f9oaWbvsa5eJjunb9iJ33gDABZTSm38V5/8
vJVzOEB3dwux0312LcTIg+WmBha3ETX/YvzYlgts6SsOF3T+1BLtq3Hedk4sR6240p4geIRNd5Oc
t7JqpBbuRusEn12GXGyvdrhGV7/OBpllQavVdOOD5xq3v6kNtNXdZUrgKNPvLfYF5D3ixKrsQo+t
zZ74bk0VjD61q3WBc8HXiYyHOWOwxn5JEE7X6d4Sh0oNlmKA0rv57PBpVXQ7ZB2/LdEcK/0eLNu6
di7v6FEApL6CoFP/4lHSVlY1PagePgc9R6Je7wzZzt6a+QBTrkQWan6gt9WsSJXsE4RsrKmmkY4B
CzA9Tu1rTJRdh/xEPWjtEmqCzyCSwtMY62YAHPB/Zv+OmcR1AzhXElIljDmqv/SYw7kY0kwLeTH7
8sMigCrlNDhiMIyqLtXZk+cIlTb5s0oZMFSuhLAWpvFWk4Ldn3dsVRdBmkCYbpd8/OgJP5pwgprB
GNkRdtCLaa+vjEu1ihkm0wbn6oX61wQBmbHEEMU9fbnQIqpqFTlpkOkbUa5D+ntZ1OGnsGwIlkFp
tYmpDek3pj3n4Bzv/W9TpFT3ILByI0AhgY4js0MWrH7ICPiJ8ZQ+ZChLjSgfJmWwuDNE+TIv0j0p
YldDCAdIiMHSHfEq5NAc17+7I/7AY3AXNHvRnh44ImprsAhpDqUyGnjkqkniezS8+ecUkYL359rt
Va2dXBTF1CyR6Y+8qk0dU/TYdFli4omYbLJMEJ2enHEfTDq8FJkH6UHsLC9P/QVQFynnsqKP2NxB
iwWDHfNFgPK+KK7jBnesEiC/cR6n7416EklMSIShzB76EITRvmuTfj9q6JY0OUp7zQ+tikRnyZkd
Mqs+hPLDqR7GuMms6Lx1hywFD2fQcYkeW19xXxOWaUCdjudaRTTd9ZgTb1bLbt2PAJFMBFnv3Fqg
bwehiQ2GUZTRzZ2xChCN1W6UO61wtey6SdvJHYgqgGriDb0lLhHvT5OR+14y6eJk8jpOEmQYCBkK
SEhFe28ko+zxjfqgAi8NKwi0BYxQhVVo+13dLtt5IuI09NRiy6B+Vmwyq/NRVDeQVNDuomR2v11/
ShbSCAAgWEnTfhxyI3gop3eCiAMUy1fsLePMkO1NAeaxrSv4XmiR+qGxN41YeupAjty53SETjCO4
ZNaacg0YIQ+eImcOnSUhlXgodn4Ubvdt2cDOhuRkUOZmHnSo0b9Lg+Xew49RczKnTi4+3/cgGabi
622HpjPjwbmndNkyKJNb0luLBwMl4moT0e+3NTpzD5JFhgBKFijhWyzG5BUtzonIFPuU9uXGJMp7
QbdTuaRvERj6MOpFcYbAMTIWREIeVJlvg/jbx32hgWD6c5J1WDNEyENzaTYOZ381K1roOjqJNmJu
AeMV0u4KtaRHSDnu9tIDxSxnGTVDIRfF9jar0nqW6zV1PRTIlYOF4fZLiSY+P54GFCHMfY7Uj3li
eowVUoF6pdQsZuXnayfCTfjxGS1axn21AeyqZhtFPMykG97GWTSExtUqyaFicwMThcFeya+yIhVf
w7WyR/ur+b1oV4jpx8q/qJpqI0Jtd3ew2FVi+pdloCRCkR/hr4vPDZmk4SvHLhaYukId10IyU84A
mE0/WJdhS/HeMNb/1F2jL/X/UVsmoqqmcVP83cwwrQ/4XHhYCw4aVbM10M/KPjduQKBRz4QYp9WW
hU4rFIxAiGFvdx2JLb33BUU4p8RNzKcAYF6Rjz2wv/sTCQpq/jy/p79KzMwjAWU7UVFOBNg9qnlu
omEZZCcwiVck+hMjLaCMbo394divnyyvNnytTsm6+fIuskdoLBkp0p3DmT8uoPEcn2NP8CP31xsI
k1S7UnJNj7vMbTFpuvvJJePSIR2Qo3cXA4NjEp3F2g4t6Es+AanfttOZPA8VCuXokLiuTQv/c+BB
FlkZ+7ftnEcTElg0FUQslX37q3sCST5IWnEf6Cfq03kUB2VRbpn62thCSgZoWne6ePiKiuc55ZCo
OtWbahN8NC1kCZoIB8KeldqEBy1lpyrCw/qbuXXgvIjHwxO29rLGtQtD6dNT/5f2i47RR/41qsRT
hGMZgBJ7C66pTKhqbuKS5/3noTYZTAEk04YkqObNfcPogZkM6L55zYdouIIhV9T29MmMGUecqwsi
dFb+Cm2rjuJLBdwg2tCQ2/5a24YUfDEbSi56Dhm1j3i73tvBSNrcMw0bSQINWC4w4HUgjZ51fR9Z
T317dtOQxXK5RRbxRenJizoH8yzNEYbR3VJSY+UIgvczK6L01r+HgHFIr57k620qwyP3SSj82x2z
X6Qd66S7OLC53VwVMb6S2S2VQ+Ui2TGY+HaWr+enAOg0VeZ4p4kfHywxpXftMT7XiToiNFs/u44U
U6RKXjHGHemfzQrJAQxW//u0lnxEetxheH7MZV0hUDXRgP0N5AAFoabaTPQ76ustyrQALjuqTqXs
9TY3OlizBjQT60q4KlKvyPXT59Z9egIBqZHzZpiDc1GZ2JruKCBAaGvWvnHXlpAB08CFtoYqYtyG
qqJZ4aSwYKC/0/ARk2YGesQs23dS9PhqZNVqP7XiIhLcBZ43zIN9nW8XQD8Hd+HxoRp95eFNums4
9jC5ElkbVjHuAUcZt88yDXZFyfjI6G04c+q/arrE7wrtlDkfYUo++Zy7lRaDF/x7KWsMGdQSqzdx
fJI8z+W+5F9UZoo0KCpaSyADmSOvOx8rlZ17t0vACMLwCRHmk7lvZNl/9I45d6WE89vsd/4oozHl
g3zyTl5NIA2OzANn+Cb+gnL16Rq2H9IOs9z8f3rQA5ksimb+iOjwVdcTSpGSCL9xIsHQflwjjBa8
4nJRUA7jyI8sZLZSRg4niEvo8NzZtOQmbKrYGF3qQQplBfVvSOQ0FXvjRtVTAj/kYHbKDGXBxwpT
70e27PZHtVnqw0kqhKQJqHQA82rs7FboRSZHPWFq3OMizZ2DtVMVi6z2TC9ehbl+jVei41Ov385k
zqWnyyZretpJSUAgWwpSIIUj3elMWwspNdbXGihVQ/g4Fdly5JmxvzQDknWw07hmKOVEH7Oj+hKM
l5iZfKL7vOv7qs0WxRuBNhkDHgECBgaCRLxnbHC51Gx0S47crZ0/wClPuMlmhieRtuSkAg55UrmI
82Y4HxgOQfYmbSwwx+SwYlx+QV6NLx++NWDFAmnjD8JUI9KqUhlGukSdkJM9/2kMxs0ql++x+UBT
RfD9FSxmq4byJMsMzuq91R9S0gLqwurR6VVEwaUPgGR6oO+rUCVQ0dy2mgkdgi48FL91fP24AMb2
nfkf/v/o7838wZz9AKUwOPq5c1ud6wdw0qshjC8IObF/h5NOWQl5PwST4GJlk8HAs1DBeUJITAqp
nMVI85FTP3uGBfZCzhM+MPRYgrysmgIyw74K8cQ77vu7euIHF4lW4vL299/beYJkSzYUypydIVUA
tDDbb4RTimYf+w6k69JV/YVVa+w8JLvgMWlgaPjqeIl74Fzx2qv6o3KEkhtsey41pvMaV2uwCkpo
yCxwuuG0gKKyxOc5YpgOqYQ0/xksVAkx4/mGIsrsX9rpuBE0IcLGi67+pyXGdzYKDZrNzk0OcZ9D
y/xSn5gAM/Y/1aw26DRXCSYrvTcNW7swwfjrbxN6VilM5VGi6jwaL3L290jS27ytRD7F9fVzoF7A
3nOLNeUej7hGE5gppLQ31HTbrXJ0WawybA4CCAZfCM0tF5giLfifzUtMbMjyIS8xdV5B8IL8UM9W
Ofxm6zsFNjuiTFizn5q6XRJ5O3ZvNotAuPwKnAjtxGs0a2BJz3UJCOzHS42pV9thIRR4JAZy7YWr
12YaXNg97iOXa+Ug4TnRK/ALbqEUDgbfH4iw2ef0OujKEbHGXgfZtMVwIAnciS0MxNhWOu1co3Gz
JDL0iHXy7n+Pf+DVeBZtZZ1dt1gLEOVb+zZ7HnBGL6e5k2N7urJLDrjg5gi3yVNFCipMDQ3wFLuA
q1EV63dtqgFxQhPCc1MCk/L32K4XKHsh01OzAPOr0Q9HUiOUkUKSY71++dzyID8dvbzgMoeVl5t6
Kr4a28nOl5h7lwN1ppFn0fX1B65yM2wXGFryi800Q0kOPiwB8S2vzLqNQ9L8HKk8chn17DdqOA05
WS7N6MYfoTEuxj+0CCrQOj7m60rTozQgPvjhFGOwZCKBO2+3rrLbVOdZuuG9n1+PyrvWDIz9WMUA
jtVHSOepxvxKtlAwM4UiQGpErrxexzutnGfUKfxep+rwrvF5kZblzfNuWqNfuaavFdDdT30H9P1l
F/j8wIP2KeuypjA6Pjo2/NYPk91DV/1q1lYMXomzJ60yhmwDRZl183WwGpIXoivOHmcyeDSeWuED
rkj8kCsgYv/D+JI0GGwENL7DyLA3RkV4HvFOwrb1pX84fqiyRqC5+iPRQ3Xpq9Pm9FncVU+YwU8Y
Hav4DyG1+Z1NifvJngujgIIu4tQFl1bnmgzKItAK1R71YhzFzyQh8rlXSkyBCWCLLseCFcJ6cVcQ
pWLWRpfaZOD+mi/Ys7aWOcZU9+XMR8xBG4q2KSO/EfMcKqXW9jUFJXraEcg8oa3Nl7tMmWae5IpJ
w8j2t+aF9M0Ell9pHG4JQN8TVwRL8jSusjD4HVCbQR6shXNmS1VFy6D+AU9kV7tC3xbErLzBvWeg
cbM7DKauosq5Q2vrMx80UrPz2KLULx35lbXgzFeHLUypXNC5nuAO4CS05EuPcCOJnNcD9AsL09Jq
Ncw441W5ZnlzLIB8oXkAH327AKXQ2LeTmKPNVd7M8jv85Cd2mJWyuOt8w/AfPO9D1H9NTUJfX5Xa
oQ0G9MPsWUdcw4SKb7XRAe9Sw922l13p/dDew6j9X19mlmNkP5kTllbU5X1J/4lMzSYPx/D32ac7
EwmdoZqiH6FMnkTWcLxfG/rrmfEGOQl12XhPBxQtNdftSxCgTDHoPtxClCc63tnG/LnDOaLqQGZz
ipUTeuN6f0fzEZf9RI4KwJ3WEcONTl1iv2nVtuqKWUWVHUILJOIiV9Cc0YNIypZLBGlx1doHaTmD
InTpoRdd6NUegAddODbNTKelY84i6WuziRe3iwhfSXKLp5GGVbDsyDxm1EsAXBTEExKcBMeQ5J+7
CxmnDNyhVNASXOOlB0IKnxxQ2zG+7fAzBpX1v4Tb4KTyjYAB1CoiIKRsZO9N1pGdifmnNqNnG9tp
hPRAoBbwXoJZ7KwDZYAGoD+/eV+qZ2Uz5x/4eDKxr2mjFbcSSbEjAS9ZIbiRWN359pVuEe4pRU5L
jznGuuEPZujpxNqta6g0/y37Tl/ACMVg7WPKAxkAcce9P/iR1TMk8DM9feZg/4eM6Ieju/P+FObO
KhAB9P26fIrW94q2d/Rywj2qMJdBGkhu4MwWivW29WcN8IVBEchuQIJMlKb+gUR6jlkZ6vd/vFcu
AKbozWNVg+GhVAVMfBnx8HTO029G+QBCcM45wG5r0EDrhZm2KKpjSEok3uQ9nVr2sUQRMw+wkZGG
kkTwo1KXnHsyMSCK7zDhxA4YE6cUuOtoBOquh+V+RbbSnewXbbZliKgfwxLdO3MckPtyRHyTU0fN
uEvVzq8PDFiH5zhLl6lo3p74YzSuMLiTqhXVqP6BjS97dACAtqA+0crZgtMjfiMwjxUatv7uwfV7
scrXzSwDeMx6E0C3pY1m2vZmi349vEzMBqRtiVvoCKy01fcEskskQeVHZNOEdFIW+tHy1siysdVW
hKE1j116kpLoKMCucqH7aUe0Sra/PPrZM3yqpd2LcyjVOeg9Pd85A18XtIcZWPvQXmxQFLocOwDf
ImM9Ec6AiW/j3fNYRzU3Ju5CMubKVDnxPFa8z7clMZclEqaRgKAAnjnFdceGdX3g0v0pDDjDqGRD
9cc5aNYmx8oxLsP7Oe8fc+/jL7g0gNHFL6nlEv8EagcNi22lFPzt5wZmcozWwbVudQS1CHypFTaq
0zKZbHq7qlIXWF07NbLKEOoMgaLq13y4S0aEWL9bJ5yibo3tRjLUAMtJr76M7wsSpXAN3JidfvZw
TBKPCSYB65mKY2Sm67eCb3c4tjG9i1PRRCzzpK9G9vrzpwMvGXDzHEpuJ2YfECFYOBv/DHcJ/V7o
N4zUhXmpa77pX7ao0nnnYUUbm7YLvrt3ZtWKjSVrB5ikziEUU/oHWgyypoEQqC1MXc/e8c7rYD5z
F/xXD6bQgBpbThjodqZotf+7pH7xb2qT9pft/8ZwWarFMfuewPLlONBKqKKbrTEduJqoBPe8tfm3
s6FW6+d49gQ7lZVHQlNbFQGvdko/WrNTxMeC+t7O1D1v34L+S4a6QuViOO+kMpkHuWXDSurvggc5
AWxP/nQJ1gCkE5B4GGI83aJtF/UvhtM1i0uxGzutaPuRrheRp04MbgdHXf5bBsVFWL0BsdJU1RT4
1xFmxqiF5PkmXTmbPK2GU23T7TIaukQc0kWd+9nXETH0LWTzQv5MHN9fQhK2MYQF7n/WsaRDhHdj
jLRHm9dpOYLyEPsAn5vC0+ndNbIGjnS3G6vRZMTsmCLTeCC1R62zpJkHvyowD0LEtK1yC8gwc96j
/8XJtpwLuUNLZK/gZAAezQPtJG5o6czhMWm2wOZBP0pbmpYi7aSouwW8HTzPJvz98p8QlHMQVVPm
a9Sml0d8iOJDBKTHEY4U751gIlArnrtJgkQLOAKew4qLLTgTS6gbiUIlUziH4/W0eN4esseOqKRT
c+oB5vA36jl9nklKy9/9TyF+g9bKVUZd/6lD80rnV7T9K77jzsmhsTndwtI0y3JdVz/vz/glh05r
GEzaJuciJ7zplk7KWOXB6exzUKkctcUQibooZsMTb//F2grD/YodqPKjgpaI9f44TSiR8nUp/F+T
wCoxHeO5qHKUEh7aFEvZxhLHh20Rta2doAIgzPmWoVCVG03eZ2k+eoqW43KsSp0WLTf5nNqq8S74
Bh8W/qJoMV+VOrcttX10reGqWEaOg+TWvGlcrdASyu8nX4pGKffiOFm8HH2iKkAdJ0VC+15ICa2p
3I4ogNAxi06kRD62Bw0ldU2lgMX3oO880f6xqFwdqaObcw9djHKEnBHa3dGaT540Ibk7t48MXI39
mRvoVp5HdSJGhUa3tS8y49jFCy0Hbx6Rnsb2Ty6+x7VWxHGKN2lWymNN/m04HVXlOCKzh7BjqmY/
qEcKS6Irsax9AgAg2z1fDLn+R9tjVhnCQMNLm5qIN/opDWO5i8/7QkBxQbkRTeqrF0UEUS7hwGg/
69z1/ep1G2OR6w7fn/Rm1pr4GFkvTEj7smk7JmYeYU+XFoqr0Hbgo0GGdBkQ1AkSqw3ek6CpiE4N
Y73Zl2ymtspqdO3b4axHDX8PHyERzzFR1LbUwNyIGb0t8Sjbt/soPJB1gKgJfdpBUsVq6qAtrWKx
giMUJoyWbarTRrdT6xeSYqH5WmGKLaWyqgKrOD1F7D0PKrut2kgx+JQXBbyOs3ILY959Ks7Udak0
ZA1dqkMkTM/ndmENuhqaLcjBj0EJPfSFb7TADDBbjK/vVjnNrmOs9PtwQ1yBwH6J9qa+DFPzlleP
Z3hnb2KyVbjRHlAiWuELIy+tLniUFNHa0N6b3ZSbhKTz4SJGKLWyDLrPIIKIJSzhXYMVXZGcr5BQ
I6qGpJ/X+DGBANfBlWYf7ggQGOcT6RnUoR3zuJJaIwaMbCruKjpbEm/tkH4JlGGPxdwHXJQc612C
GMHrFPmMKk9ch3n1mGtKO5SL234ZPazSdAnfXob2E8D3sl/mwqo78w4cQVP4HZH8k5WqRWemdv/B
nDcYge3EJcA2h/Za6/FMfa8v+7bIgFOLE6xy1J+f28TnMmT77OyirMwi0ey822lAJWdHA4aPcX9k
U68q2O+uhUcHSawdo9hC1+7PMojzABROeRIrNpSE8/uR0/F+mmEATWyfvj8+nMW2ILIXcIumgh4O
/RGWUBZspnCmligzseQhcdFJrBBY3Zko4V+55S3augnKkQD6MQzWDdDPE2oOQXxZwc+IfDs6Mi9r
KWXipU8a0th6XOzD2xEsHlZVJjMWHN2aB1x2aZ18GqaJkKe+qhbRcCgcHrF0Tlqb4n2ElXMzMyvy
H0bUQ3Fa/dAPRHL+sTd15io0KkCYp2wiHYSmaxWhIE2Ho007KzjASSZvYad/Qq6RXfx4GBpURm3r
4iQ5SJtjLSKrOt4MNfeP7r+ysVPO8mXVaIYPKg68y/FwK0nkgc534t19kITrmLVm/gkE9p6RsNBN
b0A7Sc9g9xykaLcIvMU2XLnR6FQglaBYApKP/MOpX2h5oC0x5hSmQyj2V0XLWcWFavWQrq2OiZyA
spAnr1nSxIRkztaVJ8iRtE6UIAOOXjQFC+E1L6zommiVTpbugXe8gw+T2thZPXNv6b5Kax5AKiF7
xSLoGr9l5GcYTI9beNnt89P5gOSbOJd6WagH3KaFT85hDGnEEG7uDYZwEEQuIgD245D9pPxu6qSB
sfTDc7FwAR30TUHFb6gxaYqR9eDQKNpUCl8ayQgQAt+xwSgq7JeMQomWXcO6iLUCcG6Wp8YrJR6t
Xo+ijRMuuNS+A8IA1WBaEaGvUC6SPvAl20jGT1hzHZh7OLeJMXuSTzt+8+r50Wod5eOfei3DTXQG
zExz5eVSAH6BD9xczAdvHQ75AKqKG+5xyX3mhoZ8s/YCSv3+YmNV6YRSfgugdCetjg2IVFZNLlje
nxA+5OPgRch3+dcyTp03VCTVg5C3wc7kaEbX//x4fkMU5bR07gskSrL3jEHEB9sqKXyO5tJu3xwm
R8fvVatrkTzcP4B26nwEDzuJVu6xsmrDT5z3RXI7DdZUA1vQtOiME7QnsmNzOVtU/lSEJlVSeOO2
f0F4Zurv4JWufIsaDem0lH4qE1brG9PS6U59Azy2jmlfi+yo0QCtiulmAeCvfhhM7BEaODLEf5nA
/maUNhQ+du10kg8Vz76a7QvaiveE4CDKHLrpAsD59T8DPqBuAiZskElX5PZZSMlA/xgncbq4UpFK
jRBmHGNDHsLtEynxWBDq43gHE+QkfUxJUGdliGUJUhkl45gB2SUkcmLOnTY0ay8SaCNxBmnVBjfK
Xvd806V5a0gQPTWHn+o8T6dAqgk6yeSk9Jf6rby/aMFbHknGdvH0/4KYa7k+WhPIcU0nJRn6RUcP
AX0BNY11HCC8aHAzimpv63gljp0EKYHHcPoJbJ/MoJ+34LhWHMwFG0OOMC1iSHUAL5cuqbzw3DxS
l39xuM4l5S9q/2zP6GflsxEzYlJy2VFb2bWe6d4DyOKC9hRNf53hi6VjEE1LA3q05E+EQADrG6l5
eWfdR7VHe9M5zBlE1QbUw51Dl7H51oH/QuBQCurL0FHU54HsC+hiXVDNZqEs95IWddwsq5OmpFKN
v5rIbLe46dboPhrQXheCj0d/nDgrO5kmI4m909il9ro5qFO8Sxxul/NjOmTzVO0T72XXFLPhrYNb
yczj81hdVTVjvUpMsT4dXs7jUVmUDBvaFglh5QW2wxtwNQfr7F+4rLfVymNo5PgzoIFX2kgif1Zw
/PXw0RclviyBwLYijxx+86tSMd1ohxopBClGvO4jgK0wla2u0S+aFAcu/w3CDMEKuQZxSPCwSaty
NJKfxlM//TxOsnv5N6vBlIS0z94jqcvI5jBNJIaca7Eb+ICAAfcG5DhdIxsY2uRliCNE9Re6gnjV
5pxHgL6yQ2oeZ7zbGRgd738lMnrMJuEbDGZIoyHCrwLS4zXNYwUH8oeqQsykerGAJuA9Pi8rKVll
qsBIljJg6EztvA6UA/FRWfRZqt5Ad2KroS0UjcQTxZet1kSl+SFhR8vVWp0HAigZ8MojzXi+t0SF
iuLF+I1vK1T04afIzHfilVlGjlTbR1H4ywC1yS/F4D41ReG54SuVU2IdnltmLinUtO5HQ0QT0OaV
bepXShOs+GulyeQDKU9zB/Q0sJgB3QmtWIviSoq12O2nJITS3HMF6XWZda3uMX3YVG+rmF5jGKXZ
ZXptzUDvjNdynHub5NmZfFjMGPiXRqShD26xfyv3+Fq0wcm9SEFqZBLcPa+Gvo2RtuO0eh0FBLNH
z0RIcnHrfWZAPUaoPe0hVXpMkzVCB5785Fzn0olP88eVQMYpY+r2Q/rL+lDRmojcqce3Sr1WL059
DyQvGuhJZAbjcZdRkU+B4jqAORQ5R2pIWJs6ICiq9Fb4EFVGhyAdu/5J3EWwgELlTgQ5MjwZxpyc
pbMfjAVk2v4DJVSeUrWtM4rT43FIpGjI836ZOYrBUjUT+tqyanG9M0mO8D8YUPOSt8bAJ9dpasKP
gWPQEClAOiYodeYwRrFB7NXVZGfq/m6en2MKPXSG0ZazLymlwJV7pO5avM69F6QxFifSUYNKvZnt
krs3TuzBI1N29MIafOfKybcKrprgjbokn32e7SOLqG2VedogqkWQKYzf6KI7LiUmVpZv/PkhH7qO
C9VrZE5znOhDkvY0T7Gv+cahXqMqKa/gxnAD8wgxYTSb1nhrkn8WzxUboqWoaVNzkFvYEAvsOZAk
eWd457HrfqHNvxJ1iUV1h8aoX1zIdCiwmSVgN0mIP8BdEHuChnPz7MklSsm9VQNadR5xVpjc3v4B
X3lhM0r2LmOJW8G4TuxlsjChsdRf5j+wI3qucOxuLRHuONkn/Z0psVFVQq1w5Jl7lrfXvVjs52Zd
rbsiWcBy7ywGDOtEozAwEYTg671O/dscmlvHe1cziHTp4IS4/WJgg2husDlxqFQhWl10NMDr96AE
on0G4oE3Kk9boyrOSm0wxaQ4CcRbu4nlnxKTmIjZvbwVtn4qHdDuBwMMAe8IyDVODRvFJCHiSCmt
HaCanUn2CoDIrrqsg5uTOygTWhATJLjXQvSvgAvSK/jlIGjfdr//jAbDg4BwPH640695MqqiMS8t
FPi0uSw0k3Bc+Kuc8YDCFMcnHevP0bifBCwDxHwzPLcQEa0fsx2sjZNIcHKfbSTDsGNMR4cM2Zx8
q6RLQv2TvraZi45GrosXOC1J47YL4j4mgyF2GsPYS49zseWpAS8/KCJooQ76sZT48lmiBD+X8G0x
Wt7dPGltK/Iem6c0u053gauYpFdj+BmIz4NE9fVHg5Thdz7MhMrkNBHbRDPKQnZjeyqxEg1sFkQM
/aBKtxPCgPPOFnlKURtyslF/eFp/GWft1I1zQRvCtpvmWqoRL6h7QM19/vzr6SuJwdwyDBYNKMQW
TDaW1lrhnHG7M8F6TqlXKuR7E75t8uwZ4sVif15/20SP/pGNE7EVqkA3bmdA5ao4kkS5FLUuTbHA
baTl3dO4F8tgq0z8xlimumK/cEO2+j1+ZnqpJYbygpNR1OrGq/utrjV7YdP6hvjgFG6oWi9aeQHb
FL8uo8thTIV32mAESobddhYAOFz5KCgGscw9r6nAw835+msR1uTw/dap14qGvSIgydREzqPQLI6T
TAPIFltwUf6dSaFL9tQj7ZCHiYssNxz7eeWaS3ZJ13nfjFLzdP8ajvEcH4M1H0p1jcNGta7c8NqM
gNl0Mh5IHsN86/Ee7pMYPu9+8T3CiVKYnfuTfWBeFlzfgtx4Er4MIRs+FebTBZnSRaPUyuvdvpTg
8CjfCltQutDOCziFOXME9FxBbLLp+1gWpY8WDcZ0aZZL48WeOMTTBpW6BUpe5ZTNijkAVxdskAAu
mICFrwGeW9cWYOo+5vDoJzyZ2BQAu1oNkAtSD+d9Vf6hKTr2FGA5M5RQTg/dhpLZJ0U8AvR5K2gm
N7NuJYUyD7NUt3nYZ5EsWrHNIol3xXRCm1jwuEilTV6kASnjHxy+ldcwTLqI9AybZRoIEoXoAUS/
36ORc92qlPx5zM5KopIu3JNqhLlRhF88RWP3SGmRrHieSxWwYQLxo4OUiPdys3NNDSTvD9IAwJWW
W7Zfcanup9k1Qq8smfAWJqWjxn6orLKYQSVOTWo+83fFWf3hn6SBVj82qzINeV/S4Tkl8a7dkYlP
BCoREHfetZqIOuI75lpQtjFB6Tcs9yEgCa8+x83RqdIjZn4PCXFwK/yqm05k8GLxQp0itvBBE7Lh
WnkbDbtcCcEn5IGTnVNznBhxTrH6v0VqxrrPhOileoy2rCAuvHemDRk01K/kAtmuxe1Bny+ifNH7
b5zPXEzeuxtUFPkY3hocFlHNRxpCfm2J5XOnRTdW9RkfTGUqgW6Odzt9y6VER4AGkTnP3jmqQ9jo
V+0q7p4t2ucm3GIAI4vzIyYipVC1mOZXcbBMvZfSCXI3fTkweVOsG3s8FU8FZhHeV4sOj5DLzEiL
iuA71McnbRsK28RTLlxitfmnDhjO3LbIZhevR7KFTiEhunTVAKfJPKvD5aoAOV60cRbb2n2M94+R
0d98L2daQ0x0U+N07kUJpoHZvGVXZ73fE4REvdtGBp3qPfzCmMfGbgFga8cRPw0y5qhdDa59goIz
8rA2QqdNoXeM6C3ne0eVQDCNoZiU6H9XCPGB0FnUkFCJY/ziVWRFUx3jdsHVaAeJNE/Ji2BiyigX
HxMnKstws7JxignPT6f96p33vnNpH8o/aIAiwE215bjE/fr4RDzQ3/EDoapUZq+tbm/1OAu8YzkK
2z5W6/U7GfO39jemJWaNJMrNWXYyx370H7t+y2G8goxTENMxrxcpSpmKdYPPHiSU1kd9CvStwPri
wJ6hcjqvucKE88XedoU9fgW25Vnrct4TTz5DmIjqBFFATf6vJAx+V3eKzIYpP0gMUYkRPMY/oX5m
qe0kvuhjAIDEwZoZs/bhspT1subPvpN6Aj4FT81fb9DHGsZCyyyVR+RTPtwjVAnqlvWkwpe/LorH
EN/jKt3PE+1Pg2ws43sVjOoy4GNXjIqnZTHq1D2/REPMaYZsCg1pcTzoSZIsQXx9P2Wj8iCaygPI
jv/9HWx+zBVwUSxvkkYsG/FXa20LRylUMTt0s4y3RVRPcDnZ4JmjaLq/ruoA+fktGKbUaU6ewr1Z
hYduUW0iy39F6FvAm+epGzVAc8KgbqqSrffDILhfy/CYy/JSFCXxSSp+L751HeJBVCRCifo7sNc5
ou2havBip25z/T0AeIJiVkDUYCdlzFiBOW6Pck3Kvzl1uIAs7vqT3GIbKW7emymgZZSt4xPgi5ve
6zPqkZfn//b2Q/Jxx6cVkxKu0BBwd66ixsGCpa1yQsejBDSH1EIrEOSbWZNTrTDOZu8mbgNW5lr6
JLmh00UzETL68K32NpZCin+3zqwbPLVfARHOhQskv8VNFawxKPYC3d/tgP/flzBrKFQO3oXYdoD8
BWSBTNqg5SWrGp+JG1b+o96aY2TLGYcaYoxRorNRdFKT5+rYOtxJl40dob6WV2ErH92ePUuQupXs
3g5xyh+Mfe43K/DbtBwunbLGfhQ4/0gldTXQZrn+F1QcSKg2ch0JztyP04Hqwt0vdKOUBIzLyPgn
7+f+Q6Kap3p9Ym9P/qXq2XKW1oaCd9E8oSWWTYfUCo7DDSLIHAD2Tr2/NzrvsTlqERMq/g0roZDH
CiHIiSf3l/zJCVsisCdTOd68qOfy/xgrPBHn0z06iuLB/X1syoYQSTenNVw/i/+zyWVL9G5Pm14Q
yRidWNWYLdWdDtdk7a9uOZ9oTrGBL/5bk8eIRHkHr991WpxvlJBkNvaVd2S2EBJ2ZWx7NcXBVRvs
dVdghD9inQP0Hvg4nleJGQ1iU2cdw33A7z0YXU75zbeM5CPpe41SLiVbTqPGGFYH1DFVR54AyDgk
3DGTyYEdS52QhtERMX0ROrm5/KWWdn27VVJq2fGBtPsB1HnHDfHIn0vnw/Pax9DprXgBV++9Ncxk
fAwrHo+XFsWjcViE9i1ySx1wUq/S4VUeeSFpAHStMFizd1fkieWrg2jB7Mk6ZmtRdbnhk/yShNqq
BvUdRa72VgwvekHgnK3ihvLNwy6ZGY6Zt4OHyotEeU/QCAO6oz+suT/k5Q5M58W9gTWBKbPaRQiL
UQgcRR08/P71P9FP3Xj7LsPKlt/30w+/gqjz0ukpauXc+Pj7Y9ysk9FUNE33AJhjLTemx/1vf6Jy
cosR3uo48rggnIyHnkHM6FAwkF20HIDdldHGrq5myAO+zA4OmtMuXUvUIHYFVTFyJjDFAwWjAebB
yaIUMGEpR/xxHv2bDByjar+id2CfxfCU5GuQus/LRSiIexH9Fn0dqC8BL+003pjQwxSWpkBE22mp
IvsvkjqhgaBuWgrQnku1eg/7PCvzFmG2QmE4up7Njb3snrfrp2eTnP3te8tg8tnEVSvAKU05Ca/+
30UDsF4QYAnwJZAhUlQjYIasUxH5G/D++6qFIaF6JpYxhHgCAV8GyZ1L2bW3V55DUYOxKcjJDYVV
9hVqGQpb6D82tJLF10ltGZ3stYo5xpZtNwUtHfeQn4wUX1dPyKABCY8d5B/R+FIikHuI7pTAEKlL
xN5PYsl0mtVHx7+B0H42tXODLOnCrCfasZq91uM3U3ljxruBKYjYScSbkFXDlWeLEgQbIy4cJ6Ac
CXeNdqb036Pw5pxbY4dtH/2Nd13xXO0gBSwhG37dNFYaWSjCCkt8tP5ZtjNFeUEkYnwRqP/ohgZq
AJ+iKmgrNrd/SYjnTNuWcGz5puDu9Z5uStZSCtyrNTobq4YdReNwtDif8kYJEyStcdh2ePTS/xch
YD+/aJ2mzc/mchnD9NY8PqtHTQG405M/Yg/3WLfhNr3asd5kvD9m+7nciax/YOmV2ckJdYBEXqld
gSFAfZSyxtCI0UVqiuzgMqaNsX8bcQsspyO56C7FQEWzexa75IWRpIurY5Mk22KSAVtH0/Y7Z93j
erbSeVFfnoYO1djh//n7gN62r6dKPYTvIiW0CEx0KBLf3md1wFR8GC+7ok9zGGBAgvAL2mJqIpqC
n3Eed9r26UEduQ8Kqcka+Z3OZENZqRfM2ceI1sk+SVTWv63rVD3RwfohtJwBWCDUiNG7a45A/QsY
BWSQkSh9B/sEKmzkplWtKUyyPliT/mSmFD1OKtpTNoiHAiqP7I7rmyB5V4PWSBWYrNE5KWT/pK79
KC4CVjjnePV5BhkyEn4xhI1y0bHNotN60ZpyHaOyn9G71WqaF12Fbbtc8ca1P8JxFyX2oyI660k7
Ek0XtTyi9y4fb/m1t27I26gZzFiDmNuvO4+mT5nNPyeBnRJ9tZ6Gmuhq0PpT3lZ1IOT9kTfDwtjK
XsgutvCgORIwTx5d9V4md33g9I8apq0cAxJLhaM/a5jc44VzinlzjizTye9Edruh0vkXT/A51nOk
KRFlNadyjpMRKyaivj5yeLArYtwbFZ2JGpjUgCYYVjRbrdAoE2uZLiTlhN0pQ/XQAPElLpWDohPB
2Sd81RE4N+b8iDj3XRwRQNWuhVbk9YgGADP5K0JHgrxAIbDOrxQsHPo3cBPaexXh1OS6l0LUnpmb
V0SBtoit4TVp5DdAYwQk6xNntX9hSj0u3R3KMDkoB+x17osHCzLzsFcvIwmSYiRANeODMvms2nQU
7OxRajECClzUaUUZobzOqSzLf0pXoRhQ9JN7qBgouVTJFRfGGe2XnzjuDmHjJdtiKkLSnItqflNI
ic9QbSLUp5qfeUI1Bcbe02NXL5jB6iOFf+XK35PspjmDNBF6cdLDA1WamLV5pWHjqL8iNfLXkSSO
QL4CMr3sqoyjbcNGPJmEWdpZlLzgUozWUWh7FVmXyk7egY0rT0MGGTObYeK+tFMVP7zRZGGlD4A6
Bd473I3+CKepqpNKrKDqAlcSjIzOcDI5B3O98zfghVLr4be0EixnkmLj58lgeVFldaqmotf3ayfC
WSgyEQBKg09EoEA4IRTNos2jHWH+/+wRFkQOgaMgGPS/s4WdZCEyKYIzDQlnJf1UfrxtYMf+ebca
UDu7o/El3KtE1rhN8vmf6WgGMVmWPQTD4C/4+4DNSixBNo0TwzLhVKh80grm67yuMAc1MlvIOrjk
dQSCfxTE34/RGeEmMpBbLP4O13g4TUFJS/hY1ITSNfIA/ufD8bXDghYHD0rM/Uw2fhogXZrwi0iq
fPUO6/lboYAl8wj1C6sGtn5aDW0Qf3o7+cANw9HTCjIX6SwhBmB/iDoXjdf8/ZYEw2hWA4PxHqpT
LFDTnlbQzCUbgnr4LBSY/Jm3/I/JiV3rmT6EeR4YNziyRZ2yue/pD8MhOXEYk1bwoyykl7JxFXpS
xRhsDmVNbUVL7thZFI1ly3Wp5a5zdky6ckn2YEu2xbj/RYtXVi4Fl2XZGQyt3MZJToScgB/j25Me
4IhUrXDcMqmfs+88+aFHnh6XChI0WZVxK+6k/R1VeqpGurIbQWpyuXAJW1Nz+l+MToqFZPWowEan
sjbXn7P1E4e8FSio+A3xj0kSbMwXA8aZ7ZXndFHUKkBHp94MN1HUR25HZVNeFdyBoXT3A1NYc/Mq
0tQncwRVf7nXtDe1gAZuDUTWIHor64aRvxfkpNqou1lrAu/l/2DbCxj+0WOnUQbXr/VUQRTGIfIs
CvR1kGmKJX5YoG3Xz4zWZAg5PeIk+Ac0ZueZzwo8Jjn+2qKWvlXvjNBJV23iqPpeNqLo6qrdx1T7
5tghkFDn2JHRKShHY/QTYNELzxqEq6UIs/0r1BYapv3zl+gEamHmVbxmWxvq40xgjHitVuay7krw
iQ0aSM4a1rrc2IxXDUqP4QJz5MuHNiijjweciqSEccXwqrpCkIK7ulabVghBAlayYCy7zhQmLe7G
3mSQ9rPbpaA2M4TLkJ4XDD3d75Hl5eU8ZSAh1RDKyrJyt1zFeChvJyCn++HaABeWwajq01bKj8Zv
Ij3pvsGTZ9GlZym42SvNKPuaXwqnLgWzdfj+blSj6iWpdneuyBH+3fQ1RrcNcIzXdBH8NWYHhm2y
grwv7n98ZaXIqGiD83wQkS0mUn9Lsj/W4LMmul5+N3Yq3fmMpN9rYPB0C1wjRqDWc/h60a/f9lt0
zv+Vhm+HeEBcf/x6Vkj2Co7N1OCqCmbG5nrKhAek1kaF9+jSEvoI3Qh9XkFGvah7G6SaVNxk5dFp
xL+AhMbZDYcHNPdrlZohB+Hr4Ib3+IGGn5+4/ve1pciPhi8B2FMggQMlOsPId0++K3pC09BVkAm7
Z/mNY714FKrJZFUSjYxXNs3iWyNr8Fv0Ff24CEErJnEsJTMm8Sy+hU4cZX1AxCXVI2/y9dOARKor
cdGZx5ccKTwYhV8irRt9fE+gfaJRMVvZqRl7Fqf0G6VF4pCGTG0RtgNZeuAGlwd6y5UISeXQreq6
xB+ZgG+l9apK2exT8VDRqigP5pstd8tRMmClkzo7IV2rd1c9mBLqRJMhSzampcxwIPpu8WigKnr6
gHPV+QFebuIZe0QOQw3ZFh6kV8pNmqRo7UuG97gDgW1Q7Ai03qvcMXh/Y3jTXTFFmFxWEV73dtKj
DqmoOREgFUyd0kXeLkzCARiIumxPKokawaIurR1pIeKogPylQLvjnAyMDKjzxHzTpL3Ct0pBfUvt
m5404RW2tYG273JIc8eXQWiE2ofQ/l8o/ylYT0JLz+Isqh3tqjltZRRKCQwD/lGRcwvLVchRYoeW
1580zvmXRNLioRZ2BNzECXE3n2thp4dA4XyUQ/5/uQ0oqzY9gFTA7qtdaQW9CDNv6ycfc2PxJf4P
9IpG2lTTIB7G8/fKnJku7LdI8IyaApFMkjWRR5Fdq5mJo2VV16m8TgCHTiUKPwUklcwlCLF2OmTJ
rhBfqGlQJjco7s89QNZuftvtJf0P3mtCurtK9CrctUiJ9GmxASOU99NKbeX6D99nXIpMI9gE7xwZ
QVfmHmb2zsbD9cYe6PLJr5BTDMby0eW/K/qN6A5k6mtKKs8dXrF7CmJrVZNrLBeAKfpjqcU9FnrI
nloaTwBd3rcVRs9fXYxtXOna4AX+ADbrjjyf7Tvic3Jb3pRH2J0SzYL/ml3wXasZPDLwf3AN2ShA
gi8BckldvZc8k/3jGr9+fu5/QPPaJerGv5Mp7Xj8p+eHhvG+o9GvjgmU5IM7wCP218hQx+s1Gaun
s1kz8Twj/kTSD/bPsVMmXn49v/LaUf+kvddcecHLD1qX1mW26M7xXvP/CeNklF52liRSmZE+O/1R
EvRyHDCRsCxEnIQPnpgzt53WEZ7OeAS8kLkDehTKUO/WItJVN5PrsH0HvEX8pQa1xNDvr74xb1Io
8jb75Y5CFPexVip31MYp4vVkXTCilU3KvDJcTbhh75/0sgsDTobJ1I2PYi7ury3FLr5Qto4P3KUK
uGwlATWK1HuDlI0cimuuhI2qMnp8trs6Yt3VYYHeQZDV3pLNrCXbDUJbOdc8rm9xa3FFAOoQb4Qq
cNfV11+d0jIxUA1WDe31o4MnREaGFVpfSmrvvmA2IygP33RvCW72oMIkMaQrW1g7IgRWyfdz5iq1
p6HeNgynKmWMzItSN+BIllidfaOEK+p1svMjcm0I6qyuV5mqVCkT1akkr1eiSFBRWFG9jfbN1fzL
gXnnSwY6Pk8HISZTxIh8dnVrqqz/ytiwZlmTYAn+y4VPqyMNViNG7GpwiDKdwJOaRZ7ZzqkztmRe
+gtsCwsAm2RInQWIrukPlWC5xHes5OTRhmjyOIzFlkVK0nHJKDf2SI/Ui8yb2Y7OHPlmwje/k11Q
OWba2mKp7tukQP6eAS0PVyu3kgKclD0Erk4M9uYkuFPAE302uZgD2zM/WKtavYzde9L0RJJUtjJ4
Lr22njBxYt4mUnCzRq3QakUk1zFcSrWeODIqlk44YkKCzLM+ZiqWPyHrWGGSuHBg/u0efmt8M45E
6L2qhGXkt6a3t0Rslq/EHpy4J61Y7sv1wNb8NXiQIJXvXZtG3iAUlgJaeTvUaddL1xk8s7vXa2L5
mShXBrNNecDrkcRbMJFpNkbJUjhkZpn70ARmS5wFLhojHDDRHsiAmS18Sl39c7qILPWL52rvKHMG
4PiRAakQJIQ51/1ghlHv325H59LeR2/7ExgS8FEffK/euxpXYthTx/N/phtdJZ4lAemr/EDhB+Vy
ICfGmI9sbJCK4EPST9PCIPbXDO+QHs2pVPmadURygHAOOSzTxTjdbCY+3aFwKAdY2py8qTJcaUKd
it0uyURu/NI47IeuLhuaq0IFDhXnJy4veBi4qzIco8VdIjPwk6XxDoeVmFfYG1+XVeKdZCrCnGJN
S/6uYBu1eJHE69tkZEnjjdjMiUXAmhyRpPt+8S8mEqL7xMTKE7BY+uxcoAg21L/mZn6nn3DPHyJ8
HExCsz+ksQN9BIM8FnbVrawFtXtZwruUOKWykWeXC0NGGVnDBEotCgpCjLXjFlkt36po9ER6Kjux
hsAje4cV6gC6p1vf7Jj4qU8iz8iBFx/HOvBgwXypGFNuHrV8HrcG0h1dsRp18GhIVtdD55Khs/aX
NenXJIxbOMa8eWx6IxWTNPTk8KA4MnpJhuv0qaEJ+Uh9VPz5fm4Kcdb28EkkAn21Gk15ByW/NnfE
bgZjohDFtKnK+JyGbljUmIAEE29LnHfre8PcmtNGQFrKtQZDOAy7YM9SCowmDfjLe2r4g0v0K6MA
8H1WwHfYuO4yY++alnwaczF5wiwmE9ZleaVmFZM/GZcyT+AMkaEbpusQgbkLOXH/d4riGPtqpB+c
rRX4zmpT9GHlWpxAsRGa5IKFz/cyCT3kpoev/KWOwVDv4RXDEGOrR1brqAJjHNg/qsalfdoewIyj
rRYscVvZiFLdg776T4+qqX1G/qPqjcg6te816GTXmbXT5WzToj2GiwwrSzXKRi6mQ8HBWzSzmvwJ
+cya5qTcAfbZT/CoM2tlgofpQPkhTs6rbxjnNvvoviS92f+iGK9uBLaboOKg+HVhB/A4jPCvxAG9
za0UE/IizJlhK8zuGBjItRTkZtim56JN4pk8YkeE70GV8R6Vy/uxazagTN6XutpNfsJq9IMhRX+u
5MzsaitT3wdThK6j9ZTaVUkPFRMQ4YhjxFKHSOOB3iD3yyS8Rg9rbHRZd6p+tcHLAmq0g+8OutFV
kzwt153/A7AMi6kk5taRvwj4IFsdGQFZYIrOiMtKKTXlAXUNQBb+8c9xL/IvznBuwSMjZnCH+v1Q
hea4yYSWFGBMax6vwK0nhQT1WsjQwcltHlB0jjUfkEwCjepvs3AQKmfFWDrzQByM4zt1QSiD+bIj
SuvRO4uTbWrgS/wSvC/Pi5NgAO+1tPMlBFs78M2MQ+jv6Q3qdA7tkuSQLnrdcLL6C9N5CXD2qRwQ
0neAL4VpnnEEgHhnvj0kDC6Jnnww/4c2asdD/KuA+LGfAZz3IwvHO71KsTJF7gCkQL4XfbMXL2ht
4Yl3VyrF+IEv9BuDElOZNEWyKPJ/tI2j49ldj3T0Z8OBBuHqu9RFc1rLlQZdDvykgo7fk64aBd7Q
Z0cKnvDZrfeXt90aVg6eA+MFiQXUw1ZuZkSFYbdRrzLxY0qh/B/Tzrt7tB1Z1gomJ1/RmrLPLJm4
NbHvGydhiByBOSgDGNY5/DoWyk9RxzIPOipM7KQuIritZEF6sd1uYKW2+ckZ0zO4Vq5n0RCcA1Zt
sq9PXub+Cj1nXAWY0SL05yqv5PT3+xdhcLqsMG7fdqROl5ngBcLqNvm40mTjPDN3eloqdkFBADUk
fI9dkVckfacslpjP8n80qb5QPpZkraKPCFsfmmAEKOR+quoOcEoDHVg58Jxw7x+9+zYHGlK4RGvS
ejWk4FbVO+Tm+jozswXidf6aK/ZIVHxfc1HuqawLIwlHEBXv9wpYktv125cxt6IeDKPDl02K4dPp
8ZGm2B7/le7HeXqnda9kPf6f8kJtfwAk8GfVU8xhT1rkBUzy8hfIKlkIJbusF/aK94uCz4RBGCvx
qHWDeMOgCTzcU2UhAmBzaGUHzf0jIQeJQ0GbpNhuyMfynYQeI8ffV68e6wTMB1FsYiB9fJyvtG5b
cq8jbTsk2GilSpbpcbkSoCxbqFUkkdupyuv0QNHUY1USJlnPz/1nmgD5OpInETFhTlhXZc1wImEg
p8yAIUYOh0yUxoMxus8KolH6TaE9fVkUlcvZasFUWja9Z/4DkL6y76g36vk0XYv0YLFnVB1/hjuO
KHqTm3oNMxXeqJTdxw+ByB95k43r9XVu1TS+97HW0+dPCQ/Kr3TMeaU/YBZ5iiCklcPHbDf3+80g
G8s+two6zwv1KbvHKKdtAjeeykLMzDXzGWt2HxhQDqm4hedGRMr2UqyfGaspcOTwapndaWIK6dMi
QNdC6eyv7esVtUqOuQRHTZoFZhcTIH0YkYi4SvRvVXh3WTUuJUFdp0xnrA3w4yg+7NYoPSjOuOow
KWDU1nqiSGrW6eQzHOzQbU+61k68OtbhGs7WoVkcWmFSle0aMyIgmibvx81xKhCJta1Z6cZKikZD
BIVbHPRdkt0Fur/B0f/pm9+cxVVACwFMzgwugFrRlkVj6R5uTJirKf3U86qUkbSj+n1SoaWxQauE
EDah5WzHcW1pPqas3dqoE53n4ef7YDfJpndyqI8BDA6qFJbwtlpsrwgF3UvLLOOKGihAkunkWw0u
s3Vg2W8NBLYAEGi/zm5XSr9jP6+jK0auq7tpu5Q3mFrKoj93+j8N0BuAPgif6cHkPcvYEh6B8l5I
BpaTPV8n+xJbQa9PsE3WL0W/NOWW8WpWtdqfVTdONR+oy9BGqbaxh9Fe9UlFXcsGB5+xmGeUKjM/
+FNNTuC4k0aFGTv0KC8ogIq8dwEykvb43fE1epai/ISkPuoP01cGB5pUWJkNtWoBA+cmOIFpNzMM
lZrqe7MU+fbubHy8IqqiNRihwsDhQj58/MGqejHdEpTLGAQkfQwpaG6g1JgYW+nlQRqMDIN7JTLi
IDeAujRft9FEGmui6Fx2Oo77frR9pPneLHHnVTgqBR2c3jPpGHs2MfB9cRFOfDPG3J+6ecugZB+6
L6xaeIrsCMDg9gmcCXr40v8enNmPHqbUVI7CgSJgE+MmF36siTcYDIr4xa+UYcS/CLL4GI26EP+1
mz1IH8+v723UMk6LprBa6vgWokZ5RQb+YOHMVpMP60fB3Lrwcr2Hpwrz98jPBfkz8HKXOLj8KSQq
LgG+Y8wAPV9BSvMGrd3r6tpuB+dS2rlANIrrrXXJOme4/odHeNKoaj/ctO5yE+JMOBxrZRHg+FCV
F7gjwEX93Ir4rjlvNfdreSrP0jQ8r8LMt9TPIkf4rpC0AUQI2Uq1miKbCeL8mv6Kpsmg+FpCKMaQ
1ROioUHvXW3vliWD7CZch3IOQzIQ53JBTFCHujBVNtPyWEwpJ9g4icnSWAg46x6lbmoZJMROsFd3
vKo176BnjXcqZMo4ndrl2KGOxsbIv6Z6FhkNbx2QqFfLOu2DfSKuP9VX8dSxskhUUN/b4G4Noc5b
RCwHLeF2SazDVV1hDELBZRfHa+jmfHSgBXvIE9xJ2UpYwn7RhhOPnba3RhIJ8aAPx5/Lkdp0htZu
NUn8gba/gL2V3x3GqffySd8inplE01yxOS5FE3fSM+Sehc+XqkOY7N+eeNTCCvtG5TdvUweQqSw2
e40949uqzwxPU/5QSOED14+wIaVmUSF5VjVD3QoLPUcuLpA4w0ccka3xWa3tY6dtg4p+BXjbqKMj
2ItzI1ijUbftLRgUdnQehWwYtNucjAGXcWibN+e0DcFAlJ6PdTyOCJgwySzdIz/Hlm0IHiTAoL99
M9c4LWyKBv6SyPkR9Ky6TU278spVE/wDrEfvnNTH4gqdSxyb7jU/N5awDT+TH5acvTvtTxsTbCno
MiaO53sTQVuu288qB1o+1+U5bv59dOOvw+EZ2Sc8FZg6szYLo6pTsFHDynz45J9Gy+LyHZhTl3/B
htIHIqB56VuAr+/v5Hb6iUwPf/g/3YamyD5GHPQYDSJTK1tdiH+cFu9sos8ZmzgU6MWPYUHReQM2
GPbbI20odN81w/2o6r4oBLr6q2iWpG13FojpWCpM+omf06G0cT1fXPtwayZjl3DQk64FoPWMq136
mWCfvgmcfgMfVsOneqHxrs5MIT/JvPf3byWZdV+97JMRHv8R20h0K071BWXDUPjlf02XLsIMq9qh
4X81tEAxZgXxC4fsN5fviYzCS5AhoglsXc8ViVUfOJ80kmAXfat56r1o33HyyQ2bxkf+NHtNBJ7n
/pgmmq8mRv1Jzp5J7l6ooicfUiXbmLMzylJANmO2l3icJU7RkNa4Wj3dfkps5vn2bQQjp0mUqaY2
5UznHJDPNLcZvmGPnwSSzCAOJlRLpHIhqFlc0t8GfR2pSQZP4sRKI3MZ92i4+2wUXnLSrgbOwyQL
x6UdwUtANSKUIBWZvx6iR1NBwj0xtwunksN1edaehF+sRTtmTGPfHkNPEe5n3iGo6SbZDVR+st3t
NQYriY6237c6GQl8UKUjgh7D8B3YE0cFaA5EdKcXB1WqQnJklOqToa/JJ70gxqnS9elIXpUd4Vmk
uN/6kNFAPmY9Qbb7K7RCZTkYepuQRGQH4WK2g3vr28HtWBBlkW9bQj3l9IOce0IOcnb1jwVsIDrV
GFP84I65w7rNwKPLVhRCCkHxcd4xm0qWi6TY9mGbx1HC1K1m33AkKHvgzaIcYVk1CUox5oSJU0XM
AsJ9UfxcmOFfh/bZAP9y+j0tHHo9mWOJOy4Eisk6hmMpUlJTVSYOKlDJt7bVF2+LrATHnOayuINY
QVN6xu/Rc+xD/8gfePHJArspG+eHT+sduM4UsZdOmI+PyAjMb+gvgPnO4Uu6aDlDbfzReVaROVF1
Nd1BaxMP7NiUenSdtArIGgerdISOS/yg0xuAKI0AkBVKuOEn5NMvWtC7bLUVWBTLKo8RVXVqsHAr
f9uitHt1KPmgR0x9rvugp87w927fmVDejD89ryy3GII8NGtaikaNe9oRwkNQsiejD4RVDVB43oN5
b3esmvgpd4mNzXvn4BgHcCYP/8OYlQG2JR2IMZLB51SF2SKfgUuaa07XsemOTBWZQGeuEcKitad+
8K0q0iyflOzyKdQmyXG7MDamsZ+UHZDBg0264uk8ovQH3u6ZVQPhQOS1GRMS/X6u9Hxb6KR1ysJc
5wGFduuBo2/ompY1UrQSmM5uE28DPYkUTs0yoqO9UwRY70ZAvfAd3Ogzz1FweAT9D2gqPsPL20HQ
WHBZjYxO4fLnHasSdwOmOY2y97XzmlUB75OFYAh/vqyVAzKeCTmbh0CVmO3sVWUmUy0ERk1brmDr
BATOl29fvaT2YaseEeLg6fvBQ4CbhtbTroYgVWeW2WyiI8VQVl94v7m3iBEmHeRDcBdmCkbOUMB2
AqitqiVeHPoobenpwfUiPerP1gMjXRq8uKr2oFWiGYeUEJVY/pKxWR2G7ovFbLuqgGjl5uj7Ya3G
t5asu8UOOL4xzZ+OVdv8yN1UZiIP5X/BWu+AKQzzzZWEqszPe2eJFXlwI+OujCejbFh3uNsjH/8I
UstJQXy2tEYvvMn/3B9ArBSNUWTvzBdI0bTkF1KCvDpXFaIPgvJkP6RMiQRDMPxACq+1YLjEpK5X
4H+1hbOEEkfhHWHe939pdq2JT1uPf+bH9CNjczgyLCiPl48Iu5v6CcD0pE2g635qENYDCzeXTZYj
fVo4/tr+7+kmGSaQmhazatCcZIvUg/aq0yPL1J/Z2/V7ogpWpqSJ79tsYtHrgTH5GKAz9UqGKEKD
xAuU/3zjxYwR+6mps2KeHMVyP7NH+tAGkYn9iMuSdsU7GLIc2Xx+ybWFxUxp2dYNy6CFLIkNiC5z
rnvU5HH1QpirxLndbBYeAiia3nREjTEiP5hUnnbb15LbTz+16pnHMc3I4MTIeRQGgn+40qfAJ8Za
UdWEimnbtWBKJYU7U12pwxBQ2xxGwkORAV5JtvwJMl7rS7EkByNx5LjGjtU5oCTeRnvesLrp5REA
3yxD36vk9KDTkIUPsSn90YYJec2tz+Xtjp7+LND3ojnKQbJPncUGUbuIy1ifuINSJS/kNN1+eWsY
tZ13Jb2HWdwutwdgT5fA2FylSadHDE2jUF84QgQOThRBRLuLgplhz17rHptbLGsybGBXFYK9vPdg
le8twcfXobxLZdnIA6ynEvisv3LxlsIshjJ2/3mgb6B7XY+0RVR89zGnfEWq2Ss7ir90ISlSuOK1
XWa4E+UOr75Bfcgjlt7syi6oqLfqz7APP6+8cDMEg4rfzoyGvjl9+ltKEHrYLUEhaBwxeg6pYoFH
pj16RhjEzLRVV3l0+fHm1o+344kFFIc6HrPWWjCQ3CbeOKbzfqGi3YxoLdqPCorYzqnarkmFQDc6
ouSX9cu+mDYZ4IIqgih6qhGW53rTbmIrkTVSF2xvsiGDF3/I9dT/tj9cJCFsWuH13pvw3mOHevTr
iuAC9nRvgc0PQYVkSdef1bu+VsTK5oZnV73shy1MgH5kxKY5UhO5fUJLN5YjQP2qiLpEnZHWWODf
EBdMRJuy8Wz8Zj99mrVq4YNbfxgrPXxpLLwvMJuTgvIjDMYlg/+JTW3ysH+FT7G3NhQpOjGZViOk
YP3MtSg526mxVc2ppSB/4KYfiomtuYxMVmLATSNH+tzuD59QntouZr9pnlMFUmbyc8pzhsHQuFlf
uWgusg6BxXWc579J0GP0cp2O5L+pmg323GYCBF+5JNeZp7jwGYsjlAB6OJmGtyOHe+EmDnYgs610
Rv5g1dkkfYOmpfnmmI7MltNTv/938O2iPGtmTGVBuFCcACbl2cymA0Yngy3/3hf1WqrYsffbmrUy
uF2tFlXwzJl+0Tws5tW/mUyGLL3BEF/BT8MFuY78mbAewk52+wOIrk06t2ZWmnUHEG8a16AjaHM7
t4EEWvSmTLKn6E2hBImrx0l/TXy/YNxVAWHLRRVx99Nr2U5U0duXfBhXZliWpQwPityvFxhN2RDc
dS0T8JbKptp49EAEEwA+fIuvtQ/GRQ/rNksd3Bf6BHdt1KUPoNk7H+fwWnOG1GBbLwUgXNCgmMY+
Myc0Pn7QVaOCx5BNoemuicnbtzlBqsL8sdbXBLrvlPXlf9lZK81tvfEw7Pp4lUlPaZf+jH8F+LTQ
8CvBizFKZR+egpnvYwyQOiiewD1VeksrEvTVsXgfrKxSX6DspfGWXgU93feND4labq6ubMPpIsZB
SLSLligJZzaLMIbQI6vYqpkY5NUTe9NHt7mffw35F0f3otNEZWziyBWmaz028Oe02F8vxZLOfV/y
/ZGpApurLXHesIm4EO/fw0NhAZ85hz6deIU89VBqi5k+RdeKGlV8ZbKNlUxBsoanylXTYVHwGbH6
B/Enqq7OZXV0uekmrLesAQu3HOr1eA+432bKdPqI9UiAfZVC37f+BHMftvZ5SKCoN09cndXgG3ai
Bh0fUvY7RuEY6WVluRAVBimVWATjs/A/cu0xNRmuYaCkN7+8f2deFX4VvSAeTIpgg///TUTDTPgt
cKZEaAmKie/tBQTaf9zglSrViLagRIuVOPzYcj7Uns6D+bagh7nhmJF/8CdQ2aY7LnTJC5x0gBCF
axsrqMGZXpl8eJimHV/Yt7vUTDkzKcnGR2G/vwPbeqYTW8syADLEy+PbHkCxc8ZublAFz37a6DJ1
JkNu9Ae0F+a2B6Fh5UqUeOckliASLRL3ujwhidNnD/AfW9v40F6HemXvx7PkOyT/akUmMQxW/pAe
fP8Phgx497M9nDsLKvwEiHbH1zV2/OAAWvLZheLP/Qt/nUGBBku/56CvptQFVJtXlue652bksWT5
5ESWUTVeYO3zha7KunxmL9Cya8V3CqtGU45YL5A/b+1iGjGnskgnug6l3F/ZZZVjeeLlbR14XLS4
UIatJ6accecB3r6FnkSXyb3NomEPxg/wE0rWhnjefGZmb/AEL7A2ZRMVG+5ItTS4G6o0j0BD5rbl
sE0d0jUIWlyNADwufAR9fqkX0RSnKLHkB/wSjJ3PQnB82tya4D2iZJr+zoTv9vJeV6ptYeeiMwPs
zkWVQ2McBNr9auF7TRf/MykS+VZGhOzImyPZfVDQ//tD98u2Fd2NATLBKNr2nFkU/mHmE4sQy52I
XIq5o5OQx7XLvmoAmhA5w/A9SgzxkFKUtd7AhKhkKtdV3fb+54ZGAtkDCSXbGVJ5hALOQudY9WBc
0tqPcZjFWNpwj+9/B975maCs1WRIX+4h6eE3oLWBqU1TkC8geYmuvdRnQahqZ9XXk/6zbz6HO8G3
d23vTJncFma9Ooc2thguMnLU6FavkgbvEePQZ5tHdP/KyOR+eFQYe1sY6L0NNT2NovqdIKL7HlLQ
aiHWlb7tnHNptwoHhlkuf9UIX6B8QzbBJA1G0zU5G4CIKT5EIBYRpGhWEIaAwHWHSV3ms71booA5
tbxjPnitQn4K4oqlf0UKvmlAsLXfr/8SIQm56h/39c7hn4+OXsKt2HDCOR0Qo6ePzAksq2NlD4KK
B7XSynaOkbfV3GYjHFptewMSWHRsikitZ10qlarMVLTC4wOdE+FydUTZzO+sjDxA4yHAVOnPyB+s
KB+T9n2hfzv1AYdkNfCIDjBzEBEgCRQriBVS7HFx7/Kxxiam90pYiqBe2rYJp5hyi1uvnbcCgsi8
x3qiI2bIYhM7hUzBBz86MxjQTMHw+M8werZfDG/D+wM4gOKCFmpIvdDRRqxKaDLq/pHAy+GFtMQt
vW3YulLIQVnIWgby+BaXOYaQ6/OWUAhgQ8bgMIzvKK5coMDES4zLO9bQ4HQdXGxMQotdERI/ZWIA
ZnPUV6/kTrY+FlfwExQGtXupNErMTFEAGB7GZvAAezrzD1wXPi4dFULNTBEOf3UvVVbdaYWeg6aM
TvZ/53avsmrC0gEzlBf/3hRNalPtxY/fgbUwIsRUdPzH/a4r4pl+ixgmXMV9bEXYDflHG0T7PaTJ
wnDAwlc5AwMEzR9Lqo3oyTvNPKlplqye8Y2SZdmH7xgmma6cgotC9c8/p6jsnL+ahnV2AL3mksBY
sCOOeinWWHzF1Qt4u4g6RPHA2feTc64LVqRQOqFImozimwA2dU7U675P/Aded3MZC8znxgXcqgF+
VQW6TX42Z2MZmGB2lOH2qq/01KFoBOkIIoJuprxc96OcKXH/ko8wZuoXTz5Dh1XEY/LMmbsQw2P4
Z0xNe+9acy2fVW3y/V8pmSgjB6E5NHnB0cZYjvm1AIlK95nhq0Va6OUf6aD90LZjPxH2gUTang/d
8A5XiHA9S/Sbz47nHserxRM0KXZrjOrwJQ0krIKOWBPD3ObFIdLseG1mkv0zDqPpIM0sPmyRI02m
sChz0w0ZeH60wqQz2kpPqC+RFfp8vrsUB3fKnYRUP/hhnK+sSryMhK20ucKXHJ2mij5S86N24bm3
GzLIA9TimrlAfciac2jsP7n8ankd+hE/jIQROf17sX68pl3qS65ySA7J8CNQu/9UHW48NfjvkJmK
eUdHIEVusC0akB8Ca8IiFeHxQfioDFsQ5swZbU36MWRpQYZDL5UPIluQI/zlbTm1rLbB0izab707
UxOouCxSOSOar2O2OGJT2mzcKQwvjhGJUtQZlHlm1SuWHZ0MipTO+N9GsaoB7nq9wJ7BlkAuZDQx
GVKN+1MYzbLNhFumemQk6zDaAWVoiQVVGlWVnHvB/sfQP+MOT2Viz8Ys7a+IuxWEMnAhJ9gyMVVk
TGsWZuxinc886qPJduwChgfjBBvCTyjqxHJRMyuF2u0mcIpsLmce3Y4oj7u+1WXpa1iFW1jYZ0mq
Uie0iSPYoJNZZumQdZpUgMms5Er/AKhePOtRVfIREogs2djhgYQ9xssxDjl0yLFjQ9HAWtNJi9o6
z5v1GLJ19EfpqSoKIN7/ehAg/ZbLjfm6VilNU6hWKNqjGjfLRguEt1q75V5w9sxryT8/BpLDlnFA
HFbn0IMpIsmls09NSOWP/RDv4m0frcg3EgAOaNMaNI4YYqOocOg96s4QaN+qx4yXFUF7gR3BEugl
yFep7b1WbWI7BHBhajaNfCC2a1lqZ2qpx7bKfr4MZ83vZJk7f5pq+bsTH7WWLI1W6jTPVLT3WEQK
afpaZ0RmV041+0FOeoIKATRPiIVBtgjGpu1VajbXvDnWzEQZiAzePh5xikjjtfRQurN+1gOvSea/
pCdTrcinzbcnEBoD0ZPre0TPqtj8g+Y9UgvG9dYJp71PdNg4YqcQzgvDoECIZtVGhxiUI+EHdzWl
Aie9nBlPUR1skUKu4iPJEtO4bAJaxIrppNXOFo5yaCOuldirDCsvOHHi4U4tFKZemeF1ycVX20kh
NCnnGjWxjPANyEsL4nA/QJX4FuLsrNiCcdLfvRiDYl0iLl9jMd+uwmirq3+4UVyvaOMAG40qgxZF
N9N6sCp2bo9Njb48C0papOuV93pnufVVNv4mrhOv44P8xGEynJtQCuFY9hFYz2sW3Z+1Y/DD+L0L
Ao6G/iZLSAwkoqrygZza9A2d8Kll2YXCGwa/ybEWsDJAV3dNuksghDN/+PbKCkWN2m/GoV4XPG4h
jShxO99woNZ/0xgHEikj4MCXe/mQq2uSRW0G6w6ptaQBzc74GhSy3jJjsBLNp9ZhOa85RnRrbWU1
LG6CiynPoObNnmBBTtPuIOuVnlH5qHR339uknUthTDrIbkBz+Njzg/EuBH/kcidHa2adCPFBzOFS
1rJXQpHY65YhF/jXZ+lC8Owl6q459mzauxmC4DFUI+k5clnWTl8uMEsQam8aOTelvA3UPJ7OKDVC
m2yUmTsTiPLf+aj4JpRaHOrHI+Ch7waTGgsR3A/nqzmvATDR3vwV/3ZD7YydJVEjRxAKWI8PDpBn
9LOKablZT+TAiIDVcU/pOmJ/9uTbD609nAdkfS5eOrdqZl4exyxqCpd5aFdEfTdpFtZQYi4UBRIp
4TImF4l8iFxYKlzth1LUCJGeIMMoS8dOf7ThDVuTdGiACYoMVOE7QrK1XxIEljncDY1o8Ad5L5z0
CtwpcFmH6CMymmB8vmbi8uGVWUCQDiW/rldppI7y6cJlKS2xqUMlE0WCc/j0iX/2Klzr+tUlNHZY
iunoWKcYtH1R8Xa0OUj5EFOQL+vmclq6BOUc0DdBu96Dd1vQjERxZD/7+ZHoGqYQkvS61UrHgr2P
8h1zm4ztfgnQ1rVgeqyW2P0JHUyejfInmA6qXOu/lmO2FlkGYsfqlnZoVyPW7LbARjfJE6chwu8I
RbfcobASQu4+ccHlSoJJ9w0eQHl4Kr11FPEdgBf2IoR4w/tF7+iPb3a360jQ1oOWFzgfOZ47dbfd
+8u02+RDIUSprxp9sUnHHgpY2oP4VL9MoNQZirvaxC47m9gakrNDPTv2r1YABQwRU9u+0OIbk+8y
QVNSRpcwuymL2vn3owGb5O6j20URGdYhAVzBf4C1Rlni0jfBuwZcLrZDxNzPPtAxramiZQqJLDXu
YaxDMueNl6pGNa7S9hGRoylBSedS5zLCnyvUa5/M8uapNa8ra8k0V+Gor232Xp6bAYBIdsjHu4Od
lq1pbKA/Qbh6l9FrTR6GSzPh6GJe9kcC2bDDfSXQOZZd4cDRqBfMNlq7sYsavMisHB0unyO63V8B
Ou25lf3LKvWEPH9RQjM4khNqMwE+pPcBgvhVzXibB6ihjUQtrRqWApW0L5eLh2E9EAY5lBFhH9T8
X6JbqAgeHAkpZs0tSqkHe9F/0JL/AyLuOKC8cWI7szThSG2aPDvTnIWcCr/+zE2eryo8tLlnXJTA
dzL+QzjO1k3hvI+RqyZzzt1nTSRDrzo7iP2K6a7aE6OpXd0lYtPRqNKJUrVFQjN2TxDW0zaSUnje
btzyC9x4ve9f4Jd8qID1Kk+LhUunT+3/XYrp+uw/0FFj9Sws+LNclunCWilvkPMe/BolSyiMAcHD
hiYe9LK0Hqwly+FCmbCJVy44e5afhujruT9i6azjZBnUkC8Pz0R3OqgV/eY3dD3Z7i3hhcfk6X3P
mbmsQnQ/+xG6u9YP7B4oHqTYOtA6jpBzaP8BzC480PvMckv0SE2+qfCQzfjo4TmjaoeqA74MZnmO
UYLOTvZ4ULZYUsy3uko/SaqFbCZEmd3XeB6sy2D6ALO84Ai0KyFNyvNO11EAU7u9Xne7FOoqOh1t
V140qvr/zFr2usqwwQlcrNqurt6qzyyr7a5Dq2evSQnRtPcZ+3WV+PDnqTA7mUYAJXfsA1Wsj2BT
iUo6O6ptKVq4g2LWnybg4Ul6s9cBUDqD3QpJyg2qIZojQiGOI75c30Tl9bwiNiosbLYqw4pb3OLp
i2tHl4mpE23iGl2irFjifJKnZXR8xH3Fs2/XvHyOJD494nS9xvT/bsVZpS17HH5P0gOTV905pL37
zUBvgg9Xh2K3Gkn6mJpPyOY0UeWoV7oKp/XxRGitAKH1KmliPytQGnitgCE+0l4E6mJZNK6Bf4lV
blujTwkV6cZMkU1ktY5IXj6+yUiJwR0rmD3lyDUzwV9XSttm3eGkxGUNWFJs5QmgmdR8HxRsnu5W
niltHuUlEof2NYQU3roAsdvsriJPGtcVbtkrsvJbI35dR38NeFa4f+P2Aw6FEMzwsiTAzNmQni5N
B395xWal7P6JSM4qrlYTmW3sZddcvXCs1FlBDE6giHbEsIfMthMUr+avvgZ0Q2hJNftIsOaM0koo
EivKM1hRg3Qfg+and/joZw8vEUEDZaeSE+/sOZzmB7hwTWYVvY7trNdc8ZJXJQ/gvE7NvrXkFhOb
kTFjjFWB2ZOTnUsg7npHzKCAhqxyc6VgLWCAg2bAl98uULWkOYxBrEqwf33bWxjCDgyRJZO3Rvqv
bzkcPj9fsQPZ2xnTTy0SEYsjRCtBHtup0lmJ01y2kBmHuWZcR09D+To3JPPddXBxkRlkW8jXC7qq
7jqdUA3pSzxiOR06KpT6QqGSX16yJtpjdzCCfEXNunPtNOZzLfgbxdqGjzqKx8iB/Qp+Ue8ORcoj
vVteHKxUremoiQ/1VJ5K0vv2GnF/5UQH4cP+z9OclGANcupZrgJNpSdrrs76keMMoJFx0Yvh9HKm
Nxpl/zn7qOKk9jY7SlEMzjr8cWEPToR1QfL6iy4+XCp/jg0x4L1wk/59gNx4H/Ouls2rcSyT3Ed1
7dXxc1Ewc1xnCFg3wRscH1A7NkyBwGL3QzPXF492w3daTFuSmSmdKBoMly8SNqZbZ0XOH3zVhebt
0H2dojOrYHabO86yToGXken3fJnEpCKNlEMCt6bEX0/xqewVlq1I8AmEaqOCDyZuuNgxekQMGTvR
rb5vPYrs3lLDtl1RH3QxepTgX3e9Zp0uh1AvdefJkSKh+Kiku+gxwwHdvJhKqJHFhr9JhkU+MbQj
YJ2rMvdnSg2N7vjjn8rnrj0ZYs7taCFTejkhcdwh1YVcf4nQRu2fZY63GXWxq2GvMCQCCEP2PuEP
6VVskN0ak7sLI2lyPbzQTyJYX11MTnPByQIwWFEqTrG+6TQmJczqVTeCVfl4Jvhoq6wQkKR+qUHY
ap/J7MEzQiB5G8AlG8t8Xsdiv1uC9w53TbeDIb/n2HcstFtSXELfIq60BBeTbxKQu0XAQRSIGWgL
jXth31/Hja3lGV+G70+OVwY0LdLAN96Dtq7onj7+0dqaXKkCBIjAwjJpiTGed4sbxvHTXjq/g3OW
aUiw+8/RU1TLSYYcrEgF/zZ6piUVpMcelozbRsD4w5VaaBAnlk2fq+mH9GmU794ez1hNPNdUo+pL
oY0s/RZnAs+pxHTIYh4nI810jTDrwO04SWWGTdnASIicFuVmPg10nMcNbHk8EL0QnFd5/iDPzJ4Z
N0RiBYBB+jWEDTy0ks8dtpD2mYNecr0ZMeX3MVkSFaY0Jrz4KZGL+BW0yMdsC3DoH3zhNcAXzrKx
Ifz3S6IjSMbxYD4TS0o4Woup4Ijb8LgRyht9usyTrCUBz6m6X2JR0ksp7iIKcRT2xMIVyGazOGcB
Y9cr8AKrzRcfn+OrG8gcVX1Rw5zClCd4Jc/cgFbNZeHeeIkNO7immFPl7AwUu/7qpYdcK1Qn7fE+
bKCtiM4yrdkxW/OvKrl9EIsh5w6uNL7M0+tFIjdtE3SdRKzKk8e8SeNYIu4TH6QD3a8gw4A+uhtB
UJJgyLX1K5wn878yXSCWhdifRuA3TIDewj51J3MC+/fVuZXUWr2Kv3aRUEdJnRXcqE9oRd4GQNlK
gCrqEkEjXjYKqIRAt+4c1lZgwYtcMlaBJwqnsXkPNdHvi3zVLdqOqf+NPbpsaxGB61hNd6RJxjBf
iQorcKHgt9MgY0vrV/L42urbvRjNSA/3j8gB/oeK82lP7yB+QLIWnIdH7qGMYWT1tbV0SN+3TiYP
DW8Tj3WWYx5xIwxkVSy+4IPtGtjbNqdPTWa7T//vEBmVz/GH8gxj9cp4/okZaxzfWb+xXhd11lhf
jqiYcWjk/wB0aiKq4uivMtf+tmOhJ54pa4LkrIEPDST9RI5gp0XhVIQND42iLj/CUfdJkVKBQE9k
OT1Kf5s4Ly2d1s3CkuDVkJPrZ2AeNqNtdhD0Z3678ad8Cqc88szgFOS+lwvrxGyyMQNPibGz+qP0
DOc6/nfnucVP+BwBmgzEkobdY7KIg/AgvSI3KRd5QvblkLeSDGRf2XZ7qFT96evDknhcYqc33gPk
MRvoUFaaRhYjqkpF0Ah0VDvDvS5MNk6G+3H0L2LQ4uRdDJ+oy/VYunRVcfLp4wkBlCFMceiBRxTy
ldo8nEIfbqZrsztAS/kuIcIt0k3Uyuwf1KmVYzslY4/zLh0+0ui9c93EeyixcbGNuw3tgrIJTc2F
mo1T5xmu2DDpriGPw+RlN/SfnyUtEPvFadJhRoP2AywuQeBAsASTA/Cfy0D8uCM5RyQpeGDp+ixD
wXyo1YtAT+VQF0PoszfL792SwQUcegyvcGoqLc4ZhbWVyYH6kWooW2AuXMF2JqCYJ+y+cILy6+5p
5yOpHh17oYWbVJcF2NCMktRIZ74HwbfWzL5+TxWe/THPCter2fzRGGEihHEg76A3E1tgVt44wpMn
ujfUQy1467Gob0YjNZ2CbSwu6ql2d5LBihBi6l02FB6jmTcTwBwhPTn3d6oKWzzROgv56inmyAvU
QYwS1Nv4In8jKoJksvGV3osN0EXQBgchki/kuD/3gWaFWcFS3iW2DuV6RneW/wbWCGEaoz9jXpDH
mdIakYrnnlQQ//GJ8ZEICrT55GPIEY4sbZpkDYT9YQG1KrgEa4iozp42VN/89aMD3zIvgUkVCghC
VBKTdvaykopc7uVuP7RkAtSspiOlsD7dNID+uavg58Ssk00WBXW5ilZlIYuVjgZA26rdKQOsjiHx
ux9pFdm76tKjuG23WnRatgwUAwlMtQ5tVeQSh7ESWzysNpmye9VRKuGbFRkrl3MGRMAXv2khASpC
h5ja4oKlZADXW249VkfoAuvX3XMFC4i2/6UvWOLt+Kou9aQ7/FjL2iYQNThOYp+XFQ4Lx44YXggR
wYuu7WZ+jCihebDK+oMoJ56qnmnIfwyBfGUuk1NL8N3W56quT6B7a5CLLS3/lNFYbeBeCVqKV07H
Aw85Gg08Ck7MTef0aOXGEum2Pw1UFgt7h83lgfXml9/oAgQ765/gsd7ilcqXM71juvFsfanC4mwI
Ux7xTR+k8cMOYBWMwx/b2Qc7KFWM0av39uLaiWUj3IxZ+UoAWj309ImqMdpjKNWKGBXsGFOaUSLz
+j2C7E8Es93aygFz8XZNnMlcHClHoRvUuVsDxuc5POxxT1Y/wO/NnT3vgL/ZbVRikuW+U6SJ+Uai
3Yzn+jh5FkDLzkE13J15t2nNGMWYYGXQPu8PjN79kR6eXpwQfealOBSysicVOTA1D9v7wwYMtN/H
itCfAl9Lkj3TkCZn5U8cndqlYmQkpy3bSwMZWJFgIDYy2QvEYbj/cKR9eRqM4ovLiY6qz1EvrHM+
AqSiKxeF6yWH65jZ0LsY3u+p+a6D6Ns++nsuNWIuqhss5UvjpVrPTURWWU7Pfe8AP8ZwD20+8NXI
TGtie/utdq1iaIhy34NyXsleLxjIl5YLizsYxJMfQQO7GiVpZcDPNmv8SZG+perDqEGFZNqT3ql5
YmDY1brXv76UOuf+Q893H3FFkWl3iYC8pp5VTCyIaB3mBHXLZynI4kblyOHNWfnJvUCjWrTiGsEX
U7ciR8TREAx+7yvm26Z56PchMynqEODcsy18hh1WnLFFsRqFuiT28Kwfs8whTAXS0+TadPvUFfdM
h3uG5ioahJegjNPxfES/HGayqqrXiDMM95FQUPRrk71q92/Yr47XwPrVZyMsfK+F12MeoRE6JnAI
hvZP66vgEJm1zZHdgEvq4cDoemSDw5OqLUJBmij2evhJmIczxVjwSshhME62Scn+pfe+G8kkLE2V
qTwEsgDUxd49jk68SFWQ579coLf1mrAQUXYWcuAEtWggeZIZM/BPu3cpZzckFHdO5TZyGo9/zXXI
cHRIKD1TsVfqcFBzgS1UDA47mfIPXt+ErF7Ci58hnRcyhiScc2QZ5W9IInfdMXWsQ82tEWm1w6no
Us2bt9tNvqSkrabJzs/6EpnCLB6MCd7ukFfvDMtQLnk6UNe0MBFD2g8uLfIM1VoA72Z95wEtFE3M
i3dW/jzuqzxns5+oGjxsBwxa3siam3s3Yfs1CtA/XkcuHDiahxqkjF2jlGoQ05zR3NtLlvWmqWrP
XqLtmSQ1FBJlgy58oRGbLvcC+SmYz+xHvXBwgwa8bE4rGDvyvL91huhZKqP6wSLX7fFrlN4Ku04V
BVqMSt/lMZP/J2tq4FfFdwuSTrHAQHOK3IZh1Q3mG4Mijs+dcgja7gRvwyiIqwrApY3l+JTz92vl
I4hbE5v8+aVfTNvYqtZ5IcOGv9tnoIvdilEYE6aWGOE5uN4dtn+8qQ8D6o8LwjeX1Gphl0sAJV21
Z7h8Ah6qz37ZZYmhQR/LMqNmoeWv92nn+UZ0LEnUPHO0KW/ae9QtxwGXELIqvh9EBlYTl6bS8KbN
MRkynyUX2YvrdJdvYN81T7maQZnt7rwXX0r6P6GyqJH4eb4LHiblCWjBopFh+yLcfAA4ZsCbnNW7
dGAqYfOFAD5fKlW/fflwtu72F6u6irHuZ7wAhYxtyaAFF+vL1G354k0kfoyezoSsLXwwJFXeIm+l
w7vDHLNNCRdw5huVXWTwmsVyiyb+Gr1xcDpEyGfbP7/GsP3PiF0eJOh+haDBX3evCj1Toef4Bdyj
b1MsM77Rx+vNmj0o35JqZCiGWAEu9yZBMiBXfAGVgi0vp9J64q0YucVWGBTf0eaMIOlHIJ5SORJ/
8ERGnJ9TSiXfleIPvrJb0eyseayxA93sfxIqR7Egm7k+1IwmYr4c1e6yRcMLekorcaShxrrp/6UN
HFSOQIaNCoeElF5m1zmHl0XLWM76C8M2K1Q109G0R5oYa3btovSJqg9+dOyKOcL28JFiaexsRVeL
8GCNs8aYunw6lrgfSkv0PDbcO3xKdTFKYj0Le8Wg9Y80Zfd3EKVvHmkFtkV+1ycgEZqvIHUweJ35
KHNJDz4RTbgEO/i3Bt4y+5m6FB2zsNwFjAW0W49/AwSW18/9fuIiVnXwwdnGDpe5djV4LrUqYueq
xF14LefIVeBKSzcb1zOKrdur4YYvuvplyVMSCTLb7ffkYc60ntaFAKFCcUdvuFCj1ZYaEKRJI5NJ
vPYX8yHuwsy0LLg7OcleRXfstaPinBcV8y8H4vRGltMnIBvD3fvdw0uahErZaj3wO4NVaKwiVH8Q
bzv99kc/vauJF8hKzid+r48upwOG2JvGnAOp4S1YPmfwB/55mtQWj4lZjnQsr52bj6OKQk7SuXQU
UBxCc1md/wiUeSxbyt+tJbwJ/Xt78w8Mj859Ksl1IJtv1eQEJggmbrhRxN9qurz2x4sqbZUP/SdP
6HiT1OoyuAlkYlTOt9P4wibrZNo1YJsAEyyu/F2E9jZsYrVJPEIs2OoqfrOUCSfAowf8BMFf6bx/
3tnXJON6hFVwMnIHCknH2eIydY1Ip/mHVy3zUlkgOv8e36bWei7h5tbKkQYUS6TYlv/NbwQLV1U3
g/UMK5XxB2OjBW3ePy2f6CUQpuJADZwWL8gKdtkhUJ3x3zcjX74iJf82o1lmu9Yih6MSHf4Tt1uW
sAaKaSVAHfYpElQwF52R/k87SKS3+ufyjjc4gcNnwpl3as5jeUU4CQVlDOOWyay/6DSEDDLr3YMF
VposapHLg2bhXE9mzdj10xRsyhmaV73Y07uTYfVzD/57edychZe5n5KdKaW8HdelRf9xtytXzURY
mWUtsm8MIWz0IMef/uQHLfqI0yXUzASY6fQAiFi9RvhhQT1fVRwGvW8DdyjtiTD3bxpwLdChgtoM
w5d1U1YCN7LLfmJUl7xFketajFC+ZZwQHmxA9TS92XFi7lyRVB1o0pPQdQ1bGL2GsJJSHMbcnjaP
FBPnh1bFKG6jNd9coYIpVx2SaFxZuvXFJLNMz3nRWUn3hSgoDogflhk318iNJJa35bDl0KTKStWX
79lAvaCF/CrmCnh3f0M1ExlNDRTT01zeZELn5D00rMraRu9haN2OAuG/KSZmhm+4scM+8a0mCmLc
ZF6QWy4atHYlw6wNiVnvRZFzXErwcjblcKLpHU3BB7pgXnQRTfHawh12TuyEBU/W7mEgKTQJhnbM
wxSR4KGpGAtm5vZQOVKtZsoRNV7/ekWROdFTRL8vU5ESE/tP0OHVlN4ApG4XciMqkBh6JK/cSvY0
GNbDlWmQ72A6QPcXZAmx+O8C0RgIsxelYlbE7lS4v4Wreovtscy/2uA9Y7BhSIQAigpLfKBZ3j4k
ldvVqzZl0G6N6HRri3vqhvd1/bX1+mBXWFGNaDPtGxLkaaTPRqsybHiL2EaGOhlx6TDEkCXo4H8Q
8H/ILSMCwjReD2f4+5HPBWJ7IRbVcwwIVpqJdiGZeGPTBFyYtSqpeIG4ZE4YO7iUYBO7uXDYKGNZ
MYwMQOpoONBVoIrRUHb2zj8aKDMGy1qCen4hPQC0MOdu9OZMCu11ne+4sAomvToXBJipzb56UZtI
edDlJHYtPaPLdv+xc2lRrIAwpvSEJMNGcdcYoOfCk8SV9ePwb2ImtpIcRsmDOLOZmFfDsUsocTac
OVDBm3yhxKpToJaWFu0Q6VSZ6N4PHLxODhzRQjIVcdLJGTtJJYha0E3ABGCYhJTHwEC4LRZyFJyk
1/cg1/LiV7vEWeMZo2cn7cfPIFNg20fq9LM3/u83wvWaz4UbnW53zhbxVm1jpUDxomf7KFI1hCUW
u9u55X7Z3F2paFyRnYkPPDXlYybj2Wn6r7t5AS/X78+xsFHvv2Mhsg1DfnGqPNHVPoj2wRMX9VhX
TMoy0aYFyJm/CROkUGxyNrHdTVqGaZZwXA7BMSHIdg+KybG1BreFQLot3u0240afWVMA3nDCTbXT
yst8Abg+u6d2COFYMlC4Zy3hpV7u8vSXNys99UnpLmb9e8O+bh73haAWZ+aeqGv9hGXz24yEoKvm
Vwv6hQ/a88eEkRvkwVeVX/KCSIdQmMnZ72+24FTgZu5sdxqE7b2DywPhq4myqZGoqv7e+DNCk76J
WcMpjOmR2Cn00Iqq1WH8xD9LO+QHQ3EfnREjP5Ca2wjQksVRt/vcq7Nn2p+ynRA/wAxQ24FXdxQ1
jD4WGL+W336pmIn+5iF8H8oSABPxt8ENOA/Cl07KxFPcibwKT4D6LtZmTZC2NYgQInVQyzxqPSgK
hee6/yCyv7Pxftpb34V/+zsgZ1Xo7fWCAZsRHq7kLzbBus53wIRwCI/pc4ZdoH+OBhPh/OdmXcvZ
3sHroIFLi+XHWdfqwzxEanxvN56XNUxZaEUBj/F+aXHke7cTAqLaA86VqlAFDYmM5d7AoAmNd3Cv
ZXDcRGfSiNuNvZF3JGQ+OHaBC6z+l0PacukfbukBmqwaan5io7SH1+p9GLbaByCj51XWS7MjdhZu
XAEa6y/cf1bZNmhWATNb6OlwU3f6v7KN9OKKp/fee1c1jPic04NnHDrTADVcfGFHHs1d5aWFjF1M
0+NjKdfByiOFFYvr6LyThkxP0rVSc1OcaU2ER6t/hYssfv7H8DTm6D5VAwhbJ58bnhl33iEEKDXD
USRQUEKUm8JToY7t7edPNKcbO3/cHMZCc+3QH7qYILfQjZXLCEivc3bNkrf7k1lU4mOaHIkQU7K7
9nxeXqDP2BZYCwGu5wor4E1LgA64kFiTrnKQ1YueSv0iCAzjOiyyLrjLEFOI1nQkyARV0zR95yk7
HVNMo++uSMboaYh1MKLqskoyeLn3ypplXbzYX6GUoxP4wlHj3YPDUxVnmSPM3s2Njwn1C1XlNGR9
x+Khewzh/M+32AgZeUYS4jjhlSVjwNNYOzz/rOo4zNLcH0dMh3xEr8cDgN9nN5EY10BuhemVAyjp
qdSnNi6OAw7m27B/Q93wumfD9J7/FPYnAG2y+Aft5Cn8Tr/PFPm1hZutMn8KLcvMKQ2brZyCT4aK
m81uQF78KmGHdVpFHnvl6m1DzK/qqzS9PiRAWwAT/yeuZWMf5G93gs7TIjCmAXh7gXGNUKaD9Q+i
fZOVAQAVTgUEFZc0CK0Ke+opr5j9Pc4bUpp9X19YPVHwqFmIAVNKHE2XR1gzDTMol+v3G8hVAucP
MCX2pMnGD2gMaxavFVIpImQwhpwxOu30kc93DAOgJR2jbbf1d5A36ksyzlT3LzqvAd8vnXRAS4o9
V2Mm5ozZwPJHx13Zr60bjqFhY5TcTVN3LXIj5ys1bKu12Ag64rx+Cq5ML6kpOVvBcCvtiWQGPWup
pshzch7p6j8oRh+A+mdybwzX4xbwcknbNGfcPGSbjcsEUDS82or9sE8oM4EDZqwHT1oCurwLdGGg
0f/sIyU87HSXT+CFjxUfuixDr2hZHHjfmPGJoy7QZykFYWVkriyJaO0pZxs43O4AFSYu0Wy+iHkC
oEWn8T2F1F4rNLZyyfjhd7x7I5mPK+ORhPqtkbMqOZygYvDganfJFM/fLwcaHB8CpAXGN6uUYvVL
AwCSRx8zBRzRyMf/ZqZexMtep4QCdSAhptnPKh7AaDddxxK1FgbbXo4okxXhAr4SYm0LsGTEO15W
sl6VQZwqlYBx7DHAzEv6SZa3sBXEU3+4Itl7gQ0VnYxExyB0yQQl0n4lRFUQwSUgdignS2o9c/+j
vkKdoGdyjHY+NWgXhbOr1kzFMmdA8xK2OU13ZA4199nvXzzO5wEq59RuhqlF/5pANWYT0mOu0ul8
rz58NFjaje7Xss/sw7KSyC6hPzZ73jYsBK/QgaAg1eldW53uU5G9CmMnUx8wpSQ0+8ZI01nLfaAp
sp6VfYKO3uXSEQBahxiuly+fuVYVtMl1pn5j9s48dc4s0pBaa+pcZQVVtpEZKmVDVGEsTKkwAbrN
qsIPRYWnIm589d9wH0KQ2IqnWFGLZBwGe7YiKwcR4JtwfxrizwOOPB2ka1YwFG1CIddb8rwrpM8T
6DHMW5BiXF+s2tRXguben/oUd9dECirl4VNERNXfgOQOVmAbme1A8Ut929eAb02YWAOScJ22UPcQ
iPKd2XXzHlKSq7eS3DrwZ34C7PNAYDCUVL1xb/Qvwp85QUvEGwY3Fjsqsu7SziTUC90dhQ4pdbcH
y7yY3BT5rAZA+DFOqsDmw/1fTSho5cNBXObF1z0Rx+8bF1X3V90klsQWjnCXc5+xTVNSBzXOWXiR
8jEsz0lO4z3n30U7K2kEag1kJbLxHtb9wQ2f9AU83xdXjLZiSqSNpMiUgY09PZQOE0DLb/08Jsfk
SDyox/rntXa1xbfwDCgdaWyJk/Vs3P3j/BuWrKApB5T7E8YGKsiTwpo5WyytsSzOX1YkupLil2Sj
MqD7/Kcufjs9DLZ2AT3BzjR/1XdMhzww9O6Jmvcv/+2ajRFYibodyAfg4Ce1shDHW59ctCO7qYWc
ebeJzQV9cl0u+NUt9KcSivd3tzPJM75xwDxXjSv6gT9E+5+Ej2jl3afxlJkK8dDpHwLX1mkN18AC
0HgKkYjQVmAwVeROv3c/jNF8udp8KQICnQFC4QQF9PUw4HG3MHtxQEJ91RAYXknlS3FKvoUqJoMh
0oALqx4Kt4BvzeAMmPlUlMd2A7k63EC80o9gH6apng5oR8Bs9AgFHAFzdT2/iLzmqjpFMujd4gWD
Oq9a9VhZmKle5Jsy5Rcs9gE1qv7BMpnvAnpBKzZIK32qLHHsNGaw87GB65hHEMBAKxyrkB/mVVMm
eqEFy8fcH/HDx7UxAE0EONM5hiKe3MpHIPJWOSeLIWFnecjPXrQBVwSkbg1horDzJ7Ieff2UlWUR
m6F0zwcr86zTRrxTkqCk7lijuMUUF64voxqUkYSqPw+WFOKVPI9gvXEdwLhAqflhsZD2rqKqK3lo
tAesqd5NqsDBl5rmKW23/wMyyMJR/+tDO/SWWOnKD2K6ql2HuHB4lvKgmGbqbRs6lrpZdJ0O8Jd2
BN9S2HGz4sFKdkMMd19vQFgsDhufZnVGFeL/sYUnyFfm7g8Nh+HWszXO0ELbsj8gwUeMwnlwRUv4
K311UUEE8gaTXuBCgNv2fdDPT6UfFa2MgTz62WNv6JDu+AlFeWPNOIqPqp6TP7PoKbHB+Hyb8gsi
TmPEPoWuZp+ebqiCDDLEChMtoZbMwmcqMyP8M8M759x4YuMfNqE8zl5iuXy/8N8OYC6rqKBK4F75
+3Tepkuq/fZDaAtcvED/HH/bjhHbyCT9NB2GEMdgffaHBwGS3cXcNpRodCF+rXk3HXNk/v3sfmEE
Ax+PnaRwE8K1yUTMBlpp1BIkqPZnmZQ2wzP3L6pSmc19BjfWAfDt3SL004ofwR9XzMWEdGYIVRh7
Jf+U/dZw1Wz4s/i0t9ZQ6hCAERTxeHE4CMhY66QCjWbfQyn4bVzVyvwcgPakyajNM0GnKROps5Gn
HAGWFouytYxOVQ4c3PIxy/6kVLUg6k1vJRw9TNpO/qJoVavL7yOuNEm7ImoDyALIrd/KbRZ6b3Gq
rBV1W8gx/n3+vQRHWv7GtPZ8VHvaYjJwn53Q31n10bX1wAnzEyoy9YDGW5WLca6IIqMWrA357XII
i7a+hqht8TBQFHo/+qiBJ+ED101So4kSqdyllVVh/2Hut3gdHIurtXmWiZnXZnl0hErzKrtNOeLS
FKVh+u0ZvNcZ66L6NP2IPbeVg9X9fGAHAkl/JLQgJCDQ8vKxO7unCsMzBVn5NWGt7t1EcbY4u2Nm
/nyClIMCKsymdowktLHUeDMi+beUVoi7WcXul3HNUqlbUlgQtMKXS2CQ6VWSe3G72xP4cr+dU9BF
bHPWyMMdi5Dq+Qz1P5xXV4ycdNhKclPVnZu7TMMGsamATC3rkq+7syHi8MsV3iLEFHbL4zrTP5hg
TD2zcvrR8T1HX4at9se9GXpFqtPokXqhiwsop7KyJftWCxAR5fntUuOHQxyqA3zT0JSWt2Gv5OvW
wU4otYk2RbOesXOk+LEBaiCpi53wH6wkeyLlzORG5HaFX9SeAE3tKP1a4e+pcelRiUaTj3hvI1Ij
cNHDTZ6t9ZsBSvqLJdVd899JOrq41N0QljrNePiVzWjQkCiOJC4jvKfbalq8h1zXmClKq6wfb+ow
c5G1K0dhkE8HX+gNcFqCzNl7jWy4BdNhjZO0fSq4l2w5xjt8ObcTRYANR84f6HK90t9evzmaXR43
8TIhyIjrkiBv26CkVGCchSGM0VcSlYBP0mHHz1GaMqutgmur04KqClOIutAbpIUqhq3zVoE8WCnY
WZJvFQ7M8CjAYuMk5d53ts2ZfAyotPt4lRYxmp/gJegQvljnPHzJbqP6FjiumctNiSvplxnv+LuX
22d0xPZ36feX/InamxwqD+Irx4TwnUwxl0KClexCBIrFrR0t8Fsru7JPMqsSqk4Rk+cRhmw5YtKl
I2CaJf+PJKHYAdoaabdPrygui3005j3MIv8U2fUK4tr4uyhdBjEX4tdNmt8OmV0yhLwG6hKqfaAJ
3uDuHDc5SP4FN82wZfDxGGA7MQvkFDmfhlYs0boysBruANaByGoG5gTM1QqNOHcWKciBsWVdQK6T
IV4d5SLLpgLMY72mUUA7/B2MTkgPujq0uYfyW+63pbe8uL2BusKAX8H09xLu74RUh3UiXNXP/lUw
hfJYg21hyc2UZ7kLbZlHrqHkmULg8JFjHJuYy08ZY+yop1x5ZdEiCP6dAXa7zjvdsb4XIlLzSkZB
Bfu43ezGjcjpNwrYdovscg9uboewtsHMJCF7dkHO1te3dNUalUF0rJBkhb7hzkLvoJWMZk4Wd/s+
QteKoK8gpPu8/FltB4e0Beo4l14VnY0/5abLYPkIBXcv+h6HTQHUaOZZExFfdgbt2H/G1Kln+Tnx
5J8dqf8vID6qkeqkJ7Wb/ixxeCy7JGodfdoy2ToFBw/D/d7gYYgJU6ZiE4DfDDQKcNjWl6UcUJ2s
Cs2sSGw59Ws/atrQ91JdG5uOStFHd3VlTiIS3HmqdnCMZu+Dbr1XTDmua9pFlYIDyMu9ofvshjNK
Xk7u77IHq+HqApBDXNZePpw3OYgv/c6297IJo09H6D28VrGKUIqsNq1AsPJ5e+95lD3Te3H1lnOo
zdzXWF0wjelKYkObReHkLMMm8zrY5/+0evrDtW9UAdyEKwa+ihJIjK12pFb9kCaM6web0UgdOSiW
Qlx4N1ajURDbpJdg4s1n9emYRj2lVTGm4QQ2VlTuxsoz9J7GA+mdnrzfHDGPwEFSHQaSenHKefX9
K1vIp05buOXiFfK1iYAZpdqSNXMSYyxBY2Xd3ANGfoHwCSqhtyp01x7oxwYN7uMyLc1mCAcsNS/0
BlqVtT9GkGUBOMyMwRhVMhrv/WQaldLDeCWUBU2WlbWeURVXDCMhayGnBqp5BjDxhQQs1UAMOTC9
CfZApwpEPjO3494ehNb7gD+3LFsE0aPJ9HmtN85cP+6zuv1IT1osi1KAW4HZIwTYYEr5sItXZODn
aBeJ8D5UG9zX9+cfn6x5n1dU6Gpr29IZ4QxgbuN5jDPsreXJ4JbXM75rACKYTzwOJM7G2z+KMsG0
ON7lf6v7ujgeUhQjVv8e51ORlbqtWKgbC4FJKVHUY26nEYWm7t1S85gCYM/njxtyQ3PD5D8GqGze
F43HpOeWJ0DKgTWw8yurCs78GztOp+pW8dgEQAKES0nJGglXPtD4tDEqctr/xttNczBkNHCEB4bU
Ty/XR9U6cw0KoJRSmxiLJxBfz+ShIqfhWlRxkd+R1bTTEkDUEc+iqt3u/1CxZDCseH1X/H+hFJoL
FOZreUXb8NipI4QA++KnD3slgnU9avo6ODv1UmMkIVW/xGOLzVQisIJHSBZcSGrxNTnpZLra176d
KMEdrbgxm1TUTtS3l2vbJhuR7BLf2jMKBmvLmjyYfY24G6ccXRi49Ys3u2ZKE6C1/IZ2zD3C+5Fi
cYcQe/zid8H/SaIRJNAc7YZLzupJwYz+FNIITdqqPkTwNXlz0GB9iDiQvSYyg7HwXrb9jhkGOui9
N+7oSlEuLTzkPR9iG2jdQKTdB3QtcR+35rSafM8h9ObKDt1wadJBJSl1lcpHHDTONALxJnNImIBZ
v3WOvkzklhf2TwfAIruF3X5M/3RGXHBHBwIgFgzqIls4r7WRwkR7R+Ggj6mIIpDsX7U+wFHl5UZV
h/xLr4E+uJ8J4tATb5hsuJDS/3s6qFT1ZHTn/7emSMNO8Dn6umSDET9pzIhoIAlf4XDxSkn15t0v
CA4TzcfaTfeLakKiw1z3wjkzgSCA6QwT0eB25zMipiwPq3OhWySiqZvR0mPuW/FhwlsI/M3EfOru
Vcp7+4SrwM14xN+k8x6OQliiQp7uNaHKiEROJluKWsMnedZAx/5VDt1QKYJpOjlBWwnc+f9kk+w5
Vnyx4RRBCKuNtET4gSJ5zTNUILPCcnifE2hIkLyC7rH4lmtC/3GGRebEpgiZ3zvxHGMFSGAOUqb6
8d7swfOQvl0yfFbvf5V4Id1sx5knxmpOQeuItja0xlUvHtvbuoMBm7M1pZhLI8Pn5NxNEaqU/KhK
PUmxi8O8WQvd+4BFRjT32tqfcW8V3YeN5tmcdZ63UeTb6lSvyR66+GiS9Mbw4Y7Jd00MeobVe9xn
IokUkGJ1wREAbsP/nmsGHLJp7i1E77/qNsnekNJ6dRDwlJkWXqHwXJIlmnh8zUU70q3Z+4dN3ou4
OhoUEMkikMZSUQ3TTKXOFuCNAeqvXGeR09/01taQdYuPLyHFy35sGLSR3USFb6J4HwoTa1CFqDBA
FHNkIEDKUFgvzSLP7MKgPfGP3zwizAtaHKa22phZm8NGjXSKwBCb4fbavWSnObjDUWgYCFUP1grA
tJXatjylw83AlPdSuZpWJBD4U4cSZawcre2XNTsqnlpr8ViFUQza+CjPaHmz38Dh6GV7KQ9RhVdt
8NuMeSXAdLS+CuuCkdEiYZV9pIk28H1CpJzlJVJxHyTGTPcA0UCv4dStv5W8hWFJKTRrrjTbQe1Z
3dTEf/xfAw7CQAnpAr0P9yeCchScp/r5TWZgoYejw+wo7mXgehuEmays66ltsB0Rzq0CSY4UsX1j
muxSHujc/jfarLNX8AbfhafIxBJ78C/d5mwLnr/7LBgWxXMJdTa5QShq9y7pelOpFgbgsIbEFyyR
LEUhPXWcPHbPsRh6Gn9ei7vKsXAZjv+oKrJC1AJrDA0yC5/NC1c//Zs3u+/wSD1f+kUrUvEji267
jrr7IRJ3dPconqNIy9PDPmBIRKwlmc1XeBIskFY/QirKB18+E2AkzAnS4sEsYd6NjRizWljREXig
ucHt/HRIHNWWB+ljKK099f7/2UbPM4idiDVHB3ujsSYlLVFl6d4Tu87ZS1dpcJO82sMkcdRK/M5T
w9MZuyJolnzVGOrQjcI5HoXA0hS75058rz+vaWffuYfzAuw08mf8U2+TCyBPBrPHhqwPppjKnpSz
XtqiqMKXQ3ldQpEMS+9TG7dsN130JpbF4opiIFhvUQM4YFM5Cug2bljkeHpg3cde5OJVoOYGP47b
qPC7OiNGkSfns/JtPyHhxZ/MPjz8481DaaoRcQ7fRvFEFz/RIFGzjk/TSZtGBwvII9/my+/USNx+
BLOgnSEMDbAOcZHsHgyhR2QuFI9STMD6pSSw5pS6D4ZOO10TSJoyXZdJQZUa33Ss75/9DDwiaspX
FoV5ruOtt9QbUjbAI67x3+LhjKOVUXQf4uG0672NV/qXytzYrpzlgDSa5U4jZ3i2gPVp3XZcq39X
0Aq46Ty3RkafHyqCykSGS7F/o36c8+VR3UQxvz47DQKk40jKXGumDYfGGa7iK/TaIzirn4rXvEdl
henWFuLl2PcQ8ued2dUUfwrDxdnF4gDbNLkd8yGe0Tz3f1p/i/fEr4Q491S4kdK8ZLkXpxfFAFWt
tgC4H+uRfgn2582qxxzxGQHx/L4pfFSnm+MEr0+g4PMdzXhgo2Fb/kU6QLy/0UcmXwVfjH45iKjZ
EWz1eOuwAkQI1KeFiuK7awUHFFVe49Ht7w5jxk4EnHmGh6ZUQuIq9jI9GvFYvv/wKjxBbisISPSn
IIw40UrRnz9yYC/2ggqqHFGNkYVW3nBb9v1I2Zgj1R2igBhKLDFJeJAdniSBML/X5jowxPcl6nQO
ca1y89gkjR0Ja+LPQm/vw9h4pq/xxcLv2cr9b7WhXTJYiPl1GrwHPZ9s2cnUJ7HauNtPaWI+AYxE
IGbrNQm5tCn+wi7HOxGYPm+zGSeTS6pr1hZqz2vrt4mIhnujjG4S3bKklU1OPLUURsQZTCNYaU5K
ttGduoqQohcRj5z8rVq/VSKmfTj823oj7kWGzY18nKNQjt1VINhQnDIz8Rzs4fiQNKcmGcHdbi02
7ITbVvRrUSNLkL17xyUWbEKVncN3M54N5ZIzEXU5j7Ds6GwOSngVD2UGH0aar2zjuzNav+wlZEHQ
hc8MEHnfd2xGIR5r0YyhhOuQFCGALnr2I2LMvodNHdsPWLvJidyleNkeGsY2TCEO5QWnRtTGTxrr
PNoyJcUB9d9bD/QI5d6/VoQ6R6icZ6vEUpw2sHLiWK6Mb2rRw8yF32Q89uFV/rgytpKUDM1groRL
hnwXS02RK9mJjodVs1GpkA3roHpXTzAmpaZYM5hPH+1lAozsipa8OvpJ6AF1vBTnZQkrJCva4zzQ
ncAQsfUAXrDqqqYnRum0kEMTLWmbq54PQGU3AlqyV4XhEcOVsbJbd9fJd3JH1m2w0QvYfOfGS96w
62vgEVAIp4imVwgDnSgOjc3chD3zV2qHUjaKoEgd5W/JlPBoYL1PdSJXVcDK8SoBHL4ES8VTJt12
UWzSVVA2JzLiR0sIN1yXuzYMaHK543k4dngp4yT9AZ2AKbVK81Q2N/Gv3gqPDrczPcyjT5MTA0Qf
koiUQmLcz1abvOU91kbUJTs71FyqLAef5hYb9lyQ1irfuTH9si19h/1HSCUyV489it+ZCDXJuoUB
5CGdmtt/6mFg7Ws/eDFu9iQkEtKFz7wov8d3s2TsmH++9c18n+SpECGM7PFMpC4yCGK1n5P9Ki3Z
YuoOq4Vh6qlCvtBo3825zu0mP4rXiMDB72+RZJi5bUnYYcwZ7lC/+aSWzyMwl1Pl5l2zLAIDIiLC
I5JBnemCK+QHZI4LwAdNL+AA3V3aMk7wXZop8m9sRi0X9Vs+hgLshMHSy4NNo+hGkqwSYxmComdP
nGliMg7q+yGGMr2JBv9iZnHxYsDJt24qlsN4/YVftggMNkNcybPq7uPaCQD9fX5mLtJwZltXLsLY
yLsqfAQ0n2S8XHbctHXPrZVeJtx+ugnAk+vyBr3YB5dlyV02Mi4Rh0I3fW/A4ZsNF7ZLGQ4VsTTD
C463ucNhK2XD2csScefZVmVP7O6Dx2+qgSW5mCWMO1/1ASwZy8HMXN0m3/a5uvt75QIam6Q/2kAX
N0JVWPjh7hmDAA4VpJufGgu7fkFN/pt87gv0ilfYU2kuvfd05RYn77ZzV63qMP8NV5zwMymREdCo
Q5NSmJjpd08PkLPjEAKoY9m25gWdr8Jxn5Zr9jB5ml8HfK5qaMcki3yN1E4CFcwkC2HxvlDiVWLt
HyYIkiuw9TWXjQfKnPlSWS5WKlIqGcfTyjA4gIYxMhC3X6UuhLY2m7UHjkf+3hrbEep1MRoqresf
F5kD0optfZKZwFZs5t6geoAfMIZ1lsriv4Pc7Pi/hC4qFId24lW0dib9ou+MXHZ6ruyEOrt/bKx4
E+2NITyj7z/zjqSusZfCOeecMX4crhmqM5drz/O0SEIpTN4QgaVEhmVNs8KDQsZzAO600/fh7NU1
netVRJld9Im9B1eVzeDs0Fe6Xx1qbFKaunbvVevcDrV67t3vx5hP8RurtR492l5pE+RP/y59PIW2
VNmbe9JcEae+sO+0i9DJyjRrdAGVffBOlov9k30StCWEP7ItRQdLoD7RbRLct5gIy4/dtri85Uh9
++NA+YaGbveZ3tDqUkrFDhp7fSswYzwvORfiP9T7Qxj+0ome6MgnXe+HVeLrsEzMyr920Mtfh6ZP
VbCR2Jrj4KdTIEwtFXbiUtzxFGwSuz30EPZ4yQpfTjudycrih48Mo1sLS54fY8ozfMJ5qWMCd86b
PptDBKFxcNMbS8AY8YvYha9SPYUzh3LWz0Lwpn188Sce3/J7Ckyf3P3z8IIDJDkYYTSHnp/Aeiez
NaXcG/S19fzn1FK0o46LR3iNJcqn1/hKWO7CFyeYUui73EnDon8ZDIGi/VG7ZG8ukAUbo2FzmEmr
/b2B+HV9AW6MLC00Bacocb03ISG+9rMP+ahrW9YKRDyDQ3upmJmLgX7KoyEjXfUbiwLY4xCElnHW
tqCdkmiEQoZeEZ5cVeTjKlkPtsjtkKi99nSrsBktofp3zB2i5qNV5R4yefMfa87p+Hug2hshGuxb
k/G1ntLwe8BUdq0uTBuH9i9sqWV4HrbPHkMqsp759cAmOEZUTvSuV878t4wWPkDJtRlIgjNP3DhD
KXLoFLqU9qgWJH9Ykh/dMVhvc3iDEas1ntpmMuUOe0s1QBfajs9LUtLigZ06nrDnRB+SNsLQE17T
MRnDI2Aja2MYssMqG764CCF35ybQlAOvwIUvC0YO8Z+Kg6GoapknocaIjVdhsVGeM6l16bYh3T2+
c/W7Xm2DsJpAkltoRm0UnT73tn2L+5mIGOYbutIYwwv009QMJWq8McpJ3cZsF8BWFUkXbqFyNLbB
EVTBg+kNtGv1CXt6GsItMRcRWXjwxaQ6612gIq3xQobABJQY2ca38CF0bkl6nCMRcHh0rfjqB7MI
kPiMunSE0/ifo9gDi6c3UuKpFb34bXGM3Trx52/ZxpTCYPnQQkQz0Nt/g4UmMaJN+dsrWih9H7qO
IVECkcZbXV02lbkAH04dc2Bo+48usdGQPR0IoPe4A+MQTpr6J9Scjeg/xO/VIQ/qZFW+KShnFRSv
z1IKSTJc/OwdZzShwGJ1sIoHhqoxWRyfNpgfciWW8GVBJ2CDa7rO1dgsLnHFPdCSOQDjaNJoGnmE
xL2ZqHmkIPZTf9JYzx1OAqopMXbMP1onzefOS2iGNUXAMnPw/jH6ImWUaeewdtWMmSwIniPJKm7w
K0SWPDOriGiiQ2rGSxD5uj2iAKjRoHYG0CvI7Xkpx9Kje7xppotPiGwVOZhO0Kf6e0K+9/16j5K2
P0d+/qw/srxZfUipfcODLiFREA81W0cGNHcDo9LGysB2Vt8EhOmLg24izUumPeCybDaahxqP4F7t
1Ap8Dg/eggiMg27GWIJ98nX1TWiRaALLs3Bg5b9UbHEzCN7Ntlfr1biKL2valN0PfKNv5LCuNv6+
mLrCXct5PmnnP21KkZval6/x7M+MV7xjDEwU09S/xCcrZcNVpwcK0+EuGKhhMgz3sc7E/Vl6f7Sp
G/nFPai9RLsH9xUG3Rf3FumSKL32Xu1jiJH6y3jpf4KUkxwiPFGmll3rWZdAIeV0RK/vsb7RD4pX
7FU+HsqIhNHk5yfKpfD2DVIW+HyjSSnIqo+UOXcbEkvL34nqPO7Ux9xPY6fQ7E/wEMJF1Fm/lN9s
6lF6bTLDMPqpnGWlKEugtfcEnF0g0Ivzig90rcGbkmzDurXLAft6MyfoGpQZmu92k53ThCrQ+q1P
utjHGb5hQb2+sBHduDkdhGq4aZkjUj8kDudFkWheuto6Nlei7E8ySLuTn+9cJ2UvAku/pAmidI9q
tzOXQNTnmTbgcTJXVgQNbfYbLrWhFn5tCgpP8HIv3I9HY2dM9tS3ket0lupNnCZbD5QJuNGBBYrs
8ozjVo8e7ERhDjHF/juC4xXCy+ZllCfi7DpfNGk7uE2ow82v52MQDnS/G4iOoHH0WhaIbZhAC8kJ
gNs+/ZjaS6gWJgAHH7cgenpkGWmPDmpz0iGV19b5gsZ915NU4oJslWPcLrOFVPr1iMmW/IxRlINZ
LYfn/by42OV+yvveKsmiE+QEflqq7H3M25xj5rPOTEgSElsUZsS128S8W7pWAl6J6468Km0vgUpB
VyDaCI2rCaOIqIXW9CMv3NleerSlVetJxfzgvL5rg7Z1iAcNu13mFS+2m93f8WukKUF+GqhuY6ZU
AoQV4pPrgCOtyZuHFRMwvjEscnjTQzkI61YjIr+/DvUvAdEYsqi40CKCn3+bVXYD9x7v/vJ1jS13
wtCVQDbse0WIqtCxvRWf8sNmIouKA3YNr817CfboZdfywRfaJ1ViqEsxsytU4d7yuHE1WfHJ+m7w
rrwv4TibBWpFuRBQmnkJSiAsNTHWRsyeiCw0FNEtDSnNQ3VA5uoS7XNz1y7KyIsyn2XOcWcQSEXq
4sx10Tox2/kHC3UenD9J5QYeA0RwicADu2bcrPWgyJzYezoF8IS2TS/r6tY7Q9r0pMSWxe/f9A60
pm66pn/ofOaBTfGfWWMgKuZ2yEG+3hRHDbQjIthUnQx878Kzit6x+OJCj5QGZGq6nfH1wyq69TJl
epJ0qhL3NiRlXwuPDcMjCjquVfXkC7EczGzVoGBENO6uWfRbiWbSF7EeX0EREk70ktWUDDWDvZ9X
6kx5hNyr8PSAoRPnsKqJxCdDEbNGyo+NA1LV0BlnlxfxEFBRg2oydV9D9XyNec7LbWWU1LTthapJ
I/Tq8DwC88Ajhd+gJIbBkrr6LXhQRY/bM8Uhd/nqBWVVNOi1mZQmICtBpik0MKbb9SAWfkJkp+wx
6HYbi9Y3JQjKT2Uu553wbyQodCAE9RPu4w/zgiN6PTtolkflH09mpCXfl4EbzbieZ/OzbE4kxto9
3JGq4x4bZYnOP4NoiQQIF2eEdFdOAGs2vqIif1gjvLDMdirrAQrxyzmmn5mUiQC7EG9mR5Qmx9I9
qI5cYn/O3/eT7+vrSKVmxHFwEU76FryA4snbba7uxsNFR+GyHa32zIow0D/QLeOdUF43gZhnXFj7
j+iHhCx8CVNyhb+4S8qYOGJ0gpd1UoGPLt/o/i1daawTao+PRADRA5JCQCSgwsHIly544/7COyzR
UU77zpDJx3PmU1jLzlv1fhskSfO5F7Ff2/0SRFpQEO9jhCwBcmsvbP8ZQlYYBjAbVfc/TpeL+FZb
grH0tMKAdjoWCtPvmcbWWDPG6tEi+xbmZd0ASsBg8bOWe4alWYQ3YtYiefP0S26pKJFUCu18nGkx
3+3dBq6CvgN9nsoY9whBEle7UZ7zqLCZ97/caIq0rsMQHevnVhcqDJP2Yxt4IGtM68CZqWrFVuux
QeP8SA5wBX2w2/LYwJkscYE+m9pjuRNmZUZyhy3Gdiywv+AO8AL0eR3K6KXkVAFIKG0qjxcoPETo
qj2TRrZbpz2duzBcrBNXNDPp6lz2+H50zAZDsfsfgrxSZRHi93pC73topAKp2RSgIH7WZDB3V4+M
QcW+qJM1IwFLuQ4CBM0ELn5mOrstjazwR7ZuKM0g61p4GtuYIJ8dGFT9LYYeIxGJ6hcVvPlscTla
Al6uTaEMzuD5m6+HNIT8iIsiDhPWFRXUEm+ZdfBq5bL7+3nlPfNxoo4Wza7DkB8knXV8tJc+o87D
4b003OhFD9o1OnE1ha2gxFQ+St6HWtVdX1sl3DUqSDY3OEZ5nYU0pGmMGnKQxOcOAHK1a8REE7MQ
NnvNdD/u0q6EKi0Rm2ifnlXDQ9pT7+kssXLfAgbB0RPCQUrNFXLlpSfGZU2YbEMFW2eiY1eB0EOm
JinKncXIaLe6ng/Va6KF23PQMO8o3vQJvs83YWGSDRK1ABWqn6aOv7JQkc1PE0WZf7ANXkNl7ohO
vOcsNCHtMMzt1nZsQj5LdRWoAPDCaVWfraahusyyUZ3mPBQehIo8u5gwUPJwRn1zq1lnabZYWIdl
k+0LiI2BT0prIbwryZrgOf7zy2kBJh6pACo5oLkZ1YlSB4tCf4qUVAzvWNIwZpcWZH6XflvIY7q0
FCQxHsXQRJj8IY2s90PvD1WIsiWnNlKR4wgFWmmFzu/UJz4bT+1VJvDgSui8cSu9Y1RsvFRxAEMV
dvlFTeexOc9Z24XwkYtAKZbTl/9vp/ShFk87Fgxmah/YxBxOiBe5bd45s5dcDlEwtZaVBND/cxwv
9xgDVhV5BL2w9rBJktZLt1Kdywbdjxd0Sy+JBJYo4QMc+yPmpvGBU1S9cI0h4e+Df8XgTX9NXav9
B/LAyT1Mb1X56s/imMIVrt8+SNzdfdoByrsku85aD5dR6ZBdjK6bgme91FPXPv7whOAC92Ctj6YW
v2KqW5WtMdGgb/a4wbiQviyZSVDpOLkyQSwFzvz/DpRfoi6DQNgpKRoTPMOPYkoUww6CE08xRsXE
FfN+pdmqaia0k3+41gUJI2UP/6bPgh0XGuV2bcjEIRqWdFUzHb7s1F0NcyfLCBv9duND4vPUfL2P
lcqIHd8mtFOv4q2ShNdzVpXnT28s3znyn7mJV0B4aq4jRTMJAQYkkBdSKaKTRLSbabxM8ExMjP3q
CyfhZmfnLxDNKqoT0IMpB3xGvlLYuMz7cZ3KsvasQ6wOKNPNjnUQDfwYOv6PfR1Y705LiblB/Gmb
bvrgqtco0exw+Lf+NJkJOEi+uYS7AI2O2Daus6O6ZDIOQcQ8Th34/5CCFpWSpqMp0qCG7n9uGpk7
WdXraD1UCsnmn56ydnAo//Luqf2hWZOXI6lRFaiLrXow2anpSsVg5cRxk9HiEk9mkdKDUORRFiSO
o3vfvDKz7uf+4eIDzpD+fI6qGAwcEdQS8dC06bF4kGiEl9AEfgJomng4Y0Rz32L+RY+xQEBggOGd
a/OvTJLaEC5bGnoJxlH3fdseMYiJRq8q/0ZmJJooFIEdhJcV4kGl3kCcBv/DQlB+9YgALdfhOu4n
5iP9W29Nwi07kTb06xOD8XRw8v0XeO7IlGHS1kQ1MwuvY1Yrrekzpd9789O0ng160hPRZLv0RJY6
ngrSCslBGyYzLm8x8AVUOGBBoOm+dWLs0ma+vzUOW9yWgpWsfCIcZHbNRr7iEL/7bx+EM2/SeDPf
iUprLxO1Max6IglqbjPKUl898zsVG6mXmiO25CMLUlEYlCfDs0Kggo+Drrub5FBt1Cp3UrBPo1GM
TvR64dU6FxGAgogaX8YiD+Yi6w6KLIHylPdIv2O/6r/OqAON0Xyxi77zWgIYzFjXfQeoI3LQot1Z
CauDlx6/HgSG+eTraYoHg7X7fWDyQIiXdRMc/qwhiplB4vb9HYBqyfMiApfJQtstO7/kVsyH8RHA
dz7F6C7pa6tI9z1L0QJNlIh9lUkxtnvasqjw56okxnPPeEbssR2TzCsFegWIYTeMjaSK1Q6EA0nz
LYVl0wZjHpnqmhSlBUt4OmGQXYBh0qOMup7Ge53QzO1aWjyJf+7x4vebjNXGDBCWq+wPDrc45hDr
9yBD2ch+Nuk+VYG6MEuIfPWRShuuMwWIF93L0opEtlqDQl/4BhsQGYYhTvd4U5e4YoA9sYzQWlgl
/3plhcetiv5q4C34AKEl+MjN3KFK8AQjWdprfL1khMAwwvykORxrHm10ro4HTI7zMKVDHkz3y3fF
gyVFRuFuX4MWyifgzIGvMrtU/dnApThOl/uNZi1s/kJXV8LbB17k1kf16t7CUvw8Ujy4OADVhAcA
zouCuzUPj3RHDTUTUU0Cc9CoX1q3kXm6vdQapBREq+GjtsMHfM0jVZ8WzmN94aIhr6EryNGMlEW0
0nbM28bU2MpuwjCmmGKp8zrzUCh9IufCjfcQMfP/rnGaTAUTktLY4CInT2F7pDZgfag/MPpB6e1Y
qJeZnxBqq/B8CI4B0rpJR+mvbZ8rKmRUO4jFWqPZbkSlTz3kz7m3LclH51PtGis8A98jUxRGooqn
NZJGC+417Vf2P5Qacwo8v7XuKzdT5scX8TimiA11tY87eJvYon1cHsSMRncWcuttULkraDh9b9MH
PMDzCHqGuM4e+7SPVBk9PS2HbFpf5X2/eQvKz8vPoXOV9W9Uc7DL04Et7TaKt17Hsy2oTyQCdMfR
izeqng4CxrxXD00yQ73a37NIyd8mguQGMw5L6u49lD1YZat0kqhmEeKtknFpuEZcK6U459wXy11J
xCoAsOszo3/s7lbA+94lmXKCqYWm1dMmdUg3//JJUMLXzetoWM/KVsvkgpComcw12uA+Gdcw6yp/
B5lC8QqVDhyMus/GuScinD24eFGantOXQe5cXSUN8rHqVnr7oW6BYnSfY87l/bx/ZT3fYu/7ocLj
VdEYhrO+doBLJQr+Eq7h+a3I0Jcb5jQEhSDBhnZc/lAyOih2N7Uen3GTOF8FmeVCv5yF3gFNOc00
3lg9hdpSooVbMUz7fYalCHtDkvMS7SWTe2KAIJZRQPq035VP92lFQC9VNWn5Vx7uIgU5ojNQZAti
3W5Qqb2TPzQeIgYEDNOu09Hn4o9IJmlaWea4OXdetN0dkirT0xpLkCrqj69wXqzj2gwWhwXLHj61
/zfJ9jjBEMXjyS/mBdyycSwMnyGYHBxsREtap+TqJhtKCgdcrXdIrb28ARaOCGkDngvDlGraCuKO
UHr3ODmjkIehveVQibG3NPJpC8L7JJlDRhTec2RAa706VpSZTKjNQGnCT1ckeHQwbeK3Mgwcr3Dj
LpeZ+cVZgI0eCILPYwBRNb6ki3UkZrHEGn33SPS56LHoQQkUzS1rxS1HwFdcagREqULIR8zWSXhA
VSDzsSufTkPBNhGbGlitscgP+8NNhJWvIbPzJQt+2ctFNMHFlk7BEtqPiSzxETflGHJm5R+XFlhl
XNPootbBumdqs1pHMbjo30Ciueyx+2EpsKfBSypn/2HMLvFuBT6B95hn/wdhbNoVQp3j96JwO6HR
zViWcu71j2KkqN+V8Wkd8AMfNCxCNgWjydrjSWmm1lJnodTI003LDb468Dbl4lZukOxN4uRxXSHU
NtySNR+IpLwADzA1c5c7BwTZBQZ1r+1VgDcbout2Z+LL9ZT2s2DzJylvTx9oJY7Q6BpwShhqjYOZ
MLOWbvxEvt7+WB+w4ofpMLscTZISwu/mukqsnUUyXEn5fOsjL3FevXx538HfrwJM7wQkzLPtWtve
Va9U2N0U+6x9hIa1oA5xpeeuKYBu4GEnYl7xBBX4W/kr0C/qGIs8VRYdkUjWaoYgELuuAfRzlB8S
EhUMplUhskD2qKVM99FFt8jFqTJdRuNArzrdJEuUx/e+peBfLvMA4y+oHXIpniW6RTH+Wo5FJ+Ny
dAA+3PGTom3SQlwrrHB7xixliuKaS5A8Kyp80AHdJmbSjphK3VftIH9qBfKWqXKKoWpOfTgJrP4i
d/l/CBHde+xVgInuz74leJF37YWc4WIv04HcYlNK9DaEiKn9gc+Cmc6P8JdGfycpId+3L+p5gA2/
YWcTSOiERc4vrAkpoFULNWDAsyCRLiiEKMJdKnsNzC1wAi/JlbnFe854thtAychM6kGjWvbBAYtl
9jn0todmc5g6rUw1dhPlGAlVIGVstxOeOQOZwgeGZiPL4U0ho2EyTUyVcDoFfPOqrh5zMViukSXo
1ApDl12SmkpR09Vgsor6sF2Zy7hXz2Cb07hhHaJUjPgAuIsYe8msDITUqw61/n5MOrH5KXNDS01+
TVGD0CQlG9x5q6zoFkXB91KhHjISsV3AmsShB41qqQeO9iqjlaVx9gRfRjPXeIulGFfRm37FDNXI
Rh6NAkbSqU83vAIy0kgat8o4hZ/Tv2w8NtXL6sH1ldlQQQ61gwkq9lrStD5Xbj6OKosk8De6KJ1P
4BZhQojwV/gyhRBz37VuFdzIhVi5IS5JD9RFNqZSM3L8MltRzElrv2fxu5AylMiLZJK47AtAGYHf
JHf1MnWVme/6/xSwzldW8Gl7eI7jut8Vwv9SSCDt8srbmsUbXRbc9Z9ijYHStA+UG1keQeyQsYZM
LQckDvC1O7MS2no0/ZnLVgmIOmSJBqyHyY9xQksT60RbQssmOC2MMXumoj0VJaxRY63xccnmuAnD
oU2J5iMHCPWNbfhKBbfCQwXTrdOU0bq/b22ijFMNiBPNcL7hzaDa3gRlF2izZfd/T4oexYMdY0YL
EO3PMsa67xqQaU92QQ/JSFB8Y3E2ke8cPjTG6T91h5MPE7YtRyvgcE1iiYmonQy6iZ209gPAjWLd
+7OpRAf22bD3lKfOM9n3qaKeNRBlCt7wUHvsOd96Xl5owgA55U0FYHDRSqi+NT8BM7eRDNNNve38
51ymZkAq4+ZtRMCUGULkugmRKG5iaZ8rMRE5yxXr2JisP2pbcgroeSxLZhsUaBs8geYmHfeftgU4
V0R5KDcEzZtRJGhghe1rP2LJaUGFd2vEUjCOlHiHiSZDkctydOU4ixUVomST39/54X8FT4o3yqft
eGG7rjKqkMP4cc5q04JIyZW+wEmrWxWqf+2Uqy1KA/LyzehMaRVVCruJNU5o5AeO+9acW2G4v4//
f2Rr7zWwEFnR/FX9/Dktel8TZS5KQNczx+i70jWXHCS9WvtHz7ZbBqXXI0Td8ahr/Dg9t7mBTHZK
Q5pRhKTABv6RANtgn5B6y3hsmV4kWMOWyF64j2w2+7tIxb3eRf6XHK6d9iCtDIaqP64rBIVSS425
7/3O/HwRHqeaeRaq9qqCjY/lGE6fuV/tBUw42YcTi6pKrxlSI3ii7auPfB8RXK7cgVvUsCHWapy0
JUUM+BpYqdW/B8PnoT0hyibJ0FxFmPKODxMQEzU8BhbAQXYNfrBw+6W4Oh0SwXh/ktBVLYSF2Fv7
wU1KMtfdAXvp6rN5Gp21qolmN86c6nskQsWM+OOAU+uGMxCIlw/PGM2Zocm5V1usdNAcn5qxvVqa
A2qeafnqwDiaae71WKYntp1G5YpgN+QgIyQItUZrxqRWMJkYy7d0M0tTnhJYbRFi6vo9MWA0d7uT
M8mVs74/kjC2MyQUjDBxLRS52AmUwTv4O9OEX0ZTK+8lXgszQgiyhiiWyXmjzT7dSCQLwJLpaFH0
spVHOIkw5yFk3p+cf2cYAaHZEzYZ/gT4ddZEDbjNfKRXeDEty5H6CMASaPyc9EI7FU0CFCSZDkFj
0/+OUgVje82w+6dxoj+I7bcGSprLTCO3F2dxZrg7PaowkrrgudBFWDgvwd6DsgZAcgPDpNjlJIzo
xWBrFEMGcjSej2qRoE+OtF9ofR5eDKr2H0LcCYmEgN3okjWyMbvpfIcsntdieV/WT+4AwVJgN91C
5Cji0XEd07TtMpRYKyDGaqiUVMh/TWmveJZW0w/xU54gm+b2tXw9XBpk0uDHZgYfEjesLwCD5LS7
OMpwMfVXJU4ai5zkIYWQKZ9D87X9nqp4vWfDRrTC6/holrQB9FOIMfvV1ffdykEAIsWZp1o2QThm
qsYA5mrOUgpSzqGGPlgUj4HKvpxbIz7XBPsamq1nDAtdgaCqlXXt3Bz8ZJPeK9+7K7CFFWm/10IY
v7CGgx5INpIwOY9ArGRWui3lRn8lABineVJdJ00Q2+j61bMsjUozs4parj5hMUyyaYU5Tbgj+4P9
HN38km73f4jq0SVYW0WDxb7rT7OIwHWDzyZDtmuC2dj8WdxYATEk3Hz54hcrtemNcsZckfF9dfpB
+jAqepCZBWDnvlYj1/TkEUibk9ySS4+ITdAQ0LoucDEY6AW+TTYw+8kfc5rODGHX/xC+h0/o0KX0
tbHr/G3IFQa+/WK1X6nwS15XMWK4asvS/1P38HMdEUyeWzdQSd3hm3+Ih8RBmF8zoFFAds2Lhkuo
EvKudzDuj5GsenAClfd9QRjjdSC3xYg6agI4KJQ3lg8/SnVkMzJcaxNXrVVl57nfps8/nZ6D5WWl
NdBycw5dGxVnMmAvFOKFcyTjp4S/Y7ZopWrFa/BFcLcYprSNcq6G9LqaidGZDcKSVnG5k61ofKU6
IyO7qUISZ3TYlNuBc3UBP0t+hXP8SyzXuBcuI6IFlMLqNcVrvGwUTrlNpVq6LLiNNsuleZb9Mk7c
2gMSZU4vegXcjAOEelR8AwQDdUvFwJ5dLCkl9+MuO/xaUXEaLt7eBJLN0bf10IKv/PoOW4m7S1vv
cxNBHwR/pyIPgnBRGHbSqhwi6uykn4TCLx0toeJ2YpEzzQDA1blimdyIg4BJ6hY4fgwxZ5mJb8yQ
9rIsb16cOMKnQo0leHnrM9isHS8fJKoPyftELNYKDZLzIhqKnCWeqDydbDxeawb9/3BDeUbWaHU1
qmAVJe33iBafsM1SsYGOxXVZMrPwlqkhnO/Yq+x6MxPbo7xzp7eWCt7ETF6lr3Lv1Wuq1HV60pPs
2Cs8TRyGhEES6NkD3ukowh2920As8ccTUQ6eWzbVGqaAI3cDzK6gh66xasIDNGQOPisb5eN2aMwu
DJ9b55Y4w2KVN7uxI5Rn1LkBOYKtG2yIMpIXdCwqzXaFjKMch3/9tNEPAghiTeEdjPHHjimbsEgN
/9k9ERbwHIlQ3ZivwsQb5fOnNWH9vkD84vlkPQqkz8Z72S7Oy39eZNN+rdPELsi7f8pOI7eoWj/z
sA2W2EjLMzFnEpmbbVOjFt6W6jYN63RTwdACBspH/dcd54D06VRfTngCCDIeiDUL0sFZOB8suH6F
95+ivAUqi4P8bgO54UuI32m9m90bt5Aw4SmjPFhh0+Tqlns/o0wGejmW3c6celQ/HyjeONlyudyk
YHTVFj8KjsbaYufogkHlcKj2EJng6O2RTQXlH3EQ1cfCqji8wiEieeCj9IYE+yL1zbAMQ9LDSWr6
ZXsf9EX0PsBMQU+SbJlP9CwoMP1uv2t+7fA4Ma4wQOhtw6T+6Nknod5TzaAYQXLctgNgjRj3csYc
ycDLk0aU6VOdj8vFFj2U4VVlTFUIytMjsDKND+a4X2ZnAtFlAMRkyX8KUEqfVUXpsidj5HqmW3eh
lMXZTAY3cD6XjgqYba8uY7My13RwXOdyxUZOZPZoHUoE6VklpmP9mJd1ZdtV7wapZzYR0g2VAggR
uEYDR2X/lHRrOg84DVDR0IGdsyaLnmN7PDDl0/Ua/zfIS4Hc1NHwNBL4Hv+5rI3dcCGPiifYmkE1
UgXI+eCgxy5xQgbxno3YfYS4mdJnmyUQKPrrLPkERL4uAaR5DgoPSOI/uCtn48WORfycyRKCb6Ve
syYG0rh2gvh21bzAo4vohuX+Qnyc9OhAZw2HpxC5i/6+7DIrCdzJgadOqev2CC2YKtLLELdzMkFd
NfgtefLxrnoK+pk4WJB1NFC/M85DgFvZGWTFtERoc23ME/hcDQyDlDcDpXVhEFOLM9U0V9CYFQNi
FIPJ2OTxvhigMvMQjOQK9BjxNErv61ORyx1uBBvlXOef13V3Lf5+Pj5SilIprkOIAsq2Y3wwUhP7
BW2+vkKxWsjYkX7pMaN9FEjBYOCY7DgavIsCqfYsSdtvU1t+U5oMI28XgDUESsaIsKi4hwouu2uM
dD2i3vBMOw8Y8xAr56shTMI74M2NaKBbHH0K4AE3Uz9NOnNvyFikqmgWMcbU9RoBXDshIhh8GBeM
0yGSXiFV4ytJlO5afV3v6xxKvGJ+GuBojtPoFmkSeLSO5dfUtD1AgDNSlkiO0LmIZcVLzvFB60JU
Bq9WZv5GS91weButPRYchJ5IqYhN4CZwvnTILkDXtFNR76852igh/MaotFmWrZTiI1fur4ntaDw1
+LifzUu/VUpkwgHpjtGLUliLY032AL61V8KkuuKOwP9BqA5cfTvl0mUzKIMbR3uWP9nmtKu0zecD
Er8y04jBCsAppUfFwrai0X1BiDSxv+YatwiKOBpW3swMP4IXQoK9jAohm/H5byFDscE8UkhDKlUA
u0rOyIlVNqgAGtM0O45JWsSOPnrRFStHCmuTdj1V3yo4r0qrHM0+xAgAN7FNsAdAPyIdHwtDRsXK
ks2T/XR3XN96/RIv2dHeqbwxxL2wjuSI5U7JoRxO5EpqdHY5DGm5g5vcyfbpQObglpLxe+6AnNvw
s7Q4NmLnarf84RoNtNpy8dBFLJCa3F/pRgNZycrjKvkKeg+4sPUiGwQgP4CjhK9ZaN9cQuRVCcU/
k/c5d36r32N65aTBmoPZ2S60rSSvPcB5hOJov88JlRcG8n0siCsO4wcB1JbRuKkeMy7BR/pPgyEs
rhzIME1gLRT9GRxspa1UCVKrBMFIRfuBZg/Z+5dkfPFBbX1kwiFjVPqqDsInCf0BDUptoqek+UDQ
llyqtuxjb1m6AWbx0pl4fnQF793lmMEhPwyKRKYFqTe5IDtlmuGEySbEE4CIaHF1ElnPNszMWJc7
fA4Lge037rMzjGqX6kNA/TBp+GR9Z53n4vUQYXInte/HZdKRfrkE2Ht2gdsutiuOBCAaVDh8Lovk
7yKyd4yZe6u3mTe9AM1wQVHzEKvHTroPuyWnTGSFYYvHbvn7EvRZRbogqNeY7qxqRoN8vYbzjFa1
lII+o6Mft1IAEoccfRgM2MPI+mNquDVdk7/spV1O8RkIbVZHB15dHlYGhY3Rw0g54Q2a6nbFbH7o
4VEa5Meat2doo2htFukoVeF0AkS5SrFUDtmUJnDXOQzu1hwWvkdk3QyWPdBsB/+46CQsrUrOZuby
VzI7Gu7X/VVOwNhwZDZeiCG+3QF1R7qA22qnft6JkgAx+4OPLFrdLDyeMKjRrGYdSuXX6smimuwh
zrNFu7zXPOc1qGN560O/7LBt2mZrEWnxdgwfrJf0zwbStvc5JXrk9dLXA48DmXSYmIIrFWtKjxBi
JWcPP4wzrZye0zCbtWIrE58078YKRm56ZvP4ygRncdFEFIdQt0meR8ftE3Szk1JXJouMeEHmkgN/
7J2Q1p6eYSn5AtjNJANioo+Gxm4tHMYUzlK4NNHtmUhB4YLqV/vt6F/0JuzAfSJH7Qhxt8dSdjdV
deeOwiM4zP2cLuNQW0RqrLD+ARx6ANNd1Lq1qaQaqUNjW2GGCQoZJX+d14jUlXiHzC4Ix1d1jfPH
Od5PlPD2qsWqTZaTWrfYtC2/yEKkIqgOSCMBMm/6aRlyNPXiLeBZDUAQWUaNGwdys/yn0sN5deTv
lwJr/3pgAFVvNLB8rSk8WAzl5zK9k02YYCJqN1OynqfDuDdOppVbs9iApThD4/TdsH/iAcTskuEC
53mFs0PTtmshTQHOIf6IWZ2gowSnnwZQh5q+RcxpAFENbty4Oh0L5JTYcMaT3oqNUblPeysCD3B8
3k3aMI9MTUSKs3OmsnjlT6qdQZ/aI5yH56MClQ8VLYjAauRQJpgcCcEIPQKA2mdhHL4e4oJuz1fK
S0T93Kz5dN7VokOgqO5AZ2aI2hQR8MvN/Xnn6lTN+aaZL6T/wi5uLJCdvx6hG1l43hG2IBD6H56E
7S6z86Gj3LoInmX9Lc4AIjOmK1lHd2kNBG/LwJ0mUPWK42pR3rZPx63YKKVs2brdfc4+FXtdZblc
zWIzXXBpGG3afXl8VjtZtEM9q/avJtidfu0O/7umf0kkMjssgmw2pUlPMl1sv4eSAbTf5Agod57R
vyAfhTfOFruIz0DneZ5NmmIquOjvE9tVugRtbu8rhK7ZLKtJJQPOYvayqWBUtMRi5GsxjhZ6CxeO
IfnhBUFbYAQee+vmpAZIW2Wsnhi1EoJlxPh1ZXBawaFey1N+mm9XqCPo4w78cbxe3MrOUdhZT3nZ
c2XLUvpKC8fQP+a1H2xZY5PQhIA8jPAv0a7yHOSvVWDmwbrs/2ILeyQmiNAC0xEm3B9Nr2UoGeGp
H50ubmNSLJ85zmM0I2ue9Krmtp9rzWtAapeqseOFWEmMUcfRlxboxnDJVD4KQYMLljSh3VFfYHdC
4Yz7lIiUQ6NLGfhKT0NqnFSznE1isJWMqSHlOEu1dzb51yXEHEf59wtb4UfcHaBwk4sEbN4wnltV
ukdZOftgZ5GwfNhyif5gQgS+sfMnpSoXQVtVsikOHFLwnTTWapxixLxdR42p2zueITx3FotY3quM
XE9lRJMNhbpM2+dKc9YMNypE05ufTHr94wgtm8KycDbxo1iNQpP8tNxUcLuWZBWh4oZSNX6EVU5T
wgeRgx2VOGgjl6vFkcTygsILUd+xgv21YnvND4Ht8dPwkcWuSSt5dLo5XvUvHIxVi0jIeOyhnkyT
EypwlXJrDCBv/mdYvM6V0QyVCzCu6uNtVp3Z3Wt4vL/6KcP7WhqE6O4Ar2evR5nHZLtOayLx2Fcc
ZNxWFyOQZ3ptaqokyHoGk2p7ybCwsoKR6y90roWZ/pxlIfErMc1117LjVb6y8VqOY2hJf7M4qbr7
o4/DGivcjUQsVMmcx4QnppZE+GYvmplxRSUacW5InOKnmrEkv/B7ly65kYJ0PfUz88GXKLfmKRY6
HBWNZpiprxgYbzWJADygKsFqtdscXUtavMum5Fmc8MxN8B6YXAre9wPs886exFi9k17I6lvTiOh5
fb1kP0f/XIZ+CdiGaq/fnMBKSUUjA1vh60c/2gW3J3uaNUw3kSRK849W6Bic67wg1mkyqu4mcJiw
LtMW3shzucrsLMMPMIgdOR31KaqIenIJLe7jax6IHwG2zPaLTNJKpHamaX3h3QyQqqglj/VXWS6H
pw0+IkSrkSxp92uAmS8sP/2J7uVY/1HZnbWc2v4LdhrwPf5Ny0SUBPSnJ78oZ6j556x0SvS1CTZA
qlXgIZb/98XoUW0Y+d444lr7O01cO/eQ4PlPyg2GXJ77FQ96u5CvfxxMVz59GzoKuqRkvHeD6X77
m1frdaT8MZs5n68yBpA3E6aiFwt/BGHigsqEn0gSe6xrL5OI63Vbs4/K5N8oxgB6jR47Vkedkkka
WZ3N1mnyen39ibNvS6ZNLQmHFDkYFWb42bvKcivbA03gjqPJx1ns5v59w4eS4suE4H7I4qJF2GUy
u8bS0GMytJgI1q/ZjUCe0OI6Kyf/1es3ujOqqYDg6YmiqN3vlwdQn//tDxLhTPNOdjPwz1AJ8YEF
Gd/OaMqM7cNoqUl8c2/GV35wPpof7bcX+jkDRKU0sL52TGzAAZpI3metk27+NaFbVYZcxD/3RGST
4f5l0780dN4WwgoT989FiQGIVfASNMe5RkY0SfFIeFbRItknBvyShCAtlrg7dZlvF4AdIYrAV8Id
Ra731Db0ULACo+weEYNapgZDOQXQoed6Y4R0oGmm7Flolt9UAk4+SAMHIGUn/cwjS/xcMM9gjVLq
yOs6DwCJdr9EpFOgKf9hCcXC6ywJQCSy62esKZfNZFLxsOm7Y/x4KV9gEzn/u+BPkuvKxW4ISYQY
vDwjwzm6jeLv8FaeqhAiOsRJ1OPYZQ2vPZErSYi13KVV1IpnmmPiZ604JLZsMhxpw6qV77X455Ch
K1SfXOpDqe96YJOykAlbtqyWvbUg+aX2BlQK2hwvdoF3cPvq7Hf4LKzafaQsuZGK0wae81syoNTK
htlYyJpWBXf39QWI3WviZ4IVm2QIGU3xXi3G1htSFeBudCpappmO6rccmmyxML5JyIJ1fOhz0gWe
QsD9pcSi4kjRVe8/9f7B3NlNxDmJNvGF3gYZsT95auyKzYaC4m9V+ITHHTx+b0D2W91Lt/pSWy5Y
dBkwYpGPxgkZOhlqTpKZYDwCbK9mjqaGYRnEo+D9RyVat41ScbhvBPsnTrnwebEmiNlyWz/HmB5K
8E93RiClPlCl71dXJ+FplLRfKKg5H2TIi97lwvlMvZrs4WQS7k+7tpzf5OvvyCa+KXtq+IC6lCdm
rpPlwxIgFk8LKfBJ7pYYyHY+7VoDINwtUwiIJYI12ozmrqx8BJP/diuXN9WpsuRxuRpIfRhUXJqx
fuSSQ3Emgy5JPJ8daHdqJzECH05UNiXvrILkAHk2HiIJgNQ1gZ7jE0xDu5dTHmMx3wXm+Qnauecv
xh2jlA5jzqMoJt2A8t1ADOA4NS9MUI/GFxlxBLWivE1HPWkMKKvpVIWAmh2ZFZfdvLualyBpU0p1
kuoMFq0LUSQ8I+nOZwCeM4L1V8hHoK4zJThWQyP1Vpjt7QljqVhyVSfx/wSfOpRbUMMvwJM3NCov
l8Y4ClqWoYB+QMU/4XDO3qXGk/Q+NenJvP7hcA82gpV2BLUr3fLJXMuxTSER0E1oKIzfyrwQ6u84
Pjf0nKnAr5Kw3soGrt8OKoGsW9FmqtDTU9LdIFFDzv+vJKgAK+V4WE6W8hD9KXrLJaVrVFfICa2B
Ww2PlNACnhodHFzgtZekcw6h9V/hy/gX21bjbORKt0KCCz1O+x3RD1xcZODwd0kqS3yhNHIT95qO
P2U4lYFxEN7KsrNnk/PqYs7XkhNznYSCnGUdk1sHD+9ATP1e0IPDeqhJrlNwfc5g9nIDq7oZhU1z
OO3sLYQ/fq7IEwyfV3kouy2lMPPk70Oj5B+9BOoWHIWC5ePQLQh1VTp4eKc0EfSWbpMA2RIWV9uE
PiAwdgCYoH1hVRTnBk8Bu28/zODhVNT6tcZYG5DOzecjR24UnEordGq+tcAvOnpMdSrCRVTzRGoP
uuAHsANunw6JcB6ePawe4uSjTi/8x9sgYOJV3FFxgC1cN5ySjXtYLfkMdPIbMIEIdNNw+dhaUEtE
LFmDdfS/TMscH2fwSmgwc20aKiJricQ0uc5FKgLxKpEE7CGi/aoTyn4vniCYD7hjTlaNM6Ulm6dE
JW38Zhl3RvvWKkESlNYL/OkCwNYk5FomFKb5tnD9E/22iiCaDmNZjUBX1fOFnhXZjcCYRACTPJxe
gRPtW13loy+DIjYPaD5CCA/tDRSRbpixOxpVPK6/CRNdRTXz4/ui2hUc7MRRmU7Nx4ZE0tzjyCQD
1Vja0dvf7cdQu9PI4yLphgcOKKp0xTnsQE2B6iZNKp5FP0FXfDkxhs/D8ms7ixF5IfMtEgCG6sVP
HVc5q46ll78dASxe/O9dGuVQblXgAtMrxuF4OAqSe6jDIANLaG2aFZcTPBxvByQ/y16PDXAFsHgx
J18ztG+nUD38E87r4QZIcMGql4OmKj7munylXFTunwM45kA/lojooLU+afvhkkejugm9FT4yc6PP
TSncZOWB/zjYmJj/Ss/PzRb7BTjAY75tz6bsK6Dq0mjqWpdoaTy9VGcaz9Cg2EJNEJSFttV0RAD1
b2uXLoCBgPk2EjJ1BgDkp24xWxOqBf3NvodH+baJcXNyt5QeENM+WTe52t/eobInGiz/VBABwFqv
wsPO9A8J4Dfp7LlrLocP6ejlgcmRIlwNsFBSkM5UtRiGpr4pjvM9fdjqsIXLIJi0ghAiqRUr9Ruz
crtlNqbVEL6Lug5JyF+cwT/zoOFyOLHBaNet9RMvlKpRs+KEmcFjNyX7JZJ1XmETjmi+5P9QKuk3
Y+hg1cn20OooREu9D5oEI2cFu9lUEXkHAGHMA3o890Zz6U96Yez9ffDAXN3B75b+1Wol/uLTs/vN
C0ELfy9g9rh3QkPaub5WgaX7sWVttDTNTI8FKkXyvBj/N4y99zdR1cNHZl8/hK6wNy/7OgDZdB64
Jcdn4D1U8mJcXddsMZaUe2LGBZ8PD1HqyYGJg/R0+BT6XlDLpF1N1VlOp++csqP8TJo9K8eflwYR
KyPAQYmIA0XJaK2/hPa+45e4sA5MuYMoQfODTU7haxR7944m9jQTNcFgcvzqgRN8brTOtGk8ElXc
JUZtq365NFER/HHraq19hsOTGJJQ3zj6BnHhvPQCVWYYOXnqvQEba6r9c3I/YjGJNBNtry/gCMRe
EzURT12LpHnhY5Z9O7ahKmetchR+Su5fL5rC2FjedLe63kuLjHk4X3w5AplMqtjgSgcv/WTMGL0g
/yQaMc8ZbdIJYQ8qhhKFaUo6DYeTYeyhnesGT/qN0eEOuSBFH21k4SYzmr9mxwrP5fzbVLjBKedn
DOxNIDP0LdYi0gWKb41ftPDwrsTG66hpI/n+57C4GGKV7Psx1okNN3mKgGyWxbN3jeKiYU/mctIl
PABuwLG20ZZbj58mXGENaN8TxNDdq+UX91x3bMSWcG79NNUOKm2qHrBA2KGAjEs7gUpR6pBtv3Il
si2jUuW3bDTIY0hGZGdQjkzuZers6OoNMNpFcAO6Kxy0u7m+z5wlZq80rJlyNOoQpS8mM6bRvuQQ
5SMqiCDO5AObrkjlDD/gr66ccm4LnMuj8hK19eT+YtfQDoVY5Fp/JQ1scRW1A9ko5MYaEHgCbQBp
t4bi3fm1jOSGpcMy+ac1EWBLvTwq4TYmSRtWnL/8fHUhE2aQ+K+tNW9rlfKeM861KEd2dG9l9M2x
UaYF8W079ZqfSeg6WDu556R1BaZvdxAc1bEMMlhOvVSj8HcpKxtky9/p8VgL5Xbvuw+MMPEh+sfx
kSnYzWuVhBxI8OJmYDtmTpjPcPb8C1JpmSDYIpWGD5tgOXVFNVClX3CHm3dIgdhx5MbFXSNqVsgR
o63UtRfhycmwCOp5svl5cZ8wGgvJFk2sI1/R0Hbeal/kmtQzNTl/KOzyqAFo0fXLebIJzkZooJrF
EP4LNs7TpztIOJURoMH6xfRM++CsPCj7UyzCIxDqr7p9iXMeeLDJeaXAjaUN4vuQo0euwC/b3zlm
viwVakWVuNj4fiL0QTviyLXxiCCJEsW4e25MdxQUlzNTb9epxQ/KYWz0XcHGWKRBGBafjD5tC7bE
FzuxMm5WWD7UTAcqHFOw0JPAsMkVPJ0x1kWhXmwQ18xRDrR/szX4xt4u0De3JKB8dHblabddpULw
/p9vXKkecCBHxbaraEuv/acaCw9UJGyNtT2ELOpiyrwey9IqZQcNV0IADLtoGvixd2SFsTL52vyM
9H35nCnZj7KlQwzw6Tidij3XxvcqjwoXQtc1S72z1qxv8L70PNX6b2UocxU/tJ8ZwbEl5ZOgEEFa
/HDtkBNLlbKZHf52PBy4P2xUjxm5q+RoNGUlfqaX59wRWpqAWRPS8+ujabAXDlsA3wcRR7AyC5uM
gMPEaeYZblVFHklWYz2ZG10mAFcNST7c/NrEFyMi1FwB1C9E7TjXnCudEjKrfet+cN1YYxSxMG6y
av0Sx3B5Qi82KpIV/H6yvb3p116fKdEqss3nD/Npyw7GcMMA4N6EIFAwT1mFCDCbcZsDQrG2HXk+
W4sulyHNeHsGbK19uS0yPHDzpqqltjcAJ/ErSZGxT3hrDtiIZcn4tKVUpO7j31DKVaw+t0H/sH4f
larxz+bEjSny0OewHH5YfzKSsYKLiGek0MotnpORSTVzfM4i4qzPmW9XnIyZ94JFeYTyCZHajNY4
WZOOOUO8TMDTHxjkfgi7aFbmg6RMqp5rrct3eo5gbEvJPWF4iv8F6UlM/zT1zB3bTavYgv+Xs0F5
xYOfnO3E6DYAFC5OtjG7dm6hZfwFWhaCE4QYNw0pAueYNkqYYiBCH7wPTvFL7q2mPoPXq910cuPR
5QGS5SM9ekN3auk4pMGnYwrVKlF/IX3Fgx18SucJR1lBr9cU3l3aKHA6Or9RtWKzbJXLyYFY165Q
Esh7+w6uRbfLHj1jonfBgL14b1YoYsDsv3O5K30S6qPVJqTaxhKJU9q0PEhWRxJy/eFN+GD1RO9N
46FIVC3KrpWVMg0gnbqFvNbEWcQS21IxzmuWmcKcfoSiN8oFSrJ8fcJzVJN4F8u8fMDaymHksRud
vRCmQEwXWC4kUixvlylVEyBJFs0jyAgnJOki69xgNR7EbzT4LXehIyJi62EJCwq4NercHyuq+YQF
VXycoEWzWhHma5EgZC+olarUvpSQ1OTiRwHU7o/gKX1/eeqnJ3eXoGO6iUkrM7YUz7ZpIbTYp3mg
DSE9cTnM7B5+WVTVp0Nyo54JjV1BpxY4ZZP6IRQ7UlvluJdYCRRniyNNTl9PfR8rQw2XA1O7tLKO
1u+uZK9FH6rMLsy3967ESkPAwh4byQwMwUnodF8uNcA4NOXXxWzHZifs3OMMchAOc2iJ8M9nfAjM
fa742oIlHIwS/tX2oDFcysTbsWBz5e114memtqra6HHdCCgO8HuM+nOYTG6jv/2WqZqB8AYXiBg7
uqmLs/BGKt/8KWor6e7Yx5V0fn7k8VolYwwfeiFWV5Nk0/oi3Go5iQ2K+P9RoPw60lIBDAiYFkRh
08+PGRCwDeQauzJrPeJcbWL5LeahccP28OxcN1w0MVyWdbO8f8MV6GKBP7YvhfTvDcwRSrjaegFV
AWjcVZxLHY4cS13Gt64p40cSt1POMDaHzUj6QbdD2SnSVGREgpVx5gQApW2H9w9EAi0NOoHomAoC
sLKFymIC/umVNqcJq08B18sZ8bZrGAc6cXWZ+8UahIABp9egZ0e/0XlIo+SCy3nrfukjPlb/kRUL
LL+TYeCPG0Z1NRujsFJxXKrNRfTX2xDzTGA9OEhgbdgA2CypXNYaYseMrWNyYvtGsWwyl7sPIPM9
V02uWBiaStU8/IPCJIgtdiwpEaOER3eOIurwVJzTEpPnTJMcNBe9rZ1zIUSF3mXEc//dtUS7zy5N
UW/EmJ+OMS28LXh8IcVwRLovZ8cYj13iU7VBskwGce8odhiwBUBb0TNCtmKJrRihHN6h8vuypNGs
aJrUxsq6LBy9DPDVqIj5rm0P9Fn/BWZ8QnhUzhBO6h6bMaZkcWZwnT12ifiZ4SRMe2OkPdubz3cd
dzufUKTWerk0sT/wjPduVjmrPPUz/rtBV+0zdj7P4ebHPalExOoc6snGI+WitnWQZ+EdmkOhH6J3
6rFrg1AfZ4xefaf+Zwnunaub6XGoNKIkQjuo9mxqc0dPpeTDdGsI/QvnDojrm42B9WBI83nu3d0F
GEQQuSuF0CG5l1iqms9QGcJsoYS3pJikBNmlBC9uoo422mVhpDsnHeZlqoJ//ITMOjnIpzB7H2zB
9MVE7sUZeYtqrlDGff+zhLn8XPeRXvjZRGYvWPJhiIVxz8KbMYBuhypF8qvCzFA9d1yyTL34nsH9
7S4xTrgareoR5i353MDRxz/2IS3TfyT4Y/xCaGiKlr7mMPmbYEkfvNk2XJzwK8Y/FCHYrsWBh4q/
GsVr3LqQ4b3Yo/POY4ldJAAP6aL9VLQtGTCML0qI09RcEW6ph9+7W3hb96XRJJSMrPfh9inENKXt
Ld57mpygkTz2YZHKgCv2QWGk5C6ARhvcgdZZ33HlDq9f+SlcneCGBCRAUsFAMGucjH31+3XPVUl9
NSWfYM7KjETnuG73pS+DzurgSrWrN0PMdMolARBg0eZNjo7bxaQk+W7FFO8wkD+DBpSOYi3a337G
EK2yIZ9AWHAYXxI45RY/YcPdDe/CcXyDHcRxYPSmuzKGBH7PiCWwKoobwcO8mFG4zBzPYqV/ouxf
/4/EtKEefUw7rY4y9RX6weK7Hsc3PtA1+1TvCYhtKugHJLn9KXH9cKVU1xjv9De0lWJQbk+kmX3U
7L8n1a975lhA6g+KAwFlpByk0fMeWh/KPYqkTcnfbPFtOzA3iDrUmdQ3YK7aUkNTJlkxst4qeuUK
Xx4ktQroWypBSIecW4VxwzvgMSFh1jrb1RLn9mrTOtZS+KyxpPY4DOJ49MGcS4R8T9f+gTWLHDgN
JxFJZU5fAH7GRbrAp63F4j35Mm+bFi7Vt691LsXM9P4I2/sLdwo1W3EsMoeKZgxYtJjldaq2H3PD
VKzh08LKaa7rEAULD9G3JO0VOnitlpAELMsM4/Al8rWNl4q9T4jkjJkUw56E4BNTLUXF34zRACmh
3zpm6qRLkwsBMrGogw8JNlNMGUd9kmfw4QkM+FQqzbFqVjHM4NviHHr6mFqkUdcJyfA8IX/dXxM5
xECZK1thgkq+xzV5X+XP7FhSgd9U6sXqm+p3EbSyVOkFO0Z3zbkMH/NsipFBz9RbyRxSFIz0IxB9
dAfxVNYnrtjwDoWw0S2/H3BVC8G7Bj3J2F8mNm6PpPd2Z3LgysAVkt8tHMYMKhkw+nut7vwQ3hJJ
edBhEA8SKhTUIhfyaXG874l5w+SeFhijwH4BkiWoC5YAUcgH+ZLXuZIhe731+u/wLCFLfm5rWdhw
v+xRIirrNUH2zABml5sVtpaQURxNblU2y13IuOXqkukJn+bBTf5OxIH+Pn8AZk28how6no8hVDLq
/rGwRLMlA4kPgHfm+iityrPv8hCT2pwKS21MFf/aPui5UqBFduP+dS3en0aacqytSH8czoB+IUUt
52D9EY+Xc5y9TmVbyW8cXl48JYU39ifW355WaqjeL0V6jClFoEtSyAS8J21JRH1kdKF3MLlpNN1Y
dKsubIJfX8YOgPqaVYJPeoJt+vBr0NMUnKM2oqMLROz4vk9sq09Nh2gu5pJgw5TI/mde2qhmVl0U
sEBMSwHqZa21K0wsMfXWb3xPl+nmaCkgv7brCoy9yco/C8Q0AMQGiY3KNJZkgjwa/8ygadM2n1+z
0pvEFMqUVi8hkUAmBKRFEsA2Fax1mJAT4jfW6YDJrC9haXcoa1ad7c/57qztBlkcy/6UcgOdUxVr
ELpnqnTEAzAoiZRecxqY0Cl9P6NPZt2tXagKoHm3d3Dk2PjiK8NSWr+qC+9p0D0xctORkmTuTe0Z
R/HYyiM3u+bSoCVoVz33g2/EhCy7H1mYKGL4A13ZnQX8Pm1KQqwFK+89RGopxr9gfSLtiT0qGRRc
trxvg/7I3j5KeQij53/wOia14kNW5aEozewugdudvRzj9E2tezVMdeDCekcyW9g+sYJVHWinpCk/
TGmyUHXDJo7PaYzdy/fpbHne0aSJJu+8Nbvml/zmz0c3rjbdHaPV44MliHpYqiqqEdQOGkTE1bUQ
a/pb47q4FDw+YHl61CL1Lqjl/9VPeL5s/37K+zlWjtDbyIDZnGkJaDhAQxYWBdcVxUyf9Xzd0EQ4
OnkPJj+Casgs+S3GwHL79bqjW3jhY80NVMP3aWPPUkqXBz1tnnjuvqT40CMLy1W9DAst0L1jX4Kp
JrKwKshca2I3WazF5wY+YLn7iWYODOvnk1qiONlD5ivNc8T1X9rBrskeSmRADdmy9WSOiXdkaGAA
P9z/V0BSzRFu0eEeWTmY/bFfd+pgxbiB/jWghGu7aDLXN6L4uxfO8ch9Ic/RueYJN/2QK5cC3jas
Ab3RcFglCh0qzuJ6V71SPySEwLx1DBhgbOBD9y3Mz0LfeXL9jthr/d0IfT3STknWPyQmHLodm6Bh
yJIbPOQmabetliK9toC/XKgM4wLnJii7IFq61X6C93b04CWVnsCdapZSelS4zPLTIRMaq3A+CeMg
nAMzbLd23SfmZRfa99UhRzQ2uDmsyGadOByFmD+fyGFYiQPQ2nxrPjyogCdJlEk7zabH+9fMsLs9
rVALy6rITXlFTd+craN0eBtuDEOCbxzhKlMDnO26/0CXBF9U/t9ke6Wgfo2kVD5PhDDYL0tKsPa/
x75bQX0BSni9R8fUPT3uOkKwa0NYsuUI3cLwj3gremAwubN4s1NiLOdyagLub1EOOjw6tkCj7SUZ
mwfPvEHoCEH48pDL9bucllaK0lLvFHsZ/XkdK+FJJlSxhxXjg2LrKwDC9gqnitywS/Jg0GozF5kQ
e8YVh4xqxOzyf99JS8xxYtQXWfVcyjvrgGbmyGkDsL1cbxU18y520dHr2UfOHaM0bC9DNi0vhNNP
Or9W1WLnf/phaMjsO3D+/KYdjcwffJ3IRMwdQwDpVQ1XBVOv5S5DhL9PGIgSaA/ySWgUPu+9dcpD
jf2CgzXy8AZvzdkHRxko4Y25Q9cmsbNcWqMTgr4nETlWNfEti0GQB6NitZiD42rupst1pXklYE8Y
VL8fLimWcIFlDTZ/vWdy4+ByJal+5qc7I2QyGUetw8Urp4aHQtqIW/SD1DBGeBSdBGFpdTKyTKm2
9faPXIjnyPB5FRGUtj448CmqaW5DdlvUuU2EJ9FnO1t24x3JFHU5KYzHHcHwPj/JOq5ednJ/9HW3
vVB/HeU9+y2acY1oBgxEVUbKFss2SyGNhVeArleJ6RC4F7iALpps/gMiviWI+nWxM6gedV38OMRu
fyfyfeDWvySxS4Oc6NgCP400ztO9eQ19N3IXWjsKvUX/ddwCX7uNeURPnKuixME8A0/bX8wA+FvV
pwSjTLxDXpSra04ehzFh8EqZY7yEM+1X/nQsue++lyeZL9AX1LKzlnjW3DSTELkzNy12wtihyHLP
76cjhOBIGZfP0zkWSPuY1nqm0gMbL+9b1Ib4aT14ByKIz7VWvV58xy5u81dMSXAkf74bx4mNzWNZ
iHJyx6eLQvdCcsjlif7w6Zc61F5CpcDOBR8AEJSZLxx7h7EfJgGkv7hrABlXTov+XTQXNp5pU9C8
i9ontTQlumovxgZ5MIaok7urAeRrso4+HUtaacPCYzodzs+GPiGmhJ5s+AYqYSgFPB4effTqDlJR
uJXfMRyHdIZ3me3UamjH0x1o52IeE/it7bFGMv5NQK4TTHn0m7I12sjo4u82P6ZHnjLidCesh2AO
FdivxlDiag38c3Yk9LVbg78hUVBRs560T2JAYXJJqbCXN0DTp0gklWC9bebgsfUmKdL07KVkMl7u
9ck0onl0gjMStH7evMXXVk54T8LfksYUfIj8QrVqZkJLD092mzljRHVrvK3LpXy3bNsQ1o4Eywxe
sWZD5Xncf1cLQH2LtpwLGD2e8p+3s44DydXDyqTY4olMBGYtxHd8yWv35hgOC1dETJ+5zkRdHF6n
ESVv1H5nd3q/R5keTUnU5Qzq7FEmx9tvQLk7D7Dun7V2SIXkNz8vxkgFZQCbz+TNLNqAMEQgH2AE
aJLM2bPpswt8nOjs9p4ffW64B1obDfctgJ5DNHrVPKAE/JOThUO5154WNlOBrEaPtZuWk0NX8dz1
uS30uqueGzlZqB698149F0l9qDkfTZoLJ/LcMusk1wC9rrZNHOeH/HbOC1rV9Nl/wkrU583Bt63o
7AIbPOPlM3C8U6QN20HbBJDlyWckRgT33ZBdAiJVT0NHe9rUMrDm7na07PgnPWDdRfgIZNAYr9E/
eQfXeXxSIxSeum3514BZHaooaXBD5/Lwf/l8E0JaGpHi149A3hgZ16+aw8s2tT6FvNCWrVp9hbS+
uyyTfhL9m5G5ZJDss4dH6pviU6fjdXMI5Pn0hgsF35Qzs24wMbcEYT+9TMkVS27EMW2WDxfF7xkC
ge2xyUrWEoWh7AI3J1+orbZzh9nRkuOd6QL1XiDbityhBB2Y7oCWU3flhENMxisrlVGqlGAd8Koi
+k35BIKWJzkfPJCctlu47GzGiky9FO4JBw5+9yzPEZ9Rb3kSRgzZwqfZr109NHgpmvqJPI0yOVaU
Bi+w0ae6Q0SN7fhl1GXgyPvYQR5c4v3dN4FOZaMydSmUuEKGT5pbAzihY8/2nea1JIbg7PTUw0mR
HBvSdST5t5wt+hdVWXoXFtpylqAl2hdIH1J+vpFG5c4i8FJUp5mTrwaTGd0z9+WHbZzYJZ8rF6qV
Q0Q337AqB4cTsbXv98c6Rc97jMDp6DNz7gucoR2VhuNds47HMxcCmjU/TBa32cg49c8tdwqcaZWD
k3AIGsI20CN+2PrLQR6Q8qNmqETZCoUch2hNNrKZOsGDLFLx7MV0d02OKjJ4MqXCs0cOp+/zVEFs
cH6ZEnCCPkjVd0hHrd9pEJXjGs5Ti0j1PwYmr0Cw60k5ggsleVtCIBjummA/ImEwa/5JmLsK8m/r
7HU29VyGLhVtrC/vJl2U7gFWCkJni52xAAJWTzDvEhDwmU0EMvURGP0HHdQBOaWLSdqvtwCaNZjQ
fYz0tIiywX8Em/UPaIOE2kXLc99fzmXUoaPcmr2XCIekBpizs8j0yRosBafm06OusFUPO0BUWMA7
J+jxLnuVppl4cEeOJeJ/rs5bEC3EAVi/Tp/s1zMTmbqvkqgJtSCGHaiy31GxhQ4CCVxgVy+xLwtp
0tVxsihk+s5rvwUHQyoAn5N7WU4aPrCdKTHxZOXUSFxCoj5fYNVBZ54nBNoUmJG+Qdj9T1e8zsRH
uhSLslZcOh02BZCOQ8XAhBCtFrrIxnGdTvcGBLFPo60QfB711iWeqQJhydgw8XY3gkC+tKP4ui/t
OfExZd2f36KpBZVQ9q8W1q6oVKCpyGbMdipeZDk6eItjLmrY/H8T9DX7xdhYVcRunF7gWKWwye0d
vssILtNU0h9WCDhlLXo7qeG5Ojp/oeo0D6k94NR0uX4l3J4qhjJIsJbL+s1Zc5EizoJd2WyDnGdj
QZK+fxVCmg3b4F38NTH0RUeV4jK+PpEbg9YfLIuu5i11q7any73zcwgZ+QASzLzSVhdhEJ443E/n
N4pNKdedeb2P3YvwjaA/pOrRwWN+jGRHB7WlG8duSf6lCcJCi6b+P0/nwOZ6ho5YYXDN2tMFD89U
+Zv/DjUFTrYiciPw5Nve49gEhkJPf8dVuT7dX9CdGE4rLNC08dOR0m9xL70PlSr/pLdaORsjIaMT
mw3lUpeJCyR2m20BRQWPZwXddQu1qxbvGIa2M/qksd6qrTm1E2pLaECBX09P2QTH1tJU7JyasTSq
Fb9PAm6QTLLFowXbgOXEOQnzmZnPl90OBsmtuLmQohP1ZN87hHsRpjtuMqiNA4P5FHxwxe7yWLLt
UttG9+tozVkHhfENF/xZzh3mlm+ya1xUoIJTaDCahilXJ2cIZe+GV/u9x+8woV/6PnR84kn7zG0z
r0HoLyd6cop3S8F2xtG0dFQQ/0bkZVjo7OD2PLFYdxxMF4knZvUmvrQN00feeJ3wG0TAGoLQyO9/
c1ukFJ7dor6yKmGBv+eADWXZrh2kNdg+Fj2sdky3Edpe9hk8nwigUpSw7aHPrZ1ETU1ZnAfKpc5k
emNHTsmgGuDeHpCx46tKjZM7cu5IbZpBb7JdT7RL3rzrtmmBjqRSzaLAgfaYQI1NdAP6JV52f1cr
QnX+DztoWdjdicRlcymad2hF6s9WRVkAYaZvP+RKZOf1r+4KIjm0feQU1VXoYaetMjEAq0Q4irYM
IEScrjqB65tvd8wjR20NhCITDZC155/sICUBObL/dz18p5+7P12WSPDpenDHxxms3XoX0hr6Slmw
V4TVPXP7pBJPnX0mIBJpU0cn4a8NxdSdzqCvzpsSY4xFY6nQ1Xv/S6VBsQfvQplPfx+CTrzKRZz3
jX+sF29x9NjNNKmIYNMKmVntoQm2qlwJ5hKmRGyP95xlPvS++4x9uup83mePTII4B5TfTv19OwO5
g+N+XOmYyC//rMRC+4GqC4XYFmpqMLon72+EeiBfpstLDD4GjI8p0/X7EMab+QaXAU8/nutGu3GA
d2/hb0FpPQZ08FRcjqzPcYsnDELz5QUUNB628duimyxU/ENEkCP76RDBK/fegmFwnlobNiHIHM4y
bbgOAx1xRfqPB4KMviw81d7kllNChlL/PNNC1hXJ30IiciRj3fbQu7MD0MVTZuGSgc6kqz5dy+TT
656IJAZPD+mmHFQ7OJfEgg7T2inwmWIFavtqOebLZtPId1E4rj3ZRRrLYZbmwWtXD6yFB2NisyYL
zvzSDE8GLCO2l6iQWTmQHFL5G+IZIztXubfKCmEXNXR5dxAX0FlhUqcQDnDNHpoC33JQGIxZbnMZ
NSi7d/DZWULvIi4sJaXr7jiJ+tL1DVHyNC8iNoXJ91Wjd9k9fuK5mVj/qSqCSUk9+WBdzwTzbgMA
cJ2gTFXyVh6W1qjTz6/g8dGB5XCqw+UfCb7U3h5GvU4kevnSZsz+cKTVFp6q5OhaEFV4mn+q4jOu
hk3UTRpeAh00PQ+LNAKg2xVj53MGBUmn21T4bsG3t8L9N0HE9KWp6oFjm+ozmQeLZR22Xng+Tq9G
+BbCvNWLYBRACITopoEuTMCcoCwLQCqCUKUNcsCDdnekfgNs2iQvlBajU5kywRkWEXcwPcvHr1ce
uHWRLIzibyWY9au1j4apoiGk4sTXD2BCbJQnHlp7eGb9tMt0hBkU0mFzT+ji3RkFxhN5t8CuuO2w
pdf6fuUdGYABYhWxwSaOHWwjdQ2DKhtn6aAdOhmQkO30nk8OuZGH/UgHo8APN2FXh3hnXSf9UTnu
AWHHwGQIoTfDj7aV3tPVXF+hYsdHmf4IRNERRRpPJi4s1bykT2yxCFavXEXiGxGaX9RuVVqCT906
HHpQJCh2k5z7Iht/Ht3nzegLAM2Jutgp/fWvpUIsHp+LXFCa6Z5lDtgm7UoCrLYDBZzcWW4ZS7iJ
XqbQ/gU1ZRkH6cYR+cxxsgUXgFUTtfJ36QVWCFhPXPvw7YD9K3q/CsB9iVpf3aIIpCud6uqKUHO7
Z6uzNrrngpMTw5WPQ/orOEUvUUrDYznDG6fd0QCQyMFb/Ez58avnA6csEtok5YvPO2fyPbgiBO3W
7CkUTo9GFPXZZiACNzGBovHCmgd76/01V0f9Dz6ydW5BreTrFYSrs3X0Dop60HlFSsPG2jI6fzYa
HpR5RG2S9jytBBLTndCm0W5QbBDFECOwBNHSYJdDdLNLPigylvqntfqRbkSnFGB71k42sGLlMARv
LIQIWnrghK1cyjdKEjBkm+bCvOTPZmnl7Pz2yDC33SoA8ZbaC+Ln+B9kOvCfFRpIIqePEHwE4tls
Lx3xeI2CkroIr/NSvU1Saw0tQ5DyYpm0Uojrwmw6dezj4T8piNbaxzht1xYAPFMy68Sa8+LlS56a
YRfXoTSL1h8iZhxH3VAefw+/srU6UgD48LqbW7bILFrlZUjUG12CxGHsxQAIlpcgZ66ix5kIfg+F
wsKhI9ia17D+nWu+QISSeuljppO2/lc+UrcDuNoWvi4rnBH/5ZKGw3eTbDWRoHVIoyk+qtpgHSpf
UKxeNSGN/jDFVa4Ds/1O+7SMD3q81r7nPGQHpQ6Cal/osSpp/2O8ID1V+ngVDGC9j/b1RfsR+CU7
EwINWdt6Wy4uJdrBPlgTRrB8MT51SxoO/50k+/z68CVAeRkXTaw8G36foUFEqXKzYnysCVf9v3JF
EEFHZLkjrFu24Z2z3G7adjRdDxhIMxJoZ1m0g/VKH5Vi2M1W82I2OfNDUDOFDez6FYVjeuZRC3xS
z9Tn4uwKYqDP7d9tzEoohzsIM9El4UzkWBCNzko6zeWH1mwCDGMwSC/etBhYHJ4yefVs6vmSFDN9
DmulDWztM8haBAE/0aMqMkJanppZggdo89J/647NfxUmTv05ov6TPBtLRN1BDg4hVE090NgE+SIc
A8fCt3+yaYA7MjfnGPbIe8Enyssbp+Vvu/PF+f/iNvL3RttIxMQ/PIR1W70dmwMlBJpKL/1e472l
2YtoEHAvPvt7H2wSzbadrUC8bstUpl8LexdyhSxM+5BUG2KTw9BWX5NK4Vk2u2hadNofBCTwjCq/
swNWvWFKSExUD/oUGRSZwJ/ZdTx4vbGV2gNsSJnOC608Us32m9aC2OmK/kpN3DFOPtOpgDw3ZJMx
QR0meto8nvs5oghQSQGWxtXegP0BZLDWgiEzwAZ+SGr98XWYbKWw8XpjZoQVJlpqwwxD9lDnNmvu
gYOMR+7RW5vDN0pzHeIKyURIsEjt5EhulrgYAPwL7/u7+C0AshWeJWBSwOXUjSqXbxYAKjA5JUO8
IhKqnoJduuCRv9Lv2dYY2NNo5HEsocEFISaPLeKvBRHZWu0kWOxJmi82P/fvXJga7HuqTRvIronL
gv+33hHo8fzCdI1vovkgug1NcbxQ2+MjIwaWl9ArY6N2AhtVJlAIQ/7Ovk1+p6X9kH2y66cy3OWP
+3QXCtJizDFmmXyTUe5F9mn39XAV+iFZkz3beK9XZUSZTRJpUqwwn8oe/89i99TPF1wvay8Jd7de
AHxiOzxXW0pzXhwwv72JKeAU5hXobtUmVVHJkIzAnJQUpx/1OSNNQfPN47IdwWg1z7KzeIqFJuY6
ENoVkZuqfA1KC3FawtGvKWVfqT61tPV5tlkQ9ZemfLdZq/pJhHjC6cviiFfEGK4q507cAZq8OtIX
llWZr1JsYCIaxb3/sz28wOJtVvWLNQnZhzr3aTLOSzojUFLif79rKbe097QfqQmWb0qdJiT5rsoF
XtKz84eZq2uHkG+N7jP1Oui2SuJKw/AdDYlW3Dbuz9XybHW70JHAoljzDiyT5rC46oMjQCeNRCwS
OEho7Cnu1u+eJujCnOyQU/KOTsoOkZdx4tAe/32eY/eJvXVEt9qZtHxbsEcbiAu9UZ3oYY/HOoLP
xji5kJmehkpLjvYwCUz+wb4u4D5HQ1VkltcrFGWYtKem9skklMw4gIVi4Q8U70PL74gTaT+n3XDR
4xP0p/VwOrLaD2FhTlVlZtWcgsgIshjvxUKMGD+84aPwCq0+jFkD54+ZXB4e7mqI2bN7T4iFguof
UM/vxPFrMTPX12pWE1z6qV8cyLUSUqaz8WWd/fU5/XC7a/8+Z8dDDXAz3sd2ojdLmwML70ntx0SQ
Z3vGj3xUska2nUz3i1J+buZyxsgOYU4cM4IQ7u+KuhUAzxaHmjFpXHLIibqaqmkj2oeAQFNU/9Go
51OoUJZe0woHezi1EV5jGT0TCBFl9NCMBuP8ESvkd/RfdxqNc2Ij4iXhS+mKh8NVxlSTnhLx1Cs0
t78JOuJL3fEzRdm+J5+3Bkj3RCHFesBt/7GvRbdBe6IxwLGMHGGBL6ww1DgVyzezA25TKMt17PkJ
QdtNCbchWHbrSVaZv8Xyk9KSGJODB67qxwPKGdxbkrjeLLyz6TcbwrfU5N4twtHyIcE0OHVr5arB
xwYvqxp9cKIpJsjqLxE9e6Hf8uUwdhwDqMIfwQeh3c3oUD2gFqeK9LMhfnwAM4dePzzZ4ktUbr69
9TkVlLRDT6/NU8N66tNgKBUsfCgs7X2WjuFSdtKLAQuZeeMBQ6aRorfjc6fbYsRe2xZmwjCBlSq/
j6GSXkesTJYL8LpU+WnxSxJCQ1mW34RNZdH2tpZpJfVPthovsLdKvl0CFfa0M++fwo+IDPCvwQ+7
i2HrFBkiTCeG9hzx5ozqprgvbAJ/MqS59DhloBi8H1+irsnQAWKVt30sqidrwM8HlbuyioeeRl8F
AqTrlN0DgFJ2BxEbEWjBs96lYU1Ge3+Wx0AN5mk2Gg0t1j7ky703YwsjE3V8jEpRcpl2nNRF8mYq
rJWh6Mh1uQDNntZGibogfv2m6x9fygSo+g/I4uMZf7VsfCEhiJ5sYNC86PQ6qHzrsujhTHjU04UO
dgAgRYuQmi8Z40EWPjvARD9zlFCWb4ncJB8BBLXQ6RxJuKIdXZHMsNqfPbQdH/k3M8eRh0bcr4qp
N07QP+twwdmfSrzA+dVp0U3JF/CRxBr/09zXvJ69pvIpk/CKr5/MsudQTCpAODUpt3tgK34PQ8sU
jkR6mk3eA+RDwflrjYVgq+IvRj7laWWY908TqPSP0RA3luHfkK6WUazSZfl5g9xvvA2HZNLqV5hw
s4Xdm+yBORSiqcNaVVj5GtIyRGFvVnt8CSMMbpGoGXOWK00j8melCm/A+zlswiD2iVO50dbWirwS
nhr9+T7cupxgzIx3aittKDC6MBsl/SNMta/2RbTsUubu0Ej6Wlzo2O1+PXreXN3pKF7ycVmTR+oI
0eZr7ZavwoLrZlajKv01ePKNDwe0XIDjoIlX2GZYMVGyMW8KhlCpPz0qUYPnWN6XE/0sgk+1vphc
CwI757RXD10Aze3Yuvzw4i1vI73cU20I1twJKouaAgu+RVVJWxZk00VvGSEQubLQGx670i3H5K10
swxJJ2p6dKAZskkjnCzI3THmcj7IlEH+yh5OV/jwoTW50Gp8sMZ7bJ6ZQTBlOtZoyBAOEEEj7Aja
LsZUVZLtn7V2SX/PTHRkuKhQ+1smhaH25Kn7kp3hmj1nAl/4gunCyMEIh1/xeskURPuRnK3ejuFv
zxVNTO8shrZZm2da1hbfguslU035+AokMAx4HyqLdsiO/7YtrDYovOG0qvJ2/eQFssVv95KvX2lz
fLqYajmj080vLzzJYQT5/GqLg9dIk5/EvMxvcnvzaHztjq9VZ8u2FuiEITvzcSjTDTMuorauo10W
mypHo4oN0HUDGdqTCqI1SVI5a6ME4pNGqpwIIwUcfDQus8Ij1Yp4M+BuCbJRM5xWPcMBmlOU6rVH
oNbzlLirQPaUM0F3WV2KGmniB09QDY1v8F3YVmkCg6GwwExTF2NtbOYJYgMb9Hg0t0gfRcyQCZR+
tBOkRId+ZYKNdjbN06lMkpETsNyI1WwFLw67oxR5b8YuB04rBEgdWa2sgRO+IGSlGeAPJSad4YMm
Y1CgiRkV8olTwRQxq7yIqLXkqEkRgp/MwzKyE0ArDu7FZaQ2vgP8pwilhX945HPb/VbwTer3LVqE
SSYSIF5Ji8qIcxFN7pF1TY9y9USGG7IPBkgFyvbHXW+GuOFVLk5j2vgwra/1l4sGaA5NNVxE234I
IaZXojx8LXWVdlH12nSb0c0a5Z8Id9ECpJxV3UI0M/Xt+2nFLkSwgKXIZLYwSuSu9OUXyxnslDOS
0QjZz4CFpg0mQO3+gtNyOvA5ONoFKpk2pmcCfAo92j3z2ONN1+83iPoAsB2VRGJY18THjvOd2d+j
Rqh2OiBIJqPWesIDSdU6R3RVju0qnyWyQwwM48h+gowQvM1XobbRw4dVckz4nY3M6llOpuVWyGs8
D1gKpYSvgxyvSIQ+39TSQ6NMYHIycetQ1VgJpMV8+kA26gv8DQth1dx8gEMcDApbKZ5obs4Qw+RA
4/Bwr2Pbsijb+6FBhvYXadoWdmB3+OyWtLlovbjE4cjeBbhE0I1iuwln4dUWV36mhUd4qhmQS/dX
J7k1H1FIqcS1MobzqAlP71euvdT0RPNyx/lx/Q62Wis9OyWBmzR+D87BY4eMM+Cp9EfJ9Wd3cCrQ
SnwyI1NNsTXVwV8+XJoH+IgcJqjohxbBwMIHYLqh+adP6eRtN0PO227na+UIBJJw8AWMZaqkgv4t
Soqc2Ok502JMaHzbfhIe6UG/ZUnDkXzhCIexaxqfW9IOS2qERbwgZ6KIE3OgTj3nZmOy/ha4FLct
i7FYdU6DKAE1y2CoGhColOc5T7vDiZaIQsi05rKADfan62aH4YlKmGRgk3LdKm21E/zLw/JY6brg
I2GyKSePek8mGC3/iCvWQkAiH/yaQjiWdDOgrCXGT8m8ybQQZRxj15KxxmqwWnfaxFsMzTio6JxT
vK++X3VquzWPHdXjLm4hWCtUSGVcowk7NmcJSRL9q08tKdP/62dVAUcPjoLKNxIuEbN5E5fEgi/+
KJ2PqrZ5R9Hr81C5QmMzQ0kZxD49WGWRBKV5hlC0P4fYhva42oAYpg7ls+k8pdOLwa4C4COB3i03
cQQTCvpDOtC9v3PZSwqG/R6WRWOtkMT1R3WnysBvoRW45U4wRXwF6uS2Nc+lNeNiTxr+mpMjpc2z
Agal+hVpZc3HmtRD8yy707iDTtx/gcnPfLUHNoZz0zsh33lmAUP0/ftCLVo1ZC3x58Vm8b0/gQd5
f/CodeCegr3OKpeU9HGkKmm9WVKLt5AGea8GWy7liIwny84fV9uOk2dFkLKEO0njpFersSFxf08q
VwDJTKbqMhIuH5fav02o0aaeLxwAHQ0q8d46dtgUg2t7xZjBnRR1rK6PmP/paycFVzjQt3eWmcr7
ysThCzl3cuPryzGaFtpHXj6Ir5g4R6NcXsJVPITE9FGPwpnm42E8r4ntHef54GRlaESNCXo8SOYQ
wNKf/j9DqMwTJrw0JJGhre9DfpmGEYLpfuc9ICIU448cFxCdtUf1vVHux+/VEXCEAqkyIEYJoxmY
3fXfEifFHh+XW+cfrt9gTYSAh/n9MjhkITCx9mI8U6gc2Pvu1pB2nX0OyZleSad2r0KXZO0A3Nzq
E4y8UKO28DtCPoz1qm+yj7tY955biPccoGd1Tntj9U0tOH3XGOJAlfis9GfqEtmDPirfgCDW1cnV
3ffYai6RAsYiu4EegcrGw1ec2ofxnx7URPT2zZjxMlp4+Gf4YiC+Q8vxRknCF02v0W1lmjM3v9uw
0mGIKtf4C+txwaAVP9rKh0+yHyr7ajIy0Cvjohbtn5MjQ2znzHeVET9ToBe1J7+XN08ii1JmBCp6
b0vyegOM0aq7gKn7XPNMJnXD8M4ol5ALQnzNNO39YQVcE4CD0Kz4qffJ3iPG9rDXXJ3GNwJesXg/
CXFXBFDZExU/xRAnDLrx1ctWNfC7iG7+dNpneeiqQILXmuiipJQzX4sYc+5bf6PFMh/XcnJWfDSw
WQRBe6S8HLqp96Gqo2sUIAtkeZREImhZ+eFBoB2PoRLqjyL1MPM0I4LM2XAswyDtepU4ZdltrYPO
abhzP5QAL7ArLfw2d9TZfUz1BhInS22lXcRj7bijvL4Sbg9cPUSM+CNrmF2+IFDnv41bspR5QKYS
CoUkd1BthZhDdN8HfsKDbT3rOUj8DGWP9W6YL6AtpNlwgPQb2g8Cef7ElzUrat99deCzU6/9Z4CO
00XJwtH3t8/YZXr33qZPMcFvIRP55KbKE3WwOSLWriDo0470D3K5Yt85bDFa4AtIMOwRluOK19yu
L+oPPOTZ/gkuSlV+B2Oy1ngMm8V5GFuq8EID8kDgNACSMrvsd2Nz3ZOvxz6lO9s34X6XHtgot2SP
ZPnPZ71nKZNPnuDoZDVwzBMFVWnKtHO4zEfV+2m8y47ZOrYPot3MFgKYvMTajze1CswZ11u0FNai
H+hAIpFx5hjVweSa3GqlakF5HpFPmdxF/QbW6SewqesbUcltP9GswPEWTCg4Zd8BhA+a2LHaHGH8
IzgELAMQ61M/mJKRZLGjvmtF1H2qR4w6A2ZxgLaiEEuV6sbR7+XaUN/U0KS3NIO6A+9LRAf0i3Ou
8FZtOfJUMew8FKuSOLT3/JScaGTI1M57Xii+af1S9o1n8hz+ibfQPmArDtTirO7CJPjWUzox77Nx
POP36tcKDs41xGgWtepItXjjhKlw1qcJqfryym6TFSVfF8tfU1yB6AENZa2/ZCTW0qRtUAbAt0P1
vRxe7iemV+TdU/MKDLbyg7RmiXY4cS9UkTXZCLTeLmgOsvhJII+iWRyDH4obBqBrs8C+ZcceVKex
BT6BUJt9RqG4SSjswc+oDz4BjIXnlF6RlKeMZJynzjWesTBmcYMT1958rQ9rt2WklToxF45o98lo
wq2O6myKY9lLQbFWYG3yGZM/Hurp9hUc/QSr/m/omCajgBnEGwMzv9ugrKnsdWd5J3G0r0l5koxV
PXDqmFOtTAws20/AC46qf79k7eiG4VVKeAN0LWUObAWWlaRk8FLlIRcKzBuE7elV9OzoUNmQxOLk
AOcpiqHCIjgv0ogVKnns8FKmFqGvMexXjC3asOpAMAoCuYM9ZwFQPgTExu+qjYdvtHlfuqdwwgeF
7LSFhrmtLguXQJ1d4KoHHVdc1mC4FnO9IVrxNIHTDGx0lpWX8HYjh7a2pVp1eI3WGXwxzVvYrrd+
HQ1GJlV7ATgNTIbTcbK+UYZ2YWYICmEZllpDMO0BxNvXwq2ZCOKDNBKfr+jZDZA60cnKPeTYwmuk
oEziYlLViNqX/akz4e86IZOgxV8x1SF8SprNN5RbNRE8C/IipLryhmkUMLGLmmHvs3Ei08/1xdch
qLclLz0LL3CvoOED3a93TDURL7ZRkiJ7u2cOiBRzibvxwqyqqhAd/WWXVHyBpMBMd26+kccrsNpb
mx70dGrrEuofYSlQqqwozkNMu6a1ndveDyzoQ6O6pt3ORGUXhp0R52r1DudL4W5wDsoHJhNyFxis
Zjo4LBfTaq8dph8L6uDNedmspDxdqSBYSDG4goDwfYmctAbqX/817sjuGH4OK/hSj1SRDxXp5KBS
QoZVzPmPwQzTPGQ3wlB5wbcBGmEtUJIFKxPGpEqTwdqWBb6HDV5dNAKZG9FmloExCanmNub7FFRl
6CVKRiX9+WWzP/qvNyZOdzmtt8ITuwIqnuyE6k3ne4KWbMT+/pMb5h8SNkn1bEbiX5GdpX93P4M9
E84UjPFcRJiTfgti9AwgGlGoo8ONxcSLPAsm7tBIdhqIhapvL3ResEH8po8dMEiFQxxOITSkho9j
Nh2vufNOrMTfnm1qmav5M7yLQ0FtxruZ9JhaCPtpn2hBKe60AVPugKkUF5PXb1em3LFFXBmdSKe/
hKSnw1u4Gy0267QaqekWfpIu89gVxnwgbyrUjbfDTeT0GOt5ebuhj1pcXXMYkvx2WK7RyARPoom4
z4dg69vdeI2JAHVTHQHWxOgvAyYZjvoofe08XbcJu5y5NHvW7gTgYzvjCVQR2S3KyOYMyWtYfMoc
43cGEWPHGqlUmdS3K7rKbJ02kWXVGK1BkzGEsW1ElDT/ptxytGyg7pOfY+YU3XOFb4aZ7iSGmhzh
uOII/KLw/XpemkOenIlWr9vh6JJkLLBypVC+1F24nWcfzHtXCGVaLhUg5S/DtYh/6p7u1A2sx/+8
xGaXSGEGigGLo4mpejSq3xEEVY9HY4RoPi3bK9naAxUAbX9DYF3BtFboI1TTVl8GedQlXtg4bbWr
gTKhugX0F3Jt0Stfu3jWSc3Blvzbj4yCmbuGMx4z6FWQT9LhtrVpUYPYHlOF7MrByeKY/5Fex0HG
4g4BNG184dNoIMEFxRnNMAGH4w1pE4Y+33/U5KP9xsSJY+vBBKOcd1blSzk4NFf/n3E78AOn4gkd
JZ4knrwMRRigb33DA67Pm1cPVwADHXTa2gFhVL76d+DY7l0oyX2CV4L7p657en2j98D3XyxTt4Bz
KpIuCmOg2RG69d0BgH6tFv/viWeXWSf4zfjC/e6L64iaiGVioqjZoCGgMkJdHrMOG6p26fEDlbxN
5+gKqSKdE6Cy8q+bvZr3QYTTv7Lwm36rfbw2wXcmJQv7eesIkHYd6q83sLGq087FnwXFYlKgOjYa
OwIF/1j0gHdI6BOs9Y95RIOd/qL1rpFniOtLFFvxa0UJ8URC4lANGvXW6+d6OLectKF7FF+0TFUC
5fdiUmULnsk5FJ2ub9xq+2HrmKtP3dlzg5sJYQmIy6UoLI8PeNmd2gESKgw41rvPTJEvk6JF7v7u
3+sOYslNj9z3XkJEvo1L1LkmGFsHljAQthEa77PmFj/4f+263O7gXrtjSe9NO67+d9oT+P+S5bFG
BrEa1E8yJv1FxYVviOyjsXknkZRNJ/E5YBjn5LI/MGlJmmsbfoApEABXH1hF6e1/CMrTG4UrWG10
4Y+aEqG7nUOjTWekQeKvZRwOyQ0O82O/3J9VF5xuOoiwVOYeYmVXEgbNXCMyiZ/GtsNUwM7BWLm+
bFQc5uv0s5+Jc3g4/K1XUCJi/fRGtURb7BtrXL8JGq3EK2/DCmuJzZh7gd8/0zHj2lAz8NL6/Me6
+JrTAaonELH5Dl8vSAifaZ7k5xUh1QQ1600rwUzsVZfWwLrMVjiEWRiXQ8ofabMMrUVXyfelkODy
naPRlSwltYzQebuQrRkn5g2iw01JRl2KC4TyWM3gCAg1Coo8JwQfQUu4/R1S5te5dx8Sdo3MWevs
0RCi1mzcxN98ZYkpW8usrk6O3HSCheMWYLfJLqMqJExuKyuZ6yvN0EQGrj4kPRMQmLiJHG9rvylF
/CL4k7+i0Ku7a3nrtYSjrqLfQ7XKrsJ1qfLYtVo88BTu50WbA39aZXuLO4VfRSPmg1MGpun3zMw4
X89PVf4BtI4UykRwIE6fikX0cs40DCqllyarthWU93Idv/CxnA/Sb+lgYoW0o/18Qi6qzM/kcqed
Pvx7DD6ubEQgv9uYwM/YUVIAcJdmggZ8qgWfMRuNCNvGAbPFi4f7Ew0TVcnioJm+TLYvLS/Dl37c
k50Xhkoyj2LorwiMg+lWI9xx6EdWwHd7/Je0WuujJmQrgYoj9UWJTuU7/1PDkEFeM8aFNw5GFoL4
67d6IfRfVcDPfkdzUnOgkkiEgWFBq6EX10IO8Y4SKZRKuENJegh7fDzwzlMcGccLtBDMGy8m5J8N
tpKUzvHaKeHcPXezuZoDksm3DXtB03Sol/8sOxyi6hL+FnqCtpvgSi6VN8XtRsVnREW80P7XDUEz
f2ZtA2dd6sF25XiHJlQcIHHAmJnZLELEu9LEC1sx/s8lTTJQHQ5GPUAqbEqJVB8Gf0rWcoOXK5o/
YTpGPfS57wXdXwsORt611pk/5zxS/DHVZf0JkRvqVTa0GTOBtDsbEW57JGNtvYMpsp5SahCd8+dh
2oOvj2af62jNMQSC/nQhCKY8HnqNkl+4QM9l69F6SiKaq4SJUal8f7USab1A0OYPgDUXHK8VT8kT
jNdJrZzrA3hpdOD6/ukwpnvl4DaBsH/EoBp7iDSPIdoqcACxJ9gTbvm5/qLoqPCyGRZm9Vkax80Z
IfBdWiGEeGUzhNpWcgRzJVO3NU5gVVcfnww37VaQz0GUhuKmYem+4vBUB8bRQ4iLTFw5Qhuev6If
3g7hFNM1MBS9fm8QBpKe3HivOkHsuPWA7S6baqbMlP1gwEq057ytEpzox3/uHFcTuQ7ubx/oij2M
LYUFahFnSFASt3mwYlCygvy87i8WuCgvPbMueADRbfbXvvxpTflBq1AeQtmicko8ao2tL+BNUKEe
F0n9sPDmoBCC4BhQQ3h6qypBV0g9BuYuVvmFcLYWLLn7jo4NbgKAsclJ22mK2w1mhbejzIEbdoTt
UnkgQdHdF6nCZqcVZLtm1gpzdxEVSi+E+h/e4BB1HjInYyRhf9m+REUYjGZDdRfnZfwcUGapbHMW
qbSuTIfcjAryWnRLo3WbWpMXa6AE9hWfBzRvrHHsaVvr65r4WRaLf5LOPzuvJSSfTWnbKyW/ZotU
09lykp/nh8kACB2QkFGkljp1X3ag7yPer8OOgI58Ucaib+cuGe53qW/HoWz9emTZq3SEbiyCxtzi
LhSWJVFRMHEkEN4E3Y68GC4hZvmZMUf6Sfd4oTcTbyKutBihl4+HKRkcHHqDs3p3XtW1SRDvYhCl
78ThgI9LXS4T290eXSXYrJC2Qi3pDZHkCAp0FTd0Ykx2qNrWa4ITUh4LzQIUqNROK8SL1Wac8a7F
MgF0Pj3OweJ40sClIvWq4ZQ5jmTbbHjebkepxLkVAkd7rcdRYIhvhruRKfy/xultzAexwu1UU7mN
mJ0/arzaj3v/tfEs3Obm7knLiUK7GOyjimkrngMb+NBqPGbw0B37KPGPld1CtzNgE6/Oug1g844j
Sw56XrPO0oEPHbP/kpihEhTqhMl9QlhdqCk5fAdpXj16vO6cvGAbS04CaJq2fUB7PF3nYzqfG6/k
kyA+uarJjz0qpEqS6zK70l/hKcx/Lem0/WSIg77RHx0KDSk74GOiwIO+XUlqkqFLa/4MEN4Z+znj
GH5EtVs0VQTFa3df8Bwpdr0lEQp+1UBc68/f3oSJBs7BANTB9lrxEKkhlu0/lpGRMGIp9WGT8SqF
n79Oyf4ABPn65PVLT6j/rVGftYJc/pNSGZlDoe8VmwgvW9h8RbCUlTQ/roxBW88JACebD1a8nIB5
q23JuFLAyfdabGcgFnje8pf4Y+hwiCPq2KIbGPgGgk6ahpsc2lfizr654V7c1xFY5pgm+/mFBAdS
aDeVcr/rxr9kqE9txfgnnnrBC4U1f6OtXgaeXyh11Uj1eKsZu1ktVUYS4MYLrfrUCj7vUB0tVpee
LbAs2edNkeVOFrM9OeKTok7H56/OIN99H8kIWQ0JZHCyy9OJ3YbArDa/v8QyKsx+x+w1ibct6XuI
ahWJ6QonFgZFiLbIb2fOrtv81FC4RJAvDGQPcZLb+ELDthx4m0zmBGKbgMWGcS01OMn3hNdvMs+r
T2uWxgKAfGIWpx+4Tau68NozyOQhmYa3PCKa69xPyRGqmL5CNqxWCSNq9zElYi1NKuq8OggZu/EG
ltsTusAqyFbMZtaVVf8F9v4s17VZITBq6sTQ1J7U4ZS98BnoVBfKyqm/zZKGTIF3hdEB+VpwRxtb
XRY2ZMNJBkKkvCgfV5M2jG+JQYmvPDvgh9meOgoiiDFjAGuRM+03J/LZYkFeL6pVm9NZQrCVAYhW
tI4QZmgns8jbsmnYnnW2CwW+P5LoKtHSfJHFQKSVjAZiiAp5lIWxsPF3zmraOX6usPPLVN2UZTve
WMnGXRhxUGp6LRZ18+enHsvFAlu0P+2WPBDt677/bUFr9hDuLrrQi5PsAN9ASQdilrrPHYAQusIY
9IYTufy0jebrOWxowNdujfFeyj4qs/8ZaONiDDfXschkAoa/zFBOG/XpsxQSSts2X+PvkTLqmFfi
4q+CujfQN7u8uti9sgkSIrjQ1k3D9UBEdpv7kcYXLuGX9Zp0UkfERFysKwt8siM9bXlbFTgdKAhS
QGdgsHPSsWrd+XfYBcRcMPK7CELj6PTIIXHQrScUQIFnM3FfpqXp3zHTgZ1+bvZXmxk7Op8eUCkI
kr+Dr3E2N7zZJNAK7ssumO+vHJKONJoYtLFNws/pXc5kpr/EzQRsly12f4H3VV+sod81uDR7rnLF
zgG9Sb4cXN7vmJbYxZwM18Z6xU7dAWgxHZuLHcEhFOFdMtHlQ/zO+ACxvczuts8Jb1xdltkEA0vj
wJtNviKUc1XxlqFdcHjrQkXAHrw/4neJl8jEwa7ZTPe0/LBLFxNOuVC8UFDu4CWQu5wwQcWG9XwB
nW8tMqA5I9ZKin1P/a1NArknpLIuBMGd4zvnJgyv/EK4GLeDhR3udeK7NE8PxSew9ExjqMDnf03x
0f2NGcD7C0RNaEkJXvZF/PBt7x0PD+b8YclFQ4xnPDyI28Gf6HQty2oAQViPc2669lRRqLZZt57d
6KKLKEBzylb9QXaYCYB1nQEHW3iNsJ8zrgAK21zO3oSqmCyTzJ08keFJrHNJHsJoSOf3XIF2HuE/
f7v/YW/vl6VlBc7yCWcXQcEoyUwDkkMAzBT/qv+hgCdx+BGKOHWGlSdxRJpkbsiNZUTszZVe19xH
jDkWzOw44bD3VsK3STemZw2j8aMPvNG0KFriEiKgXXKqDA0ekNQ+RGUmQIEreg6T88LEEpuQH7uu
2Uo4gq2/3br27qPbvo1G2h/GQ/97kja2OpqLLdYYHrLmm3L6tWtgWqwqvPtjqVdpgRZyMEFry8sh
aJQzfEvhl9r9l+CfKbFqBN2TE2LFJhXSfdow14evkinuahW83B8/QkbgN1D1yybvqXKV8LcWMUWs
cf4VKrfRFVyNzwj+ES0W1db6mNDG5+sHOTCRBhQQoCVZVHxdvTPqbsjY4R7+GssSHlrWydZB8wvy
GeAN8tKwj3RsQgnDAXX2cyHVu+LbSy71e6cOlD21KP9I0GpYA40aGsOiBsLjlp6vDSH9i68fM9Di
m/W2hLLDOW3PMuvJzO6x6h1HtR9WFEzls1QMmhvjsbnkOzX8y/jrsFUynTREFBPxYLZT/vlSxKj7
BBuuNskA5ud+B/3Ig/Es92x+uisnwhjA8TC8azlJWZTgdZa74L1SicqueFgPjXUZjTfSbp9pV2fP
fLiuPf5az0WXhFV8mEx8ABonjPQ12D577M/vmHmdB0pnZ17bHbuddKwFs2I3tCnXaGv+fxHaYvIH
7SqmxxUPupGY6nQo7MvpT5OD+q09TN9yEH51r9CN0GB7iB2iOmiumeyYtd/nazRVSaHp17wrRT81
GP1FTwGq8yvXx6lKPnH8HKXIbhwLPPJspzsQxVEh7VYMU3BE/SE9U4PsU8ZQOH6KjIZPvp057BAv
jnexyMyw8LrsI3wD9ONpVreEa0yAoRNnB7vkxZRoarHChcy//xaAd5/H2RmC8LtOSYp5ACsbJ1yL
AroCMZMP+4WYYFbiCWY1lHOspYjmimqH9DpnpXipwnpIfJ0j/k1RXkyP25Jp5kUJsrmjfGBCW3X2
eOZRWKLCe/HuMDjaGhUfTu16HSCkhiqW3N9FbuRzjwMjRWeu93j962cnwJJe77RKvSy+lx9BTDcI
Ch/s6FJxNv36Qw2jSn1BVYIPBjmq81vjzI9+EQBOzrAQj84W/f1Czlntt0oQ3ndOYfR7hqceZ5ML
ZmFbnEKUmg0lFwsxjBDNNv38bxPVSfxvKkDTVZ9bTT2+c4IZe+f4w7vjHwhGBnEVJmRJC3ZNwQ99
iOWMLH1fmFz6KE6izaHbNXfVPCKT6tgybWAyJ34NuFlwdX1MCqOc1PLSS47rIpaao4BvCbejeBbl
Fzs3d7E4o6dfjAXjY+axCZ1h+wJLb24jQK82XolslPlasVkNHD65oNm5l+1Qp0+CwWU4UUS11Sdt
e3X+WCRFRvLPx4Ku+LpRHS7k7OF1/QMTDkLhBWkn8gsFd0EzqEbwNuGJbfjV9u2ETkEjdnvqS31q
KoCut5XGWLuJuBygaBhMdetgsLYIlZskPUFu1Cy6bfvwBAEMX7gZp4ZpQnBDXlU/A0xZBaB/OSZ4
O6goGNRHRzaSFeV6UKSea1BJzPRN4hGrSXJ27wArbtXP3Tgg3wx58jzE/3Q1URVIWWH0GfoBET8b
pLI7AIiQBZNC62jyO+uuut/QpZQv3d1KUGgk/wgeVf1oHovgwnC2xWAabaVzrMhXOa/HSjWna3mx
cO5lHuToXze2RH3bNoLLAaHtbHruGaD0sElNC5UFIHAtjSa1DKe9aC62dEkkhldjgSujmvBt7ROr
DIl9SlExMrpjcEmz+FBXDAO6x74Za3m80gdPdTkThcaveizZsP3SKdCCIQNA/bub6SE52QvrfWsT
WnL2Bvgwd5mw74k/2oayZ5x81MmsjZKIGb3xQ5F2xoKXrIWGPCP/ufV1zy3JlTxwuKZPVyitRMtt
ZALQgk6/tocAV6LsWcstWIkCjYoHDxBwk1UDkFkbSbE4cYVr/2kR9u16bwcN5KIDFuaINgEHLlPU
pqVXxEZGD/uf3t6+G2/EOGAo6CWj3i4ISZeG3HSpQwJBHMCZ6exOsbbsZLdMCHrCqsuACfEM3Ln2
rCaPuz/P4KvY46sfVfImzGejZy6cS646KnSzAdDRMGY2w7CWI87PUZJ/0jF/AnXtexEV7jUbKcPe
5g9UkjeEnSGdYHFxqgIH2C/YVn/9mnYNkAiHaXW9K7xbCbVh98L47UB5BNz1jPNGm+NVdoo7eszF
WXiR7MjqLRG1grZa2Cug41eZ8D+N81agKF8jIn0QcyuYwgudqPXlrk8I2rU1JpIzN4NpY9Cgn4RC
/0R3Xu62rE/a2wqTmaMgniW0BMnfFmmpEj5gbeD62bldfEWjX37nHDgqoX8ZmrZTWJskZe4LZNZQ
on3Hhv5q/5rs1u8iiqYtm9QfeWt4aVj/fv8TM2e/LtB2TaE1R48Gbd/sCcy7sNGdlTIX6TrA3EGz
F4dZFM722bqqKr0KPSxJ4zIrzPCw9f0/RV7hvQaOsd2KAsyd3V3GuO94/s08wHmMFea5CgAczZJL
m0lkEoWV8uL5qvwIER2sSOQy4c6j0ak+wZEcQjppxuXIOWmrc9/73/D5TjBx3Srkh0BhfusLw7AG
RCe3HFmsbIsx3LJEwXc+dUf0EWIpK/seQ0V+KDwSPZNUkoNVTY9YeWnm56gm8kpngUzjM+h+L+PB
dFgxoMD7lHnkHegZ1189M++abrvMrlaQy5W9w10SZMxEb19bHrNRrFtL0aXSvVaYFCS1saRggosl
h8D4LCaob/YXblWA182yT8z5oQb13h88pqKR+p6Dhh2loKLBdXaG/7zYLlHjz3sNXg68c6UREZPi
SWccIZ3z61z1fyjnAYfEqsQiILjQubxXs2b47vxoqm/qje1//OFHQIIOrCZH0IXG8Y9P6VjS5X6G
sY6hCIkJa5YlHoumMpfkCVum83X6vwhZCOCqU3Re5tC50cSzhYTVqM8z1GeVF0vIVvom3gPKa5I2
Emi/suHH5xH8+h6Zbb9WvyG0P5/bVKal3wO7hxjUMceV1A4g9fhpCRPNiGJOhnVhHQegWKpbTZci
/gYmncmbRTqejDEsCBDZw3E9xoPVtEK0ELu3GJCbwmRcdPPc+F3YvwHr4EuoMnsPyPoADGbQyot5
xn295Ga0x4t2eJPhqfjtVS4dc0hDD51xt8k9oBMI3ZRI67r3ca5rRgr0apbyLeqby7dVSOvND+dy
lMOkjwaxzS2yBU56sUJ31WsIGCS62Dg+YuLwBaYTLheO21m8QJjopW08+49E7mom4Jup/TjZuUb8
NzUQEi5R0AYRIMuRs7swel3qE5yUlpgOGdkzV1vCrl9B0wMiTBO39LzWyVitb1UKLA0qj7QSiEOI
HBX8Dy9a9bRJmlcglVXmqfbeQAYco7u5f+fuvw+EDtlocfR4FyDEGdQGWHHcYQlF6CDu+QYledaX
ja0CctAHh9G8rfn4N4aioPXA8D3mzNtIwngERGq/Bftk55Fgj2g1+8Q7yZp/R8CoWkI0iczLz06c
4KW4wBSsK76hSY7fikktdrQQnqaXNtg69lpKuAdPJnHlY/WNdEVy9TNh/senbQSfT92agAG8rJb9
QE4uRIHaaTlvjzwwBbq+2kF14SV8Yoxa8grfhm7QEUuOG1O6XA9boZSI52aDUe0fxX6Qx9BCyzsC
El96lI0T8iarDp14uxM2PFXFvSnjYkoL91jVCD8IylpP+/qg6lgKB2mw6qwcsovCrqQfPC9syplx
9PsbJvvDUNDv3D/2muaT10Un24wxk8iyDyDyQSD221e4C4fUXg288zVEyBnZhk0v1qPTf6poOXw7
Zur6umLG1+ezqOZjEAQDdsEuV9M57rCqVi5BPKqcvu7KLX+pix6GTUqMAZClE8a63z+hSCX6FB0Q
oQCFEeUhYRc3jHZCTkO/S6Ifo1WfJ3nOzqZ1Zj+keXyxp/9fQgQ7ardgeR4ngnDg/ZgQtc6I+N9c
LsDn3xQbkXgPEdg/wVQs24p9qSXNfoNY9S9K+Qla3llKgzZNXANupC63SxI0C3zh5CPHYdKood9V
7meoo1t+8+WBsqSy/4sJWrRaoOQ5sIxAM2F8EPYI2g2C1YvdS1Tb2sTbDVUoOXX2UllhL1goQVxh
8JhY+e16Gc9Y8S+qqwvGY6d9ZDjyFMvKX3xfQ2QVbFdyVaHm6mzdWwZeyYKNE8/1BjDioMmuY+K4
wDiOaTCXj8qwS4WKYCGkX4R6ZwXyrEUjngVtbOxUftok5+5+fujeDiXzaiGqg3eSL3ZYnkwLJ8v9
sjHolGsKiKDiRwG+0Ym65z/A2JPoFL0HU9v2hohnk3Dof8UbtgxSB2xBMCeoAO/H9L4IqDls2wHS
6um0mwLe36jX9PRQLgpw2FRvmHN9wUWPm5gw3xMNVybr7uXvLoPik4mTETcZ411DyXGASDu6wgW4
slrx2/z/NMAVeq46xXTGZikO1ad6nb2HkbXHKk5jWmNi2U58BLMtGmsqEWoe47CPT5LOsyMIt6Z/
SEi3UmCd6qTIbS9AHmyyyvSmg4O/b4aNCIyNhDLxbEpzS4U1AE21DXVgmE18H0dn4ukl9Vtjj1Jn
y30/AS3mag5o1VliHnafIR0xc5FZ1NZRbMkRhgH4VFovd1ED5885EfefECNJGA8zEUaQ2lgNL6cN
itomF5AKoXgbXKcmiG46VI8S3MbSlo5sYcobc1Wx6xYV/Dk6UrotTe1WDNS+rKygZe47GRHamEac
lGdqfCbMajCIIsLpyg+XNfhsPkoSHbG3ohjqsnNsgvlOuUDFt1TBYPIj1BtEilwLP2z2thN7tqOx
1Ny23vAeZrxskyhg4fKH18QeXDYlzcuzGdTX0SGUGYD0n6qiMAVP+pk1dX+fg6HjVxL51aLpyyHx
Wvm/jkfMmIWojc/VkdMs8B9a9SzoYbtXINQn2duCN0TWmB4jnV0B8VDbHLcFRRipXc3GJ9M8Y1hN
iNZRyqUf3jCjIRT3LzhShRpGvOjF6LE3eojmmy9Azo3fA4Gsr5xYyqgzFWhZg+LjMhYDjDKNjlJT
yOmLJex5E0UafAFXGsTg9X5fMovbpoz5sA+IGugP3k0zu6os7EOK2Dut9ukPQozp/PsiOJJKea3x
Rx5R6HWFsBuXrUM10rPN6501kR4ixWD19flPhp6go3nnyUJZkoknXPvwJiKHuaBLA9EQBbzrOorY
ZBUwDpBWnCqecVKSX+qRPLdaYp+NDhXObDaAs/H4agYvzYRitHrg0QBrQZNglrQGcsPVRnIc3E25
YoMkzWYCb96McGJ8XYv/fAxQ8WatV36qdKbHlG5pmzrQSJY+qHRJLSomLu+CNGppuPRI3z3pi9Jn
9y+0SrhsJ2yFmRuh3sAvgJCA0nX+3yiJ1ykkXnCBTF52hn2t6/qqEhtdo2gHYpPJEycvhCgcBzj0
GxLQ3oYnIYyiy4IErgYLAmi5U41KCA51tnMrPIvS8VT2PNHIvhZcG27AE6nTIeKyhsQL1qoqRVPh
ZbXcrBmis3KLWOtcSfcmeEc4ArXd6CvGOyeROHMxiPe3v+LWtfquaJ4/6uImrOsZ+EzNjsgqXcr+
QEh1+NpmL45qcM1jQL5V7GaAkisvlqegVaa//voKlHtBXp63KQQ3aIYySIUgqB1mu/j1BVVpFKXW
pUpySopjqMPBJ+Kg0hspu7eg3DIb0o2O71DXhBOrZSmY4ITLnyaxEfkjzR8rj+eCSmVgczCyCEXI
dZKocjK8G+TMhXbDCG9YPEoj1sQQcJyHHiY3hxdqZ0R3Hw+gMFBwsTcfDlqbdeAPQoPC2lvySY6M
R1X3U1s+61UxssreKDjdzS4KV5zNS8pw98SD1UIxKnaO8mU25vEYJrC+Q9w9Zm1S9A+GhQ7QaU2G
J8Sk9Bz4m3I/3K+nW14pOVa01Z/fYLPHBbex6ZW5TcprEW1a/AH+JSm4etHWfLHQko2ONZtRxD84
LlWWTMiLtjl2ioTP7HyXXiT5qsexJ3Rjvr1TNh08XFPsAgrxzv/E/65bH2RBvr0l4iMQOxvBXPa1
nyfu4lOnkXOxXCnqlwyd1MGa+VANnCv6n8lZPCS5QY6zi4mD92+qoGWTavd77qjUgRJoR9ScbURf
7irs8Kdvc4Ai31MWFrHWNNLApGN4+RrQ8Cwxva/G9jKc9YHyhakGFPyWQetXWqdcIv0EdYzhekyn
6l9KytdVGhLWwJfpU4DU5+qa8PFX46jEssM/XaaPSB0fwH0dTBGFd2aafqrviPUw4hzKdIk2rCCH
ofPvxjCuHLk65GlQE7PtqwbkOFdegicXgry6LGh6+nueDDKUe5JXRDgvrH0l94JMFsgivGkHhbqZ
3B869y+eZw47rgI+LRoMb5M4ghz1wBeyPLrNuM7rM8JaUl1sgmfuWvxzoQU11+yMQBcXICrwpi8e
EggT1/e2SEAnxFAe64P9QYsWAqaZMeGbureK480WXuqobaLVNUhMtcnGP/7yVNQAgKC6AbTneURa
Ws5jCto8tR6dRhYkKy0DamaDJugj9Nyaz56f36lt+2KRqWjLDgxxSkSqbZSot4or9Klq5IJXrGAv
oMdSSPfzaPZygVn56jzGKH+TNkOkhRlhI83o9FmyU/uRQNh097BeNdZ2IZgmJQ8ZqcZJfOgskbmp
fLz4L9KsSUjn2IpeqCTNbw0rGnT9/7sx+N2O8F3SYxva4SqUOYwne0KW17XhJdEAxwyTp8Msddjr
ZtOajJgqMr+Q79V97Jv03pu9S1q9wytVqnZhexXqWPKtaIRwyZrFxLHl0ArZa9JxylEpYCYPGMpH
MQ5ouxZbj/Z8fOn+Iu4A/fu2QxbIxU8IHtzs1ImzhzPvU2bXCwR8TbJiqbQmCZqkFyEw9Kn5R0u/
0ekzAvLEmh1r/7aSlPQlmHkWIMknWWGxF0evtH4Qo39leGtgRl49F/s3a/mfEWPAcc0cSPenQRgp
uX1A9C4cIuMrBqESNfrbF3Enw6m8CHTFYUqq640YFPO0ZdOK8m62TRNWIa1kLTEbrY4IgUEOT7HX
bzLgdxVQIzY4rebQDmL35lN5duNXeqh3680QJ0stOFGCPEWeBBAz+C1upMsok2zMPH+3mIsU2FVb
0azi4AnHSt+2zSuCmH+v1JKxmsBvjR0fsfbB/JGtzhpjN10dRkEp8+yu5aAnzHVG8pk7VQ9lIPFy
AVArs0/UbtfSXZe76VqGlZoK+J3KLAs4c6OjgpJWLJ6bonNxNokuvd/0eXFdw6giG8DsyG3hnfB5
UQB1gbmAnarVRQp4yUE5QOYY8DZh/FiW+dlZD8ikmGl0jsZ79EnFyCld+XE+H13N6DWjFD4uMZvq
/H5BdsrzBnnfExQCsPdBMJhH/vPrrlPzDcAXQwEf17Su0vGZjIBU8QCEoXMLzEdiEELUVQ+IqSH/
z6Iuz/tXy6F4/PiSnOTa0+ZMtGCGcChHpATCPx/xy2eFRGopH7RqHVGKzEx/xSE60H0mi0EC43lO
hEo1MS4PvANAqyXAgs8JsGR8CArVp3vG3YVvq1WPm7jBVaPTPuEuw7A381q4Zwu7lJHCcvVWLyVI
sInXd/dpe1thBQZTGq96aQqJw1L9Ywf71JO4/bX5pMdScAhQLgcAqwrrFL3NAc05u7xiu+T8mJ9n
Eiai8MDP4M3QT/np3Sa69exRR574o7Vu6Va3kNWcyqB0v1p3BHeO80XgCtCZfwLNhUmCiQRFFwxZ
W+2IFSBkdWhyrp8LfFSe5N37fajGQKLQBsy4Ajdmt5G84i7FMD+VJZzE2F4quH+A9FimSTTNjkgG
pKrwFR51NG5hQ/hhOxtlraEwNZG6KVXZCTny9cV2hEEv0FMj+r1Htvq1sp04b29Bmm4m01wTX4J2
mChUJimedtjez9gPeafzxYpSMi4yhC7bokCba9UX3X26UgpEHCaj6PMZGxk3WZLD0XA8DgDyrEd3
4BlaoRGJrEd4TF3226/EcJOhnKaAoh8sMquiWJNdMcWJssVloTEGA1xCjnRXT0c6S2/dWpxfI/t2
agQJPaUvhKOu8saU7hFqwmpOYjYeKZT8Z4oAy0RLpvWMsf2HVCaUFzR2CMxVntGyqfArHfYRfRs5
wpO/1TB3RLCeAny23tWh3KXYgeeAnSeqFGUSM1Vkc8vQPY75YT24h3gBqon55MvvKHBKKbpWT7w7
b+r+/l4q8mXbiTvobiPOuZUXKAlSO+wT5n7tW+VCkzmnYPKth+lS5vI5NxVCATslyneudwalC5lQ
Z6Kf+ISYOqwChldKiupyMPPH+mJpVMLaASdpjGf3cuYKBTwWriZwIwYm4iyN5BBEFUJZy5aYCg03
MMTxDbeuLrN/ctJeDs218EbsDEmL27EHeFFRGTNL8ibqzrbxdJZqhsVMfrks6tVNMJ7ptJpqk5LP
JcFaI5AEsYk+pvlnZ8SWGs9PJdWCQsQVvA/vOYUDoaWP40rCKbyDpe5aUvRruGVtp9tbJdfsyVBn
3pltlx8V9KMQbvrc+aSCZYf32hKEV/lBhgI2SIBoON4V5/XaT9D7NDtTowH+9YRLGZOmyPfj/TGZ
olFJaDe4y966Xanf+/QHh5EnUeErP8Szd3Xm9z/g0IgaOHihBVjO5MhfH162ou3Cq1wC7jKA0/Ef
QCOgvIkLan9twTJq5hHJx+/WxcBZxkhQWMC3ut6rYLt9w/Lm37aTu8KV7uQFuri7ZU2u5Q2aYPbv
dQPqLTAtMktqm33jdUlp/Gh7Jmb1RFzcfAIUh7cXHegzcCVIhZT2rAkeniUkX8AhAq43iIQfjUoW
it3wg0LjeBLDtkdVKAZcAfits50ohtftl63Qrhm3iPYs+i7SKtddpomCFnTJK21SoSdeuRcHkM3u
nikc4qaTgX7rrcvr4km11WsWvvD2/PlPpZZXx0TB/x2rAKRc9f6CCecH9jcw21hpvO5ProeoZRT7
oVQ46aopVpM30wYZw0dWggX+lqm3DOUU83tTkiQnNV1ZJzQNfEtw0m7oiF7xQmADA5I/A4zH5taW
UpMl1SBzDhJ2DSqChSDSUGahYmW4qzswGad+yQiXqoV8phUVIwgsJWvhOqmZs7qJGFABx+Cgx9sd
PeJXctULsDx0iEjk1jug0AeTAAEBoJIYDxa5pCpWC31wBxTzprSkQ+prqog8ZJLGN0nOWteqWdR+
PP4ZoVvu1AF8HFvzt9k+F/0OuuEHizG6z5NdhWgiGyc2oOziY3X7nxlmG1t2I4C3iS3spyVWox5U
xZ+6D8tkI6nIlrRN4lnMFGxWqDWDEDdmbeTql8OgEDCx0f0Xon9892Px4gIzaWW85+PbCDtqNqFS
dG3sLcteAMl97UduEj7Nn0JvjIGO34+WSRzsJVsqawnFBzYlTtFhnHtQ3sr3aAC8NGSVDIJJ3t3d
aaFMFeoudEWIUevBdjQwBcCrtyeQTI/VO+6VhpPXQOJz0VWC0KUWXcf5Q/5eLyC/rluvLY7avpQn
XCHLHJrfY6yy660buWNpH6OblYl1JwEOkav0nAdXwGvrpVJh10UxQRJbQeQ+jU1Plf7xUvQ45PdB
7mVQ0ltvRk+S0g8uwa5AYePdIw6gldbAQZWr9JM5JQvmE3RroQ2RmNo6SRevBIKjHP7AAwDJVnvN
pTZY1UQYS4E9EifW1qIasXJvZNIiBU9h3H2rbjZP3Iq0TvpjuJcvwsE8JtSwwp0+d1OM9ufB/1f2
AaZkGkJDsba2JzqGY+WzTzfGxGcHH3lwjxrikzmKWkJfmVcnUUbfZVekyNd6+8yWRP0qyjkFfOYg
rQmwnpiDQVlKWyq4nzTd5CHlBGOp7hO0olixdKJ9reUbneNTm6BsMqLCY0tkV7SS4s2Zlnus72WX
O6M36lr9mVWVVuyb5e+hcVHmtjazmzkn+mBlEe00sIpId/Asm/flLiGKVH+xQd6qf0lOC7eaUsAV
pyGyx0uTZBfZHQSzOg9LJOTtXqUw3KBtmeb78Wa1un0emSsd9oSIIMrO5VjY6flxkAIeCNFyF5tg
6zYenm9c12PQN9lC5fJQMvhcRivQugriLhvPkLYQEUMUq2B+nu/OMteGmsWEt98BaNom5YdxjqvW
JdSyS1X/ItiYTZ2U65Ep9wIytgbGi2gxVrAujNZ7sgZAfFZYsNQkKEhh/pyW2s4QXKPBkDgA7vIN
3gaiop3U5cr+KuTaoXeT8J+XzoTYaG+LvpCB+GeACd5w5+yr1bbr9e0nt/0a/4x2yvWZ2yzUnPNo
j9nxRo3FZxbJWPQZngPFdwbcHLD3yUOWzu2+Ur6tmlGM7kuQfl4mplaW9HY7aL5E7CRoCrFxUmtS
nyIFQen95GVJN9nVZxaFp7FPRu5UFM8XfE+LpBFPcch/q9ZHv86Ym5L+RIBywiujuqZFyxAoVAVM
xaKVPIXmlWmgpA0gfg9WVqleeFl7zAP87Ir5deLOwBUFeaswBUy98ZOnKGT5vTxa8mD+5Qc3xh9A
j+aD0qSbhZpAT+zk4FBP9jIPD8dbtyGowt08FxZAtAy/0Dd32SMm1Ws/J1kXZNWK9vByVC6bxNOS
cNbwqRytPENGtJ365iBjpAdTyhLm+0YYJ2dLllwntum31BuKpYXZ63Tk79ItaDZfAquUaCVJDQOP
3Qnf+kxu3KGnF7H2Q3GvceP2tePYfnTe4E9RvTryGfZGApBiGrHlxgxrf48ZBe6LTvSyjNWha6+h
c5G/mWAjUFp+cS8s2mtQEugP235bQcOyobQ1fh4Cel/kq93Ls/V22YnAa+EQk132hz7AFjuuSR2T
t5ht4Xn/J7ukPw0QqdSxRE/qRHLLXD57BXDXv1fzfrENzDjWf4xKYYa3epUUUC8xfPe4bHZOplqk
VpvL/CCnUBUBhBISUVYV0YeZKi/0lc1amqmeo7CXkezOzhygK5GfH3L2bni+ryjzxduXr6FqIHU9
kBoxHr2fTzR+eIZtYEXmaBtyaTN6CHDjDBaC2usO2846aVCs5NIXj6kgi8N1QoCkyf0nj8qxNPuq
gmid4n4ksCDSPJHNgyHPr/AsSUdghpl1Syn+pEUsmIeadO/Z3VoFQ0nDXIkHBy9qas/HQtWJnzCQ
ZY9qsJkBmXOAwBl0ZWJkOr+A8cq1eWBop5TPlbInA+B1a0cocz35nucvn8GVj2Xj/FnQDEMhUZA4
AHHWEUShMkrEXsYWh152mceXrGDn4elR7s/pARbLC5maJx0qSBRirEPgj+OAMiJUKBxu2dX5Lxag
knWrKpVaXCShxyvlT37/2gDxL/0U0D4acXEI8dCYQhdWDAp+1dC+E1YI6RCKNOAddnpF9GmSgH7Q
sdGpZ/vSm8CSyR8/4xDlDsvpeftS/xoH4IY0s96PUUsJnna05SosOrR5ysnY7muUz5M5y7Wqs6uq
4jkY0VAEh7Cdor/a7h1qV1FNLVEh7KDGeGGpEYb3u4oYmSFwyGJk4aFce4NSOY1fqw1nWeyhPHAv
kH3tl2HFlW0brd56QN2VpNvDd2a0TP3jZ6ZlPlSs81ihuYqyaC4WJke/smiVTvEYPw3FFy8SLk4k
6whUDr5bh8dLJevPPrQbvoqQg2cgyUeCjy75WBidnHIm8O8KuoyV+Ko8Z3hNz6+77muO+RhqtaIq
+s2Xyf2A7vlaZucYVOuxQoLCuBE/9Y0i3GUryUP3ezCZFSLyyRKn7yzsm1No3R4whvspyCqn4Qgw
dSk9aXejTRsa9zW0GOL67M8lC3S2HTTocPvkNbAKp+ZdZnCVyvghuWVK/1KkJddT6UD9/r7sh9tL
YdlchKxtNDtvIouWqYce+tsFvMve24mbkP9mcYG7kLBT+bitHt8im/ETZqPEDBzEpTVKXuBCi2kr
KwRgvkKbdt15fp0JjI7o1V4bvBxFI1zTomwXO0xR5wzr3NLEMOJ/dWgjA806cwDn49GB+IFVK5N5
ucpSoNnREGjE39SXE9djQr3JEEv79paAwolz4le6IMODeHE3/oncXwwRdQGY/lSe1XdXUprfEfcO
ThPqwjhSQFHu/z77P75P9TU/0+qECzsOk3orN6kU49Df7xMhb+7qoHoLofqzqoBsZfbM6k0jvdQ3
m7H+nIUC8wjqAB1o0N3cSw+lAWDtlkRRBQAa8IDOfEBOFrwlWnQAB/t14MoMHNCoGfTWZnHDIBoR
8/XgIq2xfksPFfkPeOCxJtt3EVGb7KTIxcZNJnuqjkbYB6G38jLrdRy95XU0DLp0TZ12Ba5EMG77
TT4OyoqKytgWbdaLMsFGsdySP4vsRpC2aMWnN1PmTMMhv9/ZLUHeaZPuO1IkSx8mvNUSdpl209RI
E9A+hESPQkWk0hqKLU0skB9mGq0zNRtOD24TlSB5Fz4VTM4kS7Jp6dVNHSmFkZZXPQJrXOFdAevs
AO+cyA7DZLcSy4FnJZbWFcLcYRh7q/G30Rmmgaf9Gju97yHX4mkUbkAs/g2HV4C9W15aw7vjplwZ
hN0jmwAxs8zrtCnYESrS09dmNmu7zCOeZwd2xbKybALersk6zxXr9mLYVdr55xCeWqg1EgEgAUEX
8/BwgMtoH4OrhqKYovQnJwfpcRi2KPiE7TiSU1uOLf0k95r/WgRalESy8ZTRNziuoo0B7833o8mA
wBEQJAdzMVRTgwNa8Q7DvQXYoo2a0d6n6a6VtLr89Lqg7uveQi1F692L32aiol0gsTgAqNyakb/Z
Fb4nvaN8VjxvPZ5bPg68THPfuFPwYO9w+JS03ydBF1mReJ4ErEtqg48WzExS4thU8sf0K7zS7M+p
KpqrOrCLzmNQ+0Luuq7lXR2jGsPa6ATbaxp3Smhf7SDZ+VXrkoOkQmPcaP7Yaslv+JA2Tx4s+jWQ
za40p28dR3vEVhEhs7Yo+90XXIM3cpm1UBYyFaD7+//bJ+4tzjLsfR5+qkRfSDT5WRg8NzLemgzB
waa+i30SLStplftUm0devLQ1VGekK3A4JMIpFTkI7+fyu1BEpDPkwqvec4ABD+Oq7yiA6LFFfpDQ
F3Us141e8kRh1hffew+eYts8q8nih18Sl+AVAgm9UeVEpMO1cbelsXs0ZmQhSHpC14KHrLmSYixB
FT1eSxXZ5tnN2J4DmTZjwVQkF3wPw/0qPQTlGZBFBP7ni4IzXCX5JFryofvYXYjjXsdUG23waZn1
vyiQHgF9EeQQCLFD+vt8DvQr17zPZ8Vcou1cKBHMrxi9Yu8W53cnI84JMPivejhrj0ic6oVU6Sol
5jWv6O/SH+CkJL4A4odUlBxS443IwzAZz0faFxphwQnyfg3oYXrGh+r+0PCJfY4qq3D8LNf4xLLO
I1X+GRCpFEc4mAKZI2K9IERer8n+AftcLo2Z4YNza3/zEWfu90hXBzXDX82JXXJIFe7zVlfsJ+QK
/Q//pBE4DTAi62qXk/8fZCUKMAIGgOYe3KwZyDY6GBpx2lmz8L904KHVnWzpWNVZWHNU7xRgddyT
dVjzdcBo+KWj2TLM9GyKy+FDoSdIt5sUxkc3I5Mut25RXfESf1tBZPsT9F+22VI2Dm2ar651Xivk
QyXxAv3ndCrvFJaoX9BaFkCYhJWcYIIdFdj2Ix6zco5cEMv1jc+uTEpvDtGNMoqjBaDwZfzKw9aq
mHcZPjGTgtbSd/MiRa3hgKj8ZHgd6PKnJfchCat6W0A+M/fIdxCW1FkDBABHCm7wdx+dL/6us0HW
hiGTJP5AcP8G/L4FAJAuGGQiKbC9Yszkqk8+gfOSbp7gWHW4E5uh35PcN2CdmxMSqYyH6P+sw8ju
KjVi+VTnu8h/t9out0ynxHBu6sTifIPJdCdDAWibWrRnC68Eyr2gGbHnGficIvHWD96+Mq+mtp9q
7/sQNlD6SzKb28Ete3ahZBA6oWmhFFVSubYz3RKx0gVMGoqSzqYq/Gh56Ckbb0YkjkF6K3On/tfN
vyIPLAUEcNVY8cX/W68s6EEeN1/gOFK1QEStImYzbqFjwCNcAgMR7cbLl5zIEeXctS34KU3d4z7B
W0ATl3tx5Ev2jsS8b9EpjNM9nHDdtdCYvnQzgcJedGNmg0j+YgputX3m3kJHhaJPhgwImt1Cb/Ko
4jatRHIGZNvfUl39CWKJoj93Ccg2ZYeFFZPXmvIVg0VohU7JaZIEWT4Yw/9+l9mzy/KwqWWReq9k
Y3/lmLEmS20GbZkt5hVX/hrFgdDGvX/8m2OXrgGgyqrIhK02qcS1TxTqIO6HIBp8w/wtg7lm5Kag
/Cl7SFM0wFRK+Ls/SDGgqmgChgQu95ChgNpzJViWnjK1BB+SxvdRn/ydwgq4ZBm60pPiEsGuF0SD
b7vkIjIWVMqRpI/fpgqvMdmp3cIgzvMqa7rG2Sw3LwHvSc3fePSMqRl3RQWDLgDCbkWoNd6OEbij
RnmcJ3sQ6Vtfbx0DUcRd7TK0UJjpp5vAsQkOxWyarC7by1j+1zw63sJ8lqEkGpIbyypvt/XzMXOf
4FRRn7gNGCTL+GoZPNgyDoQyTyMFcY4xcDf0yqf60hNFdzxyCH3GgZWiZTXTFp1ed1C0sVKBHw6q
fNe26hOs+ZVn27Q7y8IEuOqHMfsjIp0U0wrF3EV40ln+BzDsrQQxewr0BoNTWjwJXp0AlPqDUcgZ
TfKduIzE13wQYFYOk+TJq+GN+1rpcN+d3yKpFxTY/p/t2bEDgQhKqgQKdwg5hoeAS01a5yl4rhBl
cM55EV6N7uNSY+Ds9UfJeBv4ffM8E7vbf/Hmn2lncXT6M4RQBu7N+0dpIChQR4wIOVP9NiHOKLr1
jaoWLtrO/62DTRuxLQuGyC5kbSsjFamNowI0bdXRis5tjU8SWfd9Ec5L3i/oWkR421JaV2759JhX
m2RjMfoGd4yeXO1D1/zXVwNqlSGADK6J3pI+NFC3vc0zweeM/JiKYFqJUSnunFJ6Uqmdcd0tzPOO
q4zcLvM8iGKQdqxvLL+WuDdsqoJvH4A/vAr1Ilb50PIP0B6QBi9nI7SelE6ES8FOoq36zBSdadTe
a2tsUOpoTgOJafMUqNfuq6mZDJ196/HhleSaFPUa+pNWaYU7t3WlCUElx77CRuYZCgGUXATiFarg
tJdRasdsRXkLtALjU/RW11hgjy4pHDivpkA/qdbauc1Mx5M9qxcuRVT1KoUMfTTekcNKTtLT8Y/T
5VMSUlgl7xNdOhgcQU7EznYDCQSg8XeD/6kDDNd0slc2dMfdEarNJRm5GuruYnU3acqbMvLj8v+S
im2YpX61X91lAR+qIzVeQwohf+fzLXbQ6M5pxeWeP8N9ZokUKFXTR+PHVPPpi+qWvD3BXPQqBiNm
Ur82JoLtlvHtq69QlEduw5CYgLLg/0No5REKecXII/RtgmFrbuygEjB3xaZUElYqHlNOi43pGFrW
R3lvufFKUJcwjyUkJ586FWJzJ/wkset52A1jGAR2lwIjxYpG1DtQXdrVnt5oapUqOVpzgKrahsEI
g8tboRz/mHRcqOJedUeEel76Jg+FS30ffGkI8T626ycHPIKqUYBbPxV3WTlA+tByEowWlCUCPSUo
mCUZUEPaVmtxiFtwVCdiH163xyoqWyoDAcIVzqsZbW1rK+TPf/8zqsaYIafCn7Y/JDxwaG18i01i
kyMrieQ+dHyNhaHJ+YTXBhOWPvVR1GEZmQAyMwmocoaBQwS7MZTDf4NPsx8+3KGUXL+P9WQozYWr
1J+0O9JfAUikvimDIWCNVsGMHstN8Cbc++8t2VXHOe7qmj91IyCyRl4EvYQC/p/wwGo1g1hA60MH
PYor4TKTiWXsswsIL9IORG8rOVf0Xk4+hWpIOTeSctrPTmQ0uhDaqES03M9Tuv/nnYH/uAY/6Kg0
YCMWh5bP7bNewJQOnIQUn4wx4ylqhpXex0/S+Kblu8psNTci7HpWuDV65yFIQzp8jwwo5aiyYFrl
pw9VIwKFPrdWTSiDN1F7MNLJku1K4Cwty7t4jeINqkbTh3uNnwCaMOFxKnoqj4/5T6gVqH0Qq2UV
oENCisYYYzTM4C/l8lCRXJYd+Iqg2IHFyje7j+vj3jogmiMrKkQ2nftZNeCiJHCNde2AQvziPvaZ
WdnK37QaV+MND+JAnlUgtXzve9d1I/EIq9NbA+mFYa+4yuMGhQctecyiaKcex/mffMQCKDz7u5p5
/VOQQQgsHtQ+5GqyhbYvKNxG4YD0b9+c77jLCNBOLKKeBU4lFBBCawTnnnOdmM7xx1krblMbqGkf
1QNTSVYYoAV8N1BY8jRqu9lnSo8rXmAOtQiXuRl7ApAz5/SxnyMMOz7rXkBRzQOknr07wE/LMPFd
/LHMopaGPB4d1Q55n4e0zEMtBOhZHofjgpJcE7w0hOTRI8k0xbBkN47dPPQcDlVeYBQwSlHtgvvN
JiOCemTAUgomcJn0/a7VfU9/QUQ9vrzTMkUNi3WbKUunVDg1aFp7HxbaBOed7nj4dEmaR5oyxAxf
C+TDnwge8dgq3TPaV7itIiqMOcG4XllV/2Dz9GxSIAsnHolg3Ova88RatFA6EMdrxGw8LPpndH5w
+Qn2V4hDOEGjY7cfmSPv8EyBwWcyW69QpA5MQYOyQtW7eZ5Zm2NbfDoDXa9YzSunqx3hMZrjSHeQ
9UDe4Z8Qsh4n47oEN0QNRRwzeUn07LwQFIOB59eP7C3+E5kCw/bDIS5Z2FWz1tKe9fZOEJLMxERh
PIcLsXhG7qwgo6kv1IwImuysAD9Lt1EsCBvf8EU+vyED+afoZYSUCDHnCGbZxABGbF85i6QZYU2L
AOpXQLIy1uQEr4Yk7I0Q5WmRZnAomHnVBQMaxMz2fvZm//Xyko24wdfj3h2HXO1M/NFl42a/OOig
Ye/vhv/UkA0IIPaJzwJLO1jK2KkGGY8kMocxWW0VBzj9UgULclIzZcERafE3NDi8cJN/0BQ6a41y
gXIh4klSuKA6Oy/GbKaN8TXRDcQXmNUKbqi6HjUqpfdm+BHqyaqfIMqB7THO6oNANdI7f9a1nl5K
Gg41sb4WJNNmzmnRnn3vnKsOYMIpF30We/6hDqMehTBlJfncyAi1OTQKaH9D1JXkcriH/QFg67dU
V9yiXgMR3HKbR5HLV6ouosSO4hJDFRljyvCRoPIG5gZAuh+XjqzDsyf9xOS3mYYGsforUKyA5TtM
usCrLayFZuzsjNaZH5PreC+SuxbwsnryQUWsW9CJCE9c5R4WjkO1zV0SClkBkbRxJG77W8J4+oGP
NytO8Cjaqg8keCYRqNQrRuUdFydaHEd1AZ0/0uNGewQIc3tVP8vSKbtEXWmyJY1JI5Y2kZmJZM2P
j526+zeM6DVD+MlnjMJBA5OHd1xJ694DT5KzYH4OVy62Adoq5G8wmwMhMFU0koE6LC6O98PLMR1u
8dVvBikSdC5T9i/9kQa1MrMdmtZr8S235K0v/pNheHN+Ib7b1b29WoNlHoKKRZqwkxC4jCDsymT7
QkzSWs3gcJNKbTBURjnfqcZ5UIiXsURmyY0J/eGuVbFyylkodSrJsp9Q64WTrdJV1Pm1cA5MaC7g
uluv7HGKNZUayerTLpQK1Iv7tL48KyIujMNn3xe2mPISqNraCnxr4b1i808x6aUkfoaA6psBX92X
0lPHtfoiskBOLnyceW9P3KhSZU+cbqt9g2pmf3MBMUEIhR4H3NCEgUeUwzzLhcOa75OdmFqO1vV0
z+gYpItKWoleZhe3SuPCgSTCqfKk/PCORES5QoXPqYqxPLx3r58OXLXV2Xkgt1EVjDrz8jCLLT20
p5Q/n/5r5ygySIVs3yCdmrSela+HviMdkhhpr/C7JZg+7nTG+FRzTzggysAAB40664h+ikdeNyhu
nrI4Fn4HXw9o8fEZwT10siAA+UcRGJAHkP+ht8v0s0nlEr25lzKNd0F3es/cJmpTXKPq4pP5dVc0
AsCD/KmjBMLyZfwV1hwQ+CPBudPx7Tm8DVUayhM18wVlu8vYtBfI+QFanUiJ788gZsyMxdSiUki/
HKWjY0b6VhtHexauBPRzDOaI9Rbjxy0aY9ZfYZC/wK79oTzPK/Fb3bVKpx0yZBKIeWS/3Chd9ts6
sFNwMgre64ncTrxtR9oyJQeg4Yv2Z9zGG9NMYaI21hrOJaBjXsFPQIJp8a04B1TGmXNK62jNlhuk
SV3OG3UF+whsV+81QgjbRbzocT82XJs9wpDjQB1gE9FjvoqAmlXpmNis3baxQeg1bV4acb3RfOPF
fecCq/va5xsP0JibNKTO8Ux78Ap3Mp/0+8EbmJROg+OHENa6gbW6R2UA7jplGH6iLk9HuZY6Idiu
/vTRBkSsydsQ29ROKS6S9KYEeKYue296cdYm4TsHp1Q5Iwjf5jcsltmfaH9FZs1UAI3YITWP7WME
RSimcekMaW+ZEqhpGyw0hJfb9uB1S6bMVQoRukinj+lIAr4lj+uV223Jc7/pLV1sRjFnZfmPU3fQ
YQ8XvfmKk2k9RXKNCv70Z5j2v+qM7n8Y0yfwaK4rdZZzdjFCjQOuth8OQFowEmMu/RJinFeYFqvK
Q2F20R+PTLmLjsF83JpK99fUiTYo0KCiT7JFToJxT0VwLksBsf22uBDHIfZqYDQeV9zRZ4OzPIWW
81m2l1FWzPqHYQhYID3mH52DouejVkB2me7gblQwTndIzAydkKjsH/M0v56XiA4bBd8EfCmrwq5i
obrce9MBqu2iSKwiHQLDXH15ctTJ5r37eoG9erLCRH82sWMmyFr5VJ9YAO0ww82+5pavqa//gVIl
7zQ5gz/M1UZUQBwhBayz4KnW3Imnr2pKUajqPeajUDlRFJ9wLWC44jeZzF67mWTu7v4KKQpe84Mw
X4QTlrsJjVfgUUZM8/Pz+VoWDm7uMX/iAoH1bSBqmk6Yn2ZlE+CoWUIUADtFh2dqYIba544y+vrC
ivWXCxTp9NrbmqXVpv7IADBfZ+cYkiw87GqXxFjikZi88L6YcZuvMcZCKEWIAqkZFfoY0ys9P2d7
Deefnb5XkZJOSosdBOsFPlRfAhKkiL5FVTyDHYuEG6iLC/i0Npr2MrQFSjo4AYXfxHoP75E6L6LE
lyVZaGkUw1BIsCYd8gnL3y9B7AKyiX5RBY5TsCATsTCv6FbFmj6stpICYo3VTtKUbBrQv/6pO6NH
iQLZkddWOF5MjqkeCUTPTf4zTTsb8uizBDiePoganVTiFh2CTs4EE+tTvB8p3VdOxwoKxfnpI3uB
g6dKhk0Gbkpn410V0NVBPcAz07VjsLMaVGjNv3jaqrVs620Bm/7TU5C/5XY8Hg9WsWvROHRJBH7I
7hgVrDAR/2Dr3SPl5GfC7eOwusSvsq3Cbz05IXHmxrbeL7ZVg9hqPHO9a/UhKpAFB2vejSZk/8kd
DiA/RuDzHzKUkyv6WYkUKrzVeFHYEcTWCLYA2gAFNfZvq1EnlNwksKh+nbtMq1AEehgvA6jEUIn5
EZNEAL5AYtDEvJwblYltogOZMxvie2tHfOxHBK7Vk9Uhl8WHdgZzJM9p5gnEFoFwphRNfC9rngph
HmN6fSP81aHyao7sOWkQ5tO8N47JDZ6bnrw0Gt8l+gP5LE0qsuaHDyGHuCdqJox7O/91AIojZmYR
ZZW68Zs7EIZh6KkRwcvMLWf4nTqvSu7oaLg44SIvDmvZ+Qu0yduj+c2esuKfX+3DmTX60uJNAEg2
xAy0YyQIuOottYsAam73G4bGBNVjaHpkqO8ohvUNnbg3yNcI1FTznluvHcAXN4zY7Q5u5loRbFv6
rtqM9AClzA6amok6p9t6iGh31XZv0HF749WcjJ26pKCiyg+2nOKiUQn8sVf3y71KeQ3DlfENa3wv
FRuRgNfsw+GERFxLz84B0orRJRCfXRXgR6uFUu4rx5X3Rnwfsbhxj/tn9Hdz2XkXkQ4JTKJLrkc2
LQmLXWYKvWoJbuMi9Omb2rWL8ELus++OqTCFlT/c+RkpcTYmNfho4KegGSNwLb2jlfaitojmJyTj
MVvLGqjgcdNdTWwnGKO19u+lTf0eYyuGU1Ssa/7rZ0VyPIBdpH+RRIfE+n6vrGt26Dr7sUjSigy5
8gnWBbKmT17ucOKOa5Oj3EfE8RCXVZUEVOzau6qwWaT7YCPJJ9GS/1WmsVCcXLTde/zqo72atE1k
4tiqoJ9t4YbBU4b4KfV6VJDY56dihvv8PecpesYit6pc75J2Gz8wkUqr7mxhMImKz2YA4hF0fmky
m1zmKcwa2G3idRLrkqH/FQglaCoACev65VMHDEafcsSSXCf+mO3tiOXRG5g5vdYUUWI3NYq03hUm
O5kHRGz/xB2LjIJZ0zsDekwMhPw1NF+1/pn7+W3LzogHijVYy/3o8lPYEEqVGArEoTx5qDK4JWzc
iQkiKGVvDN4qtHzpQ+flbVh0L8jIB4tzTpTDhjpC3I4rZV5z0gl+XX8oJcIDOsZAUFaEJyHaLae9
yNde9LmHA5OLFeUOIX9To4Y6SvHOqlKh7GqFHCblbkyVOd6crWSnqwhUYDLMWRXGrAW8Wd84/Zr6
pvSPS/SCyjpigzaFPizBlpCzHfbuzcZxjti070/xeh1Nof/YVo9HKq8shRLFb2rjMHtTpzlfB1jK
dvQlQsA4N0AfX7TpCTFvGaBQgmxTNfl55A4FkGj+tC+TCVHZogPzER367WlwhbF+WmIL9/vzFq7U
Urn+tYqv09jv1fwZibj4WMYjgQDwfbGlVnpevZsIpWLQBxQbKLbSRsxk5QdMJjpmwRzbnwmQZiCu
Tjc4r5G4yqHY1o4FyCVRmaAItsF5+FuwFmBCVOwhPo2MAss7r46eWQnbTx7A2QTtPItvkFwz8NSD
XPj0fIiuXTUyC+ifZa0WjcitrhEFxIEaPcVjVjR7OUXdbSlE/ivIYuyTFVcYxNYn07ARqDVWq5nI
olukfr86BKqKSnfjS/NOK54GXX+n4zXw+sgHPNu64WyL5VdcW2686zbWaWa8RjOC2XxlX6/kh9J5
eZhuKTlsiMfnsKdEreaZVbflDrACrDe6hK7bOisqCz3Tq5297svHD4sYtA/NGpC7STdUKG+klKCH
iKOVuavF1GGGDqAN1rpLXaOvGeiZt7jK4mLdEtX7vmtG8GxIJAZp8GTpm8OX+voUob4RoLXfKeox
I3Uheto+HWkqBQjHaq6FJmtsAxioZ8lRI5Q5e5olMSDWcdOdZ7fHtVFADwg7AqRsfdmVALi5a3nF
gSD/6BlAJ6jkfFJBFaSgIQ0PzBN7p67K52tQ0NvXAlcX8nA99ViM5JfNf469Q0s4qkE4PRWiCOTf
78NolyRqJUMvhlh2l+CHtoxYQO32hJwA1osk1u9rUF8Kl3j6ZOTVujj6AUBI0ngcEBffNhGhJtfs
Kv9c/xtyay6CEYKMkowNCrIXx4HFRmFuse+3mkgaovv9gBab71ni0f32EotsP5490xFuA2r4mFKb
vyp86nbqcqXfcIaCqdIwYjSdM/izj1bx9sr+8b03DeYkG5nYTiwy6UizMzVD8NUMMUPHRHSKh0kl
HPePaUEaO7oDYh+rGRQ4Y1OUpWrYXbGQLy6dWGlhGsjC5MScXfUjfhv7BXi0cAvq0VHppo3/t5pu
lvJJTQ325EBW//7xUH95pMwCKZp7rq0fQ9zBjWwUVagL8NJINXlD9IRBFiOylYs8g41y5IpyV92P
Ew5Wn8Bu6cEvRST9GUOuQfQMpTZG9aJC3rUcEPcWJcEPNsTq7lKh+Wz0SNFc0cBxB+ERXPCTP8L4
Nyj5lCsnQ7aFfIL/c0O1BAiMhtxyYapGhNb5XIn/JuhcywrTUySV4IfQUzyf8Yo2couLLwItUKMI
buSWPmt34hEQ/h3S3NDwGAvwS4vXfBiFQQ2oalgvN0CyxT7N4moEjB82u8SsNuiMOcmtet7u5ahd
Av5GalZu28gduOU1iJNDvwa/14SQHr2bZgNAE5h2j7wS6J7++9i+7wckuIp7OKWNUH6pcnRpQet5
WqiY6bC1SMpxZAqdhNuyrAdbWHQ4Dbh6ndatiz+KG1V5q5RxnHDd7pbJRHQmI3bcnY+1StXNjr6F
pw5RW6lz6ewN+TPumc+aqGWHvr9XuHUc3cYpooGhW2AcvB+XomSQIyXyocE5zCF8CIg/Au6G2vUj
aTEnPRL9/pYsfznTGjG3bF5ED1VNSDVWrdyt8CCECYtnPhlrIwxnlbo4H0qErwYiI6FCcBNsA3Be
Q/wmFcI/TTp41Et2GXaGZQAu7T/6x5ccWcw6gKUbT22kI4N5yH8JnXILKkJVhmNryz1c0yn5zGv4
qvFFNdNfkXc25SDBY8AY+sP6E+CB5lFw3OSZGPl7jPJiLtnn46bepRI7c5MNCdl25yk7oOa5B8GE
RASgjtwNm3iAIKf207bHlEUy5TlfhNg/VXEu8umyV/BPdpAlvQrJISg1FvNcNifxAG1YzcMZa9OK
SzF6aCgHqcv0nU+y8YTv//UCWlzW7qc3b+vDLOGko7i9tWkYXoAgL6CHNrzdIvNoT8wtdVslVCOT
8fH2w7jyLt/isU6UXOxAOxaHbfKmcrCs3Ru4NHAi7crair+OjTdp0EJgRdmtZE2f5j3po95kkbuh
mj8dqPaKC3k97DL9W3V2qr+moQH/F9Ka7UpvVNRl37YeMYUzTjtgZc87Z4K6B1CUba4t9nxqd/hP
UYOlEJBFJVvIFjlhZXWMZXijqpcddy0ZvD4JqYBPyot+QuizzRk+t9OKsIbpv0QrfBDzAccWt/2i
bMa9U1ZYcPxgjz1ZQSwt718W45WuqtfPtkC+n/QOK4kMwxWiGufV3zGBHR69pholkI2IoPESDfDE
1YGs9gvCIm/EpQ7UQbQRjJaDywn6y9jDqyez9KwWVKaYeD+LJ9HmAgBwx5b5eao80QleT0y52qL6
fTE80rd83YUpXI9QpJGYOQIAaMgpl4UorU09usDu4zUMe9PU5QLaHsWcuXM7bmxjYr5FNNZyYFC1
b/hDX8paJWk9BjMruWUY4944ecu4X/zdJOxwJTTB3f3XpT8GOIZ/ckuhNHpYfOy5MsrmoyAnccGS
m4pWop+Uvg7t7/AoRMJRr9AJRZ0npNoYpWzrwzriWPxeDcwIEbFmKzJezdgKquiDH4Jq4EevS9C/
5zbH+Gf3yPHPG7TvHJArWm4zB2lXGZq18oRH7gMwk4qgembOth4OI74KI2FGqBfgf5UB9HGJVHjg
jJUCXYWwOo50ThosKwTOIk5CSqj80R65WsRRthNlJ9NYmja3n5fWXVvcw7GnVfhv1kn9wvqyrZxV
HHjJfTFZEgZ2l7gsx4avuWTqT4awiVF1pTCtlDFir+t2k0YoL3GqkJDGnhWlGRLGHElsVRHr+uTG
KPyF2pcablROoY9NPpBEuyGa2FXmIihrHcIWncm3sx9dcK23Yel3JSC2XSEnbIs9h00UAF2iy1t+
3P71zSUP5qnJ84WkHVU6ZRQaIt1JJAf1nUnpdevzpzmYZcsnq/Y0y2J0t6KttgBX1q2ThfRtNMfR
VRW58GkDPcbiMztPfiy261RjyYklGwnvhO7I7vaUOWKeRaTf4XwP2nwx8f0D/PmNb9ZZA/LCBBVX
4bcYeFPUaozzZF9Vso9BkvAsFXs04iPVr695+v38Ak+tOf8lKT1tliIxR/D+xBiyzP8MlCCAFKk/
w8103xUfL5jilPRycovHaJpF1iZ4CmCaoSGWtg+/D9uCIyNz50PtVwKFWqKjndIl9Z8O7HXPI2rV
FTBp946Ub0F9iDfevHK6UxmM/mpc+pRo8NIvFrrAZWpLBMboRfqyBKIFHzMpC1Wnzh1pWasTEDJd
c5SKHUlMapvSzVLiA17d5jILNGo7w8n52qCXq+VCsDJGZbYJSfb6LIDN1T7QZN5v3s4Koh31ykrd
mMo7svObq/gZU3J6tpgKdjvQSYe7ZXk5NfL+UI4R80kf08A+ANMrYb5SZFD6C+74lUMg2DQnxW3q
sokrBCL7enTgh3qOYMfoL0gaLy0O2ph/6VTxaLo56JtJ+zbqi1E3rRQWFeaUl9j22tuBfJkMmXxj
HkSOE1zx1/XD4901y/IF3m30D1n61mvCNNHTYVWHM48beO4GZo4XtUtK3+mCpdHG6eDFPNDshrD7
St1bByEY0q/wPHPH/V3tAKcOBCtB6ZS2YW/pY62cpp9SYy7FueKMC+UrwrONbofjo0iyP4Dm/wf+
T0L/u5jRb0g36gm6l27eRgLMsj0bdNYeFZ8qE36QorijI9/5qkuwpddw9rdH7qSS+rGNxKtt2KBH
uNTUUZLYN9uMZ3x0YYbnMsW/13peTV+ota9XSBrZMEtwiFOgONaZZlTCG734ZbDJBSvan9x3HCmH
ipRvTJmgjSjAJm/VpaQrpQX3rWQ2XFjj1M7XHF+mLh4Jrq/Pa3dWdxDGdozM+o9J1W8uwfeNw64Y
SeQcj6mX98TZ5DRcRgsb4eexOZyIUG66gzfv3OCbKi/OBGfpY1yVQXs1ZvXbFcp26EaHo/LrXUgY
OkPWnYxlE5lLQEmdichxtP6BbHOfTxgcnoNZ9wj7JDyPEzsHFkCfuS7+kiD/TkgKGZMZ+tSXXr/A
M9liN3jQ5nsjao4UTumyuwTu4duIbmF/jBSNz34wQtlBiRydOEbUn6NvPszYVzO58P15eVwOIeF1
ijKhhkvVUdntdCOZDcNkDyFrq0r8g7Wi9DfgsIGm5fVTJVW2/gpFFvc2yR1MbTqIyo69jdXGYbhN
JL/qaECxVENSt15hzOx3PzVuo1vK8zEAqAi9bO9HIEOMUaXbn+gTaTc1MBiW//Ng6mB8GbumR+f9
L/QzvPJEtVDdnaahur9Hled6N1iEPQpQRHEb+uDh8TchYkerpKTWxD5X+hfsRTAAi/sd5eGwVPni
splCQbfttUJDEyWQdOWR5dFfC5MH6mtZUp8UOysdmyxZo6CEwmP0o2714rn9paiz9KVCRC9e0aM/
Owytg0gzVzKxcaLGbWG2IOx794a5yGQ1l6lTesVI5vQHVlbodu35RmfQjtywsEEbkfM+GHDoSASS
pIRv/jqPlQTJBFn7H2DIXDb4sX0L6EYqxuesccZG97H00X/Mz6Qub1TqjjaNYmGM4iKFt5SOL/Do
1w8VEgxgsvgeBaXajH/Jz6f7yVHpF2kM8mafEXMxqEhNcXdd0ugStfGnbNZSYzWmwl62BtPpwFRC
UYdjZgntHAmGJNaV/9f8f39zpYH0CfPskPa8Yb5iiEn//gU7bISlsPqzj6Qqe1Cdx9NHcgJQONh4
okwZLYFtuuESI89b4iy4rvStTAY4KI0dtG/yBU1sdocJ98OnuamjAH6ftinxIKH8ZW20IKneFiaO
Ci1lNGK1+G1HXaxGnpJwOr/0AMlpyuikXz21cYbHwCKMNnVgJ1RtgPogYd/ZPQmg33s6Aio5zkPy
3trWlaAMlHRabPqnz7nZH3vWtj2wSoR7BxT3xNcUqIjb/vf/J9+JXc/tFm8bivTaQm+OH/248DYU
xgbJNJNiGDHrdCqH0yT/sTsqSquEAFsfqNuGJIobxiEiRp3Ej8WamktbQKbwwicg+M8BVNs6VJcg
mF91+6CCPZHZXQz/p7pnCKdvGS2xW0PfzR4IX/iNy1RtkXaM4xP7ciJSrCB0KtBd9YN5sGxeIa4l
IWHsDLAAzrlpvsE4dFSaoabM5tQKpOMORKaauRWpFVeIX4LkN+ZT4JJHOoKFu3pNJeHQjp04Vw6p
q+i9ZbcCR+xq6wFOKZYpigjZDk7JOhfAw9+v1Tab+v44RveLJh/ihcZS50abxBk8EMy/8hwrbijH
W8ckledKlRXxvWkRjq/oWfKmA7X0PiDQzGL/YCWyjFtkTlpjcCKpxP9aeg3/HsBTzR4F2N8QpUvz
7TLzpnJ0nZmsLv9ZbzgACu7LhW7+TMc+CkZ4Ezhg4IIuxTDi5cGLO4W6Gd/7E6514voi5RjRuYEf
bo6rQxXs8YUAaOxaIDtZ+slbhICtfMUZAHL2jxc4eUGBxuQwER8hxOHUFYGmlzVHZW45+PCJo5M7
gqxJg7KAscZsVky8lewScqaDiWFVK2/Le0R+j0n46uMs2cFVtsIwJGykkE+5OSzviuZKmb4KHzdj
+cFsGiprpYyhT44ze38bBicvraURVuAj28Ksbja5pGRpnq26dm26Atwlb8kFYUVPimpEHgqZtwpu
ZQd9viGxmOlcfSBjgx1YA0QmGp1pohacGnmU9qYSnrdxLkLIN3ZzCDPvY6A9khzBKiCVoPQogvV6
EZ4v21GoDlqzqONk6PRDf4eJVHLkZfHlDhxRntosUuOLLFbpcZiEel8+7/Vb8inqXnR8o8FviYPo
28ZxfGNENnbcBLy+A4fAP0EQ0FfbBBGGOSw6UXwDbAlEge6omR0r/1TsSoZoEoAvJhdDt3HHnu6q
/FXgmFMLDGnRq9wIoVslMBC445COvPc17hoFM4dwTvabyCTfGSQ7jt0FCrBAzrtQGMyKPg7AmfI1
N0vswS6pC6r2oLN4pQm8sFRG7SU/6aqF5b3JokPZepbCBQNzs4D0qYaaMheK/g0Ho598UjP45BYx
1Zip+gJ5S2ELE6UO2OY03c2pTUJy65npfRNyHupL5bSRL3LdTYvD3S0HAbhPMMAYBSSk9mZmvk+C
DNrMGJjAMMb46yAWusOpJZsg4XgYCyED/y+w/48CH+r7c7xNYm3765u6QtpDd3D4XerfwPSA+ST7
XwwOY5rhYsM0csooAdsd9aJ2El5TTSGPju4yj4g1fa4gXcYv4bruzMcQ3KjkSU5e24ofkk08fSqU
iLkSXeEeC5GXw+2S6ovcFhdbs9VaDWUV967dKqqLRBHxrLEHCKanSWYX+Z7hJlFkfNHSTj2m1Aib
mxwkNsk+hQ0rvYG7kuJvOUDQynv9+O04CgKgfRdcyK+GZEfv60M1xC63HrJx7BGO4B+oGUU+0d/f
yR5O51bIioBCMbHIqB5M4n83vws9gp1FAojfKIuwZMtLYx3IAPo8Mt/xbWGbU+OhJtAn3BZPQrZ6
RdgZ+5amgwtlTQVr0n190J2/zpDRpujZqs5dIv832UAIn2V3x0XDt3oHnmLOoF2z1VzwcU+sFogW
OuyH0ToCNWKD3WJSDBKuhuGaNJho/FU+DQN55irQlaSOn+oVP3qYulUOHG2bUOkfCLHnyI23VUmm
TyQM/tpIG+qtG11um/0UCa/L/zlVM61gPVIYOijGsBZeBy2chapBfA84fcg8rjxc1U/t13GoCTFw
BL21jumNx7GcNfpuduj5rIgR4qMZCvPe7N1+mAEqPIdVJtT/WLKmhPFQGqHEVe7KlxeR8r6molpr
RHkTASfxadJoxJNw7M7YfWg1XP1JxtibIE2yaTMjs10ZJkMKrZQUWgAtrzWs6/5z+NJhQGyFq30W
/ceTllHxBXJiPtKULhdFCpQHHGS8lwXTlf7Y2UAxkXWRQyf1zEuPuOtogunoUUDx5Bx0druwoMFW
ukGRCluW9u5rpJ7hdCMnEk2x1cB99x4byBM3iBlroJYUJcb58/8PPgm5O3m4snbL+38ijy5OyN8Q
zkJEoqY3P32nGI3AheysvptMczp2Hp6WoDKBxdjX5UVI3W8k6XYIRfw2Ne6qxi5jUHH4WfovD20A
D92+6QoQW53Ftqt2l+seKXK/+mi7wsQWEgG2S4symFKUIsiIDkAdSr4OTxuqQKFnw6yZvGi8cByy
5xk9+FMk9JJCbxF2PooIgV4VNea56sGKLWyd4LlTrjDl6Nz5rQfFoZiknwJBa0lJVGWnZ4bEpheM
/Bfot+wdhmZOnqS+DvK0nfv3ZcH5ROXqZtXPrmPQVgJayGs4g/L13YQyXlByaqHAWGkg+VJbOG1i
PH/q/vbfPEca5xKioWrdtqkUa1z23qsTVd+iW6bXaM9GcPV2pxEhtSOI23lUZ2tjxsTzAm5UbtoA
+pUqYDydu2Zbj6WR8qci8Rt7wOoe/VUL4kmQraoY0ztad3tzhp+1z4EdGcg0HguTWhETIXPV2RFv
wwLO9Oc9uXhPd+QUJWpceBcGrVyHByEsR25vHnjIA0cEdRYbAANMtaSKp4paZo4LJ2pc7ycegKYT
XNfDbI2pS2IBkdosTk65HPVkdf7NCBtKfdMMIZxfxvQXCwmx1LYWhu3+2COzt1ori2EJ++i9uN1N
YXTclObB3yUDiqNH/g9H+HKQ/mSA5b4QGJGdZWgUQMh7wK6R5jAUBLw0KTXZPIkdTwr26VV7HDfr
rpM33uoEkPMTIbKJAtFyFTsaHRrgtAEJIrx7BEJOQ2vm826bHvenPCj6hOZBJTNlfL9O4cGsiCuT
xt8xTeY+3J9Dea8idfDLEpSQlj+WsR9GR+8fw75y6uxuLrbcAgixsfTnFJVAb+klQQN/e5iERbn4
PRu6iSlsVLy3XW9n8RLysFpAcJL5GV7JNo6iWReOO/uHAdcky4ZVtAsEZLp9FvkHjDcGcC7DI1sL
f99IrG1Mwiyc7g6IgfJwz5i+4Apq0EU8+x7JEgqMQjPX0Id6gC3j3hY823ZvAQMz+AgIYDSqeaOu
0xWSJpt3Q1E46J5bWxoS7/YGNkaAMvjDna5iXLJsl3hEVi2EqUnLbgbxFbnEQfum8G6KLU3igrhA
jd8vQlpbeWnBK33tLiAzHReFwbs24u4HIJAuEaT+/wrQAXuTpft92kouwe79y4z3bwJPa9b7W1FV
1RxpKbWexSKkCj0NWvaJVAMF428DqOdoNxNz76wz7eZZREpsiMHX+2Dc8V82xw/tTPpWTCqBwVbL
IyEx6AELDp1Bho6zYsu2Ba5snc2nQnCKx8M7mBKAztQX7ELg9kebCbgI5J08+mv/AF3HAcgfwn10
1jsbdFkwD87RXBTfCTI25vPYuCEVmwE/JU7CvlWXD2lOd/udB4Q+c0pbXGGbmA5KXEeG1ZCccN/y
iGzZUiX3CxvVdhtUi37Ler9P8cAgPSa3rIpvd73iz8+25mBfT1CDnUm9bR+w+T7LbPL8EgLVhVIR
iZuXULYkw2y7txq1Y8jqpdwWvTCPmIIvvCT3k962fRlW5JQVWV62fr2KJWxK/fSfhXA6yXp8pFf2
B763hO1QJNBpojVeTgDhEFaObwx9q2pIpXmKQTpBpkjqS675i/XtOtLMveFnp7X3LXPSxesfTCzS
Fxolm7QczjeT2Y+qDBSWb0W28BlPYTVtzH/bPOWqzi9Gs2T2TLx8+XRySBFN6CPEI9KTOM7wGBVH
ZLgw9bNI2MTZkfyTn5g+ls1yrQ+OclS4jgpfVvyUevIUCUOLGZpYRr+2PrtmKzdoX0vT+upgIK1z
PTlpYjVYBkOnMW+Hjbej7uu3C+CflPYqoGpXjpAu3gnZiinfDaCca7ifdoth4pG/VbkWzad63YhV
rrLOcUt/HELaFf1dErfsyVO4thK+azhbfwQauwE2cdPjafUTkUlYoQhRcIrYWOvWVDUaN7TZFFYi
G6Y4M3xdKvDSQ7QEILIm6TzluaYdBnGxmvsAhPyjmPn906CAC3NkQEtmDw6fdciPNlTPFM4QVwYa
DH4XF0IsNll43xWUsla6IMgng4rLcpxeYVUWr7x4KlvyWte7JloHWp6HK26M/pz5BR0lv/fASwLp
kN6339huKZutxiHWXvx+g0ZoVvnpOLG6AuBKd1CMtRDA0CWe7x3ghmqg48Dg7w5jCBv+GBTp8wRN
6XTUS5YuguH+h0Mu7NlS6yq4lEEIfCBE1ao41biqPdW8h3eD9KXOfW+JSZLezIenX2+B4vUtl9ob
xKJXmUXXaM7ZztRKi1nHPOE0EzRRk46b5L8MI/Wflv3X4lt8E42xuaEy8YEz1rdV1UT9szzEaMhG
lDiPH6nLlO7/jDYE9blPcz3zrY7PwxwApDwoSR7T+VHf3+e9cB9WArRrlsY/8+rSM6LM+NkEVTm3
oYoviqmhlff3r5qsuHYLjEqUHeXfvjciAONe+QP7jw4EYPHT4B4R55KgmQ5PdF1NFA9/4vZ0jIYa
nWWyVpNTwtLRq69ammhfDfvmeTdBMkOkANY7ULHB5SdaXrukCd1ko0uebsx12q1Ao+9jkLpfJVdG
gdDGlxhcwOGJGa2gcbB4SjPT3QZxcmSru/g/mVPnLjJ7+8ed6n2/Wvsaql8GNcPeuGNTSU9kIaFL
rq7TnjNGaF7QK7gOa+774Qa5MUnlFXaKY5fEoOJrfor59HOJyK5eS5m5FHwVa8mOhMFfRi9sHTjk
XV46dzhglaQjcjWx9EqQ6huqm4LyTFQp1Sxua21LeXJnwfrGtkZwU/0eNO0zsD+wNvFCQEhBFGLr
45H/RTsg4lUCKkwnQai9CJKRhCpVMC2Z6pPRawnjLDULyt8ectrJc+TNEoh5OVHka+0Pt2mrEiBD
vVuspIqloRB6JuCzL2Gm1te5meIQZtLyUEK5UJ5q62sn9j2DWTF+PU65W3enUh/jcL4lfp9rZ/Cc
f/BA9/puW7a2AwinhywXIAKoqnT5pJN+3zkGKjRDD+e0bnrwyggXWoeclDn5GdTG44hYPr+bzNHQ
xQsSr39MUJtD+WeXXGYRpHWWoWHW4t0PtZOIW1nrJ6oH9siaAVibO1MD2wiATvFgeYaJE1lg3KKi
21eTbR/c/yyuGVpRe1F/htt2ya4dHIYuvk0Fk4dSEPCK97MbczKv4d9muuyRpPRAvjQD4s5NpJ9D
bS0iyz7WZLPAAv1CDCZfRWXaUDfH7ksV1Ex/K6roalE36000eAmXVjj+1GFlYMVe3DpLviucix3z
h2GFRJkX9ldqHuJWGfdcRUiVeNxXpkxhgWVaiqDKfWhDOL7KAs/p/YX8yXVE3WUnQozsEaYnrSdV
msEpJVjujL1GHA/99A2Z//kwtswEpSdGrsM7GbBdWiZrKIAcYfdPJY8MFcsnUfswAJMVDZ66zQ3Z
Fr6J0uPqT+rMukR+8f8V8pjdpt7yNS7plSar5eEiLVL3wjicR3JW4AaqXNcHr4PRGamK+VosJyti
6hP/H/1fndkhylT5rbcJqupnKv5CKYI95CMw99GncRmsI2HOfSurnlvQXbtwfvnXmSRNFLQ3KtBA
HErg6gPbGp/CaWNxXmdudHp41WQWKV+XWpB8uOMmSToj7XL/Cj7MKYv2QUXKKzSr7ohYDc1EJQU/
Fb+ZHVi4cjgId9wvIH1HIQLYw8tKm1SHpySJd4E/6uP8B6POHTInv+3dEy+wSONv6/xtCgJMqIDK
7awm1NZ0S3W5BFjPSfwKeqCpevlZW3RHhbMjpMBPFHMspjjox8mS+fsrMgW6ujXoQgK8EFMaoHjn
mEH0IDQSFfF3knrAzhMXf7PyaRdhmMi+TpWcapcnztBqFyIi9NSHkPwVD5yWyGhN4XRk+ZspCCxm
CpubYTu4eAHmBjBGGzDT+U1oz/b7lKCE9/1fQxPRjVaXrsEJR58RoQj3yReHBj77huEhlyQjpo+G
ug0b9CsLbn7c78sWlLvQYlMdRR2kapRO/JfxxaIqitVB/TGy5d81FxQIDcND0V3ooGFRi+A3TaOu
zYYsm1t6pgnuF/k3hvcLvpYYJb7K+74q4MDlh7yrRM9Cb9UjBU+DkWG1DL6zZvuauuGMNfpBdE9h
weg/VtehivzxW/s6STQ01NMSTOQMYE/RnMz1u1qk5YaUnuwuwvgco7DCcwcOZWWOeVYOOLcOIfU6
WYrG8rhlkzSwOp1DOm6mm8+wvvTHvH9Ci5XpZXJiOMBlByr20/UfRIscTBIlxgPd8khPyKaXmUdc
GgPUsVCqvvXvElpAnz/YKDTM4jWDjDN7Wsqx6cO/N4PoBNQnfTHax9gStp4iBqiNRwM7MyPmAsRh
nNsLNV1hX0DsrNo0bb72UQ+i/RnypnKNIhAgppuh2FeCDfds94tuLj9tX8aA+PvX+GsTnTIEaoPG
dwjLYnuJ8pAdVpF2q6R2fLDaV+tP+sa6r3TxfiqFZmDyWad+MU+f09aXWbbUBnVk4VUyTLnnZjFF
emCUh48NtiXun2BHJXvLxnfvMIf6C/LN9VhytHWX3U2n/VuXU8nylNKZf3/rSGpoJMsox20SOcjU
fPQbPntcI2kCWn7M3kGSdYCFOOi1Sr5VpNEdqGhNwBAKJQMNucbDpvG1LOIpoAWb8XcQ5VqDjoO4
gQBNLMZutinLl9JQFRe1k/x0PQNvrVVw9iGhgZfW10QBoxaDuvCJlyFyIYC5n1M6Ql12BMIvVRnP
Uq7onJSaEJWbVFP1E8TADZ4q7t8eplhbA1HL6vEaaL7tExOJ8oBtWYMBx8H4g+cNke2XRQb9QOhc
4H8UsFlKaC9jdjhFlFXsRIwEFx2KfqXsGYceI3OCtNQpqWugI91wxBMP8+3MnD4D1CM231pQ7zll
E22iMTYb6zu4fT1n9gfj89gkT8Iw38CCPThH2Z3s+VQYHhi3YCZP6+OOqxnNeCvuM5l/tDTBUd04
g0ZQf88yFUAXJ+77ZFV70xikLtMQs3MKzd9ur7z46uEF9hMwSwFe4IWCBBzRlXrtfNSOsNu2PKlQ
81R6tpMq17wu7jat4fPWA6qttepxpP1oWmUSQXBPa594MMI/CPNiUeaQ6QQbUiRwHAQczSK2Gd5E
AwVXTKjNAfTfnIWhoY4aDkDH5gfPp8yCWCSqSQXZfCt8Xiz05mpovPhY1GRv6f76ttByeLPcqzyU
eCaq6vrCz7WTNxsF5f2zxqQC4yz9R5tMLVKyTMmf3VM+WL7lgr9KZDA1hiMzQ2GqGFLL6u5Q+oRc
XOWtPX8ocxgk5VeKPvJj9M6s0Z9oIEXi/p9aHJ4YbVp8WLekcbTWMLhmaoR2Rtk1jNHnMvNltVWO
fMu9knA6VvZvW1xYqN4JXmISLB1plw3e9oaeSQiNZK48RPX70l7CQfpfx9ujnnEkSHRPtplhQ/kP
C7lpGCXm5fYeetDB3gj3UKgTtuK0qGNTcrDlDqwRGy54Q4Y3RZqU+gzg3zP93phAHGqWnnYF29p2
5klygC2moThRTJpS1zVw2qe1XY7r5lMMq3mghkxA53WpYOSsCYUUZV2EP5yhA7somz/xYv4vs2cL
CphJlCrJb/q/zsRz5TBAtF4/5IqeNgMuHJMmDQ/KX/iv1cBDq8bQLtATneqxYErgtk1gokj/C4EU
vGkk+W4MrL3vZlA698jOb98JF7KqH7qY1rt7QRzet4ctLrsRmLOYm4TDMYXjJzz4M8ZO30yGN1Hl
RAn72+czJBj93XXaj9ZQFYGaLDkZ9FpJ0jdYylAITLUo4exl7v9CapcFqlo2Zg6mc//7lWbRtvFj
9LROMM/ln68GGfJzFD+B6i4oc2yESPlafRv506/RdViHUTkaRiWSe6mHHh/MdtGBl686yvFPf2L/
/bF10IFXlTfUWFbRp5FFCrJAsWYs+NddszxvEvLuaSkoHacQWjBP4vUsu1gIKE8viXUH6McQ3/4T
zR1NHWN1lOpGUrPCacXY8mAWGhsl8bBS6D70lLQYfiDbqgV+/WZYbnEo6CKUhj1vcJMa9jG/vkDy
G6RrWfSTTo8SPsWOlR3vU71T37bwUt7inP4A04cmATF/6adyuLnaTD7LDg1w7tdXPKYz6sjIFeCk
cOh0K+vimU9IWUTxLgx0OdOv2GvJwo0F6CEvwsHWQkwW0Ntszmg3R9SovpytzUjnJbrw9OrUlPbn
JLVSi8uUeL3HRMPKuNEJA0jqzIXk+NlPO+6Av5Ot+EeqqUfmZsob6gW2BtmR2bXEawQyQTb/QVTb
3ZIU6YqrUuLnILDORb13aVVd/LyyYXbM7Vm0tHOoxyt/uayCu2Ljbhrt6eiMI0xjbZBkgz4FMkM6
/gN8O8UUnrnBBnenBNN4zQHQfa+IyO/S0oLrjjRoEBSAIS6nOad8ts0sOzQo7bhRicCzY5U3gqc3
fw5rFZQaDLunWWz+BC7RiQfWpMQNiwEobk/Ok/NWYVUa1CumQAll1HRjaWF9IgjpE1b6X9aQBLl6
Uoq20riIoZf7DfN+338f2z/pZaHtvDVTDFUJWZaUHa088BJQK3G5a0EsJjhCq4NTDKzG1D2t0qmJ
EiKlb66zMq6lwTOVEximDrBlveL0R3F7/57WpR3kCxsfLoRQAod5UTpBFH+CGz1pahAKMcypyxc6
zKhkvMEokfy6Yt2S1CfwsQNq5Bb8tyPy3+nOJbDmxfzcCY/45b1lLBXflSgUtCifIOZKBbW2Pxes
5vKd7Xm5Fk3KaQvWZEJnd6KWeZDTTWYFjxOiwhWYOMHknSsHVs0rkcbq21HiXncnc0gNHoujwQC5
7MedwhdnumEwv5RtYFPP8HkQz/iT+e7ITkC0o0LjxIl6zMdVgPEUTeH4CXxiouOe8c+xVimsPZ72
GklgC5fdS3M4m1NJ/9iAIZDrUjYjHxw7sZT+e10eLlMHK4ADi6DgrU7CkU7rnrzJimiPV7IhUxxo
b9yEO40QJRmRIZl/UIQEmIClapz26fYNfSs1A7rVdUkUQFy7rc+h6H+1pfNmT5tzHpOtL+oGko6/
jHuA1KNxJSggDjg/laD/brGCxoVdhNzD3fNvEdzbEzHE0yDnrla0AYoBWiZnLPTghSNK1XfgjZCP
85nvLcNcYjdMGtOf1urQCeV+funuKzlI/hpTLhFhHR+VW3b1Bd6drPHK3eDPPitFbotDFd6120ZV
eN1yfg0NySWGRn/qR0Kdp9EJ5oDj2sBPzgziJm/A8l5W1/ONwIEiwxkHoAlb1C69cDGAAQQI/JUL
6179pa1DXuwdoORUnqWuCXO6Z5F2vo0v//cqoSrE942dLcQ9dqd/CKWeSjUvWUY7D1Poy3ffia/w
wU8d3kf84b3oKFtFEQR5+5XwSz07cb+O8ANql2F+ynJBBUNBGSaoO/N5RoXcpMINUVWMWNz/U2Ns
31tCssOAAqZStfmWMUpjF4gf/vtUDYZv1ZAlPVuZcZ4WUE0CDMIVibgnSII8X4o22MTLeQm57DX3
mtGK6N3QVlRwDhcdaRwz2lEfY7dTM3Sdm00yvsQaE1EKlcNiRuYUuPuYI0zZKvmvf7Xo9BXf+fyw
6hOGBPEFOHg7O9oIgiSM7QIqKcvzazciXVFcLNgqpqrGUL3UOdLu5ilwaC3DrjXcMBaFBeJtWhhI
wXxbiybAuHv/Ci3DsN8OWTZ2ehD3h4bKn6Uxaz8FjuaQZiO4+U7LWc0AmMkeQ6Kf4CT5dtMekrzX
jUDGcutfp6Ftr9JWU3E0HAoIb7uA69qCNAuqQ+QAko+3YWp6ng4DmKusc2dAjjeg8+Qr/Yp11a1n
/fig5CgwptxxvDdkEBTzno0rKLE2S1RiRbO21GgmHMrALuuSRJ/BfSUNMNcFPHnQ2sVTMnZ5CLvZ
hjm0B2pPhhu17+Nnl0nWk0YUD7ALEyP35ZeMIwFEtcU/xSgG9amVEaTj08A6GeSDpi8h9BJDIrWA
XVTF2YJEH/BusRjLsRSqZmma0aompqXAPfMcyGWP36EKbOAZZjL0FoinY20rLWvN8l0R1T8sDBhe
KICylx21o25FLByHemtPBm478wxlQZmajW8xP1vMZjia/QnUuPcy5ZcWAT7UPZQKi9halwZt6Da7
f0iejWRrS8UCFOYFLwimHE+EjVPTXiTQbWAyDPOOMqRRkLZjqNQA1TXJ1XE4H1Jx/1OBFebTN2zL
NrkdAMy+f0zZhmlNkEOOadBfMKo7uBpxI1yUhth14yZ1mnVoMZG7DgxPJ4GgUPoj3cal17jVyyzi
TKKPD9vRkM9eJQ7PRHreESJurircitgQDWYvjpAVSQZMPkMMXPH2CrdBRXKJPvChcfQ4TdKzJ/vQ
NXA8sbQwriEyKLOzK7QZ+PESVQwVOS5Iz7PAc4ZcoCpYDjSRmWL5U+8cJa7dXg/Omu7O1EzHmwyz
dZ1XXv8Z76ZQ9OturlF02HvXi8mODBlZqu5LmcbX1gw3//523mVKJUPf7+Je5IsZxdfdJPNPYTxS
tzfZ96fBYp0K0qvsX/EuycTEqWRGX5DtuJex7xGV0JaMcUFFrjlaDvu3OCBTGpmQNRoVQqrt0yxz
AsFQ9ZnZ3EuGQwQV25HqyqAcSUboBoIg2q3w56SYztfXa7Auf8mHmyl+tX9A29inAB2OoiMOi9MW
iXU2PT4qqEOu0kGfKurzM1wCoaT4M0+S8IwLPKG3JCbSOKB6Va2silKlJY0rqfd2FQq/nUN4ZbUa
Gy5gL1PWFXg0HWfPbNNln99niS64XSqZGMEwxzU2AO4iCrFZ4yg1XADif2XpXp/OplBJ5HIJh4TR
4GCnrSNWjk3+qPgut1QQYhi4lTHdKv4kiJkmoOWjwbTLeI84dEuixCBZtoVUFJEqCa6+H9bkFGAh
fVuh7aedM5gssqWOM017hxBwNsRQI0/i9aF7/WwWE/mH2wuJ1b+0stXA9a1AFQ26yz2HxnuaFKin
v4Jcpa/hW/MGp1iF8GE0qBzXjyBpjksda8DrZhZXWBAjBkVsPPNtPrnG022o3C/P5dD3lONo/XQv
UfTySjx1xO9LrIFMFjtF2dHyTatf/W8ww2wxesgj14y7ooDyHi6b7fKco5cG1/Ow75m1Q3pklViJ
dsYM4jYSpGPtROsIonHYY0Au5gCoTSAXT3OmpCzJSHHrZPbWGwWDSwXTaonzBbdAmgUeC/OhEA1t
nAzkRs2uAw9p/m8SUL3mfKFHMILseI2LGUwsJa9qDtKcc70v3XUAqIFEinf5mwnargDfhli2Ugzx
RnZ4/ONNy8EHz9CMGTlNkC6B4QWSDgE6Qej+dn82UTbuFz9ABqPPATUgLW2JdaJyovi0S2EFtVaj
JBO1qFnz9z8rs9PjJyRggWG+zChZan308e3zc+i468FNXpuT2KXVqigBYEYqH2+TQad4QPdGsung
ZZfMjDbEKZ6IR9LXxn3GWPwE6B+4VziTtvM5pP31xWTU8dptVEK9GzuYq8mBvt8T92WVGcFKPUKs
6Wo1YkCD01b7vJK9fhIGIWHtqJNRw8bcLZduKOScKykMbV/2RcpbQlLPvSUlrBuAPFsp1xLo88RA
dcr/43wrHHumlwwZ/rQkES+2EKwLMvZ1JdWIFnQ4KVTHDSUNkw3m/uq4li6XHvQzUd6jgCDC7Xvy
bIBeaKXIrafABZIDN3mx9n5+5mwutv7qxakDpQKrYRt21bNjOinOHD45ioKgII7CZoDhae9UlkJL
eIdx5a9d54sjf9b/5rs6dBChbZjmUIw9G4qIXTePTYjVQFjnF1mtmAbGgHJ0T4CT6x9f2giKhx56
9XwRch+arb5YHR8anoHqB8/Fxlr/b4+jaHDivqVTekmFp6pCi3QIn5ak3MEaDEQELKHki0+gfVqa
/Un7tQOMZv/iMFklMldevx2uwonHdSMAIw95CKEZyIAE2LBQlfn1rNCS8Q691PuaENyOlkT5RiOE
UHQwiRkKASJo+UKR29oQ1K4qMBiEgs/1Rcj4j1QP2Dke1J51bFHAWkEuiDIjpDxGKYuW69kYioGl
yBHCMm5VanRurJrX1Iuq+mH3DpLp0M8gvKl1NMnygdMObOffeiBeRq8PqiwCOWBo9+oHBKUIfsGC
2lr0z/Re6xGGSPHV93ugdA3P0a4qQB4GdlDV0m2B9O/J89NfsJYs0JMm0K7AxD+7+fvwTBocrXly
neVHeCRkpOcQ2uBomr1QJNgZLlfwv+2tFkxwlifzz75UUC2YTW9Rh1kdCGf9M4QImG4jJMnOB9S8
uvJJ/zZgOInU8Cw0ESbkJ5pJI2GubQi3BJfBFjRex5eUFw40Pj8YIqoXa03IV4ap9i+OPYMvjwxJ
01oqV1Tse9OMBf+SsCBfBC/ElKu8iKVcpmb5V7h7mM4OTIa0AwrSWwJge/uqn9quYdGYvJHQUEw/
bQ/yHl9Zx5ECQlMud00FyDcRHBTHHvTE1S7lnSFdcKSN+aOY/rXufEBTv/Z+3DsCa1gFjsg8r7zj
sjxGLRioXsmAb+b2cr46VKsZ0b6i24X33Peqv1EmwVoLg08v6mBXp4/u/1oQ2BQ62Y9DNyB/LZMu
53p6Fyp5CAnGrilgHIhSr/Jxfmqyoss9QAw1ox5ZWCbv+UXjvl2QLyiCnM97aV9oLduWeLsKK5FL
R1wJJCdkpYAoPLds7wNDj7fpTZMkh1I2GT+Lc5PgsMTsPXDuH8ZHp/g3fy2s0vdRjtdww38Vd9vj
TeRhW2lXr4SrcRdSKVXPDE9dAeEYnG2QFXi7wjQqQSga6V1KsIpYBjrQf1KGUl7i9aRCKNSjYbmm
B9schFtO2PEAfowr6K04Aey9+BkI2qHVHS9Z8NQKxqyrDHosFCeuJuSujFQSnd7tbi1297AMSUFw
rWyiyYilzGu6E/29t6tAWvkmMc2BbAuZgqXyWaHe/MxnBwX+JOgbKU66CqxQjy2poDfuDrwNeyx3
oHrw0+PdlbCl/Hux0jUvX2jfBpkYSX2lZKMQEqs4WaSOtDHwQcKJcQllGK4TGeRCH0thWTLImMCS
dJ7WPVNZokuyfZ4FlUA0KsuyxL+625jeZEka56gs+rE4kfU59ZOgweVQlGuiS/Ig9fKPHxZYaVoz
Yjoh/aatiiarqlm3oBSDsYeiUEc/vJA5LPsiqnVw5alUCiKFuPqzGZw/FqgzMpOIjo5bZNPLD4bY
ar+Cyovbpjyh/Zsz90VhIrV/81EZaevnC7lOfHp56Rq6Py15hMUqBtIeCohqj0KEtIKqYnfslPih
AQ9hqF+FLdeVxUUSxIpLNsL8WiEQKkzh+TTGQ+ut/05STRlCLJRPdrzLy3Ot7iybtbmqLnkZBUYv
2JOLq50ade7T3OhBVEtjLvZgnITYHnUatcPS2ZKPP3SYz0A8PGKx9vd6+jF8nlTIf8oynpPlyaHe
KSr7ptJ/A4g34XmXLAWkOQ4lucMebOs8E33T3SIvz2FIt3rfJCITHijfCT4j3SihYT2oeRuhVYbw
7hugf5tIPHDz0m4yeir/Ul22GbtYyfirSLsb/SgAdCfczYCgUyEVacuI467st7+70hHCAOyUmseI
uhQJebPg5yy3cnu6LAcQyrf/94efMfHfLaXPIaUd4feJTrnIhfaspLEvt4IN8Yh53n0QZm2YJldS
mU/hgJOC/ue0G14mHW+3/R9FbQdNNXKPH7UM16DpzRh6ohu99ls/pNacnX+XPfO3vYxsIC5GwD9w
LuJ8KPaIJcQPv6fpPBA7L+eToTl3b0ugRczVrPpBPi4qSGfyc/ZvY6D8tS5DzLhWkQLpH3dYiKcr
AgsnvCt46fWAH1uJxDoCmvaWrGF3JPewA2BbsLXY+rEMwR9VBM6SmuEpKuDpXS4Ka+2wyAhQthEQ
10qHeLDOeJvc1InBTnoNm+rD5sRe7uujp0wzymnvXg97KMkehAhvYFOqhAMavvlwyAEAxWOJWyGV
yT6TyBAW8nUj+UiuWWjGHPWemAySFIwZbnasfNFw+muwfHggt4ljzzQljrro2Ql0TJ00WW8HKphi
gYo/JPqAH6rkFg3oUDYufUI174M//Piv4fJlyA5VGY+Y6ql3aG9pI9Cs+MYuWcX92OmxhrMGpgGY
GCqreaDtJpyLoGmyPp3kSTJe2mRlsmcK6o/D7+W9cO0d8VpU+F45mRJkGw3f1cnhqGCsSNPpaSGt
itz+UMV/YChCPYrClDkuhgWZKT+vgzsCXmXUBVPgbMuqQEkXcut+WDyZKQQWnaVX48I/0qArsE52
nY/DM47IWxqh7sgo3/q73X2QKhaHbLu7aJwSq0eFKirjrGRXPKjDPrQ56JVsKqYn9XW9m3wCLMpw
6XD1XI0icu5gLeV0YmjDSf4Z+GqQSIhNeS4enmYrNwIpcFyJUOrtRxcGbNyyf4zPtwsl/1cnbBg2
bv1vL8ZyKt0Whx7yliOXAjaFe5JABEEHiwop9i4vGrzjrCQ1uKqXDmPSF2e8cF7FJ/ebGjERKAfE
7clwRFq2MzjWlIewFmyZ861/cZm6rRi2RmBO49B11ab84mA5QQ9S35usFHi/Qy2UVu/74OZio0mB
8zjx83oDok+gl3D+LMMqzy4R/QvfRdCKTz8JjESZVC9/SPvvzl4jLyy984QWylVz0fJOcafrwbD9
rX8IE7AL91uRxDIfsgK96ZthLOYqATxvKVta1jZs0/39lpuLqemwBsm0Kzj8W1qznVUtIX9WQJJw
kqnSlcah76OZnbbIBUGmPh6RTqYr+hDywrxXm+HP0MEaH+3y/3ZjuijIKewLSb1eycP5sfwKJa3r
boGcL2UUKQnkkiU8yfiwzU7wc5ny6MNWx6yij4sx1BLXI7vrZgm/XTf15WvDLQM0kQy9W/oyzHpT
t2C3/ytoMoIZxhvI6JGi4qtTCdyYEMIpwqCakAO0Lp8my6T+urKEgNFPQ8lxCetpjUwdmCyuuAVt
OJbqfLrRD3S9OV/x3eAqNlbUix7y1Joec2ddCKKjq5eCypcILZOCOZdLUX2PzEUBNEvp+bUJk3bk
v9IiXrLrEIIwsZ7E4Rssf2HafFrwKpYbQ7jdThHeLFlNMasB0+cGVFofw2hb6oSvGGyT0iK4Fcvj
KP30RMDQueBW4tSSRLLjlhWcnMcvXQ8GKRMTL2XH/uGq2vGyrfkwlcTmjAWliEznYj8iK4zflkdy
bcx889JkZozeTAe9Xw/Wxpj8TwThaNePQRqTPGU2PGqFFnGbTdkXJwotEwFGdzUtIrqvtr+z7Vlb
8Yv4kggbfzIyFKw+AdRD+QjzTNB4USMHgMrRfOfVhGABo7gTOK23t2xIIkd5efHK7EeXjNCThFj8
gs2nyYFoZ1y+zqhXpWZVe+YakcYzN2YneWUDzTWtOCPsLYlZQEYw+Mf6aVGA8aRChoSLdQQi+FDM
gGbtSHlq4y8IeaLrjnW/7TqUiaUwTZBnEJpwBkzN5wROltdfeRBPlH4myGinM95WFc47y8jAjWn5
3JIzo7i7HT/RNS2vvBFfT9i8z5q7X2ItaabQjbYMHu0zVKZdZ6Rf36PsV3b1GLo9yl1V1mjg3OPV
MqTDSwbpC+QUVXl6vNCpCPCmOgOK/W4TGlc/T8WtY24EObrjIjFTH8/P7P6k1j+jQ4lZr8OPGp4w
wucr0KacOmz2skN0VXbEt5P/oO3ht6B3UCmdpNEJiDaht4o6ra5274f0awWwnK8yVGtRyhrB9SlL
2VPMTgfzGmF0BrslZntwKVi18r17xOLAiLox1/Z7f1+npZRMeEEYK5jVtRTmR7HzM+PQdXwd+Hq+
XOpPEnS+bNXuP7cck9MnKaVmf1TWuEfnW117a4J8TtUkzjqXvy5eRS5wjHhuhoG2CtYdNj5xDIjt
GaPjfVQwI7K3OG01f1A4C0Xe3K/rOtXGgSSnF+SkWZNHu+q+TDvajgqoza/vcpahN81l6ypx82iB
6J4aUqbckm8K4AwfQV8qN1cS+StiLRgnn4nlWqz2YveLX9afe4e2TeOV/kBRpW+plo9XosNX0Bd6
kREfsz/gLHExckEx2rN+6FAbo//9xiEROtHmMgnREDS0T6NAqOzQCr3eYxo+v7NWjKdD9BVx1rFQ
kM35xPkhtzwwGnRhx8f6+E901EQ80APHcOnlimKgGehat1XYP1EcNIaTxQsmtqpOk7Vwlj0b8lMk
2cBRpOGdAwK+EmKDFakQTVdbZ1O3BFBoKYVgVwh4/8vTXBdSbEPgiOdMOCj45/D+qPzIA0+l8G54
W4fqtYf4OG57qMWwxuAyMuVMorLYxtaBNxiVn93Ck06zSkKaRoaKmFPY4RyN+3en7tQqq3D41+jk
m7oBlT+w0/0EVrH9uskICZQ59dMac91VmK7VXv2y4d2LhFQqpFKhRfFjMGcaeDehWnuaytrjvCwe
sOgMIq6YS4guhuQ826q/Z6l4YRr4Z/n7o8dDtua1B1tlAlCRR0bshS/JIpdrQ8oCQ+oR1AHrnv2a
nQrHB8NuvfGdBJuovFqeZb1bUKnZ9ZSW3t/zBKZ9wFmF95Ie+VzNyYWJch7lmxefMDmfne/SSsDL
GnU/q+/7GMcEbXZ+gdmjh4tb8VGGjEtz2fUKHMsM6KyJrb2zP1F5RGrRDDeE38EPFuYxPkHe4giD
csWxGNc3YFj5d3iDWCtv5XJJe/xJ5NG4ygrSn9p8ulkfDjYQFi1zjm6J2d8S+1+ICOb+KX3JZP/i
VANk/7N+D4izi4OxtTyftiwmjC1rMy3HL3eTLrocWrN8CJ+hEI1K1zrAVr+57zMg34GSiEH98aqL
Vd8amyxAoG1bxIkWuD9n4El5NokBtZHan0ONX6o/54nwlA39vfEuogvsbuXR6aZFRg3tas2tvCJb
E5UR19u22m+iq6TjFDF0dT649jhMRs8pEZRiPhw3vXuEd+KXE+6tONNUiBbiVYOOgfxxxjivCL3W
wMo3yJvnc5YcLQqDbZP8cWXz5x6JhHP2tFzQXoNqoXBP60nM+nBpPuEwNOjy3OO8GWaSiYBaLSCh
gnStbeGaYhxPo0kjhFDusAC/ps6TphxKOiQcCXupwhHByVEMzjrbIPDrR9Iyn/9x/FA/L/pJUTWM
VQ7krHk2Fr8MVP22pvIaRYNyFmA3ZyH+CWfWt1lCC++m3d8JYEJoG2J+JGmf+zlLRSvGMSh3CYND
2q8Hlrg/bTDtX+4x9TnF6He6QneDfcjlFUTjzoO1JSqFBcCAWCMQgiv3NqSf/vYnv9BYReEiU4QQ
3V0/qvbeC3o2gzIm8AveMz7hblUlsijAI2MOfowz/KkJRNslbhaDu2+k4hqjzErZw25debt5WKKR
elwi/2W6qT1AcIq9CLP4YfgifD3d6mfWH5wff305izG9oacOWX/9zZusxBj177cosod9Tg5eDlmx
EotTh5vEF3Y8CF9Yyu2ATCPfh8rGcfrhRVl5o5WiD5lmtyZKjwDRorslBultJbkYS5OyoenZ8pTN
tk9oAdatmYSvbsHiuFFA0mfq6TEJW1NlMiNyNE3h+gg9+sHWdeehKO01lJKJSaihnpbkJ55ADdVM
pYL8foHafwgezOAY/XZLhLOp3mDUDGTzFdO7ft57aikCqedoQVQqkdn90RUoPYRnQxxqtLEIaO5K
mOOkrTtYxDCWGiuxod32DQLuVl+wxcJW7qrOw0JtXBwLUEfvvSptGivYcjjpNXlPPvXMPFKCQ58m
eB4GWFbsvU+89g26mUZ4IJlpy8PPpEzbx2S2YYUhZZLM/032HAxzeyZ337x1MatTzU8iLTRAkptL
IWAhOkRq2gAYJBoP8r0gGHKZzfB/fc3fIHzi8QBsgwZye4id2zM6nznxN85PoAVOH7Gzm87tW2dZ
AU6JZDJ0YOuohvaa1d7d5ex2uEKDnAm//1/9yHvu4c3MBZByQNGX0Yu04kZt50ucJK69V3r2PnvL
2GnK1XynVk9LqGwlMfUnVUk14WAj96ZiAnk4qktc7VTd+Eh0y5TxZQKMCb434LweehHakESP66Mm
z0fAhwKT46+vkAa0RtHCyVrJmFi6S6+XQn7xbB1q6uW1g1wGJMphz4ieL48RThZAiV2MLjXRDexI
D5ottGPQgyXKOE+i7w5RklproP8dNUIFycPUKymgHHRYDMfb0rtAYm1kIONt+AY451krujMD+E/y
HDotTvRWgmsY05nsM3FGriHlOh6hpICqdUYs2OwLUu5zBM2HeojePgvmdtJjUURFFZr1wBjDx0fm
HCXK9UC+1ryr0U/qLzsWmZieduKpCpwbrgCH5OmnGTUL1U+I54kq3waZX8sZJMNlxR7jn7pLhMfa
L2HxEudAGWHPhLIprcSlPvL/vrkDZYmGLNyZtD89Y297GYE56EJSvFIAFMozf55Ie+G0Uixyr7sR
26B//OxyTaKzgR4IvWmdxtJL3R+z/Mm6qUyEDGcSqRzs6qOXjUZHa7YSCDUZ9jCapY7SROuffySD
aKyNz5kfRPmA9SxE/eDQgq+HBAbjDyY6/VIrurMN2Umz0xYcuHEPqKJOJlThbN4mXnaadE/sBZtP
F1iGN2VuJPHL2BzrjOVbk5YtyEgFc4ec3Us4oTY09080ryTSTaD76mMbmNUKPprKWxiF8SiluNoX
OZf/jcuiIy0aTiCjDWwcbkLJCxtDLqSSn7Cat3EAnmlpgWrxhYfP0wdyVY2jKIEdW+NMT4ks4B2Y
A3KVAK1gVq66jR1X8bVM2h12CH94ExdJvfBmOaid2bsj4i/dwBVLoPIq7H8/X6qLEA6f4sZjuI0u
FyyNZ6QtFngSYiUP1SG6sKZd5EvVTsEg9/p8uXaNYgJfe/ObTdTOozuhnk1Lq3AhIdk83FdDLN66
GCnnbuG1PjP3J1n/xuHHjxtZ1fjH4s2syKK1sDpgZSEokEBuLbbDu2ULb9jIaxPr2QZLl40NFTCd
CdXnkdWB0C9sKEWl3OuktJO5hH/QKsdAUUXXQyfpt+lG7IER67FMRTr+7+MveAn80LW1NI5kcmLP
GFaNXXEOpulVO+mQAfLZRWT0agmrpC/HWTE4R507RIm4pH6TTwD2UZWpmzQvm8E/XQmrqmOLL8H7
DEvrjOZECMv+yMK+1xrGwDeMwAbJ+n8Y5c7xOEias/6/nZsRZtV8aKIk9KG/GB3IMchrxfSEeJ4u
o4T5wjZFqccJdJtgI48TP+XnxczWRKxXDxR/RDADeD9HwaM3qPPAdlbMmG201pGSy5RFyPY6Jcsx
RNsj70XNcs5DQ2OWl+AT5N6laI0zJjCxNvgl49qtUKGtoBcjBJo0yMkwH8XEqA78zjNEl7bNnZfQ
yOnVZ7M4qu1/YkGvPbcwG/PyC2MhAWzGtLZwvSDOV1RVdwVLa+N43d6+ZMRoHbf5PNW49rjATCaA
Q9boz7h3k+OcLlmmTY3eN3uDk9MjfaQs8sA0cZQkOIg2P48moXw57D4ME6IYxVlNwAnBPo3P8bIK
MDceUM5Z77bFNYh1oEonXy8hwcsiVc7b8Vklll4Px4TJ942Slg46sjj96x/0DggKGk8MUnBVEGw7
gv/sTT7TSkFgh+q8hz+q/5SZ+IbvpWEVJaN3QN8YAUF7Y4fvV1zFVXOLJxZMko9QVkfQMv7zqAyU
pA+Mb5KhakNj1Bpiri9lbbR82wG2LvV9xXpUDyf80XdW3DMAbony72X938Ng/wb6X12GQ4T56+XD
QCsbs7MV5isxu66M47li9w39Xo9J1YIoX6amb90xLkMqWYi1IVJBqAv+w9awECQAVBnx/s9STgFP
2LKgAtpm3vyQEvuIW4TvJSmsO7IY3C8DsqWaSL+6ila9+OL+UMZLGo5PS9rgZB3HxJs+gwarcuUF
ENixDIWWR1W7BXmKopGmXVm0HxRngSL2S55EMAO1ORcgER7hzpFgXsHTmu5VFzadXE/ukXR92Jdc
EB91qyXckWzKdcz5mkd7j4ey3FDQvJ0FfWQz+0FXA96t+OFUlWLLruCt10RXLWp3gXDA2LBo9i92
DfowcdEYNmuOEeaWRjUTlw57xrVNDjPIbXpq9gMTOZ249LvwznhAInWwQy9CZAUqPrYFMXzW7XJr
InsSIHaJC/jojURrNp3P+hnxUp2Q1CxUyMjvhNW+2j+X9/vCShzQvXFNpQ2pgcIEBhImOoG50Non
PT7Xh7vcKENn7ADO07NE4y3Fsa9l/IeTCCm3v85A0C7o4JeUfhM28IOsJm/yNFtVVMOrSyaT+9be
V54eJ2/PL1C2yAmdiksGv9CoTgbIu6ps/BpfRLyjiRswOSgwlr39KSDgkN88+5bD7ROsRfVAOFQc
HsVwR/Z9eIPsq8HXe0hBhHPE/5LDWaPwXRDwyT24D1T9ML8PrpO6iCd7ZXYpcg1Eno8fQAzUep03
83YpoMndp5baVe+P6VmAsM9u6q0pUVFQ9gIXrt0dLcG97BR2p5WxqEg937IGr9xNKR/oPwBuaAqY
PLJ1NNNaOXs8U4MA/JlB9BLqIGkX4ZW+uV26cEPmzYR5ZJ70BQFK7liFWvhCUaZ+R5DVT1E5qk+O
IVBt5kUB9NV/MGAh2TypEMETyk/F2UDml8pDStbgAZDG/JxCpO1xfvjjTZwY8h4cmqwL04jlTYAE
JjRHIM5hGTQs+R23Evux4uxHS8j22ERCILHOuaCRDzoxnllpYTnj+3WlnIdqOPq9IrurFenAhx++
g6zrUBVsAmfChJEmeIVDnpg8AEwr1HTK0klqNkHDwjjRqg/f/WMiD74O8KYBGueWhGywHJOqrZlc
wM2SoP5tj6WwgT1f68j5YAtln8AnhJVLJTum5/uhAczMjWCN01KF2++efI75wkLqbahqTue2s/19
6vSsETA77UJW7obEUA0fSnZti78QTg/fRTTqWkF+ydY4nwwi6ezQmVlfceXD9DdPOABlBz6buVWV
2dmCmxrPajrCBR1ayWqe5rb3mZsE6JViNgyhs+2PllD6zidwXUBv9+A5AXmtUJ01rvHSdRKJ3yxk
DbI+9ZstZMnjwptTicnJdjsepa1RsGBuAwjwJqH07i1YEECLnQ5RkiphD29k/Y2vNuKmAx8UCTT2
Ch6VB6Ur2kv/sQda5QSY+0d/rJdKHhIFdD6pqvqAPGCQ94v+0TFYfe+YSB3S7fTJFveuett5WV2C
z9UOVttTsxeFXOSsQlrfjDUFxQ4mOBDDTKLvBuCJVvUqzjGmXyF/XCj2X1WbQy6Qb1ffQWI2AMKV
BJwD3qZmNLuvMQfstK8pJhMKOVc0EWXfBqH//BQrncKJzeCpbWIgh3VhjZ/AKgpo23q+OKzP0G0z
DVVJg4p6cca+7qPrmjaoEN3tVJjenPF5eMwSe4CXWlgvhSwRabrLabAd1x0jMw1aR4dmF/Fz5KiT
e1o+0DhBE2wt9XZUAIf2aTarUVZ8weEsRsOvCbt0cFrGnA81dbecEle7HoWuq+J3s9la+ZdQHdEj
Kwnfa8wwIzc6CStWtF4tzXzc/CQYYzRbnBFhu0XqXtvCU966VhNwFqFvqskWcaWT+H+d0x/QS6WR
EDkdb5qP4PXxlOa6da0VTT2DUAhxSZCbZT9vhNdIlpPokdYy3sxmEUq9HX8YlzF7/N6Zl/ySDWVn
W/inf9RiP+4LJIxXIxQIQHFPtqUUhAk3CZhCU8U6r7nXHSEQD1QfSlUs2DzXUqc5Efcu84g2k3KV
/2SPNBbPEODdFisGs0gMrzPHO+XmEW9qSvC9RRXnjs6Ehg6FsAAIv3XqnhSeD9LMQXuNtr4plhAA
YkUrish5aPfNBMlEyUl4a+hsDmCyzHM1ehb4umq1bFbg39ag2XkGasmt2ge6xboApj1OH8m17uOQ
c9DX3xH6Pk2qf3qq2IhkPbjJ3T789WUbIbboXfGcYCr47gA1FDOPnzO0D/DdWOTi71JQw5PCakPX
Elnzkgev4jNDKLLyy17bGmkjglQpGzJMXrocFvY4ZndR08FbICOizb1WxvNLUlR7VKlbf7eKmusS
Dqh0t6fcB+ORAQv0xLZaCeCRZYtkGqJVz7AY2eSe4a4OkbIJetfCfVSb6VCVDibfnphTQyYcoe8T
5WCi2HSUSoG36w32gWgK60wBgsH2vDcsHB9q4pDWaTjJNF1itZ0qCC6aHDfAV84/KWXJPlXzHwRA
PVX+W3WgdqgWVnO6RBB8/08IVQJkW7RDDJbKClEvuIh8TEWyrKi1p5vntbkZPgJYjo5rbHszrp2w
O5JgAg9bldNH6hhwP7ajL+ptrO43dUYZlktP9/HLGdQHfGsdnzgC6vcpthnwWgb3OhnL3fdm4E2W
wO2nnIoJbN8T/g8vJKj0AvPjrLbgoboMto2bX4waGmEY0/qA1yF7qedKh8JbkskFRcydjvotGF8v
E9t2hnQ9OEJoVTYrHNVBqNmrdfVX3RKbPMQHD4Qqlc8T9VJZdGMuVWi4fe030EzJPtajv3ulJSWH
+JnIAUWs78hYvlF9WTNhHscJRTvOnH6qPJXoDSrfHfGwyRniwhjpfWyNovODgQdBLD6X/r6S+kGv
APsukHEWBG9vbLs/gFZXQ/csbgPNnX8nWwut7V9zsejPRDSIq/BlIda+YRGLX6g7ZYM/HyFd3sa5
oapfMsZRUTxRDBbF0Suh+fSVifM3TG4zA0VEDQ5mtwFG0OD7ugoXsIKDWELZQXb50uc6My8S6s/V
imPHQ3lrIvzOb1J+cku69OI1Qq7NYutiNmldXg/4Ew2U5hC02p9KWLjpCMgBKr3RdDUTUfSxGNZk
q+4KJnufiBzMIplKOUzvS2mYW6uXXwc1NBGGUpISKXjE6SAed+qtjSO36av9Agx79KPVnhZrhkkO
8lApHeyCujKHV88UBiYH+ZLAcjmn1j/8eUJAWrVnamuAy5YnJa9CSBUqdWOI6D8lweyfn1DmE6/5
2BjuAPT5jyda5LmL6s3TyNwUZdjqOG9DlBHqVpTnuBwfRPJlhn53JtboaIpSF0KIwG7Rr5ssDbpR
tux+rVIptlFDo/l8dcPMCKCPKuEM9OEiuwbRN+gpbU9sLhFySM7DhZIzC/hGRSCFblKw9oj/Xh4+
lXFBKvt6346z2TFKMY41Pu5lFILJUycPcGgxxDIhJhejZMe7sykxNOMH2wWx/gORmbVhD4m05m7s
80gIgVbX45ujvPGHKzuw06DP9bZKA6Bln/DIVPyzBGwkPHFeyD/PXipiuOezvGDN9ttaYaYYznxl
gJb1k6QjhoipnANXG32YQWTJ4P5TnlNEWRxHe63O3Azsy+eHWPA974AU6ZpK4MtCTiScKDm5id1i
iR3rr4AguHnhOb3+svGrxCKPFX6zLU99KYlUyymClk2a4PqVVfJjGu9L0nu802P4cwGb1Jojav5z
cHa+x96ng785/3uZptUhye63gDoSezwoNmQzfVYOmlWiZVVpnt91NTVtP0uYIuaNOcw2lIkZ34rz
SipCoz+8jG2wWQXsvZOtZ5AHN72VWwXCcVgPbuFphgt3kBVhQhgOuXk9FrgpXvwi4pikHpYxUjwb
vW0bfPcqLrzRYGYBTvMqJbfMHBpvShJMkawM3j67fgYloYjUODT9m9q6IzO1umAmsc68WwhS0rl9
4c/+mQ91tZJT+horg2n4TFCTJlNs8Ugy8V4IWKH29C94uzJaySWZ+F/3d1dM6fQaluYjLY68/XXD
o/b8GQxUbyyYHcOaf/cwdBzCIBbNpFJHAflQnVbEcYUlJ/BJ5j/iGV0zvLFl+SyvWpD1VK0Es9Ew
PYLe++LP4XS869d1W5EutUHjc3EXs0/ljtnqH15KQ2rMdhWk4gOtCdwETaThcx0tcmzNpEqh7yiN
QvV+hk/K6D1cEmW2qMqV/dIUOpwRVUkCfHilWIVpzA+D0vWIWNYBuIp9FYFwuvg8Y626LlASfdSA
RP3KI5v9N9kcnHQcRBxNXOuZOuXhFIRCrXcoiQI8FjkB+xngBJXKLvS/W5qVW3hdMcr9tMNBg5u7
ZLA/pgfCskVLCWfrtMFVpXKSssCZVRHIJxkxx67NlL6NM9Z70uqvdFvjwon22OMnlYnz8nakrU1e
W2g2mVgxZUpEEh/VWAwsFXpLurriRpaEi9guV1cRear4CjeqHcs++m8iV+opPrJ95axkQIBe0yVX
yJsnIrlQYiDCw1lLZ3MlETLh9Vdb6LbQ9C3Kdo25gBqkPVG6oo+CFqN+5clpAsJ3WWnzxYCA0V6p
uP5e7ScUJWtTfodJFFr07Jv7EGGpuoclTBGIDMX7EJ73gNujUh9VuXCVa8Ke0ogIiX9++kYxvEqw
m9ucZxfdoePwf1m3ColvIIukChlhT1tl50gH9xJ/CuESF4vX1KtoUn3vTaoVHQ5TsAv418WuaHG2
uqk2cZnp3YY4io/w78SRgSkA127HeqFdnmV6KjrhWp5VPw/H7bFGPDHl7TkrXhQVJYLYj/ANa6pQ
Knu9w5vtP110PrU4mm+hTLX2e2m5ZuM1oU8RXbE83Yd28QGs25UyLk8X8OR4vzYw7EFbV3+wK3d6
hBxrqx0Ze1C+KhWcRdLOEg0dH2a8IJoeiItMtpe4dSCDgpvPfFJkdfSXWaT5ditQioJqvjE94HbM
/HpU/HsSTzeL2FcK8qyGvCYmUIw2GNeZJIqwSDw0OZIOept3ts0+XyD9K6qb/LFsCXdGxkn+gzVo
IXHZ0VRVI6o9lPh1mJ/6jKTmaRRAqSeCbPreqJYlI1yp1V5Do8ECCK7ucmvPaWW84MrbwUkauwwY
c88hw9fcPJKWoKSWFe1DqYp08l+9cr8LI15x6JvQpznFdRMsUAGww0XiaLIf53urrOcNouSNT2rO
ZS/0w652U+QZI5Q6K/Z6h7ynnFqiVV93Sh3168fxQL4vxjSs5YaHyb3r0wdUVxMxy7hGbvZSMndG
JOxMyYOBVaCaoYchvsbxTjD9j8jyasEls5goow957RrOMnSttRYmJIFJQFsJ1koSo2g3hFwqJah4
XnAcGOpQbzSePW17qzjs7BiIC4IbQ2AbD/JK6InxlnaDNMSvTaN7yhtj9TDs/94XDW1eJ94q20KE
JzWeqAKbR8JTYCnubjYZk4T0nMe3JFFFFAvT+ghKxDQY9Y2QA6UsRmiztKHXyJfBoCocKjR/6PC8
UPV21Wm7YumxeHZB7O+XxFnYUWKkDChS4Mm9uxR0y7QQW+gbMPTo3APm8T5lvvB4K55Hzr9bfwrX
H1+obdtBQY/k1Io7iM3r2q+R4K66N0mkxWlw9sJ7+AT9/dfeA4Y9rgxkP1swN+JQ9vThN4HxEIia
qA1rIuPj6iSDO97Gd+2P3L666NXGObATG9EQKQNz70F5D+pIYyDrmJY/1cWwFNObNVRkiFmZRXCc
m2B6c8cVaZddP63O3G5+GazIe+Lr6TzZmuMcJnDxRO3fryGhknOsJn9NbjDLtOxnqPxWDYd1K9wM
zHKrpnj6cB3PqIGavhOG6M8jXt6md3uAGYUSQyIR/KmgpXnzUPy3ojQZa0f6W26FRydx4jHfh+y9
NlzqnPYGpgDg/500fBjYUKBlP4fKaOxCMKqrpQdWuDt3pKMJO8BCtC5DbtAm+OfMAXmqhub6Qbo8
h7f4d65BK+tlFuvhwxIrJM6MXv4N3l1oc0Nh3LliiDFoBN6HAyF5JUD7bb3acS2rrJcVjcam9+E6
bOPpY9ED5IyJIIh76f8lQPhQqMpvlMhPyjm1n8s36CCV3OWtakCKPhzY9HHM/q3g1LM9YtbJY3Be
Io7NV/VJLY6hR9/Y9EVSQ88Ue+kmhYjwDHO46FvHszHmIxHoC7gISPDHgDaLZ/LbKVATMclut2Gq
Goqd5WlypBbeb6ytRtdJKN7gbrf4
`protect end_protected
|
mit
|
31eff73368d0c285de2492f38ac7822c
| 0.954833 | 1.825905 | false | false | false | false |
superboy0712/MIPS
|
uart/uartRx.vhd
| 3 | 3,997 |
-----------------------------------------------------------------------------------------
-- uart receive module
--
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.ALL;
entity uartRx is
port ( clr : in std_logic; -- global reset input
clk : in std_logic; -- global clock input
ce16 : in std_logic; -- baud rate multiplyed by 16 - generated by baud module
serIn : in std_logic; -- serial data input
rxData : out std_logic_vector(7 downto 0); -- data byte received
newRxData : out std_logic); -- signs that a new byte was received
end uartRx;
architecture Behavioral of uartRx is
signal ce1 : std_logic; -- clock enable at bit rate
signal ce1Mid : std_logic; -- clock enable at the middle of each bit - used to sample data
signal inSync : std_logic_vector(1 downto 0);
signal count16 : std_logic_vector(3 downto 0);
signal rxBusy : std_logic;
signal bitCount : std_logic_vector(3 downto 0);
signal dataBuf : std_logic_vector(7 downto 0);
begin
-- input async input is sampled twice
process (clr, clk)
begin
if (clr = '1') then
inSync <= (others => '1');
elsif (rising_edge(clk)) then
inSync <= inSync(0) & serIn;
end if;
end process;
-- a counter to count 16 pulses of ce_16 to generate the ce_1 and ce_1_mid pulses.
-- this counter is used to detect the start bit while the receiver is not receiving and
-- signs the sampling cycle during reception.
process (clr, clk)
begin
if (clr = '1') then
count16 <= (others => '0');
elsif (rising_edge(clk)) then
if (ce16 = '1') then
if ((rxBusy = '1') or (inSync(1) = '0')) then
count16 <= count16 + 1;
else
count16 <= (others => '0');
end if;
end if;
end if;
end process;
-- receiving busy flag
process (clr, clk)
begin
if (clr = '1') then
rxBusy <= '0';
elsif (rising_edge(clk)) then
if ((rxBusy = '0') and (ce1Mid = '1')) then
rxBusy <= '1';
elsif ((rxBusy = '1') and (bitCount = "1000") and (ce1Mid = '1')) then
rxBusy <= '0';
end if;
end if;
end process;
-- bit counter
process (clr, clk)
begin
if (clr = '1') then
bitCount <= (others => '0');
elsif (rising_edge(clk)) then
if (rxBusy = '0') then
bitCount <= (others => '0');
elsif ((rxBusy = '1') and (ce1Mid = '1')) then
bitCount <= bitCount + 1;
end if;
end if;
end process;
-- data buffer shift register
process (clr, clk)
begin
if (clr = '1') then
dataBuf <= (others => '0');
elsif (rising_edge(clk)) then
if ((rxBusy = '1') and (ce1Mid = '1')) then
dataBuf <= inSync(1) & dataBuf(7 downto 1);
end if;
end if;
end process;
-- data output and flag
process (clr, clk)
begin
if (clr = '1') then
rxData <= (others => '0');
newRxData <= '0';
elsif (rising_edge(clk)) then
if ((rxBusy = '1') and (bitCount = "1000") and (ce1 = '1')) then
rxData <= dataBuf;
newRxData <= '1';
else
newRxData <= '0';
end if;
end if;
end process;
-- ce_1 pulse indicating expected end of current bit
ce1 <= '1' when ((count16 = "1111") and (ce16 = '1')) else '0';
-- ce_1_mid pulse indication the sampling clock cycle of the current data bit
ce1Mid <= '1' when ((count16 = "0111") and (ce16 = '1')) else '0';
end Behavioral;
|
mit
|
f877630df88acbb4baa6755b31e19dfe
| 0.488116 | 3.993007 | false | false | false | false |
unhold/hdl
|
vhdl/ddr_serdes/ddr_des.vhd
| 1 | 1,323 |
library ieee;
use ieee.std_logic_1164.all;
--- DDR deserializer.
entity ddr_des is
generic (
data_width_g : positive);
port (
clk_i,
reset_ni : in std_ulogic;
data_o : out std_ulogic_vector(data_width_g-1 downto 0);
valid_stb_o : out std_ulogic;
ddr_data_i,
bit_clk_i,
frame_clk_i : in std_ulogic);
end;
architecture rtl of ddr_des is
signal data_rising : std_ulogic;
signal shift_reg : std_ulogic_vector(data_width_g-1 downto 0);
-- clk_i domain: 2 sync FFs, 1 for edge detect
signal prev_frame_clk : std_ulogic_vector(2 downto 0);
begin
process(bit_clk_i)
begin
if rising_edge(bit_clk_i) then
data_rising <= ddr_data_i;
end if;
end process;
process(bit_clk_i)
begin
if falling_edge(bit_clk_i) then
shift_reg <= ddr_data_i & data_rising & shift_reg(shift_reg'left downto 2);
end if;
end process;
process(frame_clk_i)
begin
if falling_edge(frame_clk_i) then
data_o <= shift_reg;
end if;
end process;
-- valid_stb_o: detect falling edge on sync'ed frame_clk_i
process(clk_i, reset_ni)
begin
if reset_ni = '0' then
prev_frame_clk <= (others => '0');
elsif rising_edge(clk_i) then
prev_frame_clk <= frame_clk_i & prev_frame_clk(prev_frame_clk'left downto 1);
end if;
end process;
valid_stb_o <= prev_frame_clk(0) and not prev_frame_clk(1);
end;
|
gpl-3.0
|
4cc05ad21b1a4f14bbc51421f92d3bf9
| 0.66969 | 2.563953 | false | false | false | false |
freecores/w11
|
rtl/w11a/pdp11_ubmap.vhd
| 2 | 5,084 |
-- $Id: pdp11_ubmap.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_ubmap - syn
-- Description: pdp11: 11/70 unibus mapper
--
-- Dependencies: memlib/ram_1swar_gen
-- ib_sel
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.2 now numeric_std clean
-- 2010-10-23 335 1.1.1 use ib_sel
-- 2010-10-17 333 1.1 use ibus V2 interface
-- 2008-08-22 161 1.0.1 use iblib
-- 2008-01-27 115 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_ubmap is -- 11/70 unibus mapper
port (
CLK : in slbit; -- clock
MREQ : in slbit; -- request mapping
ADDR_UB : in slv18_1; -- UNIBUS address (in)
ADDR_PM : out slv22_1; -- physical memory address (out)
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end pdp11_ubmap;
architecture syn of pdp11_ubmap is
constant ibaddr_ubmap : slv16 := slv(to_unsigned(8#170200#,16));
signal IBSEL_UBMAP : slbit := '0';
signal MAP_2_WE : slbit := '0';
signal MAP_1_WE : slbit := '0';
signal MAP_0_WE : slbit := '0';
signal MAP_ADDR : slv5 := (others => '0'); -- map regs address
signal MAP_DOUT : slv22_1 := (others => '0'); -- map regs output
begin
MAP_2 : ram_1swar_gen -- bit 21:16 of map regs
generic map (
AWIDTH => 5,
DWIDTH => 6)
port map (
CLK => CLK,
WE => MAP_2_WE,
ADDR => MAP_ADDR,
DI => IB_MREQ.din(5 downto 0),
DO => MAP_DOUT(21 downto 16));
MAP_1 : ram_1swar_gen -- bit 15:08 of map regs
generic map (
AWIDTH => 5,
DWIDTH => 8)
port map (
CLK => CLK,
WE => MAP_1_WE,
ADDR => MAP_ADDR,
DI => IB_MREQ.din(15 downto 8),
DO => MAP_DOUT(15 downto 8));
MAP_0 : ram_1swar_gen -- bit 07:01 of map regs
generic map (
AWIDTH => 5,
DWIDTH => 7)
port map (
CLK => CLK,
WE => MAP_0_WE,
ADDR => MAP_ADDR,
DI => IB_MREQ.din(7 downto 1),
DO => MAP_DOUT(7 downto 1));
SEL : ib_sel
generic map (
IB_ADDR => ibaddr_ubmap,
SAWIDTH => 6) -- 2^6 = 64 = 2*32 words
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_UBMAP
);
proc_comb: process (MREQ, ADDR_UB, IBSEL_UBMAP, IB_MREQ, MAP_DOUT)
variable ibusy : slbit := '0';
variable idout : slv16 := (others=>'0');
variable iwe2 : slbit := '0';
variable iwe1 : slbit := '0';
variable iwe0 : slbit := '0';
variable iaddr : slv5 := (others=>'0');
begin
ibusy := '0';
idout := (others=>'0');
iwe2 := '0';
iwe1 := '0';
iwe0 := '0';
iaddr := (others=>'0');
if IBSEL_UBMAP = '1' then
if IB_MREQ.addr(1) = '1' then
idout(5 downto 0) := MAP_DOUT(21 downto 16);
else
idout(15 downto 1) := MAP_DOUT(15 downto 1);
end if;
if MREQ = '1' then -- if map request, stall ib cycle
ibusy := '1';
end if;
end if;
if IBSEL_UBMAP='1' and IB_MREQ.we='1' then
if IB_MREQ.addr(1)='1' then
if IB_MREQ.be0 = '1' then
iwe2 := '1';
end if;
else
if IB_MREQ.be1 = '1' then
iwe1 := '1';
end if;
if IB_MREQ.be0 = '1' then
iwe0 := '1';
end if;
end if;
end if;
if MREQ = '1' then
iaddr := ADDR_UB(17 downto 13);
else
iaddr := IB_MREQ.addr(6 downto 2);
end if;
MAP_ADDR <= iaddr;
MAP_2_WE <= iwe2;
MAP_1_WE <= iwe1;
MAP_0_WE <= iwe0;
ADDR_PM <= slv(unsigned(MAP_DOUT) +
unsigned("000000000"&ADDR_UB(12 downto 1)));
IB_SRES.ack <= IBSEL_UBMAP and (IB_MREQ.re or IB_MREQ.we);
IB_SRES.busy <= ibusy;
IB_SRES.dout <= idout;
end process proc_comb;
end syn;
|
gpl-2.0
|
f32322f7035b4924279ed2d92a33074b
| 0.513965 | 3.355776 | false | false | false | false |
freecores/w11
|
rtl/ibus/ib_sres_or_3.vhd
| 2 | 2,609 |
-- $Id: ib_sres_or_3.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ib_sres_or_3 - syn
-- Description: ibus: result or, 3 input
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.1 add ib_sres_or_mon
-- 2008-08-22 161 1.0.2 renamed pdp11_ibres_ -> ib_sres_; use iblib
-- 2008-01-05 110 1.0.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2007-12-29 107 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ib_sres_or_3 is -- ibus result or, 3 input
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output
);
end ib_sres_or_3;
architecture syn of ib_sres_or_3 is
begin
proc_comb : process (IB_SRES_1, IB_SRES_2, IB_SRES_3)
begin
IB_SRES_OR.ack <= IB_SRES_1.ack or
IB_SRES_2.ack or
IB_SRES_3.ack;
IB_SRES_OR.busy <= IB_SRES_1.busy or
IB_SRES_2.busy or
IB_SRES_3.busy;
IB_SRES_OR.dout <= IB_SRES_1.dout or
IB_SRES_2.dout or
IB_SRES_3.dout;
end process proc_comb;
-- synthesis translate_off
ORMON : ib_sres_or_mon
port map (
IB_SRES_1 => IB_SRES_1,
IB_SRES_2 => IB_SRES_2,
IB_SRES_3 => IB_SRES_3,
IB_SRES_4 => ib_sres_init
);
-- synthesis translate_on
end syn;
|
gpl-2.0
|
9aee72b6b6683aa9d06b30501785bc6f
| 0.54657 | 3.306717 | false | false | false | false |
alphaFred/Sejits4Fpgas
|
sejits4fpgas/hw/user/filter.vhd
| 1 | 17,024 |
-------------------------------------------------------------------------------
-- Title : Filter Module
-- Project : 2d3dtof
--
-------------------------------------------------------------------------------
-- File : filter.vhd
-- Author : Florian Seibold, Nina Muehleis, Daniel Ziener, Bernhard Schmidt
-- Email : [email protected]
-- Company : Informatik 12
-- Created : 2011-11-25
-- Last update: 2012-02-01
--
-------------------------------------------------------------------------------
-- Description:
-- This filter module can process a 2D filter operation on hd grayscale image
-- and calculates the absolute values. The input and output signals have
-- different bit widths.
--
-------------------------------------------------------------------------------
-- GENERIC description:
-- - FILTERMATRIX : 3x3 filter mask
-- - FILTER_SCALE : scale factor of the filter mask
-- - IMG_WIDTH : image width
-- - IMG_HEIGHT : image height
-- - IN_BITWIDTH : bit width of the input signals
-- - OUT_BITWIDTH : bit width of the output signal
--
-------------------------------------------------------------------------------
-- PORT description:
--
-- INPUTS:
-- - CLK : input clock for the module
-- - RESET : synchronous, high-active reset input
-- - DATA_IN : input values, gray scale values in general
-- - H_SYNC_IN : input hsync signal
-- - V_SYNC_IN : input vsync signal
--
-- OUTPUTS: ( the output is delayed by 1 cycle)
-- - DATA_OUT : filtered values, pixel
-- - H_SYNC_OUT : output hsync signal
-- - V_SYNC_OUT : output vsync signal
--
-------------------------------------------------------------------------------
-- LIMITATIONS:
-- - image width must be smaller than 2046
-- - only 3x3 filter masks are allowed
-- - region of values is limited, be careful!
-------------------------------------------------------------------------------
-- Copyright (c) 2012 Informatik 12
-------------------------------------------------------------------------------
-- Changed 28.05.2012
-- Added output valid
-- Added process valid
-- Added fifo_data_count
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.the_filter_package.all;
entity filter is
generic(
FILTERMATRIX : filtMASK := (0,0,0,0, 1, 0, 0, 0,0 );
FILTER_SCALE : integer := 16;
IN_BITWIDTH : positive := 12;
OUT_BITWIDTH : positive := 16
);
port(
CLK : in std_logic;
RESET : in std_logic;
IMG_WIDTH : in integer := 1920;
IMG_HEIGHT : in integer := 1080;
DATA_IN : in std_logic_vector(IN_BITWIDTH-1 downto 0);
H_SYNC_IN : in std_logic;
V_SYNC_IN : in std_logic;
DATA_OUT : out std_logic_vector(OUT_BITWIDTH-1 downto 0);
H_SYNC_OUT : out std_logic; -- um zwei Takte verzoegert
V_SYNC_OUT : out std_logic;
VALID : inout std_logic := '0'
);
end entity filter;
architecture IMP of filter is
--------------------------------
-- FIFO Component --
--------------------------------
component bram_fifo is
generic (width, dept : integer);
port(
clk : in std_logic;
din : in std_logic_vector(width-1 downto 0);
rd_en : in std_logic;
rst : in std_logic;
wr_en : in std_logic;
data_count : out std_logic_vector(10 downto 0); --width-1
dout : out std_logic_vector(width-1 downto 0);
empty : out std_logic;
full : out std_logic;
prog_full : out std_logic
);
end component bram_fifo;
--------------------------
-- SIGNALS --
--------------------------
-- Types
-- constants
constant MAXFILTVAL : integer := (2 ** IN_BITWIDTH -1) *3;
constant MINFILTVAL : integer := (2 ** IN_BITWIDTH -1) * (-2);
constant FILTERSIZE : integer := 3; -- filtersize (3x3)
constant SYNC_DELAY : positive:= 646; -- for delay line
constant bpp : integer := IN_BITWIDTH; -- width of pixel fifos
constant fifo_size : integer := 2048; -- size of fifo
signal hsync_delay_line : std_logic_vector(SYNC_DELAY-1 downto 0) := (others => '0');
signal vsync_delay_line : std_logic_vector(SYNC_DELAY-1 downto 0) := (others => '0');
-- TYPES for FIFO SIGNALS
type filterarray is array (filtersize*filtersize-1 downto 0) of integer range MINFILTVAL to MAXFILTVAL;
type imagemask is array (filtersize*filtersize-1 downto 0) of std_logic_vector(IN_BITWIDTH-1 downto 0);
type fifo_io is array (filtersize-2 downto 0) of std_logic_vector(bpp-1 downto 0);
type fifo_data_count_type is array (filtersize-2 downto 0) of std_logic_vector(10 downto 0);
type valid_state is (SET_VALID, UNSET_VALID);
-- colors
constant BLACKx : std_logic_vector(IN_BITWIDTH-1 downto 0) := (others => '0');
-- FIFO SIGNALS
signal fifo_rd_en : std_logic_vector(filtersize-2 downto 0) := (others => '0');
signal fifo_wr_en : std_logic_vector(filtersize-2 downto 0) := (others => '0');
signal fifo_empty : std_logic_vector(filtersize-2 downto 0);
signal fifo_data_in : fifo_io;
signal fifo_data_out : fifo_io;
signal fifo_data_count : fifo_data_count_type;
signal fifo_valid_state : valid_state := UNSET_VALID;
type state is (start_fl,in_fl, start_nl, in_nl, start_ll, in_ll, end_img);
signal next_state : state := start_fl;
signal pixelmatrix : imagemask;
signal pfilt : filterarray;
signal filtered_pixel : std_logic_vector(OUT_BITWIDTH-1 downto 0);
signal datain : std_logic_vector(IN_BITWIDTH-1 downto 0);
signal vertical_counter : integer range 0 to 2047 := 0; -- vertical image counter
signal data_inReg : std_logic_vector(IN_BITWIDTH-1 downto 0);
signal data_inRegReg : std_logic_vector(IN_BITWIDTH-1 downto 0);
signal process_pixel : std_logic := '0';
signal shift_pixel : std_logic := '0';
signal sum_pixel : std_logic := '0';
signal reinit : std_logic := '0';
signal reset_fifo : std_logic := '0';
signal new_img : std_logic := '0';
signal hsync_reg : std_logic;
signal vsync_reg : std_logic;
signal hsync_regreg : std_logic;
signal vsync_regreg : std_logic;
signal valid_reg : std_logic := '0';
signal h_sync_int : std_logic := '0';
signal v_sync_int : std_logic := '0';
type vsync_state_type is (UNSET_VSYNC, SET_VSYNC);
signal vsync_state : vsync_state_type := UNSET_VSYNC;
signal line_cnt : integer range 0 to 2048;
signal valid_rising_edge : std_logic := '0';
signal valid_falling_edge : std_logic := '0';
begin
-- ##########################################
-- Generate FIFOS
-- ==============
-- Number of FIFOs == Filter Size
-- ##########################################
-- ######################################
-- PIXEL CLOCK
-- ######################################
FIFO_Data_Generation : for i in 0 to (filtersize-2) generate -- two fifos are needed for a filter of 3x3
begin
dfifo : component bram_fifo
generic map(width => bpp, dept => fifo_size)
port map(
clk => CLK,
din => fifo_data_in(i),
rd_en => fifo_rd_en(i),
rst => reset_fifo,
wr_en => fifo_wr_en(i),
data_count => fifo_data_count(i),
dout => fifo_data_out(i),
empty => fifo_empty(i),
full => open,
prog_full => open
);
end generate FIFO_Data_Generation;
pxl_CLK : process(CLK)
begin
if (CLK'event and CLK = '1') then
shift_pixel <= process_pixel;
sum_pixel <= shift_pixel;
data_inReg <= DATA_IN;
data_inRegReg <= data_inReg;
hsync_reg <= H_SYNC_IN;
vsync_reg <= V_SYNC_IN;
hsync_regreg <= hsync_reg;
vsync_regreg <= vsync_reg;
valid_reg <= valid;
--hsync_delay_line <= hsync_delay_line(SYNC_DELAY-2 downto 0) & H_SYNC_IN;
--vsync_delay_line <= vsync_delay_line(SYNC_DELAY-2 downto 0) & V_SYNC_IN;
end if;
end process pxl_CLK;
-- #####################################
-- general sync signals
--- ====================
-- This process writes the sync signals to a fifo and
-- increases/decreases counters (vertical/horizontal)
-- Furthermore it triggers the start of writing/reading
-- the sync signals
-- #####################################
general_sync_signals : process(CLK, reset)
begin
if reinit = '1' then
process_pixel <='0';
vertical_counter <= 0;
fifo_wr_en(0) <='0';
fifo_wr_en(1) <='0';
fifo_rd_en(0) <='0';
fifo_rd_en(1) <='0';
pixelmatrix(2) <= BLACKx;
pixelmatrix(5) <= BLACKx;
pixelmatrix(8) <= BLACKx;
next_state <= start_fl;
elsif (CLK'event and CLK = '1') then
process_pixel <='0';
vertical_counter <= 0;
fifo_wr_en(0) <='0';
fifo_wr_en(1) <='0';
fifo_rd_en(0) <='0';
fifo_rd_en(1) <='0';
pixelmatrix(2) <= BLACKx;
pixelmatrix(5) <= BLACKx;
pixelmatrix(8) <= BLACKx;
new_img <= '0';
case next_state is
when start_fl =>
if hsync_reg = '1' and vsync_reg = '1' then
vertical_counter <= vertical_counter +1;
fifo_wr_en(0) <= '1'; -- Randnuller
fifo_wr_en(1) <= '1';
fifo_data_in(0) <= BLACKx;
fifo_data_in(1) <= BLACKx;
next_state <= in_fl;
end if;
when in_fl =>
vertical_counter <= vertical_counter;
fifo_wr_en(0) <= '1'; -- Randnuller
fifo_wr_en(1) <= '1';
fifo_data_in(0) <= BLACKx;
fifo_data_in(1) <= data_inRegReg;
next_state <= in_fl;
if hsync_regreg = '0' then
fifo_wr_en(0) <= '1'; -- Randnulle
fifo_wr_en(1) <= '1';
fifo_data_in(0) <= BLACKx;
fifo_data_in(1) <= BLACKx;
next_state <= start_nl;
end if;
when start_nl =>
vertical_counter <= vertical_counter;
if (H_SYNC_IN = '1') and (V_SYNC_IN = '1') then
fifo_rd_en(0) <= '1';
fifo_rd_en(1) <= '1';
if hsync_reg = '1' then
vertical_counter <= vertical_counter + 1;
fifo_wr_en(0) <= '1';
fifo_wr_en(1) <= '1';
fifo_rd_en(0) <= '1';
fifo_rd_en(1) <= '1';
fifo_data_in(0) <= fifo_data_out(1);
fifo_data_in(1) <= BLACKx;
process_pixel <= '1';
pixelmatrix(2) <= fifo_data_out(0);
pixelmatrix(5) <= fifo_data_out(1);
pixelmatrix(8) <= BLACKx;
next_state <= in_nl;
end if;
end if;
when in_nl =>
vertical_counter <= vertical_counter;
fifo_wr_en(0) <= '1';
fifo_wr_en(1) <= '1';
fifo_rd_en(0) <= '1';
fifo_rd_en(1) <= '1';
fifo_data_in(0) <= fifo_data_out(1);
fifo_data_in(1) <= data_inRegReg;
process_pixel <= '1';
pixelmatrix(2) <= fifo_data_out(0);
pixelmatrix(5) <= fifo_data_out(1);
pixelmatrix(8) <= data_inRegReg;
if (hsync_reg = '0') then
fifo_rd_en(0) <= '1';
fifo_rd_en(1) <= '1';
end if;
if hsync_regreg = '0' then
process_pixel <= '0';
fifo_wr_en(0) <= '1';
fifo_wr_en(1) <= '1';
fifo_rd_en(0) <= '0';
fifo_rd_en(1) <= '0';
fifo_data_in(0) <= fifo_data_out(1);
fifo_data_in(1) <= BLACKx;
pixelmatrix(2) <= fifo_data_out(0);
pixelmatrix(5) <= fifo_data_out(1);
pixelmatrix(8) <= BLACKx;
next_state <= start_nl;
if vertical_counter = IMG_HEIGHT then
--next_state <= end_img;
next_state <= start_ll;
end if;
end if;
when start_ll =>
fifo_wr_en(0) <= '0';
fifo_wr_en(1) <= '0';
fifo_rd_en(0) <= '1';
fifo_rd_en(1) <= '1';
next_state <= in_ll;
when in_ll =>
fifo_rd_en(0) <= '1';
fifo_rd_en(1) <= '1';
pixelmatrix(2) <= fifo_data_out(0);
pixelmatrix(5) <= fifo_data_out(1);
pixelmatrix(8) <= BLACKx;
process_pixel <= '1';
if unsigned(fifo_data_count(filtersize-2)) = 1 then
next_state <= end_img;
process_pixel <= '0';
fifo_rd_en(0) <= '0';
fifo_rd_en(1) <= '0';
end if;
when end_img =>
new_img <= '1';
next_state <= start_fl;
end case;
end if;
end process general_sync_signals;
-- ##############################################
-- Generate Filter Processes
-- multiply all components
-- ##############################################
filtergeneration : for i in 0 to filtersize*filtersize-1 generate
begin
filter_process : process(CLK)
begin
if (CLK = '1' and CLK'EVENT) then
pfilt(i) <= to_integer(unsigned(pixelmatrix(i))) * filtermatrix(i);
end if;
end process filter_process;
end generate filtergeneration;
-- ##############################################
-- PROCESS pmproc
-- FILTERMATRIX --> pixel durchschieben!
-- ##############################################
pmproc : process (CLK)
begin
if (CLK = '1' and CLK'EVENT) then
if reinit = '1' or reset = '1' then -- initialize pixel
pixelmatrix(0) <= BLACKx;
pixelmatrix(1) <= BLACKx;
pixelmatrix(3) <= BLACKx;
pixelmatrix(4) <= BLACKx;
pixelmatrix(6) <= BLACKx;
pixelmatrix(7) <= BLACKx;
elsif process_pixel = '1' then -- process pixel
pixelmatrix(0) <= pixelmatrix(1);
pixelmatrix(1) <= pixelmatrix(2);
pixelmatrix(3) <= pixelmatrix(4);
pixelmatrix(4) <= pixelmatrix(5);
pixelmatrix(6) <= pixelmatrix(7);
pixelmatrix(7) <= pixelmatrix(8);
end if;
end if;
end process pmproc;
-- #################################
-- ergebnis addieren
-- process msum
-- #################################
msum : process(CLK)
variable tmppfilt0 : integer range 4*4095 downto -4*4095;
variable tmppfilt1 : integer range 4*4095 downto -4*4095;
variable bv : signed(OUT_BITWIDTH-1 downto 0);
begin
if (CLK = '1' and CLK'EVENT) then
--valid <= '0';
--if (sum_pixel = '1') then
tmppfilt0 := 0;
tmppfilt1 := 0;
-- add all
for k in 0 to ((filtersize*filtersize)/2-1) loop
tmppfilt0 := tmppfilt0 + pfilt(k);
end loop;
for k in ((filtersize*filtersize)/2) to filtersize*filtersize-1 loop
tmppfilt1 := tmppfilt1 + pfilt(k);
end loop;
tmppfilt0 := (tmppfilt0 + tmppfilt1)/FILTER_SCALE; -- scale
bv := to_signed(tmppfilt0, bv'length);
filtered_pixel <= std_logic_vector(bv); -- output
--valid <= '1';
--else
-- filtered_pixel <= (others => '1');
--end if;
end if;
end process msum;
-- ##############################################
-- PROCESS proc_valid
-- Produces an output valid signal
-- ##############################################
proc_valid : process (CLK)
begin
if (CLK = '1' and CLK'EVENT) then
case fifo_valid_state is
when UNSET_VALID =>
valid <= '0';
if (sum_pixel = '1') then
fifo_valid_state <= SET_VALID;
end if;
when SET_VALID =>
valid <= '1';
if (sum_pixel = '0') then
valid <= '0';
fifo_valid_state <= UNSET_VALID;
end if;
end case;
end if;
end process proc_valid;
-- ##############################################
-- PROCESS proc_vsync
-- Produces the vsync signal
-- ##############################################
proc_vsync : process (CLK)
--variable line_cnt : integer := 0;
begin
if (CLK = '1' and CLK'EVENT) then
if reinit = '1' then
v_sync_int <= '0';
--valid_reg <= '0';
line_cnt <= 0;
vsync_state <= UNSET_VSYNC;
else
case vsync_state is
when UNSET_VSYNC =>
if valid = '1' and valid_reg = '0' and line_cnt = 0 then
v_sync_int <= '1';
vsync_state <= SET_VSYNC;
end if;
when SET_VSYNC =>
if valid = '0' and valid_reg = '1' then
line_cnt <= line_cnt + 1;
if line_cnt = IMG_HEIGHT - 1 then
v_sync_int <= '0';
vsync_state <= UNSET_VSYNC;
end if;
end if;
end case;
end if;
end if;
end process proc_vsync;
valid_rising_edge <= '1' when valid = '1' and valid_reg = '0' and line_cnt = 0 else '0';
valid_falling_edge <= '1' when valid = '0' and valid_reg = '1' and line_cnt = IMG_HEIGHT - 1 else '0';
V_SYNC_OUT <= (v_sync_int or valid_rising_edge) and (not valid_falling_edge);
proc_reset : process (CLK)
begin
if (CLK = '1' and CLK'EVENT) then
reinit <= '0';
if reset = '1' then
reinit <= '1';
end if;
end if;
end process;
proc_reset_fifo : process (CLK)
begin
if (CLK = '1' and CLK'EVENT) then
reset_fifo <= '0';
if new_img = '1' or reset = '1' then
reset_fifo <= '1';
end if;
end if;
end process;
DATA_OUT <= filtered_pixel;
H_SYNC_OUT <= hsync_delay_line(SYNC_DELAY-1);
--V_SYNC_OUT <= v_sync_int;--vsync_delay_line(SYNC_DELAY-1);
end IMP;
|
gpl-3.0
|
99110019a63d968e0adf21c63cc6ac3b
| 0.521558 | 3.341971 | false | false | false | false |
vaisup/uvmprimer
|
23_UVM_Sequences/tinyalu_dut/three_cycle_mult.vhd
| 24 | 2,435 |
-- Copyright 2013 Ray Salemi
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- VHDL Architecture tinyalu_lib.three_cycle.mult
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY three_cycle IS
PORT(
A : IN unsigned ( 7 DOWNTO 0 );
B : IN unsigned ( 7 DOWNTO 0 );
clk : IN std_logic;
reset_n : IN std_logic;
start : IN std_logic;
done_mult : OUT std_logic;
result_mult : OUT unsigned (15 DOWNTO 0)
);
-- Declarations
END three_cycle ;
--
architecture mult of three_cycle is
signal a_int,b_int : unsigned (7 downto 0); -- start pipeline
signal mult1,mult2 : unsigned (15 downto 0); -- pipeline registers
signal done3,done2,done1,done_mult_int : std_logic; -- pipeline the done signal
begin
-- purpose: Three stage pipelined multiplier
-- type : sequential
-- inputs : clk, reset_n, a,b
-- outputs: result_mult
multiplier: process (clk, reset_n)
begin -- process multiplier
if reset_n = '0' then -- asynchronous reset (active low)
done_mult_int <= '0';
done3 <= '0';
done2 <= '0';
done1 <= '0';
a_int <= "00000000";
b_int <= "00000000";
mult1 <= "0000000000000000";
mult2 <= "0000000000000000";
result_mult <= "0000000000000000";
elsif clk'event and clk = '1' then -- rising clock edge
a_int <= a;
b_int <= b;
mult1 <= a_int * b_int;
mult2 <= mult1;
result_mult <= mult2;
done3 <= start and (not done_mult_int);
done2 <= done3 and (not done_mult_int);
done1 <= done2 and (not done_mult_int);
done_mult_int <= done1 and (not done_mult_int);
end if;
end process multiplier;
done_mult <= done_mult_int;
end architecture mult;
|
apache-2.0
|
b205582f7c5e4f677f2997ce682a893e
| 0.598768 | 3.64521 | false | false | false | false |
palbicoc/AUX_Bus
|
AUX_bus.srcs/sources_1/new/prbs_any.vhd
| 1 | 8,098 |
--------------------------------------------------------------------------------
-- File Name: PRBS_ANY.vhd
-- Version: 1.1
-- Date: 06-2015
--------------------------------------------------------------------------------
--
-- Company: Xilinx, Inc.
-- Contributor: Daniele Riccardi, Paolo Novellini
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2010 Xilinx, Inc.
-- All rights reserved.
--
----------------------------------------------------------------------------
-- DESCRIPTION
----------------------------------------------------------------------------
-- This module generates or check a PRBS pattern. The following table shows how
-- to set the GENERICS for compliance to ITU-T Recommendation O.150 Section 5.
--
----------------------------------------------------------------------------
-- GENERICS
----------------------------------------------------------------------------
-- INV_PATTERN : true : invert prbs pattern
-- in "generate mode" the generated prbs is inverted bit-wise at outputs
-- in "check mode" the input data are inverted before processing
-- POLY_LENGHT : length of the polynomial (= number of shift register stages)
-- POLY_TAP : intermediate stage that is xor-ed with the last stage to generate to next prbs bit
-- NBITS : bus size of DATA_IN and DATA_OUT
--
----------------------------------------------------------------------------
-- NOTES
----------------------------------------------------------------------------
--
--
-- Set paramaters to the following values for a ITU-T compliant PRBS
--------------------------------------------------------------------------------
-- POLY_LENGHT POLY_TAP INV_PATTERN || nbr of bit seq. max 0 feedback
-- || stages length sequence stages
--------------------------------------------------------------------------------
-- 7 6 false || 7 127 6 ni 6, 7
-- 9 5 false || 9 511 8 ni 5, 9
-- 11 9 false || 11 2047 10 ni 9,11
-- 15 14 true || 15 32767 15 i 14,15
-- 20 3 false || 20 1048575 19 ni 3,20
-- 23 18 true || 23 8388607 23 i 18,23
-- 29 27 true || 29 536870911 29 i 27,29
-- 31 28 true || 31 2147483647 31 i 28,31
--
-- i=inverted, ni= non-inverted
------------------------------------------------------------------------------
--
-- In the generated parallel PRBS, LSB is the first generated bit, for example
-- if the PRBS serial stream is : 000001111011... then
-- the generated PRBS with a parallelism of 3 bit becomes:
-- data_out(2) = 0 1 1 1 ...
-- data_out(1) = 0 0 1 1 ...
-- data_out(0) = 0 0 1 0 ...
-- In the received parallel PRBS, LSB is oldest bit received
--
-- RESET pin is not needed for power-on reset : all registers are properly inizialized
-- in the source code.
--
--------------------------------------------------------------------------------
-- PINS DESCRIPTION
--------------------------------------------------------------------------------
--
-- RST : in : syncronous reset active high
-- CLK : in : system clock
-- DATA_IN : in : inject error (in generate mode)
-- data to be checked (in check mode)
-- EN : in : enable/pause pattern generation/check
-- DATA_OUT : out: generated prbs pattern (in generate mode)
-- error found (in check mode)
-- CHK_MODE : '1' => check mode
-- '0' => generate mode
--
-- When the CHK_MODE is '0', it uses a LFSR strucure to generate the
-- PRBS pattern.
-- When the CHK_MODE is '1', the incoming data are loaded into prbs registers
-- and compared with the locally generated PRBS.
---------------------------------------------------------------------------------------------------
-- History:
-- Version : 1.0
-- Date : 6-jul-10
-- Author : Daniele Riccardi
-- Description: First release
--
-- Version : 1.1
-- Date : 06-2015
-- Author : Pietro Albicocco, LNF-INFN
-- Description: CHK_MODE moved from generic of type boolean to input port of type std_logic.
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PRBS_ANY is
generic (
--CHK_MODE: boolean := false;
INV_PATTERN : boolean := false;
POLY_LENGHT : natural range 2 to 63 := 7 ;
POLY_TAP : natural range 1 to 62 := 6 ;
NBITS : natural range 1 to 512 := 4
);
port (
CHK_MODE : in std_logic;
RST : in std_logic; -- sync reset active high
CLK : in std_logic; -- system clock
DATA_IN : in std_logic_vector(NBITS - 1 downto 0); -- inject error/data to be checked
EN : in std_logic; -- enable/pause pattern generation
DATA_OUT : out std_logic_vector(NBITS - 1 downto 0):= (others => '0') -- generated prbs pattern/errors found
);
end PRBS_ANY;
architecture PRBS_ANY of PRBS_ANY is
type prbs_type is array (NBITS downto 0) of std_logic_vector(1 to POLY_LENGHT);
signal prbs : prbs_type := (others => (others => '1'));
signal data_in_i : std_logic_vector(NBITS-1 downto 0);
signal prbs_xor_a : std_logic_vector(NBITS-1 downto 0);
signal prbs_xor_b : std_logic_vector(NBITS-1 downto 0);
signal prbs_msb : std_logic_vector(NBITS downto 1);
begin
data_in_i <= DATA_IN when INV_PATTERN = false else (not DATA_IN);
g1: for I in 0 to NBITS-1 generate
prbs_xor_a(I) <= prbs(I)(POLY_TAP) xor prbs(I)(POLY_LENGHT);
prbs_xor_b(I) <= prbs_xor_a(I) xor data_in_i(I);
prbs_msb(I+1) <= prbs_xor_a(I) when CHK_MODE = '0' else data_in_i(I);
prbs(I+1) <= prbs_msb(I+1) & prbs(I)(1 to POLY_LENGHT-1);
end generate;
PRBS_GEN_01 : process (CLK)
begin
if rising_edge(CLK) then
if RST = '1' then
prbs(0) <= (others => '1');
DATA_OUT <= (others => '1');
elsif EN = '1' then
DATA_OUT <= prbs_xor_b;
prbs(0) <= prbs(NBITS);
end if;
end if;
end process;
end PRBS_ANY;
|
mit
|
b22ade879b0e166c45ecb72a6ef46f1d
| 0.444431 | 4.534155 | false | false | false | false |
freecores/w11
|
rtl/vlib/rlink/tb/tbu_rlink_sp1c.vhd
| 2 | 6,098 |
-- $Id: tbu_rlink_sp1c.vhd 442 2011-12-23 10:03:28Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tbu_rlink_sp1c - syn
-- Description: Wrapper for rlink_sp1c to avoid records.
-- It has a port interface which will not be modified by xst
-- synthesis (no records, no generic port).
--
-- Dependencies: rlink_sp1c
--
-- To test: rlink_sp1c
--
-- Target Devices: generic
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-12-22 442 13.1 O40d xc3s1000-4 348 704 64 473 s 9.08
-- 2010-04-03 274 11.4 L68 xc3s1000-4 278 588 18 366 s 9.83
-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 273 547 18 - t 9.65
-- 2007-10-27 92 9.1 J30 xc3s1000-4 273 545 18 - t 9.65
-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 283 594 18 323 s 10.3
-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 285 596 18 - s 9.32
--
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-22 442 3.2 renamed and retargeted to test rlink_sp1c
-- 2011-11-19 427 3.1.2 now numeric_std clean
-- 2010-12-28 350 3.1.1 use CLKDIV/CDINIT=0;
-- 2010-12-26 348 3.1 use rlink_base now; add RTS/CTS ports
-- 2010-12-24 347 3.0.1 rename: CP_*->RL->*
-- 2010-12-05 343 3.0 rri->rlink renames; port to rbus V3 protocol;
-- 2010-06-03 300 2.2.3 use default FAWIDTH for rri_core_serport
-- 2010-05-02 287 2.2.2 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT from interfaces; drop RTSFLUSH generic
-- 2010-04-18 279 2.2.1 drop RTSFBUF generic for rri_serport
-- 2010-04-03 274 2.2 add CP_FLUSH, add rri_serport handshake logic
-- 2009-03-14 197 2.1 remove records in interface to allow _ssim usage
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2007-11-24 98 1.1 added RP_IINT support
-- 2007-07-02 63 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.rlinklib.all;
entity tbu_rlink_sp1c is -- rlink core+serport combo
port (
CLK : in slbit; -- clock
CE_INT : in slbit; -- rlink ito time unit clock enable
CE_USEC : in slbit; -- 1 usec clock enable
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
CTS_N : in slbit; -- clear to send (act.low, board view)
RTS_N : out slbit; -- request to send (act.low, board view)
RB_MREQ_aval : out slbit; -- rbus: request - aval
RB_MREQ_re : out slbit; -- rbus: request - re
RB_MREQ_we : out slbit; -- rbus: request - we
RB_MREQ_initt: out slbit; -- rbus: request - init; avoid name coll
RB_MREQ_addr : out slv8; -- rbus: request - addr
RB_MREQ_din : out slv16; -- rbus: request - din
RB_SRES_ack : in slbit; -- rbus: response - ack
RB_SRES_busy : in slbit; -- rbus: response - busy
RB_SRES_err : in slbit; -- rbus: response - err
RB_SRES_dout : in slv16; -- rbus: response - dout
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end entity tbu_rlink_sp1c;
architecture syn of tbu_rlink_sp1c is
constant CDWIDTH : positive := 13;
constant c_cdinit : natural := 0; -- NOTE: change in tbd_rlink_sp1c !!
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RLB_DI : slv8 := (others=>'0');
signal RLB_ENA : slbit := '0';
signal RLB_BUSY : slbit := '0';
signal RLB_DO : slv8 := (others=>'0');
signal RLB_VAL : slbit := '0';
signal RLB_HOLD : slbit := '0';
begin
RB_MREQ_aval <= RB_MREQ.aval;
RB_MREQ_re <= RB_MREQ.re;
RB_MREQ_we <= RB_MREQ.we;
RB_MREQ_initt<= RB_MREQ.init;
RB_MREQ_addr <= RB_MREQ.addr;
RB_MREQ_din <= RB_MREQ.din;
RB_SRES.ack <= RB_SRES_ack;
RB_SRES.busy <= RB_SRES_busy;
RB_SRES.err <= RB_SRES_err;
RB_SRES.dout <= RB_SRES_dout;
RLINK : rlink_sp1c
generic map (
ATOWIDTH => 5,
ITOWIDTH => 6,
CPREF => c_rlink_cpref,
IFAWIDTH => 5,
OFAWIDTH => 5,
ENAPIN_RLMON => -1, -- no monitors (both are instantiated in
ENAPIN_RBMON => -1, -- tbd_rlink_sp1c for ssim avail.)
CDWIDTH => 15,
CDINIT => c_cdinit)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_INT,
RESET => RESET,
ENAXON => '0',
ENAESC => '0',
RXSD => RXSD,
TXSD => TXSD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open
-- SER_MONI => open -- ISE 13.1 err's when a second record is mapped open
);
end syn;
|
gpl-2.0
|
c45c567fbd2e1aa636ed9ee86a3c9517
| 0.547721 | 3.216245 | false | false | false | false |
Vadman97/ImageAES
|
des/DES/ipcore_dir/constants_mem/example_design/constants_mem_prod (Vadim-Laptop's conflicted copy 2017-04-27).vhd
| 1 | 9,936 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: constants_mem_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : constants_mem.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 1
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 1
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY constants_mem_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END constants_mem_prod;
ARCHITECTURE xilinx OF constants_mem_prod IS
COMPONENT constants_mem_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : constants_mem_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
gpl-3.0
|
9fe8928bbbc8a37cd5546572a2b70a27
| 0.495773 | 3.834813 | false | false | false | false |
freecores/w11
|
rtl/vlib/rlink/tb/tbd_rlink_sp1c.vhd
| 1 | 9,513 |
-- $Id: tbd_rlink_sp1c.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tbd_rlink_sp1c - syn
-- Description: Wrapper for rlink_core plus rlink_serport with an interface
-- compatible to the rlink_core only module.
-- NOTE: this implementation is a hack, should be redone
-- using configurations.
--
-- Dependencies: tbu_rlink_sp1c [UUT]
-- serport_uart_tx
-- serport_uart_rx
-- byte2cdata
-- cdata2byte
-- simlib/simclkcnt
--
-- To test: rlink_sp1c
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 3.2 use simclkcnt instead of simbus global
-- 2011-12-22 442 3.1 renamed and retargeted to tbu_rlink_sp1c
-- 2011-11-19 427 3.0.5 now numeric_std clean
-- 2010-12-28 350 3.0.4 use CLKDIV/CDINIT=0;
-- 2010-12-26 348 3.0.3 add RTS/CTS ports for tbu_;
-- 2010-12-24 347 3.0.2 rename: CP_*->RL->*
-- 2010-12-22 346 3.0.1 removed proc_moni, use .rlmon cmd in test bench
-- 2010-12-05 343 3.0 rri->rlink renames; port to rbus V3 protocol;
-- 2010-06-06 301 2.3 use NCOMM=4 (new eop,nak commas)
-- 2010-05-02 287 2.2.2 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- 2010-04-24 281 2.2.1 use serport_uart_[tr]x directly again
-- 2010-04-03 274 2.2 add CE_USEC
-- 2009-03-14 197 2.1 remove records in interface to allow _ssim usage
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2007-11-25 98 1.1 added RP_IINT support; use entity rather arch
-- name to switch core/serport;
-- use serport_uart_[tr]x_tb to allow that UUT is a
-- [sft]sim model compiled with keep hierarchy
-- 2007-07-02 63 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.comlib.all;
use work.serportlib.all;
use work.simlib.all;
use work.simbus.all;
entity tbd_rlink_sp1c is -- rlink_sp1c tb design
-- implements tbd_rlink_gen
port (
CLK : in slbit; -- clock
CE_INT : in slbit; -- rlink ito time unit clock enable
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit; -- reset
RL_DI : in slv9; -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : out slbit; -- rlink: data busy
RL_DO : out slv9; -- rlink: data out
RL_VAL : out slbit; -- rlink: data valid
RL_HOLD : in slbit; -- rlink: data hold
RB_MREQ_aval : out slbit; -- rbus: request - aval
RB_MREQ_re : out slbit; -- rbus: request - re
RB_MREQ_we : out slbit; -- rbus: request - we
RB_MREQ_initt : out slbit; -- rbus: request - init; avoid name coll
RB_MREQ_addr : out slv8; -- rbus: request - addr
RB_MREQ_din : out slv16; -- rbus: request - din
RB_SRES_ack : in slbit; -- rbus: response - ack
RB_SRES_busy : in slbit; -- rbus: response - busy
RB_SRES_err : in slbit; -- rbus: response - err
RB_SRES_dout : in slv16; -- rbus: response - dout
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3; -- rbus: status flags
TXRXACT : out slbit -- txrx active flag
);
end entity tbd_rlink_sp1c;
architecture syn of tbd_rlink_sp1c is
constant CDWIDTH : positive := 13;
constant c_cdinit : natural := 0; -- NOTE: change in tbu_rlink_sp1c !!
signal RRI_RXSD : slbit := '0';
signal RRI_TXSD : slbit := '0';
signal RTS_N : slbit := '0';
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal CLKDIV : slv13 := slv(to_unsigned(c_cdinit,CDWIDTH));
signal CLK_CYCLE : integer := 0;
component tbu_rlink_sp1c is -- rlink core+serport combo
port (
CLK : in slbit; -- clock
CE_INT : in slbit; -- rlink ito time unit clock enable
CE_USEC : in slbit; -- 1 usec clock enable
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
CTS_N : in slbit; -- clear to send (act.low, board view)
RTS_N : out slbit; -- request to send (act.low, board view)
RB_MREQ_aval : out slbit; -- rbus: request - aval
RB_MREQ_re : out slbit; -- rbus: request - re
RB_MREQ_we : out slbit; -- rbus: request - we
RB_MREQ_initt : out slbit; -- rbus: request - init; avoid name coll
RB_MREQ_addr : out slv8; -- rbus: request - addr
RB_MREQ_din : out slv16; -- rbus: request - din
RB_SRES_ack : in slbit; -- rbus: response - ack
RB_SRES_busy : in slbit; -- rbus: response - busy
RB_SRES_err : in slbit; -- rbus: response - err
RB_SRES_dout : in slv16; -- rbus: response - dout
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end component;
begin
UUT : tbu_rlink_sp1c
port map (
CLK => CLK,
CE_INT => CE_INT,
CE_USEC => CE_USEC,
CE_MSEC => '1',
RESET => RESET,
RXSD => RRI_RXSD,
TXSD => RRI_TXSD,
CTS_N => '0',
RTS_N => RTS_N,
RB_MREQ_aval => RB_MREQ_aval,
RB_MREQ_re => RB_MREQ_re,
RB_MREQ_we => RB_MREQ_we,
RB_MREQ_initt=> RB_MREQ_initt,
RB_MREQ_addr => RB_MREQ_addr,
RB_MREQ_din => RB_MREQ_din,
RB_SRES_ack => RB_SRES_ack,
RB_SRES_busy => RB_SRES_busy,
RB_SRES_err => RB_SRES_err,
RB_SRES_dout => RB_SRES_dout,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
UARTRX : serport_uart_rx
generic map (
CDWIDTH => CDWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => RRI_TXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => open,
RXACT => RXACT
);
UARTTX : serport_uart_tx
generic map (
CDWIDTH => CDWIDTH)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
TXSD => RRI_RXSD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
TXRXACT <= RXACT or TXBUSY;
B2CD : byte2cdata -- byte stream -> 9bit comma,data
generic map (
CPREF => c_rlink_cpref,
NCOMM => c_rlink_ncomm)
port map (
CLK => CLK,
RESET => RESET,
DI => RXDATA,
ENA => RXVAL,
BUSY => open,
DO => RL_DO,
VAL => RL_VAL,
HOLD => RL_HOLD
);
CD2B : cdata2byte -- 9bit comma,data -> byte stream
generic map (
CPREF => c_rlink_cpref,
NCOMM => c_rlink_ncomm)
port map (
CLK => CLK,
RESET => RESET,
DI => RL_DI,
ENA => RL_ENA,
BUSY => RL_BUSY,
DO => TXDATA,
VAL => TXENA,
HOLD => TXBUSY
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
proc_moni: process
variable oline : line;
variable rts_last : slbit := '0';
variable ncycle : integer := 0;
begin
loop
wait until rising_edge(CLK); -- check at end of clock cycle
if RTS_N /= rts_last then
writetimestamp(oline, CLK_CYCLE, ": rts ");
write(oline, string'(" RTS_N "));
write(oline, rts_last, right, 1);
write(oline, string'(" -> "));
write(oline, RTS_N, right, 1);
write(oline, string'(" after "));
write(oline, ncycle, right, 5);
write(oline, string'(" cycles"));
writeline(output, oline);
rts_last := RTS_N;
ncycle := 0;
end if;
ncycle := ncycle + 1;
end loop;
end process proc_moni;
end syn;
|
gpl-2.0
|
3e1a789b877fc130df801af685e64b88
| 0.5195 | 3.612989 | false | false | false | false |
freecores/w11
|
rtl/vlib/xlib/iob_reg_o.vhd
| 2 | 1,857 |
-- $Id: iob_reg_o.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: iob_reg_i - syn
-- Description: Registered IOB, output only
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-16 101 1.0.1 add INIT generic port
-- 2007-12-08 100 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity iob_reg_o is -- registered IOB, output
generic (
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DO : in slbit; -- output data
PAD : out slbit -- i/o pad
);
end iob_reg_o;
architecture syn of iob_reg_o is
begin
IOB : iob_reg_o_gen
generic map (
DWIDTH => 1,
INIT => INIT)
port map (
CLK => CLK,
CE => CE,
DO(0) => DO,
PAD(0) => PAD
);
end syn;
|
gpl-2.0
|
6ba21d7f514b6ef3aad1c5c25d963fc2
| 0.542811 | 3.759109 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_rlink/s3board/sys_conf.vhd
| 2 | 1,553 |
-- $Id: sys_conf.vhd 442 2011-12-23 10:03:28Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_s3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-22 442 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- derived constants
constant sys_conf_clksys : integer := 50000000;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
|
gpl-2.0
|
297d2a9eec4dded8fd06c54e0a795475
| 0.640695 | 3.951654 | false | false | false | false |
freecores/w11
|
rtl/ibus/ibdr_maxisys.vhd
| 2 | 13,752 |
-- $Id: ibdr_maxisys.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2009-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ibdr_maxisys - syn
-- Description: ibus(rem) devices for full system
--
-- Dependencies: ibd_iist
-- ibd_kw11l
-- ibdr_rk11
-- ibdr_dl11
-- ibdr_pc11
-- ibdr_lp11
-- ibdr_sdreg
-- ib_sres_or_4
-- ib_sres_or_3
-- ib_intmap
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 312 1058 16 617 s 10.3
-- 2010-10-17 314 12.1 M53d xc3s1000-4 300 1094 16 626 s 10.4
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.2 now numeric_std clean
-- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM;
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-07-12 233 1.0.4 reorder ports; add RESET, CE_USEC to _dl11
-- 2009-06-20 227 1.0.3 rename generate labels.
-- 2009-06-07 224 1.0.2 add iist_mreq and iist_sres interfaces
-- 2009-06-01 221 1.0.1 add CE_USEC; add RESET to kw11l; add _pc11, _iist
-- 2009-05-24 219 1.0 Initial version
------------------------------------------------------------------------------
--
--
-- full system setup
--
-- ibbase vec pri slot attn sror device name
--
-- 172540 104 ?7 14 17 - 1/1 KW11-P
-- 177500 260 6 13 16 - 1/2 IIST
-- 177546 100 6 12 15 - 1/3 KW11-L
-- 174510 120 5 14 9 1/4 DEUNA
-- 176700 254 5 13 6 2/1 RH70/RP06
-- 174400 160 5 11 12 5 2/2 RL11
-- 177400 220 5 10 11 4 2/3 RK11
-- 172520 224 5 10 7 2/4 TM11
-- 160100 310? 5 9 9 3 3/1 DZ11-RX
-- 314? 5 8 8 ^ DZ11-TX
-- 177560 060 4 7 7 1 3/2 DL11-RX 1st
-- 064 4 6 6 ^ DL11-TX 1st
-- 176500 300 4 5 5 2 3/3 DL11-RX 2nd
-- 304 4 4 4 ^ DL11-TX 2nd
-- 177550 070 4 3 3 10 4/1 PC11/PTR
-- 074 4 2 2 ^ PC11/PTP
-- 177514 200 4 1 1 8 4/2 LP11
-- 177570 - - - - 4/3 sdreg
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.ibdlib.all;
-- ----------------------------------------------------------------------------
entity ibdr_maxisys is -- ibus(rem) full system
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
CE_MSEC : in slbit; -- msec pulse
RESET : in slbit; -- reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slv16_1; -- remote attention vector
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_ACKM : in slbit; -- interrupt acknowledge (from master)
EI_PRI : out slv3; -- interrupt priority (to cpu)
EI_VECT : out slv9_2; -- interrupt vector (to cpu)
DISPREG : out slv16 -- display register
);
end ibdr_maxisys;
architecture syn of ibdr_maxisys is
constant conf_intmap : intmap_array_type :=
(intmap_init, -- line 15
(8#104#,6), -- line 14 KW11-P
(8#260#,6), -- line 13 IIST
(8#100#,6), -- line 12 KW11-L
(8#160#,5), -- line 11 RL11
(8#220#,5), -- line 10 RK11
(8#310#,5), -- line 9 DZ11-RX
(8#314#,5), -- line 8 DZ11-TX
(8#060#,4), -- line 7 DL11-RX 1st
(8#064#,4), -- line 6 DL11-TX 1st
(8#300#,4), -- line 5 DL11-RX 2nd
(8#304#,4), -- line 4 DL11-TX 2nd
(8#070#,4), -- line 3 PC11-PTR
(8#074#,4), -- line 2 PC11-PTP
(8#200#,4), -- line 1 LP11
intmap_init -- line 0
);
signal RB_LAM_DENUA : slbit := '0';
signal RB_LAM_RP06 : slbit := '0';
signal RB_LAM_RL11 : slbit := '0';
signal RB_LAM_RK11 : slbit := '0';
signal RB_LAM_TM11 : slbit := '0';
signal RB_LAM_DZ11 : slbit := '0';
signal RB_LAM_DL11_0 : slbit := '0';
signal RB_LAM_DL11_1 : slbit := '0';
signal RB_LAM_PC11 : slbit := '0';
signal RB_LAM_LP11 : slbit := '0';
signal IB_SRES_IIST : ib_sres_type := ib_sres_init;
signal IB_SRES_KW11P : ib_sres_type := ib_sres_init;
signal IB_SRES_KW11L : ib_sres_type := ib_sres_init;
signal IB_SRES_DEUNA : ib_sres_type := ib_sres_init;
signal IB_SRES_RP06 : ib_sres_type := ib_sres_init;
signal IB_SRES_RL11 : ib_sres_type := ib_sres_init;
signal IB_SRES_RK11 : ib_sres_type := ib_sres_init;
signal IB_SRES_TM11 : ib_sres_type := ib_sres_init;
signal IB_SRES_DZ11 : ib_sres_type := ib_sres_init;
signal IB_SRES_DL11_0 : ib_sres_type := ib_sres_init;
signal IB_SRES_DL11_1 : ib_sres_type := ib_sres_init;
signal IB_SRES_PC11 : ib_sres_type := ib_sres_init;
signal IB_SRES_LP11 : ib_sres_type := ib_sres_init;
signal IB_SRES_SDREG : ib_sres_type := ib_sres_init;
signal IB_SRES_1 : ib_sres_type := ib_sres_init;
signal IB_SRES_2 : ib_sres_type := ib_sres_init;
signal IB_SRES_3 : ib_sres_type := ib_sres_init;
signal IB_SRES_4 : ib_sres_type := ib_sres_init;
signal EI_REQ : slv16_1 := (others=>'0');
signal EI_ACK : slv16_1 := (others=>'0');
signal EI_REQ_IIST : slbit := '0';
signal EI_REQ_KW11P : slbit := '0';
signal EI_REQ_KW11L : slbit := '0';
signal EI_REQ_DEUNA : slbit := '0';
signal EI_REQ_RP06 : slbit := '0';
signal EI_REQ_RL11 : slbit := '0';
signal EI_REQ_RK11 : slbit := '0';
signal EI_REQ_TM11 : slbit := '0';
signal EI_REQ_DZ11RX : slbit := '0';
signal EI_REQ_DZ11TX : slbit := '0';
signal EI_REQ_DL11RX_0 : slbit := '0';
signal EI_REQ_DL11TX_0 : slbit := '0';
signal EI_REQ_DL11RX_1 : slbit := '0';
signal EI_REQ_DL11TX_1 : slbit := '0';
signal EI_REQ_PC11PTR : slbit := '0';
signal EI_REQ_PC11PTP : slbit := '0';
signal EI_REQ_LP11 : slbit := '0';
signal EI_ACK_IIST : slbit := '0';
signal EI_ACK_KW11P : slbit := '0';
signal EI_ACK_KW11L : slbit := '0';
signal EI_ACK_DEUNA : slbit := '0';
signal EI_ACK_RP06 : slbit := '0';
signal EI_ACK_RL11 : slbit := '0';
signal EI_ACK_RK11 : slbit := '0';
signal EI_ACK_TM11 : slbit := '0';
signal EI_ACK_DZ11RX : slbit := '0';
signal EI_ACK_DZ11TX : slbit := '0';
signal EI_ACK_DL11RX_0 : slbit := '0';
signal EI_ACK_DL11TX_0 : slbit := '0';
signal EI_ACK_DL11RX_1 : slbit := '0';
signal EI_ACK_DL11TX_1 : slbit := '0';
signal EI_ACK_PC11PTR : slbit := '0';
signal EI_ACK_PC11PTP : slbit := '0';
signal EI_ACK_LP11 : slbit := '0';
signal IIST_BUS : iist_bus_type := iist_bus_init;
signal IIST_OUT_0 : iist_line_type := iist_line_init;
signal IIST_MREQ : iist_mreq_type := iist_mreq_init;
signal IIST_SRES : iist_sres_type := iist_sres_init;
begin
IIST: if true generate
begin
I0 : ibd_iist
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
BRESET => BRESET,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IIST,
EI_REQ => EI_REQ_IIST,
EI_ACK => EI_ACK_IIST,
IIST_BUS => IIST_BUS,
IIST_OUT => IIST_OUT_0,
IIST_MREQ => IIST_MREQ,
IIST_SRES => IIST_SRES
);
IIST_BUS(0) <= IIST_OUT_0;
IIST_BUS(1) <= iist_line_init;
IIST_BUS(2) <= iist_line_init;
IIST_BUS(3) <= iist_line_init;
end generate IIST;
KW11L : ibd_kw11l
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
BRESET => BRESET,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_KW11L,
EI_REQ => EI_REQ_KW11L,
EI_ACK => EI_ACK_KW11L
);
RK11: if true generate
begin
I0 : ibdr_rk11
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
BRESET => BRESET,
RB_LAM => RB_LAM_RK11,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_RK11,
EI_REQ => EI_REQ_RK11,
EI_ACK => EI_ACK_RK11
);
end generate RK11;
DL11_0 : ibdr_dl11
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
BRESET => BRESET,
RB_LAM => RB_LAM_DL11_0,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_DL11_0,
EI_REQ_RX => EI_REQ_DL11RX_0,
EI_REQ_TX => EI_REQ_DL11TX_0,
EI_ACK_RX => EI_ACK_DL11RX_0,
EI_ACK_TX => EI_ACK_DL11TX_0
);
DL11_1: if true generate
begin
I0 : ibdr_dl11
generic map (
IB_ADDR => slv(to_unsigned(8#176500#,16)))
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
BRESET => BRESET,
RB_LAM => RB_LAM_DL11_1,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_DL11_1,
EI_REQ_RX => EI_REQ_DL11RX_1,
EI_REQ_TX => EI_REQ_DL11TX_1,
EI_ACK_RX => EI_ACK_DL11RX_1,
EI_ACK_TX => EI_ACK_DL11TX_1
);
end generate DL11_1;
PC11: if true generate
begin
I0 : ibdr_pc11
port map (
CLK => CLK,
RESET => RESET,
BRESET => BRESET,
RB_LAM => RB_LAM_PC11,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_PC11,
EI_REQ_PTR => EI_REQ_PC11PTR,
EI_REQ_PTP => EI_REQ_PC11PTP,
EI_ACK_PTR => EI_ACK_PC11PTR,
EI_ACK_PTP => EI_ACK_PC11PTP
);
end generate PC11;
LP11: if true generate
begin
I0 : ibdr_lp11
port map (
CLK => CLK,
RESET => RESET,
BRESET => BRESET,
RB_LAM => RB_LAM_LP11,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_LP11,
EI_REQ => EI_REQ_LP11,
EI_ACK => EI_ACK_LP11
);
end generate LP11;
SDREG : ibdr_sdreg
port map (
CLK => CLK,
RESET => RESET,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_SDREG,
DISPREG => DISPREG
);
SRES_OR_1 : ib_sres_or_4
port map (
IB_SRES_1 => IB_SRES_KW11P,
IB_SRES_2 => IB_SRES_IIST,
IB_SRES_3 => IB_SRES_KW11L,
IB_SRES_4 => IB_SRES_DEUNA,
IB_SRES_OR => IB_SRES_1
);
SRES_OR_2 : ib_sres_or_4
port map (
IB_SRES_1 => IB_SRES_RP06,
IB_SRES_2 => IB_SRES_RL11,
IB_SRES_3 => IB_SRES_RK11,
IB_SRES_4 => IB_SRES_TM11,
IB_SRES_OR => IB_SRES_2
);
SRES_OR_3 : ib_sres_or_3
port map (
IB_SRES_1 => IB_SRES_DZ11,
IB_SRES_2 => IB_SRES_DL11_0,
IB_SRES_3 => IB_SRES_DL11_1,
IB_SRES_OR => IB_SRES_3
);
SRES_OR_4 : ib_sres_or_3
port map (
IB_SRES_1 => IB_SRES_PC11,
IB_SRES_2 => IB_SRES_LP11,
IB_SRES_3 => IB_SRES_SDREG,
IB_SRES_OR => IB_SRES_4
);
SRES_OR : ib_sres_or_4
port map (
IB_SRES_1 => IB_SRES_1,
IB_SRES_2 => IB_SRES_2,
IB_SRES_3 => IB_SRES_3,
IB_SRES_4 => IB_SRES_4,
IB_SRES_OR => IB_SRES
);
INTMAP : ib_intmap
generic map (
INTMAP => conf_intmap)
port map (
EI_REQ => EI_REQ,
EI_ACKM => EI_ACKM,
EI_ACK => EI_ACK,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT
);
EI_REQ(14) <= EI_REQ_KW11P;
EI_REQ(13) <= EI_REQ_IIST;
EI_REQ(12) <= EI_REQ_KW11L;
EI_REQ(11) <= EI_REQ_RL11;
EI_REQ(10) <= EI_REQ_RK11;
EI_REQ( 9) <= EI_REQ_DZ11RX;
EI_REQ( 8) <= EI_REQ_DZ11TX;
EI_REQ( 7) <= EI_REQ_DL11RX_0;
EI_REQ( 6) <= EI_REQ_DL11TX_0;
EI_REQ( 5) <= EI_REQ_DL11RX_1;
EI_REQ( 4) <= EI_REQ_DL11TX_1;
EI_REQ( 3) <= EI_REQ_PC11PTR;
EI_REQ( 2) <= EI_REQ_PC11PTP;
EI_REQ( 1) <= EI_REQ_LP11;
EI_ACK_KW11P <= EI_ACK(14);
EI_ACK_IIST <= EI_ACK(13);
EI_ACK_KW11L <= EI_ACK(12);
EI_ACK_RL11 <= EI_ACK(11);
EI_ACK_RK11 <= EI_ACK(10);
EI_ACK_DZ11RX <= EI_ACK( 9);
EI_ACK_DZ11TX <= EI_ACK( 8);
EI_ACK_DL11RX_0 <= EI_ACK( 7);
EI_ACK_DL11TX_0 <= EI_ACK( 6);
EI_ACK_DL11RX_1 <= EI_ACK( 5);
EI_ACK_DL11TX_1 <= EI_ACK( 4);
EI_ACK_PC11PTR <= EI_ACK( 3);
EI_ACK_PC11PTP <= EI_ACK( 2);
EI_ACK_LP11 <= EI_ACK( 1);
RB_LAM(15 downto 11) <= (others=>'0');
RB_LAM(10) <= RB_LAM_PC11;
RB_LAM( 9) <= RB_LAM_DENUA;
RB_LAM( 8) <= RB_LAM_LP11;
RB_LAM( 7) <= RB_LAM_TM11;
RB_LAM( 6) <= RB_LAM_RP06;
RB_LAM( 5) <= RB_LAM_RL11;
RB_LAM( 4) <= RB_LAM_RK11;
RB_LAM( 3) <= RB_LAM_DZ11;
RB_LAM( 2) <= RB_LAM_DL11_1;
RB_LAM( 1) <= RB_LAM_DL11_0;
end syn;
|
gpl-2.0
|
9646bb0a7e0c665775b0cf884259a4f1
| 0.500218 | 2.804813 | false | false | false | false |
freecores/w11
|
rtl/vlib/xlib/s6_cmt_sfs_unisim.vhd
| 1 | 4,645 |
-- $Id: $
--
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: s6_cmt_sfs - syn
-- Description: Spartan-6 CMT for simple frequency synthesis
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan-6
-- Tool versions: xst 14.5; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-05 537 1.0 Initial version (derived from s7_cmt_sfs)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
entity s6_cmt_sfs is -- Spartan-6 CMT for simple freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT_DIVIDE : positive := 1; -- output divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or DCM
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- pll/dcm locked
);
end s6_cmt_sfs;
architecture syn of s6_cmt_sfs is
begin
assert GEN_TYPE = "PLL" or GEN_TYPE = "DCM"
report "assert(GEN_TYPE='PLL' or GEN_TYPE='DCM')"
severity failure;
NOGEN: if VCO_DIVIDE=1 and VCO_MULTIPLY=1 and OUT_DIVIDE=1 generate
CLKFX <= CLKIN;
LOCKED <= '1';
end generate NOGEN;
USEPLL: if GEN_TYPE = "PLL" and
not(VCO_DIVIDE=1 and VCO_MULTIPLY=1 and OUT_DIVIDE=1) generate
signal CLKFBOUT : slbit;
signal CLKOUT0 : slbit;
signal CLKOUT1_UNUSED : slbit;
signal CLKOUT2_UNUSED : slbit;
signal CLKOUT3_UNUSED : slbit;
signal CLKOUT4_UNUSED : slbit;
signal CLKOUT5_UNUSED : slbit;
begin
PLL : pll_base
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => VCO_DIVIDE,
CLKFBOUT_MULT => VCO_MULTIPLY,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => OUT_DIVIDE,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => CLKIN_PERIOD,
REF_JITTER => CLKIN_JITTER)
port map (
CLKFBOUT => CLKFBOUT,
CLKOUT0 => CLKOUT0,
CLKOUT1 => CLKOUT1_UNUSED,
CLKOUT2 => CLKOUT2_UNUSED,
CLKOUT3 => CLKOUT3_UNUSED,
CLKOUT4 => CLKOUT4_UNUSED,
CLKOUT5 => CLKOUT5_UNUSED,
CLKFBIN => CLKFBOUT,
CLKIN => CLKIN,
LOCKED => LOCKED,
RST => '0'
);
BUFG_CLKOUT : bufg
port map (
I => CLKOUT0,
O => CLKFX
);
end generate USEPLL;
USEDCM: if GEN_TYPE = "DCM" and
not(VCO_DIVIDE=1 and VCO_MULTIPLY=1 and OUT_DIVIDE=1) generate
signal CLKOUT0 : slbit;
begin
DCM : dcm_sp
generic map (
CLK_FEEDBACK => "NONE",
CLKFX_DIVIDE => VCO_DIVIDE,
CLKFX_MULTIPLY => VCO_MULTIPLY,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => CLKIN_PERIOD,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DSS_MODE => "NONE",
STARTUP_WAIT => STARTUP_WAIT)
port map (
CLKIN => CLKIN,
CLKFX => CLKOUT0,
LOCKED => LOCKED
);
BUFG_CLKOUT : bufg
port map (
I => CLKOUT0,
O => CLKFX
);
end generate USEDCM;
end syn;
|
gpl-2.0
|
ad292de72d14efdfbd2a7547b97c4c70
| 0.530463 | 4.117908 | false | false | false | false |
freecores/w11
|
rtl/bplib/s3board/tb/tb_s3board_core.vhd
| 1 | 3,259 |
-- $Id: tb_s3board_core.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_s3board_core - sim
-- Description: Test bench for s3board - core device handling
--
-- Dependencies: vlib/parts/issi/is61lv25616al
--
-- To test: generic, any s3board target
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.2 now numeric_std clean
-- 2010-05-02 287 1.0.1 add sbaddr_(swi|btn) defs, now sbus addr 16,17
-- 2010-04-24 282 1.0 Initial version (from vlib/s3board/tb/tb_s3board)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.simbus.all;
entity tb_s3board_core is
port (
I_SWI : out slv8; -- s3 switches
I_BTN : out slv4; -- s3 buttons
O_MEM_CE_N : in slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : in slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : in slbit; -- sram: write enable (act.low)
O_MEM_OE_N : in slbit; -- sram: output enable (act.low)
O_MEM_ADDR : in slv18; -- sram: address lines
IO_MEM_DATA : inout slv32 -- sram: data lines
);
end tb_s3board_core;
architecture sim of tb_s3board_core is
signal R_SWI : slv8 := (others=>'0');
signal R_BTN : slv4 := (others=>'0');
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin
MEM_L : entity work.is61lv25616al
port map (
CE_N => O_MEM_CE_N(0),
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA(15 downto 0)
);
MEM_U : entity work.is61lv25616al
port map (
CE_N => O_MEM_CE_N(1),
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(3),
LB_N => O_MEM_BE_N(2),
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA(31 downto 16)
);
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
end sim;
|
gpl-2.0
|
fc43ff36639b5b022cbb97834658cf71
| 0.5695 | 3.077432 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/tst_serloop/tst_serloop_hiomap.vhd
| 1 | 7,321 |
-- $Id: tst_serloop_hiomap.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tst_serloop_hiomap - syn
-- Description: default human I/O mapper
--
-- Dependencies: -
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-09 437 1.0.2 rename serport stat->moni port
-- 2011-11-16 426 1.0.1 setup leds and dps
-- 2011-11-05 420 1.0 Initial version
------------------------------------------------------------------------------
--
-- Usage of Switches, Buttons, LEDs:
--
-- BTN(3): -- unused --
-- (2): -- unused --
-- (1): load enables from SWI(7:4)
-- SWI(7) -> ENAFTDI
-- SWI(6) -> ENATHROTTLE
-- SWI(5) -> ENAESC
-- SWI(4) -> ENAXON
-- (0): reset state [!! decoded by top level design !!]
--
-- SWI(7:4) select display or enable pattern (when BTN(1) pressed)
-- (3) -- unused --
-- (2:1): mode 00 idle
-- 01 rxblast
-- 10 txblast
-- 11 loop
-- SWI(0) 0 -> main board RS232 port
-- 1 -> Pmod1 RS232 port
--
-- LED(7) enaesc
-- (6) enaxon
-- (5) rxfecnt > 0 (frame error)
-- (4) rxoecnt > 0 (overrun error)
-- (3) rxsecnt > 0 (sequence error)
-- (2) abact (shows ab activity)
-- (1) (not rxok) or (not txok) (shows back preasure)
-- (0) rxact or txact (shows activity)
--
-- DSP data as selected by SWI(7:4)
-- 0000 -> rxfecnt
-- 0001 -> rxoecnt
-- 0010 -> rxsecnt
-- 0100 -> rxcnt.l
-- 0101 -> rxcnt.h
-- 0110 -> txcnt.l
-- 0111 -> txcnt.h
-- 1000 -> rxokcnt
-- 1001 -> txokcnt
-- 1010 -> rxuicnt,rxuidat
-- 1111 -> abclkdiv
--
-- DP(3): not SER_MONI.txok (shows tx back preasure)
-- (2): SER_MONI.txact (shows tx activity)
-- (1): not SER_MONI.rxok (shows rx back preasure)
-- (0): SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.tst_serlooplib.all;
-- ----------------------------------------------------------------------------
entity tst_serloop_hiomap is -- default human I/O mapper
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
HIO_CNTL : out hio_cntl_type; -- tester controls from hio
HIO_STAT : in hio_stat_type; -- tester status to diaplay by hio
SER_MONI : in serport_moni_type; -- serport monitor to display by hio
SWI : in slv8; -- switch settings
BTN : in slv4; -- button settings
LED : out slv8; -- led data
DSP_DAT : out slv16; -- display data
DSP_DP : out slv4 -- display decimal points
);
end tst_serloop_hiomap;
architecture syn of tst_serloop_hiomap is
type regs_type is record
enaxon : slbit; -- enable xon/xoff handling
enaesc : slbit; -- enable xon/xoff escaping
enathrottle : slbit; -- enable 1 msec tx throttling
enaftdi : slbit; -- enable ftdi flush handling
dspdat : slv16; -- display data
end record regs_type;
constant regs_init : regs_type := (
'0','0','0','0', -- enaxon,enaesc,enathrottle,enaftdi
(others=>'0') -- dspdat
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, HIO_STAT, SER_MONI, SWI, BTN)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable icntl : hio_cntl_type := hio_cntl_init;
variable iled : slv8 := (others=>'0');
variable idat : slv16 := (others=>'0');
variable idp : slv4 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
icntl := hio_cntl_init;
iled := (others=>'0');
idat := (others=>'0');
idp := (others=>'0');
-- handle BTN(1) "load enables" press
if BTN(1) = '1' then
n.enaxon := SWI(4);
n.enaesc := SWI(5);
n.enathrottle := SWI(6);
n.enaftdi := SWI(7);
end if;
-- setup tester controls
icntl.mode := SWI(2 downto 1);
icntl.enaxon := r.enaxon;
icntl.enaesc := r.enaesc;
icntl.enathrottle := r.enathrottle;
icntl.enaftdi := r.enaftdi;
-- setup leds
iled(7) := icntl.enaesc;
iled(6) := icntl.enaxon;
if unsigned(HIO_STAT.rxfecnt) > 0 then iled(5) := '1'; end if;
if unsigned(HIO_STAT.rxoecnt) > 0 then iled(4) := '1'; end if;
if unsigned(HIO_STAT.rxsecnt) > 0 then iled(3) := '1'; end if;
iled(2) := SER_MONI.abact;
iled(1) := (not SER_MONI.rxok) or (not SER_MONI.txok);
iled(0) := SER_MONI.rxact or SER_MONI.txact;
-- setup display data
case SWI(7 downto 4) is
when "0000" => idat := HIO_STAT.rxfecnt;
when "0001" => idat := HIO_STAT.rxoecnt;
when "0010" => idat := HIO_STAT.rxsecnt;
when "0100" => idat := HIO_STAT.rxcnt(15 downto 0);
when "0101" => idat := HIO_STAT.rxcnt(31 downto 16);
when "0110" => idat := HIO_STAT.txcnt(15 downto 0);
when "0111" => idat := HIO_STAT.txcnt(31 downto 16);
when "1000" => idat := HIO_STAT.rxokcnt;
when "1001" => idat := HIO_STAT.txokcnt;
when "1010" => idat := HIO_STAT.rxuicnt & HIO_STAT.rxuidat;
when "1111" => idat := SER_MONI.abclkdiv;
when others => null;
end case;
n.dspdat := idat;
-- setup display decimal points
idp(3) := not SER_MONI.txok; -- tx back preasure
idp(2) := SER_MONI.txact; -- tx activity
idp(1) := not SER_MONI.rxok; -- rx back preasure
idp(0) := SER_MONI.rxact; -- rx activity
N_REGS <= n;
HIO_CNTL <= icntl;
LED <= iled;
DSP_DAT <= r.dspdat;
DSP_DP <= idp;
end process proc_next;
end syn;
|
gpl-2.0
|
c1b091218da1a58d22ccdd3eb66a0402
| 0.509493 | 3.664164 | false | false | false | false |
freecores/w11
|
rtl/vlib/xlib/iob_reg_io_gen.vhd
| 2 | 4,120 |
-- $Id: iob_reg_io_gen.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2008 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: iob_reg_io_gen - syn
-- Description: Registered IOB, in/output, vector
--
-- Dependencies: iob_keeper_gen [sim only]
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2008-05-22 149 1.0.4 use internally TE to match OBUFT T polarity
-- 2008-05-22 148 1.0.3 remove UNISIM prim's; PULL implemented only for sim
-- 2008-05-18 147 1.0.2 add PULL generic, to enable PULL-UP,-DOWN or KEEPER
-- 2007-12-16 101 1.0.1 add INIT generic ports
-- 2007-12-08 100 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity iob_reg_io_gen is -- registered IOB, in/output, vector
generic (
DWIDTH : positive := 16; -- data port width
INITI : slbit := '0'; -- initial state ( in flop)
INITO : slbit := '0'; -- initial state (out flop)
INITE : slbit := '0'; -- initial state ( oe flop)
PULL : string := "NONE"); -- pull-up,-down or keeper
port (
CLK : in slbit; -- clock
CEI : in slbit := '1'; -- clock enable ( in flops)
CEO : in slbit := '1'; -- clock enable (out flops)
OE : in slbit; -- output enable
DI : out slv(DWIDTH-1 downto 0); -- input data (read from pad)
DO : in slv(DWIDTH-1 downto 0); -- output data (write to pad)
PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
);
end iob_reg_io_gen;
architecture syn of iob_reg_io_gen is
signal R_TE : slbit := not INITE;
signal R_DI : slv(DWIDTH-1 downto 0) := (others=>INITI);
signal R_DO : slv(DWIDTH-1 downto 0) := (others=>INITO);
constant all_z : slv(DWIDTH-1 downto 0) := (others=>'Z');
constant all_l : slv(DWIDTH-1 downto 0) := (others=>'L');
constant all_h : slv(DWIDTH-1 downto 0) := (others=>'H');
attribute iob : string;
attribute iob of R_TE : signal is "true";
attribute iob of R_DI : signal is "true";
attribute iob of R_DO : signal is "true";
begin
assert PULL="NONE" or PULL="UP" or PULL="DOWN" or PULL="KEEP"
report "assert(PULL): only NONE, UP, DOWN, OR KEEP supported"
severity failure;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
R_TE <= not OE;
if CEI = '1' then
R_DI <= to_x01(PAD);
end if;
if CEO = '1' then
R_DO <= DO;
end if;
end if;
end process proc_regs;
proc_comb: process (R_TE, R_DO)
begin
if R_TE = '1' then
PAD <= all_z;
else
PAD <= R_DO;
end if;
end process proc_comb;
DI <= R_DI;
-- Note: PULL (UP, DOWN or KEEP) is only implemented for simulation, not
-- for inference in synthesis. Use pin attributes in UCF's or use
-- iob_reg_io_gen_unisim
--
-- synthesis translate_off
PULL_UP: if PULL = "UP" generate
PAD <= all_h;
end generate PULL_UP;
PULL_DOWN: if PULL = "DOWN" generate
PAD <= all_l;
end generate PULL_DOWN;
PULL_KEEP: if PULL = "KEEP" generate
KEEPER : iob_keeper_gen
generic map (DWIDTH => DWIDTH)
port map (PAD => PAD);
end generate PULL_KEEP;
-- synthesis translate_on
end syn;
|
gpl-2.0
|
6bd7d6399041ae119e0b32e7f576be48
| 0.580097 | 3.456376 | false | false | false | false |
superboy0712/MIPS
|
pipeline files/MEMWB_register.vhd
| 1 | 1,883 |
library ieee;
use ieee.std_logic_1164.all;
entity EXMEM_register is
port(Clk, reset : in std_logic;
ALU_ressult_i, data_mem_i: in std_logic_vector(31 downto 0);
ALU_ressult_o, data_mem_o: out std_logic_vector(31 downto 0);
register_address_i: in std_logic_vector(4 downto 0);
register_address_o: out std_logic_vector(4 downto 0);
MemtoReg_i, RegWrite_i: in std_logic;
MemtoReg_o, RegWrite_o: out std_logic);
end EXMEM_register;
architecture EXMEM_register_a of EXMEM_register is
type tmp_array is array (0 to 1) of std_logic_vector(31 downto 0);
type tmp_array_short is array (0 to 1) of std_logic_vector(4 downto 0);
type tmp_array_logic is array (0 to 1) of std_logic;
signal data_mem_tmp, ALU_ressult_tmp: tmp_array;
signal register_address_tmp: tmp_array_short;
signal MemtoReg_tmp, RegWrite_tmp: tmp_array_logic;
begin
process (Clk)
begin
if (reset = '1') then
data_mem_tmp(1) <= (others => '0');
register_address_tmp(1) <= (others => '0');
ALU_ressult_tmp(1) <= (others => '0');
MemtoReg_tmp(1) <= '0';
RegWrite_tmp(1) <= '0';
elsif (rising_edge(clk)) then
data_mem_tmp(0) <= data_mem_tmp(1);
register_address_tmp(0) <= register_address_tmp(1);
ALU_ressult_tmp(0) <= ALU_ressult_tmp(1);
MemtoReg_tmp(0) <= MemtoReg_tmp(1);
RegWrite_tmp(0) <= RegWrite_tmp(1);
data_mem_tmp(1) <= data_mem_i;
register_address_tmp(1) <= register_address_i;
ALU_ressult_tmp(1) <= ALU_ressult_i;
MemtoReg_tmp(1) <= MemtoReg_i;
RegWrite_tmp(1) <= RegWrite_i;
end if;
end process;
data_mem_o <= data_mem_tmp(0);
register_address_o <= register_address_tmp(0);
ALU_ressult_o <= ALU_ressult_tmp(0);
MemtoReg_o <= MemtoReg_tmp(0);
RegWrite_o <= RegWrite_tmp(0);
end EXMEM_register_a;
|
mit
|
b60c9b61f66f8fb8fd795c78cdebc619
| 0.621349 | 2.85303 | false | false | false | false |
freecores/w11
|
rtl/ibus/iblib.vhd
| 2 | 6,144 |
-- $Id: iblib.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: iblib
-- Description: Definitions for ibus interface and bus entities
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 2.0.1 add ib_sel; add ib_sres_or_mon
-- 2010-10-17 333 2.0 ibus V2 interface: use aval,re,we,rmw
-- 2010-06-11 303 1.1 added racc,cacc signals to ib_mreq_type
-- 2009-06-01 221 1.0.1 added dip signal to ib_mreq_type
-- 2008-08-22 161 1.0 Initial version (extracted from pdp11.vhd)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package iblib is
type ib_mreq_type is record -- ibus - master request
aval : slbit; -- address valid
re : slbit; -- read enable
we : slbit; -- write enable
rmw : slbit; -- read-modify-write
be0 : slbit; -- byte enable low
be1 : slbit; -- byte enable high
cacc : slbit; -- console access
racc : slbit; -- remote access
addr : slv13_1; -- address bit(12:1)
din : slv16; -- data (input to slave)
end record ib_mreq_type;
constant ib_mreq_init : ib_mreq_type :=
('0','0','0','0', -- aval, re, we, rmw
'0','0','0','0', -- be0, be1, cacc, racc
(others=>'0'), -- addr
(others=>'0')); -- din
type ib_sres_type is record -- ibus - slave response
ack : slbit; -- acknowledge
busy : slbit; -- busy
dout : slv16; -- data (output from slave)
end record ib_sres_type;
constant ib_sres_init : ib_sres_type :=
('0','0', -- ack, busy
(others=>'0')); -- dout
type ib_sres_vector is array (natural range <>) of ib_sres_type;
subtype ibf_byte1 is integer range 15 downto 8;
subtype ibf_byte0 is integer range 7 downto 0;
component ib_sel is -- ibus address select logic
generic (
IB_ADDR : slv16; -- ibus address base
SAWIDTH : natural := 0); -- device subaddress space width
port (
CLK : in slbit; -- clock
IB_MREQ : in ib_mreq_type; -- ibus request
SEL : out slbit -- select state bit
);
end component;
component ib_sres_or_2 is -- ibus result or, 2 input
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output
);
end component;
component ib_sres_or_3 is -- ibus result or, 3 input
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output
);
end component;
component ib_sres_or_4 is -- ibus result or, 4 input
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
IB_SRES_4 : in ib_sres_type := ib_sres_init; -- ib_sres input 4
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output
);
end component;
component ib_sres_or_gen is -- ibus result or, generic
generic (
WIDTH : natural := 4); -- number of input ports
port (
IB_SRES_IN : in ib_sres_vector(1 to WIDTH); -- ib_sres input array
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output
);
end component;
type intmap_type is record -- interrupt map entry type
vec : integer; -- vector address
pri : integer; -- priority
end record intmap_type;
constant intmap_init : intmap_type := (0,0);
type intmap_array_type is array (15 downto 0) of intmap_type;
constant intmap_array_init : intmap_array_type := (others=>intmap_init);
component ib_intmap is -- external interrupt mapper
generic (
INTMAP : intmap_array_type := intmap_array_init);
port (
EI_REQ : in slv16_1; -- interrupt request lines
EI_ACKM : in slbit; -- interrupt acknowledge (from master)
EI_ACK : out slv16_1; -- interrupt acknowledge (to requestor)
EI_PRI : out slv3; -- interrupt priority
EI_VECT : out slv9_2 -- interrupt vector
);
end component;
--
-- components for use in test benches (not synthesizable)
--
component ib_sres_or_mon is -- ibus result or monitor
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
IB_SRES_4 : in ib_sres_type := ib_sres_init -- ib_sres input 4
);
end component;
end package iblib;
|
gpl-2.0
|
9fc81528e925dd68fe8f5f23d43ae337
| 0.536784 | 3.683453 | false | false | false | false |
palbicoc/AUX_Bus
|
AUX_bus.srcs/sim_1/new/vme64x_top_tb.vhd
| 1 | 34,606 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13.01.2016 14:56:57
-- Design Name:
-- Module Name: vme64x_top_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- librerie per simulazione vme64x ...
library work;
use work.VME64xSim.all;
use work.VME64x.all;
-- vme64x che non servono per la simulazione
-- use work.VME_CR_pack.all;
-- use work.VME_CSR_pack.all;
-- use work.wishbone_pkg.all;
-- use work.vme64x_pack.all;
library std;
use std.textio.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity vme64x_top_tb is
end vme64x_top_tb;
architecture AUX_Behavioral of vme64x_top_tb is
-- Component Declaration of UUT
COMPONENT VME64x_top
PORT (
clk_p : in STD_LOGIC;
clk_n : in STD_LOGIC;
-- Segnali Bus VME
VME_sysres_n : in STD_LOGIC;
VME_data : inout STD_LOGIC_VECTOR (31 downto 0); -- ALSO AUX
VME_dataOE : out STD_LOGIC;
VME_data_DIR : out STD_LOGIC;
VME_DSy : in STD_LOGIC_VECTOR (1 downto 0);
VME_addr : inout STD_LOGIC_VECTOR (31 downto 1);
VME_addrOE : out STD_LOGIC;
VME_addr_DIR : out STD_LOGIC;
VME_WRITEy : in STD_LOGIC;
VME_LWordy : inout STD_LOGIC;
VME_oeabBERR : out STD_LOGIC;
VME_oeabDTACK : out STD_LOGIC;
VME_DTACKa : out STD_LOGIC;
VME_ASy : in STD_LOGIC;
VME_IACKy : in STD_LOGIC;
VME_IACKINy : in std_logic;
VME_IACKOUTa : out std_logic;
VME_oeabRETRY : out STD_LOGIC;
VME_RETRYa : out STD_LOGIC;
VME_am : in STD_LOGIC_VECTOR (5 downto 0);
VME_switch : in STD_LOGIC_VECTOR (7 downto 0);
VME_irq : out STD_LOGIC_VECTOR (7 downto 1);
VME_ga_n : in STD_LOGIC_VECTOR (4 downto 0);
VME_gap_n : in STD_LOGIC;
VME_sysclk : in STD_LOGIC;
VME_statrd_n : out STD_LOGIC;
-- Segnali Bus AUX
AUX_xsel_n : out STD_LOGIC;
AUX_xsds_n : out STD_LOGIC;
AUX_xeob_n : out STD_LOGIC;
AUX_xdk_n : out STD_LOGIC;
AUX_xbusy : out STD_LOGIC;
AUX_xbk_n : out STD_LOGIC;
AUX_xberr : out STD_LOGIC;
AUX_xds_n : in STD_LOGIC;
AUX_on_n : out STD_LOGIC;
AUX_xtrig : in STD_LOGIC_VECTOR (3 downto 0);
AUX_xas_n : in STD_LOGIC;
AUX_xtrgv_n : in STD_LOGIC;
AUX_xsyncrd_n : in STD_LOGIC;
AUX_xa_sel : in STD_LOGIC;
Led_red : out STD_LOGIC_VECTOR (2 downto 0);
Led_yellow : out STD_LOGIC_VECTOR (2 downto 0)
);
END COMPONENT;
-- Generic
-- Constant xxx
-- UUT BiDirs
signal VME_data : STD_LOGIC_VECTOR (31 downto 0);
signal VME_addr : STD_LOGIC_VECTOR (31 downto 0);
-- UUT Inputs ( := )
signal clk_p : STD_LOGIC := '0';
signal clk_n : STD_LOGIC := '1';
signal VME_sysres_n : STD_LOGIC;
signal VME_DSy : STD_LOGIC_VECTOR (1 downto 0);
signal VME_WRITEy : STD_LOGIC;
-- alias VME_LWordy : STD_LOGIC IS VME_addr(0);
signal VME_ASy : STD_LOGIC;
signal VME_IACKy : STD_LOGIC;
signal VME_am : STD_LOGIC_VECTOR (5 downto 0);
signal VME_switch : STD_LOGIC_VECTOR (7 downto 0) := BA;
signal VME_ga_n : STD_LOGIC_VECTOR (4 downto 0) := "11111"; -- simulo old vme bus := VME_GA(4 downto 0);
signal VME_gap_n : STD_LOGIC := '1'; -- simulo old vme bus := VME_GA(5);
signal VME_sysclk : STD_LOGIC;
signal AUX_xds_n : STD_LOGIC;
signal AUX_xtrig : STD_LOGIC_VECTOR (3 downto 0);
signal AUX_xas_n : STD_LOGIC;
signal AUX_xtrgv_n : STD_LOGIC;
signal AUX_xsyncrd_n : STD_LOGIC;
signal AUX_xa_sel : STD_LOGIC;
-- UUT Outputs
signal VME_dataOE : STD_LOGIC;
signal VME_data_DIR : STD_LOGIC;
signal VME_addrOE : STD_LOGIC;
signal VME_addr_DIR : STD_LOGIC;
signal VME_oeabBERR : STD_LOGIC;
signal VME_oeabDTACK : STD_LOGIC;
signal VME_DTACKa : STD_LOGIC;
signal VME_oeabRETRY : STD_LOGIC;
signal VME_RETRYa : STD_LOGIC;
signal VME_irq : STD_LOGIC_VECTOR (7 downto 1);
signal VME_statrd_n : STD_LOGIC;
signal AUX_xsel_n : STD_LOGIC;
signal AUX_xsds_n : STD_LOGIC;
signal AUX_xeob_n : STD_LOGIC;
signal AUX_xdk_n : STD_LOGIC;
signal AUX_xbusy : STD_LOGIC;
signal AUX_xbk_n : STD_LOGIC;
signal AUX_xberr : STD_LOGIC;
signal AUX_on_n : STD_LOGIC;
signal Led_red : STD_LOGIC_VECTOR (2 downto 0);
signal Led_yellow : STD_LOGIC_VECTOR (2 downto 0);
-- Others signal
signal VME_IACKINy : STD_LOGIC;
signal VME_IACKOUTa : STD_LOGIC;
-- Flags
signal ReadInProgress : std_logic := '0';
signal WriteInProgress : std_logic := '0';
-- Buffer and type
signal s_Buffer_BLT : t_Buffer_BLT;
signal s_Buffer_MBLT : t_Buffer_MBLT;
signal s_dataTransferType : t_dataTransferType;
signal s_AddressingType : t_Addressing_Type;
-- Control signals
signal s_dataToSend : std_logic_vector(31 downto 0) := (others => '0');
signal s_dataToReceive : std_logic_vector(31 downto 0) := (others => '0');
signal s_address : std_logic_vector(63 downto 0) := (others => '0');
signal csr_address : std_logic_vector(19 downto 0) := (others => '0');
signal s_num : std_logic_vector( 8 downto 0) := (others => '0');
-- Records
signal VME64xBus_out : VME64xBusOut_Record := VME64xBusOut_Default;
signal VME64xBus_in : VME64xBusIn_Record;
-- BUS VME testbench signal
signal BUS_DATA : STD_LOGIC_VECTOR (31 downto 0) :=(others => '1');
signal BUS_ADDR : STD_LOGIC_VECTOR (31 downto 0) :=(others => '1');
-- alias BUS_LWORD_n : STD_LOGIC IS BUS_ADDR(0);
signal BUS_DS_n : STD_LOGIC_VECTOR ( 1 downto 0) :=(others => '1');
signal BUS_AM : STD_LOGIC_VECTOR ( 5 downto 0) :=(others => '1');
signal BUS_SYSRES_n : STD_LOGIC := '1';
signal BUS_SYSCLK : STD_LOGIC := '1';
signal BUS_AS_n : STD_LOGIC := '1';
signal BUS_IACK_n : STD_LOGIC := '1';
signal BUS_IACKIN_n : STD_LOGIC := '1';
signal BUS_IACKOUT_n : STD_LOGIC; --out
signal BUS_DTACK_n : STD_LOGIC; --out
signal BUS_WRITE_n : STD_LOGIC := '1';
signal BUS_RETRY_n : STD_LOGIC; --out
signal BUS_BERR_n : STD_LOGIC; --out
signal BUS_IRQ : STD_LOGIC_VECTOR ( 7 downto 1); --out
-- BUS AUX testbench signal
signal BUS_XD : STD_LOGIC_VECTOR (19 downto 0); -- out
signal BUS_XT : STD_LOGIC_VECTOR (11 downto 0) :=(others => '1');
signal BUS_XSDS_n : STD_LOGIC; --out
signal BUS_XAS_n : STD_LOGIC := '1';
signal BUS_XTRGV_n : STD_LOGIC := '1';
signal BUS_XDS_n : STD_LOGIC := '1';
signal BUS_XSYNCRD_n : STD_LOGIC := '1';
signal BUS_XDK_n : STD_LOGIC := '1';
signal BUS_XEOB_n : STD_LOGIC := '1';
signal BUS_XA_SEL : STD_LOGIC := '1';
signal BUS_XBK : STD_LOGIC; --out
signal BUS_XBUSY_n : STD_LOGIC; --out
signal BUS_XBERR_n : STD_LOGIC; --out
signal BUS_XT1 : STD_LOGIC := '0';
signal BUS_XT2 : STD_LOGIC := '0';
signal BUS_XRES : STD_LOGIC := '0';
signal BUS_XCLK : STD_LOGIC := '0';
signal STAT_REG : STD_LOGIC_VECTOR (7 downto 0);
-- Other Components
COMPONENT sn74vme
GENERIC ( NUMOFBIT : integer);
PORT(
I1OEAB : in STD_LOGIC;
I1A : in STD_LOGIC;
I1Y : out STD_LOGIC;
O1B : inout STD_LOGIC;
I2OEAB : in STD_LOGIC;
I2A : in STD_LOGIC;
I2Y : out STD_LOGIC;
O2B : inout STD_LOGIC;
OEn : in STD_LOGIC;
DIR : in STD_LOGIC;
I3A : inout STD_LOGIC_VECTOR (NUMOFBIT - 1 downto 0);
O3B : inout STD_LOGIC_VECTOR (NUMOFBIT - 1 downto 0)
);
END COMPONENT;
-- ram block ...
-- Clock period definitions
constant CLK_period : time := 5 ns; -- 200 MHz
-- constant definition
-- procedure declaration
--------------------
-- PRBS_ANY
--------------------
component PRBS_ANY
generic (
-- out alp:
--CHK_MODE: boolean := false;
INV_PATTERN : boolean := false;
POLY_LENGHT : natural range 0 to 63 := 31;
POLY_TAP : natural range 0 to 63 := 3;
NBITS : natural range 0 to 512 := 22
);
port (
-- in alp:
CHK_MODE : in std_logic;
RST : in std_logic; -- sync reset active high
CLK : in std_logic; -- system clock
DATA_IN : in std_logic_vector(NBITS - 1 downto 0); -- inject error/data to be checked
EN : in std_logic; -- enable/pause pattern generation
DATA_OUT : out std_logic_vector(NBITS - 1 downto 0) -- generated prbs pattern/errors found
);
end component;
--------------------
-- PRBS_ANY
--------------------
-- PRBS-15 Settings
constant A_INV_PATTERN : boolean := true;
constant B_INV_PATTERN : boolean := false;
constant POLY_LENGHT : natural range 0 to 63 := 15;
constant POLY_TAP : natural range 0 to 63 := 14;
--------------------
-- CHECK RX DATA
--------------------
signal a_data : std_logic_vector(11 downto 0) := (others => '0');
signal a_valid : std_logic := '0';
signal a_data_check : std_logic_vector(11 downto 0) := (others => '0');
signal a_clk : std_logic := '1';
signal b_data : std_logic_vector(11 downto 0) := (others => '0');
signal b_valid : std_logic := '0';
signal b_data_check : std_logic_vector(11 downto 0) := (others => '0');
signal b_clk : std_logic := '1';
--------------------
-- AUXBUS STIMULI
--------------------
signal rst : std_logic := '1';
signal trigger : std_logic := '0';
signal trig_num : integer := 0;
signal founddata : std_logic := '0';
signal rx_data : std_logic_vector(19 downto 0) := (others => '0');
begin
-- Instantiate the Unit Under Test (UUT)
uut: VME64x_top
PORT MAP (
clk_p => clk_p,
clk_n => clk_n,
VME_sysres_n => VME_sysres_n,
VME_data => VME_data,
VME_dataOE => VME_dataOE,
VME_data_DIR => VME_data_DIR,
VME_DSy => VME_DSy,
VME_addr => VME_addr(31 downto 1),
VME_addrOE => VME_addrOE,
VME_addr_DIR => VME_addr_DIR,
VME_WRITEy => VME_WRITEy,
VME_LWordy => VME_addr(0),
VME_oeabBERR => VME_oeabBERR,
VME_oeabDTACK => VME_oeabDTACK,
VME_DTACKa => VME_DTACKa,
VME_ASy => VME_ASy,
VME_IACKy => VME_IACKy,
VME_IACKINy => VME_IACKINy,
VME_IACKOUTa => VME_IACKOUTa,
VME_oeabRETRY => VME_oeabRETRY,
VME_RETRYa => VME_RETRYa,
VME_am => VME_am,
VME_switch => VME_switch,
VME_irq => VME_irq,
VME_ga_n => VME_ga_n,
VME_gap_n => VME_gap_n,
VME_sysclk => VME_sysclk,
VME_statrd_n => VME_statrd_n,
AUX_xsel_n => AUX_xsel_n,
AUX_xsds_n => AUX_xsds_n,
AUX_xeob_n => AUX_xeob_n,
AUX_xdk_n => AUX_xdk_n,
AUX_xbusy => AUX_xbusy,
AUX_xbk_n => AUX_xbk_n,
AUX_xberr => AUX_xberr,
AUX_xds_n => AUX_xds_n,
AUX_on_n => AUX_on_n,
AUX_xtrig => AUX_xtrig,
AUX_xas_n => AUX_xas_n,
AUX_xtrgv_n => AUX_xtrgv_n,
AUX_xsyncrd_n => AUX_xsyncrd_n,
AUX_xa_sel => AUX_xa_sel,
Led_red => Led_red,
Led_yellow => Led_yellow
);
U15_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 8 )
PORT MAP(
I1OEAB => '0',
I1A => '0',
I1Y => open,
O1B => open,
I2OEAB => '0',
I2A => '0',
I2Y => open,
O2B => open,
OEn => VME_dataOE,
DIR => VME_data_DIR,
I3A => VME_data(7 downto 0),
O3B => BUS_DATA(7 downto 0)
);
U16_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 8 )
PORT MAP(
I1OEAB => '0',
I1A => '0',
I1Y => VME_Dsy(1),
O1B => BUS_DS_n(1),
I2OEAB => '0',
I2A => '0',
I2Y => VME_Dsy(0),
O2B => BUS_DS_n(0),
OEn => VME_dataOE,
DIR => VME_data_DIR,
I3A => VME_data(15 downto 8),
O3B => BUS_DATA(15 downto 8)
);
U17_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 8 )
PORT MAP(
I1OEAB => '0',
I1A => '0',
I1Y => open,
O1B => open,
I2OEAB => '0',
I2A => '0',
I2Y => open,
O2B => open,
OEn => VME_dataOE,
DIR => VME_data_DIR,
I3A => VME_data(23 downto 16),
O3B => BUS_DATA(23 downto 16)
);
U18_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 8 )
PORT MAP(
I1OEAB => '0',
I1A => '0',
I1Y => open,
O1B => open,
I2OEAB => '0',
I2A => '0',
I2Y => open,
O2B => open,
OEn => VME_dataOE,
DIR => VME_data_DIR,
I3A => VME_data(31 downto 24),
O3B => BUS_DATA(31 downto 24)
);
U21_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 8 )
PORT MAP(
I1OEAB => '0',
I1A => '0',
I1Y => VME_ASy,
O1B => BUS_AS_n,
I2OEAB => '0',
I2A => '0',
I2Y => VME_IACKy,
O2B => BUS_IACK_n,
OEn => VME_addrOE,
DIR => VME_addr_DIR,
I3A => VME_addr(7 downto 0),
O3B => BUS_ADDR(7 downto 0)
);
U22_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 8 )
PORT MAP(
I1OEAB => '0',
I1A => '0',
I1Y => VME_IACKINy,
O1B => BUS_IACKIN_n,
I2OEAB => '1',
I2A => VME_IACKOUTa,
I2Y => open,
O2B => BUS_IACKOUT_n,
OEn => VME_addrOE,
DIR => VME_addr_DIR,
I3A => VME_addr(15 downto 8),
O3B => BUS_ADDR(15 downto 8)
);
U23_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 8 )
PORT MAP(
I1OEAB => VME_oeabDTACK,
I1A => VME_DTACKa,
I1Y => open,
O1B => BUS_DTACK_n,
I2OEAB => '0',
I2A => '0',
I2Y => VME_WRITEy,
O2B => BUS_WRITE_n,
OEn => VME_addrOE,
DIR => VME_addr_DIR,
I3A => VME_addr(23 downto 16),
O3B => BUS_ADDR(23 downto 16)
);
U24_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 8 )
PORT MAP(
I1OEAB => VME_oeabRETRY,
I1A => VME_RETRYa,
I1Y => open,
O1B => BUS_RETRY_n,
I2OEAB => '0',
I2A => '0',
I2Y => open,
O2B => open,
OEn => VME_addrOE,
DIR => VME_addr_DIR,
I3A => VME_addr(31 downto 24),
O3B => BUS_ADDR(31 downto 24)
);
U19_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 6 )
PORT MAP(
I1OEAB => VME_oeabBERR,
I1A => '0',
I1Y => open,
O1B => BUS_BERR_n,
I2OEAB => VME_IRQ(1),
I2A => '0',
I2Y => open,
O2B => BUS_IRQ(1),
OEn => '0',
DIR => '0',
I3A => VME_am(5 downto 0),
O3B => BUS_AM(5 downto 0)
);
--in realta' sono su U19 ...
VME_sysclk <= BUS_SYSCLK;
VME_sysres_n <= BUS_SYSRES_n;
U51_LCV07A:
for i in 2 to 7 generate
BUS_IRQ(i) <= '0' when (VME_IRQ(i) = '1') else 'Z';
end generate;
-- AUX BUS
BUS_XT2 <= trigger;
-- in realta arrivano differenziali su U31 ...
AUX_xtrig <= BUS_XCLK & BUS_XRES & BUS_XT2 & BUS_XT1;
U25_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 8 )
PORT MAP(
I1OEAB => '0',
I1A => '0',
I1Y => open,
O1B => open,
I2OEAB => '1',
I2A => AUX_xsds_n,
I2Y => open,
O2B => BUS_XSDS_n,
OEn => AUX_xsel_n,
DIR => '1',
I3A => VME_data(7 downto 0),
O3B => BUS_XD(7 downto 0)
);
U26_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 8 )
PORT MAP(
I1OEAB => '0',
I1A => '0',
I1Y => AUX_xas_n,
O1B => BUS_XAS_n,
I2OEAB => '0',
I2A => '0',
I2Y => AUX_xtrgv_n,
O2B => BUS_XTRGV_n,
OEn => AUX_xsel_n,
DIR => '1',
I3A => VME_data(15 downto 8),
O3B => BUS_XD(15 downto 8)
);
U27_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 4 )
PORT MAP(
I1OEAB => '0',
I1A => '0',
I1Y => AUX_xds_n,
O1B => BUS_XDS_n,
I2OEAB => '0',
I2A => '0',
I2Y => AUX_xsyncrd_n,
O2B => BUS_XSYNCRD_n,
OEn => AUX_xsel_n,
DIR => '1',
I3A => VME_data(19 downto 16),
O3B => BUS_XD(19 downto 16)
);
-- in realta sono su U27 ...
-- out alp:
-- AUX_xdk_n <= BUS_XDK_n when AUX_xsel_n = '0' else 'Z';
-- AUX_xeob_n <= BUS_XEOB_n when AUX_xsel_n = '0' else 'Z';
-- in alp:
BUS_xdk_n <= AUX_XDK_n when AUX_xsel_n = '0' else 'Z';
BUS_xeob_n <= AUX_XEOB_n when AUX_xsel_n = '0' else 'Z';
U28_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 8 )
PORT MAP(
I1OEAB => '0',
I1A => '0',
I1Y => AUX_xa_sel,
O1B => BUS_XA_SEL,
I2OEAB => AUX_xbk_n,
I2A => '0',
I2Y => BUS_XBK,
O2B => open,
OEn => AUX_on_n,
DIR => '0',
I3A => VME_data(27 downto 20),
O3B => BUS_XT(7 downto 0)
);
U20_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 4 )
PORT MAP(
I1OEAB => AUX_xbusy,
I1A => '0',
I1Y => open,
O1B => BUS_XBUSY_n,
I2OEAB => AUX_xberr,
I2A => '0',
I2Y => open,
O2B => BUS_XBERR_n,
OEn => AUX_on_n,
DIR => '0',
I3A => VME_data(31 downto 28),
O3B => BUS_XT(11 downto 8)
);
U52_sn74vme: sn74vme
GENERIC MAP ( NUMOFBIT => 8 )
PORT MAP(
I1OEAB => '0',
I1A => '0',
I1Y => open,
O1B => open,
I2OEAB => '0',
I2A => '0',
I2Y => open,
O2B => open,
OEn => VME_statrd_n,
DIR => '1',
I3A => STAT_REG(7 downto 0),
O3B => BUS_DATA(7 downto 0)
);
STAT_REG <= "00" & AUX_xbk_n & AUX_xeob_n & AUX_xsds_n & AUX_xbusy & AUX_xberr & AUX_on_n;
-- VME BUS SIGNAL from vme64x simulation
BUS_IACKIN_n <= VME64xBus_out.Vme64xIACKIN;
BUS_IACK_n <= VME64xBus_out.Vme64xIACK;
BUS_AS_n <= VME64xBus_out.Vme64xAsN;
BUS_WRITE_n <= VME64xBus_out.Vme64xWRITEN;
BUS_AM <= VME64xBus_out.Vme64xAM;
BUS_DS_n(1) <= VME64xBus_out.Vme64xDs1N;
BUS_DS_n(0) <= VME64xBus_out.Vme64xDs0N;
BUS_ADDR(0) <= VME64xBus_out.Vme64xLWORDN;
BUS_ADDR(31 downto 1) <= VME64xBus_out.Vme64xADDR;
BUS_DATA <= VME64xBus_out.Vme64xDATA;
VME64xBus_in.Vme64xLWORDN <= to_UX01(BUS_ADDR(0));
VME64xBus_in.Vme64xADDR <= to_UX01(BUS_ADDR(31 downto 1));
VME64xBus_in.Vme64xDATA <= to_UX01(BUS_DATA);
VME64xBus_in.Vme64xDtackN <= to_UX01(BUS_DTACK_n);
VME64xBus_in.Vme64xBerrN <= to_UX01(BUS_BERR_n);
VME64xBus_in.Vme64xRetryN <= to_UX01(BUS_RETRY_n);
VME64xBus_in.Vme64xIRQ <= BUS_IRQ; -- era _n perche'?
VME64xBus_in.Vme64xIACKOUT <= BUS_IACKOUT_n;
PULLUP_DTACK_n : PULLUP
port map (
O => BUS_DTACK_n -- Pullup output (connect directly to top-level port)
);
PULLUP_BERR_n : PULLUP
port map (
O => BUS_BERR_n -- Pullup output (connect directly to top-level port)
);
PULLUP_RETRY_n : PULLUP
port map (
O => BUS_RETRY_n -- Pullup output (connect directly to top-level port)
);
PULLUP_XBUSY_n : PULLUP
port map (
O => BUS_XBUSY_n -- Pullup output (connect directly to top-level port)
);
PULLUP_XBERR_n : PULLUP
port map (
O => BUS_XBERR_n -- Pullup output (connect directly to top-level port)
);
PULLUP_XBK : PULLUP
port map (
O => BUS_XBK -- Pullup output (connect directly to top-level port)
);
BUS_PULL_UP:
for i in 0 to 31 generate
data_pull_up : PULLUP
port map (
O => BUS_DATA(i)
);
addr_pull_up : PULLUP
port map (
O => BUS_ADDR(i)
);
end generate;
-- Clock process definitions
CLK_process :process
begin
clk_p <= '0';
clk_n <= '1';
wait for CLK_period/2;
clk_p <= '1';
clk_n <= '0';
wait for CLK_period/2;
end process;
-- Stimuli process
VME_stimuli_proc: process
--variable s : line;
---------- in alp: -----------
procedure W_CSR( address : in integer; data : in integer range 0 to 2**08-1 ) is
begin s_AddressingType <= CR_CSR; s_dataTransferType <= D08Byte3; s_dataToSend <= std_logic_vector(to_unsigned(data,32)); wait for 1 ns;
WriteCSR(c_address => std_logic_vector(to_unsigned(address, 20)), s_dataToSend => s_dataToSend,
s_dataTransferType => s_dataTransferType, s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in, VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
end procedure;
procedure W_CSR( address : in std_logic_vector(19 downto 0); data : in std_logic_vector(7 downto 0) ) is
begin s_AddressingType <= CR_CSR; s_dataTransferType <= D08Byte3; s_dataToSend <= x"000000" & data; wait for 1 ns;
WriteCSR(c_address => address, s_dataToSend => s_dataToSend,
s_dataTransferType => s_dataTransferType, s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in, VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
end procedure;
procedure axi_write( address : in integer; data : in integer ) is
begin s_AddressingType <= A32; s_dataTransferType <= D32; s_dataToSend <= std_logic_vector(to_unsigned(data,32)); wait for 1 ns;
S_Write(v_address => x"00000000" & x"0800" & std_logic_vector(to_unsigned(address, 14)) & "00" , s_dataToSend => s_dataToSend,
s_dataTransferType => s_dataTransferType, s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In, VME64xBus_Out => VME64xBus_Out);
wait for 100 ns;
end procedure;
procedure axi_write( address : in std_logic_vector(13 downto 0); data : in std_logic_vector(31 downto 0) ) is
begin s_AddressingType <= A32; s_dataTransferType <= D32; s_dataToSend <= data; wait for 1 ns;
S_Write(v_address => x"00000000" & x"0800" & address & "00" , s_dataToSend => s_dataToSend,
s_dataTransferType => s_dataTransferType, s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In, VME64xBus_Out => VME64xBus_Out);
wait for 100 ns;
end procedure;
procedure axi_read( address : in integer; data : in integer range 0 to 2**8-1 ) is begin
-- create the procedure in pack
end procedure;
----------------------
begin
BUS_SYSRES_n <= '0'; -- hold reset state for 100 ns.
wait for 102 ns;
wait for 1 us;
BUS_SYSRES_n <= '1';
VME64xBus_Out.Vme64xIACK <= '1';
VME64xBus_Out.Vme64xIACKIN <= '1';
wait for 10 us; -- wait until the initialization finish (wait more than 8705 ns)
------------------------------------------------------------------------------
-- Configure window to access WB bus (ADER)
------------------------------------------------------------------------------
wait for 50 ns;
report "START WRITE ADER";
--W_CSR(x"FFF63", x"08"); -- 0x0FFF63: "00001000"
W_CSR(c_FUNC0_ADER_3, ADER0_A32(31 downto 24)); -- 0x07FF63: BA(7 downto 3) & "000"
W_CSR(c_FUNC0_ADER_2, ADER0_A32(23 downto 16)); -- 0x07FF67: "00000000"
W_CSR(c_FUNC0_ADER_1, ADER0_A32(15 downto 8)); -- 0x07FF6B: "00000000"
W_CSR(c_FUNC0_ADER_0, ADER0_A32( 7 downto 0)); -- 0x07FF6F: Addr Modifier & "00" : 0x24 per AM = 0x09
report "THE MASTER HAS WRITTEN CORRECTLY ALL THE ADERs";
------------------------------------------------------------------------------
-- Enables the VME64x core
------------------------------------------------------------------------------
-- Module Enabled:
W_CSR(c_BIT_SET_REG, x"10"); -- 0x07FF6B: "00010000"
report "THE MASTER HAS ENABLED THE BOARD";
------------------------------------------------------------------------------
-- Access to AXI registers
------------------------------------------------------------------------------
-- Reset AUX BUS
axi_write(0,1);
-- Enable AUX BUS Test Mode
axi_write(1,3);
-- Run AUX BUS
axi_write(0,0);
report "THE MASTER HAS SET THE AUX IN BUILT_IN TEST MODE";
-- Enable AUX BUS
W_CSR(c_USR_BIT_SET_REG, "00000000");
report "THE MASTER HAS ENABLED THE AUX";
-- wait for 1 us;
-- -- Enable AUX BUS
-- W_CSR(c_USR_BIT_CLR_REG, "00000000");
-- report "THE MASTER HAS DISENABLED THE AUX";
wait;
end process;
--------------------
-- CHECK RX DATA
--------------------
process
variable inc : integer := 0;
variable van : integer := 0;
variable vbn : integer := 0;
variable vai : integer := 0;
variable vbi : integer := 0;
begin
wait until rising_edge(BUS_xtrgv_n);
if BUS_xsyncrd_n = '0' then
wait until rising_edge(BUS_xsyncrd_n);
else
-- TEST MODE
wait until falling_edge(BUS_xdk_n);
if to_integer(unsigned(BUS_xd(BUS_xd'high downto BUS_xd'high-6))) < 48 then
a_data <= BUS_xd(BUS_xd'high-8 downto 0);
a_valid <= '1';
a_clk <= '0';
else
b_data <= BUS_xd(BUS_xd'high-8 downto 0);
b_valid <= '1';
b_clk <= '0';
end if;
while BUS_xeob_n/='0' loop
wait until BUS_xdk_n'event and BUS_xdk_n='1';--rising_edge(BUS_xdk_n);
a_valid <= '1';
a_clk <= '1';
b_valid <= '1';
b_clk <= '1';
wait until falling_edge(BUS_xdk_n);
if to_integer(unsigned(BUS_xd(BUS_xd'high downto BUS_xd'high-6))) < 48 then
a_data <= BUS_xd(BUS_xd'high-8 downto 0);
a_valid <= '1';
a_clk <= '0';
else
b_data <= BUS_xd(BUS_xd'high-8 downto 0);
b_valid <= '1';
b_clk <= '0';
end if;
end loop;
wait until BUS_xdk_n'event and BUS_xdk_n='1';--rising_edge(BUS_xdk_n);
a_valid <= '1';
a_clk <= '1';
b_valid <= '1';
b_clk <= '1';
inc := inc+1;
end if;
end process;
--------------------
-- PRBS_ANY: A DATA CHECK
--------------------
a_data_gen: PRBS_ANY
GENERIC MAP(
INV_PATTERN => A_INV_PATTERN,
POLY_LENGHT => POLY_LENGHT,
POLY_TAP => POLY_TAP,
NBITS => a_data'high+1
)
PORT MAP(
CHK_MODE => '0',
RST => rst,
CLK => a_clk,
DATA_IN => a_data,
EN => a_valid,
DATA_OUT => a_data_check
);
--------------------
-- PRBS_ANY: B DATA CHECK
--------------------
b_data_gen: PRBS_ANY
GENERIC MAP(
INV_PATTERN => B_INV_PATTERN,
POLY_LENGHT => POLY_LENGHT,
POLY_TAP => POLY_TAP,
NBITS => b_data'high+1
)
PORT MAP(
CHK_MODE => '0',
RST => rst,
CLK => b_clk,
DATA_IN => b_data,
EN => b_valid,
DATA_OUT => b_data_check
);
--------------------
-- AUXBUS STIMULI
--------------------
process
--------------------
-- Sync Cycle
--------------------
procedure sync_cycle is
constant tn : std_logic_vector(11 downto 0) := std_logic_vector(to_unsigned(trig_num,12));
begin
-- Trigger Bus, first valid trigger is 001
BUS_xt <= (others=> '0');
-- Master is initiating a synch check, Active LOW
BUS_xsyncrd_n <= '0';
wait for 50 ns;
-- Trigger Bus Data is valide, Active LOW
BUS_xtrgv_n <= '0';
wait until BUS_xbk = '1' for 1 us;
-- if BUS_xbk = '0' then
-- report "No response during Trigger Cycle with Trigger Number " & integer'image(trig_num) & "." severity WARNING;
-- end if;
founddata <= not BUS_xsds_n;
wait for 5 ns;
assert not(BUS_xbk='0') report "ERROR: xbk asserted to '0' before xtrgv_n is released during trigger cycle with Trigger Number " & integer'image(trig_num) & "." severity FAILURE;
-- Trigger Bus Data is valide, Active LOW
BUS_xtrgv_n <= '1';
-- Trigger Bus, first valid trigger is 001
BUS_xt <= (others => '0');
end sync_cycle;
--------------------
-- Sync Readout Cycle
--------------------
procedure sync_readout (founddata : std_logic) is
begin
if founddata = '0' then
report "Error: xsds not asserted low during sync cycle." severity FAILURE;
return;
end if;
-- Address Bus
BUS_xa_sel <= '1';
wait for 40 ns;
-- Address Bus is Valid
BUS_xas_n <= '0';
wait for 1 ns;
RO_loop: loop
-- ROCK ready to read from slave, Active LOW
-- ROCK finished to read from slave, Active HIGH
BUS_xds_n <= '0';
wait until BUS_xdk_n = '0' for 1 us;
if BUS_xdk_n /= '0' then
report "No response from target " & "during Sync Readout Cycle " & "." severity FAILURE;
exit RO_loop;
end if;
rx_data <= BUS_xd;
-- ROCK ready to read from slave, Active LOW
-- ROCK finished to read from slave, Active HIGH
BUS_xds_n <= '1';
wait for 15 ns;
exit RO_loop when BUS_xeob_n = '0';
report "xeob_n not asserted low during Sync Readout" & "." severity FAILURE;
end loop;
wait for 5 ns;
-- Address Bus is Valid
BUS_xas_n <= '1';
wait for 50 ns;
-- Address Bus
BUS_xa_sel <= '0';
-- Master is initiating a synch check, Active LOW
BUS_xsyncrd_n <= '1';
end sync_readout;
--------------------
-- Set in Idle
--------------------
procedure idle is
begin
-- Trigger Bus, first valid trigger is 001
BUS_xt <= (others => '0');
-- Trigger Bus Data is valide, Active LOW
BUS_xtrgv_n <= '1';
-- Address Bus
BUS_xa_sel <= '0';
-- Address Bus is Valid
BUS_xas_n <= '1';
-- ROCK ready to read from slave, Active LOW
-- ROCK finished to read from slave, Active HIGH
BUS_xds_n <= '1';
-- Master is initiating a synch check, Active LOW
BUS_xsyncrd_n <= '1';
-- ROCK send a system HALT due to Error,
--xsyshalt <= '1';
-- ROCK produces a create level AUX reset
--xsysreset <= '1';
-- Other Signals
founddata <= '0';
rx_data <= (others => '0');
end idle;
--------------------
-- Trigger Cycle
--------------------
procedure trigger_cycle (trig_num :integer) is
constant tn : std_logic_vector(11 downto 0) := std_logic_vector(to_unsigned(trig_num,12));
begin
-- Trigger Bus, first valid trigger is 000
BUS_xt <= tn;
wait for 40 ns;
-- Trigger Bus Data is valide, Active LOW
BUS_xtrgv_n <= '0';
wait until BUS_xbk = '1' for 1 us;
-- if xbk = '0' then
-- report "No response during Trigger Cycle with Trigger Number " & integer'image(trig_num) & "." severity WARNING;
-- else
founddata <= not BUS_xsds_n;
wait for 5 ns;
assert not(BUS_xbk='0') report "ERROR: xbk asserted to '0' before xtrgv_n is released during trigger cycle with Trigger Number " & integer'image(trig_num) & "." severity FAILURE;
-- end if;
-- Trigger Bus Data is valide, Active LOW
BUS_xtrgv_n <= '1';
-- Trigger Bus, first valid trigger is 001
BUS_xt <= (others => '0');
end trigger_cycle;
--------------------
-- Trigger Readout Cycle
--------------------
procedure trigger_readout (trig_num : integer; founddata : std_logic) is
begin
if founddata = '0' then
--report "No found data, exiting from readout cycle." severity note;
return;
end if;
-- Address Bus
BUS_xa_sel <= '1';
wait for 40 ns;
-- Address Bus is Valid
BUS_xas_n <= '0';
wait for 1 ns;
RO_loop: loop
-- ROCK ready to read from slave, Active LOW
-- ROCK finished to read from slave, Active HIGH
BUS_xds_n <= '0';
wait until BUS_xdk_n = '0' for 1 us;
if BUS_xdk_n /= '0' then
report "No response from target " & "during Readout Cycle with Trigger Number " & integer'image(trig_num) & "." severity FAILURE;
exit RO_loop;
end if;
rx_data <= BUS_xd;
wait for 4 ns;
BUS_xds_n <= '1';
wait for 1 ns;
-- ROCK ready to read from slave, Active LOW
-- ROCK finished to read from slave, Active HIGH
exit RO_loop when BUS_xeob_n = '0';
wait for 15 ns;
end loop;
wait for 10 ns;
-- Address Bus is Valid
BUS_xas_n <= '1';
wait for 40 ns;
-- Address Bus
BUS_xa_sel <= '0';
end trigger_readout;
variable tst : time := 300 ps;
begin
tst := (tst + 300 ps);
-- idle
idle;
wait for 100 ns;
if AUX_on_n='1' then
wait until AUX_on_n = '0';
wait for 100 ns;
end if;
trig_num <= trig_num + 1;
wait for tst;
--report "Start AUX Trigger Cycle..." severity NOTE;
trigger_cycle(trig_num);
--report "Done." severity NOTE;
wait for 150 ns;
wait for tst;
--report "Start AUX Trigger Readout Cycle..." severity NOTE;
trigger_readout(trig_num, founddata);
--report "Done." severity NOTE;
--wait for 100 ns;
--trig_num <= trig_num + 1;
wait for 10 ns;
wait for tst;
idle;
wait for 1 us;
wait for tst;
sync_cycle;
wait for 150 ns;
wait for tst;
sync_readout(founddata);
wait for 10 ns;
--wait;
end process;
--------------------
-- TIMING REPORT
--------------------
-- trigger (35 ns)
process
variable time_diff : time;
variable curr_time : time;
begin
wait until falling_edge(BUS_xtrgv_n);
wait until BUS_xsds_n = '0';
curr_time := now;
wait until BUS_xbk = '1'; --'Z'
time_diff := now - curr_time;
--report "--------- - - 35ns -> " & time'image(time_diff) severity NOTE;
assert time_diff >= 35 ns report "TRIGGER TIMING ERROR:35ns -> " & time'image(time_diff) severity FAILURE;
end process;
-- readout (15 ns)
process
variable time_diff : time;
variable curr_time : time;
variable xd_temp : std_logic_vector(19 DOWNTO 0);
begin
wait until rising_edge(BUS_xds_n);
wait until BUS_xd'event;
xd_temp := BUS_xd;
curr_time := now;
loop ---------- Note: There could be a second event in xd.
wait until falling_edge(BUS_xdk_n) or BUS_xd'event;
if xd_temp = BUS_xd then
exit;
end if;
xd_temp := BUS_xd;
curr_time := now;
end loop;
time_diff := now - curr_time;
--report "--------- - - 15ns -> " & time'image(time_diff) severity NOTE;
assert time_diff >= 15 ns report "READOUT TIMING ERROR: 15ns -> " & time'image(time_diff) severity FAILURE;
end process;
rst <= not BUS_SYSRES_n;
--------------------
-- TRIGGER PROCESS
--------------------
tr_pr: process
begin
trigger <= '0';
wait for clk_period*1;
if rst = '1' then
wait until rst='0';
end if;
wait for clk_period*50;
wait until clk_p'event and clk_p='1';
wait for clk_period/5;
if BUS_xsyncrd_n='1'and AUX_xbusy='0' then
trigger <= '1';
end if;
wait for clk_period*10;
end process;
end AUX_Behavioral;
|
mit
|
bbac6a9b75cfe6a4955d12d04f5f4be7
| 0.547333 | 2.829368 | false | false | false | false |
freecores/w11
|
rtl/vlib/comlib/comlib.vhd
| 2 | 7,831 |
-- $Id: comlib.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: comlib
-- Description: communication components
--
-- Dependencies: -
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-09-17 410 1.4 now numeric_std clean; use for crc8 'A6' polynomial
-- of Koopman et al.; crc8_update(_tbl) now function
-- 2011-07-30 400 1.3 added byte2word, word2byte
-- 2007-10-12 88 1.2.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-07-08 65 1.2 added procedure crc8_update_tbl
-- 2007-06-29 61 1.1.1 rename for crc8 SALT->INIT
-- 2007-06-17 58 1.1 add crc8
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
package comlib is
component byte2word is -- 2 byte -> 1 word stream converter
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv8; -- input data (byte)
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv16; -- output data (word)
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
ODD : out slbit -- odd byte pending
);
end component;
component word2byte is -- 1 word -> 2 byte stream converter
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv16; -- input data (word)
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv8; -- output data (byte)
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
ODD : out slbit -- odd byte pending
);
end component;
component cdata2byte is -- 9bit comma,data -> byte stream
generic (
CPREF : slv4 := "1000"; -- comma prefix
NCOMM : positive := 4); -- number of comma chars
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv9; -- input data; bit 8 = komma flag
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv8; -- output data
VAL : out slbit; -- read valid
HOLD : in slbit -- read hold
);
end component;
component byte2cdata is -- byte stream -> 9bit comma,data
generic (
CPREF : slv4 := "1000"; -- comma prefix
NCOMM : positive := 4); -- number of comma chars
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv8; -- input data
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv9; -- output data; bit 8 = komma flag
VAL : out slbit; -- read valid
HOLD : in slbit -- read hold
);
end component;
component crc8 is -- crc-8 generator, checker
generic (
INIT: slv8 := "00000000"); -- initial state of crc register
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENA : in slbit; -- update enable
DI : in slv8; -- input data
CRC : out slv8 -- crc code
);
end component;
function crc8_update (crc : in slv8; data : in slv8) return slv8;
function crc8_update_tbl (crc : in slv8; data : in slv8) return slv8;
end package comlib;
-- ----------------------------------------------------------------------------
package body comlib is
function crc8_update (crc: in slv8; data: in slv8) return slv8 is
variable t : slv8 := (others=>'0');
variable n : slv8 := (others=>'0');
begin
t := data xor crc;
n(0) := t(5) xor t(4) xor t(2) xor t(0);
n(1) := t(6) xor t(5) xor t(3) xor t(1);
n(2) := t(7) xor t(6) xor t(5) xor t(0);
n(3) := t(7) xor t(6) xor t(5) xor t(4) xor t(2) xor t(1) xor t(0);
n(4) := t(7) xor t(6) xor t(5) xor t(3) xor t(2) xor t(1);
n(5) := t(7) xor t(6) xor t(4) xor t(3) xor t(2);
n(6) := t(7) xor t(3) xor t(2) xor t(0);
n(7) := t(4) xor t(3) xor t(1);
return n;
end function crc8_update;
function crc8_update_tbl (crc: in slv8; data: in slv8) return slv8 is
type crc8_tbl_type is array (0 to 255) of integer;
variable crc8_tbl : crc8_tbl_type := -- generated with gen_crc8_tbl
( 0, 77, 154, 215, 121, 52, 227, 174, -- 00-07
242, 191, 104, 37, 139, 198, 17, 92, -- 00-0f
169, 228, 51, 126, 208, 157, 74, 7, -- 10-17
91, 22, 193, 140, 34, 111, 184, 245, -- 10-1f
31, 82, 133, 200, 102, 43, 252, 177, -- 20-27
237, 160, 119, 58, 148, 217, 14, 67, -- 20-2f
182, 251, 44, 97, 207, 130, 85, 24, -- 30-37
68, 9, 222, 147, 61, 112, 167, 234, -- 30-3f
62, 115, 164, 233, 71, 10, 221, 144, -- 40-47
204, 129, 86, 27, 181, 248, 47, 98, -- 40-4f
151, 218, 13, 64, 238, 163, 116, 57, -- 50-57
101, 40, 255, 178, 28, 81, 134, 203, -- 50-5f
33, 108, 187, 246, 88, 21, 194, 143, -- 60-67
211, 158, 73, 4, 170, 231, 48, 125, -- 60-6f
136, 197, 18, 95, 241, 188, 107, 38, -- 70-70
122, 55, 224, 173, 3, 78, 153, 212, -- 70-7f
124, 49, 230, 171, 5, 72, 159, 210, -- 80-87
142, 195, 20, 89, 247, 186, 109, 32, -- 80-8f
213, 152, 79, 2, 172, 225, 54, 123, -- 90-97
39, 106, 189, 240, 94, 19, 196, 137, -- 90-9f
99, 46, 249, 180, 26, 87, 128, 205, -- a0-a7
145, 220, 11, 70, 232, 165, 114, 63, -- a0-af
202, 135, 80, 29, 179, 254, 41, 100, -- b0-b7
56, 117, 162, 239, 65, 12, 219, 150, -- b0-bf
66, 15, 216, 149, 59, 118, 161, 236, -- c0-c7
176, 253, 42, 103, 201, 132, 83, 30, -- c0-cf
235, 166, 113, 60, 146, 223, 8, 69, -- d0-d7
25, 84, 131, 206, 96, 45, 250, 183, -- d0-df
93, 16, 199, 138, 36, 105, 190, 243, -- e0-e7
175, 226, 53, 120, 214, 155, 76, 1, -- e0-ef
244, 185, 110, 35, 141, 192, 23, 90, -- f0-f7
6, 75, 156, 209, 127, 50, 229, 168 -- f0-ff
);
begin
return slv(to_unsigned(crc8_tbl(to_integer(unsigned(data xor crc))), 8));
end function crc8_update_tbl;
end package body comlib;
|
gpl-2.0
|
38d94c1aa9475fb9c7b0d2917ddf3595
| 0.47363 | 3.30701 | false | false | false | false |
freecores/w11
|
rtl/vlib/rbus/rbd_eyemon.vhd
| 2 | 11,776 |
-- $Id: rbd_eyemon.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rbd_eyemon - syn
-- Description: rbus dev: eye monitor for serport's
--
-- Dependencies: memlib/ram_2swsr_wfirst_gen
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 12.1, 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-04-02 374 12.1 M53d xc3s1000-4 46 154 - 109 s 8.7
-- 2010-12-27 349 12.1 M53d xc3s1000-4 45 147 - 106 s 8.9
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.3 now numeric_std clean
-- 2011-04-02 375 1.0.2 handle back-to-back chars properly (in sim..)
-- 2010-12-31 352 1.0.1 simplify irb_ack logic
-- 2010-12-27 349 1.0 Initial version
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Address Bits Name r/w/f Function
-- bbbbbb00 cntl r/w/- Control register
-- 03 ena01 r/w/- track 0->1 rxsd transitions
-- 02 ena10 r/w/- track 1->0 rxsd transitions
-- 01 clr r/-/f w: writing a 1 starts memory clear
-- r: 1 indicates clr in progress (512 cyc)
-- 00 go r/w/- enables monitor
-- bbbbbb01 7:00 rdiv r/w/- Sample rate divider
-- bbbbbb10 addr r/w/- Address register
-- 9:01 laddr r/w/ line address
-- 00 waddr r/w/ word address
-- bbbbbb11 15:00 data r/-/- Data register
--
-- data format:
-- word 1 counter msb's
-- word 0 counter lsb's
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.rblib.all;
entity rbd_eyemon is -- rbus dev: eye monitor for serport's
generic (
RB_ADDR : slv8 := slv(to_unsigned(2#11111000#,8));
RDIV : slv8 := slv(to_unsigned(0,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RXSD : in slbit; -- rx: serial data
RXACT : in slbit -- rx: active (start seen)
);
end entity rbd_eyemon;
architecture syn of rbd_eyemon is
constant rbaddr_cntl : slv2 := "00"; -- cntl address offset
constant rbaddr_rdiv : slv2 := "01"; -- rdiv address offset
constant rbaddr_addr : slv2 := "10"; -- addr address offset
constant rbaddr_data : slv2 := "11"; -- data address offset
constant cntl_rbf_ena01 : integer := 3;
constant cntl_rbf_ena10 : integer := 2;
constant cntl_rbf_clr : integer := 1;
constant cntl_rbf_go : integer := 0;
subtype addr_rbf_laddr is integer range 9 downto 1;
constant addr_rbf_waddr : integer := 0;
type state_type is (
s_idle, -- s_idle: wait for char or clr
s_char, -- s_char: processing a char
s_clr -- s_clr: clear memory
);
type regs_type is record -- state registers
state : state_type; -- state
rbsel : slbit; -- rbus select
go : slbit; -- go flag
clr : slbit; -- clear pending
ena10 : slbit; -- enable 1->0
ena01 : slbit; -- enable 0->1
rdiv : slv8; -- rate divider
laddr : slv9; -- line address
waddr : slbit; -- word address
laddr_1 : slv9; -- line address last cycle
rxsd_1 : slbit; -- rxsd last cycle
memwe : slbit; -- write bram (clr or inc)
memclr : slbit; -- write zero into bram
rdivcnt : slv8; -- rate divider counter
end record regs_type;
constant regs_init : regs_type := (
s_idle, -- state
'0', -- rbsel
'0', -- go (default is off)
'0','0','0', -- clr,ena01,ena10
(others=>'0'), -- rdiv
(others=>'0'), -- laddr
'0', -- waddr
(others=>'0'), -- laddr_1
'0','0','0', -- rxsd_1,memwe,memclr
(others=>'0') -- rdivcnt
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal BRAM_ENA : slbit := '0';
signal BRAM_DIA : slv32 := (others=>'0');
signal BRAM_DIB : slv32 := (others=>'0');
signal BRAM_DOA : slv32 := (others=>'0');
begin
BRAM_DIA <= (others=>'0'); -- always 0, no writes on this port
BRAM : ram_2swsr_wfirst_gen
generic map (
AWIDTH => 9,
DWIDTH => 32)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => BRAM_ENA,
ENB => R_REGS.memwe,
WEA => '0',
WEB => R_REGS.memwe,
ADDRA => R_REGS.laddr,
ADDRB => R_REGS.laddr_1,
DIA => BRAM_DIA,
DIB => BRAM_DIB,
DOA => BRAM_DOA,
DOB => open
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, RB_MREQ, RXSD, RXACT, BRAM_DOA)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
variable ibramen : slbit := '0';
variable ibramdi : slv32 := (others=>'0');
variable laddr_we : slbit := '0';
variable laddr_clr : slbit := '0';
variable laddr_inc : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
ibramen := '0';
laddr_we := '0';
laddr_clr := '0';
laddr_inc := '0';
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(7 downto 2)=RB_ADDR(7 downto 2) then
n.rbsel := '1';
ibramen := '1';
end if;
-- rbus transactions
if r.rbsel = '1' then
irb_ack := irbena; -- ack all accesses
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl =>
if RB_MREQ.we = '1' then
n.ena01 := RB_MREQ.din(cntl_rbf_ena01);
n.ena10 := RB_MREQ.din(cntl_rbf_ena10);
if RB_MREQ.din(cntl_rbf_clr) = '1' then
n.clr := '1';
end if;
n.go := RB_MREQ.din(cntl_rbf_go);
end if;
when rbaddr_rdiv =>
if RB_MREQ.we = '1' then
n.rdiv := RB_MREQ.din(n.rdiv'range);
end if;
when rbaddr_addr =>
if RB_MREQ.we = '1' then
laddr_we := '1';
n.waddr := RB_MREQ.din(addr_rbf_waddr);
end if;
when rbaddr_data =>
if RB_MREQ.we='1' then
irb_err := '1';
end if;
if RB_MREQ.re = '1' then
if r.go='0' and r.clr='0' and r.state=s_idle then
n.waddr := not r.waddr;
if r.waddr = '1' then
laddr_inc := '1';
end if;
else
irb_err := '1';
end if;
end if;
when others => null;
end case;
end if;
-- rbus output driver
if r.rbsel = '1' then
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl =>
irb_dout(cntl_rbf_ena01) := r.ena01;
irb_dout(cntl_rbf_ena10) := r.ena10;
irb_dout(cntl_rbf_clr) := r.clr;
irb_dout(cntl_rbf_go) := r.go;
when rbaddr_rdiv =>
irb_dout(r.rdiv'range) := r.rdiv;
when rbaddr_addr =>
irb_dout(addr_rbf_laddr) := r.laddr;
irb_dout(addr_rbf_waddr) := r.waddr;
when rbaddr_data =>
case r.waddr is
when '1' => irb_dout := BRAM_DOA(31 downto 16);
when '0' => irb_dout := BRAM_DOA(15 downto 0);
when others => null;
end case;
when others => null;
end case;
end if;
-- eye monitor
n.memwe := '0';
n.memclr := '0';
case r.state is
when s_idle => -- s_idle: wait for char or clr ------
if r.clr = '1' then
laddr_clr := '1';
n.state := s_clr;
elsif r.go = '1' and RXSD='0' then
laddr_clr := '1';
n.rdivcnt := r.rdiv;
n.state := s_char;
end if;
when s_char => -- s_char: processing a char ---------
if RXACT = '0' then -- uart went unactive
if RXSD = '1' then -- line idle -> to s_idle
n.state := s_idle;
else -- already next start bit seen
laddr_clr := '1'; -- clear and restart
n.rdivcnt := r.rdiv; -- happens only in simulation...
end if;
else
if (r.ena01='1' and r.rxsd_1='0' and RXSD='1') or
(r.ena10='1' and r.rxsd_1='1' and RXSD='0') then
n.memwe := '1';
ibramen := '1';
end if;
end if;
if unsigned(r.rdiv)=0 or unsigned(r.rdivcnt)=0 then
n.rdivcnt := r.rdiv;
if unsigned(r.laddr) /= (2**r.laddr'length)-1 then
laddr_inc := '1';
end if;
else
n.rdivcnt := slv(unsigned(r.rdivcnt) - 1);
end if;
when s_clr => -- s_clr: clear memory ---------------
laddr_inc := '1';
n.memwe := '1';
n.memclr := '1';
if unsigned(r.laddr) = (2**r.laddr'length)-1 then
n.clr := '0';
n.state := s_idle;
end if;
when others => null;
end case;
if laddr_we = '1' then
n.laddr := RB_MREQ.din(addr_rbf_laddr);
elsif laddr_clr = '1' then
n.laddr := (others=>'0');
elsif laddr_inc = '1' then
n.laddr := slv(unsigned(r.laddr) + 1);
end if;
n.laddr_1 := r.laddr;
n.rxsd_1 := RXSD;
ibramdi := (others=>'0');
if r.memclr = '0' then
ibramdi := slv(unsigned(BRAM_DOA) + 1);
end if;
N_REGS <= n;
BRAM_ENA <= ibramen;
BRAM_DIB <= ibramdi;
RB_SRES.dout <= irb_dout;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= irb_err;
RB_SRES.busy <= irb_busy;
end process proc_next;
end syn;
|
gpl-2.0
|
4e456d2f86545632b46c3dfe5ef0be7f
| 0.472232 | 3.596823 | false | false | false | false |
freecores/w11
|
rtl/w11a/pdp11_tmu_sb.vhd
| 2 | 2,138 |
-- $Id: pdp11_tmu_sb.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2009- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_tmu - sim
-- Description: pdp11: trace and monitor unit; simbus wrapper
--
-- Dependencies: simbus
-- Test bench: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2009-05-10 214 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.pdp11.all;
entity pdp11_tmu_sb is -- trace and mon. unit; simbus wrapper
generic (
ENAPIN : integer := 13); -- SB_CNTL signal to use for enable
port (
CLK : in slbit; -- clock
DM_STAT_DP : in dm_stat_dp_type; -- DM dpath
DM_STAT_VM : in dm_stat_vm_type; -- DM vmbox
DM_STAT_CO : in dm_stat_co_type; -- DM core
DM_STAT_SY : in dm_stat_sy_type -- DM system
);
end pdp11_tmu_sb;
architecture sim of pdp11_tmu_sb is
signal ENA : slbit := '0';
begin
assert ENAPIN>=SB_CNTL'low and ENAPIN<=SB_CNTL'high
report "assert(ENAPIN in SB_CNTL'range)" severity failure;
ENA <= to_x01(SB_CNTL(ENAPIN));
CPMON : pdp11_tmu
port map (
CLK => CLK,
ENA => ENA,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO,
DM_STAT_SY => DM_STAT_SY
);
end sim;
|
gpl-2.0
|
ba3875cf0dab4ede2f334563d370c3ed
| 0.583255 | 3.482085 | false | false | false | false |
freecores/w11
|
rtl/w11a/pdp11_dpath.vhd
| 2 | 11,075 |
-- $Id: pdp11_dpath.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_dpath - syn
-- Description: pdp11: CPU datapath
--
-- Dependencies: pdp11_gpr
-- pdp11_psr
-- pdp11_ounit
-- pdp11_aunit
-- pdp11_lunit
-- pdp11_munit
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-09-18 300 1.2.1 rename (adlm)box->(oalm)unit
-- 2010-06-13 305 1.2 rename CPDIN -> CP_DIN; add CP_DOUT out port;
-- remove CPADDR out port; drop R_CPADDR, proc_cpaddr;
-- added R_CPDOUT, proc_cpdout
-- 2009-05-30 220 1.1.6 final removal of snoopers (were already commented)
-- 2008-12-14 177 1.1.5 fill gpr_* fields in DM_STAT_DP
-- 2008-08-22 161 1.1.4 rename ubf_ -> ibf_; use iblib
-- 2008-04-19 137 1.1.3 add DM_STAT_DP port
-- 2008-03-02 121 1.1.2 remove snoopers
-- 2008-02-24 119 1.1.1 add CPADDR register, remove R_MDIN (not needed)
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now (for psr access)
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_dpath is -- CPU datapath
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- console reset
CNTL : in dpath_cntl_type; -- control interface
STAT : out dpath_stat_type; -- status interface
CP_DIN : in slv16; -- console port data in
CP_DOUT : out slv16; -- console port data out
PSWOUT : out psw_type; -- current psw
PCOUT : out slv16; -- current pc
IREG : out slv16; -- ireg out
VM_ADDR : out slv16; -- virt. memory address
VM_DOUT : in slv16; -- virt. memory data out
VM_DIN : out slv16; -- virt. memory data in
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
DM_STAT_DP : out dm_stat_dp_type -- debug and monitor status
);
end pdp11_dpath;
architecture syn of pdp11_dpath is
signal R_DSRC : slv16 := (others=>'0'); -- SRC register
signal R_DDST : slv16 := (others=>'0'); -- DST register
signal R_DTMP : slv16 := (others=>'0'); -- TMP register
signal R_IREG : slv16 := (others=>'0'); -- IREG register
signal R_CPDOUT : slv16 := (others=>'0'); -- cp dout buffer
signal GPR_DSRC : slv16 := (others=>'0'); --
signal GPR_DDST : slv16 := (others=>'0'); --
signal GPR_PC : slv16 := (others=>'0'); --
signal PSW : psw_type := psw_init; --
signal CCIN : slv4 := (others=>'0'); -- cc input to xbox's
signal CCOUT : slv4 := (others=>'0'); -- cc output from xbox's
signal DRES : slv16 := (others=>'0'); -- result bus
signal DRESE : slv16 := (others=>'0'); -- result bus extra
signal OUNIT_DOUT : slv16 := (others=>'0'); -- result ounit
signal AUNIT_DOUT : slv16 := (others=>'0'); -- result aunit
signal LUNIT_DOUT : slv16 := (others=>'0'); -- result lunit
signal MUNIT_DOUT : slv16 := (others=>'0'); -- result munit
signal OUNIT_NZOUT : slv2 := (others=>'0'); -- nz flags ounit
signal OUNIT_CCOUT : slv4 := (others=>'0'); -- cc flags ounit
signal AUNIT_CCOUT : slv4 := (others=>'0'); -- cc flags aunit
signal LUNIT_CCOUT : slv4 := (others=>'0'); -- cc flags lunit
signal MUNIT_CCOUT : slv4 := (others=>'0'); -- cc flags munit
subtype lal_ibf_addr is integer range 15 downto 1;
subtype lah_ibf_addr is integer range 5 downto 0;
constant lah_ibf_ena_22bit: integer := 6;
constant lah_ibf_ena_ubmap: integer := 7;
begin
GPR : pdp11_gpr port map (
CLK => CLK,
DIN => DRES,
ASRC => CNTL.gpr_asrc,
ADST => CNTL.gpr_adst,
MODE => CNTL.gpr_mode,
RSET => CNTL.gpr_rset,
WE => CNTL.gpr_we,
BYTOP => CNTL.gpr_bytop,
PCINC => CNTL.gpr_pcinc,
DSRC => GPR_DSRC,
DDST => GPR_DDST,
PC => GPR_PC
);
PSR : pdp11_psr port map(
CLK => CLK,
CRESET => CRESET,
DIN => DRES,
CCIN => CCOUT,
CCWE => CNTL.psr_ccwe,
WE => CNTL.psr_we,
FUNC => CNTL.psr_func,
PSW => PSW,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES
);
OUNIT : pdp11_ounit port map (
DSRC => R_DSRC,
DDST => R_DDST,
DTMP => R_DTMP,
PC => GPR_PC,
ASEL => CNTL.ounit_asel,
AZERO => CNTL.ounit_azero,
IREG8 => R_IREG(7 downto 0),
VMDOUT => VM_DOUT,
CONST => CNTL.ounit_const,
BSEL => CNTL.ounit_bsel,
OPSUB => CNTL.ounit_opsub,
DOUT => OUNIT_DOUT,
NZOUT => OUNIT_NZOUT
);
AUNIT : pdp11_aunit port map (
DSRC => R_DSRC,
DDST => R_DDST,
CI => CCIN(0),
SRCMOD => CNTL.aunit_srcmod,
DSTMOD => CNTL.aunit_dstmod,
CIMOD => CNTL.aunit_cimod,
CC1OP => CNTL.aunit_cc1op,
CCMODE => CNTL.aunit_ccmode,
BYTOP => CNTL.aunit_bytop,
DOUT => AUNIT_DOUT,
CCOUT => AUNIT_CCOUT
);
LUNIT : pdp11_lunit port map (
DSRC => R_DSRC,
DDST => R_DDST,
CCIN => CCIN,
FUNC => CNTL.lunit_func,
BYTOP => CNTL.lunit_bytop,
DOUT => LUNIT_DOUT,
CCOUT => LUNIT_CCOUT
);
MUNIT : pdp11_munit port map (
CLK => CLK,
DSRC => R_DSRC,
DDST => R_DDST,
DTMP => R_DTMP,
GPR_DSRC => GPR_DSRC,
FUNC => CNTL.munit_func,
S_DIV => CNTL.munit_s_div,
S_DIV_CN => CNTL.munit_s_div_cn,
S_DIV_CR => CNTL.munit_s_div_cr,
S_ASH => CNTL.munit_s_ash,
S_ASH_CN => CNTL.munit_s_ash_cn,
S_ASHC => CNTL.munit_s_ashc,
S_ASHC_CN => CNTL.munit_s_ashc_cn,
SHC_TC => STAT.shc_tc,
DIV_CR => STAT.div_cr,
DIV_CQ => STAT.div_cq,
DIV_ZERO => STAT.div_zero,
DIV_OVFL => STAT.div_ovfl,
DOUT => MUNIT_DOUT,
DOUTE => DRESE,
CCOUT => MUNIT_CCOUT
);
CCIN <= PSW.cc;
OUNIT_CCOUT <= OUNIT_NZOUT & "0" & CCIN(0); -- clear v, keep c
proc_dres_sel: process (OUNIT_DOUT, AUNIT_DOUT, LUNIT_DOUT, MUNIT_DOUT,
VM_DOUT, R_IREG, CP_DIN, CNTL)
begin
case CNTL.dres_sel is
when c_dpath_res_ounit => DRES <= OUNIT_DOUT;
when c_dpath_res_aunit => DRES <= AUNIT_DOUT;
when c_dpath_res_lunit => DRES <= LUNIT_DOUT;
when c_dpath_res_munit => DRES <= MUNIT_DOUT;
when c_dpath_res_vmdout => DRES <= VM_DOUT;
when c_dpath_res_fpdout => DRES <= (others=>'0');
when c_dpath_res_ireg => DRES <= R_IREG;
when c_dpath_res_cpdin => DRES <= CP_DIN;
when others => null;
end case;
end process proc_dres_sel;
proc_cres_sel: process (OUNIT_CCOUT, AUNIT_CCOUT, LUNIT_CCOUT, MUNIT_CCOUT,
CCIN, CNTL)
begin
case CNTL.cres_sel is
when c_dpath_res_ounit => CCOUT <= OUNIT_CCOUT;
when c_dpath_res_aunit => CCOUT <= AUNIT_CCOUT;
when c_dpath_res_lunit => CCOUT <= LUNIT_CCOUT;
when c_dpath_res_munit => CCOUT <= MUNIT_CCOUT;
when c_dpath_res_vmdout => CCOUT <= CCIN;
when c_dpath_res_fpdout => CCOUT <= "0000";
when c_dpath_res_ireg => CCOUT <= CCIN;
when c_dpath_res_cpdin => CCOUT <= CCIN;
when others => null;
end case;
end process proc_cres_sel;
proc_dregs: process (CLK)
begin
if rising_edge(CLK) then
if CNTL.dsrc_we = '1' then
if CNTL.dsrc_sel = '0' then
R_DSRC <= GPR_DSRC;
else
R_DSRC <= DRES;
end if;
end if;
if CNTL.ddst_we = '1' then
if CNTL.ddst_sel = '0' then
R_DDST <= GPR_DDST;
else
R_DDST <= DRES;
end if;
end if;
if CNTL.dtmp_we = '1' then
case CNTL.dtmp_sel is
when c_dpath_dtmp_dsrc => R_DTMP <= GPR_DSRC;
when c_dpath_dtmp_psw =>
R_DTMP <= (others=>'0');
R_DTMP(psw_ibf_cmode) <= PSW.cmode;
R_DTMP(psw_ibf_pmode) <= PSW.pmode;
R_DTMP(psw_ibf_rset) <= PSW.rset;
R_DTMP(psw_ibf_pri) <= PSW.pri;
R_DTMP(psw_ibf_tflag) <= PSW.tflag;
R_DTMP(psw_ibf_cc) <= PSW.cc;
when c_dpath_dtmp_dres => R_DTMP <= DRES;
when c_dpath_dtmp_drese => R_DTMP <= DRESE;
when others => null;
end case;
end if;
end if;
end process proc_dregs;
proc_mregs: process (CLK)
begin
if rising_edge(CLK) then
if CNTL.ireg_we = '1' then
R_IREG <= VM_DOUT;
end if;
end if;
end process proc_mregs;
proc_cpdout: process (CLK)
begin
if rising_edge(CLK) then
if CRESET = '1' then
R_CPDOUT <= (others=>'0');
else
if CNTL.cpdout_we = '1' then
R_CPDOUT <= DRES;
end if;
end if;
end if;
end process proc_cpdout;
proc_vmaddr_sel: process (R_DSRC, R_DDST, R_DTMP, GPR_PC, CNTL)
begin
case CNTL.vmaddr_sel is
when c_dpath_vmaddr_dsrc => VM_ADDR <= R_DSRC;
when c_dpath_vmaddr_ddst => VM_ADDR <= R_DDST;
when c_dpath_vmaddr_dtmp => VM_ADDR <= R_DTMP;
when c_dpath_vmaddr_pc => VM_ADDR <= GPR_PC;
when others => null;
end case;
end process proc_vmaddr_sel;
STAT.ccout_z <= CCOUT(2); -- current Z cc flag
PSWOUT <= PSW;
PCOUT <= GPR_PC;
IREG <= R_IREG;
VM_DIN <= DRES;
CP_DOUT <= R_CPDOUT;
DM_STAT_DP.pc <= GPR_PC;
DM_STAT_DP.psw <= PSW;
DM_STAT_DP.ireg <= R_IREG;
DM_STAT_DP.ireg_we <= CNTL.ireg_we;
DM_STAT_DP.dsrc <= R_DSRC;
DM_STAT_DP.ddst <= R_DDST;
DM_STAT_DP.dtmp <= R_DTMP;
DM_STAT_DP.dres <= DRES;
DM_STAT_DP.gpr_adst <= CNTL.gpr_adst;
DM_STAT_DP.gpr_mode <= CNTL.gpr_mode;
DM_STAT_DP.gpr_bytop <= CNTL.gpr_bytop;
DM_STAT_DP.gpr_we <= CNTL.gpr_we;
end syn;
|
gpl-2.0
|
54092bf6a8159ee6c3b6276656590eb1
| 0.539052 | 3.242096 | false | false | false | false |
freecores/w11
|
rtl/bplib/fx2lib/fx2_2fifoctl_as.vhd
| 1 | 21,261 |
-- $Id: fx2_2fifoctl_as.vhd 453 2012-01-15 17:51:18Z mueller $
--
-- Copyright 2011-2012 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: fx2_2fifoctl_as - syn
-- Description: Cypress EZ-USB FX2 driver (2 fifo; async)
--
-- Dependencies: vlib/xlib/iob_reg_o
-- vlib/xlib/iob_reg_i_gen
-- vlib/xlib/iob_reg_o_gen
-- vlib/xlib/iob_reg_io_gen
-- memlib/fifo_1c_dram
--
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 12.1, 13.1, 13.3; ghdl 0.26-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2012-01-14 453 13.3 O76x xc3s1200e-4 65 153 64 133 s 7.2
-- 2012-01-03 449 13.3 O76x xc3s1200e-4 67 149 64 133 s 7.2
-- 2011-12-25 445 13.3 O76x xc3s1200e-4 61 147 64 127 s 7.2
-- 2011-12-25 444 13.3 O76x xc3s1200e-4 54 140 64 123 s 7.2
-- 2011-07-07 389 12.1 M53d xc3s1200e-4 45 132 64 109 s 7.9
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-01-14 453 1.3 common DELAY for PE and WR; use aempty/afull logic
-- 2012-01-04 450 1.2.2 use new FLAG layout (EF,FF now fixed)
-- 2012-01-03 449 1.2.1 use new fx2ctl_moni layout; hardcode ep's
-- 2011-12-25 445 1.2 change pktend handling, now timer based
-- 2011-11-25 433 1.1.1 now numeric_std clean
-- 2011-07-30 400 1.1 capture rx data in 2nd last s_rdpwh cycle
-- 2011-07-24 389 1.0.2 use FX2_FLAG_N to signal that flags are act.low
-- 2011-07-17 394 1.0.1 (RX|TX)FIFOEP now generics; add MONI port
-- 2011-07-08 390 1.0 Initial version
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.memlib.all;
use work.fx2lib.all;
entity fx2_2fifoctl_as is -- EZ-USB FX2 driver (2 fifo; async)
generic (
RXFAWIDTH : positive := 5; -- receive fifo address width
TXFAWIDTH : positive := 5; -- transmit fifo address width
PETOWIDTH : positive := 7; -- packet end time-out counter width
CCWIDTH : positive := 5; -- chunk counter width
RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag
TXAFULL_THRES : natural := 1; -- threshold for tx afull flag
RDPWLDELAY : positive := 5; -- slrd low delay in clock cycles
RDPWHDELAY : positive := 5; -- slrd high delay in clock cycles
WRPWLDELAY : positive := 5; -- slwr low delay in clock cycles
WRPWHDELAY : positive := 7; -- slwr high delay in clock cycles
FLAGDELAY : positive := 2); -- flag delay in clock cycles
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit := '0'; -- reset
RXDATA : out slv8; -- receive data out
RXVAL : out slbit; -- receive data valid
RXHOLD : in slbit; -- receive data hold
RXAEMPTY : out slbit; -- receive almost empty flag
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit data busy
TXAFULL : out slbit; -- transmit almost full flag
MONI : out fx2ctl_moni_type; -- monitor port data
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end fx2_2fifoctl_as;
architecture syn of fx2_2fifoctl_as is
constant c_rxfifo : slv2 := c_fifo_ep4;
constant c_txfifo : slv2 := c_fifo_ep6;
constant c_flag_prog : integer := 0;
constant c_flag_tx_ff : integer := 1;
constant c_flag_rx_ef : integer := 2;
constant c_flag_tx2_ff : integer := 3;
type state_type is (
s_init, -- s_init: init state
s_rdprep, -- s_rdprep: prepare read
s_rdwait, -- s_rdwait: wait for data
s_rdpwl, -- s_rdpwl: read, strobe low
s_rdpwh, -- s_rdpwh: read, strobe high
s_wrprep, -- s_wrprep: prepare write
s_wrpwl, -- s_wrpwl: write, strobe low
s_wrpwh, -- s_wrpwh: write, strobe high
s_peprep, -- s_peprep: prepare pktend
s_pepwl, -- s_pepwl: pktend, strobe low
s_pepwh -- s_pepwh: pktend, strobe high
);
type regs_type is record
state : state_type; -- state
petocnt : slv(PETOWIDTH-1 downto 0); -- pktend time out counter
pepend : slbit; -- pktend pending
dlycnt : slv4; -- wait delay counter
moni_ep4_sel : slbit; -- ep4 (rx) select
moni_ep6_sel : slbit; -- ep6 (tx) select
moni_ep4_pf : slbit; -- ep4 (rx) prog flag
moni_ep6_pf : slbit; -- ep6 (rx) prog flag
end record regs_type;
constant petocnt_init : slv(PETOWIDTH-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
s_init, -- state
petocnt_init, -- petocnt
'0', -- pepend
(others=>'0'), -- cntdly
'0','0', -- moni_ep(4|6)_sel
'0','0' -- moni_ep(4|6)_pf
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal FX2_FIFO : slv2 := (others=>'0');
signal FX2_FIFO_CE : slbit := '0';
signal FX2_FLAG_N : slv4 := (others=>'0');
signal FX2_SLRD_N : slbit := '1';
signal FX2_SLWR_N : slbit := '1';
signal FX2_SLOE_N : slbit := '1';
signal FX2_PKTEND_N : slbit := '1';
signal FX2_DATA_CEI : slbit := '0';
signal FX2_DATA_CEO : slbit := '0';
signal FX2_DATA_OE : slbit := '0';
signal RXFIFO_DI : slv8 := (others=>'0');
signal RXFIFO_ENA : slbit := '0';
signal RXFIFO_BUSY : slbit := '0';
signal RXSIZE : slv(RXFAWIDTH downto 0) := (others=>'0');
signal TXFIFO_DO : slv8 := (others=>'0');
signal TXFIFO_VAL : slbit := '0';
signal TXFIFO_HOLD : slbit := '0';
signal TXSIZE : slv(TXFAWIDTH downto 0) := (others=>'0');
signal TXBUSY_L : slbit := '0';
begin
assert RDPWLDELAY<=2**R_REGS.dlycnt'length and
RDPWHDELAY<=2**R_REGS.dlycnt'length and RDPWHDELAY>=2 and
WRPWLDELAY<=2**R_REGS.dlycnt'length and
WRPWHDELAY<=2**R_REGS.dlycnt'length and
FLAGDELAY<=2**R_REGS.dlycnt'length
report "assert(*DELAY <= 2**dlycnt'length and RDPWHDELAY >=2)"
severity failure;
assert RXAEMPTY_THRES<=2**RXFAWIDTH and
TXAFULL_THRES<=2**TXFAWIDTH
report "assert((RXAEMPTY|TXAFULL)_THRES <= 2**(RX|TX)FAWIDTH)"
severity failure;
IOB_FX2_FIFO : iob_reg_o_gen
generic map (
DWIDTH => 2,
INIT => '0')
port map (
CLK => CLK,
CE => FX2_FIFO_CE,
DO => FX2_FIFO,
PAD => O_FX2_FIFO
);
IOB_FX2_FLAG : iob_reg_i_gen
generic map (
DWIDTH => 4,
INIT => '0')
port map (
CLK => CLK,
CE => '1',
DI => FX2_FLAG_N,
PAD => I_FX2_FLAG
);
IOB_FX2_SLRD : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => FX2_SLRD_N,
PAD => O_FX2_SLRD_N
);
IOB_FX2_SLWR : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => FX2_SLWR_N,
PAD => O_FX2_SLWR_N
);
IOB_FX2_SLOE : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => FX2_SLOE_N,
PAD => O_FX2_SLOE_N
);
IOB_FX2_PKTEND : iob_reg_o
generic map (
INIT => '1')
port map (
CLK => CLK,
CE => '1',
DO => FX2_PKTEND_N,
PAD => O_FX2_PKTEND_N
);
IOB_FX2_DATA : iob_reg_io_gen
generic map (
DWIDTH => 8,
PULL => "KEEP")
port map (
CLK => CLK,
CEI => FX2_DATA_CEI,
CEO => FX2_DATA_CEO,
OE => FX2_DATA_OE,
DI => RXFIFO_DI, -- input data (read from pad)
DO => TXFIFO_DO, -- output data (write to pad)
PAD => IO_FX2_DATA
);
RXFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based
generic map (
AWIDTH => RXFAWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => RESET,
DI => RXFIFO_DI,
ENA => RXFIFO_ENA,
BUSY => RXFIFO_BUSY,
DO => RXDATA,
VAL => RXVAL,
HOLD => RXHOLD,
SIZE => RXSIZE
);
TXFIFO : fifo_1c_dram -- output fifo, 1 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => RESET,
DI => TXDATA,
ENA => TXENA,
BUSY => TXBUSY_L,
DO => TXFIFO_DO,
VAL => TXFIFO_VAL,
HOLD => TXFIFO_HOLD,
SIZE => TXSIZE
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_USEC,
FX2_FLAG_N, TXFIFO_VAL, RXFIFO_BUSY, TXBUSY_L)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idly_ld : slbit := '0';
variable idly_val : slv(r.dlycnt'range) := (others=>'0');
variable idly_end : slbit := '0';
variable idly_end1 : slbit := '0';
variable iflag_rdok : slbit := '0';
variable iflag_wrok : slbit := '0';
variable ififo_ce : slbit := '0';
variable ififo : slv2 := "00";
variable irxfifo_ena : slbit := '0';
variable itxfifo_hold : slbit := '0';
variable islrd : slbit := '0';
variable islwr : slbit := '0';
variable isloe : slbit := '0';
variable ipktend : slbit := '0';
variable idata_cei : slbit := '0';
variable idata_ceo : slbit := '0';
variable idata_oe : slbit := '0';
variable imoni : fx2ctl_moni_type := fx2ctl_moni_init;
procedure go_rdprep(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
ififo_ce : out slbit;
ififo : out slv2) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(FLAGDELAY-1, idly_val'length));
ififo_ce := '1';
ififo := c_rxfifo;
nstate := s_rdprep;
end procedure go_rdprep;
procedure go_wrprep(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
ififo_ce : out slbit;
ififo : out slv2) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(FLAGDELAY-1, idly_val'length));
ififo_ce := '1';
ififo := c_txfifo;
nstate := s_wrprep;
end procedure go_wrprep;
procedure go_peprep(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
ififo_ce : out slbit;
ififo : out slv2) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(FLAGDELAY-1, idly_val'length));
ififo_ce := '1';
ififo := c_txfifo;
nstate := s_peprep;
end procedure go_peprep;
procedure go_rdpwl(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
islrd : out slbit) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(RDPWLDELAY-1, n.dlycnt'length));
islrd := '1';
nstate := s_rdpwl;
end procedure go_rdpwl;
procedure go_wrpwl(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
islwr : out slbit) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(WRPWLDELAY-1, n.dlycnt'length));
islwr := '1';
nstate := s_wrpwl;
end procedure go_wrpwl;
procedure go_pepwl(nstate : out state_type;
idly_ld : out slbit;
idly_val : out slv4;
ipktend : out slbit) is
begin
idly_ld := '1';
idly_val := slv(to_unsigned(WRPWLDELAY-1, n.dlycnt'length));
ipktend := '1';
nstate := s_pepwl;
end procedure go_pepwl;
begin
r := R_REGS;
n := R_REGS;
ififo_ce := '0';
ififo := "00";
irxfifo_ena := '0';
itxfifo_hold := '1';
islrd := '0';
islwr := '0';
isloe := '0';
ipktend := '0';
idata_cei := '0';
idata_ceo := '0';
idata_oe := '0';
imoni := fx2ctl_moni_init;
iflag_rdok := FX2_FLAG_N(c_flag_rx_ef); -- empty flag is act.low!
iflag_wrok := FX2_FLAG_N(c_flag_tx_ff); -- full flag is act.low!
idly_ld := '0';
idly_val := (others=>'0');
idly_end := '1';
idly_end1 := '0';
if unsigned(r.dlycnt) /= 0 then
idly_end := '0';
end if;
if unsigned(r.dlycnt) = 1 then
idly_end1 := '1';
end if;
case r.state is
when s_init => -- s_init:
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
when s_rdprep => -- s_rdprep: prepare read
if idly_end = '1' then
n.state := s_rdwait;
end if;
when s_rdwait => -- s_rdwait: wait for data
if r.pepend='1' and TXFIFO_VAL='0' then
go_peprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
elsif iflag_rdok='1' and
(RXFIFO_BUSY='0' and TXBUSY_L='0') then
go_rdpwl(n.state, idly_ld, idly_val, islrd);
elsif TXFIFO_VAL = '1' then
go_wrprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
end if;
when s_rdpwl => -- s_rdpwl: read, strobe low
idata_cei := '1';
isloe := '1';
if idly_end = '1' then
idly_ld := '1';
idly_val := slv(to_unsigned(RDPWHDELAY-1, n.dlycnt'length));
n.state := s_rdpwh;
else
islrd := '1';
n.state := s_rdpwl;
end if;
-- Note: data is sampled and written into rxfifo in 2nd last cycle in the
-- last cycle the rxfifo busy reflects therefore last written byte
-- and safely indicates whether another byte will fit.
when s_rdpwh => -- s_rdpwh: read, strobe high
idata_cei := '1';
isloe := '1';
if idly_end1 = '1' then -- 2nd last cycle
irxfifo_ena := '1'; -- capture rxdata
end if;
if idly_end = '1' then -- last cycle
if iflag_rdok='1' and
(RXFIFO_BUSY='0' and TXBUSY_L='0') then
go_rdpwl(n.state, idly_ld, idly_val, islrd);
elsif TXFIFO_VAL = '1' then
go_wrprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
else
n.state := s_rdwait;
end if;
end if;
when s_wrprep => -- s_wrprep: prepare write
if idly_end = '1' then
if iflag_wrok = '1' then
go_wrpwl(n.state, idly_ld, idly_val, islwr);
else
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
end if;
end if;
when s_wrpwl => -- s_wrpwl: write, strobe low
idata_ceo := '1';
idata_oe := '1';
if idly_end = '1' then
idata_ceo := '0';
itxfifo_hold := '0';
idly_ld := '1';
idly_val := slv(to_unsigned(WRPWHDELAY-1, n.dlycnt'length));
n.state := s_wrpwh;
else
islwr := '1';
n.state := s_wrpwl;
end if;
when s_wrpwh => -- s_wrpwh: write, strobe high
idata_oe := '1';
if idly_end = '1' then
if iflag_wrok='1' and TXFIFO_VAL='1' then
go_wrpwl(n.state, idly_ld, idly_val, islwr);
elsif iflag_wrok='1' and r.pepend='1' and TXFIFO_VAL='0' then
go_pepwl(n.state, idly_ld, idly_val, ipktend);
else
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
end if;
end if;
when s_peprep => -- s_peprep: prepare pktend
if idly_end = '1' then
if iflag_wrok = '1' then
go_pepwl(n.state, idly_ld, idly_val, ipktend);
else
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
end if;
end if;
when s_pepwl => -- s_pepwl: pktend, strobe low
if idly_end = '1' then
idly_ld := '1';
idly_val := slv(to_unsigned(WRPWHDELAY-1, n.dlycnt'length));
n.state := s_pepwh;
else
ipktend := '1';
n.state := s_pepwl;
end if;
when s_pepwh => -- s_pepwh: pktend, strobe high
if idly_end = '1' then
n.pepend := '0';
go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo);
end if;
when others => null;
end case;
if idly_ld = '1' then
n.dlycnt := idly_val;
elsif idly_end = '0' then
n.dlycnt := slv(unsigned(r.dlycnt) - 1);
end if;
-- pktend time-out handling:
-- if tx fifo is non-empty, set counter to max
-- if tx fifo is empty, count down every usec
-- on 1->0 transition queue pktend request
if TXFIFO_VAL = '1' then
n.petocnt := (others=>'1');
else
if CE_USEC = '1' and unsigned(r.petocnt) /= 0 then
n.petocnt := slv(unsigned(r.petocnt) - 1);
if unsigned(r.petocnt) = 1 then
n.pepend := '1';
end if;
end if;
end if;
n.moni_ep4_sel := '0';
n.moni_ep6_sel := '0';
if r.state = s_wrprep or r.state = s_wrpwl or r.state = s_wrpwh or
r.state = s_peprep or r.state = s_pepwl or r.state = s_pepwh then
n.moni_ep6_sel := '1';
n.moni_ep6_pf := not FX2_FLAG_N(c_flag_prog);
else
n.moni_ep4_sel := '1';
n.moni_ep4_pf := not FX2_FLAG_N(c_flag_prog);
end if;
imoni.fifo_ep4 := r.moni_ep4_sel;
imoni.fifo_ep6 := r.moni_ep6_sel;
imoni.flag_ep4_empty := not FX2_FLAG_N(c_flag_rx_ef);
imoni.flag_ep4_almost := r.moni_ep4_pf;
imoni.flag_ep6_full := not FX2_FLAG_N(c_flag_tx_ff);
imoni.flag_ep6_almost := r.moni_ep6_pf;
imoni.slrd := islrd;
imoni.slwr := islwr;
imoni.pktend := ipktend;
N_REGS <= n;
FX2_FIFO_CE <= ififo_ce;
FX2_FIFO <= ififo;
FX2_SLRD_N <= not islrd;
FX2_SLWR_N <= not islwr;
FX2_SLOE_N <= not isloe;
FX2_PKTEND_N <= not ipktend;
FX2_DATA_CEI <= idata_cei;
FX2_DATA_CEO <= idata_ceo;
FX2_DATA_OE <= idata_oe;
RXFIFO_ENA <= irxfifo_ena;
TXFIFO_HOLD <= itxfifo_hold;
MONI <= imoni;
end process proc_next;
proc_almost: process (RXSIZE, TXSIZE)
begin
-- (rx|tx)size is the number of bytes in fifo
-- --> rxsize is number of bytes which can be read
-- --> 2**txfawidth-txsize is is number of bytes which can be written
if unsigned(RXSIZE) <= RXAEMPTY_THRES then
RXAEMPTY <= '1';
else
RXAEMPTY <= '0';
end if;
if unsigned(TXSIZE) >= 2**TXFAWIDTH-TXAFULL_THRES then
TXAFULL <= '1';
else
TXAFULL <= '0';
end if;
end process proc_almost;
TXBUSY <= TXBUSY_L;
end syn;
|
gpl-2.0
|
9a4cd9c0ff321ba5a3f6da403ce26975
| 0.500447 | 3.432515 | false | false | false | false |
freecores/w11
|
rtl/sys_gen/w11a/s3board/sys_conf.vhd
| 2 | 2,739 |
-- $Id: sys_conf.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2007-2008 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_s3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2010-05-05 288 1.1.1 add sys_conf_hio_debounce
-- 2008-02-23 118 1.1 add memory config
-- 2007-09-23 84 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_ser2rri_cdinit : integer := 434-1; -- 50000000/115200
constant sys_conf_bram : integer := 0; -- no bram, use cache
constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB)
constant sys_conf_mem_losize : integer := 8#037777#; -- 1 MByte
--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug)
-- constant sys_conf_bram : integer := 1; -- bram only
-- constant sys_conf_bram_awidth : integer := 15; -- bram size (32 kB)
-- constant sys_conf_mem_losize : integer := 8#000777#; -- 32 kByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
end package sys_conf;
-- Note: mem_losize holds 16 MSB of the PA of the addressable memory
-- 2 211 111 111 110 000 000 000
-- 1 098 765 432 109 876 543 210
--
-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte
-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte
-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte
-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte
-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte
-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte
-- upper 256 kB excluded for 11/70 UB
|
gpl-2.0
|
9a5d0d832b5448062a05a4587f43435b
| 0.588901 | 3.656876 | false | false | false | false |
agostini01/FPGA_Neural-Network
|
source_files/neuralnet/core/nn_instance.vhd
| 1 | 5,645 |
--=============================================================================
-- This file is part of FPGA_NEURAL-Network.
--
-- FPGA_NEURAL-Network is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- FPGA_NEURAL-Network is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with FPGA_NEURAL-Network.
-- If not, see <http://www.gnu.org/licenses/>.
--=============================================================================
-- FILE NAME : nn_instance.vhd
-- PROJECT : FPGA_NEURAL-Network
-- ENTITY : NN_INSTANCE
-- ARCHITECTURE : structure
--=============================================================================
-- AUTORS(s) : Agostini, N; Barbosa, F
-- DEPARTMENT : Electrical Engineering (UFRGS)
-- DATE : Dec 12, 2014
--=============================================================================
-- Description:
--
--=============================================================================
library ieee;
use ieee.std_logic_1164.all;
use work.NN_TYPES_pkg.all;
use work.NN_CONSTANTS_pkg.all;
--=============================================================================
-- Entity declaration for NN_INSTANCE
--=============================================================================
entity NN_INSTANCE is
port (
clk : in std_logic;
NN_start : in std_logic;
NN_sample : in std_logic_vector (7 downto 0);
NN_result : out std_logic_vector (1 downto 0);
NN_expected : out std_logic_vector (1 downto 0);
NN_ready : out std_logic
);
end NN_INSTANCE;
--=============================================================================
-- architecture declaration
--=============================================================================
architecture structure of NN_INSTANCE is
-- Signals for the NEURAL NETWORK
signal START : std_logic;
signal CONTROL_IN, CONTROL_HIDDEN, CONTROL_OUT :std_logic;
signal DATA_READY : std_logic;
signal NN_INPUT : ARRAY_OF_SFIXED (0 to (PERCEPTRONS_INPUT-1));
signal NN_OUTPUT : ARRAY_OF_SFIXED (0 to (PERCEPTRONS_OUTPUT-1));
signal TARGET : ARRAY_OF_SFIXED (0 to PERCEPTRONS_OUTPUT-1); -- number of outputs: 3 for this example
component GENERIC_NEURAL_NET
generic (
NUMBER_OF_INPUT_NEURONS : natural;
NUMBER_OF_HIDDEN_NEURONS : natural;
NUMBER_OF_OUTPUT_NEURONS : natural;
WEIGHTS_MATRIX : FIXED_WEIGHTS_MATRIX
);
port (
INPUT :in ARRAY_OF_SFIXED;
CONTROL_IN, CONTROL_HIDDEN, CONTROL_OUT :in std_logic;
START, CLK :in std_logic;
OUTPUT :out ARRAY_OF_SFIXED;
DATA_READY :out std_logic
);
end component;
component INPUT_SELECT
port (
CLK : in std_logic;
SAMPLE_NUMBER : in std_logic_vector (7 downto 0);
NN_INPUT : out ARRAY_OF_SFIXED;
TARGET_VALUE : out ARRAY_OF_SFIXED
);
end component;
component OUTPUT_CONTROL
port (
CLK : in std_logic;
DATA_READY : in std_logic;
OUTPUT_READY : out std_logic;
NN_OUTPUT : in ARRAY_OF_SFIXED;
TARGET_VALUE : in ARRAY_OF_SFIXED;
NN_result : out std_logic_vector (1 downto 0);
NN_expected : out std_logic_vector (1 downto 0)
);
end component;
--=============================================================================
-- architecture begin
--=============================================================================
begin
--=============================================================================
-- OVERRIDE NN_RESULT FOR DEBUGGING
--=============================================================================
--NN_ready <= '1';
--NN_result <= "00";
--NN_expected <= "11";
--=============================================================================
-- OVERRIDE NN_RESULT FOR DEBUGGING
--=============================================================================
-- Signals Assigments
CONTROL_IN<='1';
CONTROL_HIDDEN<='1';
CONTROL_OUT<='1';
-- Components Assigments
GEN_NET: GENERIC_NEURAL_NET
generic map (
NUMBER_OF_INPUT_NEURONS => PERCEPTRONS_INPUT,
NUMBER_OF_HIDDEN_NEURONS => PERCEPTRONS_HIDDEN,
NUMBER_OF_OUTPUT_NEURONS => PERCEPTRONS_OUTPUT,
WEIGHTS_MATRIX=> FIXED_WEIGHTS_MATRIX_INSTANCE
)
port map (
INPUT => NN_INPUT,
CONTROL_IN => CONTROL_IN, CONTROL_HIDDEN => CONTROL_IN, CONTROL_OUT => CONTROL_IN,
START => START, CLK => CLK,
OUTPUT=> NN_OUTPUT,
DATA_READY => DATA_READY
);
IN_SELECTION: INPUT_SELECT
port map (
CLK => CLK,
SAMPLE_NUMBER => NN_sample,
NN_INPUT => NN_INPUT,
TARGET_VALUE => TARGET
);
OUTPUT_CTR: OUTPUT_CONTROL
port map (
CLK => CLK,
DATA_READY => DATA_READY,
OUTPUT_READY => NN_ready,
NN_OUTPUT => NN_OUTPUT,
TARGET_VALUE => TARGET,
NN_result => NN_result,
NN_expected => NN_expected
);
end structure;
--=============================================================================
-- architecture end
--=============================================================================
|
gpl-3.0
|
f7ac295bd34b6c7576eae1d99b42ff2a
| 0.479185 | 3.966971 | false | false | false | false |
freecores/w11
|
rtl/bplib/bpgen/sn_humanio_rbus.vhd
| 1 | 11,212 |
-- $Id: sn_humanio_rbus.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sn_humanio_rbus - syn
-- Description: sn_humanio with rbus interceptor
--
-- Dependencies: bpgen/sn_humanio
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-08-14 406 12.1 M53d xc3s1000-4 142 156 0 123 s 5.1 ns
-- 2011-08-07 404 12.1 M53d xc3s1000-4 142 157 0 124 s 5.1 ns
-- 2010-12-29 351 12.1 M53d xc3s1000-4 93 138 0 111 s 6.8 ns
-- 2010-06-03 300 11.4 L68 xc3s1000-4 92 137 0 111 s 6.7 ns
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.2.1 now numeric_std clean
-- 2011-08-14 406 1.2 common register layout with bp_swibtnled_rbus
-- 2011-08-07 404 1.3 add pipeline regs ledin,(swi,btn,led,dp,dat)eff
-- 2011-07-08 390 1.2 renamed from s3_humanio_rbus, add BWIDTH generic
-- 2010-12-29 351 1.1 renamed from s3_humanio_rri; ported to rbv3
-- 2010-06-18 306 1.0.1 rename rbus data fields to _rbf_
-- 2010-06-03 300 1.0 Initial version
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Address Bits Name r/w/f Function
-- bbbbbb00 cntl r/w/- Control register and BTN access
-- x:08 btn r/w/- r: return hio BTN status
-- w: ored with hio BTN to drive BTN
-- 3 dsp_en r/w/- if 1 display data will be driven by rbus
-- 2 dp_en r/w/- if 1 display dp's will be driven by rbus
-- 1 led_en r/w/- if 1 LED will be driven by rri
-- 0 swi_en r/w/- if 1 SWI will be driven by rri
--
-- bbbbbb01 7:00 swi r/w/- r: return hio SWI status
-- w: will drive SWI when swi_en=1
--
-- bbbbbb10 led r/w/- Interface to LED and DSP_DP
-- 15:12 dp r/w/- r: returns DSP_DP status
-- w: will drive display dp's when dp_en=1
-- 7:00 led r/w/- r: returns LED status
-- w: will drive led's when led_en=1
--
-- bbbbbb11 15:00 dsp r/w/- r: return hio DSP_DAT status
-- w: will drive DSP_DAT when dsp_en=1
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.bpgenlib.all;
-- ----------------------------------------------------------------------------
entity sn_humanio_rbus is -- human i/o handling /w rbus intercept
generic (
BWIDTH : positive := 4; -- BTN port width
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv8; -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv8; -- pad-o: leds
O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low)
);
end sn_humanio_rbus;
architecture syn of sn_humanio_rbus is
type regs_type is record
rbsel : slbit; -- rbus select
swi : slv8; -- rbus swi
btn : slv(BWIDTH-1 downto 0); -- rbus btn
led : slv8; -- rbus led
dsp_dat : slv16; -- rbus dsp_dat
dsp_dp : slv4; -- rbus dsp_dp
ledin : slv8; -- led from design
swieff : slv8; -- effective swi
btneff : slv(BWIDTH-1 downto 0); -- effective btn
ledeff : slv8; -- effective led
dpeff : slv4; -- effective dsp_dp
dateff : slv16; -- effective dsp_dat
swi_en : slbit; -- enable: swi from rbus
led_en : slbit; -- enable: led from rbus
dsp_en : slbit; -- enable: dsp_dat from rbus
dp_en : slbit; -- enable: dsp_dp from rbus
end record regs_type;
constant btnzero : slv(BWIDTH-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
'0', -- rbsel
(others=>'0'), -- swi
btnzero, -- btn
(others=>'0'), -- led
(others=>'0'), -- dsp_dat
(others=>'0'), -- dsp_dp
(others=>'0'), -- ledin
(others=>'0'), -- swieff
btnzero, -- btneff
(others=>'0'), -- ledeff
(others=>'0'), -- dpeff
(others=>'0'), -- dateff
'0','0','0','0' -- (swi|led|dsp|dp)_en
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
subtype cntl_rbf_btn is integer range BWIDTH+8-1 downto 8;
constant cntl_rbf_dsp_en: integer := 3;
constant cntl_rbf_dp_en: integer := 2;
constant cntl_rbf_led_en: integer := 1;
constant cntl_rbf_swi_en: integer := 0;
subtype led_rbf_dp is integer range 15 downto 12;
subtype led_rbf_led is integer range 7 downto 0;
constant rbaddr_cntl: slv2 := "00"; -- 0 r/w/-
constant rbaddr_swi: slv2 := "01"; -- 1 r/w/-
constant rbaddr_led: slv2 := "10"; -- 2 r/w/-
constant rbaddr_dsp: slv2 := "11"; -- 3 r/w/-
signal HIO_SWI : slv8 := (others=>'0');
signal HIO_BTN : slv(BWIDTH-1 downto 0) := (others=>'0');
signal HIO_LED : slv8 := (others=>'0');
signal HIO_DSP_DAT : slv16 := (others=>'0');
signal HIO_DSP_DP : slv4 := (others=>'0');
begin
HIO : sn_humanio
generic map (
BWIDTH => BWIDTH,
DEBOUNCE => DEBOUNCE)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => HIO_SWI,
BTN => HIO_BTN,
LED => HIO_LED,
DSP_DAT => HIO_DSP_DAT,
DSP_DP => HIO_DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, RB_MREQ, LED, DSP_DAT, DSP_DP,
HIO_SWI, HIO_BTN, HIO_DSP_DAT, HIO_DSP_DP)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
-- input register for LED signal
n.ledin := LED;
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(7 downto 2)=RB_ADDR(7 downto 2) then
n.rbsel := '1';
end if;
-- rbus transactions
if r.rbsel = '1' then
irb_ack := irbena; -- ack all accesses
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl =>
irb_dout(cntl_rbf_btn) := HIO_BTN;
irb_dout(cntl_rbf_dsp_en) := r.dsp_en;
irb_dout(cntl_rbf_dp_en) := r.dp_en;
irb_dout(cntl_rbf_led_en) := r.led_en;
irb_dout(cntl_rbf_swi_en) := r.swi_en;
if RB_MREQ.we = '1' then
n.btn := RB_MREQ.din(cntl_rbf_btn);
n.dsp_en := RB_MREQ.din(cntl_rbf_dsp_en);
n.dp_en := RB_MREQ.din(cntl_rbf_dp_en);
n.led_en := RB_MREQ.din(cntl_rbf_led_en);
n.swi_en := RB_MREQ.din(cntl_rbf_swi_en);
end if;
when rbaddr_swi =>
irb_dout(HIO_SWI'range) := HIO_SWI;
if RB_MREQ.we = '1' then
n.swi := RB_MREQ.din(n.swi'range);
end if;
when rbaddr_led =>
irb_dout(led_rbf_dp) := HIO_DSP_DP;
irb_dout(led_rbf_led) := r.ledin;
if RB_MREQ.we = '1' then
n.dsp_dp := RB_MREQ.din(led_rbf_dp);
n.led := RB_MREQ.din(led_rbf_led);
end if;
when rbaddr_dsp =>
irb_dout := HIO_DSP_DAT;
if RB_MREQ.we = '1' then
n.dsp_dat := RB_MREQ.din;
end if;
when others => null;
end case;
end if;
n.btneff := HIO_BTN or r.btn;
if r.swi_en = '0' then
n.swieff := HIO_SWI;
else
n.swieff := r.swi;
end if;
if r.led_en = '0' then
n.ledeff := r.ledin;
else
n.ledeff := r.led;
end if;
if r.dp_en = '0' then
n.dpeff := DSP_DP;
else
n.dpeff := r.dsp_dp;
end if;
if r.dsp_en = '0' then
n.dateff := DSP_DAT;
else
n.dateff := r.dsp_dat;
end if;
N_REGS <= n;
BTN <= R_REGS.btneff;
SWI <= R_REGS.swieff;
HIO_LED <= R_REGS.ledeff;
HIO_DSP_DP <= R_REGS.dpeff;
HIO_DSP_DAT <= R_REGS.dateff;
RB_SRES <= rb_sres_init;
RB_SRES.ack <= irb_ack;
RB_SRES.busy <= irb_busy;
RB_SRES.err <= irb_err;
RB_SRES.dout <= irb_dout;
end process proc_next;
end syn;
|
gpl-2.0
|
a1a9456dabc545abbb933617e9d54b7e
| 0.482875 | 3.406867 | false | false | false | false |
alphaFred/Sejits4Fpgas
|
sejits4fpgas/hw/user/SyncNode.vhd
| 1 | 2,718 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNIMACRO;
use UNIMACRO.vcomponents.all;
Library UNISIM;
use UNISIM.vcomponents.all;
-- All connected input streams must have the same width!
-- Input stream width = WIDTH/N_IO
entity SyncNode is
generic (
WIDTH : positive := 32;
N_IO : positive := 2;
DELAY : positive := 1
);
port (
CLK : in std_logic;
RST : in std_logic;
VALID_IN : in std_logic;
READY_IN : in std_logic;
SYNC_IN : in std_logic_vector((N_IO*WIDTH)-1 downto 0);
VALID_IN_PORT : in std_logic_vector(N_IO-1 downto 0);
VALID_OUT : out std_logic;
READY_OUT : out std_logic;
SYNC_OUT : out std_logic_vector((N_IO*WIDTH)-1 downto 0)
);
end SyncNode;
architecture arch of SyncNode is
signal SyncRE : std_logic := '0';
--
signal EMPTY_log : std_logic_vector(N_IO-1 downto 0);
signal FULL_log : std_logic_vector(N_IO-1 downto 0);
--
TYPE READ_D is array(2 downto 0) of std_logic;
signal read_delay : READ_D;
TYPE iBus_D is array(N_IO-1 downto 0) of std_logic_vector(WIDTH-1 downto 0);
signal data_in : iBus_D;
signal data_out : iBus_D;
--
component sync_fifo_32x64 is
port (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
end component;
function or_reduct(slv : in std_logic_vector) return std_logic is
variable res_v : std_logic := '0'; -- Null slv vector will also return '1'
begin
for i in slv'range loop
res_v := res_v or slv(i);
end loop;
return res_v;
end function;
begin
-- SyncRE <= VALID_IN AND READY_IN;
fifos: for i in 0 to N_IO-1 generate
begin
sync_fifo_inst : component sync_fifo_32x64
port map(
clk => CLK,
rst => RST,
din => data_in(i),
wr_en => VALID_IN_PORT(i),
rd_en => SyncRE,
dout => data_out(i),
full => FULL_log(i),
empty => EMPTY_log(i)
);
end generate fifos;
data_in(0) <= SYNC_IN(31 downto 0);
data_in(1) <= SYNC_IN(63 downto 32);
SyncRE <= (NOT or_reduct(EMPTY_log)) AND READY_IN;
SYNC_OUT(31 downto 0) <= data_out(0);
SYNC_OUT(63 downto 32) <= data_out(1);
--
READY_OUT <= READY_IN AND (NOT or_reduct(FULL_log));
VALID_OUT <= SyncRE;
end architecture ; -- arch
|
gpl-3.0
|
0a2d30da348d1abb25bc03eddd22e801
| 0.555188 | 3.314634 | false | false | false | false |
freecores/w11
|
rtl/bplib/fx2rlink/ioleds_sp1c_fx2.vhd
| 1 | 3,361 |
-- $Id: ioleds_sp1c_fx2.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ioleds_sp1c_fx2 - syn
-- Description: io activity leds for rlink+serport_1clk+fx2_ic combo
--
-- Dependencies:
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.genlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.serportlib.all;
entity ioleds_sp1c_fx2 is -- io activity leds for rlink_sp1c_fx2
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit; -- reset
ENAFX2 : in slbit; -- enable fx2 usage
RB_SRES : in rb_sres_type; -- rbus: response
RLB_MONI : in rlb_moni_type; -- rlink 8b: monitor port
SER_MONI : in serport_moni_type; -- ser: monitor port
IOLEDS : out slv4 -- 4 bit IO monitor (e.g. for DSP_DP)
);
end entity ioleds_sp1c_fx2;
architecture syn of ioleds_sp1c_fx2 is
signal R_LEDDIV : slv6 := (others=>'0'); -- clock divider for LED pulses
signal R_LEDCE : slbit := '0'; -- ce every 64 usec
signal TXENA_LED : slbit := '0';
signal RXVAL_LED : slbit := '0';
begin
RXVAL_PSTR : led_pulse_stretch
port map (
CLK => CLK,
CE_INT => R_LEDCE,
RESET => '0',
DIN => RLB_MONI.rxval,
POUT => RXVAL_LED
);
TXENA_PSTR : led_pulse_stretch
port map (
CLK => CLK,
CE_INT => R_LEDCE,
RESET => '0',
DIN => RLB_MONI.txena,
POUT => TXENA_LED
);
proc_leddiv: process (CLK)
begin
if rising_edge(CLK) then
R_LEDCE <= '0';
if CE_USEC = '1' then
R_LEDDIV <= slv(unsigned(R_LEDDIV) - 1);
if unsigned(R_LEDDIV) = 0 then
R_LEDCE <= '1';
end if;
end if;
end if;
end process proc_leddiv;
proc_ledmux : process (ENAFX2, SER_MONI, RLB_MONI, RB_SRES,
TXENA_LED, RXVAL_LED)
begin
if ENAFX2 = '0' then
IOLEDS(3) <= not SER_MONI.txok;
IOLEDS(2) <= SER_MONI.txact;
IOLEDS(1) <= not SER_MONI.rxok;
IOLEDS(0) <= SER_MONI.rxact;
else
IOLEDS(3) <= RB_SRES.busy;
IOLEDS(2) <= RLB_MONI.txbusy;
IOLEDS(1) <= TXENA_LED;
IOLEDS(0) <= RXVAL_LED;
end if;
end process proc_ledmux;
end syn;
|
gpl-2.0
|
b193279efe44f41f36184c757fa2b695
| 0.549539 | 3.537895 | false | false | false | false |
agostini01/FPGA_Neural-Network
|
source_files/neuralnet/sigmoid/sigmoid_select.vhd
| 1 | 3,480 |
--=============================================================================
-- This file is part of FPGA_NEURAL-Network.
--
-- FPGA_NEURAL-Network is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- FPGA_NEURAL-Network is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with FPGA_NEURAL-Network.
-- If not, see <http://www.gnu.org/licenses/>.
--=============================================================================
-- FILE NAME : input_select.vhd
-- PROJECT : FPGA_NEURAL-Network
-- ENTITY : SIGMOID_SELECT
-- ARCHITECTURE : structure
--=============================================================================
-- AUTORS(s) : Agostini, N;
-- DEPARTMENT : Electrical Engineering (UFRGS)
-- DATE : Dec 14, 2014
--=============================================================================
-- Description:
--
--=============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- is the to unsigned really required????
use work.fixed_pkg.all; -- ieee_proposed for compatibility version
use work.SIGMOID_ROM_pkg.all;
use work.NN_TYPES_pkg.all;
--=============================================================================
-- Entity declaration for SIGMOID_SELECT
--=============================================================================
entity SIGMOID_SELECT is
port (
CLK : in std_logic;
X_VALUE : in CONSTRAINED_SFIXED;
Y_VALUE : out CONSTRAINED_SFIXED
);
end SIGMOID_SELECT;
--=============================================================================
-- architecture declaration
--=============================================================================
architecture STRUCTURE of SIGMOID_SELECT is
-- Signals
signal SAMPLE_NUMBER : std_logic_vector ((NUMBER_OF_BITS-1) downto 0);
signal IN_UNSIGNED : unsigned((NUMBER_OF_BITS-1) downto 0);
-- Components
component SIGMOID_ROM
port (
clk : in std_logic;
X_VALUE : in std_logic_vector ((NUMBER_OF_BITS-1) downto 0);
Y_VALUE : out CONSTRAINED_SFIXED
);
end component;
--=============================================================================
-- architecture begin
--=============================================================================
begin
ROM: SIGMOID_ROM
port map (
CLK => CLK,
X_VALUE => SAMPLE_NUMBER,
Y_VALUE => Y_VALUE
);
IN_UNSIGNED <= unsigned(to_slv(resize(X_VALUE,3,-(NUMBER_OF_BITS-4))));
SAMPLE_NUMBER <=
std_logic_vector(to_unsigned(0, NUMBER_OF_BITS)) when X_VALUE <= -3 -- limits from the tansig function where it almost saturates
else
std_logic_vector(to_unsigned(VECTOR_SIZE, NUMBER_OF_BITS)) when X_VALUE >= 3
else
std_logic_vector(IN_UNSIGNED);
end STRUCTURE;
--=============================================================================
-- architecture end
--=============================================================================
|
gpl-3.0
|
53db9e40c34c3d531091d4a9cf6567f0
| 0.476149 | 4.473008 | false | false | false | false |
freecores/w11
|
rtl/ibus/ibdr_pc11.vhd
| 1 | 12,870 |
-- $Id: ibdr_pc11.vhd 515 2013-05-04 17:28:59Z mueller $
--
-- Copyright 2009-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ibdr_pc11 - syn
-- Description: ibus dev(rem): PC11
--
-- Dependencies: -
-- Test bench: xxdp: zpcae0
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.3; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 26 97 0 57 s 6.0
-- 2009-06-28 230 10.1.03 K39 xc3s1000-4 25 92 0 54 s 4.9
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-05-04 515 1.3 BUGFIX: r.rbuf was immediately cleared ! Was broken
-- since ibus V2 update, never tested afterwards...
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-06-28 230 1.0 prdy now inits to '1'; setting err bit in csr now
-- causes interrupt, if enabled; validated with zpcae0
-- 2009-06-01 221 0.9 Initial version (untested)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_pc11 is -- ibus dev(rem): PC11
-- fixed address: 177550
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_PTR : out slbit; -- interrupt request, reader
EI_REQ_PTP : out slbit; -- interrupt request, punch
EI_ACK_PTR : in slbit; -- interrupt acknowledge, reader
EI_ACK_PTP : in slbit -- interrupt acknowledge, punch
);
end ibdr_pc11;
architecture syn of ibdr_pc11 is
constant ibaddr_pc11 : slv16 := slv(to_unsigned(8#177550#,16));
constant ibaddr_rcsr : slv2 := "00"; -- rcsr address offset
constant ibaddr_rbuf : slv2 := "01"; -- rbuf address offset
constant ibaddr_pcsr : slv2 := "10"; -- pcsr address offset
constant ibaddr_pbuf : slv2 := "11"; -- pbuf address offset
constant rcsr_ibf_rerr : integer := 15;
constant rcsr_ibf_rbusy : integer := 11;
constant rcsr_ibf_rdone : integer := 7;
constant rcsr_ibf_rie : integer := 6;
constant rcsr_ibf_renb : integer := 0;
constant pcsr_ibf_perr : integer := 15;
constant pcsr_ibf_prdy : integer := 7;
constant pcsr_ibf_pie : integer := 6;
constant pbuf_ibf_pval : integer := 8;
constant pbuf_ibf_rbusy : integer := 9;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
rerr : slbit; -- rcsr: reader error
rbusy : slbit; -- rcsr: reader busy
rdone : slbit; -- rcsr: reader done
rie : slbit; -- rcsr: reader interrupt enable
rbuf : slv8; -- rbuf:
rintreq : slbit; -- ptr interrupt request
perr : slbit; -- pcsr: punch error
prdy : slbit; -- pcsr: punch ready
pie : slbit; -- pcsr: punch interrupt enable
pbuf : slv8; -- pbuf:
pintreq : slbit; -- ptp interrupt request
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
'1', -- rerr (init=1!)
'0','0','0', -- rbusy,rdone,rie
(others=>'0'), -- rbuf
'0', -- rintreq
'1', -- perr (init=1!)
'1', -- prdy (init=1!)
'0', -- pie
(others=>'0'), -- pbuf
'0' -- pintreq
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then -- BRESET is 1 for system and ibus reset
R_REGS <= regs_init; --
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.rerr <= N_REGS.rerr; -- don't reset RERR flag
R_REGS.perr <= N_REGS.perr; -- don't reset PERR flag
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, EI_ACK_PTR, EI_ACK_PTP)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ilam : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ilam := '0';
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 3)=ibaddr_pc11(12 downto 3) then
n.ibsel := '1';
end if;
-- ibus transactions
if r.ibsel = '1' then
case IB_MREQ.addr(2 downto 1) is
when ibaddr_rcsr => -- RCSR -- reader control status -----
idout(rcsr_ibf_rerr) := r.rerr;
idout(rcsr_ibf_rbusy) := r.rbusy;
idout(rcsr_ibf_rdone) := r.rdone;
idout(rcsr_ibf_rie) := r.rie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.rie := IB_MREQ.din(rcsr_ibf_rie);
if IB_MREQ.din(rcsr_ibf_rie) = '1' then-- set IE to 1
if r.rie = '0' and -- IE 0->1 transition
IB_MREQ.din(rcsr_ibf_renb)='0' and -- when RENB not set
(r.rerr='1' or r.rdone='1') then -- but err or done set
n.rintreq := '1'; -- request interrupt
end if;
else -- set IE to 0
n.rintreq := '0'; -- cancel interrupts
end if;
if IB_MREQ.din(rcsr_ibf_renb) = '1' then -- set RENB
if r.rerr = '0' then -- if not in error state
n.rbusy := '1'; -- set busy
n.rdone := '0'; -- clear done
n.rbuf := (others=>'0'); -- clear buffer
n.rintreq := '0'; -- cancel interrupt
ilam := '1'; -- rri lam
else -- if in error state
if r.rie = '1' then -- if interrupts on
n.rintreq := '1'; -- request interrupt
end if;
end if;
end if;
end if;
else -- rri ---------------------
if ibw1 = '1' then
n.rerr := IB_MREQ.din(rcsr_ibf_rerr); -- set ERR bit
if IB_MREQ.din(rcsr_ibf_rerr)='1' -- if 0->1 transition
and r.rerr='0' then
n.rbusy := '0'; -- clear busy
n.rdone := '0'; -- clear done
if r.rie = '1' then -- if interrupts on
n.rintreq := '1'; -- request interrupt
end if;
end if;
end if;
end if;
when ibaddr_rbuf => -- RBUF -- reader data buffer --------
idout(r.rbuf'range) := r.rbuf;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibreq = '1' then -- !! PC11 is unusual !!
n.rdone := '0'; -- *any* read or write will clear done
n.rbuf := (others=>'0'); -- and the reader buffer
n.rintreq := '0'; -- also interrupt is canceled
end if;
else -- rri ---------------------
if ibw0 = '1' then
n.rbuf := IB_MREQ.din(n.rbuf'range);
n.rbusy := '0';
n.rdone := '1';
if r.rie = '1' then
n.rintreq := '1';
end if;
end if;
end if;
when ibaddr_pcsr => -- PCSR -- punch control status ------
idout(pcsr_ibf_perr) := r.perr;
idout(pcsr_ibf_prdy) := r.prdy;
idout(pcsr_ibf_pie) := r.pie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.pie := IB_MREQ.din(pcsr_ibf_pie);
if IB_MREQ.din(pcsr_ibf_pie) = '1' then-- set IE to 1
if r.pie='0' and -- IE 0->1 transition
(r.perr='1' or r.prdy='1') then -- but err or done set
n.pintreq := '1'; -- request interrupt
end if;
else -- set IE to 0
n.pintreq := '0'; -- cancel interrupts
end if;
end if;
else -- rri ---------------------
if ibw1 = '1' then
n.perr := IB_MREQ.din(pcsr_ibf_perr); -- set ERR bit
if IB_MREQ.din(pcsr_ibf_perr)='1' -- if 0->1 transition
and r.perr='0' then
n.prdy := '1'; -- set ready
if r.pie = '1' then -- if interrupts on
n.pintreq := '1'; -- request interrupt
end if;
end if;
end if;
end if;
when ibaddr_pbuf => -- PBUF -- punch data buffer ---------
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
if r.perr = '0' then -- if not in error state
n.pbuf := IB_MREQ.din(n.pbuf'range);
n.prdy := '0'; -- clear ready
n.pintreq := '0'; -- cancel interrupts
ilam := '1'; -- rri lam
else -- if in error state
if r.pie = '1' then -- if interrupts on
n.pintreq := '1'; -- request interrupt
end if;
end if;
end if;
else -- rri ---------------------
idout(r.pbuf'range) := r.pbuf;
idout(pbuf_ibf_pval) := not r.prdy;
idout(pbuf_ibf_rbusy) := r.rbusy;
if ibrd = '1' then
n.prdy := '1';
if r.pie = '1' then
n.pintreq := '1';
end if;
end if;
end if;
when others => null;
end case;
end if;
-- other state changes
if EI_ACK_PTR = '1' then
n.rintreq := '0';
end if;
if EI_ACK_PTP = '1' then
n.pintreq := '0';
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= '0';
RB_LAM <= ilam;
EI_REQ_PTR <= r.rintreq;
EI_REQ_PTP <= r.pintreq;
end process proc_next;
end syn;
|
gpl-2.0
|
5140a79060c86d7506c831a977c94421
| 0.429992 | 4.057377 | false | false | false | false |
GOOD-Stuff/srio_test
|
srio_test.cache/ip/e31747a7077a3e80/fifo_generator_0_sim_netlist.vhdl
| 1 | 322,265 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Mon Sep 18 12:52:54 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_0_sim_netlist.vhdl
-- Design : fifo_generator_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 35 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc1.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 35 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => Q(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 5) => \gc1.count_d2_reg[9]\(9 downto 0),
ADDRBWRADDR(4 downto 0) => B"11111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => wr_clk,
CLKBWRCLK => rd_clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 24) => din(34 downto 27),
DIADI(23 downto 16) => din(25 downto 18),
DIADI(15 downto 8) => din(16 downto 9),
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3) => din(35),
DIPADIP(2) => din(26),
DIPADIP(1) => din(17),
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 24) => dout(34 downto 27),
DOBDO(23 downto 16) => dout(25 downto 18),
DOBDO(15 downto 8) => dout(16 downto 9),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3) => dout(35),
DOPBDOP(2) => dout(26),
DOPBDOP(1) => dout(17),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => WEA(0),
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => WEA(0),
WEA(2) => WEA(0),
WEA(1) => WEA(0),
WEA(0) => WEA(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 27 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc1.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => Q(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 5) => \gc1.count_d2_reg[9]\(9 downto 0),
ADDRBWRADDR(4 downto 0) => B"11111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => wr_clk,
CLKBWRCLK => rd_clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30 downto 24) => din(27 downto 21),
DIADI(23) => '0',
DIADI(22 downto 16) => din(20 downto 14),
DIADI(15) => '0',
DIADI(14 downto 8) => din(13 downto 7),
DIADI(7) => '0',
DIADI(6 downto 0) => din(6 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53\,
DOBDO(30 downto 24) => dout(27 downto 21),
DOBDO(23) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61\,
DOBDO(22 downto 16) => dout(20 downto 14),
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69\,
DOBDO(14 downto 8) => dout(13 downto 7),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\,
DOBDO(6 downto 0) => dout(6 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89\,
DOPBDOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => WEA(0),
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => WEA(0),
WEA(2) => WEA(0),
WEA(1) => WEA(0),
WEA(0) => WEA(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 is
port (
comp2 : out STD_LOGIC;
ram_full_i_reg : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
\out\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
comp1 : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \^comp2\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
comp2 <= \^comp2\;
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => \^comp2\,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_0(4)
);
ram_full_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FF20"
)
port map (
I0 => \^comp2\,
I1 => \out\,
I2 => wr_en,
I3 => comp1,
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
O => ram_full_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 is
port (
\gaf.ram_almost_full_i_reg\ : out STD_LOGIC;
v1_reg_1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_en : in STD_LOGIC;
comp2 : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\out\ : in STD_LOGIC;
almost_full : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gaf.ram_almost_full_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FF00F8000000F8"
)
port map (
I0 => comp3,
I1 => wr_en,
I2 => comp2,
I3 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I4 => \out\,
I5 => almost_full,
O => \gaf.ram_almost_full_i_reg\
);
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_1(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp3,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_1(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 is
port (
ram_empty_i0 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC;
comp1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
ram_empty_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"AEAA"
)
port map (
I0 => comp0,
I1 => rd_en,
I2 => \out\,
I3 => comp1,
O => ram_empty_i0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_6 is
port (
comp1 : out STD_LOGIC;
\gae.ram_almost_empty_i_reg\ : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_en : in STD_LOGIC;
comp2 : in STD_LOGIC;
\out\ : in STD_LOGIC;
almost_empty : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_6 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_6;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_6 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \^comp1\ : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
comp1 <= \^comp1\;
\gae.ram_almost_empty_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEA00EA"
)
port map (
I0 => \^comp1\,
I1 => rd_en,
I2 => comp2,
I3 => \out\,
I4 => almost_empty,
O => \gae.ram_almost_empty_i_reg\
);
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => \^comp1\,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_0(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_7 is
port (
comp2 : out STD_LOGIC;
v1_reg_1 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_7 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_7;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_7 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_1(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp2,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_1(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
\gc1.count_d2_reg[9]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gc1.count[9]_i_2_n_0\ : STD_LOGIC;
signal \^gc1.count_d2_reg[9]_0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc1.count[0]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc1.count[2]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc1.count[3]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gc1.count[4]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gc1.count[6]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc1.count[7]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc1.count[8]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gc1.count[9]_i_1\ : label is "soft_lutpair8";
begin
Q(9 downto 0) <= \^q\(9 downto 0);
\gc1.count_d2_reg[9]_0\(9 downto 0) <= \^gc1.count_d2_reg[9]_0\(9 downto 0);
\gc1.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gc1.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__0\(1)
);
\gc1.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => \plusOp__0\(2)
);
\gc1.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => \plusOp__0\(3)
);
\gc1.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => \plusOp__0\(4)
);
\gc1.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => \plusOp__0\(5)
);
\gc1.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gc1.count[9]_i_2_n_0\,
I1 => \^q\(6),
O => \plusOp__0\(6)
);
\gc1.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gc1.count[9]_i_2_n_0\,
I1 => \^q\(6),
I2 => \^q\(7),
O => \plusOp__0\(7)
);
\gc1.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(6),
I1 => \gc1.count[9]_i_2_n_0\,
I2 => \^q\(7),
I3 => \^q\(8),
O => \plusOp__0\(8)
);
\gc1.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(7),
I1 => \gc1.count[9]_i_2_n_0\,
I2 => \^q\(6),
I3 => \^q\(8),
I4 => \^q\(9),
O => \plusOp__0\(9)
);
\gc1.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(5),
I1 => \^q\(3),
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \^q\(2),
I5 => \^q\(4),
O => \gc1.count[9]_i_2_n_0\
);
\gc1.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gc1.count_d2_reg[9]_0\(0)
);
\gc1.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gc1.count_d2_reg[9]_0\(1)
);
\gc1.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gc1.count_d2_reg[9]_0\(2)
);
\gc1.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gc1.count_d2_reg[9]_0\(3)
);
\gc1.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(4),
Q => \^gc1.count_d2_reg[9]_0\(4)
);
\gc1.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(5),
Q => \^gc1.count_d2_reg[9]_0\(5)
);
\gc1.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(6),
Q => \^gc1.count_d2_reg[9]_0\(6)
);
\gc1.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(7),
Q => \^gc1.count_d2_reg[9]_0\(7)
);
\gc1.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(8),
Q => \^gc1.count_d2_reg[9]_0\(8)
);
\gc1.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(9),
Q => \^gc1.count_d2_reg[9]_0\(9)
);
\gc1.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^gc1.count_d2_reg[9]_0\(0),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(0)
);
\gc1.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^gc1.count_d2_reg[9]_0\(1),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(1)
);
\gc1.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^gc1.count_d2_reg[9]_0\(2),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(2)
);
\gc1.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^gc1.count_d2_reg[9]_0\(3),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(3)
);
\gc1.count_d2_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^gc1.count_d2_reg[9]_0\(4),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(4)
);
\gc1.count_d2_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^gc1.count_d2_reg[9]_0\(5),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(5)
);
\gc1.count_d2_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^gc1.count_d2_reg[9]_0\(6),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(6)
);
\gc1.count_d2_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^gc1.count_d2_reg[9]_0\(7),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(7)
);
\gc1.count_d2_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^gc1.count_d2_reg[9]_0\(8),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(8)
);
\gc1.count_d2_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^gc1.count_d2_reg[9]_0\(9),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9)
);
\gc1.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(0),
Q => \^q\(0)
);
\gc1.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => \plusOp__0\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gc1.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => \^q\(2)
);
\gc1.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => \^q\(3)
);
\gc1.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(4),
Q => \^q\(4)
);
\gc1.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(5),
Q => \^q\(5)
);
\gc1.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(6),
Q => \^q\(6)
);
\gc1.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(7),
Q => \^q\(7)
);
\gc1.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(8),
Q => \^q\(8)
);
\gc1.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(9),
Q => \^q\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as is
port (
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[8]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as is
begin
\rd_dc_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(0),
Q => rd_data_count(0)
);
\rd_dc_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(1),
Q => rd_data_count(1)
);
\rd_dc_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(2),
Q => rd_data_count(2)
);
\rd_dc_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(3),
Q => rd_data_count(3)
);
\rd_dc_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(4),
Q => rd_data_count(4)
);
\rd_dc_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(5),
Q => rd_data_count(5)
);
\rd_dc_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(6),
Q => rd_data_count(6)
);
\rd_dc_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(7),
Q => rd_data_count(7)
);
\rd_dc_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(8),
Q => rd_data_count(8)
);
\rd_dc_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(9),
Q => rd_data_count(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as is
port (
prog_empty : out STD_LOGIC;
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as is
signal \gdiff.diff_pntr_pad_reg_n_0_[10]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[1]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[2]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[3]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[4]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[5]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[6]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[7]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[8]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[9]\ : STD_LOGIC;
signal \gpe1.prog_empty_i_i_1_n_0\ : STD_LOGIC;
signal \gpe1.prog_empty_i_i_2_n_0\ : STD_LOGIC;
signal \gpe1.prog_empty_i_i_3_n_0\ : STD_LOGIC;
signal \^prog_empty\ : STD_LOGIC;
begin
prog_empty <= \^prog_empty\;
\gdiff.diff_pntr_pad_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(9),
Q => \gdiff.diff_pntr_pad_reg_n_0_[10]\
);
\gdiff.diff_pntr_pad_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(0),
Q => \gdiff.diff_pntr_pad_reg_n_0_[1]\
);
\gdiff.diff_pntr_pad_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(1),
Q => \gdiff.diff_pntr_pad_reg_n_0_[2]\
);
\gdiff.diff_pntr_pad_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(2),
Q => \gdiff.diff_pntr_pad_reg_n_0_[3]\
);
\gdiff.diff_pntr_pad_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(3),
Q => \gdiff.diff_pntr_pad_reg_n_0_[4]\
);
\gdiff.diff_pntr_pad_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(4),
Q => \gdiff.diff_pntr_pad_reg_n_0_[5]\
);
\gdiff.diff_pntr_pad_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(5),
Q => \gdiff.diff_pntr_pad_reg_n_0_[6]\
);
\gdiff.diff_pntr_pad_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(6),
Q => \gdiff.diff_pntr_pad_reg_n_0_[7]\
);
\gdiff.diff_pntr_pad_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(7),
Q => \gdiff.diff_pntr_pad_reg_n_0_[8]\
);
\gdiff.diff_pntr_pad_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(8),
Q => \gdiff.diff_pntr_pad_reg_n_0_[9]\
);
\gpe1.prog_empty_i_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F202"
)
port map (
I0 => \gpe1.prog_empty_i_i_2_n_0\,
I1 => \gpe1.prog_empty_i_i_3_n_0\,
I2 => \out\,
I3 => \^prog_empty\,
O => \gpe1.prog_empty_i_i_1_n_0\
);
\gpe1.prog_empty_i_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \gdiff.diff_pntr_pad_reg_n_0_[9]\,
I1 => \gdiff.diff_pntr_pad_reg_n_0_[10]\,
I2 => \gdiff.diff_pntr_pad_reg_n_0_[8]\,
I3 => \gdiff.diff_pntr_pad_reg_n_0_[7]\,
O => \gpe1.prog_empty_i_i_2_n_0\
);
\gpe1.prog_empty_i_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFEA"
)
port map (
I0 => \gdiff.diff_pntr_pad_reg_n_0_[4]\,
I1 => \gdiff.diff_pntr_pad_reg_n_0_[1]\,
I2 => \gdiff.diff_pntr_pad_reg_n_0_[2]\,
I3 => \gdiff.diff_pntr_pad_reg_n_0_[3]\,
I4 => \gdiff.diff_pntr_pad_reg_n_0_[6]\,
I5 => \gdiff.diff_pntr_pad_reg_n_0_[5]\,
O => \gpe1.prog_empty_i_i_3_n_0\
);
\gpe1.prog_empty_i_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \gpe1.prog_empty_i_i_1_n_0\,
PRE => AR(0),
Q => \^prog_empty\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
rd_clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
wr_clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\ is
port (
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\ : entity is "synchronizer_ff";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
D(9 downto 0) <= Q_reg(9 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(9),
Q => Q_reg(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\ is
port (
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\ : entity is "synchronizer_ff";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
D(9 downto 0) <= Q_reg(9 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(9),
Q => Q_reg(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.wr_pntr_bin_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\ : entity is "synchronizer_ff";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
signal \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
\out\(0) <= Q_reg(9);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(9),
Q => Q_reg(9)
);
\gnxpm_cdc.wr_pntr_bin[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(1),
I1 => Q_reg(0),
I2 => Q_reg(2),
I3 => \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0\,
I4 => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\,
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(0)
);
\gnxpm_cdc.wr_pntr_bin[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(3),
I2 => Q_reg(9),
O => \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0\
);
\gnxpm_cdc.wr_pntr_bin[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(9),
I2 => Q_reg(3),
I3 => Q_reg(4),
I4 => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\,
I5 => Q_reg(1),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(1)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\,
I1 => Q_reg(4),
I2 => Q_reg(3),
I3 => Q_reg(9),
I4 => Q_reg(2),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(2)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(6),
I3 => Q_reg(5),
O => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\
);
\gnxpm_cdc.wr_pntr_bin[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(9),
I1 => Q_reg(3),
I2 => Q_reg(4),
I3 => \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0\,
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(3)
);
\gnxpm_cdc.wr_pntr_bin[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(5),
I1 => Q_reg(6),
O => \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0\
);
\gnxpm_cdc.wr_pntr_bin[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(4),
I2 => Q_reg(5),
I3 => Q_reg(9),
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(4)
);
\gnxpm_cdc.wr_pntr_bin[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(5),
I2 => Q_reg(6),
I3 => Q_reg(9),
I4 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(5)
);
\gnxpm_cdc.wr_pntr_bin[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(9),
I3 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(6)
);
\gnxpm_cdc.wr_pntr_bin[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(9),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(7)
);
\gnxpm_cdc.wr_pntr_bin[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(9),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\ : entity is "synchronizer_ff";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
signal \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
\out\(0) <= Q_reg(9);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(9),
Q => Q_reg(9)
);
\gnxpm_cdc.rd_pntr_bin[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(1),
I1 => Q_reg(0),
I2 => Q_reg(2),
I3 => \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0\,
I4 => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\,
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(0)
);
\gnxpm_cdc.rd_pntr_bin[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(3),
I2 => Q_reg(9),
O => \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0\
);
\gnxpm_cdc.rd_pntr_bin[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(9),
I2 => Q_reg(3),
I3 => Q_reg(4),
I4 => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\,
I5 => Q_reg(1),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(1)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\,
I1 => Q_reg(4),
I2 => Q_reg(3),
I3 => Q_reg(9),
I4 => Q_reg(2),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(2)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(6),
I3 => Q_reg(5),
O => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\
);
\gnxpm_cdc.rd_pntr_bin[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(9),
I1 => Q_reg(3),
I2 => Q_reg(4),
I3 => \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0\,
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(3)
);
\gnxpm_cdc.rd_pntr_bin[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(5),
I1 => Q_reg(6),
O => \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0\
);
\gnxpm_cdc.rd_pntr_bin[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(4),
I2 => Q_reg(5),
I3 => Q_reg(9),
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(4)
);
\gnxpm_cdc.rd_pntr_bin[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(5),
I2 => Q_reg(6),
I3 => Q_reg(9),
I4 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(5)
);
\gnxpm_cdc.rd_pntr_bin[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(9),
I3 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(6)
);
\gnxpm_cdc.rd_pntr_bin[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(9),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(7)
);
\gnxpm_cdc.rd_pntr_bin[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(9),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
port (
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : out STD_LOGIC_VECTOR ( 8 downto 0 );
\gdiff.diff_pntr_pad_reg[8]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gdiff.diff_pntr_pad_reg[10]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wr_data_count_i_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
\wr_data_count_i_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wr_data_count_i_reg[9]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_1 : out STD_LOGIC_VECTOR ( 4 downto 0 );
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 9 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.simple_prim36.ram\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \gic0.gc1.count[9]_i_2_n_0\ : STD_LOGIC;
signal p_13_out : STD_LOGIC_VECTOR ( 9 to 9 );
signal \plusOp__1\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal wr_pntr_plus3 : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc1.count[0]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gic0.gc1.count[1]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gic0.gc1.count[3]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gic0.gc1.count[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gic0.gc1.count[6]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc1.count[7]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc1.count[8]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gic0.gc1.count[9]_i_1\ : label is "soft_lutpair12";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) <= \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9 downto 0);
Q(8 downto 0) <= \^q\(8 downto 0);
\gic0.gc1.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => wr_pntr_plus3(0),
O => \plusOp__1\(0)
);
\gic0.gc1.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => wr_pntr_plus3(0),
I1 => wr_pntr_plus3(1),
O => \plusOp__1\(1)
);
\gic0.gc1.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => wr_pntr_plus3(0),
I1 => wr_pntr_plus3(1),
I2 => wr_pntr_plus3(2),
O => \plusOp__1\(2)
);
\gic0.gc1.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => wr_pntr_plus3(1),
I1 => wr_pntr_plus3(0),
I2 => wr_pntr_plus3(2),
I3 => wr_pntr_plus3(3),
O => \plusOp__1\(3)
);
\gic0.gc1.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => wr_pntr_plus3(2),
I1 => wr_pntr_plus3(0),
I2 => wr_pntr_plus3(1),
I3 => wr_pntr_plus3(3),
I4 => wr_pntr_plus3(4),
O => \plusOp__1\(4)
);
\gic0.gc1.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => wr_pntr_plus3(3),
I1 => wr_pntr_plus3(1),
I2 => wr_pntr_plus3(0),
I3 => wr_pntr_plus3(2),
I4 => wr_pntr_plus3(4),
I5 => wr_pntr_plus3(5),
O => \plusOp__1\(5)
);
\gic0.gc1.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc1.count[9]_i_2_n_0\,
I1 => wr_pntr_plus3(6),
O => \plusOp__1\(6)
);
\gic0.gc1.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gic0.gc1.count[9]_i_2_n_0\,
I1 => wr_pntr_plus3(6),
I2 => wr_pntr_plus3(7),
O => \plusOp__1\(7)
);
\gic0.gc1.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => wr_pntr_plus3(6),
I1 => \gic0.gc1.count[9]_i_2_n_0\,
I2 => wr_pntr_plus3(7),
I3 => wr_pntr_plus3(8),
O => \plusOp__1\(8)
);
\gic0.gc1.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => wr_pntr_plus3(7),
I1 => \gic0.gc1.count[9]_i_2_n_0\,
I2 => wr_pntr_plus3(6),
I3 => wr_pntr_plus3(8),
I4 => wr_pntr_plus3(9),
O => \plusOp__1\(9)
);
\gic0.gc1.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => wr_pntr_plus3(5),
I1 => wr_pntr_plus3(3),
I2 => wr_pntr_plus3(1),
I3 => wr_pntr_plus3(0),
I4 => wr_pntr_plus3(2),
I5 => wr_pntr_plus3(4),
O => \gic0.gc1.count[9]_i_2_n_0\
);
\gic0.gc1.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus3(0),
Q => wr_pntr_plus2(0)
);
\gic0.gc1.count_d1_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => wr_pntr_plus3(1),
PRE => AR(0),
Q => wr_pntr_plus2(1)
);
\gic0.gc1.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus3(2),
Q => wr_pntr_plus2(2)
);
\gic0.gc1.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus3(3),
Q => wr_pntr_plus2(3)
);
\gic0.gc1.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus3(4),
Q => wr_pntr_plus2(4)
);
\gic0.gc1.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus3(5),
Q => wr_pntr_plus2(5)
);
\gic0.gc1.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus3(6),
Q => wr_pntr_plus2(6)
);
\gic0.gc1.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus3(7),
Q => wr_pntr_plus2(7)
);
\gic0.gc1.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus3(8),
Q => wr_pntr_plus2(8)
);
\gic0.gc1.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus3(9),
Q => wr_pntr_plus2(9)
);
\gic0.gc1.count_d2_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => wr_pntr_plus2(0),
PRE => AR(0),
Q => \^q\(0)
);
\gic0.gc1.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(1),
Q => \^q\(1)
);
\gic0.gc1.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(2),
Q => \^q\(2)
);
\gic0.gc1.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(3),
Q => \^q\(3)
);
\gic0.gc1.count_d2_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(4),
Q => \^q\(4)
);
\gic0.gc1.count_d2_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(5),
Q => \^q\(5)
);
\gic0.gc1.count_d2_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(6),
Q => \^q\(6)
);
\gic0.gc1.count_d2_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(7),
Q => \^q\(7)
);
\gic0.gc1.count_d2_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(8),
Q => \^q\(8)
);
\gic0.gc1.count_d2_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(9),
Q => p_13_out(9)
);
\gic0.gc1.count_d3_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(0)
);
\gic0.gc1.count_d3_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1)
);
\gic0.gc1.count_d3_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(2)
);
\gic0.gc1.count_d3_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(3)
);
\gic0.gc1.count_d3_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(4),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(4)
);
\gic0.gc1.count_d3_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(5),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(5)
);
\gic0.gc1.count_d3_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(6),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(6)
);
\gic0.gc1.count_d3_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(7),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(7)
);
\gic0.gc1.count_d3_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(8),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(8)
);
\gic0.gc1.count_d3_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(9),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9)
);
\gic0.gc1.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \plusOp__1\(0),
PRE => AR(0),
Q => wr_pntr_plus3(0)
);
\gic0.gc1.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \plusOp__1\(1),
PRE => AR(0),
Q => wr_pntr_plus3(1)
);
\gic0.gc1.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(2),
Q => wr_pntr_plus3(2)
);
\gic0.gc1.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(3),
Q => wr_pntr_plus3(3)
);
\gic0.gc1.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(4),
Q => wr_pntr_plus3(4)
);
\gic0.gc1.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(5),
Q => wr_pntr_plus3(5)
);
\gic0.gc1.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(6),
Q => wr_pntr_plus3(6)
);
\gic0.gc1.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(7),
Q => wr_pntr_plus3(7)
);
\gic0.gc1.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(8),
Q => wr_pntr_plus3(8)
);
\gic0.gc1.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(9),
Q => wr_pntr_plus3(9)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => RD_PNTR_WR(0),
I2 => \^q\(1),
I3 => RD_PNTR_WR(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => RD_PNTR_WR(0),
I2 => wr_pntr_plus2(1),
I3 => RD_PNTR_WR(1),
O => v1_reg_0(0)
);
\gmux.gm[0].gm1.m1_i_1__4\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus3(0),
I1 => RD_PNTR_WR(0),
I2 => wr_pntr_plus3(1),
I3 => RD_PNTR_WR(1),
O => v1_reg_1(0)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => RD_PNTR_WR(2),
I2 => \^q\(3),
I3 => RD_PNTR_WR(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(2),
I1 => RD_PNTR_WR(2),
I2 => wr_pntr_plus2(3),
I3 => RD_PNTR_WR(3),
O => v1_reg_0(1)
);
\gmux.gm[1].gms.ms_i_1__4\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus3(2),
I1 => RD_PNTR_WR(2),
I2 => wr_pntr_plus3(3),
I3 => RD_PNTR_WR(3),
O => v1_reg_1(1)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => RD_PNTR_WR(4),
I2 => \^q\(5),
I3 => RD_PNTR_WR(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(4),
I1 => RD_PNTR_WR(4),
I2 => wr_pntr_plus2(5),
I3 => RD_PNTR_WR(5),
O => v1_reg_0(2)
);
\gmux.gm[2].gms.ms_i_1__4\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus3(4),
I1 => RD_PNTR_WR(4),
I2 => wr_pntr_plus3(5),
I3 => RD_PNTR_WR(5),
O => v1_reg_1(2)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => RD_PNTR_WR(6),
I2 => \^q\(7),
I3 => RD_PNTR_WR(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(6),
I1 => RD_PNTR_WR(6),
I2 => wr_pntr_plus2(7),
I3 => RD_PNTR_WR(7),
O => v1_reg_0(3)
);
\gmux.gm[3].gms.ms_i_1__4\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus3(6),
I1 => RD_PNTR_WR(6),
I2 => wr_pntr_plus3(7),
I3 => RD_PNTR_WR(7),
O => v1_reg_1(3)
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => RD_PNTR_WR(8),
I2 => p_13_out(9),
I3 => RD_PNTR_WR(9),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(8),
I1 => RD_PNTR_WR(8),
I2 => wr_pntr_plus2(9),
I3 => RD_PNTR_WR(9),
O => v1_reg_0(4)
);
\gmux.gm[4].gms.ms_i_1__4\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus3(8),
I1 => RD_PNTR_WR(8),
I2 => wr_pntr_plus3(9),
I3 => RD_PNTR_WR(9),
O => v1_reg_1(4)
);
\minusOp_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(7),
I1 => RD_PNTR_WR(7),
O => \wr_data_count_i_reg[7]\(3)
);
\minusOp_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(6),
I1 => RD_PNTR_WR(6),
O => \wr_data_count_i_reg[7]\(2)
);
\minusOp_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(5),
I1 => RD_PNTR_WR(5),
O => \wr_data_count_i_reg[7]\(1)
);
\minusOp_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(4),
I1 => RD_PNTR_WR(4),
O => \wr_data_count_i_reg[7]\(0)
);
\minusOp_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9),
I1 => RD_PNTR_WR(9),
O => \wr_data_count_i_reg[9]\(1)
);
\minusOp_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(8),
I1 => RD_PNTR_WR(8),
O => \wr_data_count_i_reg[9]\(0)
);
minusOp_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(3),
I1 => RD_PNTR_WR(3),
O => \wr_data_count_i_reg[3]\(3)
);
minusOp_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(2),
I1 => RD_PNTR_WR(2),
O => \wr_data_count_i_reg[3]\(2)
);
minusOp_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1),
I1 => RD_PNTR_WR(1),
O => \wr_data_count_i_reg[3]\(1)
);
minusOp_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(0),
I1 => RD_PNTR_WR(0),
O => \wr_data_count_i_reg[3]\(0)
);
\plusOp_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(7),
I1 => RD_PNTR_WR(7),
O => \gdiff.diff_pntr_pad_reg[8]\(3)
);
\plusOp_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(6),
I1 => RD_PNTR_WR(6),
O => \gdiff.diff_pntr_pad_reg[8]\(2)
);
\plusOp_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(5),
I1 => RD_PNTR_WR(5),
O => \gdiff.diff_pntr_pad_reg[8]\(1)
);
\plusOp_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(4),
I1 => RD_PNTR_WR(4),
O => \gdiff.diff_pntr_pad_reg[8]\(0)
);
\plusOp_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_13_out(9),
I1 => RD_PNTR_WR(9),
O => \gdiff.diff_pntr_pad_reg[10]\(1)
);
\plusOp_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(8),
I1 => RD_PNTR_WR(8),
O => \gdiff.diff_pntr_pad_reg[10]\(0)
);
plusOp_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(3),
I1 => RD_PNTR_WR(3),
O => S(3)
);
plusOp_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(2),
I1 => RD_PNTR_WR(2),
O => S(2)
);
plusOp_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(1),
I1 => RD_PNTR_WR(1),
O => S(1)
);
plusOp_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(0),
I1 => RD_PNTR_WR(0),
O => S(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as is
port (
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc1.count_d3_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc1.count_d3_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as is
signal \minusOp_carry__0_n_0\ : STD_LOGIC;
signal \minusOp_carry__0_n_1\ : STD_LOGIC;
signal \minusOp_carry__0_n_2\ : STD_LOGIC;
signal \minusOp_carry__0_n_3\ : STD_LOGIC;
signal \minusOp_carry__0_n_4\ : STD_LOGIC;
signal \minusOp_carry__0_n_5\ : STD_LOGIC;
signal \minusOp_carry__0_n_6\ : STD_LOGIC;
signal \minusOp_carry__0_n_7\ : STD_LOGIC;
signal \minusOp_carry__1_n_3\ : STD_LOGIC;
signal \minusOp_carry__1_n_6\ : STD_LOGIC;
signal \minusOp_carry__1_n_7\ : STD_LOGIC;
signal minusOp_carry_n_0 : STD_LOGIC;
signal minusOp_carry_n_1 : STD_LOGIC;
signal minusOp_carry_n_2 : STD_LOGIC;
signal minusOp_carry_n_3 : STD_LOGIC;
signal minusOp_carry_n_4 : STD_LOGIC;
signal minusOp_carry_n_5 : STD_LOGIC;
signal minusOp_carry_n_6 : STD_LOGIC;
signal minusOp_carry_n_7 : STD_LOGIC;
signal \NLW_minusOp_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_minusOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
begin
minusOp_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => minusOp_carry_n_0,
CO(2) => minusOp_carry_n_1,
CO(1) => minusOp_carry_n_2,
CO(0) => minusOp_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => Q(3 downto 0),
O(3) => minusOp_carry_n_4,
O(2) => minusOp_carry_n_5,
O(1) => minusOp_carry_n_6,
O(0) => minusOp_carry_n_7,
S(3 downto 0) => S(3 downto 0)
);
\minusOp_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => minusOp_carry_n_0,
CO(3) => \minusOp_carry__0_n_0\,
CO(2) => \minusOp_carry__0_n_1\,
CO(1) => \minusOp_carry__0_n_2\,
CO(0) => \minusOp_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => Q(7 downto 4),
O(3) => \minusOp_carry__0_n_4\,
O(2) => \minusOp_carry__0_n_5\,
O(1) => \minusOp_carry__0_n_6\,
O(0) => \minusOp_carry__0_n_7\,
S(3 downto 0) => \gic0.gc1.count_d3_reg[7]\(3 downto 0)
);
\minusOp_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \minusOp_carry__0_n_0\,
CO(3 downto 1) => \NLW_minusOp_carry__1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \minusOp_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => Q(8),
O(3 downto 2) => \NLW_minusOp_carry__1_O_UNCONNECTED\(3 downto 2),
O(1) => \minusOp_carry__1_n_6\,
O(0) => \minusOp_carry__1_n_7\,
S(3 downto 2) => B"00",
S(1 downto 0) => \gic0.gc1.count_d3_reg[9]\(1 downto 0)
);
\wr_data_count_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => minusOp_carry_n_7,
Q => wr_data_count(0)
);
\wr_data_count_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => minusOp_carry_n_6,
Q => wr_data_count(1)
);
\wr_data_count_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => minusOp_carry_n_5,
Q => wr_data_count(2)
);
\wr_data_count_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => minusOp_carry_n_4,
Q => wr_data_count(3)
);
\wr_data_count_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__0_n_7\,
Q => wr_data_count(4)
);
\wr_data_count_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__0_n_6\,
Q => wr_data_count(5)
);
\wr_data_count_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__0_n_5\,
Q => wr_data_count(6)
);
\wr_data_count_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__0_n_4\,
Q => wr_data_count(7)
);
\wr_data_count_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__1_n_7\,
Q => wr_data_count(8)
);
\wr_data_count_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__1_n_6\,
Q => wr_data_count(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as is
port (
prog_full : out STD_LOGIC;
wr_clk : in STD_LOGIC;
\out\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc1.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc1.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as is
signal diff_pntr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gpf1.prog_full_i_i_1_n_0\ : STD_LOGIC;
signal \gpf1.prog_full_i_i_2_n_0\ : STD_LOGIC;
signal \gpf1.prog_full_i_i_3_n_0\ : STD_LOGIC;
signal \plusOp_carry__0_n_0\ : STD_LOGIC;
signal \plusOp_carry__0_n_1\ : STD_LOGIC;
signal \plusOp_carry__0_n_2\ : STD_LOGIC;
signal \plusOp_carry__0_n_3\ : STD_LOGIC;
signal \plusOp_carry__0_n_4\ : STD_LOGIC;
signal \plusOp_carry__0_n_5\ : STD_LOGIC;
signal \plusOp_carry__0_n_6\ : STD_LOGIC;
signal \plusOp_carry__0_n_7\ : STD_LOGIC;
signal \plusOp_carry__1_n_3\ : STD_LOGIC;
signal \plusOp_carry__1_n_6\ : STD_LOGIC;
signal \plusOp_carry__1_n_7\ : STD_LOGIC;
signal plusOp_carry_n_0 : STD_LOGIC;
signal plusOp_carry_n_1 : STD_LOGIC;
signal plusOp_carry_n_2 : STD_LOGIC;
signal plusOp_carry_n_3 : STD_LOGIC;
signal plusOp_carry_n_4 : STD_LOGIC;
signal plusOp_carry_n_5 : STD_LOGIC;
signal plusOp_carry_n_6 : STD_LOGIC;
signal plusOp_carry_n_7 : STD_LOGIC;
signal \^prog_full\ : STD_LOGIC;
signal \NLW_plusOp_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_plusOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
begin
prog_full <= \^prog_full\;
\gdiff.diff_pntr_pad_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__1_n_6\,
Q => diff_pntr(9)
);
\gdiff.diff_pntr_pad_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => plusOp_carry_n_7,
Q => diff_pntr(0)
);
\gdiff.diff_pntr_pad_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => plusOp_carry_n_6,
Q => diff_pntr(1)
);
\gdiff.diff_pntr_pad_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => plusOp_carry_n_5,
Q => diff_pntr(2)
);
\gdiff.diff_pntr_pad_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => plusOp_carry_n_4,
Q => diff_pntr(3)
);
\gdiff.diff_pntr_pad_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__0_n_7\,
Q => diff_pntr(4)
);
\gdiff.diff_pntr_pad_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__0_n_6\,
Q => diff_pntr(5)
);
\gdiff.diff_pntr_pad_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__0_n_5\,
Q => diff_pntr(6)
);
\gdiff.diff_pntr_pad_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__0_n_4\,
Q => diff_pntr(7)
);
\gdiff.diff_pntr_pad_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__1_n_7\,
Q => diff_pntr(8)
);
\gpf1.prog_full_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FF000200000002"
)
port map (
I0 => diff_pntr(9),
I1 => \gpf1.prog_full_i_i_2_n_0\,
I2 => \gpf1.prog_full_i_i_3_n_0\,
I3 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I4 => ram_full_fb_i_reg,
I5 => \^prog_full\,
O => \gpf1.prog_full_i_i_1_n_0\
);
\gpf1.prog_full_i_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"777FFFFF"
)
port map (
I0 => diff_pntr(2),
I1 => diff_pntr(3),
I2 => diff_pntr(0),
I3 => diff_pntr(1),
I4 => diff_pntr(7),
O => \gpf1.prog_full_i_i_2_n_0\
);
\gpf1.prog_full_i_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => diff_pntr(6),
I1 => diff_pntr(8),
I2 => diff_pntr(4),
I3 => diff_pntr(5),
O => \gpf1.prog_full_i_i_3_n_0\
);
\gpf1.prog_full_i_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \gpf1.prog_full_i_i_1_n_0\,
PRE => \out\,
Q => \^prog_full\
);
plusOp_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => plusOp_carry_n_0,
CO(2) => plusOp_carry_n_1,
CO(1) => plusOp_carry_n_2,
CO(0) => plusOp_carry_n_3,
CYINIT => E(0),
DI(3 downto 0) => Q(3 downto 0),
O(3) => plusOp_carry_n_4,
O(2) => plusOp_carry_n_5,
O(1) => plusOp_carry_n_6,
O(0) => plusOp_carry_n_7,
S(3 downto 0) => S(3 downto 0)
);
\plusOp_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => plusOp_carry_n_0,
CO(3) => \plusOp_carry__0_n_0\,
CO(2) => \plusOp_carry__0_n_1\,
CO(1) => \plusOp_carry__0_n_2\,
CO(0) => \plusOp_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => Q(7 downto 4),
O(3) => \plusOp_carry__0_n_4\,
O(2) => \plusOp_carry__0_n_5\,
O(1) => \plusOp_carry__0_n_6\,
O(0) => \plusOp_carry__0_n_7\,
S(3 downto 0) => \gic0.gc1.count_d2_reg[7]\(3 downto 0)
);
\plusOp_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \plusOp_carry__0_n_0\,
CO(3 downto 1) => \NLW_plusOp_carry__1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \plusOp_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => Q(8),
O(3 downto 2) => \NLW_plusOp_carry__1_O_UNCONNECTED\(3 downto 2),
O(1) => \plusOp_carry__1_n_6\,
O(0) => \plusOp_carry__1_n_7\,
S(3 downto 2) => B"00",
S(1 downto 0) => \gic0.gc1.count_d2_reg[9]\(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 35 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc1.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 35 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
din(35 downto 0) => din(35 downto 0),
dout(35 downto 0) => dout(35 downto 0),
\gc1.count_d2_reg[9]\(9 downto 0) => \gc1.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 27 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc1.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
din(27 downto 0) => din(27 downto 0),
dout(27 downto 0) => dout(27 downto 0),
\gc1.count_d2_reg[9]\(9 downto 0) => \gc1.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs is
port (
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_1 : out STD_LOGIC_VECTOR ( 4 downto 0 );
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
\rd_dc_i_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
RD_PNTR_WR : out STD_LOGIC_VECTOR ( 9 downto 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc1.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc1.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
p_0_out : in STD_LOGIC;
\gic0.gc1.count_d3_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs is
signal bin2gray : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \gdiff.diff_pntr_pad[10]_i_2_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[10]_i_3_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[4]_i_3_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[4]_i_4_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[4]_i_5_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[4]_i_6_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[8]_i_2_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[8]_i_3_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[8]_i_4_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[8]_i_5_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[10]_i_1_n_3\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_0_out_0 : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 9 to 9 );
signal p_6_out : STD_LOGIC_VECTOR ( 9 to 9 );
signal \rd_dc_i[3]_i_2_n_0\ : STD_LOGIC;
signal \rd_dc_i[3]_i_3_n_0\ : STD_LOGIC;
signal \rd_dc_i[3]_i_4_n_0\ : STD_LOGIC;
signal \rd_dc_i[3]_i_5_n_0\ : STD_LOGIC;
signal \rd_dc_i[7]_i_2_n_0\ : STD_LOGIC;
signal \rd_dc_i[7]_i_3_n_0\ : STD_LOGIC;
signal \rd_dc_i[7]_i_4_n_0\ : STD_LOGIC;
signal \rd_dc_i[7]_i_5_n_0\ : STD_LOGIC;
signal \rd_dc_i[9]_i_2_n_0\ : STD_LOGIC;
signal \rd_dc_i[9]_i_3_n_0\ : STD_LOGIC;
signal \rd_dc_i_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \rd_dc_i_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \rd_dc_i_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \rd_dc_i_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \rd_dc_i_reg[9]_i_1_n_3\ : STD_LOGIC;
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 9 downto 0 );
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_gdiff.diff_pntr_pad_reg[10]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gdiff.diff_pntr_pad_reg[10]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_rd_dc_i_reg[9]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_rd_dc_i_reg[9]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[5]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[6]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[7]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[5]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[6]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[7]_i_1\ : label is "soft_lutpair3";
begin
\gdiff.diff_pntr_pad[10]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(9),
I1 => Q(9),
O => \gdiff.diff_pntr_pad[10]_i_2_n_0\
);
\gdiff.diff_pntr_pad[10]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(8),
I1 => Q(8),
O => \gdiff.diff_pntr_pad[10]_i_3_n_0\
);
\gdiff.diff_pntr_pad[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(3),
I1 => Q(3),
O => \gdiff.diff_pntr_pad[4]_i_3_n_0\
);
\gdiff.diff_pntr_pad[4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(2),
I1 => Q(2),
O => \gdiff.diff_pntr_pad[4]_i_4_n_0\
);
\gdiff.diff_pntr_pad[4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(1),
I1 => Q(1),
O => \gdiff.diff_pntr_pad[4]_i_5_n_0\
);
\gdiff.diff_pntr_pad[4]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(0),
I1 => Q(0),
O => \gdiff.diff_pntr_pad[4]_i_6_n_0\
);
\gdiff.diff_pntr_pad[8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(7),
I1 => Q(7),
O => \gdiff.diff_pntr_pad[8]_i_2_n_0\
);
\gdiff.diff_pntr_pad[8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(6),
I1 => Q(6),
O => \gdiff.diff_pntr_pad[8]_i_3_n_0\
);
\gdiff.diff_pntr_pad[8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(5),
I1 => Q(5),
O => \gdiff.diff_pntr_pad[8]_i_4_n_0\
);
\gdiff.diff_pntr_pad[8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(4),
I1 => Q(4),
O => \gdiff.diff_pntr_pad[8]_i_5_n_0\
);
\gdiff.diff_pntr_pad_reg[10]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gdiff.diff_pntr_pad_reg[8]_i_1_n_0\,
CO(3 downto 1) => \NLW_gdiff.diff_pntr_pad_reg[10]_i_1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \gdiff.diff_pntr_pad_reg[10]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => p_22_out(8),
O(3 downto 2) => \NLW_gdiff.diff_pntr_pad_reg[10]_i_1_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => D(9 downto 8),
S(3 downto 2) => B"00",
S(1) => \gdiff.diff_pntr_pad[10]_i_2_n_0\,
S(0) => \gdiff.diff_pntr_pad[10]_i_3_n_0\
);
\gdiff.diff_pntr_pad_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gdiff.diff_pntr_pad_reg[4]_i_1_n_0\,
CO(2) => \gdiff.diff_pntr_pad_reg[4]_i_1_n_1\,
CO(1) => \gdiff.diff_pntr_pad_reg[4]_i_1_n_2\,
CO(0) => \gdiff.diff_pntr_pad_reg[4]_i_1_n_3\,
CYINIT => p_0_out,
DI(3 downto 0) => p_22_out(3 downto 0),
O(3 downto 0) => D(3 downto 0),
S(3) => \gdiff.diff_pntr_pad[4]_i_3_n_0\,
S(2) => \gdiff.diff_pntr_pad[4]_i_4_n_0\,
S(1) => \gdiff.diff_pntr_pad[4]_i_5_n_0\,
S(0) => \gdiff.diff_pntr_pad[4]_i_6_n_0\
);
\gdiff.diff_pntr_pad_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gdiff.diff_pntr_pad_reg[4]_i_1_n_0\,
CO(3) => \gdiff.diff_pntr_pad_reg[8]_i_1_n_0\,
CO(2) => \gdiff.diff_pntr_pad_reg[8]_i_1_n_1\,
CO(1) => \gdiff.diff_pntr_pad_reg[8]_i_1_n_2\,
CO(0) => \gdiff.diff_pntr_pad_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => p_22_out(7 downto 4),
O(3 downto 0) => D(7 downto 4),
S(3) => \gdiff.diff_pntr_pad[8]_i_2_n_0\,
S(2) => \gdiff.diff_pntr_pad[8]_i_3_n_0\,
S(1) => \gdiff.diff_pntr_pad[8]_i_4_n_0\,
S(0) => \gdiff.diff_pntr_pad[8]_i_5_n_0\
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(0),
I1 => Q(0),
I2 => p_22_out(1),
I3 => Q(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(0),
I1 => \gc1.count_d1_reg[9]\(0),
I2 => p_22_out(1),
I3 => \gc1.count_d1_reg[9]\(1),
O => v1_reg_0(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(0),
I1 => \gc1.count_reg[9]\(0),
I2 => p_22_out(1),
I3 => \gc1.count_reg[9]\(1),
O => v1_reg_1(0)
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(2),
I1 => Q(2),
I2 => p_22_out(3),
I3 => Q(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(2),
I1 => \gc1.count_d1_reg[9]\(2),
I2 => p_22_out(3),
I3 => \gc1.count_d1_reg[9]\(3),
O => v1_reg_0(1)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(2),
I1 => \gc1.count_reg[9]\(2),
I2 => p_22_out(3),
I3 => \gc1.count_reg[9]\(3),
O => v1_reg_1(1)
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(4),
I1 => Q(4),
I2 => p_22_out(5),
I3 => Q(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(4),
I1 => \gc1.count_d1_reg[9]\(4),
I2 => p_22_out(5),
I3 => \gc1.count_d1_reg[9]\(5),
O => v1_reg_0(2)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(4),
I1 => \gc1.count_reg[9]\(4),
I2 => p_22_out(5),
I3 => \gc1.count_reg[9]\(5),
O => v1_reg_1(2)
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(6),
I1 => Q(6),
I2 => p_22_out(7),
I3 => Q(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(6),
I1 => \gc1.count_d1_reg[9]\(6),
I2 => p_22_out(7),
I3 => \gc1.count_d1_reg[9]\(7),
O => v1_reg_0(3)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(6),
I1 => \gc1.count_reg[9]\(6),
I2 => p_22_out(7),
I3 => \gc1.count_reg[9]\(7),
O => v1_reg_1(3)
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(8),
I1 => Q(8),
I2 => p_22_out(9),
I3 => Q(9),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(8),
I1 => \gc1.count_d1_reg[9]\(8),
I2 => p_22_out(9),
I3 => \gc1.count_d1_reg[9]\(9),
O => v1_reg_0(4)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(8),
I1 => \gc1.count_reg[9]\(8),
I2 => p_22_out(9),
I3 => \gc1.count_reg[9]\(9),
O => v1_reg_1(4)
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\
port map (
D(9 downto 0) => p_3_out(9 downto 0),
Q(9 downto 0) => wr_pntr_gc(9 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
rd_clk => rd_clk
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\
port map (
AR(0) => AR(0),
D(9 downto 0) => p_4_out(9 downto 0),
Q(9 downto 0) => rd_pntr_gc(9 downto 0),
wr_clk => wr_clk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\
port map (
D(9 downto 0) => p_3_out(9 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[8]\(8) => p_0_out_0,
\gnxpm_cdc.wr_pntr_bin_reg[8]\(7 downto 0) => gray2bin(7 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(0) => p_5_out(9),
rd_clk => rd_clk
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\
port map (
AR(0) => AR(0),
D(9 downto 0) => p_4_out(9 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[8]\(8) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(7) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(6) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(5) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(4) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(3) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(2) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(1) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(0) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9\,
\out\(0) => p_6_out(9),
wr_clk => wr_clk
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9\,
Q => RD_PNTR_WR(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8\,
Q => RD_PNTR_WR(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\,
Q => RD_PNTR_WR(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\,
Q => RD_PNTR_WR(3)
);
\gnxpm_cdc.rd_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5\,
Q => RD_PNTR_WR(4)
);
\gnxpm_cdc.rd_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
Q => RD_PNTR_WR(5)
);
\gnxpm_cdc.rd_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3\,
Q => RD_PNTR_WR(6)
);
\gnxpm_cdc.rd_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2\,
Q => RD_PNTR_WR(7)
);
\gnxpm_cdc.rd_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1\,
Q => RD_PNTR_WR(8)
);
\gnxpm_cdc.rd_pntr_bin_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => p_6_out(9),
Q => RD_PNTR_WR(9)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(0),
I1 => Q(1),
O => \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(1),
I1 => Q(2),
O => \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(2),
I1 => Q(3),
O => \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(3),
I1 => Q(4),
O => \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(4),
I1 => Q(5),
O => \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(5),
I1 => Q(6),
O => \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(6),
I1 => Q(7),
O => \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(7),
I1 => Q(8),
O => \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(8),
I1 => Q(9),
O => \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0\,
Q => rd_pntr_gc(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0\,
Q => rd_pntr_gc(1)
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0\,
Q => rd_pntr_gc(2)
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0\,
Q => rd_pntr_gc(3)
);
\gnxpm_cdc.rd_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0\,
Q => rd_pntr_gc(4)
);
\gnxpm_cdc.rd_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0\,
Q => rd_pntr_gc(5)
);
\gnxpm_cdc.rd_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0\,
Q => rd_pntr_gc(6)
);
\gnxpm_cdc.rd_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0\,
Q => rd_pntr_gc(7)
);
\gnxpm_cdc.rd_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0\,
Q => rd_pntr_gc(8)
);
\gnxpm_cdc.rd_pntr_gc_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(9),
Q => rd_pntr_gc(9)
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(0),
Q => p_22_out(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(1),
Q => p_22_out(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(2),
Q => p_22_out(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(3),
Q => p_22_out(3)
);
\gnxpm_cdc.wr_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(4),
Q => p_22_out(4)
);
\gnxpm_cdc.wr_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(5),
Q => p_22_out(5)
);
\gnxpm_cdc.wr_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(6),
Q => p_22_out(6)
);
\gnxpm_cdc.wr_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(7),
Q => p_22_out(7)
);
\gnxpm_cdc.wr_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_out_0,
Q => p_22_out(8)
);
\gnxpm_cdc.wr_pntr_bin_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_5_out(9),
Q => p_22_out(9)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc1.count_d3_reg[9]\(0),
I1 => \gic0.gc1.count_d3_reg[9]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc1.count_d3_reg[9]\(1),
I1 => \gic0.gc1.count_d3_reg[9]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc1.count_d3_reg[9]\(2),
I1 => \gic0.gc1.count_d3_reg[9]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc1.count_d3_reg[9]\(3),
I1 => \gic0.gc1.count_d3_reg[9]\(4),
O => bin2gray(3)
);
\gnxpm_cdc.wr_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc1.count_d3_reg[9]\(4),
I1 => \gic0.gc1.count_d3_reg[9]\(5),
O => bin2gray(4)
);
\gnxpm_cdc.wr_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc1.count_d3_reg[9]\(5),
I1 => \gic0.gc1.count_d3_reg[9]\(6),
O => bin2gray(5)
);
\gnxpm_cdc.wr_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc1.count_d3_reg[9]\(6),
I1 => \gic0.gc1.count_d3_reg[9]\(7),
O => bin2gray(6)
);
\gnxpm_cdc.wr_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc1.count_d3_reg[9]\(7),
I1 => \gic0.gc1.count_d3_reg[9]\(8),
O => bin2gray(7)
);
\gnxpm_cdc.wr_pntr_gc[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc1.count_d3_reg[9]\(8),
I1 => \gic0.gc1.count_d3_reg[9]\(9),
O => bin2gray(8)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => wr_pntr_gc(0)
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => wr_pntr_gc(1)
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => wr_pntr_gc(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(3),
Q => wr_pntr_gc(3)
);
\gnxpm_cdc.wr_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(4),
Q => wr_pntr_gc(4)
);
\gnxpm_cdc.wr_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(5),
Q => wr_pntr_gc(5)
);
\gnxpm_cdc.wr_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(6),
Q => wr_pntr_gc(6)
);
\gnxpm_cdc.wr_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(7),
Q => wr_pntr_gc(7)
);
\gnxpm_cdc.wr_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(8),
Q => wr_pntr_gc(8)
);
\gnxpm_cdc.wr_pntr_gc_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gic0.gc1.count_d3_reg[9]\(9),
Q => wr_pntr_gc(9)
);
\rd_dc_i[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(3),
I1 => Q(3),
O => \rd_dc_i[3]_i_2_n_0\
);
\rd_dc_i[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(2),
I1 => Q(2),
O => \rd_dc_i[3]_i_3_n_0\
);
\rd_dc_i[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(1),
I1 => Q(1),
O => \rd_dc_i[3]_i_4_n_0\
);
\rd_dc_i[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(0),
I1 => Q(0),
O => \rd_dc_i[3]_i_5_n_0\
);
\rd_dc_i[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(7),
I1 => Q(7),
O => \rd_dc_i[7]_i_2_n_0\
);
\rd_dc_i[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(6),
I1 => Q(6),
O => \rd_dc_i[7]_i_3_n_0\
);
\rd_dc_i[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(5),
I1 => Q(5),
O => \rd_dc_i[7]_i_4_n_0\
);
\rd_dc_i[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(4),
I1 => Q(4),
O => \rd_dc_i[7]_i_5_n_0\
);
\rd_dc_i[9]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(9),
I1 => Q(9),
O => \rd_dc_i[9]_i_2_n_0\
);
\rd_dc_i[9]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(8),
I1 => Q(8),
O => \rd_dc_i[9]_i_3_n_0\
);
\rd_dc_i_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rd_dc_i_reg[3]_i_1_n_0\,
CO(2) => \rd_dc_i_reg[3]_i_1_n_1\,
CO(1) => \rd_dc_i_reg[3]_i_1_n_2\,
CO(0) => \rd_dc_i_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3 downto 0) => p_22_out(3 downto 0),
O(3 downto 0) => \rd_dc_i_reg[9]\(3 downto 0),
S(3) => \rd_dc_i[3]_i_2_n_0\,
S(2) => \rd_dc_i[3]_i_3_n_0\,
S(1) => \rd_dc_i[3]_i_4_n_0\,
S(0) => \rd_dc_i[3]_i_5_n_0\
);
\rd_dc_i_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rd_dc_i_reg[3]_i_1_n_0\,
CO(3) => \rd_dc_i_reg[7]_i_1_n_0\,
CO(2) => \rd_dc_i_reg[7]_i_1_n_1\,
CO(1) => \rd_dc_i_reg[7]_i_1_n_2\,
CO(0) => \rd_dc_i_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => p_22_out(7 downto 4),
O(3 downto 0) => \rd_dc_i_reg[9]\(7 downto 4),
S(3) => \rd_dc_i[7]_i_2_n_0\,
S(2) => \rd_dc_i[7]_i_3_n_0\,
S(1) => \rd_dc_i[7]_i_4_n_0\,
S(0) => \rd_dc_i[7]_i_5_n_0\
);
\rd_dc_i_reg[9]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rd_dc_i_reg[7]_i_1_n_0\,
CO(3 downto 1) => \NLW_rd_dc_i_reg[9]_i_1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \rd_dc_i_reg[9]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => p_22_out(8),
O(3 downto 2) => \NLW_rd_dc_i_reg[9]_i_1_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => \rd_dc_i_reg[9]\(9 downto 8),
S(3 downto 2) => B"00",
S(1) => \rd_dc_i[9]_i_2_n_0\,
S(0) => \rd_dc_i[9]_i_3_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as is
port (
empty : out STD_LOGIC;
\out\ : out STD_LOGIC;
almost_empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
p_0_out : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as is
signal \^almost_empty\ : STD_LOGIC;
signal c1_n_1 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal comp2 : STD_LOGIC;
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
signal ram_empty_i0 : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
almost_empty <= \^almost_empty\;
empty <= ram_empty_i;
\out\ <= ram_empty_fb_i;
c0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5
port map (
comp1 => comp1,
\out\ => ram_empty_fb_i,
ram_empty_i0 => ram_empty_i0,
rd_en => rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0)
);
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_6
port map (
almost_empty => \^almost_empty\,
comp1 => comp1,
comp2 => comp2,
\gae.ram_almost_empty_i_reg\ => c1_n_1,
\out\ => ram_empty_fb_i,
rd_en => rd_en,
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
\gae.c2\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_7
port map (
comp2 => comp2,
v1_reg_1(4 downto 0) => v1_reg_1(4 downto 0)
);
\gae.ram_almost_empty_i_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => c1_n_1,
PRE => AR(0),
Q => \^almost_empty\
);
\gc1.count_d1[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => ram_empty_fb_i,
O => E(0)
);
\gdiff.diff_pntr_pad[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => ram_empty_fb_i,
I1 => rd_en,
O => p_0_out
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => ram_empty_i0,
PRE => AR(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => ram_empty_i0,
PRE => AR(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc1.count_reg[0]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
WR_RST_BUSY : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
rd_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
WR_RST_BUSY <= rst_d3;
\gc1.count_reg[0]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => rd_rst_reg(0),
I1 => ram_empty_fb_i_reg,
I2 => rd_en,
O => tmp_ram_rd_en
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff
port map (
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out,
rd_clk => rd_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0
port map (
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out,
wr_clk => wr_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
in0(0) => rd_rst_asreg,
\out\ => p_7_out,
rd_clk => rd_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
in0(0) => wr_rst_asreg,
\out\ => p_8_out,
wr_clk => wr_clk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as is
port (
full : out STD_LOGIC;
\out\ : out STD_LOGIC;
almost_full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_clk : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as is
signal \^almost_full\ : STD_LOGIC;
signal c2_n_1 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal comp2 : STD_LOGIC;
signal \gaf.c3_n_0\ : STD_LOGIC;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
almost_full <= \^almost_full\;
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare
port map (
comp1 => comp1,
v1_reg(4 downto 0) => v1_reg(4 downto 0)
);
c2: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3
port map (
comp1 => comp1,
comp2 => comp2,
\grstd1.grst_full.grst_f.rst_d3_reg\ => \grstd1.grst_full.grst_f.rst_d3_reg\,
\out\ => ram_full_fb_i,
ram_full_i_reg => c2_n_1,
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0),
wr_en => wr_en
);
\gaf.c3\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4
port map (
almost_full => \^almost_full\,
comp2 => comp2,
\gaf.ram_almost_full_i_reg\ => \gaf.c3_n_0\,
\grstd1.grst_full.grst_f.rst_d3_reg\ => \grstd1.grst_full.grst_f.rst_d3_reg\,
\out\ => ram_full_fb_i,
v1_reg_1(4 downto 0) => v1_reg_1(4 downto 0),
wr_en => wr_en
);
\gaf.ram_almost_full_i_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \gaf.c3_n_0\,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => \^almost_full\
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => c2_n_1,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => c2_n_1,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc1.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
din(35 downto 0) => din(35 downto 0),
dout(35 downto 0) => dout(35 downto 0),
\gc1.count_d2_reg[9]\(9 downto 0) => \gc1.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
\ramloop[1].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
din(27 downto 0) => din(63 downto 36),
dout(27 downto 0) => dout(63 downto 36),
\gc1.count_d2_reg[9]\(9 downto 0) => \gc1.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
port (
empty : out STD_LOGIC;
\out\ : out STD_LOGIC;
almost_empty : out STD_LOGIC;
prog_empty : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
p_0_out : out STD_LOGIC;
\gc1.count_d2_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[8]\ : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
signal \gras.rsts_n_3\ : STD_LOGIC;
signal \^out\ : STD_LOGIC;
begin
\out\ <= \^out\;
\gras.gpe.rdpe\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as
port map (
AR(0) => AR(0),
D(9 downto 0) => D(9 downto 0),
\out\ => \^out\,
prog_empty => prog_empty,
rd_clk => rd_clk
);
\gras.grdc1.rdc\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as
port map (
AR(0) => AR(0),
\gnxpm_cdc.wr_pntr_bin_reg[8]\(9 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[8]\(9 downto 0),
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0)
);
\gras.rsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as
port map (
AR(0) => AR(0),
E(0) => \gras.rsts_n_3\,
almost_empty => almost_empty,
empty => empty,
\out\ => \^out\,
p_0_out => p_0_out,
rd_clk => rd_clk,
rd_en => rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0),
v1_reg_1(4 downto 0) => v1_reg_1(4 downto 0)
);
rpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
port map (
AR(0) => AR(0),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0),
E(0) => \gras.rsts_n_3\,
Q(9 downto 0) => Q(9 downto 0),
\gc1.count_d2_reg[9]_0\(9 downto 0) => \gc1.count_d2_reg[9]\(9 downto 0),
rd_clk => rd_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
port (
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
prog_full : out STD_LOGIC;
WEA : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
\out\ : in STD_LOGIC;
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_en : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^wea\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \c2/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gaf.c3/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gwas.wsts_n_1\ : STD_LOGIC;
signal p_13_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal wpntr_n_0 : STD_LOGIC;
signal wpntr_n_1 : STD_LOGIC;
signal wpntr_n_13 : STD_LOGIC;
signal wpntr_n_14 : STD_LOGIC;
signal wpntr_n_15 : STD_LOGIC;
signal wpntr_n_16 : STD_LOGIC;
signal wpntr_n_17 : STD_LOGIC;
signal wpntr_n_18 : STD_LOGIC;
signal wpntr_n_19 : STD_LOGIC;
signal wpntr_n_2 : STD_LOGIC;
signal wpntr_n_20 : STD_LOGIC;
signal wpntr_n_21 : STD_LOGIC;
signal wpntr_n_22 : STD_LOGIC;
signal wpntr_n_3 : STD_LOGIC;
signal wpntr_n_33 : STD_LOGIC;
signal wpntr_n_34 : STD_LOGIC;
signal wpntr_n_35 : STD_LOGIC;
signal wpntr_n_36 : STD_LOGIC;
signal wpntr_n_37 : STD_LOGIC;
signal wpntr_n_38 : STD_LOGIC;
begin
Q(9 downto 0) <= \^q\(9 downto 0);
WEA(0) <= \^wea\(0);
\gwas.gpf.wrpf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as
port map (
AR(0) => AR(0),
E(0) => \^wea\(0),
Q(8 downto 0) => p_13_out(8 downto 0),
S(3) => wpntr_n_0,
S(2) => wpntr_n_1,
S(1) => wpntr_n_2,
S(0) => wpntr_n_3,
\gic0.gc1.count_d2_reg[7]\(3) => wpntr_n_13,
\gic0.gc1.count_d2_reg[7]\(2) => wpntr_n_14,
\gic0.gc1.count_d2_reg[7]\(1) => wpntr_n_15,
\gic0.gc1.count_d2_reg[7]\(0) => wpntr_n_16,
\gic0.gc1.count_d2_reg[9]\(1) => wpntr_n_17,
\gic0.gc1.count_d2_reg[9]\(0) => wpntr_n_18,
\grstd1.grst_full.grst_f.rst_d3_reg\ => \grstd1.grst_full.grst_f.rst_d3_reg\,
\out\ => \out\,
prog_full => prog_full,
ram_full_fb_i_reg => \gwas.wsts_n_1\,
wr_clk => wr_clk
);
\gwas.gwdc0.wdc\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as
port map (
AR(0) => AR(0),
Q(8 downto 0) => \^q\(8 downto 0),
S(3) => wpntr_n_19,
S(2) => wpntr_n_20,
S(1) => wpntr_n_21,
S(0) => wpntr_n_22,
\gic0.gc1.count_d3_reg[7]\(3) => wpntr_n_33,
\gic0.gc1.count_d3_reg[7]\(2) => wpntr_n_34,
\gic0.gc1.count_d3_reg[7]\(1) => wpntr_n_35,
\gic0.gc1.count_d3_reg[7]\(0) => wpntr_n_36,
\gic0.gc1.count_d3_reg[9]\(1) => wpntr_n_37,
\gic0.gc1.count_d3_reg[9]\(0) => wpntr_n_38,
wr_clk => wr_clk,
wr_data_count(9 downto 0) => wr_data_count(9 downto 0)
);
\gwas.wsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as
port map (
E(0) => \^wea\(0),
almost_full => almost_full,
full => full,
\grstd1.grst_full.grst_f.rst_d2_reg\ => \out\,
\grstd1.grst_full.grst_f.rst_d3_reg\ => \grstd1.grst_full.grst_f.rst_d3_reg\,
\out\ => \gwas.wsts_n_1\,
v1_reg(4 downto 0) => \c1/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \c2/v1_reg\(4 downto 0),
v1_reg_1(4 downto 0) => \gaf.c3/v1_reg\(4 downto 0),
wr_clk => wr_clk,
wr_en => wr_en
);
wpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
port map (
AR(0) => AR(0),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => \^q\(9 downto 0),
E(0) => \^wea\(0),
Q(8 downto 0) => p_13_out(8 downto 0),
RD_PNTR_WR(9 downto 0) => RD_PNTR_WR(9 downto 0),
S(3) => wpntr_n_0,
S(2) => wpntr_n_1,
S(1) => wpntr_n_2,
S(0) => wpntr_n_3,
\gdiff.diff_pntr_pad_reg[10]\(1) => wpntr_n_17,
\gdiff.diff_pntr_pad_reg[10]\(0) => wpntr_n_18,
\gdiff.diff_pntr_pad_reg[8]\(3) => wpntr_n_13,
\gdiff.diff_pntr_pad_reg[8]\(2) => wpntr_n_14,
\gdiff.diff_pntr_pad_reg[8]\(1) => wpntr_n_15,
\gdiff.diff_pntr_pad_reg[8]\(0) => wpntr_n_16,
v1_reg(4 downto 0) => \c1/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \c2/v1_reg\(4 downto 0),
v1_reg_1(4 downto 0) => \gaf.c3/v1_reg\(4 downto 0),
wr_clk => wr_clk,
\wr_data_count_i_reg[3]\(3) => wpntr_n_19,
\wr_data_count_i_reg[3]\(2) => wpntr_n_20,
\wr_data_count_i_reg[3]\(1) => wpntr_n_21,
\wr_data_count_i_reg[3]\(0) => wpntr_n_22,
\wr_data_count_i_reg[7]\(3) => wpntr_n_33,
\wr_data_count_i_reg[7]\(2) => wpntr_n_34,
\wr_data_count_i_reg[7]\(1) => wpntr_n_35,
\wr_data_count_i_reg[7]\(0) => wpntr_n_36,
\wr_data_count_i_reg[9]\(1) => wpntr_n_37,
\wr_data_count_i_reg[9]\(0) => wpntr_n_38
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc1.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc1.count_d2_reg[9]\(9 downto 0) => \gc1.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc1.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc1.count_d2_reg[9]\(9 downto 0) => \gc1.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc1.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
begin
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc1.count_d2_reg[9]\(9 downto 0) => \gc1.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc1.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc1.count_d2_reg[9]\(9 downto 0) => \gc1.count_d2_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
port (
WR_RST_BUSY : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty : out STD_LOGIC;
almost_full : out STD_LOGIC;
prog_full : out STD_LOGIC;
almost_empty : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
signal \^wr_rst_busy\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal \gras.rsts/c0/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gras.rsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gras.rsts/gae.c2/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal minusOp : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_0_out : STD_LOGIC;
signal p_0_out_0 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_2_out : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 10 downto 1 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal rd_pntr_plus2 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
WR_RST_BUSY <= \^wr_rst_busy\;
\gntv_or_sync_fifo.gcx.clkx\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs
port map (
AR(0) => wr_rst_i(0),
D(9 downto 0) => plusOp(10 downto 1),
Q(9 downto 0) => p_0_out_0(9 downto 0),
RD_PNTR_WR(9 downto 0) => p_23_out(9 downto 0),
\gc1.count_d1_reg[9]\(9 downto 0) => rd_pntr_plus1(9 downto 0),
\gc1.count_reg[9]\(9 downto 0) => rd_pntr_plus2(9 downto 0),
\gic0.gc1.count_d3_reg[9]\(9 downto 0) => p_12_out(9 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
p_0_out => p_0_out,
rd_clk => rd_clk,
\rd_dc_i_reg[9]\(9 downto 0) => minusOp(9 downto 0),
v1_reg(4 downto 0) => \gras.rsts/c0/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \gras.rsts/c1/v1_reg\(4 downto 0),
v1_reg_1(4 downto 0) => \gras.rsts/gae.c2/v1_reg\(4 downto 0),
wr_clk => wr_clk
);
\gntv_or_sync_fifo.gl0.rd\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
port map (
AR(0) => rd_rst_i(2),
D(9 downto 0) => plusOp(10 downto 1),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => p_0_out_0(9 downto 0),
Q(9 downto 0) => rd_pntr_plus2(9 downto 0),
almost_empty => almost_empty,
empty => empty,
\gc1.count_d2_reg[9]\(9 downto 0) => rd_pntr_plus1(9 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[8]\(9 downto 0) => minusOp(9 downto 0),
\out\ => p_2_out,
p_0_out => p_0_out,
prog_empty => prog_empty,
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0),
rd_en => rd_en,
v1_reg(4 downto 0) => \gras.rsts/c0/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \gras.rsts/c1/v1_reg\(4 downto 0),
v1_reg_1(4 downto 0) => \gras.rsts/gae.c2/v1_reg\(4 downto 0)
);
\gntv_or_sync_fifo.gl0.wr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
port map (
AR(0) => wr_rst_i(1),
Q(9 downto 0) => p_12_out(9 downto 0),
RD_PNTR_WR(9 downto 0) => p_23_out(9 downto 0),
WEA(0) => \gntv_or_sync_fifo.gl0.wr_n_3\,
almost_full => almost_full,
full => full,
\grstd1.grst_full.grst_f.rst_d3_reg\ => \^wr_rst_busy\,
\out\ => rst_full_ff_i,
prog_full => prog_full,
wr_clk => wr_clk,
wr_data_count(9 downto 0) => wr_data_count(9 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
port map (
Q(9 downto 0) => p_12_out(9 downto 0),
WEA(0) => \gntv_or_sync_fifo.gl0.wr_n_3\,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc1.count_d2_reg[9]\(9 downto 0) => p_0_out_0(9 downto 0),
\out\(0) => rd_rst_i(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
rstblk: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo
port map (
WR_RST_BUSY => \^wr_rst_busy\,
\gc1.count_reg[0]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
port (
WR_RST_BUSY : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty : out STD_LOGIC;
almost_full : out STD_LOGIC;
prog_full : out STD_LOGIC;
almost_empty : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
begin
\grf.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
port map (
WR_RST_BUSY => WR_RST_BUSY,
almost_empty => almost_empty,
almost_full => almost_full,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
prog_empty => prog_empty,
prog_full => prog_full,
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0),
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_data_count(9 downto 0) => wr_data_count(9 downto 0),
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
port (
WR_RST_BUSY : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty : out STD_LOGIC;
almost_full : out STD_LOGIC;
prog_full : out STD_LOGIC;
almost_empty : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
begin
\gconvfifo.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
port map (
WR_RST_BUSY => WR_RST_BUSY,
almost_empty => almost_empty,
almost_full => almost_full,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
prog_empty => prog_empty,
prog_full => prog_full,
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0),
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_data_count(9 downto 0) => wr_data_count(9 downto 0),
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1021;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1020;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
port map (
WR_RST_BUSY => wr_rst_busy,
almost_empty => almost_empty,
almost_full => almost_full,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
prog_empty => prog_empty,
prog_full => prog_full,
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0),
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_data_count(9 downto 0) => wr_data_count(9 downto 0),
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_0,fifo_generator_v13_1_2,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_v13_1_2,Vivado 2016.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 1;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 1;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 1;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 1;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 1;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 1021;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 1020;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 1;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
port map (
almost_empty => almost_empty,
almost_full => almost_full,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(9 downto 0) => NLW_U0_data_count_UNCONNECTED(9 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => prog_empty,
prog_empty_thresh(9 downto 0) => B"0000000000",
prog_empty_thresh_assert(9 downto 0) => B"0000000000",
prog_empty_thresh_negate(9 downto 0) => B"0000000000",
prog_full => prog_full,
prog_full_thresh(9 downto 0) => B"0000000000",
prog_full_thresh_assert(9 downto 0) => B"0000000000",
prog_full_thresh_negate(9 downto 0) => B"0000000000",
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => wr_clk,
wr_data_count(9 downto 0) => wr_data_count(9 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
mit
|
e34e5c56f397191a2ba811095b0c8e8f
| 0.611959 | 2.91595 | false | false | false | false |
unhold/hdl
|
vhdl/example/function_fsmd.vhd
| 1 | 1,040 |
-- Demonstration of a functional FSMD coding style.
entity function_fsmd is
port(
clk_i,
reset_i : in bit;
a_i, b_i : in bit;
x_o, y_o : out bit);
end;
architecture rtl of function_fsmd is
type seq_t is (idle, start, run);
type state_t is record
seq : seq_t;
x : bit;
end record;
constant reset_state_c : state_t := (
seq => idle,
x => '0');
signal r : state_t;
impure function delta(r : state_t) return state_t is
variable n : state_t := r;
begin
case r.seq is
when idle =>
if a_i = '1' then
n.seq := start;
end if;
when start =>
n.seq := run;
n.x := '1';
when run =>
if b_i = '1' then
n.seq := idle;
n.x := '0';
end if;
end case;
return n;
end;
begin
sync : process(clk_i, reset_i)
begin
if reset_i = '1' then
r <= reset_state_c;
elsif rising_edge(clk_i) then
r <= delta(r);
end if;
end process;
lambda : process(r, b_i)
begin
x_o <= r.x;
if r.seq = idle then
y_o <= b_i;
else
y_o <= '0';
end if;
end process;
end;
|
gpl-3.0
|
09496e0df36bd6a71f69ff32e8f53215
| 0.556731 | 2.390805 | false | false | false | false |
freecores/w11
|
rtl/vlib/xlib/s6_cmt_sfs_gsim.vhd
| 1 | 6,362 |
-- $Id: s6_cmt_sfs_gsim.vhd 556 2014-05-29 19:01:39Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: s6_cmt_sfs - sim
-- Description: Spartan-6 CMT for simple frequency synthesis
-- simple vhdl model, without Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan-6
-- Tool versions: xst 14.5, 14.6; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.0 Initial version (derived from s7_cmt_sfs_gsim)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity s6_cmt_sfs is -- Spartan-6 CMT for simple freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT_DIVIDE : positive := 1; -- output divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or MMCM
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- pll/mmcm locked
);
end s6_cmt_sfs;
architecture sim of s6_cmt_sfs is
signal CLK_DIVPULSE : slbit := '0';
signal CLKOUT_PERIOD : time := 0 ns;
signal R_CLKOUT : slbit := '0';
signal R_LOCKED : slbit := '0';
begin
proc_init : process
-- currently frequency limits taken from Spartan-6 speed grade -2
constant f_vcomin_pll : integer := 400;
constant f_vcomax_pll : integer := 1000;
constant f_pdmin_pll : integer := 19;
constant f_pdmax_pll : integer := 375;
variable t_vco : time := 0 ns;
variable t_vcomin : time := 0 ns;
variable t_vcomax : time := 0 ns;
variable t_pd : time := 0 ns;
variable t_pdmin : time := 0 ns;
variable t_pdmax : time := 0 ns;
begin
-- validate generics
if not (GEN_TYPE = "PLL" or GEN_TYPE = "DCM") then
assert false
report "assert(GEN_TYPE='PLL' or GEN_TYPE='DCM')"
severity failure;
end if;
if VCO_DIVIDE/=1 or VCO_MULTIPLY/=1 or OUT_DIVIDE/=1 then
if GEN_TYPE = "PLL" then
-- check DIV/MULT parameter range
if VCO_DIVIDE<1 or VCO_DIVIDE>52 or
VCO_MULTIPLY<1 or VCO_MULTIPLY>64 or
OUT_DIVIDE<1 or OUT_DIVIDE>128
then
assert false
report
"assert(VCO_DIVIDE in 1:52 VCO_MULTIPLY in 1:64 OUT_DIVIDE in 1:128)"
severity failure;
end if;
-- setup VCO and PD range check boundaries
t_vcomin := (1000 ns / f_vcomax_pll) - 1 ps;
t_vcomax := (1000 ns / f_vcomin_pll) + 1 ps;
t_pdmin := (1000 ns / f_pdmax_pll) - 1 ps;
t_pdmax := (1000 ns / f_pdmin_pll) + 1 ps;
-- now check whether VCO and PD frequency is in range
t_pd := (1 ps * (1000.0*CLKIN_PERIOD)) * VCO_DIVIDE;
t_vco := t_pd / VCO_MULTIPLY;
if t_vco<t_vcomin or t_vco>t_vcomax then
assert false
report "assert(VCO frequency out of range)"
severity failure;
end if;
if t_pd<t_pdmin or t_pd>t_pdmax then
assert FALSE
report "assert(PD frequency out of range)"
severity failure;
end if;
end if; -- GEN_TYPE = "PLL"
if GEN_TYPE = "DCM" then
-- check DIV/MULT parameter range
if VCO_DIVIDE<1 or VCO_DIVIDE>32 or
VCO_MULTIPLY<2 or VCO_MULTIPLY>32 or
OUT_DIVIDE/=1
then
assert false
report
"assert(VCO_DIVIDE in 1:32 VCO_MULTIPLY in 2:32 OUT_DIVIDE=1)"
severity failure;
end if;
end if; -- GEN_TYPE = "MMCM"
end if; -- one factor /= 1
wait;
end process proc_init;
proc_clkin : process (CLKIN)
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : time := 0 ns;
variable t_period : time := 0 ns;
variable nclkin : integer := 1;
begin
if CLKIN'event then
if CLKIN = '1' then -- if CLKIN rising edge
if t_lastclkin > 0 ns then
t_lastperiod := t_period;
t_period := now - t_lastclkin;
CLKOUT_PERIOD <= (t_period * VCO_DIVIDE * OUT_DIVIDE) / VCO_MULTIPLY;
if t_lastperiod > 0 ns and abs(t_period-t_lastperiod) > 1 ps then
report "s6_cmt_sp_sfs: CLKIN unstable" severity warning;
end if;
end if;
t_lastclkin := now;
if t_period > 0 ns then
nclkin := nclkin - 1;
if nclkin <= 0 then
nclkin := VCO_DIVIDE * OUT_DIVIDE;
CLK_DIVPULSE <= '1';
R_LOCKED <= '1';
end if;
end if;
else -- if CLKIN falling edge
CLK_DIVPULSE <= '0';
end if;
end if;
end process proc_clkin;
proc_clkout : process
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : time := 0 ns;
variable t_period : time := 0 ns;
variable nclkin : integer := 1;
begin
loop
wait until CLK_DIVPULSE = '1';
for i in 1 to VCO_MULTIPLY loop
R_CLKOUT <= '1';
wait for CLKOUT_PERIOD/2;
R_CLKOUT <= '0';
if i /= VCO_MULTIPLY then
wait for CLKOUT_PERIOD/2;
end if;
end loop; -- i
end loop;
end process proc_clkout;
CLKFX <= R_CLKOUT;
LOCKED <= R_LOCKED;
end sim;
|
gpl-2.0
|
ae2738463c5f522c98f7fe1e3d9a7537
| 0.551399 | 3.839469 | false | false | false | false |
freecores/w11
|
rtl/vlib/genlib/cdc_pulse.vhd
| 2 | 3,170 |
-- $Id: cdc_pulse.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: cdc_pulse - syn
-- Description: clock domain cross for pulse
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-09 422 1.0 Initial version
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity cdc_pulse is -- clock domain cross for pulse
generic (
POUT_SINGLE : boolean := false; -- if true: single cycle pout
BUSY_WACK : boolean := false); -- if true: busy waits for ack
port (
CLKM : in slbit; -- clock master
RESET : in slbit := '0'; -- M|reset
CLKS : in slbit; -- clock slave
PIN : in slbit; -- M|pulse in
BUSY : out slbit; -- M|busy
POUT : out slbit -- S|pulse out
);
end entity cdc_pulse;
architecture syn of cdc_pulse is
signal R_REQ : slbit := '0';
signal R_REQ_C : slbit := '0';
signal R_ACK : slbit := '0';
signal R_ACK_C : slbit := '0';
signal R_ACK_S : slbit := '0';
begin
proc_master: process (CLKM)
begin
if rising_edge(CLKM) then
if RESET = '1' then
R_REQ <= '0';
else
if PIN = '1' then
R_REQ <= '1';
elsif R_ACK_S = '1' then
R_REQ <= '0';
end if;
end if;
R_ACK_C <= R_ACK;
R_ACK_S <= R_ACK_C;
end if;
end process proc_master;
proc_slave: process (CLKS)
begin
if rising_edge(CLKS) then
R_REQ_C <= R_REQ;
R_ACK <= R_REQ_C;
end if;
end process proc_slave;
SINGLE1: if POUT_SINGLE = true generate
signal R_ACK_1 : slbit := '0';
signal R_POUT : slbit := '0';
begin
proc_pout: process (CLKS)
begin
if rising_edge(CLKS) then
R_ACK_1 <= R_ACK;
if R_ACK='1' and R_ACK_1='0' then
R_POUT <= '1';
else
R_POUT <= '0';
end if;
end if;
end process proc_pout;
POUT <= R_POUT;
end generate SINGLE1;
SINGLE0: if POUT_SINGLE = false generate
begin
POUT <= R_ACK;
end generate SINGLE0;
BUSY1: if BUSY_WACK = true generate
begin
BUSY <= R_REQ or R_ACK_S;
end generate BUSY1;
BUSY0: if BUSY_WACK = false generate
begin
BUSY <= R_REQ;
end generate BUSY0;
end syn;
|
gpl-2.0
|
7df947d7b0a6f6add10037ea6d0f1c45
| 0.543533 | 3.610478 | false | false | false | false |
freecores/w11
|
rtl/w11a/pdp11_munit.vhd
| 2 | 12,645 |
-- $Id: pdp11_munit.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_munit - syn
-- Description: pdp11: mul/div unit for data (munit)
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.1 now numeric_std clean
-- 2010-09-18 300 1.1 renamed from mbox
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_munit is -- mul/div unit for data (munit)
port (
CLK : in slbit; -- clock
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
DTMP : in slv16; -- 'tmp' data in
GPR_DSRC : in slv16; -- 'src' data from GPR
FUNC : in slv2; -- function
S_DIV : in slbit; -- s_opg_div state
S_DIV_CN : in slbit; -- s_opg_div_cn state
S_DIV_CR : in slbit; -- s_opg_div_cr state
S_ASH : in slbit; -- s_opg_ash state
S_ASH_CN : in slbit; -- s_opg_ash_cn state
S_ASHC : in slbit; -- s_opg_ashc state
S_ASHC_CN : in slbit; -- s_opg_ashc_cn state
SHC_TC : out slbit; -- last shc cycle (shc==0)
DIV_CR : out slbit; -- division: reminder correction needed
DIV_CQ : out slbit; -- division: quotient correction needed
DIV_ZERO : out slbit; -- division: divident or divisor zero
DIV_OVFL : out slbit; -- division: overflow
DOUT : out slv16; -- data output
DOUTE : out slv16; -- data output extra
CCOUT : out slv4 -- condition codes out
);
end pdp11_munit;
architecture syn of pdp11_munit is
signal R_DD_L : slv16 := (others=>'0'); -- divident, low order part
signal R_DDO_LT : slbit := '0'; -- original sign bit of divident
signal R_DIV_V : slbit := '0'; -- V flag for division
signal R_SHC : slv6 := (others=>'0'); -- shift counter for div and ash/c
signal R_C1 : slbit := '0'; -- first cycle indicator
signal R_MSBO : slbit := '0'; -- original sign bit for ash/c
signal R_ASH_V : slbit := '0'; -- V flag for ash/c
signal R_ASH_C : slbit := '0'; -- C flag for ash/c
signal NEXT_DD_L : slv16 := (others=>'0');
signal NEXT_DDO_LT : slbit := '0';
signal NEXT_DIV_V : slbit := '0';
signal NEXT_SHC : slv6 := (others=>'0');
signal NEXT_C1 : slbit := '0';
signal NEXT_MSBO : slbit := '0';
signal NEXT_ASH_V : slbit := '0';
signal NEXT_ASH_C : slbit := '0';
signal SHC_TC_L : slbit := '0';
signal DDST_ZERO : slbit := '0';
signal DSRC_ZERO : slbit := '0';
signal DSRC_ONES : slbit := '0';
signal DTMP_ZERO : slbit := '0';
signal DOUT_DIV : slv16 := (others=>'0');
signal DOUTE_DIV : slv16 := (others=>'0');
alias DR : slv16 is DDST; -- divisor (in DDST)
alias DD_H : slv16 is DSRC; -- divident, high order part (in DSRC)
alias Q : slv16 is DTMP; -- quotient (accumulated in DTMP)
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
R_DD_L <= NEXT_DD_L;
R_DDO_LT <= NEXT_DDO_LT;
R_DIV_V <= NEXT_DIV_V;
R_SHC <= NEXT_SHC;
R_C1 <= NEXT_C1;
R_MSBO <= NEXT_MSBO;
R_ASH_V <= NEXT_ASH_V;
R_ASH_C <= NEXT_ASH_C;
end if;
end process proc_regs;
proc_comm: process (DDST, DSRC, DTMP)
begin
DDST_ZERO <= '0';
DSRC_ZERO <= '0';
DSRC_ONES <= '0';
DTMP_ZERO <= '0';
if unsigned(DDST) = 0 then
DDST_ZERO <= '1';
end if;
if unsigned(DSRC) = 0 then
DSRC_ZERO <= '1';
end if;
if signed(DSRC) = -1 then
DSRC_ONES <= '1';
end if;
if unsigned(DTMP) = 0 then
DTMP_ZERO <= '1';
end if;
end process proc_comm;
proc_shc: process (DDST, R_SHC, R_C1,
S_DIV, S_DIV_CN, S_ASH, S_ASH_CN, S_ASHC, S_ASHC_CN)
begin
NEXT_SHC <= R_SHC;
NEXT_C1 <= R_C1;
if S_ASH='1' or S_ASHC='1' then
NEXT_SHC <= DDST(5 downto 0);
NEXT_C1 <= '1';
end if;
if S_DIV = '1' then
NEXT_SHC <= "001111";
NEXT_C1 <= '1';
end if;
if S_DIV_CN='1' or S_ASH_CN='1' or S_ASHC_CN='1' then
if R_SHC(5) = '0' then
NEXT_SHC <= slv(unsigned(R_SHC) - 1);
else
NEXT_SHC <= slv(unsigned(R_SHC) + 1);
end if;
NEXT_C1 <= '0';
end if;
SHC_TC_L <= '0';
if unsigned(R_SHC) = 0 then
SHC_TC_L <= '1';
end if;
end process proc_shc;
proc_div: process (DDST, DSRC, DTMP, GPR_DSRC, DR, DD_H, Q,
R_DD_L, R_DDO_LT, R_DIV_V, R_SHC, R_C1,
S_DIV, S_DIV_CN, S_DIV_CR,
DDST_ZERO, DSRC_ZERO, DTMP_ZERO)
variable shftdd : slbit := '0';
variable subadd : slbit := '0';
variable dd_gt : slbit := '0';
variable qbit : slbit := '0';
variable qbit_1 : slbit := '0';
variable qbit_n : slbit := '0';
variable dd_h_old : slv16 := (others=>'0'); -- dd_h before add/sub
variable dd_h_new : slv16 := (others=>'0'); -- dd_h after add/sub
begin
NEXT_DD_L <= R_DD_L;
NEXT_DDO_LT <= R_DDO_LT;
NEXT_DIV_V <= R_DIV_V;
DIV_ZERO <= '0';
DIV_OVFL <= '0';
qbit_1 := not (DR(15) xor DD_H(15)); -- !(dr<0 ^ dd_h<0)
shftdd := not S_DIV_CR;
if shftdd = '1' then
dd_h_old := DD_H(14 downto 0) & R_DD_L(15);
else
dd_h_old := DD_H(15 downto 0);
end if;
if R_C1 = '1' then
subadd := qbit_1;
DIV_ZERO <= DDST_ZERO or
(DSRC_ZERO and DTMP_ZERO); -- note: DTMP here still dd_low !
else
subadd := Q(0);
end if;
if subadd = '0' then
dd_h_new := slv(signed(dd_h_old) + signed(DR));
else
dd_h_new := slv(signed(dd_h_old) - signed(DR));
end if;
dd_gt := '0';
if dd_h_new(15) = '0' and
(unsigned(dd_h_new(14 downto 0))/=0 or
unsigned(R_DD_L(14 downto 0))/=0)
then
dd_gt := '1'; -- set if dd_new > 0
end if;
if R_DDO_LT = '0' then
qbit_n := DR(15) xor not dd_h_new(15); -- b_dr_lt ^ !b_dd_lt
else
qbit_n := DR(15) xor dd_gt; -- b_dr_lt ^ b_dd_gt
end if;
if S_DIV = '1' then
NEXT_DDO_LT <= DD_H(15);
NEXT_DD_L <= GPR_DSRC;
end if;
if R_C1 = '1' then
NEXT_DIV_V <= (DD_H(15) xor DD_H(14)) or
(DD_H(15) xor (DR(15) xor qbit_n));
DIV_OVFL <= (DD_H(15) xor DD_H(14)) or --??? cleanup
(DD_H(15) xor (DR(15) xor qbit_n)); --??? cleanup
end if;
if S_DIV_CN = '1' then
NEXT_DD_L <= R_DD_L(14 downto 0) & '0';
end if;
if S_DIV_CN = '1' then
qbit := qbit_n;
else
qbit := qbit_1;
end if;
DIV_CR <= not (R_DDO_LT xor
(DR(15) xor Q(0))); --!(b_ddo_lt ^ (b_dr_lt ^ b_qbit));
DIV_CQ <= R_DDO_LT xor DR(15); -- b_ddo_lt ^ b_dr_lt;
DOUT_DIV <= dd_h_new;
DOUTE_DIV <= Q(14 downto 0) & qbit;
end process proc_div;
proc_ash: process (R_MSBO, R_ASH_V, R_ASH_C, R_SHC, DSRC, DTMP, FUNC,
S_ASH, S_ASH_CN, S_ASHC, S_ASHC_CN, SHC_TC_L)
begin
NEXT_MSBO <= R_MSBO;
NEXT_ASH_V <= R_ASH_V;
NEXT_ASH_C <= R_ASH_C;
if S_ASH='1' or S_ASHC='1' then
NEXT_MSBO <= DSRC(15);
NEXT_ASH_V <= '0';
NEXT_ASH_C <= '0';
end if;
if (S_ASH_CN='1' or S_ASHC_CN='1') and SHC_TC_L='0' then
if R_SHC(5) = '0' then -- left shift
if (R_MSBO xor DSRC(14))='1' then
NEXT_ASH_V <= '1';
end if;
NEXT_ASH_C <= DSRC(15);
else -- right shift
if FUNC = c_munit_func_ash then
NEXT_ASH_C <= DSRC(0);
else
NEXT_ASH_C <= DTMP(0);
end if;
end if;
end if;
end process proc_ash;
proc_omux: process (DSRC, DDST, DTMP, FUNC,
R_ASH_V, R_ASH_C, R_SHC, R_DIV_V,
DOUT_DIV, DOUTE_DIV,
DSRC_ZERO, DSRC_ONES, DTMP_ZERO, DDST_ZERO)
variable prod : slv32 := (others=>'0');
variable omux_sel : slv2 := "00";
variable ash_dout0 : slbit := '0';
variable mul_c : slbit := '0';
begin
prod := slv(signed(DSRC) * signed(DDST));
case FUNC is
when c_munit_func_mul =>
omux_sel := "00";
when c_munit_func_div =>
omux_sel := "01";
when c_munit_func_ash |c_munit_func_ashc =>
if R_SHC(5) = '0' then
omux_sel := "10";
else
omux_sel := "11";
end if;
when others => null;
end case;
if FUNC = c_munit_func_ash then
ash_dout0 := '0';
else
ash_dout0 := DTMP(15);
end if;
case omux_sel is
when "00" => -- MUL
DOUT <= prod(31 downto 16);
DOUTE <= prod(15 downto 0);
when "01" => -- DIV
DOUT <= DOUT_DIV;
DOUTE <= DOUTE_DIV;
when "10" => -- shift left
DOUT <= DSRC(14 downto 0) & ash_dout0;
DOUTE <= DTMP(14 downto 0) & "0";
when "11" => -- shift right
DOUT <= DSRC(15) & DSRC(15 downto 1);
DOUTE <= DSRC(0) & DTMP(15 downto 1);
when others => null;
end case;
mul_c := '0'; -- MUL C codes is set if
if DSRC(15) = '0' then
if DSRC_ZERO='0' or DTMP(15)='1' then -- for positive results when
mul_c := '1'; -- product > 2^15-1
end if;
else -- for negative results when
if DSRC_ONES='0' or DTMP(15)='0' then
mul_c := '1'; -- product < -2^15
end if;
end if;
case FUNC is
when c_munit_func_mul =>
CCOUT(3) <= DSRC(15); -- N
CCOUT(2) <= DSRC_ZERO and DTMP_ZERO;-- Z
CCOUT(1) <= '0'; -- V=0
CCOUT(0) <= mul_c; -- C
when c_munit_func_div =>
if DDST_ZERO = '1' then
CCOUT(3) <= '0'; -- N=0 if div/0
CCOUT(2) <= '1'; -- Z=1 if div/0
elsif R_DIV_V = '1' then
CCOUT(3) <= DSRC(15) xor DDST(15); -- N (from unchanged reg)
CCOUT(2) <= '0'; -- Z (from unchanged reg) ??? veri
else
CCOUT(3) <= DTMP(15); -- N (from Q (DTMP))
CCOUT(2) <= DTMP_ZERO; -- Z (from Q (DTMP)) ??? verify
end if;
CCOUT(1) <= R_DIV_V or DDST_ZERO; -- V
CCOUT(0) <= DDST_ZERO; -- C (dst=0)
when c_munit_func_ash =>
CCOUT(3) <= DSRC(15); -- N
CCOUT(2) <= DSRC_ZERO; -- Z
CCOUT(1) <= R_ASH_V; -- V
CCOUT(0) <= R_ASH_C; -- C
when c_munit_func_ashc =>
CCOUT(3) <= DSRC(15); -- N
CCOUT(2) <= DSRC_ZERO and DTMP_ZERO;-- Z
CCOUT(1) <= R_ASH_V; -- V
CCOUT(0) <= R_ASH_C; -- C
when others => null;
end case;
end process proc_omux;
SHC_TC <= SHC_TC_L;
end syn;
|
gpl-2.0
|
8f73ea3ce40f0d3d28c60cdda6a96d39
| 0.464848 | 3.229885 | false | false | false | false |
freecores/w11
|
rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd
| 1 | 7,807 |
-- $Id: tb_nexys2_fusp.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys2_fusp - sim
-- Description: Test bench for nexys2 (base+fusp)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- xlib/dcm_sfs
-- rlink/tb/tbcore_rlink
-- tb_nexys2_core
-- serport/serport_uart_rxtx
-- nexys2_fusp_aif [UUT]
--
-- To test: generic, any nexys2_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 3.2 new system clock scheme, new tbcore_rlink iface
-- 2011-11-26 433 3.1.1 remove O_FLA_CE_N from tb_nexys2_core
-- 2011-11-21 432 3.1 update O_FLA_CE_N usage
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-29 351 3.0 use rlink/tb now
-- 2010-11-13 338 1.0.2 now dcm aware: add O_CLKSYS, use rritb_core_dcm
-- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
-- 2010-05-28 295 1.0 Initial version (derived from tb_s3board_fusp)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serportlib.all;
use work.xlib.all;
use work.nexys2lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys2_fusp is
end tb_nexys2_fusp;
architecture sim of tb_nexys2_fusp is
signal CLKOSC : slbit := '0';
signal CLKCOM : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal RX_HOLD : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slbit := '1';
signal O_MEM_BE_N : slv2 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADV_N : slbit := '1';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal O_FLA_CE_N : slbit := '0';
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal R_PORTSEL : slbit := '0';
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
);
DCM_COM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
RX_HOLD <= TXBUSY or RTS_N; -- back preasure for data flow to tb
N2CORE : entity work.tb_nexys2_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
UUT : nexys2_fusp_aif
port map (
I_CLK50 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_FLA_CE_N => O_FLA_CE_N,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
UART : serport_uart_rxtx
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => UART_TXD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
proc_port_mux: process (R_PORTSEL, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
if R_PORTSEL = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
I_FUSP_CTS_N <= '0';
else -- otherwise use pmod1 rs232
I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
I_FUSP_CTS_N <= CTS_N;
UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
RTS_N <= O_FUSP_RTS_N;
I_RXD <= '1'; -- port 0 inputs to idle state
end if;
end process proc_port_mux;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL <= to_x01(SB_DATA(0));
end if;
end if;
end process proc_simbus;
end sim;
|
gpl-2.0
|
c31e75a1aa81df2c965002adea1f2642
| 0.533367 | 3.106645 | false | false | false | false |
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