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yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
comparator/com/com.vhd
| 1 | 691 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity COM is
-- generic (D:time);
port (N1, N0, M1, M0: in BIT;
GE, LE, E, G, L: out BIT);
end COM;
use work.TRUTH4x5.all;
architecture TABLE of COM is
begin
process (N1,N0,M1,M0)
variable INDEX: INTEGER;
variable WOUT: WORD;
begin
INDEX := INTVAL (N1&N0&M1&M0);
WOUT := TRUTH (INDEX);
GE <= WOUT(4);-- after D;
LE <= WOUT(3);-- after D;
E <= WOUT(2);-- after D;
G <= WOUT(1);-- after D;
L <= WOUT(0);-- after D;
end process;
end TABLE;
--Figure 8.4 VHDL model for device COM using the ARRAY method.
|
mit
|
3d90e94f157d07f61b8a08ffa28349a7
| 0.586107 | 2.7751 | false | false | false | false |
rickyzhangNYC/Pipelined_Multimedia_Cell_Lite_Unit
|
InstructionBuffer.vhd
| 1 | 2,866 |
-------------------------------------------------------------------------------
--
-- Title : InstructionBuffer
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\InstructionBuffer.vhd
-- Generated : Wed Dec 7 14:16:19 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {InstructionBuffer} architecture {behavioral}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
entity InstructionBuffer is
port (
instruction_din: in std_logic_vector(255 downto 0);
instruction_load_enable : in std_logic;
clk : in std_logic;
instruction_dout : out std_logic_vector(15 downto 0)
);
end InstructionBuffer;
--}} End of automatically maintained section
architecture behavioral of InstructionBuffer is
type instruction_buffer is array (0 to 15) of std_logic_vector(15 downto 0); --16 ,16 bit instructions
begin
instructions: process(clk)
variable instruction_buffer_v : instruction_buffer;
variable program_counter : integer range 0 to 15 := 0;
begin
if instruction_load_enable = '1' then
program_counter := 0;
instruction_buffer_v(0) := instruction_din(255 downto 240);
instruction_buffer_v(1) := instruction_din(239 downto 224);
instruction_buffer_v(2) := instruction_din(223 downto 208);
instruction_buffer_v(3) := instruction_din(207 downto 192);
instruction_buffer_v(4) := instruction_din(191 downto 176);
instruction_buffer_v(5) := instruction_din(175 downto 160);
instruction_buffer_v(6) := instruction_din(159 downto 144);
instruction_buffer_v(7) := instruction_din(143 downto 128);
instruction_buffer_v(8) := instruction_din(127 downto 112);
instruction_buffer_v(9) := instruction_din(111 downto 96);
instruction_buffer_v(10) := instruction_din(95 downto 80);
instruction_buffer_v(11) := instruction_din(79 downto 64);
instruction_buffer_v(12) := instruction_din(63 downto 48);
instruction_buffer_v(13) := instruction_din(47 downto 32);
instruction_buffer_v(14) := instruction_din(31 downto 16);
instruction_buffer_v(15) := instruction_din(15 downto 0);
else
if rising_edge(clk) then
instruction_dout <= instruction_buffer_v(program_counter);
if program_counter /= 15 then
program_counter := program_counter + 1;
end if;
end if;
end if;
end process;
end behavioral;
|
apache-2.0
|
dbb12004eaed24c8c7fa663d842f75b2
| 0.60328 | 3.81117 | false | false | false | false |
Digilent/vivado-library
|
ip/usb2device_v1_0/src/Context_to_Stream.vhd
| 2 | 15,958 |
-------------------------------------------------------------------------------
--
-- File: Context_to_Stream.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module handles control data transfers through the DMA module
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Context_to_Stream is
Port (
CLK : in STD_LOGIC;
RESETN : in STD_LOGIC;
ind_statte_axistream : out std_logic_vector(4 downto 0);
dQH_RD : in STD_LOGIC;
dQH_WR : in STD_LOGIC;
dTD_RD : in STD_LOGIC;
dTD_WR : in STD_LOGIC;
SETUP_WR : in STD_LOGIC;
dQH_WR_EN : out STD_LOGIC;
s_axis_mm2s_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_mm2s_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_mm2s_tvalid : IN STD_LOGIC;
s_axis_mm2s_tready : OUT STD_LOGIC;
s_axis_mm2s_tlast : IN STD_LOGIC;
m_axis_s2mm_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_s2mm_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_s2mm_tvalid : OUT STD_LOGIC;
m_axis_s2mm_tready : IN STD_LOGIC;
m_axis_s2mm_tlast : OUT STD_LOGIC;
--READ S2MM
dQH_MULT_rd : in STD_LOGIC_VECTOR (1 downto 0);
dQH_ZLT_rd : in STD_LOGIC;
dQH_MAX_PACKET_LENGTH_rd : in STD_LOGIC_VECTOR (10 downto 0);
dQH_IOS_rd : in STD_LOGIC;
dQH_CURRENT_dTD_POINTER_rd : in STD_LOGIC_VECTOR (26 downto 0);
dQH_NEXT_dTD_POINTER_rd : in STD_LOGIC_VECTOR (26 downto 0);
dQH_T_rd : in STD_LOGIC;
dQH_SETUP_BUFFER_BYTES_3_0_rd : in STD_LOGIC_VECTOR (31 downto 0);
dQH_SETUP_BUFFER_BYTES_7_4_rd : in STD_LOGIC_VECTOR (31 downto 0);
dTD_TOTAL_BYTES_rd : in STD_LOGIC_VECTOR (14 downto 0);
dTD_IOC_rd : in STD_LOGIC;
dTD_C_PAGE_rd : in STD_LOGIC_VECTOR (2 downto 0);
dTD_MULT_rd : in STD_LOGIC_VECTOR (1 downto 0);
dTD_STATUS_rd : in STD_LOGIC_VECTOR (7 downto 0);
dTD_PAGE0_rd : in STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE1_rd : in STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE2_rd : in STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE3_rd : in STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE4_rd : in STD_LOGIC_VECTOR (19 downto 0);
dTD_CURRENT_OFFSET_rd : in STD_LOGIC_VECTOR (11 downto 0);
--WRITE MM2S
dQH_MULT_wr : out STD_LOGIC_VECTOR (1 downto 0);
dQH_ZLT_wr : out STD_LOGIC;
dQH_MAX_PACKET_LENGTH_wr : out STD_LOGIC_VECTOR (10 downto 0);
dQH_IOS_wr : out STD_LOGIC;
dQH_CURRENT_dTD_POINTER_wr : out STD_LOGIC_VECTOR (26 downto 0);
dQH_NEXT_dTD_POINTER_wr : out STD_LOGIC_VECTOR (26 downto 0);
dQH_T_wr : out STD_LOGIC;
dQH_SETUP_BUFFER_BYTES_3_0_wr : out STD_LOGIC_VECTOR (31 downto 0);
dQH_SETUP_BUFFER_BYTES_7_4_wr : out STD_LOGIC_VECTOR (31 downto 0);
dTD_TOTAL_BYTES_wr : out STD_LOGIC_VECTOR (14 downto 0);
dTD_IOC_wr : out STD_LOGIC;
dTD_C_PAGE_wr : out STD_LOGIC_VECTOR (2 downto 0);
dTD_MULT_wr : out STD_LOGIC_VECTOR (1 downto 0);
dTD_STATUS_wr : out STD_LOGIC_VECTOR (7 downto 0);
dTD_PAGE0_wr : out STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE1_wr : out STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE2_wr : out STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE3_wr : out STD_LOGIC_VECTOR (19 downto 0);
dTD_PAGE4_wr : out STD_LOGIC_VECTOR (19 downto 0);
dTD_CURRENT_OFFSET_wr : out STD_LOGIC_VECTOR (11 downto 0)
);
end Context_to_Stream;
architecture Behavioral of Context_to_Stream is
type state_type is (IDLE, WRITE_DQH, WRITE_DTD, READ_DQH, READ_DTD, WRITE_SETUP, ERROR);
signal state, next_state : state_type;
type dQH_vector is array (11 downto 0) of std_logic_vector(31 downto 0);
signal dQH_vector_rd : dQH_vector;
signal dQH_vector_rd_reg : dQH_vector;
signal dQH_vector_wr : dQH_vector;
signal count : integer range 0 to 11;
signal index : integer range 0 to 11;
signal wr_en_aux : STD_LOGIC_VECTOR (11 downto 0);
signal count_en : STD_LOGIC;
signal count_reset : STD_LOGIC;
signal dQH_write_enable : STD_LOGIC;
signal dQH_write_enable_reg : STD_LOGIC;
signal s_axis_tdata : STD_LOGIC_VECTOR (31 downto 0);
signal s_axi_tready : STD_LOGIC;
signal m_axis_tdata : STD_LOGIC_VECTOR (31 downto 0);
signal m_axis_tlast : STD_LOGIC;
signal m_axis_tvalid : STD_LOGIC;
-- attribute mark_debug : string;
-- attribute keep : string;
-- attribute mark_debug of m_axis_s2mm_tready : signal is "true";
-- attribute keep of m_axis_s2mm_tready : signal is "true";
-- attribute mark_debug of count : signal is "true";
-- attribute keep of count : signal is "true";
begin
dQH_WR_EN <= dQH_write_enable_reg;
m_axis_s2mm_tkeep <= "1111";
s_axis_tdata <= s_axis_mm2s_tdata;
m_axis_s2mm_tdata <= m_axis_tdata;
m_axis_s2mm_tlast <= m_axis_tlast;
s_axis_mm2s_tready <= s_axi_tready;
m_axis_s2mm_tvalid <= m_axis_tvalid;
dQH_MULT_wr <= dQH_vector_rd_reg (0)(31 downto 30);
dQH_ZLT_wr <= dQH_vector_rd_reg (0)(29);
dQH_MAX_PACKET_LENGTH_wr <= dQH_vector_rd_reg (0)(26 downto 16);
dQH_IOS_wr <= dQH_vector_rd_reg (0)(15);
dQH_CURRENT_dTD_POINTER_wr <= dQH_vector_rd_reg (1)(31 downto 5);
dQH_NEXT_dTD_POINTER_wr <= dQH_vector_rd_reg (2)(31 downto 5);
dQH_T_wr <= dQH_vector_rd_reg (2)(0);
dQH_SETUP_BUFFER_BYTES_3_0_wr <= dQH_vector_rd_reg (10);
dQH_SETUP_BUFFER_BYTES_7_4_wr <= dQH_vector_rd_reg (11);
dTD_TOTAL_BYTES_wr <= dQH_vector_rd_reg (3)(30 downto 16);
dTD_IOC_wr <= dQH_vector_rd_reg (3)(15);
dTD_C_PAGE_wr <= dQH_vector_rd_reg (3)(14 downto 12);
dTD_MULT_wr <= dQH_vector_rd_reg (3)(11 downto 10);
dTD_STATUS_wr <= dQH_vector_rd_reg (3)(7 downto 0);
dTD_PAGE0_wr <= dQH_vector_rd_reg (4)(31 downto 12);
dTD_PAGE1_wr <= dQH_vector_rd_reg (5)(31 downto 12);
dTD_PAGE2_wr <= dQH_vector_rd_reg (6)(31 downto 12);
dTD_PAGE3_wr <= dQH_vector_rd_reg (7)(31 downto 12);
dTD_PAGE4_wr <= dQH_vector_rd_reg (8)(31 downto 12);
dTD_CURRENT_OFFSET_wr <= dQH_vector_rd_reg (4)(11 downto 0);
dQH_vector_wr(0) <= dQH_MULT_rd & dQH_ZLT_rd & "00" & dQH_MAX_PACKET_LENGTH_rd & dQH_IOS_rd & "000000000000000";
dQH_vector_wr(1) <= dQH_CURRENT_dTD_POINTER_rd & "00000";
dQH_vector_wr(2) <= dQH_NEXT_dTD_POINTER_rd & "0000" & dQH_T_rd;
dQH_vector_wr(3) <= '0' & dTD_TOTAL_BYTES_rd & dTD_IOC_rd & dTD_C_PAGE_rd & dTD_MULT_rd & "00" & dTD_STATUS_rd;
dQH_vector_wr(4) <= dTD_PAGE0_rd & dTD_CURRENT_OFFSET_rd;
dQH_vector_wr(5) <= dTD_PAGE1_rd & "000000000000";
dQH_vector_wr(6) <= dTD_PAGE2_rd & "000000000000";
dQH_vector_wr(7) <= dTD_PAGE3_rd & "000000000000";
dQH_vector_wr(8) <= dTD_PAGE4_rd & "000000000000";
dQH_vector_wr(9) <= (others => '0');
dQH_vector_wr(10) <= dQH_SETUP_BUFFER_BYTES_3_0_rd;
dQH_vector_wr(11) <= dQH_SETUP_BUFFER_BYTES_7_4_rd;
process (CLK)
begin
if (CLK'event and CLK = '1') then
if (RESETN = '0') then
dQH_vector_rd_reg <= (others=> (others=>'0'));
dQH_write_enable_reg <= '0';
else
dQH_write_enable_reg <= dQH_write_enable;
for index in 0 to 11 loop
if (wr_en_aux(index) = '1') then
dQH_vector_rd_reg(index) <= dQH_vector_rd(index);
end if;
end loop;
end if;
end if;
end process;
COUNTER: process (CLK, count_en)
begin
if (CLK'event and CLK = '1') then
if (RESETN = '0' or count_reset = '1') then
count <= 0;
elsif (count_en = '1') then
count <= count + 1;
end if;
end if;
end process;
SYNC_PROC: process (CLK)
begin
if (CLK'event and CLK = '1') then
if (RESETN = '0') then
state <= IDLE;
-- init_write_dma_reg <= '0';
-- init_read_dma_reg <= '0';
else
state <= next_state;
-- init_write_dma_reg <= init_write_dma;
-- init_read_dma_reg <= init_read_dma;
end if;
end if;
end process;
NEXT_STATE_DECODE: process (state, dQH_RD, dQH_WR, dTD_RD, dTD_WR, SETUP_WR, s_axis_mm2s_tvalid, s_axis_tdata, count, s_axis_mm2s_tlast, dQH_vector_wr, m_axis_s2mm_tready)
begin
--declare default state for next_state to avoid latches
next_state <= state; --default is to stay in current state
count_reset <= '1';
count_en <= '0';
dQH_vector_rd <= (others=> (others=>'0'));
m_axis_tlast <= '0';
m_axis_tdata <= (others => '0');
s_axi_tready <= '0';
dQH_write_enable <= '0';
m_axis_tvalid <= '0';
wr_en_aux <= (others => '0');
ind_statte_axistream <= (others => '0');
--insert statements to decode next_state
--below is a simple example
case state is
when IDLE =>
if (dQH_RD = '1') then
count_reset <= '0';
next_state <= READ_DQH;
elsif (dTD_RD = '1') then
count_reset <= '0';
next_state <= READ_DTD;
elsif (dQH_WR = '1') then
count_reset <= '0';
next_state <= WRITE_DQH;
elsif (dTD_WR = '1') then
count_reset <= '0';
next_state <= WRITE_DTD;
elsif (SETUP_WR = '1') then
count_reset <= '0';
next_state <= WRITE_SETUP;
else
next_state <= IDLE;
end if;
when READ_DQH => --READ(mm2s) on axi_stream slave
ind_statte_axistream <= "00001";
count_reset <= '0';
dQH_vector_rd(count) <= s_axis_tdata;
s_axi_tready <= '1';
--wr_en_aux(count) <= '1';
if (s_axis_mm2s_tvalid = '1') then
wr_en_aux(count) <= '1';
count_en <= '1';
if (count = 11) then
if (s_axis_mm2s_tlast = '1') then
dQH_write_enable <= '1';
count_reset <= '1';
next_state <= IDLE;
else
next_state <= ERROR;
end if;
else
next_state <= READ_DQH;
end if;
end if;
when READ_DTD => --READ(mm2s) on axi_stream slave
ind_statte_axistream <= "00010";
count_reset <= '0';
dQH_vector_rd(count+2) <= s_axis_tdata;
s_axi_tready <= '1';
-- wr_en_aux(count+2) <= '1'; --data needs to be copied in the overlay area so a +2 offset is required
if (s_axis_mm2s_tvalid = '1') then
wr_en_aux(count+2) <= '1'; --data needs to be copied in the overlay area so a +2 offset is required
count_en <= '1';
if (count = 6) then
if (s_axis_mm2s_tlast = '1') then
dQH_write_enable <= '1';
count_reset <= '1';
next_state <= IDLE;
else
next_state <= ERROR;
end if;
else
next_state <= READ_DTD;
end if;
end if;
when WRITE_DQH => --WRITE(s2mm) on axi_stream master
ind_statte_axistream <= "00100";
count_reset <= '0';
m_axis_tdata <= dQH_vector_wr(count);
m_axis_tvalid <= '1';
if (m_axis_s2mm_tready = '1') then
count_en <= '1';
if (count = 11) then
m_axis_tlast <= '1';
count_reset <= '1';
next_state <= IDLE;
else
next_state <= WRITE_DQH;
end if;
end if;
when WRITE_DTD => --WRITE(s2mm) on axi_stream master
ind_statte_axistream <= "00101";
count_reset <= '0';
m_axis_tdata <= dQH_vector_wr(count);
m_axis_tvalid <= '1';
if (m_axis_s2mm_tready = '1') then
count_en <= '1';
if (count = 6) then
m_axis_tlast <= '1';
count_reset <= '1';
next_state <= IDLE;
else
next_state <= WRITE_DTD;
end if;
end if;
when WRITE_SETUP => --WRITE(s2mm) on axi_stream master
ind_statte_axistream <= "00110";
count_reset <= '0';
m_axis_tdata <= dQH_vector_wr(count+10);
m_axis_tvalid <= '1';
if (m_axis_s2mm_tready = '1') then
count_en <= '1';
if (count = 1) then
m_axis_tlast <= '1';
count_reset <= '1';
next_state <= IDLE;
else
next_state <= WRITE_SETUP;
end if;
end if;
when ERROR =>
next_state <= IDLE;
when others =>
next_state <= IDLE;
end case;
end process;
end Behavioral;
|
mit
|
47826667feac4e7e6a1208400010bf2c
| 0.535593 | 3.57322 | false | false | false | false |
Digilent/vivado-library
|
ip/MIPI_CSI_2_RX/hdl/CRC16_behavioral.vhd
| 1 | 3,954 |
-------------------------------------------------------------------------------
--
-- File: CRC16_behavioral.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI CSI-2 Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
-- Additional Comments: Sub-optimal implementation of CRC-16, with untested
-- bByteIgnore.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CRC16 is
Generic (
kLaneCount : natural range 1 to 4 := 2
);
Port (
ByteClk : in STD_LOGIC;
bData : in STD_LOGIC_VECTOR (kLaneCount*8-1 downto 0);
bDataEnable : in std_logic;
bKeep : in STD_LOGIC_VECTOR (kLaneCount-1 downto 0);
bCRC : out STD_LOGIC_VECTOR (15 downto 0);
bRst : in STD_LOGIC);
end CRC16;
architecture Behavioral of CRC16 is
function crc16_serial ( crc : std_logic_vector;
data_in : std_logic) return std_logic_vector is
variable crc_new : std_logic_vector(15 downto 0);
begin
if ((crc(0) xor data_in) = '1') then
crc_new := ('0' & crc(15 downto 1)) xor x"8408";
else
crc_new := '0' & crc(15 downto 1);
end if;
return crc_new;
end crc16_serial;
signal crc : std_logic_vector(15 downto 0);
begin
process(ByteClk)
variable crc_temp : std_logic_vector(15 downto 0);
begin
if Rising_Edge(ByteClk) then
if (bRst = '1') then
crc <= x"FFFF";
elsif (bDataEnable = '1') then
crc_temp := crc;
if std_match(bKeep, "1111") then
for i in 0 to 32-0*8-1 loop
crc_temp := crc16_serial(crc_temp, bData(i));
end loop;
elsif std_match(bKeep, "0111") then
for i in 0 to 32-1*8-1 loop
crc_temp := crc16_serial(crc_temp, bData(i));
end loop;
elsif std_match(bKeep, "-011") then
for i in 0 to 32-2*8-1 loop
crc_temp := crc16_serial(crc_temp, bData(i));
end loop;
elsif std_match(bKeep, "--01") then
for i in 0 to 32-3*8-1 loop
crc_temp := crc16_serial(crc_temp, bData(i));
end loop;
end if;
crc <= crc_temp;
end if;
end if;
end process;
bCRC <= crc;
end Behavioral;
|
mit
|
33c488220743803eaa742206f753fb14
| 0.579413 | 4.153361 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
serial2parallel/serial2parallel.vhd
| 1 | 2,677 |
-- Serial to Parallel Converter
entity STOP is
port (R, A, D, CLK: in BIT;
Z: out BIT_VECTOR(3 downto 0);
DONE: out BIT);
end STOP;
-- State Machine Description
-- for Serial to Parallel Converter (STOP)
architecture FSM_RTL of STOP is
type STATE_TYPE is (S0, S1, S2, S3, S4, S5);
signal STATE: STATE_TYPE;
signal SHIFT_REG: BIT_VECTOR (3 downto 0);
begin
-- Process to update state at end of each clock period.
MY_STATE: process (CLK)
begin
if CLK='1' then
case STATE is
when S0 =>
-- Data Section
-- Control Section
if R='1' or A='0' then
STATE <= S0;
elsif R='0' and A='1' then
STATE <= S1;
end if;
when S1 =>
-- Data Section
-- Shift in the first bit
SHIFT_REG <= D & SHIFT_REG(3 downto 1);
-- Control Section
if R='0' then
STATE <= S2;
elsif R='1' then
STATE <= S0;
end if;
when S2 =>
-- Data Section
-- Shift in the second bit
SHIFT_REG <= D & SHIFT_REG(3 downto 1);
-- Control Section
if R='0' then
STATE <= S3;
elsif R='1' then
STATE <= S0;
end if;
--Figure 8.25a VHDL model for serial to parallel converter.
-- Continuation of architecture FSM_RTL of STOP
--
when S3 =>
-- Data Section
-- Shift in the third bit
SHIFT_REG <= D & SHIFT_REG(3 downto 1);
-- Control Section
if R='0' then
STATE <= S4;
elsif R='1' then
STATE <= S0;
end if;
when S4 =>
-- Data Section
-- Shift in the fourth bit
SHIFT_REG <= D & SHIFT_REG(3 downto 1);
-- Control Section
if R='0' then
STATE <= S5;
elsif R='1' then
STATE <= S0;
end if;
when S5 =>
-- Data Section
-- Control Section
if R='0' and A='1' then
STATE <= S1;
elsif R='1' or A='0' then
STATE <= S0;
end if;
end case;
end if;
end process MY_STATE;
--
-- Output process
--
OUTPUT: process (STATE)
begin
case STATE is
when S0 to S4 =>
DONE <= '0';
when S5 =>
DONE <= '1';
Z <= SHIFT_REG;
end case;
end process OUTPUT;
end FSM_RTL;
--Figure 8.25b VHDL model for serial to parallel converter (cont
|
mit
|
354fe6bf77bd4a383233eddcb8a71484
| 0.457228 | 4.049924 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodScopeController/tb/DataPathLatency.vhd
| 1 | 5,740 |
-------------------------------------------------------------------------------
--
-- File: DataPathLatency.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 20 May 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module emulates the DataPah.vhd module latency. This operation is
-- necessary to test the calibrated outputs in the tb_TestTop top level test bench
-- of the ZmodScopeController.
-- The FIFO data latency is specified (is it? not sure...) in
-- Xilinx pg057 Table 3-26 (Read Port Flags Update Latency Due to a Write Operation)
-- Latency = 1 wr_clk + (N + 4) rd_clk (+1 rd_clk)
-- The latency is defined in Fig. 3-40 of the same document. A register stage
-- corresponds to 0 cycles of latency. Thus, for a latency of 1 wr_clk, 2 register
-- stages have to be implemented in the write clock domain to emulate the FIFO write
-- latency. An extra cycle needs to be considered for the IDDR primitives in the data
-- path. Thus, a total of 3 register stages are added on the write clock domain to
-- emulate the DataPath module write domain latency.
-- Considering the same definition for the read clock domain latency, N+4+1
-- register stages are added on the read clock domain.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DataPathLatency is
Generic (
-- FIFO number of synchronization stages
kNumFIFO_Stages : integer := 2;
-- Channel data width
kDataWidth : integer := 14
);
Port (
ADC_SamplingClk : in STD_LOGIC;
ZmodDcoClk : in STD_LOGIC;
dDataIn : in STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
cChA_DataOut : out STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
cChB_DataOut : out STD_LOGIC_VECTOR (kDataWidth-1 downto 0)
);
end DataPathLatency;
architecture Behavioral of DataPathLatency is
signal dChA_DataIn, dChB_DataIn, dChB_DataInFalling : STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
type cDlyArray_t is array (kNumFIFO_Stages+4 downto 0) of std_logic_vector(kDataWidth-1 downto 0);
signal cChA_DataDly, cChB_DataDly : cDlyArray_t := (others => (others => '0'));
type dDlyArray_t is array (1 downto 0) of std_logic_vector(kDataWidth-1 downto 0);
signal dChA_DataDly, dChB_DataDly : dDlyArray_t := (others => (others => '0'));
begin
-- Emulate IDDR on ChA (sampled on rising edge)
ProcIDDR_ChA : process (ZmodDcoClk)
begin
if (rising_edge(ZmodDcoClk)) then
dChA_DataIn <= dDataIn;
end if;
end process;
-- Emulate IDDR on ChB (sampled on falling edge)
ProcIDDR_ChB_Falling : process (ZmodDcoClk)
begin
if (falling_edge(ZmodDcoClk)) then
dChB_DataInFalling <= dDataIn;
end if;
end process;
ProcIDDR_ChB_Rising : process (ZmodDcoClk)
begin
if (rising_edge(ZmodDcoClk)) then
dChB_DataIn <= dChB_DataInFalling;
end if;
end process;
-- Emulate write clock domain latency (2 register stages)
ProcDelayDcoClk : process (ZmodDcoClk)
begin
if (rising_edge(ZmodDcoClk)) then
dChA_DataDly(0) <= dChA_DataIn;
dChB_DataDly(0) <= dChB_DataIn;
for Index in 1 to 1 loop
dChA_DataDly (Index) <= dChA_DataDly (Index - 1);
dChB_DataDly (Index) <= dChB_DataDly (Index - 1);
end loop;
end if;
end process;
-- Emulate read clock domain latency (kNumFIFO_Stages + 4 register stages)
ProcDelaySamplingClk : process (ADC_SamplingClk)
begin
if (rising_edge(ADC_SamplingClk)) then
cChA_DataDly(0) <= dChA_DataDly(1);
cChB_DataDly(0) <= dChB_DataDly(1);
for Index in 1 to (kNumFIFO_Stages+4) loop
cChA_DataDly (Index) <= cChA_DataDly (Index - 1);
cChB_DataDly (Index) <= cChB_DataDly (Index - 1);
end loop;
end if;
end process;
cChA_DataOut <= cChA_DataDly (kNumFIFO_Stages+4);
cChB_DataOut <= cChB_DataDly (kNumFIFO_Stages+4);
end Behavioral;
|
mit
|
26f072370ee612e105b655d89c62b189
| 0.682056 | 4.150398 | false | false | false | false |
grafi-tt/Maizul
|
src/DataPath.vhd
| 1 | 17,844 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;
entity DataPath is
port (
clk : in std_logic;
u232c_in : out u232c_in_t;
u232c_out : in u232c_out_t;
sramLoad : out boolean := true;
sramAddr : out sram_addr := (others => '0');
sramData : inout value_t := (others => '0'));
end DataPath;
architecture behavioral of DataPath is
component Fetch is
port (
clk : in std_logic;
d : in fetch_in_t;
q : out fetch_out_t);
end component;
component ALU is
port (
clk : in std_logic;
code : in std_logic_vector(3 downto 0);
tagD : in tag_t;
valA : in value_t;
valB : in value_t;
emitTag : out tag_t;
emitVal : out value_t);
end component;
component FPU is
port (
clk : in std_logic;
code : in std_logic_vector(5 downto 0);
tagD : in tag_t;
valA : in value_t;
valB : in value_t;
tag1 : buffer tag_t;
tag2 : buffer tag_t;
emitTag : out tag_t;
emitVal : out value_t);
end component;
component Branch is
port (
clk : in std_logic;
d : in branch_in_t;
q : out branch_out_t);
end component;
component IO is
port (
clk : in std_logic;
enable : in boolean;
code : in std_logic_vector(2 downto 0);
getTag : in tag_t;
putVal : in value_t;
blocking : out boolean;
emitTag : out tag_t;
emitVal : out value_t;
u232c_in : out u232c_in_t;
u232c_out : in u232c_out_t;
emit_instw : out blkram_write_t);
end component;
type reg_file_t is array(31 downto 0) of value_t;
signal gpr_file : reg_file_t := (others => (others => '0'));
signal fpr_file : reg_file_t := (others => (others => '0'));
attribute RAM_STYLE : string;
attribute RAM_STYLE of gpr_file : signal is "distributed";
attribute RAM_STYLE of fpr_file : signal is "distributed";
signal inst : instruction_t := (others => '0');
signal pc : blkram_addr := (others => '0');
signal d_fet : fetch_in_t;
signal q_fet : fetch_out_t;
signal code_alu : std_logic_vector(3 downto 0) := (others => '0');
signal tag_alu_d : tag_t := (others => '0');
signal emit_tag_alu : tag_t;
signal emit_val_alu : value_t;
signal code_fpu : std_logic_vector(5 downto 0) := (others => '0');
signal tag_fpu_d : tag_t := (others => '0');
signal pipe1_tag_fpu, pipe2_tag_fpu, emit_tag_fpu : tag_t;
signal emit_val_fpu : value_t;
signal val_alu_fpu_a, val_alu_fpu_b : value_t := (others => '0');
signal d_bra : branch_in_t := (
code => "000", -- jmp to addr 0 once
tag_l => (others => '0'),
val_a => (others => '0'),
val_b => (others => '0'),
val_l => (others => '0'),
val_t => (others => '0'));
signal q_bra : branch_out_t;
signal code_io : std_logic_vector(2 downto 0) := "000";
signal enable_io : boolean := false;
signal tag_spc_y : tag_t := (others => '0');
signal val_spc_x : value_t := (others => '0');
signal emit_tag_spc : tag_t;
signal emit_val_spc : value_t;
signal blocking : boolean;
signal jump1 : boolean;
signal jump2 : boolean := false;
signal ignore : boolean;
signal stall : boolean;
signal stall_lat : boolean := false;
signal addr0 : sram_addr := (others => '0');
signal load0, load1, load2, load3 : boolean := true;
signal tagM0, tagM1, tagM2, tagM3, emitTagLoad : tag_t := (others => '0');
signal tagFM0, tagFM1, tagFM2, tagFM3, emitTagFLoad : tag_t := (others => '0');
signal valM0, valM1, valM2, emitValM : value_t := (others => '0');
signal fwdM_1, fwdM_2 : boolean := false;
signal tag_gpr_w_sig : tag_t;
signal val_gpr_w_sig : value_t;
signal tag_fpr_w_sig : tag_t;
signal val_fpr_w_sig : value_t;
begin
-- fetch
fetch_map : Fetch port map (clk => clk, d => d_fet, q => q_fet);
sequential : process(clk)
begin
if rising_edge(clk) then
if ignore or not stall then
inst <= q_fet.inst;
pc <= q_fet.pc;
end if;
gpr_file(to_integer(unsigned(tag_gpr_w_sig))) <= val_gpr_w_sig;
fpr_file(to_integer(unsigned(tag_fpr_w_sig))) <= val_fpr_w_sig;
d_fet.enable_addr <= not (ignore or stall);
jump2 <= jump1;
stall_lat <= stall;
end if;
end process;
combinatorial : process(inst, pc, gpr_file, fpr_file, stall_lat,
emit_tag_alu, emit_val_alu,
pipe1_tag_fpu, pipe2_tag_fpu, emit_tag_fpu, emit_val_fpu,
q_bra, q_fet, jump1, jump2, stall, ignore, blocking,
emit_tag_spc, emit_val_spc,
load1, load2, load3, tagM1, tagM2, tagM3, emitTagLoad, tagFM1, tagFM2, tagFM3, emitTagFLoad, emitValM)
variable tag_gpr_w : tag_t;
variable val_gpr_w : value_t;
variable tag_fpr_w : tag_t;
variable val_fpr_w : value_t;
variable opcode : std_logic_vector(5 downto 0);
variable tag_x, tag_y, tag_z : tag_t;
variable imm : unsigned(15 downto 0);
variable is_alu_imm, is_alu_gpr, is_alu_fpr : boolean;
variable is_fpu_gpr, is_fpu_fpr : boolean;
variable is_mem_gpr_ld, is_mem_gpr_st, is_mem_fpr_ld, is_mem_fpr_st : boolean;
variable is_spc, is_jmp, is_bra_gpr, is_bra_fpr : boolean;
variable val_gpr_x, val_gpr_y, imm_signed, val_gpr_fwd_x, val_gpr_fwd_y : value_t;
variable val_fpr_x, val_fpr_y, val_fpr_fwd_x, val_fpr_fwd_y : value_t;
variable stall_raw_gpr_x, stall_raw_gpr_y, stall_waw_gpr_y, stall_waw_gpr_z : boolean;
variable stall_raw_fpr_x, stall_raw_fpr_y, stall_mst_fpr_y, stall_waw_fpr_z : boolean;
begin
tag_gpr_w := emit_tag_alu or q_bra.emit_tag or emit_tag_spc or emitTagLoad;
if emit_tag_alu /= "00000" then
val_gpr_w := emit_val_alu;
elsif q_bra.emit_tag /= "00000" then
val_gpr_w := value_t(x"0000" & q_bra.emit_link);
elsif emit_tag_spc /= "00000" then
val_gpr_w := emit_val_spc;
elsif emitTagLoad /= "00000" then
val_gpr_w := emitValM;
else
val_gpr_w := (others => '0');
end if;
tag_fpr_w := emit_tag_fpu or emitTagFLoad;
if emit_tag_fpu /= "00000" then
val_fpr_w := emit_val_fpu;
elsif emitTagFLoad /= "00000" then
val_fpr_w := emitValM;
else
val_fpr_w := (others => '0');
end if;
if not stall_lat then
d_fet.addr <= q_bra.emit_target;
end if;
tag_gpr_w_sig <= tag_gpr_w;
tag_fpr_w_sig <= tag_fpr_w;
val_gpr_w_sig <= val_gpr_w;
val_fpr_w_sig <= val_fpr_w;
opcode := inst(31 downto 26);
tag_x := tag_t(inst(25 downto 21));
tag_y := tag_t(inst(20 downto 16));
tag_z := tag_t(inst(15 downto 11));
imm := unsigned(inst(15 downto 0));
is_alu_imm := opcode(5 downto 4) = "00";
is_alu_gpr := opcode = "010000";
is_alu_fpr := opcode = "010001";
is_fpu_gpr := opcode = "011000";
is_fpu_fpr := opcode = "011001";
is_mem_gpr_ld := opcode = "010010";
is_mem_gpr_st := opcode = "010011";
is_mem_fpr_ld := opcode = "011010";
is_mem_fpr_st := opcode = "011011";
is_spc := opcode(5 downto 2) = "0101" and opcode(1 downto 0) = "11";
is_jmp := opcode(5 downto 2) = "0101" and opcode(1 downto 0) /= "11";
is_bra_gpr := opcode(5 downto 4) = "10";
is_bra_fpr := opcode(5 downto 4) = "11";
val_gpr_x := gpr_file(to_integer(unsigned(tag_x)));
val_gpr_y := gpr_file(to_integer(unsigned(tag_y)));
imm_signed := value_t(resize(signed(imm), 32));
if tag_x = tag_gpr_w then
val_gpr_fwd_x := val_gpr_w;
else
val_gpr_fwd_x := val_gpr_x;
end if;
if tag_y = tag_gpr_w then
val_gpr_fwd_y := val_gpr_w;
else
val_gpr_fwd_y := val_gpr_y;
end if;
val_fpr_x := fpr_file(to_integer(unsigned(tag_x)));
val_fpr_y := fpr_file(to_integer(unsigned(tag_y)));
if tag_x = tag_fpr_w then
val_fpr_fwd_x := val_fpr_w;
else
val_fpr_fwd_x := val_fpr_x;
end if;
if tag_y = tag_fpr_w then
val_fpr_fwd_y := val_fpr_w;
else
val_fpr_fwd_y := val_fpr_y;
end if;
stall_raw_gpr_x := tag_x /= "00000" and
not (is_alu_fpr or is_fpu_fpr or is_bra_fpr) and
( (load1 and tag_x = tagM1) or
(load2 and tag_x = tagM2) or
(load3 and tag_x = tagM3));
stall_raw_gpr_y := tag_y /= "00000" and
(is_alu_gpr or is_fpu_gpr or is_bra_gpr) and
( (load1 and tag_y = tagM1) or
(load2 and tag_y = tagM2) or
(load3 and tag_y = tagM3));
stall_waw_gpr_y := tag_y /= "00000" and
(is_alu_imm or is_spc or is_jmp) and
( (load1 and tag_y = tagM1) or
(load2 and tag_y = tagM2) or
(load3 and tagM3 /= "00000"));
stall_waw_gpr_z := tag_z /= "00000" and
is_alu_gpr and
( (load1 and tag_z = tagM1) or
(load2 and tag_z = tagM2) or
(load3 and tagM3 /= "00000"));
stall_raw_fpr_x := tag_x /= "00000" and
(is_alu_fpr or is_fpu_fpr or is_bra_fpr) and
( (tag_x = pipe1_tag_fpu) or
(tag_x = pipe2_tag_fpu) or
(load1 and tag_x = tagFM1) or
(load2 and tag_x = tagFM2) or
(load3 and tag_x = tagFM3));
stall_raw_fpr_y := tag_y /= "00000" and
(is_alu_fpr or is_fpu_fpr or is_bra_fpr) and
( (tag_y = pipe1_tag_fpu) or
(tag_y = pipe2_tag_fpu) or
(load1 and tag_y = tagFM1) or
(load2 and tag_y = tagFM2) or
(load3 and tag_y = tagFM3));
stall_mst_fpr_y := tag_y /= "00000" and
(is_mem_fpr_st) and
( (tag_y = pipe1_tag_fpu) or
(tag_y = pipe2_tag_fpu));
stall_waw_fpr_z := tag_z /= "00000" and
(is_fpu_gpr or is_fpu_fpr) and
( (load1 and tagFM1 /= "00000"));
stall <= stall_raw_gpr_x or stall_raw_gpr_y or stall_waw_gpr_y or stall_waw_gpr_z or
stall_raw_fpr_x or stall_raw_fpr_y or stall_mst_fpr_y or stall_waw_fpr_z or
blocking;
jump1 <= q_fet.jump;
ignore <= jump2 or jump1;
d_fet.enable_fetch <= ignore or not stall;
if is_alu_imm then
code_alu <= opcode(3 downto 0);
else
code_alu <= inst(3 downto 0);
end if;
if ignore or stall then
tag_alu_d <= "00000";
elsif is_alu_imm then
tag_alu_d <= tag_y;
elsif is_alu_gpr or is_alu_fpr then
tag_alu_d <= tag_z;
else
tag_alu_d <= "00000";
end if;
code_fpu <= inst(5 downto 0);
if ignore or stall then
tag_fpu_d <= "00000";
elsif is_fpu_gpr or is_fpu_fpr then
tag_fpu_d <= tag_z;
else
tag_fpu_d <= "00000";
end if;
if is_alu_imm then
val_alu_fpu_a <= val_gpr_fwd_x;
val_alu_fpu_b <= imm_signed;
elsif opcode(0) = '0' then
val_alu_fpu_a <= val_gpr_fwd_x;
val_alu_fpu_b <= val_gpr_fwd_y;
else
val_alu_fpu_a <= val_fpr_fwd_x;
val_alu_fpu_b <= val_fpr_fwd_y;
end if;
if ignore or stall then
d_bra.code <= "000";
d_bra.tag_l <= "00000";
if opcode(4) = '0' then
d_bra.val_a <= '1' & val_gpr_fwd_x(30 downto 0);
d_bra.val_b <= '0' & val_gpr_fwd_y(30 downto 0);
else
d_bra.val_a <= '1' & val_fpr_fwd_x(30 downto 0);
d_bra.val_b <= '0' & val_fpr_fwd_y(30 downto 0);
end if;
d_bra.val_t <= blkram_addr(imm);
else
if is_bra_gpr or is_bra_fpr then
d_bra.code <= opcode(4) & opcode(1 downto 0);
d_bra.tag_l <= "00000";
if opcode(4) = '0' then
d_bra.val_a <= val_gpr_fwd_x;
d_bra.val_b <= val_gpr_fwd_y;
else
d_bra.val_a <= val_fpr_fwd_x;
d_bra.val_b <= val_fpr_fwd_y;
end if;
d_bra.val_t <= blkram_addr(imm);
else
if is_jmp then
d_bra.code <= "010";
d_bra.tag_l <= tag_y;
else
d_bra.code <= "000";
d_bra.tag_l <= "00000";
end if;
if opcode(4) = '0' then
d_bra.val_a <= '1' & val_gpr_fwd_x(30 downto 0);
d_bra.val_b <= '0' & val_gpr_fwd_y(30 downto 0);
else
d_bra.val_a <= '1' & val_fpr_fwd_x(30 downto 0);
d_bra.val_b <= '0' & val_fpr_fwd_y(30 downto 0);
end if;
d_bra.val_t <= blkram_addr(imm or unsigned(val_gpr_fwd_x(15 downto 0)));
end if;
end if;
d_bra.val_l <= pc;
code_io <= inst(2 downto 0);
enable_io <= not (ignore or stall) and is_spc;
tag_spc_y <= tag_y;
val_spc_x <= val_gpr_fwd_x;
if ignore or stall then
load0 <= true;
tagM0 <= "00000";
tagFM0 <= "00000";
else
load0 <= not (is_mem_gpr_st or is_mem_fpr_st);
if is_mem_gpr_st or is_mem_gpr_ld then
tagM0 <= tag_y;
else
tagM0 <= "00000";
end if;
if is_mem_fpr_st or is_mem_fpr_ld then
tagFM0 <= tag_y;
else
tagFM0 <= "00000";
end if;
end if;
if opcode(3) = '0' then
valM0 <= val_gpr_fwd_y;
else
valM0 <= val_fpr_fwd_y;
end if;
addr0 <= sram_addr(unsigned(val_gpr_fwd_x(19 downto 0)) + unsigned(imm_signed(19 downto 0)));
end process;
alu_map : ALU port map (
clk => clk,
code => code_alu,
tagD => tag_alu_d,
valA => val_alu_fpu_a,
valB => val_alu_fpu_b,
emitTag => emit_tag_alu,
emitVal => emit_val_alu);
fpu_map : FPU port map (
clk => clk,
code => code_fpu,
tagD => tag_fpu_d,
valA => val_alu_fpu_a,
valB => val_alu_fpu_b,
tag1 => pipe1_tag_fpu,
tag2 => pipe2_tag_fpu,
emitTag => emit_tag_fpu,
emitVal => emit_val_fpu);
branch_map : Branch port map (clk => clk, d => d_bra, q => q_bra);
io_map : IO port map (
clk => clk,
enable => enable_io,
code => code_io,
getTag => tag_spc_y,
putVal => val_spc_x,
blocking => blocking,
emitTag => emit_tag_spc,
emitVal => emit_val_spc,
u232c_in => u232c_in,
u232c_out => u232c_out,
emit_instw => d_fet.w);
-- TODO: separate sram into another component
do_sram : process(clk)
begin
if rising_edge(clk) then
-- phase 1
load1 <= load0;
tagM1 <= tagM0;
tagFM1 <= tagFM0;
valM1 <= valM0;
sramLoad <= load0;
sramAddr <= addr0;
-- phase 2
load2 <= load1;
tagM2 <= tagM1;
tagFM2 <= tagFM1;
if (tagM1 /= "00000" and tagM1 = emitTagLoad) or (tagFM1 /= "00000" and tagFM1 = emitTagFLoad) then
valM2 <= emitValM;
else
valM2 <= valM1;
end if;
fwdM_2 <= load3 and ((tagM1 /= "00000" and tagM1 = tagM3) or (tagFM1 /= "00000" and tagFM1 = tagFM3));
fwdM_1 <= load2 and ((tagM1 /= "00000" and tagM1 = tagM2) or (tagFM1 /= "00000" and tagFM1 = tagFM2));
-- phase 3
load3 <= load2;
tagM3 <= tagM2;
tagFM3 <= tagFM2;
if load2 then
sramData <= (others => 'Z');
else
if fwdM_1 then
sramData <= sramData;
elsif fwdM_2 then
sramData <= emitValM;
else
sramData <= valM2;
end if;
end if;
-- phase 4
if load3 then
emitTagLoad <= tagM3;
emitTagFLoad <= tagFM3;
else
emitTagLoad <= "00000";
emitTagFLoad <= "00000";
end if;
emitValM <= sramData;
end if;
end process;
end behavioral;
|
bsd-2-clause
|
74aab1eb1442314a83863085d2b3b73c
| 0.468953 | 3.409247 | false | false | false | false |
Digilent/vivado-library
|
ip/usb2device_v1_0/src/Protocol_Engine.vhd
| 2 | 72,147 |
-------------------------------------------------------------------------------
--
-- File: Protocol_Engine.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates all the necessary modules to implement ULPI
-- communication, Speed negotiation , Reset and Suspend. Packet data is
-- sent/received over AXI Stream. Synchronization modules for registers
-- that corss the ULPI Clock domain to AXI clock domain is implemented
-- here
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity Protocol_Engine is
generic (
MAX_NR_ENDP : integer := 1
);
Port (
Axi_Clk : IN std_logic;
Axi_Resetn : IN STD_LOGIC;
Ulpi_Clk : in STD_LOGIC;
u_ResetN : in STD_LOGIC;
--ULPI Bus
Ulpi_Reset : out STD_LOGIC;
u_Ulpi_Data : INOUT std_logic_vector(7 downto 0);
u_Ulpi_Dir : IN std_logic;
u_Ulpi_Nxt : IN std_logic;
u_Ulpi_Stp : OUT std_logic;
led : out STD_LOGIC; --debug purposes
--Transmit FIFO write channel
a_Arb_Endpt_Nr : in std_logic_vector(4 downto 0);
Tx_Fifo_S_Aresetn : IN STD_LOGIC;
a_Tx_Fifo_S_Aclk : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tvalid : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tready : OUT STD_LOGIC;
a_Tx_Fifo_S_Axis_Tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_Tx_Fifo_S_Axis_Tlast : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tkeep : IN std_logic_vector(3 downto 0);
a_Tx_Fifo_S_Axis_Tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
tx_fifo_axis_overflow : OUT STD_LOGIC;
tx_fifo_axis_underflow : OUT STD_LOGIC;
--Receive FIFO write channel
u_Rx_Fifo_s_Aclk : OUT std_logic;
u_Rx_Fifo_s_Axis_Tready : IN std_logic;
u_Rx_Fifo_s_Axis_Tvalid : OUT std_logic;
u_Rx_Fifo_s_Axis_Tdata : OUT std_logic_vector(31 downto 0);
u_Rx_Fifo_s_Axis_Tkeep : OUT std_logic_vector (3 downto 0);
u_Rx_Fifo_s_Axis_Tlast : OUT std_logic;
u_Rx_Fifo_Axis_Overflow : IN std_logic;
u_Rx_Fifo_Axis_Underflow : IN std_logic;
--Command FIFO; used to keep track of received OUT transactions
u_Command_Fifo_Rd_En : IN std_logic;
u_Command_Fifo_Dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
u_Command_Fifo_Empty : OUT std_logic;
u_Command_Fifo_Valid : OUT std_logic;
--control signals to/from DMA_Transfer_Manager
a_In_Packet_Complete_oData : OUT std_logic_vector(31 downto 0); --a bit is set when the corresponding endpoint has completed an IN transaction
a_In_Packet_Complete_Set_En : OUT std_logic; --a_In_Packet_Complete_oData strobe
u_Send_Zero_Length_Packet_Rd : IN STD_LOGIC_VECTOR(31 downto 0); --If a bit is set, the corresponding endpoint needs to send a Zero Length Packet
a_Send_Zero_Length_Packet_Clear_oData : OUT STD_LOGIC_VECTOR(31 downto 0); --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Send_Zero_Length_Packet_Clear_En : OUT STD_LOGIC; --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Send_Zero_Length_Packet_Ack_oData : OUT STD_LOGIC_VECTOR(31 downto 0); --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Send_Zero_Length_Packet_Ack_Set_En : OUT STD_LOGIC; --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Cnt_Bytes_Sent_oData : out std_logic_vector(12 downto 0); --number of bytes sent in response to an IN token
a_Cnt_Bytes_Sent_oValid : OUT std_logic; -- a_Cnt_Bytes_Sent_oData strobe
a_Resend_oData : OUT STD_LOGIC_VECTOR(31 downto 0); --indicates to the upper layers that the endpoint corresponding to set bits need to resend a packet
a_Resend_Wr_En : OUT std_logic; --a_Resend_oData
a_In_Token_Received_oData : OUT std_logic_vector(31 downto 0); -- a bit is set when the corresponding endpoint has received an IN token
a_In_Token_Received_Set_En : OUT std_logic; --a_In_Token_Received_oData strobe
a_Endpt_Nr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --endpoint accessed by the lower layers (ULPI, Packet_Decoder)
u_Endp_Nr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
u_Endp_Nr_Arb : IN STD_LOGIC_VECTOR(4 DOWNTO 0); --endpoint accessed by the DMA_Transfer_Manager
u_Endp_Nr_Arb_Ack : OUT std_logic;
u_Endp_Nr_Arb_Valid : IN std_logic;
--Setup packets are stored in these registers before being copied into the dQH
a_Setup_Buffer_Bytes_3_0_oData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a_Setup_Buffer_Bytes_7_4_oData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Interface to Control_Registers block
u_Endp_Type : in STD_LOGIC_VECTOR(47 downto 0);
u_Endp_Stall : IN STD_LOGIC_VECTOR(23 downto 0);
u_USBADRA : in STD_LOGIC_VECTOR (7 downto 0);
a_FRINDEX_oData : out std_logic_vector(10 downto 0);
a_FRINDEX_Wr_En : out std_logic;
a_PORTSC1_PSPD_oData : out std_logic_vector(1 downto 0);
a_PORTSC1_PSPD_Wr_En : out std_logic;
a_ENDPTNAK_oData : out std_logic_vector(31 downto 0);
a_ENDPTNAK_Wr_En : out std_logic;
a_ENDPTSETUP_RECEIVED_oData : out std_logic_vector(31 downto 0);
a_ENDPTSETUP_RECEIVED_Wr_En : out std_logic;
a_USBSTS_NAKI_oData : out std_logic;
a_USBSTS_NAKI_Wr_En : out std_logic;
a_USBSTS_SLI_oData : out std_logic;
a_USBSTS_SLI_Wr_En : out std_logic;
a_USBSTS_SRI_oData : out std_logic;
a_USBSTS_SRI_Wr_En : out std_logic;
a_USBSTS_URI_oData : out std_logic;
a_USBSTS_URI_Wr_En : out std_logic;
a_USBSTS_PCI_oData : out std_logic;
a_USBSTS_PCI_Wr_En : out std_logic;
u_USBCMD_RS : in std_logic;
state_ind : out STD_LOGIC_VECTOR(5 downto 0);
state_ind_pd : out STD_LOGIC_VECTOR(6 downto 0);
state_ind_hs : out STD_LOGIC_VECTOR(4 downto 0)
);
end Protocol_Engine;
architecture Behavioral of Protocol_Engine is
COMPONENT ULPI
PORT(
Ulpi_Clk : IN std_logic;
reset : IN std_logic;
u_Ulpi_Data : INOUT std_logic_vector(7 downto 0);
u_Ulpi_Dir : IN std_logic;
u_Ulpi_Nxt : IN std_logic;
u_Ulpi_Stp : OUT std_logic;
u_Ulpi_Reset : OUT std_logic;
u_Send_NOOP_CMD : IN std_logic;
u_Send_NOPID_CMD : IN std_logic;
u_Send_PID_CMD : IN std_logic;
u_Send_EXTW_CMD : IN std_logic;
u_Send_REGW_CMD : IN std_logic;
u_Send_EXTR_CMD : IN std_logic;
u_Send_REGR_CMD : IN std_logic;
u_Send_STP_CMD : IN std_logic;
u_Send_Last : IN std_logic;
u_Send_Err : IN std_logic;
u_Tx_Data : IN std_logic_vector(7 downto 0);
u_Tx_Data_En : OUT std_logic;
u_Tx_Pid : IN std_logic_vector(3 downto 0);
u_Tx_Regw_Data : in STD_LOGIC_VECTOR (7 downto 0);
u_Tx_Reg_Addr : in STD_LOGIC_VECTOR (7 downto 0);
u_Tx_Cmd_Done : OUT STD_LOGIC;
u_USB_Mode : IN std_logic;
u_CRC16_En : out STD_LOGIC;
u_Tx_Pid_Phase_Done : out STD_LOGIC;
u_Rx_Data : OUT std_logic_vector(7 downto 0);
u_Rx_Packet_Received : OUT std_logic;
u_Ulpi_Dir_Out : out STD_LOGIC;
u_LineState : OUT std_logic_vector(1 downto 0);
u_Vbus : OUT std_logic_vector(1 downto 0);
u_RxEvent : OUT std_logic_vector(1 downto 0);
u_RxActive : out STD_LOGIC;
u_ID : OUT std_logic;
u_Alt_Int : OUT std_logic;
u_Rx_Cmd_Received : OUT std_logic;
state_ind : out STD_LOGIC_VECTOR(5 downto 0);
u_Rx_Register_Data : OUT std_logic_vector(7 downto 0);
u_Rx_Register_Data_Received : OUT std_logic
);
END COMPONENT;
COMPONENT HS_Negotiation
PORT(
u_Reset : IN std_logic;
Ulpi_Clk : IN std_logic;
u_Remote_Wake : IN std_logic;
u_LineState : IN std_logic_vector(1 downto 0);
u_Vbus : IN std_logic_vector(1 downto 0);
u_Rx_Cmd_Received : IN std_logic;
u_Send_NOPID_CMD : OUT std_logic;
u_Send_EXTW_CMD : OUT std_logic;
u_Send_REGW_CMD : OUT std_logic;
u_Send_EXTR_CMD : OUT std_logic;
u_Send_REGR_CMD : OUT std_logic;
u_Send_STP_CMD : OUT std_logic;
u_Send_Last : OUT std_logic;
u_Tx_Data : OUT std_logic_vector(7 downto 0);
u_Tx_Regw_Data : OUT STD_LOGIC_VECTOR (7 downto 0);
u_Tx_Cmd_Done : IN STD_LOGIC;
u_Tx_Reg_Addr : OUT STD_LOGIC_VECTOR (7 downto 0);
u_USB_Mode : OUT std_logic;
u_Not_Connected : OUT std_logic;
u_Set_Mode_HS : OUT std_logic;
u_Set_Mode_FS : OUT std_logic;
u_Wake : OUT std_logic;
u_USBCMD_RS : in std_logic;
state_ind_hs : out STD_LOGIC_VECTOR(4 downto 0);
u_Negociation_Done : out STD_LOGIC
);
END COMPONENT;
COMPONENT Packet_Decoder
PORT(
Ulpi_Clk : in STD_LOGIC;
reset : in STD_LOGIC;
Axi_Clk : IN std_logic;
Axi_Resetn : IN STD_LOGIC;
a_Arb_Endpt_Nr : in std_logic_vector(4 downto 0);
Tx_Fifo_S_Aresetn : IN STD_LOGIC;
a_Tx_Fifo_S_Aclk : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tvalid : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tready : OUT STD_LOGIC;
a_Tx_Fifo_S_Axis_Tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_Tx_Fifo_S_Axis_Tlast : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tkeep : IN std_logic_vector(3 downto 0);
a_Tx_Fifo_S_Axis_Tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
tx_fifo_axis_overflow : OUT STD_LOGIC;
tx_fifo_axis_underflow : OUT STD_LOGIC;
--RX FIFO (write)
u_Rx_Fifo_s_Aclk : OUT std_logic;
u_Rx_Fifo_s_Axis_Tready : IN std_logic;
u_Rx_Fifo_s_Axis_Tvalid : OUT std_logic;
u_Rx_Fifo_s_Axis_Tdata : OUT std_logic_vector(31 downto 0);
u_Rx_Fifo_s_Axis_Tkeep : OUT std_logic_vector (3 downto 0);
u_Rx_Fifo_s_Axis_Tlast : OUT std_logic;
u_Rx_Fifo_Axis_Overflow : IN std_logic;
u_Rx_Fifo_Axis_Underflow : IN std_logic;
u_Command_Fifo_Rd_En : IN std_logic;
u_Command_Fifo_Dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
u_Command_Fifo_Empty : OUT std_logic;
u_Command_Fifo_Valid : OUT std_logic;
u_Setup_Buffer_Bytes_3_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
u_Setup_Buffer_Bytes_7_4 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
u_Send_PID_CMD : out STD_LOGIC;
u_Send_Last : out STD_LOGIC;
u_Tx_Data : out STD_LOGIC_VECTOR (7 downto 0);
u_Tx_Data_En : in STD_LOGIC;
u_Tx_Pid : out STD_LOGIC_VECTOR (3 downto 0);
u_Tx_Cmd_Done : in STD_LOGIC;
u_Tx_Pid_Phase_Done : in STD_LOGIC;
u_CRC16_En_Ulpi : in STD_LOGIC;
u_RxEvent : in STD_LOGIC_VECTOR(1 downto 0);
u_RxActive : in STD_LOGIC;
u_Rx_Packet_Received : in STD_LOGIC;
u_Ulpi_Dir_Out : in STD_LOGIC;
u_Rx_Data : in STD_LOGIC_VECTOR(7 downto 0);
u_USB_Mode : in STD_LOGIC;
u_Setup_Received : OUT std_logic;
u_Setup_Received_Rst : IN std_logic;
u_In_Token_Received : OUT std_logic;
u_In_Packet_Complete : OUT std_logic;
u_In_Packet_Complete_Rst : IN std_logic;
u_iPush_Endpt_Nr_PD : OUT STD_LOGIC;
-- endp_enable : IN STD_LOGIC(11 downto 0);
u_Send_Zero_Length_Packet : in STD_LOGIC;
u_Send_Zero_Length_Packet_Ack_Set : OUT STD_LOGIC;
u_Send_Zero_Length_Packet_Clear : OUT STD_LOGIC;
u_NAK_Sent : out STD_LOGIC;
u_Frame_Index : out STD_LOGIC_VECTOR (10 downto 0);
u_SOF_received : out STD_LOGIC;
u_Cnt_Bytes_Sent : out std_logic_vector(12 downto 0);
u_Cnt_Bytes_Sent_Latch : out STD_LOGIC;
u_Resend_Set : out STD_LOGIC;
u_Endp_Nr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
u_Endp_Stall : IN STD_LOGIC;
u_Endp_Type : in STD_LOGIC_VECTOR(1 downto 0);
u_USBADRA : in STD_LOGIC_VECTOR (7 downto 0);
axis_32_to_8_latency_comp_out_port : out STD_LOGIC;
ulpi_latency_comp_out : in STD_LOGIC;
state_ind_pd : out STD_LOGIC_VECTOR(6 downto 0);
packet_err : out STD_LOGIC
);
END COMPONENT;
COMPONENT SyncBase
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
PORT(
aReset : IN std_logic;
InClk : IN std_logic;
iIn : IN std_logic;
OutClk : IN std_logic;
oOut : OUT std_logic
);
END COMPONENT;
type state_type is (IDLE, SEND_ZERO_LENGTH_STATE, RESET_SETUP_RECEIVED);
signal state, next_state : state_type;
type PACKET_IN_BYTE_COUNT is array (11 downto 0) of std_logic_vector(12 downto 0);
signal u_Cnt_Bytes_Sent_Array : PACKET_IN_BYTE_COUNT;
signal reset : STD_LOGIC;
signal not_reset : STD_LOGIC;
signal not_axi_resetn : STD_LOGIC;
signal u_Send_NOPID_CMD : STD_LOGIC;
signal u_Send_PID_CMD : STD_LOGIC;
signal u_Send_EXTW_CMD : STD_LOGIC;
signal u_Send_REGW_CMD : STD_LOGIC;
signal u_Send_EXTR_CMD : STD_LOGIC;
signal u_Send_REGR_CMD : STD_LOGIC;
signal u_Send_STP_CMD : STD_LOGIC;
signal u_Send_Last : STD_LOGIC;
signal u_Send_Last_HSNegociation : STD_LOGIC;
signal u_Send_Last_PD : STD_LOGIC;
signal u_Tx_Pid : STD_LOGIC_VECTOR(3 downto 0);
signal u_Tx_Data : STD_LOGIC_VECTOR(7 downto 0);
signal u_Tx_Regw_Data : STD_LOGIC_VECTOR(7 downto 0);
signal u_Tx_Cmd_Done : STD_LOGIC;
signal u_Tx_Reg_Addr : STD_LOGIC_VECTOR(7 downto 0);
signal u_Tx_Data_HSNegociation : STD_LOGIC_VECTOR(7 downto 0);
signal u_Tx_Data_PD : STD_LOGIC_VECTOR(7 downto 0);
signal u_Tx_Data_En : STD_LOGIC;
signal u_Tx_Pid_Phase_Done : STD_LOGIC;
signal u_CRC16_En : STD_LOGIC;
signal u_Rx_Data : STD_LOGIC_VECTOR(7 downto 0);
signal u_Rx_Cmd_Received : STD_LOGIC;
signal u_RxEvent : STD_LOGIC_VECTOR(1 downto 0);
signal u_RxActive : STD_LOGIC;
signal u_Rx_Register_Data : STD_LOGIC_VECTOR(7 downto 0);
signal u_Rx_Register_Data_Received : STD_LOGIC;
signal u_Rx_Packet_Received : STD_LOGIC;
signal u_LineState : STD_LOGIC_VECTOR(1 downto 0);
signal u_Vbus : STD_LOGIC_VECTOR(1 downto 0);
signal u_Ulpi_Dir_Out : STD_LOGIC;
signal u_ID : STD_LOGIC;
signal u_Alt_Int : STD_LOGIC;
signal u_Negociation_Done : STD_LOGIC;
signal u_USB_Mode : STD_LOGIC;
signal packet_err : STD_LOGIC;
type u_Cnt_Bytes_Sent_iData_Array is array (MAX_NR_ENDP downto 0) of std_logic_vector(12 downto 0);
signal u_Cnt_Bytes_Sent_iData : u_Cnt_Bytes_Sent_iData_Array;
type a_Cnt_Bytes_Sent_oData_Array is array (MAX_NR_ENDP downto 0) of std_logic_vector(12 downto 0);
signal a_Cnt_Bytes_Sent_oData_Loc : a_Cnt_Bytes_Sent_oData_Array;
type u_Cnt_Bytes_Sent_iPush_Array is array (MAX_NR_ENDP downto 0) of std_logic;
signal u_Cnt_Bytes_Sent_iPush : u_Cnt_Bytes_Sent_iPush_Array;
type u_Cnt_Bytes_Sent_iRdy_Array is array (MAX_NR_ENDP downto 0) of std_logic;
signal u_Cnt_Bytes_Sent_iRdy : u_Cnt_Bytes_Sent_iRdy_Array;
type a_Cnt_Bytes_Sent_oValid_Array is array (MAX_NR_ENDP downto 0) of std_logic;
signal a_Cnt_Bytes_Sent_oValid_Loc : a_Cnt_Bytes_Sent_oValid_Array;
signal u_Cnt_Bytes_Sent : STD_LOGIC_VECTOR(12 downto 0);
signal u_Cnt_Bytes_Sent_Latch, u_Cnt_Bytes_Sent_Latch_q : STD_LOGIC;
signal u_ENDPTNAK_iData : std_logic_vector(31 downto 0);
signal a_ENDPTNAK_oValid : STD_LOGIC;
signal a_ENDPTNAK_Wr_En_q : STD_LOGIC;
signal u_ENDPTNAK_iPush : STD_LOGIC;
signal u_ENDPTNAK_iRdy : STD_LOGIC;
signal u_ENDPTSETUPSTAT_iData : std_logic_vector(31 downto 0);
signal a_ENDPTSETUPSTAT_Wr_En_q : std_logic;
signal u_ENDPTSETUPSTAT_iPush : STD_LOGIC;
signal u_ENDPTSETUPSTAT_iRdy : STD_LOGIC;
signal a_ENDPTSETUPSTAT_oValid : STD_LOGIC;
signal u_Setup_Received : STD_LOGIC;
signal u_Setup_Received_Rst : STD_LOGIC;
signal a_ENDPTSETUP_RECEIVED_Wr_En_qq, a_ENDPTSETUP_RECEIVED_Wr_En_q, a_ENDPTSETUP_RECEIVED_Wr_En_Loc : STD_LOGIC;
signal ENDPTSETUPSTAT_Hanshake_Rst, a_ENDPTSETUPSTAT_Hanshake_Rst : STD_LOGIC;
signal u_In_Packet_Complete_iData : std_logic_vector (31 downto 0);
signal u_In_Packet_Complete_iPush : std_logic;
signal u_In_Packet_Complete_iRdy : std_logic;
signal a_In_Packet_Complete_Set_En_q, a_In_Packet_Complete_Set_En_qq : std_logic;
signal a_Packet_In_Complete_Hanshake_Rst, Packet_In_Complete_Hanshake_Rst : std_logic;
signal a_In_Packet_Complete_Set_En_Loc : std_logic;
signal a_In_Packet_Complete_Wr_En_q : std_logic;
signal a_In_Packet_In_Complete_oValid : STD_LOGIC;
signal u_In_Packet_Complete : STD_LOGIC;
signal u_In_Packet_Complete_Rst : STD_LOGIC;
signal u_FRINDEX_iData : std_logic_vector(10 downto 0);
signal a_FRINDEX_Wr_En_q : std_logic;
signal a_FRINDEX_oValid : STD_LOGIC;
signal u_FRINDEX_iPush : STD_LOGIC;
signal u_FRINDEX_iRdy : STD_LOGIC;
signal u_SOF_Received : STD_LOGIC;
signal u_Frame_Index : STD_LOGIC_VECTOR(10 downto 0);
signal u_In_Token_Received : std_logic;
signal u_In_Token_Received_iData : std_logic_vector(31 downto 0);
signal a_In_Token_Received_Set_En_q, a_In_Token_Received_Set_En_qq, a_In_Token_Received_Set_En_Loc : STD_LOGIC;
signal u_In_Token_Received_iPush : STD_LOGIC;
signal u_In_Token_Received_iRdy : STD_LOGIC;
signal a_In_Token_Received_oValid : STD_LOGIC;
signal a_In_Token_Received_Hanshake_Rst, In_Token_Received_Hanshake_Rst : STD_LOGIC;
signal u_Send_Zero_Length_Packet_Clear_iData : std_logic_vector(31 downto 0);
signal u_Send_Zero_Length_Packet_Clear : std_logic;
signal u_Send_Zero_Length_Packet_Clear_iPush : std_logic;
signal u_Send_Zero_Length_Packet_Clear_iRdy : std_logic;
signal a_Send_Zero_Length_Packet_Clear_oValid : std_logic;
signal a_Send_Zero_Length_Packet_Clear_En_q, a_Send_Zero_Length_Packet_Clear_En_qq : std_logic;
signal a_Send_Zero_Length_Packet_Clear_En_Loc : std_logic;
signal Send_Zero_Length_Packet_Clear_Hanshake_Rst, a_Send_Zero_Length_Packet_Clear_Hanshake_Rst : std_logic;
signal u_Send_Zero_Length_Packet_Ack_iData, u_Send_Zero_Length_Packet_Ack_iData_q : std_logic_vector(31 downto 0);
signal u_Send_Zero_Length_Packet_Ack_iRdy : std_logic;
signal u_Send_Zero_Length_Packet_Ack_Set : STD_LOGIC;
signal u_Send_Zero_Length_Packet_Ack_iPush : std_logic;
signal a_Send_Zero_Length_Packet_Ack_oValid : STD_LOGIC;
signal a_Send_Zero_Length_Packet_Ack_Set_En_q, a_Send_Zero_Length_Packet_Ack_Set_En_qq : std_logic;
signal u_Send_Zero_Length_Packet : STD_LOGIC;
signal a_Send_Zero_Length_Packet_Ack_Set_En_Loc : std_logic;
signal a_Send_Zero_Length_Packet_Ack_Set_Hanshake_Rst, Send_Zero_Length_Packet_Ack_Set_Hanshake_Rst : std_logic;
signal u_Setup_Buffer_Bytes_3_0_iData : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal u_Setup_Buffer_Bytes_3_0_q : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal u_Setup_Buffer_Bytes_3_0_iPush : STD_LOGIC;
signal u_Setup_Buffer_Bytes_3_0_iRdy : STD_LOGIC;
signal a_Setup_Buffer_Bytes_3_0_oValid : STD_LOGIC;
signal u_Setup_Buffer_Bytes_7_4_iData : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal u_Setup_Buffer_Bytes_7_4_q : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal u_Setup_Buffer_Bytes_7_4_iPush : STD_LOGIC;
signal u_Setup_Buffer_Bytes_7_4_iRdy : STD_LOGIC;
signal a_Setup_Buffer_Bytes_7_4_oValid : STD_LOGIC;
signal u_NAK_Sent : STD_LOGIC;
signal u_USBSTS_NAKI_iData : std_logic_vector(0 downto 0);
signal a_USBSTS_NAKI_Wr_En_q : std_logic;
signal u_USBSTS_NAKI_iPush : std_logic;
signal u_USBSTS_NAKI_iRdy : std_logic;
signal a_USBSTS_NAKI_oValid : std_logic;
signal a_USBSTS_NAKI_Vector : STD_LOGIC_VECTOR(0 downto 0);
signal u_USBSTS_SLI_iData : std_logic_vector(0 downto 0);
signal u_USBSTS_SLI_iPush : std_logic;
signal u_USBSTS_SLI_iRdy : std_logic;
signal a_USBSTS_SLI_oValid : std_logic;
signal a_USBSTS_SLI_Vector : STD_LOGIC_VECTOR(0 downto 0);
signal a_USBSTS_SLI_Wr_En_q : std_logic;
signal u_Suspend_State, u_Suspend_State_q, u_Set_Suspend_State : STD_LOGIC;
signal u_Clear_Suspend_State, u_Set_Clear_Suspend_State, u_Set_Clear_Suspend_State_q : STD_LOGIC;
signal u_USBSTS_SRI_iData : std_logic_vector(0 downto 0);
signal u_USBSTS_SRI_iPush : std_logic;
signal u_USBSTS_SRI_iRdy : std_logic;
signal a_USBSTS_SRI_oValid : std_logic;
signal a_USBSTS_SRI_Vector : STD_LOGIC_VECTOR(0 downto 0);
signal a_USBSTS_SRI_Wr_En_q : std_logic;
signal u_USBSTS_URI_iData : std_logic_vector(0 downto 0);
signal u_USBSTS_URI_iPush : std_logic;
signal u_USBSTS_URI_iRdy : std_logic;
signal a_USBSTS_URI_oValid : std_logic;
signal a_USBSTS_URI_Vector : STD_LOGIC_VECTOR(0 downto 0);
signal a_USBSTS_URI_Wr_En_q : std_logic;
signal u_Reset_Received_Ulpi_q, u_Reset_Received, u_Reset_Received_Ulpi : STD_LOGIC;
signal u_USBSTS_PCI_iData : std_logic_vector(0 downto 0);
signal u_USBSTS_PCI_iPush : STD_LOGIC;
signal u_USBSTS_PCI_iRdy: STD_LOGIC;
signal a_USBSTS_PCI_oValid: STD_LOGIC;
signal a_USBSTS_PCI_Vector : STD_LOGIC_VECTOR(0 downto 0);
signal a_USBSTS_PCI_Wr_En_q : std_logic;
signal u_Port_Change_Detect : STD_LOGIC;
signal u_Wake : STD_LOGIC;
signal u_Set_Mode_FS : STD_LOGIC;
signal u_Set_Mode_HS : STD_LOGIC;
signal u_PORTSC1_iData : std_logic_vector(1 downto 0);
signal u_PORTSC1_iPush : STD_LOGIC;
signal u_PORTSC1_iRdy : STD_LOGIC;
signal a_PORTSC1_oValid : STD_LOGIC;
signal a_PORTSC1_PSPD_Wr_En_q : STD_LOGIC;
signal u_Not_Connected : STD_LOGIC;
signal u_Not_Connected_Pulse : STD_LOGIC;
signal u_Not_Connected_q : STD_LOGIC;
signal u_Resend_Set : STD_LOGIC;
signal u_Resend_iData : std_logic_vector (31 downto 0);
signal u_Resend_iPush : std_logic;
signal u_Resend_iRdy : std_logic;
signal a_Resend_Wr_En_q : std_logic;
signal a_Resend_oValid : STD_LOGIC;
signal u_Endpt_Nr_Loc : STD_LOGIC_VECTOR(4 downto 0);
signal u_iPush_Endpt_Nr, u_iPush_Endpt_Nr_PD, u_Endpt_Nr_oValid, u_Endpt_Nr_iRdy : STD_LOGIC;
signal pe_endpt_nr_int_4msb : integer range 0 to 12;
signal pe_endpt_nr_int : integer range 0 to 21;
signal pe_endpt_nr_index : integer range 0 to 27;
signal arb_endpt_nr_int_4msb : integer range 0 to 22;
signal a_Arb_Endpt_Nr_Int_4msb : integer range 0 to 22;
signal u_Arb_Endpt_Nr_Loc, a_Arb_Endpt_Nr_Loc: STD_LOGIC_VECTOR(4 downto 0);
signal u_Endp_Stall_PD : STD_LOGIC;
signal u_Endp_Type_PD : STD_LOGIC_VECTOR(1 downto 0);
signal state_ind_hs_loc : STD_LOGIC_VECTOR(4 downto 0);
signal ulpi_latency_comp_in, ulpi_latency_comp_out : STD_LOGIC;
-- attribute mark_debug : string;
-- attribute keep : string;
-- attribute mark_debug of u_Send_Zero_Length_Packet_Ack_iPush : signal is "true";
-- attribute keep of u_Send_Zero_Length_Packet_Ack_iPush : signal is "true";
--attribute mark_debug of u_In_Packet_Complete_iData : signal is "true";
--attribute keep of u_In_Packet_Complete_iData : signal is "true";
--attribute mark_debug of u_In_Packet_Complete_iPush : signal is "true";
--attribute keep of u_In_Packet_Complete_iPush : signal is "true";
--attribute mark_debug of u_In_Packet_Complete_iRdy : signal is "true";
--attribute keep of u_In_Packet_Complete_iRdy : signal is "true";
--attribute mark_debug of a_In_Packet_Complete_oData : signal is "true";
--attribute keep of a_In_Packet_Complete_oData : signal is "true";
--attribute mark_debug of a_In_Packet_Complete_Set_En : signal is "true";
--attribute keep of a_In_Packet_Complete_Set_En : signal is "true";
--attribute mark_debug of u_ENDPTSETUPSTAT_iData : signal is "true";
--attribute keep of u_ENDPTSETUPSTAT_iData : signal is "true";
--attribute mark_debug of a_ENDPTSETUP_RECEIVED_oData : signal is "true";
--attribute keep of a_ENDPTSETUP_RECEIVED_oData : signal is "true";
--attribute mark_debug of u_ENDPTSETUPSTAT_iPush : signal is "true";
--attribute keep of u_ENDPTSETUPSTAT_iPush : signal is "true";
--attribute mark_debug of ENDPTSETUPSTAT_Hanshake_Rst : signal is "true";
--attribute keep of ENDPTSETUPSTAT_Hanshake_Rst : signal is "true";
--attribute mark_debug of u_In_Token_Received_iData : signal is "true";
--attribute keep of u_In_Token_Received_iData : signal is "true";
--attribute mark_debug of u_In_Token_Received_iPush : signal is "true";
--attribute keep of u_In_Token_Received_iPush : signal is "true";
--attribute mark_debug of a_In_Token_Received_oValid : signal is "true";
--attribute keep of a_In_Token_Received_oValid : signal is "true";
--attribute mark_debug of a_In_Token_Received_oData : signal is "true";
--attribute keep of a_In_Token_Received_oData : signal is "true";
--attribute mark_debug of In_Token_Received_Hanshake_Rst : signal is "true";
--attribute keep of In_Token_Received_Hanshake_Rst : signal is "true";
--attribute mark_debug of u_Cnt_Bytes_Sent_iPush : signal is "true";
--attribute keep of u_Cnt_Bytes_Sent_iPush : signal is "true";
--attribute mark_debug of a_Cnt_Bytes_Sent_oData_Loc : signal is "true";
--attribute keep of a_Cnt_Bytes_Sent_oData_Loc : signal is "true";
begin
u_Endp_Nr <= u_Endpt_Nr_Loc;
not_reset <= not (reset);
reset <= u_ResetN;
not_axi_resetn <= not (axi_resetn);
u_Arb_Endpt_Nr_Loc <= u_Endp_Nr_Arb;
a_Arb_Endpt_Nr_Loc <= a_Arb_Endpt_Nr;
state_ind_hs <= state_ind_hs_loc;
led <= '1';
--Transmit data MUX. During speed negotiation HS_Negotiation controls the ULPI bus.
--Once negotiation is done, the Packet_Decoder controls the ULPI bus
u_Tx_Data <= u_Tx_Data_PD when u_Negociation_Done = '1'
else u_Tx_Data_HSNegociation;--reg_data;--
u_Send_Last <= u_Send_Last_PD when u_Negociation_Done = '1'
else u_Send_Last_HSNegociation;
-- This module handles ULPI transmissions (NOPID, PID, EXTW, REGW, EXTR, REGR)
-- and reception
Inst_ULPI: ULPI PORT MAP(
u_Ulpi_Data => u_Ulpi_Data,
Ulpi_Clk => Ulpi_Clk,
reset => reset,
u_Ulpi_Dir => u_Ulpi_Dir,
u_Ulpi_Nxt => u_Ulpi_Nxt,
u_Ulpi_Stp => u_Ulpi_Stp,
u_Ulpi_Reset => Ulpi_Reset,
u_Send_NOOP_CMD => '0',
u_Send_NOPID_CMD => u_Send_NOPID_CMD,
u_Send_PID_CMD => u_Send_PID_CMD,
u_Send_EXTW_CMD => u_Send_EXTW_CMD,
u_Send_REGW_CMD => u_Send_REGW_CMD,
u_Send_EXTR_CMD => u_Send_EXTR_CMD,
u_Send_REGR_CMD => u_Send_REGR_CMD,
u_Send_STP_CMD => u_Send_STP_CMD,
u_Send_Last => u_Send_Last,
u_Send_Err => '0',
u_Tx_Data => u_Tx_Data,
u_Tx_Data_En => u_Tx_Data_En,
u_Tx_Pid => u_Tx_Pid,
u_Tx_Regw_Data => u_Tx_Regw_Data,
u_Tx_Reg_Addr => u_Tx_Reg_Addr,
u_Tx_Cmd_Done => u_Tx_Cmd_Done,
u_CRC16_En => u_CRC16_En,
u_Tx_Pid_Phase_Done => u_Tx_Pid_Phase_Done,
u_Rx_Data => u_Rx_Data,
u_Rx_Packet_Received => u_Rx_Packet_Received,
u_Ulpi_Dir_Out => u_Ulpi_Dir_Out,
u_LineState => u_LineState,
u_Vbus => u_Vbus,
u_RxEvent => u_RxEvent,
u_RxActive => u_RxActive,
u_ID => u_ID,
u_Alt_Int => u_Alt_Int,
u_Rx_Cmd_Received => u_Rx_Cmd_Received,
state_ind => state_ind,
u_Rx_Register_Data => u_Rx_Register_Data,
u_Rx_Register_Data_Received => u_Rx_Register_Data_Received,
u_USB_Mode => u_USB_Mode
);
-- This module handles the USB speed negociatian, reset and suspend protocols
Inst_HS_Negotiation: HS_Negotiation PORT MAP(
u_Reset => reset,
Ulpi_Clk => Ulpi_Clk,
u_Send_NOPID_CMD => u_Send_NOPID_CMD,
u_Send_EXTW_CMD => u_Send_EXTW_CMD,
u_Send_REGW_CMD => u_Send_REGW_CMD,
u_Send_EXTR_CMD => u_Send_EXTR_CMD,
u_Send_REGR_CMD => u_Send_REGR_CMD,
u_Send_STP_CMD => u_Send_STP_CMD,
u_Send_Last => u_Send_Last_HSNegociation,
u_Remote_Wake => '0',
u_Rx_Cmd_Received => u_Rx_Cmd_Received,
u_LineState => u_LineState,
u_Vbus => u_Vbus,
u_Tx_Data => u_Tx_Data_HSNegociation,
u_Tx_Regw_Data => u_Tx_Regw_Data,
u_Tx_Cmd_Done => u_Tx_Cmd_Done,
u_Tx_Reg_Addr => u_Tx_Reg_Addr,
u_USB_Mode => u_USB_Mode,
u_Not_Connected => u_Not_Connected,
u_Set_Mode_HS => u_Set_Mode_HS,
u_Set_Mode_FS => u_Set_Mode_FS,
u_Wake => u_Wake,
u_USBCMD_RS => u_USBCMD_RS,
state_ind_hs => state_ind_hs_loc,
u_Negociation_Done => u_Negociation_Done
);
u_Endp_Stall_PD <= u_Endp_Stall(pe_endpt_nr_int);
u_Endp_Type_PD <= u_Endp_Type((pe_endpt_nr_int*2) + 1 downto pe_endpt_nr_int*2);
u_Send_Zero_Length_Packet <= u_Send_Zero_Length_Packet_Rd(pe_endpt_nr_index);
-- This module implements chapter 8 of the USB protocol
Inst_Packet_Decoder: Packet_Decoder PORT MAP(
Ulpi_Clk => Ulpi_Clk,
Axi_Clk => Axi_Clk,
reset => reset,
Axi_Resetn => Axi_Resetn,
a_Arb_Endpt_Nr => a_Arb_Endpt_Nr,
Tx_Fifo_S_Aresetn => Tx_Fifo_S_Aresetn,
a_Tx_Fifo_S_Aclk => a_Tx_Fifo_S_Aclk,
a_Tx_Fifo_S_Axis_Tvalid => a_Tx_Fifo_S_Axis_Tvalid,
a_Tx_Fifo_S_Axis_Tready => a_Tx_Fifo_S_Axis_Tready,
a_Tx_Fifo_S_Axis_Tdata => a_Tx_Fifo_S_Axis_Tdata,
a_Tx_Fifo_S_Axis_Tlast => a_Tx_Fifo_S_Axis_Tlast,
a_Tx_Fifo_S_Axis_Tkeep => a_Tx_Fifo_S_Axis_Tkeep,
a_Tx_Fifo_S_Axis_Tuser => a_Tx_Fifo_S_Axis_Tuser,
tx_fifo_axis_overflow => tx_fifo_axis_overflow,
tx_fifo_axis_underflow => tx_fifo_axis_underflow,
u_Rx_Fifo_s_Aclk => u_Rx_Fifo_s_Aclk,
u_Rx_Fifo_s_Axis_Tready => u_Rx_Fifo_s_Axis_Tready,
u_Rx_Fifo_s_Axis_Tvalid => u_Rx_Fifo_s_Axis_Tvalid,
u_Rx_Fifo_s_Axis_Tdata => u_Rx_Fifo_s_Axis_Tdata,
u_Rx_Fifo_s_Axis_Tkeep => u_Rx_Fifo_s_Axis_Tkeep,
u_Rx_Fifo_s_Axis_Tlast => u_Rx_Fifo_s_Axis_Tlast,
u_Rx_Fifo_Axis_Overflow => u_Rx_Fifo_Axis_Overflow,
u_Rx_Fifo_Axis_Underflow => u_Rx_Fifo_Axis_Underflow,
u_Command_Fifo_Rd_En => u_Command_Fifo_Rd_En,
u_Command_Fifo_Dout => u_Command_Fifo_Dout,
u_Command_Fifo_Empty => u_Command_Fifo_Empty,
u_Command_Fifo_Valid => u_Command_Fifo_Valid,
u_Setup_Buffer_Bytes_3_0 => u_Setup_Buffer_Bytes_3_0_iData,
u_Setup_Buffer_Bytes_7_4 => u_Setup_Buffer_Bytes_7_4_iData,
u_Send_PID_CMD => u_Send_PID_CMD,
u_Send_Last => u_Send_Last_PD,
u_Tx_Data => u_Tx_Data_PD,
u_Tx_Data_En => u_Tx_Data_En,
u_Tx_Pid => u_Tx_Pid,
u_Tx_Cmd_Done => u_Tx_Cmd_Done,
u_Tx_Pid_Phase_Done => u_Tx_Pid_Phase_Done,
u_CRC16_En_Ulpi => u_CRC16_En,
u_Rx_Data => u_Rx_Data,
u_Rx_Packet_Received => u_Rx_Packet_Received,
u_Ulpi_Dir_Out => u_Ulpi_Dir_Out,
u_RxEvent => u_RxEvent,
u_RxActive => u_RxActive,
u_USB_Mode => u_USB_Mode,
u_Setup_Received => u_Setup_Received,
u_Setup_Received_Rst => u_Setup_Received_Rst,
u_In_Token_Received => u_In_Token_Received,
u_In_Packet_Complete => u_In_Packet_Complete,
u_In_Packet_Complete_Rst => u_In_Packet_Complete_Rst,
u_Cnt_Bytes_Sent_Latch => u_Cnt_Bytes_Sent_Latch,
u_Cnt_Bytes_Sent => u_Cnt_Bytes_Sent,
u_Resend_Set => u_Resend_Set,
u_Endp_Nr => u_Endpt_Nr_Loc,
u_iPush_Endpt_Nr_PD => u_iPush_Endpt_Nr_PD,
u_Send_Zero_Length_Packet_Clear => u_Send_Zero_Length_Packet_Clear,
u_Send_Zero_Length_Packet => u_Send_Zero_Length_Packet,
u_Send_Zero_Length_Packet_Ack_Set => u_Send_Zero_Length_Packet_Ack_Set,
u_NAK_Sent => u_NAK_Sent,
u_Frame_Index => u_Frame_Index,
u_SOF_Received => u_SOF_Received,
u_USBADRA => u_USBADRA,
u_Endp_Type => u_Endp_Type_PD,
u_Endp_Stall => u_Endp_Stall_PD,
ulpi_latency_comp_out => ulpi_latency_comp_out,
state_ind_pd => state_ind_pd,
packet_err =>packet_err
);
--Synchronization modules for data that crosses the ULPI clock domain to AXI clock domain
u_iPush_Endpt_Nr <= u_iPush_Endpt_Nr_PD when (u_Endpt_Nr_iRdy = '1') else '0';
Inst_HandshakeData_pe_endpt_nr: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 5)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_Endpt_Nr_Loc,
oData => a_Endpt_Nr ,
iPush => u_iPush_Endpt_Nr,
iRdy => u_Endpt_Nr_iRdy,
oAck => u_Endpt_Nr_oValid,
oValid => u_Endpt_Nr_oValid,
aReset => not_axi_resetn
);
--------------------------------------------------------------------------------------------
pe_endpt_nr_int_4msb <= to_integer(unsigned(u_Endpt_Nr_Loc(4 downto 1)));
pe_endpt_nr_int <= to_integer(unsigned(u_Endpt_Nr_Loc));
arb_endpt_nr_int_4msb <= to_integer(unsigned(u_Arb_Endpt_Nr_Loc(4 downto 1)));
a_Arb_Endpt_Nr_Int_4msb <= to_integer(unsigned(a_Arb_Endpt_Nr_Loc(4 downto 1)));
DEFINE_INDEX_PROC: process (reset, u_Endpt_Nr_Loc, pe_endpt_nr_int_4msb)
begin
if (reset = '0') then
pe_endpt_nr_index <= 0;
else
if (u_Endpt_Nr_Loc(0) = '0') then
pe_endpt_nr_index <= pe_endpt_nr_int_4msb;
else
pe_endpt_nr_index <= pe_endpt_nr_int_4msb + 16;
end if;
end if;
end process;
MULTIPLE_HANDSHAKE : for i in 0 to MAX_NR_ENDP generate
Inst_HandshakeData_Count: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 13)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_Cnt_Bytes_Sent_iData(i),
oData => a_Cnt_Bytes_Sent_oData_Loc(i),
iPush => u_Cnt_Bytes_Sent_iPush(i),
iRdy => u_Cnt_Bytes_Sent_iRdy(i),
oAck => a_Cnt_Bytes_Sent_oValid_Loc(i),
oValid => a_Cnt_Bytes_Sent_oValid_Loc(i),
aReset => not_axi_resetn
);
end generate;
IN_PACKET_COUNTER_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Cnt_Bytes_Sent_iData <= (others => (others => '0'));
else
if (u_Cnt_Bytes_Sent_Latch = '1') then
u_Cnt_Bytes_Sent_iData(pe_endpt_nr_int_4msb) <= u_Cnt_Bytes_Sent;
end if;
end if;
end if;
end process;
IPUSH_COUNTER_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Cnt_Bytes_Sent_iPush <= (others => '0');
u_Cnt_Bytes_Sent_Latch_q <= '0';
else
u_Cnt_Bytes_Sent_Latch_q <= u_Cnt_Bytes_Sent_Latch;
if ((u_Cnt_Bytes_Sent_Latch_q = '1') and (u_Cnt_Bytes_Sent_iRdy(pe_endpt_nr_int_4msb) = '1'))then
u_Cnt_Bytes_Sent_iPush(pe_endpt_nr_int_4msb) <= '1';
else
u_Cnt_Bytes_Sent_iPush(pe_endpt_nr_int_4msb) <= '0';
end if;
end if;
end if;
end process;
IN_TRANSF_CNT_OVALID_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_Cnt_Bytes_Sent_oValid <= '0';
else
a_Cnt_Bytes_Sent_oValid <= a_Cnt_Bytes_Sent_oValid_Loc(a_Arb_Endpt_Nr_Int_4msb);
end if;
end if;
end process;
IN_TRANSF_CNT_ODATA_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_Cnt_Bytes_Sent_oData <= (others => '0');
else
if (a_Cnt_Bytes_Sent_oValid_Loc(a_Arb_Endpt_Nr_Int_4msb) = '1') then
a_Cnt_Bytes_Sent_oData <= a_Cnt_Bytes_Sent_oData_Loc(a_Arb_Endpt_Nr_Int_4msb);
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------------
NAK_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_ENDPTNAK_iData <= (others => '0');
u_ENDPTNAK_iPush <= '0';
else
if (u_NAK_Sent = '1' and u_ENDPTNAK_iRdy = '1') then
u_ENDPTNAK_iData(pe_endpt_nr_index) <= '1';
u_ENDPTNAK_iPush <= '1';
else
u_ENDPTNAK_iData <= (others => '0');
u_ENDPTNAK_iPush <= '0';
end if;
end if;
end if;
end process;
ENDPTNAK_wr_en_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_ENDPTNAK_Wr_En <= '0';
a_ENDPTNAK_Wr_En_q <= '0';
else
a_ENDPTNAK_Wr_En_q <= a_ENDPTNAK_oValid;
a_ENDPTNAK_Wr_En <= a_ENDPTNAK_oValid and (not a_ENDPTNAK_Wr_En_q);
end if;
end if;
end process;
Inst_HandshakeData_ENDPTNAK : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_ENDPTNAK_iData,
oData => a_ENDPTNAK_oData,
iPush => u_ENDPTNAK_iPush,
iRdy => u_ENDPTNAK_iRdy,
oAck => a_ENDPTNAK_oValid,
oValid => a_ENDPTNAK_oValid,
aReset => not_axi_resetn
);
-----------------------------------------------------------------------------------------------
ENDPTSETUPSTAT_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Setup_Received_Rst <= '0';
u_ENDPTSETUPSTAT_iData <= (others => '0');
u_ENDPTSETUPSTAT_iPush <= '0';
else
if (u_Setup_Received = '1' and u_ENDPTSETUPSTAT_iRdy = '1') then
u_ENDPTSETUPSTAT_iData(pe_endpt_nr_index) <= '1';
u_ENDPTSETUPSTAT_iPush <= '1';
u_Setup_Received_Rst <= '0';
else
u_ENDPTSETUPSTAT_iData <= (others => '0');
u_Setup_Received_Rst <= '1';
u_ENDPTSETUPSTAT_iPush <= '0';
end if;
end if;
end if;
end process;
ENDPTSETUPSTAT_wr_en_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_ENDPTSETUP_RECEIVED_Wr_En_Loc <= '0';
a_ENDPTSETUPSTAT_Wr_En_q <= '0';
a_ENDPTSETUP_RECEIVED_Wr_En_qq <= '0';
a_ENDPTSETUPSTAT_Hanshake_Rst <= '0';
a_ENDPTSETUP_RECEIVED_Wr_En_q <= '0';
else
a_ENDPTSETUPSTAT_Wr_En_q <= a_ENDPTSETUPSTAT_oValid;
a_ENDPTSETUP_RECEIVED_Wr_En_Loc <= a_ENDPTSETUPSTAT_oValid and (not a_ENDPTSETUPSTAT_Wr_En_q);
a_ENDPTSETUP_RECEIVED_Wr_En_q <= a_ENDPTSETUP_RECEIVED_Wr_En_Loc;
a_ENDPTSETUP_RECEIVED_Wr_En_qq <= a_ENDPTSETUP_RECEIVED_Wr_En_q;
a_ENDPTSETUPSTAT_Hanshake_Rst <= a_ENDPTSETUP_RECEIVED_Wr_En_qq;
end if;
end if;
end process;
ENDPTSETUPSTAT_Hanshake_Rst <= a_ENDPTSETUPSTAT_Hanshake_Rst or not_axi_resetn;
a_ENDPTSETUP_RECEIVED_Wr_En <= a_ENDPTSETUP_RECEIVED_Wr_En_Loc;
Inst_HandshakeData_ENDPTSETUPSTAT : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_ENDPTSETUPSTAT_iData,
oData => a_ENDPTSETUP_RECEIVED_oData,
iPush => u_ENDPTSETUPSTAT_iPush,
iRdy => u_ENDPTSETUPSTAT_iRdy,
oAck => a_ENDPTSETUPSTAT_oValid,
oValid => a_ENDPTSETUPSTAT_oValid,
aReset => ENDPTSETUPSTAT_Hanshake_Rst
);
------------------------------------------------------------------------------------------------
PACKET_IN_COMPLETE_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_In_Packet_Complete_iData <= (others => '0');
u_In_Packet_Complete_iPush <= '0';
u_In_Packet_Complete_Rst <= '0';
else
if (u_In_Packet_Complete = '1' and u_In_Packet_Complete_iRdy = '1') then
u_In_Packet_Complete_iData(pe_endpt_nr_index) <= '1';
u_In_Packet_Complete_iPush <= '1';
u_In_Packet_Complete_Rst <= '0';
else
u_In_Packet_Complete_iData <= (others => '0');
u_In_Packet_Complete_Rst <= '1';
u_In_Packet_Complete_iPush <= '0';
end if;
end if;
end if;
end process;
packet_in_complete_wr_en_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_In_Packet_Complete_Set_En_Loc <= '0';
a_In_Packet_Complete_Wr_En_q <= '0';
a_In_Packet_Complete_Set_En_q <= '0';
a_In_Packet_Complete_Set_En_qq <= '0';
a_Packet_In_Complete_Hanshake_Rst <= '0';
else
a_In_Packet_Complete_Wr_En_q <= a_In_Packet_In_Complete_oValid;
a_In_Packet_Complete_Set_En_Loc <= a_In_Packet_In_Complete_oValid and (not a_In_Packet_Complete_Wr_En_q);
a_In_Packet_Complete_Set_En_q <= a_In_Packet_Complete_Set_En_Loc;
a_In_Packet_Complete_Set_En_qq <= a_In_Packet_Complete_Set_En_q;
a_Packet_In_Complete_Hanshake_Rst <= a_In_Packet_Complete_Set_En_qq;
end if;
end if;
end process;
a_In_Packet_Complete_Set_En <= a_In_Packet_Complete_Set_En_Loc;
Packet_In_Complete_Hanshake_Rst <= a_Packet_In_Complete_Hanshake_Rst or not_axi_resetn;
Inst_HandshakeData_packet_in_complete : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_In_Packet_Complete_iData,
oData => a_In_Packet_Complete_oData,
iPush => (u_In_Packet_Complete_iPush and u_In_Packet_Complete_iRdy),
iRdy => u_In_Packet_Complete_iRdy,
oAck => a_In_Packet_In_Complete_oValid,
oValid => a_In_Packet_In_Complete_oValid,
aReset => Packet_In_Complete_Hanshake_Rst
);
-----------------------------------------------------------------------------------------------------
FRINDEX_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_FRINDEX_iData <= (others => '0');
u_FRINDEX_iPush <= '0';
else
if (u_SOF_Received = '1' and u_FRINDEX_iRdy = '1') then
u_FRINDEX_iData(10 downto 0) <= u_Frame_Index;
u_FRINDEX_iPush <= '1';
else
u_FRINDEX_iPush <= '0';
end if;
end if;
end if;
end process;
FRINDEX_wr_en_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_FRINDEX_Wr_En <= '0';
a_FRINDEX_Wr_En_q <= '0';
else
a_FRINDEX_Wr_En_q <= a_FRINDEX_oValid;
a_FRINDEX_Wr_En <= a_FRINDEX_oValid and (not a_FRINDEX_Wr_En_q);
end if;
end if;
end process;
Inst_HandshakeData_FRINDEX : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 11)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_FRINDEX_iData,
oData => a_FRINDEX_oData,
iPush => u_FRINDEX_iPush,
iRdy => u_FRINDEX_iRdy,
oAck => a_FRINDEX_oValid,
oValid => a_FRINDEX_oValid,
aReset => not_axi_resetn
);
---------------------------------------------------------------------------------------------------------
IN_TOKEN_RECEIVED_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_In_Token_Received_iData <= (others => '0');
u_In_Token_Received_iPush <= '0';
else
u_In_Token_Received_iPush <= u_In_Token_Received and u_In_Token_Received_iRdy;
if (u_In_Token_Received = '1') then
u_In_Token_Received_iData(pe_endpt_nr_index) <= '1';
else
u_In_Token_Received_iData <= (others => '0');
end if;
end if;
end if;
end process;
in_token_received_set_en_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_In_Token_Received_Set_En_Loc <= '0';
a_In_Token_Received_Set_En_qq <= '0';
a_In_Token_Received_Set_En_q <= '0';
a_In_Token_Received_Hanshake_Rst <= '0';
else
a_In_Token_Received_Set_En_q <= a_In_Token_Received_oValid;
a_In_Token_Received_Set_En_Loc <= a_In_Token_Received_oValid and (not a_In_Token_Received_Set_En_q);
a_In_Token_Received_Set_En_qq <= a_In_Token_Received_Set_En_Loc;
a_In_Token_Received_Hanshake_Rst <= a_In_Token_Received_Set_En_qq;
end if;
end if;
end process;
a_In_Token_Received_Set_En <= a_In_Token_Received_Set_En_Loc;
In_Token_Received_Hanshake_Rst <= a_In_Token_Received_Hanshake_Rst or not_axi_resetn;
Inst_HandshakeData_in_token_received : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_In_Token_Received_iData,
oData => a_In_Token_Received_oData,
iPush => u_In_Token_Received_iPush,
iRdy => u_In_Token_Received_iRdy,
oAck => a_In_Token_Received_oValid,
oValid => a_In_Token_Received_oValid,
aReset => In_Token_Received_Hanshake_Rst
);
-----------------------------------------------------------------------------------------------------------
SEND_ZERO_LENGTH_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Send_Zero_Length_Packet_Clear_iData <= (others => '1');
u_Send_Zero_Length_Packet_Clear_iPush <= '0';
else
if (u_Send_Zero_Length_Packet_Clear = '1') then
u_Send_Zero_Length_Packet_Clear_iData(pe_endpt_nr_index) <= '0';
u_Send_Zero_Length_Packet_Clear_iPush <= '1';
else
u_Send_Zero_Length_Packet_Clear_iData <= (others => '1');
u_Send_Zero_Length_Packet_Clear_iPush <= '0';
end if;
end if;
end if;
end process;
send_zero_length_packet_clear_en_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_Send_Zero_Length_Packet_Clear_En_Loc <= '0';
a_Send_Zero_Length_Packet_Clear_En_qq <= '0';
a_Send_Zero_Length_Packet_Clear_En_q <= '0';
a_Send_Zero_Length_Packet_Clear_Hanshake_Rst <= '0';
else
a_Send_Zero_Length_Packet_Clear_En_q <= a_In_Token_Received_oValid;
a_Send_Zero_Length_Packet_Clear_En_Loc <= a_Send_Zero_Length_Packet_Clear_oValid and (not a_Send_Zero_Length_Packet_Clear_En_q);
a_Send_Zero_Length_Packet_Clear_En_qq <= a_Send_Zero_Length_Packet_Clear_En_Loc;
a_Send_Zero_Length_Packet_Clear_Hanshake_Rst <= a_Send_Zero_Length_Packet_Clear_Hanshake_Rst;
end if;
end if;
end process;
a_Send_Zero_Length_Packet_Clear_En <= a_Send_Zero_Length_Packet_Clear_En_Loc;
Send_Zero_Length_Packet_Clear_Hanshake_Rst <= a_Send_Zero_Length_Packet_Clear_Hanshake_Rst or not_axi_resetn;
Inst_HandshakeData_zero_length_clear: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_Send_Zero_Length_Packet_Clear_iData,
oData => a_Send_Zero_Length_Packet_Clear_oData ,
iPush => (u_Send_Zero_Length_Packet_Clear_iPush and u_Send_Zero_Length_Packet_Clear_iRdy),
iRdy => u_Send_Zero_Length_Packet_Clear_iRdy,
oAck => a_Send_Zero_Length_Packet_Clear_oValid,
oValid => a_Send_Zero_Length_Packet_Clear_oValid,
aReset => Send_Zero_Length_Packet_Clear_Hanshake_Rst
);
-------------------------------------------------------------------------------------------------------------
SEND_ZERO_LENGTH_ACK_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Send_Zero_Length_Packet_Ack_iData <= (others => '0');
else
if (u_Send_Zero_Length_Packet_Ack_Set = '1') then
u_Send_Zero_Length_Packet_Ack_iData(pe_endpt_nr_index) <= '1';
else
u_Send_Zero_Length_Packet_Ack_iData <= (others => '0');
end if;
end if;
end if;
end process;
IPUSH_SEND_ZERO_LENGTH_ACK_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Send_Zero_Length_Packet_Ack_iPush <= '0';
u_Send_Zero_Length_Packet_Ack_iData_q <= (others => '0');
else
u_Send_Zero_Length_Packet_Ack_iData_q <= u_Send_Zero_Length_Packet_Ack_iData;
if (u_Send_Zero_Length_Packet_Ack_iData /= u_Send_Zero_Length_Packet_Ack_iData_q and u_Send_Zero_Length_Packet_Ack_iRdy = '1') then
u_Send_Zero_Length_Packet_Ack_iPush <= '1';
else
u_Send_Zero_Length_Packet_Ack_iPush <= '0';
end if;
end if;
end if;
end process;
Send_Zero_Length_Packet_Ack_Set_En_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_Send_Zero_Length_Packet_Ack_Set_En_Loc <= '0';
a_Send_Zero_Length_Packet_Ack_Set_En_qq <= '0';
a_Send_Zero_Length_Packet_Ack_Set_En_q <= '0';
a_Send_Zero_Length_Packet_Ack_Set_Hanshake_Rst <= '0';
else
a_Send_Zero_Length_Packet_Ack_Set_En_q <= a_Send_Zero_Length_Packet_Ack_oValid;
a_Send_Zero_Length_Packet_Ack_Set_En_Loc <= a_Send_Zero_Length_Packet_Ack_oValid and (not a_Send_Zero_Length_Packet_Ack_Set_En_q);
a_Send_Zero_Length_Packet_Ack_Set_En_qq <= a_Send_Zero_Length_Packet_Ack_Set_En_Loc;
a_Send_Zero_Length_Packet_Ack_Set_Hanshake_Rst <= a_Send_Zero_Length_Packet_Ack_Set_En_qq;
end if;
end if;
end process;
a_Send_Zero_Length_Packet_Ack_Set_En <= a_Send_Zero_Length_Packet_Ack_Set_En_Loc;
Send_Zero_Length_Packet_Ack_Set_Hanshake_Rst <= a_Send_Zero_Length_Packet_Ack_Set_Hanshake_Rst or not_axi_resetn;
Inst_HandshakeData_zero_length_ack: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_Send_Zero_Length_Packet_Ack_iData,
oData => a_Send_Zero_Length_Packet_Ack_oData ,
iPush => u_Send_Zero_Length_Packet_Ack_iPush,
iRdy => u_Send_Zero_Length_Packet_Ack_iRdy,
oAck => a_Send_Zero_Length_Packet_Ack_oValid,
oValid => a_Send_Zero_Length_Packet_Ack_oValid,
aReset => Send_Zero_Length_Packet_Ack_Set_Hanshake_Rst
);
----------------------------------------------------------------------------------------------------------------
IPUSH_pe_SETUP_BUFFER_BYTES_3_0_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Setup_Buffer_Bytes_3_0_iPush <= '0';
u_Setup_Buffer_Bytes_3_0_q <= (others => '0');
else
u_Setup_Buffer_Bytes_3_0_q <= u_Setup_Buffer_Bytes_3_0_iData;
if (u_Setup_Buffer_Bytes_3_0_iData /= u_Setup_Buffer_Bytes_3_0_q and u_Setup_Buffer_Bytes_3_0_iRdy = '1') then
u_Setup_Buffer_Bytes_3_0_iPush <= '1';
else
u_Setup_Buffer_Bytes_3_0_iPush <= '0';
end if;
end if;
end if;
end process;
Inst_HandshakeData_SETUP_BUFFER_BYTES_3_0 : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_Setup_Buffer_Bytes_3_0_iData,
oData => a_Setup_Buffer_Bytes_3_0_oData,
iPush => u_Setup_Buffer_Bytes_3_0_iPush,
iRdy => u_Setup_Buffer_Bytes_3_0_iRdy,
oAck => a_Setup_Buffer_Bytes_3_0_oValid,
oValid => a_Setup_Buffer_Bytes_3_0_oValid,
aReset => not_axi_resetn
);
----------------------------------------------------------------------------------------------------------------
IPUSH_pe_SETUP_BUFFER_BYTES_7_4_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Setup_Buffer_Bytes_7_4_iPush <= '0';
u_Setup_Buffer_Bytes_7_4_q <= (others => '0');
else
u_Setup_Buffer_Bytes_7_4_q <= u_Setup_Buffer_Bytes_7_4_iData;
if (u_Setup_Buffer_Bytes_7_4_iData /= u_Setup_Buffer_Bytes_7_4_q and u_Setup_Buffer_Bytes_7_4_iRdy = '1') then
u_Setup_Buffer_Bytes_7_4_iPush <= '1';
else
u_Setup_Buffer_Bytes_7_4_iPush <= '0';
end if;
end if;
end if;
end process;
Inst_HandshakeData_pe_SETUP_BUFFER_BYTES_7_4 : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_Setup_Buffer_Bytes_7_4_iData,
oData => a_Setup_Buffer_Bytes_7_4_oData,
iPush => u_Setup_Buffer_Bytes_7_4_iPush,
iRdy => u_Setup_Buffer_Bytes_7_4_iRdy,
oAck => a_Setup_Buffer_Bytes_7_4_oValid,
oValid => a_Setup_Buffer_Bytes_7_4_oValid,
aReset => not_axi_resetn
);
----------------------------------------------------------------------------------------------------------------
USBSTS_NAKI_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_USBSTS_NAKI_iData <= "0";
u_USBSTS_NAKI_iPush <= '0';
else
if (u_NAK_Sent = '1' and u_USBSTS_NAKI_iRdy = '1') then
u_USBSTS_NAKI_iData <= "1";
u_USBSTS_NAKI_iPush <= '1';
else
u_USBSTS_NAKI_iPush <= '0';
end if;
end if;
end if;
end process;
USBSTS_wr_en_NAK_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_USBSTS_NAKI_Wr_En <= '0';
a_USBSTS_NAKI_Wr_En_q <= '0';
else
a_USBSTS_NAKI_Wr_En_q <= a_USBSTS_NAKI_oValid;
a_USBSTS_NAKI_Wr_En <= a_USBSTS_NAKI_oValid and (not a_USBSTS_NAKI_Wr_En_q);
end if;
end if;
end process;
Inst_HandshakeData_NAKI : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 1)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_USBSTS_NAKI_iData,
oData => a_USBSTS_NAKI_Vector,
iPush => u_USBSTS_NAKI_iPush,
iRdy => u_USBSTS_NAKI_iRdy,
oAck => a_USBSTS_NAKI_oValid,
oValid => a_USBSTS_NAKI_oValid,
aReset => not_axi_resetn
);
a_USBSTS_NAKI_oData <= a_USBSTS_NAKI_Vector(0);
----------------------------------------------------------------------------------------------------------------
SET_CLEAR_SUSPEND_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Set_Suspend_State <= '0';
u_Set_Clear_Suspend_State <= '0';
u_Reset_Received_Ulpi <= '0';
else
if (state_ind_hs_loc = "10010") then
u_Set_Suspend_State <= '1';
u_Set_Clear_Suspend_State <= '0';
u_Reset_Received_Ulpi <= '0';
else
u_Set_Suspend_State <= '0';
u_Set_Clear_Suspend_State <= '1';
if(state_ind_hs_loc = "01000") then
u_Reset_Received_Ulpi <= '1';
else
u_Reset_Received_Ulpi <= '0';
end if;
end if;
end if;
end if;
end process;
SET_SUSPEND_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Suspend_State <= '0';
u_Suspend_State_q <= '0';
else
u_Suspend_State_q <= u_Set_Suspend_State;
u_Suspend_State <= u_Set_Suspend_State and (not u_Suspend_State_q);
end if;
end if;
end process;
CLEAR_SUSPEND_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Clear_Suspend_State <= '0';
u_Set_Clear_Suspend_State_q <= '0';
else
u_Set_Clear_Suspend_State_q <= u_Set_Clear_Suspend_State;
u_Clear_Suspend_State <= u_Set_Clear_Suspend_State and (not u_Set_Clear_Suspend_State_q);
end if;
end if;
end process;
USBSTS_SLI_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_USBSTS_SLI_iData <= "0";
u_USBSTS_SLI_iPush <= '0';
else
if (u_Suspend_State = '1' and u_USBSTS_SLI_iRdy = '1') then
u_USBSTS_SLI_iData <= "1";
u_USBSTS_SLI_iPush <= '1';
elsif (u_Clear_Suspend_State = '1' and u_USBSTS_SLI_iRdy = '1') then
u_USBSTS_SLI_iData <= "1";
u_USBSTS_SLI_iPush <= '1';
else
u_USBSTS_SLI_iPush <= '0';
end if;
end if;
end if;
end process;
USBSTS_wr_en_SLI_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_USBSTS_SLI_Wr_En <= '0';
a_USBSTS_SLI_Wr_En_q <= '0';
else
a_USBSTS_SLI_Wr_En_q <= a_USBSTS_SLI_oValid;
a_USBSTS_SLI_Wr_En <= a_USBSTS_SLI_oValid and (not a_USBSTS_SLI_Wr_En_q);
end if;
end if;
end process;
Inst_HandshakeData_SLI: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 1)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_USBSTS_SLI_iData,
oData => a_USBSTS_SLI_Vector,
iPush => u_USBSTS_SLI_iPush,
iRdy => u_USBSTS_SLI_iRdy,
oAck => a_USBSTS_SLI_oValid,
oValid => a_USBSTS_SLI_oValid,
aReset => not_axi_resetn
);
a_USBSTS_SLI_oData <= a_USBSTS_SLI_Vector(0);
------------------------------------------------------------------------------------------------------------------------------------
USBSTS_SRI_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_USBSTS_SRI_iData <= "0";
u_USBSTS_SRI_iPush <= '0';
else
if (u_SOF_Received = '1' and u_USBSTS_SRI_iRdy = '1') then
u_USBSTS_SRI_iData <= "1";
u_USBSTS_SRI_iPush <= '1';
else
u_USBSTS_SRI_iPush <= '0';
end if;
end if;
end if;
end process;
USBSTS_wr_en_SRI_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_USBSTS_SRI_Wr_En <= '0';
a_USBSTS_SRI_Wr_En_q <= '0';
else
a_USBSTS_SRI_Wr_En_q <= a_USBSTS_SRI_oValid;
a_USBSTS_SRI_Wr_En <= a_USBSTS_SRI_oValid and (not a_USBSTS_SRI_Wr_En_q);
end if;
end if;
end process;
Inst_HandshakeData_SRI: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 1)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_USBSTS_SRI_iData,
oData => a_USBSTS_SRI_Vector,
iPush => u_USBSTS_SRI_iPush,
iRdy => u_USBSTS_SRI_iRdy,
oAck => a_USBSTS_SRI_oValid,
oValid => a_USBSTS_SRI_oValid,
aReset => not_axi_resetn
);
a_USBSTS_SRI_oData <= a_USBSTS_SRI_Vector(0);
--------------------------------------------------------------------------------------------------------------------------------------
USBSTS_URI_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_USBSTS_URI_iData <= "0";
u_USBSTS_URI_iPush <= '0';
else
if (u_Reset_Received = '1' and u_USBSTS_URI_iRdy = '1') then
u_USBSTS_URI_iData <= "1";
u_USBSTS_URI_iPush <= '1';
else
u_USBSTS_URI_iPush <= '0';
end if;
end if;
end if;
end process;
RESET_RECEIVED_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Reset_Received <= '0';
u_Reset_Received_Ulpi_q <= '0';
else
u_Reset_Received_Ulpi_q <= u_Reset_Received_Ulpi;
u_Reset_Received <= u_Reset_Received_Ulpi and (not u_Reset_Received_Ulpi_q);
end if;
end if;
end process;
USBSTS_wr_en_URI_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_USBSTS_URI_Wr_En <= '0';
a_USBSTS_URI_Wr_En_q <= '0';
else
a_USBSTS_URI_Wr_En_q <= a_USBSTS_URI_oValid;
a_USBSTS_URI_Wr_En <= a_USBSTS_URI_oValid and (not a_USBSTS_URI_Wr_En_q);
end if;
end if;
end process;
Inst_HandshakeData_URI: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 1)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_USBSTS_URI_iData,
oData => a_USBSTS_URI_Vector,
iPush => u_USBSTS_URI_iPush,
iRdy => u_USBSTS_URI_iRdy,
oAck => a_USBSTS_URI_oValid,
oValid => a_USBSTS_URI_oValid,
aReset => not_axi_resetn
);
a_USBSTS_URI_oData <= a_USBSTS_URI_Vector(0);
--------------------------------------------------------------------------------------------------------------------------------------
u_Port_Change_Detect <= u_Wake or u_Set_Mode_HS or u_Set_Mode_FS;
USBSTS_PCI_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_USBSTS_PCI_iData <= "0";
u_USBSTS_PCI_iPush <= '0';
else
if (u_Port_Change_Detect = '1' and u_USBSTS_PCI_iRdy = '1') then --resume signaling or port enters high speed or full speed mode
u_USBSTS_PCI_iData <= "1";
u_USBSTS_PCI_iPush <= '1';
else
u_USBSTS_PCI_iPush <= '0';
end if;
end if;
end if;
end process;
USBSTS_wr_en_PCI_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_USBSTS_PCI_Wr_En <= '0';
a_USBSTS_PCI_Wr_En_q <= '0';
else
a_USBSTS_PCI_Wr_En_q <= a_USBSTS_PCI_oValid;
a_USBSTS_PCI_Wr_En <= a_USBSTS_PCI_oValid and (not a_USBSTS_PCI_Wr_En_q);
end if;
end if;
end process;
Inst_HandshakeData_PCI : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 1)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_USBSTS_PCI_iData,
oData => a_USBSTS_PCI_Vector,
iPush => u_USBSTS_PCI_iPush,
iRdy => u_USBSTS_PCI_iRdy,
oAck => a_USBSTS_PCI_oValid,
oValid => a_USBSTS_PCI_oValid,
aReset => not_axi_resetn
);
a_USBSTS_PCI_oData <= a_USBSTS_PCI_Vector(0);
------------------------------------------------------------------------------------------------------------------------------------------
URESEND_IDATA_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Resend_iData <= (others => '0');
u_Resend_iPush <= '0';
else
if (u_Resend_Set = '1' and u_Resend_iRdy = '1') then --resume signaling or port enters high speed or full speed mode
u_Resend_iData(pe_endpt_nr_index) <= '1';
u_Resend_iPush <= '1';
else
u_Resend_iPush <= '0';
u_Resend_iData <= (others => '0');
end if;
end if;
end if;
end process;
RESEND_WR_EN_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_Resend_Wr_En <= '0';
a_Resend_Wr_En_q <= '0';
else
a_Resend_Wr_En_q <= a_Resend_oValid;
a_Resend_Wr_En <= a_Resend_oValid and (not a_Resend_Wr_En_q);
end if;
end if;
end process;
Inst_HandshakeData_Resend : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_Resend_iData,
oData => a_Resend_oData,
iPush => u_Resend_iPush,
iRdy => u_Resend_iRdy,
oAck => a_Resend_oValid,
oValid => a_Resend_oValid,
aReset => not_axi_resetn
);
------------------------------------------------------------------------------------------------------------------------------------------
PORTSC1_PSPD_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_PORTSC1_iData <= "00";
u_PORTSC1_iPush <= '0';
else
if (u_Not_Connected = '1') then
if (u_Not_Connected_Pulse = '1' and u_PORTSC1_iRdy = '1') then
u_PORTSC1_iData <= "11";
u_PORTSC1_iPush <= '1';
end if;
else
if (u_Set_Mode_HS = '1' and u_PORTSC1_iRdy = '1') then
u_PORTSC1_iData <= "10";
u_PORTSC1_iPush <= '1';
elsif (u_Set_Mode_FS = '0' and u_Not_Connected = '0' and u_PORTSC1_iRdy = '1')then
u_PORTSC1_iData <= "01";
u_PORTSC1_iPush <= '1';
else
u_PORTSC1_iPush <= '0';
end if;
end if;
end if;
end if;
end process;
PORTSC1_PSPD_wr_en_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_PORTSC1_PSPD_Wr_En <= '0';
a_PORTSC1_PSPD_Wr_En_q <= '0';
else
a_PORTSC1_PSPD_Wr_En_q <= a_PORTSC1_oValid;
a_PORTSC1_PSPD_Wr_En <= a_PORTSC1_oValid and (not a_PORTSC1_PSPD_Wr_En_q);
end if;
end if;
end process;
Inst_HandshakeData_PORTSC1: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 2)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_PORTSC1_iData,
oData => a_PORTSC1_PSPD_oData,
iPush => u_PORTSC1_iPush,
iRdy => u_PORTSC1_iRdy,
oAck => a_PORTSC1_oValid,
oValid => a_PORTSC1_oValid,
aReset => not_axi_resetn
);
NOT_CONNECTED_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Not_Connected_Pulse <= '0';
u_Not_Connected_q <= '0';
else
u_Not_Connected_q <= u_Not_Connected;
u_Not_Connected_Pulse <= u_Not_Connected and (not u_Not_Connected_q);
end if;
end if;
end process;
end Behavioral;
|
mit
|
f67a3cdd91d3c6ef20d49356e79cd017
| 0.555061 | 3.348355 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_gamma_correction_1_0/hdl/vhdl/AXIvideo2Mat.vhd
| 1 | 61,654 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity AXIvideo2Mat is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
stream_in_TDATA : IN STD_LOGIC_VECTOR (23 downto 0);
stream_in_TVALID : IN STD_LOGIC;
stream_in_TREADY : OUT STD_LOGIC;
stream_in_TKEEP : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TSTRB : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TID : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
img_rows_V_read : IN STD_LOGIC_VECTOR (15 downto 0);
img_cols_V_read : IN STD_LOGIC_VECTOR (15 downto 0);
img_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_full_n : IN STD_LOGIC;
img_data_stream_0_V_write : OUT STD_LOGIC;
img_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_full_n : IN STD_LOGIC;
img_data_stream_1_V_write : OUT STD_LOGIC;
img_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_full_n : IN STD_LOGIC;
img_data_stream_2_V_write : OUT STD_LOGIC );
end;
architecture behav of AXIvideo2Mat is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (7 downto 0) := "00001000";
constant ap_ST_fsm_pp1_stage0 : STD_LOGIC_VECTOR (7 downto 0) := "00010000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (7 downto 0) := "00100000";
constant ap_ST_fsm_pp2_stage0 : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal AXI_video_strm_V_data_V_0_data_out : STD_LOGIC_VECTOR (23 downto 0);
signal AXI_video_strm_V_data_V_0_vld_in : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_vld_out : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_ack_in : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_ack_out : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_payload_A : STD_LOGIC_VECTOR (23 downto 0);
signal AXI_video_strm_V_data_V_0_payload_B : STD_LOGIC_VECTOR (23 downto 0);
signal AXI_video_strm_V_data_V_0_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_data_V_0_sel_wr : STD_LOGIC := '0';
signal AXI_video_strm_V_data_V_0_sel : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_load_A : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_load_B : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal AXI_video_strm_V_data_V_0_state_cmp_full : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_data_out : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_user_V_0_vld_in : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_vld_out : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_ack_in : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_ack_out : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_payload_A : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_user_V_0_payload_B : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_user_V_0_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_user_V_0_sel_wr : STD_LOGIC := '0';
signal AXI_video_strm_V_user_V_0_sel : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_load_A : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_load_B : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal AXI_video_strm_V_user_V_0_state_cmp_full : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_data_out : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_last_V_0_vld_in : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_vld_out : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_ack_in : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_ack_out : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_payload_A : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_last_V_0_payload_B : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_last_V_0_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_last_V_0_sel_wr : STD_LOGIC := '0';
signal AXI_video_strm_V_last_V_0_sel : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_load_A : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_load_B : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal AXI_video_strm_V_last_V_0_state_cmp_full : STD_LOGIC;
signal AXI_video_strm_V_dest_V_0_vld_in : STD_LOGIC;
signal AXI_video_strm_V_dest_V_0_ack_out : STD_LOGIC;
signal AXI_video_strm_V_dest_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal stream_in_TDATA_blk_n : STD_LOGIC;
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal ap_CS_fsm_pp1_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp1_stage0 : signal is "none";
signal ap_enable_reg_pp1_iter1 : STD_LOGIC := '0';
signal ap_block_pp1_stage0 : BOOLEAN;
signal exitcond_reg_420 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_reg_429 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp2_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp2_stage0 : signal is "none";
signal ap_enable_reg_pp2_iter1 : STD_LOGIC := '0';
signal ap_block_pp2_stage0 : BOOLEAN;
signal eol_2_reg_248 : STD_LOGIC_VECTOR (0 downto 0);
signal img_data_stream_0_V_blk_n : STD_LOGIC;
signal img_data_stream_1_V_blk_n : STD_LOGIC;
signal img_data_stream_2_V_blk_n : STD_LOGIC;
signal t_V_2_reg_178 : STD_LOGIC_VECTOR (10 downto 0);
signal eol_reg_189 : STD_LOGIC_VECTOR (0 downto 0);
signal eol_1_reg_201 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_data_V_1_reg_212 : STD_LOGIC_VECTOR (23 downto 0);
signal axi_last_V_3_reg_259 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_data_V_3_reg_271 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_13_fu_293_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_13_reg_381 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_block_state1 : BOOLEAN;
signal tmp_14_fu_297_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_14_reg_386 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_data_V_reg_391 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_last_V_reg_399 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond2_fu_314_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal i_V_fu_319_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal i_V_reg_415 : STD_LOGIC_VECTOR (10 downto 0);
signal exitcond_fu_329_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_state5_pp1_stage0_iter0 : BOOLEAN;
signal ap_predicate_op62_read_state6 : BOOLEAN;
signal ap_block_state6_pp1_stage0_iter1 : BOOLEAN;
signal ap_block_pp1_stage0_11001 : BOOLEAN;
signal j_V_fu_334_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_enable_reg_pp1_iter0 : STD_LOGIC := '0';
signal brmerge_fu_343_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_state8_pp2_stage0_iter0 : BOOLEAN;
signal ap_block_state9_pp2_stage0_iter1 : BOOLEAN;
signal ap_block_pp2_stage0_11001 : BOOLEAN;
signal ap_block_pp1_stage0_subdone : BOOLEAN;
signal ap_enable_reg_pp2_iter0 : STD_LOGIC := '0';
signal ap_CS_fsm_state7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal ap_block_pp2_stage0_subdone : BOOLEAN;
signal ap_phi_mux_eol_2_phi_fu_251_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_last_V1_reg_147 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none";
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal axi_data_V1_reg_157 : STD_LOGIC_VECTOR (23 downto 0);
signal t_V_reg_167 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_phi_mux_eol_phi_fu_193_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_mux_axi_last_V_2_phi_fu_228_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_mux_p_Val2_s_phi_fu_240_p4 : STD_LOGIC_VECTOR (23 downto 0);
signal ap_phi_reg_pp1_iter1_axi_last_V_2_reg_223 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp1_iter1_p_Val2_s_reg_236 : STD_LOGIC_VECTOR (23 downto 0);
signal ap_block_pp1_stage0_01001 : BOOLEAN;
signal sof_1_fu_92 : STD_LOGIC_VECTOR (0 downto 0);
signal t_V_cast_fu_310_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal t_V_3_cast_fu_325_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_user_V_fu_301_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (7 downto 0);
signal ap_idle_pp1 : STD_LOGIC;
signal ap_enable_pp1 : STD_LOGIC;
signal ap_idle_pp2 : STD_LOGIC;
signal ap_enable_pp2 : STD_LOGIC;
signal ap_condition_495 : BOOLEAN;
begin
AXI_video_strm_V_data_V_0_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_data_V_0_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out))) then
AXI_video_strm_V_data_V_0_sel_rd <= not(AXI_video_strm_V_data_V_0_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_data_V_0_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_data_V_0_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_in) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_in))) then
AXI_video_strm_V_data_V_0_sel_wr <= not(AXI_video_strm_V_data_V_0_sel_wr);
end if;
end if;
end if;
end process;
AXI_video_strm_V_data_V_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_data_V_0_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_out)))) then
AXI_video_strm_V_data_V_0_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_in)))) then
AXI_video_strm_V_data_V_0_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_data_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_data_V_0_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_in)))) then
AXI_video_strm_V_data_V_0_state <= ap_const_lv2_3;
else
AXI_video_strm_V_data_V_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
AXI_video_strm_V_dest_V_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_0_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_ack_out)))) then
AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_0_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_vld_in)))) then
AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_dest_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_dest_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_dest_V_0_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_vld_in)))) then
AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_3;
else
AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
AXI_video_strm_V_last_V_0_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_last_V_0_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_out))) then
AXI_video_strm_V_last_V_0_sel_rd <= not(AXI_video_strm_V_last_V_0_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_last_V_0_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_last_V_0_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_in) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_in))) then
AXI_video_strm_V_last_V_0_sel_wr <= not(AXI_video_strm_V_last_V_0_sel_wr);
end if;
end if;
end if;
end process;
AXI_video_strm_V_last_V_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_last_V_0_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_0_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_out)))) then
AXI_video_strm_V_last_V_0_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_0_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_in)))) then
AXI_video_strm_V_last_V_0_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_last_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_last_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_last_V_0_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_in)))) then
AXI_video_strm_V_last_V_0_state <= ap_const_lv2_3;
else
AXI_video_strm_V_last_V_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
AXI_video_strm_V_user_V_0_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_user_V_0_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_out))) then
AXI_video_strm_V_user_V_0_sel_rd <= not(AXI_video_strm_V_user_V_0_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_user_V_0_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_user_V_0_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_in) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_in))) then
AXI_video_strm_V_user_V_0_sel_wr <= not(AXI_video_strm_V_user_V_0_sel_wr);
end if;
end if;
end if;
end process;
AXI_video_strm_V_user_V_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_user_V_0_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_0_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_out)))) then
AXI_video_strm_V_user_V_0_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_0_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_in)))) then
AXI_video_strm_V_user_V_0_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_user_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_user_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_user_V_0_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_in)))) then
AXI_video_strm_V_user_V_0_state <= ap_const_lv2_3;
else
AXI_video_strm_V_user_V_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_continue = ap_const_logic_1)) then
ap_done_reg <= ap_const_logic_0;
elsif (((exitcond2_fu_314_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp1_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
else
if (((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (exitcond_fu_329_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
elsif (((exitcond2_fu_314_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_enable_reg_pp1_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp1_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp1_iter1 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp1_stage0_subdone)) then
ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0;
elsif (((exitcond2_fu_314_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_enable_reg_pp1_iter1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_enable_reg_pp2_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp2_iter0 <= ap_const_logic_0;
else
if (((ap_const_boolean_0 = ap_block_pp2_stage0_subdone) and (ap_phi_mux_eol_2_phi_fu_251_p4 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
ap_enable_reg_pp2_iter0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
ap_enable_reg_pp2_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp2_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp2_iter1 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp2_stage0_subdone)) then
ap_enable_reg_pp2_iter1 <= ap_enable_reg_pp2_iter0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
ap_enable_reg_pp2_iter1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
axi_data_V1_reg_157_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
axi_data_V1_reg_157 <= tmp_data_V_reg_391;
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
axi_data_V1_reg_157 <= axi_data_V_3_reg_271;
end if;
end if;
end process;
axi_data_V_1_reg_212_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (exitcond_reg_420 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
axi_data_V_1_reg_212 <= ap_phi_mux_p_Val2_s_phi_fu_240_p4;
elsif (((exitcond2_fu_314_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
axi_data_V_1_reg_212 <= axi_data_V1_reg_157;
end if;
end if;
end process;
axi_data_V_3_reg_271_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
axi_data_V_3_reg_271 <= axi_data_V_1_reg_212;
elsif (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (eol_2_reg_248 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
axi_data_V_3_reg_271 <= AXI_video_strm_V_data_V_0_data_out;
end if;
end if;
end process;
axi_last_V1_reg_147_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
axi_last_V1_reg_147 <= tmp_last_V_reg_399;
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
axi_last_V1_reg_147 <= axi_last_V_3_reg_259;
end if;
end if;
end process;
axi_last_V_3_reg_259_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
axi_last_V_3_reg_259 <= eol_1_reg_201;
elsif (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (eol_2_reg_248 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
axi_last_V_3_reg_259 <= AXI_video_strm_V_last_V_0_data_out;
end if;
end if;
end process;
eol_1_reg_201_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (exitcond_reg_420 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
eol_1_reg_201 <= ap_phi_mux_axi_last_V_2_phi_fu_228_p4;
elsif (((exitcond2_fu_314_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
eol_1_reg_201 <= axi_last_V1_reg_147;
end if;
end if;
end process;
eol_2_reg_248_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
eol_2_reg_248 <= eol_reg_189;
elsif (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (eol_2_reg_248 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
eol_2_reg_248 <= AXI_video_strm_V_last_V_0_data_out;
end if;
end if;
end process;
eol_reg_189_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (exitcond_reg_420 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
eol_reg_189 <= ap_phi_mux_axi_last_V_2_phi_fu_228_p4;
elsif (((exitcond2_fu_314_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
eol_reg_189 <= ap_const_lv1_0;
end if;
end if;
end process;
sof_1_fu_92_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (exitcond_fu_329_p2 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
sof_1_fu_92 <= ap_const_lv1_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
sof_1_fu_92 <= ap_const_lv1_1;
end if;
end if;
end process;
t_V_2_reg_178_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (exitcond_fu_329_p2 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
t_V_2_reg_178 <= j_V_fu_334_p2;
elsif (((exitcond2_fu_314_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
t_V_2_reg_178 <= ap_const_lv11_0;
end if;
end if;
end process;
t_V_reg_167_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
t_V_reg_167 <= ap_const_lv11_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
t_V_reg_167 <= i_V_reg_415;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_load_A)) then
AXI_video_strm_V_data_V_0_payload_A <= stream_in_TDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_load_B)) then
AXI_video_strm_V_data_V_0_payload_B <= stream_in_TDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_last_V_0_load_A)) then
AXI_video_strm_V_last_V_0_payload_A <= stream_in_TLAST;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_last_V_0_load_B)) then
AXI_video_strm_V_last_V_0_payload_B <= stream_in_TLAST;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_user_V_0_load_A)) then
AXI_video_strm_V_user_V_0_payload_A <= stream_in_TUSER;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_user_V_0_load_B)) then
AXI_video_strm_V_user_V_0_payload_B <= stream_in_TUSER;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (exitcond_fu_329_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
brmerge_reg_429 <= brmerge_fu_343_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
exitcond_reg_420 <= exitcond_fu_329_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
i_V_reg_415 <= i_V_fu_319_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
tmp_13_reg_381 <= tmp_13_fu_293_p1;
tmp_14_reg_386 <= tmp_14_fu_297_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
tmp_data_V_reg_391 <= AXI_video_strm_V_data_V_0_data_out;
tmp_last_V_reg_399 <= AXI_video_strm_V_last_V_0_data_out;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, AXI_video_strm_V_data_V_0_vld_out, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, exitcond2_fu_314_p2, ap_CS_fsm_state4, ap_enable_reg_pp1_iter0, ap_block_pp1_stage0_subdone, ap_enable_reg_pp2_iter0, ap_block_pp2_stage0_subdone, tmp_user_V_fu_301_p1)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((tmp_user_V_fu_301_p1 = ap_const_lv1_0) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_NS_fsm <= ap_ST_fsm_state2;
elsif (((tmp_user_V_fu_301_p1 = ap_const_lv1_1) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_NS_fsm <= ap_ST_fsm_state3;
else
ap_NS_fsm <= ap_ST_fsm_state2;
end if;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
if (((exitcond2_fu_314_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
end if;
when ap_ST_fsm_pp1_stage0 =>
if (not(((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (ap_enable_reg_pp1_iter0 = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0)))) then
ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
elsif (((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (ap_enable_reg_pp1_iter0 = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
ap_NS_fsm <= ap_ST_fsm_state7;
else
ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
end if;
when ap_ST_fsm_state7 =>
ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
when ap_ST_fsm_pp2_stage0 =>
if (not(((ap_const_boolean_0 = ap_block_pp2_stage0_subdone) and (ap_enable_reg_pp2_iter0 = ap_const_logic_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)))) then
ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
elsif (((ap_const_boolean_0 = ap_block_pp2_stage0_subdone) and (ap_enable_reg_pp2_iter0 = ap_const_logic_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
ap_NS_fsm <= ap_ST_fsm_state10;
else
ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
end if;
when ap_ST_fsm_state10 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when others =>
ap_NS_fsm <= "XXXXXXXX";
end case;
end process;
AXI_video_strm_V_data_V_0_ack_in <= AXI_video_strm_V_data_V_0_state(1);
AXI_video_strm_V_data_V_0_ack_out_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_reg_248, ap_predicate_op62_read_state6, ap_block_pp1_stage0_11001, ap_block_pp2_stage0_11001)
begin
if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (eol_2_reg_248 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_predicate_op62_read_state6 = ap_const_boolean_1) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0)) or ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2)))) then
AXI_video_strm_V_data_V_0_ack_out <= ap_const_logic_1;
else
AXI_video_strm_V_data_V_0_ack_out <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_data_V_0_data_out_assign_proc : process(AXI_video_strm_V_data_V_0_payload_A, AXI_video_strm_V_data_V_0_payload_B, AXI_video_strm_V_data_V_0_sel)
begin
if ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_sel)) then
AXI_video_strm_V_data_V_0_data_out <= AXI_video_strm_V_data_V_0_payload_B;
else
AXI_video_strm_V_data_V_0_data_out <= AXI_video_strm_V_data_V_0_payload_A;
end if;
end process;
AXI_video_strm_V_data_V_0_load_A <= (not(AXI_video_strm_V_data_V_0_sel_wr) and AXI_video_strm_V_data_V_0_state_cmp_full);
AXI_video_strm_V_data_V_0_load_B <= (AXI_video_strm_V_data_V_0_state_cmp_full and AXI_video_strm_V_data_V_0_sel_wr);
AXI_video_strm_V_data_V_0_sel <= AXI_video_strm_V_data_V_0_sel_rd;
AXI_video_strm_V_data_V_0_state_cmp_full <= '0' when (AXI_video_strm_V_data_V_0_state = ap_const_lv2_1) else '1';
AXI_video_strm_V_data_V_0_vld_in <= stream_in_TVALID;
AXI_video_strm_V_data_V_0_vld_out <= AXI_video_strm_V_data_V_0_state(0);
AXI_video_strm_V_dest_V_0_ack_out_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_reg_248, ap_predicate_op62_read_state6, ap_block_pp1_stage0_11001, ap_block_pp2_stage0_11001)
begin
if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (eol_2_reg_248 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_predicate_op62_read_state6 = ap_const_boolean_1) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0)) or ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2)))) then
AXI_video_strm_V_dest_V_0_ack_out <= ap_const_logic_1;
else
AXI_video_strm_V_dest_V_0_ack_out <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_dest_V_0_vld_in <= stream_in_TVALID;
AXI_video_strm_V_last_V_0_ack_in <= AXI_video_strm_V_last_V_0_state(1);
AXI_video_strm_V_last_V_0_ack_out_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_reg_248, ap_predicate_op62_read_state6, ap_block_pp1_stage0_11001, ap_block_pp2_stage0_11001)
begin
if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (eol_2_reg_248 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_predicate_op62_read_state6 = ap_const_boolean_1) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0)) or ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2)))) then
AXI_video_strm_V_last_V_0_ack_out <= ap_const_logic_1;
else
AXI_video_strm_V_last_V_0_ack_out <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_last_V_0_data_out_assign_proc : process(AXI_video_strm_V_last_V_0_payload_A, AXI_video_strm_V_last_V_0_payload_B, AXI_video_strm_V_last_V_0_sel)
begin
if ((ap_const_logic_1 = AXI_video_strm_V_last_V_0_sel)) then
AXI_video_strm_V_last_V_0_data_out <= AXI_video_strm_V_last_V_0_payload_B;
else
AXI_video_strm_V_last_V_0_data_out <= AXI_video_strm_V_last_V_0_payload_A;
end if;
end process;
AXI_video_strm_V_last_V_0_load_A <= (not(AXI_video_strm_V_last_V_0_sel_wr) and AXI_video_strm_V_last_V_0_state_cmp_full);
AXI_video_strm_V_last_V_0_load_B <= (AXI_video_strm_V_last_V_0_state_cmp_full and AXI_video_strm_V_last_V_0_sel_wr);
AXI_video_strm_V_last_V_0_sel <= AXI_video_strm_V_last_V_0_sel_rd;
AXI_video_strm_V_last_V_0_state_cmp_full <= '0' when (AXI_video_strm_V_last_V_0_state = ap_const_lv2_1) else '1';
AXI_video_strm_V_last_V_0_vld_in <= stream_in_TVALID;
AXI_video_strm_V_last_V_0_vld_out <= AXI_video_strm_V_last_V_0_state(0);
AXI_video_strm_V_user_V_0_ack_in <= AXI_video_strm_V_user_V_0_state(1);
AXI_video_strm_V_user_V_0_ack_out_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_reg_248, ap_predicate_op62_read_state6, ap_block_pp1_stage0_11001, ap_block_pp2_stage0_11001)
begin
if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (eol_2_reg_248 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_predicate_op62_read_state6 = ap_const_boolean_1) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0)) or ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2)))) then
AXI_video_strm_V_user_V_0_ack_out <= ap_const_logic_1;
else
AXI_video_strm_V_user_V_0_ack_out <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_user_V_0_data_out_assign_proc : process(AXI_video_strm_V_user_V_0_payload_A, AXI_video_strm_V_user_V_0_payload_B, AXI_video_strm_V_user_V_0_sel)
begin
if ((ap_const_logic_1 = AXI_video_strm_V_user_V_0_sel)) then
AXI_video_strm_V_user_V_0_data_out <= AXI_video_strm_V_user_V_0_payload_B;
else
AXI_video_strm_V_user_V_0_data_out <= AXI_video_strm_V_user_V_0_payload_A;
end if;
end process;
AXI_video_strm_V_user_V_0_load_A <= (not(AXI_video_strm_V_user_V_0_sel_wr) and AXI_video_strm_V_user_V_0_state_cmp_full);
AXI_video_strm_V_user_V_0_load_B <= (AXI_video_strm_V_user_V_0_state_cmp_full and AXI_video_strm_V_user_V_0_sel_wr);
AXI_video_strm_V_user_V_0_sel <= AXI_video_strm_V_user_V_0_sel_rd;
AXI_video_strm_V_user_V_0_state_cmp_full <= '0' when (AXI_video_strm_V_user_V_0_state = ap_const_lv2_1) else '1';
AXI_video_strm_V_user_V_0_vld_in <= stream_in_TVALID;
AXI_video_strm_V_user_V_0_vld_out <= AXI_video_strm_V_user_V_0_state(0);
ap_CS_fsm_pp1_stage0 <= ap_CS_fsm(4);
ap_CS_fsm_pp2_stage0 <= ap_CS_fsm(6);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state10 <= ap_CS_fsm(7);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state7 <= ap_CS_fsm(5);
ap_block_pp1_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp1_stage0_01001_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, ap_enable_reg_pp1_iter1, exitcond_reg_420, ap_predicate_op62_read_state6)
begin
ap_block_pp1_stage0_01001 <= ((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_predicate_op62_read_state6 = ap_const_boolean_1)) or ((exitcond_reg_420 = ap_const_lv1_0) and (img_data_stream_2_V_full_n = ap_const_logic_0)) or ((exitcond_reg_420 = ap_const_lv1_0) and (img_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond_reg_420 = ap_const_lv1_0) and (img_data_stream_0_V_full_n = ap_const_logic_0))));
end process;
ap_block_pp1_stage0_11001_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, ap_enable_reg_pp1_iter1, exitcond_reg_420, ap_predicate_op62_read_state6)
begin
ap_block_pp1_stage0_11001 <= ((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_predicate_op62_read_state6 = ap_const_boolean_1)) or ((exitcond_reg_420 = ap_const_lv1_0) and (img_data_stream_2_V_full_n = ap_const_logic_0)) or ((exitcond_reg_420 = ap_const_lv1_0) and (img_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond_reg_420 = ap_const_lv1_0) and (img_data_stream_0_V_full_n = ap_const_logic_0))));
end process;
ap_block_pp1_stage0_subdone_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, ap_enable_reg_pp1_iter1, exitcond_reg_420, ap_predicate_op62_read_state6)
begin
ap_block_pp1_stage0_subdone <= ((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_predicate_op62_read_state6 = ap_const_boolean_1)) or ((exitcond_reg_420 = ap_const_lv1_0) and (img_data_stream_2_V_full_n = ap_const_logic_0)) or ((exitcond_reg_420 = ap_const_lv1_0) and (img_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond_reg_420 = ap_const_lv1_0) and (img_data_stream_0_V_full_n = ap_const_logic_0))));
end process;
ap_block_pp2_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp2_stage0_11001_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_enable_reg_pp2_iter1, eol_2_reg_248)
begin
ap_block_pp2_stage0_11001 <= ((eol_2_reg_248 = ap_const_lv1_0) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1));
end process;
ap_block_pp2_stage0_subdone_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_enable_reg_pp2_iter1, eol_2_reg_248)
begin
ap_block_pp2_stage0_subdone <= ((eol_2_reg_248 = ap_const_lv1_0) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1));
end process;
ap_block_state1_assign_proc : process(ap_start, ap_done_reg)
begin
ap_block_state1 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
ap_block_state5_pp1_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp1_stage0_iter1_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, exitcond_reg_420, ap_predicate_op62_read_state6)
begin
ap_block_state6_pp1_stage0_iter1 <= (((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_predicate_op62_read_state6 = ap_const_boolean_1)) or ((exitcond_reg_420 = ap_const_lv1_0) and (img_data_stream_2_V_full_n = ap_const_logic_0)) or ((exitcond_reg_420 = ap_const_lv1_0) and (img_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond_reg_420 = ap_const_lv1_0) and (img_data_stream_0_V_full_n = ap_const_logic_0)));
end process;
ap_block_state8_pp2_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp2_stage0_iter1_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, eol_2_reg_248)
begin
ap_block_state9_pp2_stage0_iter1 <= ((eol_2_reg_248 = ap_const_lv1_0) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out));
end process;
ap_condition_495_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_reg_420)
begin
ap_condition_495 <= ((exitcond_reg_420 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0));
end process;
ap_done_assign_proc : process(ap_done_reg, exitcond2_fu_314_p2, ap_CS_fsm_state4)
begin
if (((exitcond2_fu_314_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_enable_pp1 <= (ap_idle_pp1 xor ap_const_logic_1);
ap_enable_pp2 <= (ap_idle_pp2 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp1_assign_proc : process(ap_enable_reg_pp1_iter1, ap_enable_reg_pp1_iter0)
begin
if (((ap_enable_reg_pp1_iter0 = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0))) then
ap_idle_pp1 <= ap_const_logic_1;
else
ap_idle_pp1 <= ap_const_logic_0;
end if;
end process;
ap_idle_pp2_assign_proc : process(ap_enable_reg_pp2_iter1, ap_enable_reg_pp2_iter0)
begin
if (((ap_enable_reg_pp2_iter0 = ap_const_logic_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_0))) then
ap_idle_pp2 <= ap_const_logic_1;
else
ap_idle_pp2 <= ap_const_logic_0;
end if;
end process;
ap_phi_mux_axi_last_V_2_phi_fu_228_p4_assign_proc : process(AXI_video_strm_V_last_V_0_data_out, brmerge_reg_429, eol_1_reg_201, ap_phi_reg_pp1_iter1_axi_last_V_2_reg_223, ap_condition_495)
begin
if ((ap_const_boolean_1 = ap_condition_495)) then
if ((brmerge_reg_429 = ap_const_lv1_1)) then
ap_phi_mux_axi_last_V_2_phi_fu_228_p4 <= eol_1_reg_201;
elsif ((brmerge_reg_429 = ap_const_lv1_0)) then
ap_phi_mux_axi_last_V_2_phi_fu_228_p4 <= AXI_video_strm_V_last_V_0_data_out;
else
ap_phi_mux_axi_last_V_2_phi_fu_228_p4 <= ap_phi_reg_pp1_iter1_axi_last_V_2_reg_223;
end if;
else
ap_phi_mux_axi_last_V_2_phi_fu_228_p4 <= ap_phi_reg_pp1_iter1_axi_last_V_2_reg_223;
end if;
end process;
ap_phi_mux_eol_2_phi_fu_251_p4_assign_proc : process(AXI_video_strm_V_last_V_0_data_out, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, eol_2_reg_248)
begin
if (((eol_2_reg_248 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
ap_phi_mux_eol_2_phi_fu_251_p4 <= AXI_video_strm_V_last_V_0_data_out;
else
ap_phi_mux_eol_2_phi_fu_251_p4 <= eol_2_reg_248;
end if;
end process;
ap_phi_mux_eol_phi_fu_193_p4_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_reg_420, eol_reg_189, ap_phi_mux_axi_last_V_2_phi_fu_228_p4)
begin
if (((exitcond_reg_420 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
ap_phi_mux_eol_phi_fu_193_p4 <= ap_phi_mux_axi_last_V_2_phi_fu_228_p4;
else
ap_phi_mux_eol_phi_fu_193_p4 <= eol_reg_189;
end if;
end process;
ap_phi_mux_p_Val2_s_phi_fu_240_p4_assign_proc : process(AXI_video_strm_V_data_V_0_data_out, brmerge_reg_429, axi_data_V_1_reg_212, ap_phi_reg_pp1_iter1_p_Val2_s_reg_236, ap_condition_495)
begin
if ((ap_const_boolean_1 = ap_condition_495)) then
if ((brmerge_reg_429 = ap_const_lv1_1)) then
ap_phi_mux_p_Val2_s_phi_fu_240_p4 <= axi_data_V_1_reg_212;
elsif ((brmerge_reg_429 = ap_const_lv1_0)) then
ap_phi_mux_p_Val2_s_phi_fu_240_p4 <= AXI_video_strm_V_data_V_0_data_out;
else
ap_phi_mux_p_Val2_s_phi_fu_240_p4 <= ap_phi_reg_pp1_iter1_p_Val2_s_reg_236;
end if;
else
ap_phi_mux_p_Val2_s_phi_fu_240_p4 <= ap_phi_reg_pp1_iter1_p_Val2_s_reg_236;
end if;
end process;
ap_phi_reg_pp1_iter1_axi_last_V_2_reg_223 <= "X";
ap_phi_reg_pp1_iter1_p_Val2_s_reg_236 <= "XXXXXXXXXXXXXXXXXXXXXXXX";
ap_predicate_op62_read_state6_assign_proc : process(exitcond_reg_420, brmerge_reg_429)
begin
ap_predicate_op62_read_state6 <= ((brmerge_reg_429 = ap_const_lv1_0) and (exitcond_reg_420 = ap_const_lv1_0));
end process;
ap_ready_assign_proc : process(exitcond2_fu_314_p2, ap_CS_fsm_state4)
begin
if (((exitcond2_fu_314_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
brmerge_fu_343_p2 <= (sof_1_fu_92 or ap_phi_mux_eol_phi_fu_193_p4);
exitcond2_fu_314_p2 <= "1" when (t_V_cast_fu_310_p1 = tmp_13_reg_381) else "0";
exitcond_fu_329_p2 <= "1" when (t_V_3_cast_fu_325_p1 = tmp_14_reg_386) else "0";
i_V_fu_319_p2 <= std_logic_vector(unsigned(t_V_reg_167) + unsigned(ap_const_lv11_1));
img_data_stream_0_V_blk_n_assign_proc : process(img_data_stream_0_V_full_n, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_reg_420)
begin
if (((exitcond_reg_420 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_0_V_blk_n <= img_data_stream_0_V_full_n;
else
img_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_data_stream_0_V_din <= ap_phi_mux_p_Val2_s_phi_fu_240_p4(8 - 1 downto 0);
img_data_stream_0_V_write_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, exitcond_reg_420, ap_block_pp1_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (exitcond_reg_420 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_0_V_write <= ap_const_logic_1;
else
img_data_stream_0_V_write <= ap_const_logic_0;
end if;
end process;
img_data_stream_1_V_blk_n_assign_proc : process(img_data_stream_1_V_full_n, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_reg_420)
begin
if (((exitcond_reg_420 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_1_V_blk_n <= img_data_stream_1_V_full_n;
else
img_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_data_stream_1_V_din <= ap_phi_mux_p_Val2_s_phi_fu_240_p4(15 downto 8);
img_data_stream_1_V_write_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, exitcond_reg_420, ap_block_pp1_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (exitcond_reg_420 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_1_V_write <= ap_const_logic_1;
else
img_data_stream_1_V_write <= ap_const_logic_0;
end if;
end process;
img_data_stream_2_V_blk_n_assign_proc : process(img_data_stream_2_V_full_n, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_reg_420)
begin
if (((exitcond_reg_420 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_2_V_blk_n <= img_data_stream_2_V_full_n;
else
img_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_data_stream_2_V_din <= ap_phi_mux_p_Val2_s_phi_fu_240_p4(23 downto 16);
img_data_stream_2_V_write_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, exitcond_reg_420, ap_block_pp1_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (exitcond_reg_420 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_2_V_write <= ap_const_logic_1;
else
img_data_stream_2_V_write <= ap_const_logic_0;
end if;
end process;
j_V_fu_334_p2 <= std_logic_vector(unsigned(t_V_2_reg_178) + unsigned(ap_const_lv11_1));
stream_in_TDATA_blk_n_assign_proc : process(AXI_video_strm_V_data_V_0_state, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_reg_420, brmerge_reg_429, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, eol_2_reg_248)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) or ((eol_2_reg_248 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((brmerge_reg_429 = ap_const_lv1_0) and (exitcond_reg_420 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0)))) then
stream_in_TDATA_blk_n <= AXI_video_strm_V_data_V_0_state(0);
else
stream_in_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
stream_in_TREADY <= AXI_video_strm_V_dest_V_0_state(1);
t_V_3_cast_fu_325_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(t_V_2_reg_178),12));
t_V_cast_fu_310_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(t_V_reg_167),12));
tmp_13_fu_293_p1 <= img_rows_V_read(12 - 1 downto 0);
tmp_14_fu_297_p1 <= img_cols_V_read(12 - 1 downto 0);
tmp_user_V_fu_301_p1 <= AXI_video_strm_V_user_V_0_data_out;
end behav;
|
mit
|
527fb5e80033abc455230f37ee120d22
| 0.600918 | 2.627824 | false | false | false | false |
olajep/oh
|
src/adi/hdl/library/axi_spdif_tx/tx_encoder.vhd
| 3 | 20,140 |
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- SPDIF transmitter signal encoder. Reads out samples from the ----
---- sample buffer, assembles frames and subframes and encodes ----
---- serial data as bi-phase mark code. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tx_encoder is
generic (DATA_WIDTH: integer range 16 to 32 := 32);
port (
up_clk: in std_logic; -- clock
data_clk : in std_logic; -- data clock
resetn : in std_logic; -- resetn
conf_mode: in std_logic_vector(3 downto 0); -- sample format
conf_ratio: in std_logic_vector(7 downto 0); -- clock divider
conf_txdata: in std_logic; -- sample data enable
conf_txen: in std_logic; -- spdif signal enable
chstat_freq: in std_logic_vector(1 downto 0); -- sample freq.
chstat_gstat: in std_logic; -- generation status
chstat_preem: in std_logic; -- preemphasis status
chstat_copy: in std_logic; -- copyright bit
chstat_audio: in std_logic; -- data format
sample_data: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data
sample_data_ack: out std_logic; -- sample buffer read
channel: out std_logic;
spdif_tx_o: out std_logic);
end tx_encoder;
architecture rtl of tx_encoder is
signal spdif_clk_en, spdif_out : std_logic;
signal clk_cnt : integer range 0 to 511;
type buf_states is (IDLE, READ_CHA, READ_CHB, CHA_RDY, CHB_RDY);
signal bufctrl : buf_states;
signal cha_samp_ack, chb_samp_ack : std_logic;
type frame_states is (IDLE, BLOCK_START, CHANNEL_A, CHANNEL_B);
signal framest : frame_states;
signal frame_cnt : integer range 0 to 191;
signal bit_cnt, par_cnt : integer range 0 to 31;
signal inv_preamble, toggle, valid : std_logic;
signal def_user_data, def_ch_status : std_logic_vector(191 downto 0);
signal active_user_data, active_ch_status : std_logic_vector(191 downto 0);
signal audio : std_logic_vector(23 downto 0);
signal par_vector : std_logic_vector(26 downto 0);
signal send_audio : std_logic;
signal cdc_sync_stage0_tick_counter : std_logic := '0';
signal cdc_sync_stage1_tick_counter : std_logic := '0';
signal cdc_sync_stage2_tick_counter : std_logic := '0';
signal cdc_sync_stage3_tick_counter : std_logic := '0';
signal tick_counter : std_logic;
constant X_PREAMBLE : std_logic_vector(0 to 7) := "11100010";
constant Y_PREAMBLE : std_logic_vector(0 to 7) := "11100100";
constant Z_PREAMBLE : std_logic_vector(0 to 7) := "11101000";
function encode_bit (
signal bit_cnt : integer; -- sub-frame bit position
signal valid : std_logic; -- validity bit
signal frame_cnt : integer; -- frame counter
signal par_cnt : integer; -- parity counter
signal user_data : std_logic_vector(191 downto 0);
signal ch_status : std_logic_vector(191 downto 0);
signal audio : std_logic_vector(23 downto 0);
signal toggle : std_logic;
signal prev_spdif : std_logic) -- prev. value of spdif signal
return std_logic is
variable spdif, next_bit : std_logic;
begin
if bit_cnt > 3 and bit_cnt < 28 then -- audio part
next_bit := audio(bit_cnt - 4);
elsif bit_cnt = 28 then -- validity bit
next_bit := valid;
elsif bit_cnt = 29 then -- user data
next_bit := user_data(frame_cnt);
elsif bit_cnt = 30 then
next_bit := ch_status(frame_cnt); -- channel status
elsif bit_cnt = 31 then
if par_cnt mod 2 = 1 then
next_bit := '1';
else
next_bit := '0';
end if;
end if;
-- bi-phase mark encoding:
if next_bit = '0' then
if toggle = '0' then
spdif := not prev_spdif;
else
spdif := prev_spdif;
end if;
else
spdif := not prev_spdif;
end if;
return(spdif);
end encode_bit;
begin
-- SPDIF clock enable generation. The clock is a fraction of the data clock,
-- determined by the conf_ratio value.
DCLK : process (data_clk)
begin
if rising_edge(data_clk) then
cdc_sync_stage0_tick_counter <= not cdc_sync_stage0_tick_counter;
end if;
end process DCLK;
process (up_clk) begin
if rising_edge(up_clk) then
cdc_sync_stage1_tick_counter <= cdc_sync_stage0_tick_counter;
cdc_sync_stage2_tick_counter <= cdc_sync_stage1_tick_counter;
cdc_sync_stage3_tick_counter <= cdc_sync_stage2_tick_counter;
end if;
end process;
tick_counter <= cdc_sync_stage3_tick_counter xor cdc_sync_stage2_tick_counter;
CGEN: process (up_clk)
begin
if rising_edge(up_clk) then
if resetn = '0' or conf_txen = '0' then
clk_cnt <= 0;
spdif_clk_en <= '0';
else
spdif_clk_en <= '0';
if tick_counter = '1' then
if clk_cnt < to_integer(unsigned(conf_ratio)) then
clk_cnt <= clk_cnt + 1;
else
clk_cnt <= 0;
spdif_clk_en <= '1';
end if;
end if;
end if;
end if;
end process CGEN;
SRD: process (up_clk)
begin
if rising_edge(up_clk) then
if resetn = '0' or conf_txdata = '0' then
bufctrl <= IDLE;
sample_data_ack <= '0';
channel <= '0';
else
case bufctrl is
when IDLE =>
sample_data_ack <= '0';
if conf_txdata = '1' then
bufctrl <= READ_CHA;
sample_data_ack <='1';
end if;
when READ_CHA =>
channel <= '0';
sample_data_ack <= '0';
bufctrl <= CHA_RDY;
when CHA_RDY =>
if cha_samp_ack = '1' then
sample_data_ack <= '1';
bufctrl <= READ_CHB;
end if;
when READ_CHB =>
channel <= '1';
sample_data_ack <= '0';
bufctrl <= CHB_RDY;
when CHB_RDY =>
if chb_samp_ack = '1' then
sample_data_ack <= '1';
bufctrl <= READ_CHA;
end if;
when others =>
bufctrl <= IDLE;
end case;
end if;
end if;
end process SRD;
TXSYNC: process (data_clk)
begin
if (rising_edge(data_clk)) then
spdif_tx_o <= spdif_out;
end if;
end process TXSYNC;
-- State machine that generates sub-frames and blocks
FRST: process (up_clk)
begin
if rising_edge(up_clk) then
if resetn = '0' or conf_txen = '0' then
framest <= IDLE;
frame_cnt <= 0;
bit_cnt <= 0;
spdif_out <= '0';
inv_preamble <= '0';
toggle <= '0';
valid <= '1';
send_audio <= '0';
cha_samp_ack <= '0';
chb_samp_ack <= '0';
else
if spdif_clk_en = '1' then -- SPDIF clock is twice the bit rate
case framest is
when IDLE =>
bit_cnt <= 0;
frame_cnt <= 0;
inv_preamble <= '0';
toggle <= '0';
framest <= BLOCK_START;
when BLOCK_START => -- Start of channels status block/Ch. A
chb_samp_ack <= '0';
toggle <= not toggle; -- Each bit uses two clock enables,
if toggle = '1' then -- counted by the toggle bit.
if bit_cnt < 31 then
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 0;
if send_audio = '1' then
cha_samp_ack <= '1';
end if;
framest <= CHANNEL_B;
end if;
end if;
-- Block start uses preamble Z.
if bit_cnt < 4 then
if toggle = '0' then
spdif_out <= Z_PREAMBLE(2 * bit_cnt) xor inv_preamble;
else
spdif_out <= Z_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
end if;
par_cnt <= 0;
elsif bit_cnt > 3 and bit_cnt <= 31 then
spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
if bit_cnt = 31 then
inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
end if;
if toggle = '0' then
if bit_cnt > 3 and bit_cnt < 31 and
par_vector(bit_cnt - 4) = '1' then
par_cnt <= par_cnt + 1;
end if;
end if;
end if;
when CHANNEL_A => -- Sub-frame: channel A.
chb_samp_ack <= '0';
toggle <= not toggle;
if toggle = '1' then
if bit_cnt < 31 then
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 0;
if spdif_out = '1' then
inv_preamble <= '1';
else
inv_preamble <= '0';
end if;
if send_audio = '1' then
cha_samp_ack <= '1';
end if;
framest <= CHANNEL_B;
end if;
end if;
-- Channel A uses preable X.
if bit_cnt < 4 then
if toggle = '0' then
spdif_out <= X_PREAMBLE(2 * bit_cnt) xor inv_preamble;
else
spdif_out <= X_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
end if;
par_cnt <= 0;
elsif bit_cnt > 3 and bit_cnt <= 31 then
spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
if bit_cnt = 31 then
inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
end if;
if toggle = '0' then
if bit_cnt > 3 and bit_cnt < 31 and
par_vector(bit_cnt - 4) = '1' then
par_cnt <= par_cnt + 1;
end if;
end if;
end if;
when CHANNEL_B => -- Sub-frame: channel B.
cha_samp_ack <= '0';
toggle <= not toggle;
if toggle = '1' then
if bit_cnt < 31 then
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 0;
valid <= not conf_txdata;
if spdif_out = '1' then
inv_preamble <= '1';
else
inv_preamble <= '0';
end if;
send_audio <= conf_txdata; -- 1 if audio samples sohuld be sent
if send_audio = '1' then
chb_samp_ack <= '1';
end if;
if frame_cnt < 191 then -- One block is 192 frames
frame_cnt <= frame_cnt + 1;
framest <= CHANNEL_A;
else
frame_cnt <= 0;
framest <= BLOCK_START;
end if;
end if;
end if;
-- Channel B uses preable Y.
if bit_cnt < 4 then
if toggle = '0' then
spdif_out <= Y_PREAMBLE(2 * bit_cnt) xor inv_preamble;
else
spdif_out <= Y_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
end if;
par_cnt <= 0;
elsif bit_cnt > 3 and bit_cnt <= 31 then
spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
if bit_cnt = 31 then
inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
end if;
if toggle = '0' then
if bit_cnt > 3 and bit_cnt < 31 and
par_vector(bit_cnt - 4) = '1' then
par_cnt <= par_cnt + 1;
end if;
end if;
end if;
when others =>
framest <= IDLE;
end case;
end if;
end if;
end if;
end process FRST;
-- Audio data latching
DA32: if DATA_WIDTH = 32 generate
ALAT: process (up_clk)
begin
if rising_edge(up_clk) then
if send_audio = '0' then
audio(23 downto 0) <= (others => '0');
else
case to_integer(unsigned(conf_mode)) is
when 0 => -- 16 bit audio
audio(23 downto 8) <= sample_data(15 downto 0);
audio(7 downto 0) <= (others => '0');
when 1 => -- 17 bit audio
audio(23 downto 7) <= sample_data(16 downto 0);
audio(6 downto 0) <= (others => '0');
when 2 => -- 18 bit audio
audio(23 downto 6) <= sample_data(17 downto 0);
audio(5 downto 0) <= (others => '0');
when 3 => -- 19 bit audio
audio(23 downto 5) <= sample_data(18 downto 0);
audio(4 downto 0) <= (others => '0');
when 4 => -- 20 bit audio
audio(23 downto 4) <= sample_data(19 downto 0);
audio(3 downto 0) <= (others => '0');
when 5 => -- 21 bit audio
audio(23 downto 3) <= sample_data(20 downto 0);
audio(2 downto 0) <= (others => '0');
when 6 => -- 22 bit audio
audio(23 downto 2) <= sample_data(21 downto 0);
audio(1 downto 0) <= (others => '0');
when 7 => -- 23 bit audio
audio(23 downto 1) <= sample_data(22 downto 0);
audio(0) <= '0';
when 8 => -- 24 bit audio
audio(23 downto 0) <= sample_data(23 downto 0);
when others => -- unsupported modes
audio(23 downto 0) <= (others => '0');
end case;
end if;
end if;
end process ALAT;
end generate DA32;
DA16: if DATA_WIDTH = 16 generate
ALAT: process (up_clk)
begin
if rising_edge(up_clk) then
if send_audio = '0' then
audio(23 downto 0) <= (others => '0');
else
audio(23 downto 8) <= sample_data(15 downto 0);
audio(7 downto 0) <= (others => '0');
end if;
end if;
end process ALAT;
end generate DA16;
-- Parity vector. These bits are counted to generate even parity
par_vector(23 downto 0) <= audio(23 downto 0);
par_vector(24) <= valid;
par_vector(25) <= active_user_data(frame_cnt);
par_vector(26) <= active_ch_status(frame_cnt);
-- Channel status and user datat to be used if buffers are disabled.
-- User data is then all zero, while channel status bits are taken from
-- register TxChStat.
def_user_data(191 downto 0) <= (others => '0');
def_ch_status(0) <= '0'; -- consumer mode
def_ch_status(1) <= chstat_audio; -- audio bit
def_ch_status(2) <= chstat_copy; -- copy right
def_ch_status(5 downto 3) <= "000" when chstat_preem = '0'
else "001"; -- pre-emphasis
def_ch_status(7 downto 6) <= "00";
def_ch_status(14 downto 8) <= (others => '0');
def_ch_status(15) <= chstat_gstat; -- generation status
def_ch_status(23 downto 16) <= (others => '0');
def_ch_status(27 downto 24) <= "0000" when chstat_freq = "00" else
"0010" when chstat_freq = "01" else
"0011" when chstat_freq = "10" else
"0001";
def_ch_status(191 downto 28) <= (others => '0'); --191 28
-- Generate channel status vector based on configuration register setting.
active_ch_status <= def_ch_status;
-- Generate user data vector based on configuration register setting.
active_user_data <= def_user_data;
end rtl;
|
mit
|
5c8952c711db6e8c371a8d37cd0980b1
| 0.448858 | 4.325601 | false | false | false | false |
rickyzhangNYC/Pipelined_Multimedia_Cell_Lite_Unit
|
sixteenbit_tb.vhd
| 1 | 1,872 |
-------------------------------------------------------------------------------
--
-- Title : sixteenbit_tb
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\sixteenbit_tb.vhd
-- Generated : Sun Nov 20 18:23:18 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {sixteenbit_tb} architecture {behavior}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity sixteenbit_tb is
end sixteenbit_tb;
--}} End of automatically maintained section
architecture behavior of sixteenbit_tb is
signal a_tb, b_tb, sum_tb: std_logic_vector (15 downto 0);
signal c0: std_logic;
signal Carry_tb: std_logic;
begin
-- Create an instance of the circuit to be tested
uut: entity sixteenbit_module port map(c0 => c0, a => a_tb, b => b_tb,
s => sum_tb, Carry => Carry_tb);
-- Define a process to apply input stimulus and test outputs
tb : process
variable tempC : std_logic_vector(15 downto 0);
constant period: time := 20 ns;
constant n: integer := 16;
begin -- Apply every possible input combination
tempC(0) := c0;
for i in 0 to 2**n-1 loop
(a_tb, b_tb) <= to_unsigned(i,n);
wait for period;
assert ((sum_tb = ((a(i) xor b(i)) xor tempC(i)))
)
report "test failed" severity error;
end loop;
wait; -- indefinitely suspend process
end process;
end behavior;
|
apache-2.0
|
5161e4bb4b452ed58b626b99a96613e3
| 0.525641 | 3.744 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodScopeController/src/GainOffsetCalib.vhd
| 2 | 10,718 |
-------------------------------------------------------------------------------
--
-- File: GainOffsetCalib.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module applies the gain and offset calibration to the raw data samples
-- received from the DataPath module.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity GainOffsetCalib is
Generic (
-- ADC/DAC number of bits
kWidth : integer range 10 to 16 := 14;
-- ADC/DAC dynamic/static calibration
kExtCalibEn : boolean := true;
-- When asserted, kInvert determines the sign inversion of the data samples
-- received. Used to compensate the physical inversion of some of the
-- channels on the PCB at the ADC/DAC input/output on the Zmod.
kInvert : boolean := false;
-- Low gain multiplicative (gain) compensation coefficient parameter
kLgMultCoefStatic : std_logic_vector (17 downto 0) := "010000000000000000";
-- Low gain additive (offset) compensation coefficient parameter
kLgAddCoefStatic : std_logic_vector (17 downto 0) := "000000000000000000";
-- High gain multiplicative (gain) compensation coefficient parameter
kHgMultCoefStatic : std_logic_vector (17 downto 0) := "010000000000000000";
-- High gain additive (offset) compensation coefficient parameter
kHgAddCoefStatic : std_logic_vector (17 downto 0) := "000000000000000000"
);
Port (
-- Sampling clock
SamplingClk : in STD_LOGIC;
-- Reset signal asynchronously asserted and synchronously
-- de-asserted (in the SamplingClk domain)
acRst_n : in STD_LOGIC;
-- cTestMode is used to bypass the calibration block. When this signal
-- is asserted, raw samples are provided on the data interface
cTestMode : in STD_LOGIC;
-- Low gain gain compensation coefficient external port
cExtLgMultCoef : in std_logic_vector (17 downto 0);
-- Low gain offset compensation coefficient external port
cExtLgAddCoef : in std_logic_vector (17 downto 0);
-- High gain gain compensation coefficient external port
cExtHgMultCoef : in std_logic_vector (17 downto 0);
-- High gain offset compensation coefficient external port
cExtHgAddCoef : in std_logic_vector (17 downto 0);
-- Gain Relay State (1 -> High Gain; 0 -> Low Gain)
cGainState : in std_logic;
-- Raw data input
cDataRaw : in STD_LOGIC_VECTOR (kWidth-1 downto 0);
-- Raw data valid signal
cDataInValid : in STD_LOGIC;
-- Calibrated output data
cCalibDataOut : out STD_LOGIC_VECTOR (15 downto 0);
-- Output data valid signal
cDataCalibValid : out STD_LOGIC
);
end GainOffsetCalib;
architecture Behavioral of GainOffsetCalib is
signal cDataRaw18bSigned : signed(17 downto 0);
signal cDataRaw18b : std_logic_vector(17 downto 0);
signal cCalibMult : signed(35 downto 0);
signal cCalibAdd : signed(35 downto 0);
signal cCoefAdd : std_logic_vector(35 downto 0);
signal cCoefAddSigned : signed(35 downto 0);
signal cCoefMult : std_logic_vector(17 downto 0);
signal cCoefMultSigned : signed(17 downto 0);
signal cCoefMultLg, cCoefMultHg : std_logic_vector (17 downto 0);
signal cCoefAddLg, cCoefAddHg : std_logic_vector (17 downto 0);
signal cDataInValidR : STD_LOGIC;
constant kDummy : std_logic_vector (17-kWidth downto 0) := (others => '0');
begin
--Channel1 low gain gain compensation coefficient (output port or IP parameter).
cCoefMultLg <= cExtLgMultCoef when kExtCalibEn = true else kLgMultCoefStatic;
--Channel1 high gain gain compensation coefficient (output port or IP parameter).
cCoefMultHg <= cExtHgMultCoef when kExtCalibEn = true else kHgMultCoefStatic;
--Channel1 low gain offset compensation coefficient (output port or IP parameter).
cCoefAddLg <= cExtLgAddCoef when kExtCalibEn = true else kLgAddCoefStatic;
--Channel1 high gain offset compensation coefficient (output port or IP parameter).
cCoefAddHg <= cExtHgAddCoef when kExtCalibEn = true else kHgAddCoefStatic;
-- Numerical representation of the calibration module's signals:
-- The first operation of the calibration block is represented by the multiplication
-- of the raw data input by the multiplicative coefficient. The multiplier's
-- operands are represented as follows:
-- 1. The input raw data is considered to be a fractional number < 1, consisting
-- of a sign bit and 17 fractional bits.
-- 2. The multiplicative coefficient, which can be slightly higher or slightly
-- lower than 1, is also represented on 18 bits, i.e. 1 sign bit, 1 integer bit,
-- and 16 fractional bis.
-- The result of the multiplication is a 36 bit number, consisting of a sign bit,
-- 2 integer bits and 33 fractional bits. Thus, to apply the additive coefficient,
-- (which is interpreted by the module as a 18 bit fractional number - 1 sign bit
-- + 17 fractional bits)the additive coefficient is also converted to this format
-- (sign extended by 2 bits and padded with 16 fractional bits).
-- Determine the additive coefficient based on the channel's gain relay state
-- and convert it to a 36 bit representation (as explained above).
ProcAddCoef : process (SamplingClk, acRst_n)
begin
if (acRst_n = '0') then
cCoefAdd <= (others => '0');
elsif (rising_edge(SamplingClk)) then
if (cGainState = '0') then --Low Gain
cCoefAdd <= cCoefAddLg(17) & cCoefAddLg(17) & cCoefAddLg & x"0000";
else --High Gain
cCoefAdd <= cCoefAddHg(17) & cCoefAddHg(17) & cCoefAddHg & x"0000";
end if;
end if;
end process;
-- Determine the multiplicative coefficient based on the channel's gain relay state.
ProcMultCoef : process (SamplingClk, acRst_n)
begin
if (acRst_n = '0') then
cCoefMult <= "010000000000000000";
elsif (rising_edge(SamplingClk)) then
if (cGainState = '0') then
cCoefMult <= cCoefMultLg;
else
cCoefMult <= cCoefMultHg;
end if;
end if;
end process;
cDataRaw18b <= cDataRaw & kDummy;
-- Invert raw data input if the analog channel is inverted at the
-- ADC/DAC input/output. Inversion of the minimum negative value (-2^kWidth)
-- needs to be done explicitly.
ProcInvert : process (cDataRaw18b)
begin
if (kInvert = false) then
if (cDataRaw18b = "100000000000000000") then
-- For the inverted channel, because the inversion is done at the FPGA
-- level, the minimum negative value is -2^kWidth+1. For symmetry
-- reasons the non inverted channel also limits the minimum negative value
-- at -2^kWidth+1.
cDataRaw18bSigned <= "100000000000000001";
else
cDataRaw18bSigned <= signed(cDataRaw18b);
end if;
else
if (cDataRaw18b = "100000000000000000") then
cDataRaw18bSigned <= "011111111111111111";
else
cDataRaw18bSigned <= - signed (cDataRaw18b);
end if;
end if;
end process;
cCoefMultSigned <= signed (cCoefMult);
cCoefAddSigned <= signed (cCoefAdd);
-- Apply the multiplicative coefficient. Register multiplication result.
ProcRegMultResult : process (SamplingClk, acRst_n)
begin
if (acRst_n = '0') then
cCalibMult <= (others => '0');
cDataInValidR <= '0';
elsif (rising_edge(SamplingClk)) then
cCalibMult <= cDataRaw18bSigned * cCoefMultSigned;
--Data out valid flag must be synchronized with its corresponding sample.
cDataInValidR <= cDataInValid;
end if;
end process;
-- Apply additive coefficient.
cCalibAdd <= cCalibMult + cCoefAddSigned;
-- Register calibration result; the calibration output is saturated at
-- 2^kWidth - 1 for positive values or -2^kWidth for negative values;
-- the calibration process is bypassed if cTestMode = '1'.
ProcCalib : process (SamplingClk, acRst_n)
begin
if (acRst_n = '0') then
cCalibDataOut <= (others => '0');
cDataCalibValid <= '0';
elsif (rising_edge(SamplingClk)) then
if (cTestMode = '0') then
if ((cCalibAdd(35) = '1') and (cCalibAdd(34 downto 33) /= "11")) then
cCalibDataOut <= x"8000";
elsif ((cCalibAdd(35) = '0') and (cCalibAdd(34 downto 33) /= "00")) then
cCalibDataOut <= x"7FFF";
else
cCalibDataOut <= std_logic_vector (cCalibAdd(33 downto 18));
end if;
--Data out valid flag must be synchronized with its corresponding sample.
cDataCalibValid <= cDataInValidR;
else
cCalibDataOut <= cDataRaw18b(17 downto 2);
cDataCalibValid <= cDataInValid;
end if;
end if;
end process;
end Behavioral;
|
mit
|
008004a125a02323fc9ef2d096749798
| 0.68259 | 4.623814 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_contrast_stretch_1_0/hdl/vhdl/hls_contrast_stretch_AXILiteS_s_axi.vhd
| 1 | 10,199 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity hls_contrast_stretch_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
-- user signals
height :out STD_LOGIC_VECTOR(15 downto 0);
width :out STD_LOGIC_VECTOR(15 downto 0);
min :out STD_LOGIC_VECTOR(7 downto 0);
max :out STD_LOGIC_VECTOR(7 downto 0)
);
end entity hls_contrast_stretch_AXILiteS_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : reserved
-- 0x04 : reserved
-- 0x08 : reserved
-- 0x0c : reserved
-- 0x10 : Data signal of height
-- bit 15~0 - height[15:0] (Read/Write)
-- others - reserved
-- 0x14 : reserved
-- 0x18 : Data signal of width
-- bit 15~0 - width[15:0] (Read/Write)
-- others - reserved
-- 0x1c : reserved
-- 0x20 : Data signal of min
-- bit 7~0 - min[7:0] (Read/Write)
-- others - reserved
-- 0x24 : reserved
-- 0x28 : Data signal of max
-- bit 7~0 - max[7:0] (Read/Write)
-- others - reserved
-- 0x2c : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of hls_contrast_stretch_AXILiteS_s_axi is
type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states
signal wstate : states := wrreset;
signal rstate : states := rdreset;
signal wnext, rnext: states;
constant ADDR_HEIGHT_DATA_0 : INTEGER := 16#10#;
constant ADDR_HEIGHT_CTRL : INTEGER := 16#14#;
constant ADDR_WIDTH_DATA_0 : INTEGER := 16#18#;
constant ADDR_WIDTH_CTRL : INTEGER := 16#1c#;
constant ADDR_MIN_DATA_0 : INTEGER := 16#20#;
constant ADDR_MIN_CTRL : INTEGER := 16#24#;
constant ADDR_MAX_DATA_0 : INTEGER := 16#28#;
constant ADDR_MAX_CTRL : INTEGER := 16#2c#;
constant ADDR_BITS : INTEGER := 6;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_height : UNSIGNED(15 downto 0) := (others => '0');
signal int_width : UNSIGNED(15 downto 0) := (others => '0');
signal int_min : UNSIGNED(7 downto 0) := (others => '0');
signal int_max : UNSIGNED(7 downto 0) := (others => '0');
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wrreset;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdreset;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_HEIGHT_DATA_0 =>
rdata_data <= RESIZE(int_height(15 downto 0), 32);
when ADDR_WIDTH_DATA_0 =>
rdata_data <= RESIZE(int_width(15 downto 0), 32);
when ADDR_MIN_DATA_0 =>
rdata_data <= RESIZE(int_min(7 downto 0), 32);
when ADDR_MAX_DATA_0 =>
rdata_data <= RESIZE(int_max(7 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
height <= STD_LOGIC_VECTOR(int_height);
width <= STD_LOGIC_VECTOR(int_width);
min <= STD_LOGIC_VECTOR(int_min);
max <= STD_LOGIC_VECTOR(int_max);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_HEIGHT_DATA_0) then
int_height(15 downto 0) <= (UNSIGNED(WDATA(15 downto 0)) and wmask(15 downto 0)) or ((not wmask(15 downto 0)) and int_height(15 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_WIDTH_DATA_0) then
int_width(15 downto 0) <= (UNSIGNED(WDATA(15 downto 0)) and wmask(15 downto 0)) or ((not wmask(15 downto 0)) and int_width(15 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_MIN_DATA_0) then
int_min(7 downto 0) <= (UNSIGNED(WDATA(7 downto 0)) and wmask(7 downto 0)) or ((not wmask(7 downto 0)) and int_min(7 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_MAX_DATA_0) then
int_max(7 downto 0) <= (UNSIGNED(WDATA(7 downto 0)) and wmask(7 downto 0)) or ((not wmask(7 downto 0)) and int_max(7 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
|
mit
|
b8ed531c57ca0313fc92329558cfbd9a
| 0.472497 | 3.8987 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_contrast_stretch_1_0/hdl/vhdl/Block_Mat_exit1573_p.vhd
| 1 | 28,144 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Block_Mat_exit1573_p is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
start_full_n : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
start_out : OUT STD_LOGIC;
start_write : OUT STD_LOGIC;
height : IN STD_LOGIC_VECTOR (15 downto 0);
width : IN STD_LOGIC_VECTOR (15 downto 0);
min : IN STD_LOGIC_VECTOR (7 downto 0);
max : IN STD_LOGIC_VECTOR (7 downto 0);
min_out_din : OUT STD_LOGIC_VECTOR (7 downto 0);
min_out_full_n : IN STD_LOGIC;
min_out_write : OUT STD_LOGIC;
img0_rows_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img0_rows_V_out_full_n : IN STD_LOGIC;
img0_rows_V_out_write : OUT STD_LOGIC;
img0_cols_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img0_cols_V_out_full_n : IN STD_LOGIC;
img0_cols_V_out_write : OUT STD_LOGIC;
img2_rows_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img2_rows_V_out_full_n : IN STD_LOGIC;
img2_rows_V_out_write : OUT STD_LOGIC;
img2_cols_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img2_cols_V_out_full_n : IN STD_LOGIC;
img2_cols_V_out_write : OUT STD_LOGIC;
img3_rows_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img3_rows_V_out_full_n : IN STD_LOGIC;
img3_rows_V_out_write : OUT STD_LOGIC;
img3_cols_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img3_cols_V_out_full_n : IN STD_LOGIC;
img3_cols_V_out_write : OUT STD_LOGIC;
p_cols_assign_cast_out_out_din : OUT STD_LOGIC_VECTOR (11 downto 0);
p_cols_assign_cast_out_out_full_n : IN STD_LOGIC;
p_cols_assign_cast_out_out_write : OUT STD_LOGIC;
p_rows_assign_cast_out_out_din : OUT STD_LOGIC_VECTOR (11 downto 0);
p_rows_assign_cast_out_out_full_n : IN STD_LOGIC;
p_rows_assign_cast_out_out_write : OUT STD_LOGIC;
tmp_3_cast_out_out_din : OUT STD_LOGIC_VECTOR (7 downto 0);
tmp_3_cast_out_out_full_n : IN STD_LOGIC;
tmp_3_cast_out_out_write : OUT STD_LOGIC;
max_out_din : OUT STD_LOGIC_VECTOR (7 downto 0);
max_out_full_n : IN STD_LOGIC;
max_out_write : OUT STD_LOGIC );
end;
architecture behav of Block_Mat_exit1573_p is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
signal real_start : STD_LOGIC;
signal start_once_reg : STD_LOGIC := '0';
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal internal_ap_ready : STD_LOGIC;
signal min_out_blk_n : STD_LOGIC;
signal img0_rows_V_out_blk_n : STD_LOGIC;
signal img0_cols_V_out_blk_n : STD_LOGIC;
signal img2_rows_V_out_blk_n : STD_LOGIC;
signal img2_cols_V_out_blk_n : STD_LOGIC;
signal img3_rows_V_out_blk_n : STD_LOGIC;
signal img3_cols_V_out_blk_n : STD_LOGIC;
signal p_cols_assign_cast_out_out_blk_n : STD_LOGIC;
signal p_rows_assign_cast_out_out_blk_n : STD_LOGIC;
signal tmp_3_cast_out_out_blk_n : STD_LOGIC;
signal max_out_blk_n : STD_LOGIC;
signal ap_block_state1 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
begin
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_continue = ap_const_logic_1)) then
ap_done_reg <= ap_const_logic_0;
elsif ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
start_once_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
start_once_reg <= ap_const_logic_0;
else
if (((internal_ap_ready = ap_const_logic_0) and (real_start = ap_const_logic_1))) then
start_once_reg <= ap_const_logic_1;
elsif ((internal_ap_ready = ap_const_logic_1)) then
start_once_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (real_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_block_state1_assign_proc : process(real_start, ap_done_reg, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
ap_block_state1 <= ((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
ap_done_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
if ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_idle_assign_proc : process(real_start, ap_CS_fsm_state1)
begin
if (((real_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready <= internal_ap_ready;
img0_cols_V_out_blk_n_assign_proc : process(ap_CS_fsm_state1, img0_cols_V_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
img0_cols_V_out_blk_n <= img0_cols_V_out_full_n;
else
img0_cols_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img0_cols_V_out_din <= width;
img0_cols_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
if ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img0_cols_V_out_write <= ap_const_logic_1;
else
img0_cols_V_out_write <= ap_const_logic_0;
end if;
end process;
img0_rows_V_out_blk_n_assign_proc : process(ap_CS_fsm_state1, img0_rows_V_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
img0_rows_V_out_blk_n <= img0_rows_V_out_full_n;
else
img0_rows_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img0_rows_V_out_din <= height;
img0_rows_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
if ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img0_rows_V_out_write <= ap_const_logic_1;
else
img0_rows_V_out_write <= ap_const_logic_0;
end if;
end process;
img2_cols_V_out_blk_n_assign_proc : process(ap_CS_fsm_state1, img2_cols_V_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
img2_cols_V_out_blk_n <= img2_cols_V_out_full_n;
else
img2_cols_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img2_cols_V_out_din <= width;
img2_cols_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
if ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img2_cols_V_out_write <= ap_const_logic_1;
else
img2_cols_V_out_write <= ap_const_logic_0;
end if;
end process;
img2_rows_V_out_blk_n_assign_proc : process(ap_CS_fsm_state1, img2_rows_V_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
img2_rows_V_out_blk_n <= img2_rows_V_out_full_n;
else
img2_rows_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img2_rows_V_out_din <= height;
img2_rows_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
if ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img2_rows_V_out_write <= ap_const_logic_1;
else
img2_rows_V_out_write <= ap_const_logic_0;
end if;
end process;
img3_cols_V_out_blk_n_assign_proc : process(ap_CS_fsm_state1, img3_cols_V_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
img3_cols_V_out_blk_n <= img3_cols_V_out_full_n;
else
img3_cols_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img3_cols_V_out_din <= width;
img3_cols_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
if ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img3_cols_V_out_write <= ap_const_logic_1;
else
img3_cols_V_out_write <= ap_const_logic_0;
end if;
end process;
img3_rows_V_out_blk_n_assign_proc : process(ap_CS_fsm_state1, img3_rows_V_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
img3_rows_V_out_blk_n <= img3_rows_V_out_full_n;
else
img3_rows_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img3_rows_V_out_din <= height;
img3_rows_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
if ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img3_rows_V_out_write <= ap_const_logic_1;
else
img3_rows_V_out_write <= ap_const_logic_0;
end if;
end process;
internal_ap_ready_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
if ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
internal_ap_ready <= ap_const_logic_1;
else
internal_ap_ready <= ap_const_logic_0;
end if;
end process;
max_out_blk_n_assign_proc : process(ap_CS_fsm_state1, max_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
max_out_blk_n <= max_out_full_n;
else
max_out_blk_n <= ap_const_logic_1;
end if;
end process;
max_out_din <= max;
max_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
if ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
max_out_write <= ap_const_logic_1;
else
max_out_write <= ap_const_logic_0;
end if;
end process;
min_out_blk_n_assign_proc : process(ap_CS_fsm_state1, min_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
min_out_blk_n <= min_out_full_n;
else
min_out_blk_n <= ap_const_logic_1;
end if;
end process;
min_out_din <= min;
min_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
if ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
min_out_write <= ap_const_logic_1;
else
min_out_write <= ap_const_logic_0;
end if;
end process;
p_cols_assign_cast_out_out_blk_n_assign_proc : process(ap_CS_fsm_state1, p_cols_assign_cast_out_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
p_cols_assign_cast_out_out_blk_n <= p_cols_assign_cast_out_out_full_n;
else
p_cols_assign_cast_out_out_blk_n <= ap_const_logic_1;
end if;
end process;
p_cols_assign_cast_out_out_din <= width(12 - 1 downto 0);
p_cols_assign_cast_out_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
if ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_cols_assign_cast_out_out_write <= ap_const_logic_1;
else
p_cols_assign_cast_out_out_write <= ap_const_logic_0;
end if;
end process;
p_rows_assign_cast_out_out_blk_n_assign_proc : process(ap_CS_fsm_state1, p_rows_assign_cast_out_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
p_rows_assign_cast_out_out_blk_n <= p_rows_assign_cast_out_out_full_n;
else
p_rows_assign_cast_out_out_blk_n <= ap_const_logic_1;
end if;
end process;
p_rows_assign_cast_out_out_din <= height(12 - 1 downto 0);
p_rows_assign_cast_out_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
if ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_rows_assign_cast_out_out_write <= ap_const_logic_1;
else
p_rows_assign_cast_out_out_write <= ap_const_logic_0;
end if;
end process;
real_start_assign_proc : process(ap_start, start_full_n, start_once_reg)
begin
if (((start_full_n = ap_const_logic_0) and (start_once_reg = ap_const_logic_0))) then
real_start <= ap_const_logic_0;
else
real_start <= ap_start;
end if;
end process;
start_out <= real_start;
start_write_assign_proc : process(real_start, start_once_reg)
begin
if (((start_once_reg = ap_const_logic_0) and (real_start = ap_const_logic_1))) then
start_write <= ap_const_logic_1;
else
start_write <= ap_const_logic_0;
end if;
end process;
tmp_3_cast_out_out_blk_n_assign_proc : process(ap_CS_fsm_state1, tmp_3_cast_out_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
tmp_3_cast_out_out_blk_n <= tmp_3_cast_out_out_full_n;
else
tmp_3_cast_out_out_blk_n <= ap_const_logic_1;
end if;
end process;
tmp_3_cast_out_out_din <= min;
tmp_3_cast_out_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, min_out_full_n, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, tmp_3_cast_out_out_full_n, max_out_full_n)
begin
if ((not(((max_out_full_n = ap_const_logic_0) or (tmp_3_cast_out_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (min_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
tmp_3_cast_out_out_write <= ap_const_logic_1;
else
tmp_3_cast_out_out_write <= ap_const_logic_0;
end if;
end process;
end behav;
|
mit
|
57c27e910cd1100ea95a5261fe0342ae
| 0.627523 | 2.454775 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodAWGController/tb/AD9717_RegisterDecode.vhd
| 1 | 18,623 |
-------------------------------------------------------------------------------
--
-- File: AD9717_RegisterDecode.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodAWG1411_Controller
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module implements the register set for the AD9717 simulation model
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.PkgZmodDAC.all;
entity AD9717_RegisterDecode is
Generic (
-- Parameter identifying the Zmod:
-- 7 -> Zmod AWG 1411 - (AD9717)
kZmodID : integer range 7 to 7 := 7;
-- Register address width
kAddrWidth : integer range 0 to 32 := 5;
-- Register data width: only 8 data bits currently supported
kRegDataWidth : integer range 0 to 32 := 8
);
Port (
-- 100MHZ clock input
SysClk100 : in STD_LOGIC;
-- Reset signal asynchronously asserted and synchronously
-- de-asserted (in SysClk100 domain)
asRst_n : in STD_LOGIC;
-- When InsertError is asserted the model produces an erroneous reading for register address x01
InsertError : in STD_LOGIC;
-- Signal indicating that the data phase of he register write SPI transaction is completed and aDataDecode is valid
sDataWriteDecodeReady : in STD_LOGIC;
-- Signal indicating that the address phase of the SPI transaction is completed and aAddrDecode is valid
sAddrDecodeReady : in STD_LOGIC;
-- Input register data used to update internal egister values for write register operations
sDataDecode : in STD_LOGIC_VECTOR (kRegDataWidth-1 downto 0);
-- Register address input
sAddrDecode : in STD_LOGIC_VECTOR (kAddrWidth-1 downto 0);
-- Output register data produced by this module upon address decode for register read operations
sRegDataOut : out STD_LOGIC_VECTOR (kRegDataWidth-1 downto 0)
);
end AD9717_RegisterDecode;
architecture Behavioral of AD9717_RegisterDecode is
signal sAddrDecodeReadyPulse, sAddrDecodeReadyDly : std_logic := '0';
signal sDataWriteDecodeReadyPulse, sDataWriteDecodeReadyDly : std_logic := '0';
signal sReg00 : std_logic_vector(7 downto 0) := x"00";
signal sReg01 : std_logic_vector(7 downto 0) := x"40";
signal sReg02 : std_logic_vector(7 downto 0) := x"34";
signal sReg03 : std_logic_vector(7 downto 0) := x"00";
signal sReg04 : std_logic_vector(7 downto 0) := x"00";
signal sReg05 : std_logic_vector(7 downto 0) := x"00";
signal sReg06 : std_logic_vector(7 downto 0) := x"00";
signal sReg07 : std_logic_vector(7 downto 0) := x"00";
signal sReg08 : std_logic_vector(7 downto 0) := x"00";
signal sReg09 : std_logic_vector(7 downto 0) := x"00";
signal sReg0A : std_logic_vector(7 downto 0) := x"00";
signal sReg0B : std_logic_vector(7 downto 0) := x"00";
signal sReg0C : std_logic_vector(7 downto 0) := x"00";
signal sReg0D : std_logic_vector(7 downto 0) := x"00";
signal sReg0E : std_logic_vector(7 downto 0) := x"00";
signal sReg0F : std_logic_vector(7 downto 0) := x"00";
signal sReg10 : std_logic_vector(7 downto 0) := x"00";
signal sReg11 : std_logic_vector(7 downto 0) := x"34";
signal sReg12 : std_logic_vector(7 downto 0) := x"00";
signal sReg14 : std_logic_vector(7 downto 0) := x"00";
signal sReg1F : std_logic_vector(7 downto 0) := x"04";
signal sCalstatQ_TimerRst_n, sCalstatI_TimerRst_n : std_logic;
signal sCalstatQ_Timer, sCalstatI_Timer : unsigned (23 downto 0);
signal sSetCalstatQ, sSetCalstatI : std_logic;
signal sAddrAux : integer range 0 to 511;
begin
sAddrAux <= to_integer (unsigned (std_logic_vector'((sAddrDecode))));
-- The following section generates a pulse when sAddrDecodeReady is asserted.
-- This pulse indicates that the command phase of the SPI read transaction is
-- completed and that sAddrDecode contains valid data.
ProcAddrDecodeDly: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sAddrDecodeReadyDly <= '0';
elsif (rising_edge(SysClk100)) then
sAddrDecodeReadyDly <= sAddrDecodeReady;
end if;
end process;
sAddrDecodeReadyPulse <= sAddrDecodeReady and (not sAddrDecodeReadyDly);
-- Process managing register read operations
ReadRegister: process(SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sRegDataOut <= (others => '0');
elsif (rising_edge (SysClk100)) then
if (sAddrDecodeReadyPulse = '1') then
case (sAddrDecode) is
when "00000" =>
sRegDataOut <= sReg00;
when "00001" =>
if (InsertError = '0') then
sRegDataOut <= sReg01;
else
sRegDataOut <= x"00";
end if;
when "00010" =>
sRegDataOut <= sReg02;
when "00011" =>
sRegDataOut <= sReg03;
when "00100" =>
sRegDataOut <= sReg04;
when "00101" =>
sRegDataOut <= sReg05;
when "00110" =>
sRegDataOut <= sReg06;
when "00111" =>
sRegDataOut <= sReg07;
when "01000" =>
sRegDataOut <= sReg08;
when "01001" =>
sRegDataOut <= sReg09;
when "01010" =>
sRegDataOut <= sReg0A;
when "01011" =>
sRegDataOut <= sReg0B;
when "01100" =>
sRegDataOut <= sReg0C;
when "01101" =>
sRegDataOut <= sReg0D;
when "01110" =>
sRegDataOut <= sReg0E;
when "01111" =>
sRegDataOut <= sReg0F;
when "10000" =>
sRegDataOut <= sReg10;
when "10001" =>
sRegDataOut <= sReg11;
when "10010" =>
sRegDataOut <= sReg12;
when "10100" =>
sRegDataOut <= sReg14;
when "11111" =>
sRegDataOut <= sReg1F;
when others =>
sRegDataOut <= x"00";
report "Invalid Read Address." & LF & HT & HT
severity ERROR;
end case;
end if;
end if;
end process ReadRegister;
-- The following section generates a pulse when sDataWriteDecodeReady is asserted.
-- This pulse indicates that the command phase of the SPI write transaction is
-- completed and that sAddrDecode contains valid data.
ProcDataDecodeDly: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sDataWriteDecodeReadyDly <= '0';
elsif (rising_edge(SysClk100)) then
sDataWriteDecodeReadyDly <= sDataWriteDecodeReady;
end if;
end process;
sDataWriteDecodeReadyPulse <= sDataWriteDecodeReady and (not sDataWriteDecodeReadyDly);
-- Process managing register write operations (Reg0F is treated separately).
WriteRegister: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sReg00 <= x"00";
sReg01 <= x"40";
sReg02 <= x"34";
sReg03 <= x"00";
sReg04 <= x"00";
sReg05 <= x"00";
sReg06 <= x"00";
sReg07 <= x"00";
sReg08 <= x"00";
sReg09 <= x"00";
sReg0A <= x"00";
sReg0B <= x"00";
sReg0C <= x"00";
sReg0D <= x"00";
sReg0E(7 downto 6) <= "00";
sReg0E(3 downto 0) <= x"0";
sReg10 <= x"00";
sReg11 <= x"34";
sReg12 <= x"00";
sReg14 <= x"00";
sReg1F <= x"04";
elsif (rising_edge (SysClk100)) then
if (sDataWriteDecodeReadyPulse = '1') then
case (sAddrDecode) is
when "00000" =>
sReg00(7 downto 4) <= sDataDecode(7 downto 4);
when "00001" =>
sReg01 <= sDataDecode;
when "00010" =>
sReg02 <= sDataDecode;
when "00011" =>
sReg03(5 downto 0) <= sDataDecode(5 downto 0);
when "00100" =>
sReg04(7) <= sDataDecode(7);
sReg04(5 downto 0) <= sDataDecode(5 downto 0);
when "00101" =>
sReg05(7) <= sDataDecode(7);
sReg05(5 downto 0) <= sDataDecode(5 downto 0);
when "00110" =>
sReg06(5 downto 0) <= sDataDecode(5 downto 0);
when "00111" =>
sReg07(7) <= sDataDecode(7);
sReg07(5 downto 0) <= sDataDecode(5 downto 0);
when "01000" =>
sReg08(7) <= sDataDecode(7);
sReg08(5 downto 0) <= sDataDecode(5 downto 0);
when "01001" =>
sReg09 <= sDataDecode;
when "01010" =>
sReg0A <= sDataDecode;
when "01011" =>
sReg0B <= sDataDecode;
when "01100" =>
sReg0C <= sDataDecode;
when "01101" =>
sReg0D(5 downto 0) <= sDataDecode(5 downto 0);
when "01110" =>
sReg0E(7 downto 6) <= sDataDecode(7 downto 6);
sReg0E(3 downto 0) <= sDataDecode(3 downto 0);
when "01111" =>
-- sReg0F(7 downto 6) <= sDataDecode(7 downto 6);
-- sReg0F(3 downto 0) <= sDataDecode(3 downto 0);
report "Attempt to write to a READ ONLY location." & integer'image(sAddrAux) & LF & HT & HT
severity ERROR;
when "10000" =>
sReg10(5 downto 0) <= sDataDecode(5 downto 0);
when "10001" =>
sReg11(5 downto 0) <= sDataDecode(5 downto 0);
when "10010" =>
sReg12(7 downto 6) <= sDataDecode(7 downto 6);
sReg12(4 downto 0) <= sDataDecode(4 downto 0);
when "10100" =>
sReg14(7 downto 6) <= sDataDecode(7 downto 6);
sReg14(4 downto 0) <= sDataDecode(4 downto 0);
when "11111" =>
report "Attempt to write to a READ ONLY location." & integer'image(sAddrAux) & LF & HT & HT
severity ERROR;
when others =>
report "Invalid Write Address." & integer'image(sAddrAux) & LF & HT & HT
severity ERROR;
end case;
-- Soft Reset
elsif (sReg00(5) = '1') then
sReg01 <= x"40";
sReg02 <= x"34";
sReg03 <= x"00";
sReg04 <= x"00";
sReg05 <= x"00";
sReg06 <= x"00";
sReg07 <= x"00";
sReg08 <= x"00";
sReg09 <= x"00";
sReg0A <= x"00";
sReg0B <= x"00";
sReg0C <= x"00";
sReg0D <= x"00";
sReg0E(7 downto 6) <= "00";
sReg0E(3 downto 0) <= x"0";
sReg10 <= x"00";
sReg11 <= x"34";
sReg12 <= x"00";
sReg14 <= x"00";
sReg1F <= x"04";
end if;
end if;
end process WriteRegister;
-- Counter used to implement the CALSTATQ bit behavior
ProcCalstatQ_Tmr: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCalstatQ_Timer <= (others => '0');
elsif (rising_edge(SysClk100)) then
if (sCalstatQ_TimerRst_n = '0') then
sCalstatQ_Timer <= (others => '0');
else
sCalstatQ_Timer <= sCalstatQ_Timer + 1;
end if;
end if;
end process;
-- Counter used to implement the CALSTATI bit behavior
ProcCalstatI_Tmr: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCalstatI_Timer <= (others => '0');
elsif (rising_edge(SysClk100)) then
if (sCalstatI_TimerRst_n = '0') then
sCalstatI_Timer <= (others => '0');
else
sCalstatI_Timer <= sCalstatI_Timer + 1;
end if;
end if;
end process;
ProcEnCalstatQ_TmrRst: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCalstatQ_TimerRst_n <= '0';
elsif (rising_edge(SysClk100)) then
if (sReg0E(5) = '1') then
sCalstatQ_TimerRst_n <= '1';
else
sCalstatQ_TimerRst_n <= '0';
end if;
end if;
end process;
ProcEnCalstatI_TmrRst: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCalstatI_TimerRst_n <= '0';
elsif (rising_edge(SysClk100)) then
if (sReg0E(4) = '1') then
sCalstatI_TimerRst_n <= '1';
else
sCalstatI_TimerRst_n <= '0';
end if;
end if;
end process;
-- Configure the CALSELQ bit in the Cal Control register (0x0E)
-- for register write operations.
-- Clear CALSELQ when the Q DAC self-calibration is complete.
WriteReg0E_CALSELQ: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sReg0E(5) <= '0';
elsif (rising_edge (SysClk100)) then
if (sDataWriteDecodeReadyPulse = '1') then
if (sAddrDecode = "01110") then
sReg0E(5) <= sDataDecode(5);
end if;
elsif (sSetCalstatQ = '1') then
sReg0E(5) <= '0';
end if;
end if;
end process;
-- Configure the CALSELI bit in the Cal Control register (0x0E)
-- for register write operations.
-- Clear CALSELQ when the I DAC self-calibration is complete.
WriteReg0E_CALSELI: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sReg0E(4) <= '0';
elsif (rising_edge (SysClk100)) then
if (sDataWriteDecodeReadyPulse = '1') then
if (sAddrDecode = "01110") then
sReg0E(4) <= sDataDecode(5);
end if;
elsif (sSetCalstatI = '1') then
sReg0E(4) <= '0';
end if;
end if;
end process;
-- Manage the CALSTATQ bit in the Cal Memory register (0x0F).
-- Write operations at this address have no effect (except
-- reporting an error).
-- CALSTATQ is set at a predefined interval after the CALSETQ
-- bit in the Cal Control register is set.
-- CALSTATQ is cleared when he CALRSTQ bit in the Memory R/W
-- register (0x12) is set.
WriteReg0F_CALSTATQ: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sReg0F(7) <= '0';
elsif (rising_edge (SysClk100)) then
if (sDataWriteDecodeReadyPulse = '1') then
if (sAddrDecode = "01111") then
report "Attempt to write to a READ ONLY location." & integer'image(sAddrAux) & LF & HT & HT
severity ERROR;
end if;
elsif (sReg12(7) = '1') then
sReg0F(7) <= '0';
elsif (sSetCalstatQ = '1') then
sReg0F(7) <= '1';
end if;
end if;
end process;
-- Manage the CALSTATI bit in the Cal Memory register (0x0F).
-- Write operations at this address have no effect (except
-- reporting an error).
-- CALSTATI is set at a predefined interval after the CALSETI
-- bit in the Cal Control register is set.
-- CALSTATI is cleared when he CALRSTI bit in the Memory R/W
-- register (0x12) is set.
WriteReg0F_CALSTATI: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sReg0F(6) <= '0';
elsif (rising_edge (SysClk100)) then
if (sDataWriteDecodeReadyPulse = '1') then
if (sAddrDecode = "01111") then
report "Attempt to write to a READ ONLY location." & integer'image(sAddrAux) & LF & HT & HT
severity ERROR;
end if;
elsif (sReg12(6) = '1') then
sReg0F(6) <= '0';
elsif (sSetCalstatI = '1') then
sReg0F(6) <= '1';
end if;
end if;
end process;
-- Process used to set CALSTATQ in 300 calibration clock cycles (kCalTimeout) after
-- the self calibration process has been enabled
ProcStCalstatQ: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sSetCalstatQ <= '0';
elsif (rising_edge(SysClk100)) then
if (sCalstatQ_Timer = kCalTimeout) then
sSetCalstatQ <= '1';
else
sSetCalstatQ <= '0';
end if;
end if;
end process;
-- Process used to set CALSTATI in 300 calibration clock cycles (kCalTimeout) after
-- the self calibration process has been enabled
ProcStCalstatI: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sSetCalstatI <= '0';
elsif (rising_edge(SysClk100)) then
if (sCalstatI_Timer = kCalTimeout) then
sSetCalstatI <= '1';
else
sSetCalstatI <= '0';
end if;
end if;
end process;
end Behavioral;
|
mit
|
c94a2d334dd69173596dc8bcbcd5cae4
| 0.567202 | 4.136606 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodAWGController/src/ADI_SPI.vhd
| 1 | 15,890 |
-------------------------------------------------------------------------------
--
-- File: ADI_SPI.vhd
-- Author: Tudor Gherman
-- Original Project: Zmod ADC 1410 Low Level Controller
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module manages the SPI communication with the Analog Devices 3 wire SPI
-- configuration interface
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
use IEEE.math_real.all;
use work.PkgZmodDAC.all;
entity ADI_SPI is
Generic
(
-- The sSPI_Clk signal is obtained by dividing SysClk100 to 2^kSysClkDiv.
kSysClkDiv : integer range 2 to 63 := 4;
-- The number of data bits for the data phase of the transaction:
-- only 8 data bits currently supported.
kDataWidth : integer range 8 to 8 := 8;
-- The number of bits of the command phase of the SPI transaction.
kCommandWidth : integer range 8 to 16 := 16
);
Port (
-- input clock (100MHZ).
SysClk100 : in STD_LOGIC;
-- active low synchronous reset signal.
asRst_n : in STD_LOGIC;
--AD92xx/AD96xx SPI interface signals.
sSPI_Clk : out STD_LOGIC;
sSDIO : inout STD_LOGIC;
sCS : out STD_LOGIC := '1';
--Upper layer Interface signals
--a pulse on this input initiates the transfers, also used to register upper layer interface inputs.
sApStart : in STD_LOGIC;
--SPI read data output.
sRdData : out std_logic_vector(kDataWidth - 1 downto 0);
--SPI command data.
sWrData : in std_logic_vector(kDataWidth - 1 downto 0);
--SPI command register address.
sAddr : in std_logic_vector(kCommandWidth - 4 downto 0);
--Number of data bytes + 1; not currently used (for future development).
sWidth : in std_logic_vector(1 downto 0);
--Select between Read/Write operations.
sRdWr : in STD_LOGIC;
--A pulse is generated on this output once the SPI transfer is successfully completed.
sDone : out STD_LOGIC;
--Busy flag; sApStart ignored while this signal is asserted .
sBusy : out STD_LOGIC);
end ADI_SPI;
architecture Behavioral of ADI_SPI is
function MAX(In1 : integer; In2 : integer)
return integer is
begin
if (In1 > In2) then
return In1;
else
return In2;
end if;
end function;
constant kZeros : unsigned (kSysClkDiv - 1 downto 0) := (others => '0');
constant kOnes : unsigned (kSysClkDiv - 1 downto 0) := (others => '1');
signal sClkCounter : unsigned(kSysClkDiv - 1 downto 0) := (others => '0');
signal sSPI_ClkRst: std_logic;
signal sRdDataR : std_logic_vector(kDataWidth - 1 downto 0);
signal sTxVector : std_logic_vector (kDataWidth + kCommandWidth - 1 downto 0);
signal sRxData : std_logic;
signal sTxData : std_logic := '0';
signal sTxShift, sRxShift : std_logic;
signal sLdTx : std_logic;
signal sApStartR, sApStartPulse : std_logic;
constant kCounterMax : integer := MAX((kDataWidth + kCommandWidth + 1), kCS_PulseWidthHigh);
constant kCounterNumBits : integer := integer(ceil(log2(real(kCounterMax))));
signal sCounter : unsigned (kCounterNumBits-1 downto 0);
signal sCounterInt : integer range 0 to (2**kCounterNumBits-1);
signal sCntRst_n, sTxCntEn, sRxCntEn, sDoneCntEn : std_logic := '0';
signal sBitCount : integer range 0 to kDataWidth; --Maximum 4 byte transfers for Analog Devices 2 Wire SPI
signal sDir : std_logic := '0';
signal sDirFsm : std_logic;
signal sCS_Fsm : std_logic;
signal sDoneFsm : std_logic;
signal sBusyFsm : std_logic;
signal sCurrentState : FsmStatesSPI_t := StIdle;
signal sNextState : FsmStatesSPI_t;
-- signals used for debug purposes
-- signal fsm_state, fsm_state_r : std_logic_vector(3 downto 0);
signal kHalfScale : unsigned (kSysClkDiv - 1 downto 0);
begin
kHalfScale <= '1' & kZeros(kSysClkDiv - 2 downto 0);
------------------------------------------------------------------------------------------
-- SPI interface signal assignment
------------------------------------------------------------------------------------------
InstIOBUF : IOBUF -- instantiate SDIO three state output buffer.
generic map (
DRIVE => 12,
IOSTANDARD => "LVCMOS18",
SLEW => "SLOW")
port map (
O => sRxData, -- Buffer output
IO => sSDIO, -- Buffer inout port (connect directly to top-level port)
I => sTxData, -- Buffer input
T => sDir -- 3-state enable input, high=input, low=output
);
-- Three state buffer direction control register.
ProcDir: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sDir <= '0';
elsif (rising_edge(SysClk100)) then
if (sLdTx = '1') then
sDir <= sDirFsm;
else
if ((sClkCounter = kOnes) or (sCS_Fsm = '1')) then
sDir <= sDirFsm;
end if;
end if;
end if;
end process;
ProcRegCS: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCS <= '1';
--fsm_state_r <= (others => '0');
elsif (rising_edge (SysClk100)) then
sCS <= sCS_Fsm;
--fsm_state_r <= fsm_state;
end if;
end process;
sSPI_Clk <= sClkCounter(kSysClkDiv - 1 );
------------------------------------------------------------------------------------------
-- Input clock frequency divider
------------------------------------------------------------------------------------------
ProcClkCounter: process (SysClk100, asRst_n) --clock frequency divider
begin
if (asRst_n = '0') then
sClkCounter <= (others => '0');
elsif (rising_edge(SysClk100)) then
if (sSPI_ClkRst = '1') then
sClkCounter <= (others => '0');
else
sClkCounter <= sClkCounter + 1;
end if;
end if;
end process;
------------------------------------------------------------------------------------------
-- Transmit logic
------------------------------------------------------------------------------------------
sBitCount <= kDataWidth;
ProcApStartReg: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sApStartR <= '0';
elsif (rising_edge(SysClk100)) then
sApStartR <= sApStart;
end if;
end process;
sApStartPulse <= sApStart and (not sApStartR);
ProcShiftTx: process (SysClk100, asRst_n) --Transmit shift register
begin
if (asRst_n = '0') then
sTxVector <= (others => '0');--sRdWr & "00" & sAddr & sWrData;
sTxData <= '0';
elsif (rising_edge(SysClk100)) then
if (sApStartPulse = '1') then
--sTxVector <= sRdWr & sWidth & sAddr & sWrData;
sTxVector <= sRdWr & "00" & sAddr & sWrData;
sTxData <= '0';
else
if(sTxShift = '1') then
--data is placed on the falling edge (sClkCounter = kZeros) of sSPI_Clk for the transmit phase.
if ((sClkCounter = kZeros) and (sCounterInt <= kDataWidth+kCommandWidth)) then
sTxVector(kDataWidth + kCommandWidth - 1 downto 0) <= sTxVector(kDataWidth + kCommandWidth - 2 downto 0) & '0';
sTxData <= sTxVector(kDataWidth + kCommandWidth - 1);
elsif (sCounterInt > kDataWidth+kCommandWidth) then
sTxData <= '0';
end if;
else
sTxData <= '0';
end if;
end if;
end if;
end process;
ProcTxCount: process (asRst_n, sTxShift, sLdTx, sClkCounter) --Transmit bit count
begin
if ((asRst_n = '0') or (sLdTx = '1')) then
sTxCntEn <= '0';
else
if(sTxShift = '1') then
--The TX bit count incremented on the falling edge of the sSPI_Clk (sClkCounter = kZeros).
if (sClkCounter = kZeros) then
sTxCntEn <= '1';
else
sTxCntEn <= '0';
end if;
else
sTxCntEn <= '0';
end if;
end if;
end process;
------------------------------------------------------------------------------------------
-- Receive logic
------------------------------------------------------------------------------------------
-- Receive deserializer.
ProcShiftRx: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sRdDataR <= (others =>'0');
elsif (rising_edge(SysClk100)) then
if (sRxShift = '0') then
sRdDataR <= (others =>'0');
else
if ((sRxShift = '1') and (sClkCounter = kHalfScale)) then
--The read data is sampled on the rising edge of the sSPI_Clk (sClkCounter = kHalfScale).
sRdDataR(kDataWidth - 1 downto 0) <= sRdDataR(kDataWidth - 2 downto 0) & sRxData;
end if;
end if;
end if;
end process;
ProcRxCount: process (asRst_n, sRxShift, sClkCounter, kHalfScale) --Receive bit count
begin
if ((asRst_n = '0') or (sRxShift = '0')) then
sRxCntEn <= '0';
else
if (sRxShift = '1') then
--The RX bit count is incremented on the rising edge of the sSPI_Clk (sClkCounter = kHalfScale).
if (sClkCounter = kHalfScale) then
sRxCntEn <= '1';
else
sRxCntEn <= '0';
end if;
else
sRxCntEn <= '0';
end if;
end if;
end process;
-- Register SPI read data once read instruction is completed.
ProcRdData: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sRdData <= (others => '0');
sDone <= '0';
elsif (rising_edge (SysClk100)) then
sDone <= sDoneFsm;
if (sDoneFsm = '1') then
sRdData <= sRdDataR;
end if;
end if;
end process;
ProcBusy: process (SysClk100, asRst_n) --register sBusyFsm output
begin
if (asRst_n = '0') then
sBusy <= '1';
elsif (rising_edge (SysClk100)) then
sBusy <= sBusyFsm;
end if;
end process;
--Counter used by both transmit and receive logic; sCS minimum pulse width high is also timed by this counter.
ProcCounter: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCounter <= (others => '0');
elsif (rising_edge(SysClk100)) then
if (sCntRst_n = '0') then
sCounter <= (others => '0');
else
if ((sTxCntEn = '1') or (sRxCntEn = '1') or (sDoneCntEn = '1')) then
sCounter <= sCounter + 1;
end if;
end if;
end if;
end process;
sCounterInt <= to_integer (sCounter);
------------------------------------------------------------------------------------------
-- SPI State Machine
------------------------------------------------------------------------------------------
ProcFsmSync: process (SysClk100, asRst_n) --State machine synchronous process
begin
if (asRst_n = '0') then
sCurrentState <= StIdle;
elsif (rising_edge (SysClk100)) then
sCurrentState <= sNextState;
end if;
end process;
--Next State decode logic
ProcNextStateAndOutputDecode: process (sCurrentState, sApStart, sRdWr, sCounterInt, sClkCounter, sBitCount)
begin
sNextState <= sCurrentState;
sDirFsm <= '0';
sCS_Fsm <= '1';
sDoneFsm <= '0';
sRxShift <= '0';
sTxShift <= '0';
--fsm_state <= (others => '0');
sLdTx <= '0';
sSPI_ClkRst <= '1';
sCntRst_n <= '0';
sDoneCntEn <= '0';
sBusyFsm <= '1';
case (sCurrentState) is
when StIdle =>
--fsm_state <= "0000";
sBusyFsm <= '0';
sLdTx <= '1';
if (sApStart = '1') then
if (sRdWr = '1') then
sNextState <= StRead1;
else
sNextState <= StWrite;
end if;
end if;
when StRead1 => --send command bytes
--fsm_state <= "0001";
sCS_Fsm <= '0';
sTxShift <= '1';
sSPI_ClkRst <= '0';
sCntRst_n <= '1';
if (sCounterInt = kCommandWidth) then
sDirFsm <= '1';
sNextState <= StRead2;
end if;
when StRead2 => --send last command bit; change three state buffer direction
--fsm_state <= "0010";
sDirFsm <= '1';
sCS_Fsm <= '0';
sTxShift <= '1';
sSPI_ClkRst <= '0';
sCntRst_n <= '1';
if (sCounterInt = kCommandWidth + 1) then
sNextState <= StRead3;
sCntRst_n <= '0';
end if;
when StRead3 => --receive register read data
--fsm_state <= "0011";
sDirFsm <= '1';
sCS_Fsm <= '0';
sRxShift <= '1';
sSPI_ClkRst <= '0';
sCntRst_n <= '1';
if ((sCounterInt = sBitCount) and (sClkCounter = kOnes + 1)) then
--this condition assures a sSPI_Clk pulse width low of 2 SysClk100 cycles for last data bit
sCntRst_n <= '0';
sDirFsm <= '0';
sNextState <= StDone;
end if;
when StWrite => --send SPI command and register data
--fsm_state <= "0100";
sCS_Fsm <= '0';
sTxShift <= '1';
sSPI_ClkRst <= '0';
sCntRst_n <= '1';
if (sCounterInt = (sBitCount + kCommandWidth + 1)) then
sSPI_ClkRst <= '1';
sNextState <= StDone;
end if;
when StDone => --signal SPI instruction complete
--fsm_state <= "0101";
sDoneFsm <= '1';
sNextState <= StAssertCS;
when StAssertCS => --hold CS high for at least kCS_PulseWidthHigh SysClk100 cycles
--fsm_state <= "0111";
sCntRst_n <= '1';
sDoneCntEn <= '1';
if (sCounterInt = kCS_PulseWidthHigh) then
sNextState <= StIdle;
end if;
when others =>
--fsm_state <= (others => '1');
sNextState <= StIdle;
end case;
end process;
end Behavioral;
|
mit
|
aff36f269f8d299035c9dc58002b9823
| 0.550031 | 4.460977 | false | false | false | false |
scottlbaker/Nova-SOC
|
src/outport.vhd
| 2 | 1,471 |
--======================================================================
-- outport.vhd :: Digital Output Port
--
-- (c) Scott L. Baker, Sierra Circuit Design
--======================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity OUTPORT is
port(
CS : in std_logic; -- chip select
WE : in std_logic; -- write enable
WR_DATA : in std_logic_vector(7 downto 0); -- data in
RD_DATA : out std_logic_vector(7 downto 0); -- data out
RESET : in std_logic; -- system reset
FCLK : in std_logic -- fast clock
);
end entity OUTPORT;
architecture BEHAVIORAL of OUTPORT is
--=================================================================
-- Signal definitions
--=================================================================
signal OREG : std_logic_vector( 7 downto 0); -- output reg
begin
--=============================================
-- Output Register
--=============================================
OUTPUT_REG:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
if (CS = '1' and WE = '1') then
OREG <= WR_DATA;
end if;
if (RESET = '1') then
OREG <= (others => '0');
end if;
end if;
end process;
RD_DATA <= OREG;
end architecture BEHAVIORAL;
|
gpl-3.0
|
2aa18a9a6406aa72d7df8f37f45330fd
| 0.380693 | 4.729904 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_contrast_stretch_1_0/hdl/vhdl/hls_contrast_streibs.vhd
| 1 | 2,145 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hls_contrast_streibs_DSP48_6 is
port (
in0: in std_logic_vector(8 - 1 downto 0);
in1: in std_logic_vector(23 - 1 downto 0);
in2: in std_logic_vector(32 - 1 downto 0);
dout: out std_logic_vector(32 - 1 downto 0));
end entity;
architecture behav of hls_contrast_streibs_DSP48_6 is
signal a : signed(25-1 downto 0);
signal b : signed(18-1 downto 0);
signal c : signed(48-1 downto 0);
signal m : signed(43-1 downto 0);
signal p : signed(48-1 downto 0);
begin
a <= signed(resize(signed(in1), 25));
b <= signed(resize(signed(in0), 18));
c <= signed(resize(signed(in2), 48));
m <= a * b;
p <= m + c;
dout <= std_logic_vector(resize(unsigned(p), 32));
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity hls_contrast_streibs is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
din2 : IN STD_LOGIC_VECTOR(din2_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of hls_contrast_streibs is
component hls_contrast_streibs_DSP48_6 is
port (
in0 : IN STD_LOGIC_VECTOR;
in1 : IN STD_LOGIC_VECTOR;
in2 : IN STD_LOGIC_VECTOR;
dout : OUT STD_LOGIC_VECTOR);
end component;
begin
hls_contrast_streibs_DSP48_6_U : component hls_contrast_streibs_DSP48_6
port map (
in0 => din0,
in1 => din1,
in2 => din2,
dout => dout);
end architecture;
|
mit
|
1e6dbede7e76f71aa2aa414a0534bbad
| 0.569231 | 3.351563 | false | false | false | false |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx
|
Frecuencimentro/SalidaPrePresentacion_TB.vhd
| 2 | 2,746 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:49:41 01/18/2015
-- Design Name:
-- Module Name: C:/Users/Angel LM/Documents/Frecuencimetroo/Frecuencimentro/SalidaPrePresentacion_TB.vhd
-- Project Name: Frecuencimentro
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: EscaladoPrePresentacion
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY SalidaPrePresentacion_TB IS
END SalidaPrePresentacion_TB;
ARCHITECTURE behavior OF SalidaPrePresentacion_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT EscaladoPrePresentacion
PORT(
entrada_frec : IN std_logic_vector(0 to 31);
salida_frec : OUT std_logic_vector(15 downto 0);
salida_uds : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
--Inputs
signal entrada_frec : std_logic_vector(0 to 31) := (others => '0');
--Outputs
signal salida_frec : std_logic_vector(15 downto 0);
signal salida_uds : std_logic_vector(2 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: EscaladoPrePresentacion PORT MAP (
entrada_frec => entrada_frec,
salida_frec => salida_frec,
salida_uds => salida_uds
);
-- Clock process definitions
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
entrada_frec<="00000000000000000000000000000010"; -- 4
--wait for 100 ns;
-- entrada_frec<="00000000000000000001111100101101"; -- 7981
--wait for 100 ns;
--entrada_frec<="00000100110000011111000000001101"; -- 79818765
--wait for 100 ns;
-- entrada_frec<="01101100011010000010100111000101"; -- 1818765765
-- insert stimulus here
wait;
end process;
END;
|
gpl-2.0
|
02a352ed27a6c3db8be04c25f17df85a
| 0.621267 | 4.263975 | false | true | false | false |
hangmann/fpga-heater
|
heat_core_v1_00_a/hdl/vhdl/heat_core.vhd
| 1 | 11,704 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library heat_core_v1_00_a;
use heat_core_v1_00_a.user_logic;
entity heat_core is
generic
(
C_NUM_LUTS : integer := 1000;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 1;
C_FAMILY : string := "virtex5"
);
port
(
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity heat_core;
architecture IMP of heat_core is
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR,
ZERO_ADDR_PAD & USER_SLV_HIGHADDR
);
constant USER_SLV_NUM_REG : integer := 8;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG)
);
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
USER_LOGIC_I : entity heat_core_v1_00_a.user_logic
generic map
(
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG,
C_NUM_LUTS => C_NUM_LUTS
)
port map
(
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
|
mit
|
5e55d611b6390df1ddf0b73954297e3d
| 0.45745 | 3.756098 | false | false | false | false |
Digilent/vivado-library
|
ip/MIPI_CSI_2_RX/hdl/ECC.vhd
| 1 | 6,740 |
-------------------------------------------------------------------------------
--
-- File: ECC.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI CSI-2 Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
-- Description: The error correcting code used is a 7+1bits Hamming-modified
-- code (72,64) and the subset of it is 5+1bits or (30,24).
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ECC is
Port (
StreamClk : in std_logic;
sHeaderIn : in std_logic_vector(31 downto 0);
sCE : in std_logic;
sReady : out std_logic;
sHeaderOut : out std_logic_vector(31 downto 0);
sValid: out std_logic; --asserted for one cycle when ECC processing is done and correct data is present on sHeaderOut
sError: out std_logic; --asserted for one cycle when ECC processing detected an error
sRst : in std_logic
);
end ECC;
architecture Behavioral of ECC is
type bit_parity is array ( 0 to 23 ) of std_logic_vector(7 downto 0);
constant syndrome : bit_parity := ( "00000111", "00001011", "00001101", "00001110", "00010011", "00010101", "00010110", "00011001",
"00011010", "00011100", "00100011", "00100101", "00100110", "00101001", "00101010", "00101100",
"00110001", "00110010", "00110100", "00111000", "00011111", "00101111", "00110111", "00111011");
type state_type is (stReset, stIdle, stGenParity, stCorrect);
signal sState, sNstate : state_type;
signal sProcessing : std_logic;
signal sDataIn : std_logic_vector(23 downto 0); --24-bit data
signal sECCIn, sParity, sErrSyndrome : std_logic_vector(5 downto 0); --6-bit ECC
begin
sReady <= '1' when sState = stIdle else
'0';
InputRegister: process(StreamClk)
begin
if Rising_Edge(StreamClk) then
if (sState = stIdle and sCE = '1') then
sECCIn <= sHeaderIn(29 downto 24);
sDataIn <= sHeaderIn(23 downto 0);
end if;
end if;
end process;
-- The syndrome table is used to determine which bits of data participate in
-- each parity bit. There are 24 syndromes, one for each data bit. Each syndrome
-- encodes which parity bits does the data bit participate in. For example,
-- syndrome(0)=00000111 means that sDataIn(0) and many other data bits are XOR'd
-- together to calculate parity(2), parity(1) and parity(0) (where the syndrome
-- bits are 1).
ParityGen: process(StreamClk)
variable parity : std_logic_vector(sParity'range);
begin
if Rising_Edge(StreamClk) then
if (sState = stGenParity) then
parity := (others => '0');
for iP in 0 to 5 loop
for iD in 0 to 23 loop
if (syndrome(iD)(iP) = '1') then
parity(iP) := parity(iP) xor sDataIn(iD);
end if;
end loop;
end loop;
sParity <= parity;
sErrSyndrome <= parity xor sECCIn;
end if;
end if;
end process;
Correction: process(StreamClk)
begin
if Rising_Edge(StreamClk) then
if (sState = stCorrect) then
sValid <= '0'; sError <= '1'; -- unrecoverable error
sHeaderOut <= "00" & sErrSyndrome & sDataIn; -- debug output
case (sErrSyndrome) is
when "000000" => --no error
sHeaderOut <= "00" & sECCIn & sDataIn;
sValid <= '1'; sError <= '0';
when "000001" | "000010" | "000100" | "001000" | "010000" | "100000" =>
--if error syndrome only has one bit set, it indicates that the ECC is incorrect
sHeaderOut <= "00" & (sECCIn xor sErrSyndrome) & sDataIn; --flip the bit
sValid <= '1'; sError <= '1';
when others =>
--error in data, try to correct
for iD in 0 to 23 loop
-- if error syndrome matches a value in the syndrome matrix, the
-- corresponding data bit is incorrect
if (syndrome(iD)(5 downto 0) = sErrSyndrome) then
sHeaderOut <= "00" & sECCIn & sDataIn;
sHeaderOut(iD) <= not sDataIn(iD);
sValid <= '1'; sError <= '1';
end if;
end loop;
end case;
else --sState/=stCorrect
sValid <= '0'; sError <= '0';
end if;
end if;
end process;
SYNC_PROC: process (StreamClk)
begin
if Rising_Edge(StreamClk) then
if (sRst = '1') then
sState <= stReset;
else
sState <= sNstate;
end if;
end if;
end process;
NEXT_STATE_DECODE: process (sState, sCE)
begin
sNstate <= sState; --default is to stay in current sState
case (sState) is
when stReset =>
sNstate <= stIdle;
when stIdle =>
if (sCE = '1') then
sNstate <= stGenParity;
end if;
when stGenParity => -- calculate all parity bits
sNstate <= stCorrect;
when stCorrect => -- compare ECC, calculate error syndrome and correct data, if possible
sNstate <= stIdle;
when others =>
sNstate <= stReset;
end case;
end process;
end Behavioral;
|
mit
|
e563db26a68b9a100afe36c89eaaa6b4
| 0.601187 | 4.317745 | false | false | false | false |
EJDomi/pixel-dtb-firmware-readout-chain-master
|
dtb/lpm_mux2.vhd
| 1 | 3,886 |
-- megafunction wizard: %LPM_MUX%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_MUX
-- ============================================================
-- File Name: lpm_mux2.vhd
-- Megafunction Name(s):
-- LPM_MUX
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY lpm_mux2 IS
PORT
(
data0 : IN STD_LOGIC ;
data1 : IN STD_LOGIC ;
sel : IN STD_LOGIC ;
result : OUT STD_LOGIC
);
END lpm_mux2;
ARCHITECTURE SYN OF lpm_mux2 IS
-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
sub_wire4 <= data0;
sub_wire1 <= sub_wire0(0);
result <= sub_wire1;
sub_wire2 <= data1;
sub_wire3(1, 0) <= sub_wire2;
sub_wire3(0, 0) <= sub_wire4;
sub_wire5 <= sel;
sub_wire6(0) <= sub_wire5;
LPM_MUX_component : LPM_MUX
GENERIC MAP (
lpm_size => 2,
lpm_type => "LPM_MUX",
lpm_width => 1,
lpm_widths => 1
)
PORT MAP (
data => sub_wire3,
sel => sub_wire6,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
-- Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL "data0"
-- Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL "data1"
-- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL "result"
-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
-- Retrieval info: CONNECT: @data 1 0 1 0 data0 0 0 0 0
-- Retrieval info: CONNECT: @data 1 1 1 0 data1 0 0 0 0
-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
-- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
unlicense
|
ad274a5720f411ae6828d3f843a5e367
| 0.63227 | 3.438938 | false | false | false | false |
EJDomi/pixel-dtb-firmware-readout-chain-master
|
dtb/lpm_shiftreg1.vhd
| 1 | 4,495 |
-- megafunction wizard: %LPM_SHIFTREG%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_SHIFTREG
-- ============================================================
-- File Name: lpm_shiftreg1.vhd
-- Megafunction Name(s):
-- LPM_SHIFTREG
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_shiftreg1 IS
PORT
(
clock : IN STD_LOGIC ;
shiftin : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
shiftout : OUT STD_LOGIC
);
END lpm_shiftreg1;
ARCHITECTURE SYN OF lpm_shiftreg1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
COMPONENT lpm_shiftreg
GENERIC (
lpm_direction : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
shiftin : IN STD_LOGIC ;
shiftout : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
shiftout <= sub_wire1;
LPM_SHIFTREG_component : LPM_SHIFTREG
GENERIC MAP (
lpm_direction => "LEFT",
lpm_type => "LPM_SHIFTREG",
lpm_width => 8
)
PORT MAP (
clock => clock,
shiftin => shiftin,
q => sub_wire0,
shiftout => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LeftShift NUMERIC "1"
-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
-- Retrieval info: PRIVATE: Q_OUT NUMERIC "1"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "8"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL "shiftin"
-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL "shiftout"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
unlicense
|
f315066810a2071a4fa94cca0de7f6fe
| 0.654727 | 3.714876 | false | false | false | false |
olajep/oh
|
src/adi/hdl/library/common/axi_ctrlif.vhd
| 1 | 5,024 |
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
--
-- In this HDL repository, there are many different and unique modules, consisting
-- of various HDL (Verilog or VHDL) components. The individual modules are
-- developed independently, and may be accompanied by separate and unique license
-- terms.
--
-- The user should read each of these license terms, and understand the
-- freedoms and responsibilities that he or she has by using this source/core.
--
-- This core is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-- A PARTICULAR PURPOSE.
--
-- Redistribution and use of source or resulting binaries, with or without modification
-- of this file, are permitted under one of the following two license terms:
--
-- 1. The GNU General Public License version 2 as published by the
-- Free Software Foundation, which can be found in the top level directory
-- of this repository (LICENSE_GPL2), and also online at:
-- <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
--
-- OR
--
-- 2. An ADI specific BSD license, which can be found in the top level directory
-- of this repository (LICENSE_ADIBSD), and also on-line at:
-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
-- This will allow to generate bit files and not release the source code,
-- as long as it attaches to an ADI device.
--
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_ctrlif is
generic
(
C_NUM_REG : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_FAMILY : string := "virtex6"
);
port
(
-- AXI bus interface
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_rready : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_awready : out std_logic;
rd_addr : out integer range 0 to C_NUM_REG - 1;
rd_data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
rd_ack : out std_logic;
rd_stb : in std_logic;
wr_addr : out integer range 0 to C_NUM_REG - 1;
wr_data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
wr_ack : in std_logic;
wr_stb : out std_logic
);
end entity axi_ctrlif;
architecture Behavioral of axi_ctrlif is
type state_type is (IDLE, RESP, ACK);
signal rd_state : state_type;
signal wr_state : state_type;
begin
process (s_axi_aclk)
begin
if rising_edge(s_axi_aclk) then
if s_axi_aresetn = '0' then
rd_state <= IDLE;
else
case rd_state is
when IDLE =>
if s_axi_arvalid = '1' then
rd_state <= RESP;
rd_addr <= to_integer(unsigned(s_axi_araddr((C_S_AXI_ADDR_WIDTH-1) downto 2)));
end if;
when RESP =>
if rd_stb = '1' and s_axi_rready = '1' then
rd_state <= IDLE;
end if;
when others => null;
end case;
end if;
end if;
end process;
s_axi_arready <= '1' when rd_state = IDLE else '0';
s_axi_rvalid <= '1' when rd_state = RESP and rd_stb = '1' else '0';
s_axi_rresp <= "00";
rd_ack <= '1' when rd_state = RESP and s_axi_rready = '1' else '0';
s_axi_rdata <= rd_data;
process (s_axi_aclk)
begin
if rising_edge(s_axi_aclk) then
if s_axi_aresetn = '0' then
wr_state <= IDLE;
else
case wr_state is
when IDLE =>
if s_axi_awvalid = '1' and s_axi_wvalid = '1' and wr_ack = '1' then
wr_state <= ACK;
end if;
when ACK =>
wr_state <= RESP;
when RESP =>
if s_axi_bready = '1' then
wr_state <= IDLE;
end if;
end case;
end if;
end if;
end process;
wr_stb <= '1' when s_axi_awvalid = '1' and s_axi_wvalid = '1' and wr_state = IDLE else '0';
wr_data <= s_axi_wdata;
wr_addr <= to_integer(unsigned(s_axi_awaddr((C_S_AXI_ADDR_WIDTH-1) downto 2)));
s_axi_awready <= '1' when wr_state = ACK else '0';
s_axi_wready <= '1' when wr_state = ACK else '0';
s_axi_bresp <= "00";
s_axi_bvalid <= '1' when wr_state = RESP else '0';
end;
|
mit
|
89363297229241b047e5b05a07043d9b
| 0.606887 | 2.946628 | false | false | false | false |
grafi-tt/Maizul
|
src/Unit/ALU.vhd
| 1 | 3,369 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;
entity ALU is
port (
clk : in std_logic;
code : in std_logic_vector(3 downto 0);
tagD : in tag_t;
valA : in value_t;
valB : in value_t;
emitTag : out tag_t := (others => '0');
emitVal : out value_t);
end ALU;
architecture twoproc of ALU is
signal c : std_logic_vector(3 downto 0) := "0000";
signal s : value_t := (others => '0');
signal t : value_t := (others => '0');
function boolean_value(b : boolean) return value_t;
function boolean_value(b : boolean) return value_t is
constant z31 : std_logic_vector(31 downto 1) := (others => '0');
begin
if b then
return z31 & '1';
else
return z31 & '0';
end if;
end boolean_value;
begin
sequential : process(clk)
begin
if rising_edge(clk) then
c <= code;
emitTag <= tagD;
s <= valA;
t <= valB;
end if;
end process;
combinatorial : process(c, s, t)
variable d_add, d_sub, d_xor, d_and, d_or, d_sll, d_srl, d_sra, d_cat, d_mul : value_t;
variable d_eq, d_lt, d_feq, d_flt : boolean;
variable tmp_lt, tmp_z_s, tmp_z_t : boolean;
begin
d_add := std_logic_vector(unsigned(s) + unsigned(t));
d_sub := std_logic_vector(unsigned(s) - unsigned(t));
tmp_lt := unsigned(s(30 downto 0)) < unsigned(t(30 downto 0));
tmp_z_s := unsigned(s(30 downto 0)) = 0;
tmp_z_t := unsigned(t(30 downto 0)) = 0;
d_eq := s = t;
d_lt := (s(31) = '1' and t(31) = '0') or (s(31) = t(31) and tmp_lt);
d_and := s and t;
d_xor := s xor t;
d_or := s or t;
d_sll := std_logic_vector(shift_left(unsigned(s), to_integer(unsigned(t(4 downto 0)))));
d_srl := std_logic_vector(shift_right(unsigned(s), to_integer(unsigned(t(4 downto 0)))));
d_sra := std_logic_vector(shift_right(signed(s), to_integer(unsigned(t(4 downto 0)))));
d_cat := t(15 downto 0) & s(15 downto 0);
d_mul := value_t((unsigned(s(15 downto 0)) * unsigned(t(15 downto 0))));
d_feq := d_eq or (tmp_z_s and tmp_z_t);
d_flt := not d_feq and
( (s(31) = '1' and t(31) = '0') or
(s(31) = '0' and t(31) = '0' and tmp_lt) or
(s(31) = '1' and t(31) = '1' and not tmp_lt));
case c is
when "0000" => emitVal <= d_add;
when "0001" => emitVal <= d_sub;
when "0010" => emitVal <= boolean_value(d_eq);
when "0011" => emitVal <= boolean_value(d_lt);
when "0100" => emitVal <= d_and;
when "0101" => emitVal <= d_or;
when "0110" => emitVal <= d_xor;
when "0111" => emitVal <= d_sll;
when "1000" => emitVal <= d_srl;
when "1001" => emitVal <= d_sra;
when "1010" => emitVal <= d_cat;
when "1011" => emitVal <= d_mul;
when "1100" => emitVal <= s;
when "1101" => assert(false); emitVal <= s;
when "1110" => emitVal <= boolean_value(d_feq);
when "1111" => emitVal <= boolean_value(d_flt);
when others => assert false;
end case;
end process;
end twoproc;
|
bsd-2-clause
|
5f49d17fdd87e8fdb7ffb7dc5db29bbc
| 0.500742 | 3.208571 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
serial_addition/full_adder.vhd
| 1 | 947 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity full_adder is
Port (
a : in std_logic;
b : in std_logic;
c_in : in std_logic;
sum : out std_logic;
c_out : out std_logic;
for_augend : out std_logic;
for_addend : out std_logic;
for_c_in : out std_logic;
for_c_out : out std_logic;
for_sum : out std_logic
);
end full_adder;
architecture Behavioral of full_adder is
signal s1, s2 ,s3: std_logic;
begin
s1 <= a xor b;
s2 <= c_in and s1;
s3 <= a and b;
sum <= s1 xor c_in;
c_out <= s2 or s3;
for_augend <= a;
for_addend <= b;
for_c_in <= c_in;
for_c_out <= s2 or s3;
for_sum <= s1 xor c_in;
end Behavioral;
|
mit
|
e72c0202bbb3b4ccdc44068583f3669b
| 0.615628 | 2.68272 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/CvtColor.vhd
| 1 | 152,127 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CvtColor is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_src_rows_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
p_src_rows_V_empty_n : IN STD_LOGIC;
p_src_rows_V_read : OUT STD_LOGIC;
p_src_cols_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
p_src_cols_V_empty_n : IN STD_LOGIC;
p_src_cols_V_read : OUT STD_LOGIC;
p_src_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_0_V_empty_n : IN STD_LOGIC;
p_src_data_stream_0_V_read : OUT STD_LOGIC;
p_src_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_1_V_empty_n : IN STD_LOGIC;
p_src_data_stream_1_V_read : OUT STD_LOGIC;
p_src_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_2_V_empty_n : IN STD_LOGIC;
p_src_data_stream_2_V_read : OUT STD_LOGIC;
p_dst_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_0_V_full_n : IN STD_LOGIC;
p_dst_data_stream_0_V_write : OUT STD_LOGIC;
p_dst_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_1_V_full_n : IN STD_LOGIC;
p_dst_data_stream_1_V_write : OUT STD_LOGIC;
p_dst_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_2_V_full_n : IN STD_LOGIC;
p_dst_data_stream_2_V_write : OUT STD_LOGIC );
end;
architecture behav of CvtColor is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_ST_fsm_state37 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv20_0 : STD_LOGIC_VECTOR (19 downto 0) := "00000000000000000000";
constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv9_1FE : STD_LOGIC_VECTOR (8 downto 0) := "111111110";
constant ap_const_lv20_80000 : STD_LOGIC_VECTOR (19 downto 0) := "10000000000000000000";
constant ap_const_lv9_0 : STD_LOGIC_VECTOR (8 downto 0) := "000000000";
constant ap_const_lv6_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv8_78 : STD_LOGIC_VECTOR (7 downto 0) := "01111000";
constant ap_const_lv8_F0 : STD_LOGIC_VECTOR (7 downto 0) := "11110000";
constant ap_const_lv19_0 : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000000000";
constant ap_const_lv32_23 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100011";
constant ap_const_lv8_80 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_lv36_0 : STD_LOGIC_VECTOR (35 downto 0) := "000000000000000000000000000000000000";
constant ap_const_lv37_40000 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000001000000000000000000";
constant ap_const_lv32_24 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100100";
constant ap_const_lv37_5A00000 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000101101000000000000000000000";
constant ap_const_lv37_0 : STD_LOGIC_VECTOR (36 downto 0) := "0000000000000000000000000000000000000";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv10_3FF : STD_LOGIC_VECTOR (9 downto 0) := "1111111111";
constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal p_src_rows_V_blk_n : STD_LOGIC;
signal p_src_cols_V_blk_n : STD_LOGIC;
signal p_src_data_stream_0_V_blk_n : STD_LOGIC;
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_block_pp0_stage0 : BOOLEAN;
signal tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal p_src_data_stream_1_V_blk_n : STD_LOGIC;
signal p_src_data_stream_2_V_blk_n : STD_LOGIC;
signal p_dst_data_stream_0_V_blk_n : STD_LOGIC;
signal ap_enable_reg_pp0_iter33 : STD_LOGIC := '0';
signal ap_reg_pp0_iter32_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal p_dst_data_stream_1_V_blk_n : STD_LOGIC;
signal p_dst_data_stream_2_V_blk_n : STD_LOGIC;
signal j_i_reg_206 : STD_LOGIC_VECTOR (10 downto 0);
signal p_src_cols_V_read_reg_928 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_block_state1 : BOOLEAN;
signal p_src_rows_V_read_reg_933 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_i_fu_254_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal i_fu_259_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal i_reg_942 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_15_i_fu_269_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state5_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_state6_pp0_stage0_iter3 : BOOLEAN;
signal ap_block_state7_pp0_stage0_iter4 : BOOLEAN;
signal ap_block_state8_pp0_stage0_iter5 : BOOLEAN;
signal ap_block_state9_pp0_stage0_iter6 : BOOLEAN;
signal ap_block_state10_pp0_stage0_iter7 : BOOLEAN;
signal ap_block_state11_pp0_stage0_iter8 : BOOLEAN;
signal ap_block_state12_pp0_stage0_iter9 : BOOLEAN;
signal ap_block_state13_pp0_stage0_iter10 : BOOLEAN;
signal ap_block_state14_pp0_stage0_iter11 : BOOLEAN;
signal ap_block_state15_pp0_stage0_iter12 : BOOLEAN;
signal ap_block_state16_pp0_stage0_iter13 : BOOLEAN;
signal ap_block_state17_pp0_stage0_iter14 : BOOLEAN;
signal ap_block_state18_pp0_stage0_iter15 : BOOLEAN;
signal ap_block_state19_pp0_stage0_iter16 : BOOLEAN;
signal ap_block_state20_pp0_stage0_iter17 : BOOLEAN;
signal ap_block_state21_pp0_stage0_iter18 : BOOLEAN;
signal ap_block_state22_pp0_stage0_iter19 : BOOLEAN;
signal ap_block_state23_pp0_stage0_iter20 : BOOLEAN;
signal ap_block_state24_pp0_stage0_iter21 : BOOLEAN;
signal ap_block_state25_pp0_stage0_iter22 : BOOLEAN;
signal ap_block_state26_pp0_stage0_iter23 : BOOLEAN;
signal ap_block_state27_pp0_stage0_iter24 : BOOLEAN;
signal ap_block_state28_pp0_stage0_iter25 : BOOLEAN;
signal ap_block_state29_pp0_stage0_iter26 : BOOLEAN;
signal ap_block_state30_pp0_stage0_iter27 : BOOLEAN;
signal ap_block_state31_pp0_stage0_iter28 : BOOLEAN;
signal ap_block_state32_pp0_stage0_iter29 : BOOLEAN;
signal ap_block_state33_pp0_stage0_iter30 : BOOLEAN;
signal ap_block_state34_pp0_stage0_iter31 : BOOLEAN;
signal ap_block_state35_pp0_stage0_iter32 : BOOLEAN;
signal ap_block_state36_pp0_stage0_iter33 : BOOLEAN;
signal ap_block_pp0_stage0_11001 : BOOLEAN;
signal ap_reg_pp0_iter1_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter2_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter3_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter4_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter5_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter6_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter7_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter8_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter9_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter10_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter11_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter12_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter13_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter14_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter15_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter16_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter17_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter18_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter19_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter20_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter21_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter22_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter23_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter24_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter25_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter26_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter27_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter28_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter29_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter30_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter31_tmp_15_i_reg_947 : STD_LOGIC_VECTOR (0 downto 0);
signal j_fu_274_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal tmp_40_reg_956 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_tmp_40_reg_956 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_40_reg_956 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_41_reg_964 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_tmp_41_reg_964 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_41_reg_964 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_42_reg_974 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_tmp_42_reg_974 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_42_reg_974 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_44_i_fu_280_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_44_i_reg_985 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_i_fu_286_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_i_reg_990 : STD_LOGIC_VECTOR (0 downto 0);
signal G_1_fu_302_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal G_1_reg_995 : STD_LOGIC_VECTOR (7 downto 0);
signal G_2_fu_319_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal G_2_reg_1001 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_19_load_2_max_1_s_fu_330_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_19_load_2_max_1_s_reg_1007 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_19_load_2_min_1_s_fu_340_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_19_load_2_min_1_s_reg_1015 : STD_LOGIC_VECTOR (7 downto 0);
signal diff_fu_346_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal diff_reg_1021 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_diff_reg_1021 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_diff_reg_1021 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_diff_reg_1021 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_diff_reg_1021 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter8_diff_reg_1021 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter9_diff_reg_1021 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter10_diff_reg_1021 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter11_diff_reg_1021 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter12_diff_reg_1021 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter13_diff_reg_1021 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter14_diff_reg_1021 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter15_diff_reg_1021 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter16_diff_reg_1021 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter17_diff_reg_1021 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter18_diff_reg_1021 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter19_diff_reg_1021 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter20_diff_reg_1021 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter21_diff_reg_1021 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter22_diff_reg_1021 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter23_diff_reg_1021 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter24_diff_reg_1021 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter25_diff_reg_1021 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter26_diff_reg_1021 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter27_diff_reg_1021 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter28_diff_reg_1021 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter29_diff_reg_1021 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Val2_23_fu_358_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal p_Val2_23_reg_1027 : STD_LOGIC_VECTOR (8 downto 0);
signal p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter8_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter9_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter10_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter11_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter12_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter13_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter14_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter15_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter16_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter17_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter18_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter19_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter20_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter21_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter22_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter23_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter24_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter25_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter26_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter27_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter28_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter29_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter30_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter31_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter32_p_Val2_36_reg_1033 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_28_i_fu_374_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_28_i_reg_1039 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter5_tmp_28_i_reg_1039 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter6_tmp_28_i_reg_1039 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter7_tmp_28_i_reg_1039 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter8_tmp_28_i_reg_1039 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter9_tmp_28_i_reg_1039 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter10_tmp_28_i_reg_1039 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter11_tmp_28_i_reg_1039 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter12_tmp_28_i_reg_1039 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter13_tmp_28_i_reg_1039 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter14_tmp_28_i_reg_1039 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter15_tmp_28_i_reg_1039 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter16_tmp_28_i_reg_1039 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter17_tmp_28_i_reg_1039 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter18_tmp_28_i_reg_1039 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter19_tmp_28_i_reg_1039 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter20_tmp_28_i_reg_1039 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter21_tmp_28_i_reg_1039 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter22_tmp_28_i_reg_1039 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter23_tmp_28_i_reg_1039 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter24_tmp_28_i_reg_1039 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter25_tmp_28_i_reg_1039 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter26_tmp_28_i_reg_1039 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter27_tmp_28_i_reg_1039 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_i_fu_380_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal r_V_i_reg_1043 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_31_i_fu_386_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_31_i_reg_1048 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter5_tmp_31_i_reg_1048 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter6_tmp_31_i_reg_1048 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter7_tmp_31_i_reg_1048 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter8_tmp_31_i_reg_1048 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter9_tmp_31_i_reg_1048 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter10_tmp_31_i_reg_1048 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter11_tmp_31_i_reg_1048 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter12_tmp_31_i_reg_1048 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter13_tmp_31_i_reg_1048 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter14_tmp_31_i_reg_1048 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter15_tmp_31_i_reg_1048 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter16_tmp_31_i_reg_1048 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter17_tmp_31_i_reg_1048 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter18_tmp_31_i_reg_1048 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter19_tmp_31_i_reg_1048 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter20_tmp_31_i_reg_1048 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter21_tmp_31_i_reg_1048 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter22_tmp_31_i_reg_1048 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter23_tmp_31_i_reg_1048 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter24_tmp_31_i_reg_1048 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter25_tmp_31_i_reg_1048 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter26_tmp_31_i_reg_1048 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_33_i_fu_399_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_33_i_reg_1057 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter5_tmp_33_i_reg_1057 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter6_tmp_33_i_reg_1057 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter7_tmp_33_i_reg_1057 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter8_tmp_33_i_reg_1057 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter9_tmp_33_i_reg_1057 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter10_tmp_33_i_reg_1057 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter11_tmp_33_i_reg_1057 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter12_tmp_33_i_reg_1057 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter13_tmp_33_i_reg_1057 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter14_tmp_33_i_reg_1057 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter15_tmp_33_i_reg_1057 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter16_tmp_33_i_reg_1057 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter17_tmp_33_i_reg_1057 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter18_tmp_33_i_reg_1057 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter19_tmp_33_i_reg_1057 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter20_tmp_33_i_reg_1057 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter21_tmp_33_i_reg_1057 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter22_tmp_33_i_reg_1057 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter23_tmp_33_i_reg_1057 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter24_tmp_33_i_reg_1057 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter25_tmp_33_i_reg_1057 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter26_tmp_33_i_reg_1057 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter27_tmp_33_i_reg_1057 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_37_i_fu_415_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_37_i_reg_1063 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter5_tmp_37_i_reg_1063 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter6_tmp_37_i_reg_1063 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter7_tmp_37_i_reg_1063 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter8_tmp_37_i_reg_1063 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter9_tmp_37_i_reg_1063 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter10_tmp_37_i_reg_1063 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter11_tmp_37_i_reg_1063 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter12_tmp_37_i_reg_1063 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter13_tmp_37_i_reg_1063 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter14_tmp_37_i_reg_1063 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter15_tmp_37_i_reg_1063 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter16_tmp_37_i_reg_1063 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter17_tmp_37_i_reg_1063 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter18_tmp_37_i_reg_1063 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter19_tmp_37_i_reg_1063 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter20_tmp_37_i_reg_1063 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter21_tmp_37_i_reg_1063 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter22_tmp_37_i_reg_1063 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter23_tmp_37_i_reg_1063 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter24_tmp_37_i_reg_1063 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter25_tmp_37_i_reg_1063 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter26_tmp_37_i_reg_1063 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter27_tmp_37_i_reg_1063 : STD_LOGIC_VECTOR (0 downto 0);
signal sub_V_fu_454_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal sub_V_reg_1068 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_pp0_iter5_sub_V_reg_1068 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_pp0_iter6_sub_V_reg_1068 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_pp0_iter7_sub_V_reg_1068 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_pp0_iter8_sub_V_reg_1068 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_pp0_iter9_sub_V_reg_1068 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_pp0_iter10_sub_V_reg_1068 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_pp0_iter11_sub_V_reg_1068 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_pp0_iter12_sub_V_reg_1068 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_pp0_iter13_sub_V_reg_1068 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_pp0_iter14_sub_V_reg_1068 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_pp0_iter15_sub_V_reg_1068 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_pp0_iter16_sub_V_reg_1068 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_pp0_iter17_sub_V_reg_1068 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_pp0_iter18_sub_V_reg_1068 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_pp0_iter19_sub_V_reg_1068 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_pp0_iter20_sub_V_reg_1068 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_pp0_iter21_sub_V_reg_1068 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_pp0_iter22_sub_V_reg_1068 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_pp0_iter23_sub_V_reg_1068 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_pp0_iter24_sub_V_reg_1068 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_pp0_iter25_sub_V_reg_1068 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_reg_pp0_iter26_sub_V_reg_1068 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_25_i_fu_462_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_25_i_reg_1074 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter6_tmp_25_i_reg_1074 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter7_tmp_25_i_reg_1074 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter8_tmp_25_i_reg_1074 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter9_tmp_25_i_reg_1074 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter10_tmp_25_i_reg_1074 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter11_tmp_25_i_reg_1074 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter12_tmp_25_i_reg_1074 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter13_tmp_25_i_reg_1074 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter14_tmp_25_i_reg_1074 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter15_tmp_25_i_reg_1074 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter16_tmp_25_i_reg_1074 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter17_tmp_25_i_reg_1074 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter18_tmp_25_i_reg_1074 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter19_tmp_25_i_reg_1074 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter20_tmp_25_i_reg_1074 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter21_tmp_25_i_reg_1074 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter22_tmp_25_i_reg_1074 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter23_tmp_25_i_reg_1074 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter24_tmp_25_i_reg_1074 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter25_tmp_25_i_reg_1074 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter26_tmp_25_i_reg_1074 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter27_tmp_25_i_reg_1074 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_393_p2 : STD_LOGIC_VECTOR (19 downto 0);
signal r_V_3_i_fu_507_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal r_V_3_i_reg_1093 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_470_p2 : STD_LOGIC_VECTOR (19 downto 0);
signal grp_fu_479_p2 : STD_LOGIC_VECTOR (19 downto 0);
signal grp_fu_912_p3 : STD_LOGIC_VECTOR (35 downto 0);
signal t_V_reg_1108 : STD_LOGIC_VECTOR (35 downto 0);
signal ap_enable_reg_pp0_iter28 : STD_LOGIC := '0';
signal tmp_reg_1113 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter29_tmp_reg_1113 : STD_LOGIC_VECTOR (0 downto 0);
signal p_lshr_f_i_reg_1118 : STD_LOGIC_VECTOR (34 downto 0);
signal ap_reg_pp0_iter29_p_lshr_f_i_reg_1118 : STD_LOGIC_VECTOR (34 downto 0);
signal p_0292_0_i_i_v_v_fu_572_p3 : STD_LOGIC_VECTOR (19 downto 0);
signal p_0292_0_i_i_v_v_reg_1123 : STD_LOGIC_VECTOR (19 downto 0);
signal p_lshr_i_reg_1128 : STD_LOGIC_VECTOR (34 downto 0);
signal p_0292_0_i_i_fu_922_p2 : STD_LOGIC_VECTOR (27 downto 0);
signal p_0292_0_i_i_reg_1133 : STD_LOGIC_VECTOR (27 downto 0);
signal tmp_48_i_fu_613_p3 : STD_LOGIC_VECTOR (35 downto 0);
signal tmp_48_i_reg_1139 : STD_LOGIC_VECTOR (35 downto 0);
signal p_Val2_s_fu_645_p2 : STD_LOGIC_VECTOR (36 downto 0);
signal p_Val2_s_reg_1144 : STD_LOGIC_VECTOR (36 downto 0);
signal signbit_reg_1149 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter32_signbit_reg_1149 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_9_reg_1156 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_31_reg_1161 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Result_i_i_i_reg_1166 : STD_LOGIC_VECTOR (9 downto 0);
signal r_V_6_fu_701_p2 : STD_LOGIC_VECTOR (36 downto 0);
signal r_V_6_reg_1172 : STD_LOGIC_VECTOR (36 downto 0);
signal p_Val2_33_reg_1177 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_34_reg_1182 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp_i_i_i_i_fu_735_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal phitmp_i_i_i_i_reg_1187 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_29_fu_751_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Val2_29_reg_1192 : STD_LOGIC_VECTOR (7 downto 0);
signal p_38_i_i_i_i_fu_794_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_38_i_i_i_i_reg_1198 : STD_LOGIC_VECTOR (0 downto 0);
signal p_39_demorgan_i_i_i_i_fu_800_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_39_demorgan_i_i_i_i_reg_1204 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_40_fu_845_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Val2_40_reg_1210 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_pp0_stage0_subdone : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC;
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter5 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter6 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter7 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter8 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter9 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter10 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter11 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter12 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter13 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter14 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter15 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter16 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter17 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter18 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter19 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter20 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter21 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter22 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter23 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter24 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter25 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter26 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter27 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter29 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter30 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter31 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter32 : STD_LOGIC := '0';
signal i_i_reg_195 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_CS_fsm_state37 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state37 : signal is "none";
signal ap_phi_reg_pp0_iter0_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter1_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter2_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter3_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter4_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter5_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter6_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter7_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter8_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter9_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter10_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter11_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter12_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter13_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter14_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter15_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter16_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter17_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter18_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter19_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter20_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter21_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter22_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter23_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter24_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter25_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter26_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter27_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter28_p_0332_0_i_i_reg_217 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter0_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter1_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter2_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter3_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter4_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter5_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter6_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter7_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter8_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter9_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter10_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter11_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter12_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter13_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter14_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter15_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter16_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter17_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter18_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter19_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter20_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter21_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter22_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter23_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter24_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter25_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter26_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter27_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter28_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter29_p_0150_0_i_i_reg_228 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter0_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter1_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter2_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter3_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter4_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter5_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter6_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter7_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter8_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter9_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter10_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter11_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter12_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter13_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter14_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter15_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter16_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter17_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter18_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter19_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter20_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter21_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter22_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter23_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter24_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter25_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter26_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter27_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter28_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_phi_reg_pp0_iter29_p_0211_0_i_i_reg_239 : STD_LOGIC_VECTOR (19 downto 0);
signal ap_block_pp0_stage0_01001 : BOOLEAN;
signal i_cast_i_cast_fu_250_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal j_cast_i_cast_fu_265_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal R_tmp_19_load_2_i_fu_292_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_44_1_i_fu_297_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal R_tmp_19_load_i_fu_309_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_50_1_i_fu_314_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_44_2_i_fu_326_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_50_2_i_fu_336_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_17_cast_i_fu_355_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_16_cast_i_fu_352_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal grp_fu_393_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_34_i_fu_403_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_35_i_fu_406_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_39_i_fu_419_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_36_i_fu_409_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_43_i_fu_428_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal sel_tmp1_fu_442_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp2_fu_448_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_40_i_fu_422_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal sel_tmp_fu_434_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal grp_fu_470_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal grp_fu_479_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal p_shl4_i_fu_485_p3 : STD_LOGIC_VECTOR (14 downto 0);
signal p_shl5_i_fu_496_p3 : STD_LOGIC_VECTOR (10 downto 0);
signal p_shl4_cast_i_fu_492_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal p_shl5_cast_i_fu_503_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_fu_513_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_cast_fu_517_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_s_fu_524_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Val2_6_fu_532_p3 : STD_LOGIC_VECTOR (26 downto 0);
signal tmp_30_i_fu_567_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_neg_i_fu_580_p2 : STD_LOGIC_VECTOR (35 downto 0);
attribute use_dsp48 : string;
attribute use_dsp48 of p_neg_i_fu_580_p2 : signal is "no";
signal tmp_2_fu_601_p1 : STD_LOGIC_VECTOR (35 downto 0);
signal p_neg_t_i_fu_604_p2 : STD_LOGIC_VECTOR (35 downto 0);
signal tmp_3_fu_610_p1 : STD_LOGIC_VECTOR (35 downto 0);
signal p_Val2_7_fu_620_p1 : STD_LOGIC_VECTOR (36 downto 0);
signal r_V_fu_623_p2 : STD_LOGIC_VECTOR (36 downto 0);
signal tmp_29_fu_629_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_cast_cast_fu_637_p3 : STD_LOGIC_VECTOR (36 downto 0);
signal p_shl_i_fu_690_p3 : STD_LOGIC_VECTOR (35 downto 0);
signal p_shl_cast_i_fu_697_p1 : STD_LOGIC_VECTOR (36 downto 0);
signal OP2_V_4_cast73_i_fu_687_p1 : STD_LOGIC_VECTOR (36 downto 0);
signal tmp_6_fu_725_p4 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_11_i_i_i_fu_741_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_33_fu_756_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_32_fu_744_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_12_i_i_i_fu_764_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal carry_fu_770_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal Range1_all_ones_fu_776_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal Range1_all_zeros_fu_781_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal deleted_zeros_fu_786_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_i66_i_fu_805_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Val2_34_fu_815_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_36_fu_820_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_35_fu_808_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_i_i_i_fu_828_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal carry_1_fu_834_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal overflow_fu_840_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_13_i_i_i_fu_853_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal signbit_not_fu_863_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal neg_src_not_i_i_i_fu_868_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_39_demorgan_i_not_i_fu_878_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i_not_i_i_s_fu_873_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal neg_src_fu_858_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i_i_fu_883_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_mux_i_i_i_fu_889_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_i_i_i_fu_896_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_912_p0 : STD_LOGIC_VECTOR (19 downto 0);
signal grp_fu_912_p2 : STD_LOGIC_VECTOR (26 downto 0);
signal p_0292_0_i_i_fu_922_p0 : STD_LOGIC_VECTOR (19 downto 0);
signal p_0292_0_i_i_fu_922_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_393_ce : STD_LOGIC;
signal grp_fu_470_ce : STD_LOGIC;
signal grp_fu_479_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
signal grp_fu_393_p10 : STD_LOGIC_VECTOR (19 downto 0);
signal grp_fu_470_p10 : STD_LOGIC_VECTOR (19 downto 0);
signal grp_fu_479_p10 : STD_LOGIC_VECTOR (19 downto 0);
signal grp_fu_912_p00 : STD_LOGIC_VECTOR (35 downto 0);
signal grp_fu_912_p20 : STD_LOGIC_VECTOR (35 downto 0);
signal p_0292_0_i_i_fu_922_p00 : STD_LOGIC_VECTOR (27 downto 0);
signal p_0292_0_i_i_fu_922_p10 : STD_LOGIC_VECTOR (27 downto 0);
component hls_saturation_enbkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (19 downto 0);
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (19 downto 0) );
end component;
component hls_saturation_encud IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (19 downto 0);
din1 : IN STD_LOGIC_VECTOR (8 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (19 downto 0) );
end component;
component hls_saturation_endEe IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (19 downto 0);
din1 : IN STD_LOGIC_VECTOR (15 downto 0);
din2 : IN STD_LOGIC_VECTOR (26 downto 0);
dout : OUT STD_LOGIC_VECTOR (35 downto 0) );
end component;
component hls_saturation_eneOg IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (19 downto 0);
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
dout : OUT STD_LOGIC_VECTOR (27 downto 0) );
end component;
begin
hls_saturation_enbkb_U27 : component hls_saturation_enbkb
generic map (
ID => 1,
NUM_STAGE => 24,
din0_WIDTH => 20,
din1_WIDTH => 8,
dout_WIDTH => 20)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => ap_const_lv20_80000,
din1 => grp_fu_393_p1,
ce => grp_fu_393_ce,
dout => grp_fu_393_p2);
hls_saturation_encud_U28 : component hls_saturation_encud
generic map (
ID => 1,
NUM_STAGE => 24,
din0_WIDTH => 20,
din1_WIDTH => 9,
dout_WIDTH => 20)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => ap_const_lv20_80000,
din1 => grp_fu_470_p1,
ce => grp_fu_470_ce,
dout => grp_fu_470_p2);
hls_saturation_encud_U29 : component hls_saturation_encud
generic map (
ID => 1,
NUM_STAGE => 24,
din0_WIDTH => 20,
din1_WIDTH => 9,
dout_WIDTH => 20)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => ap_const_lv20_80000,
din1 => grp_fu_479_p1,
ce => grp_fu_479_ce,
dout => grp_fu_479_p2);
hls_saturation_endEe_U30 : component hls_saturation_endEe
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 20,
din1_WIDTH => 16,
din2_WIDTH => 27,
dout_WIDTH => 36)
port map (
din0 => grp_fu_912_p0,
din1 => r_V_3_i_reg_1093,
din2 => grp_fu_912_p2,
dout => grp_fu_912_p3);
hls_saturation_eneOg_U31 : component hls_saturation_eneOg
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 20,
din1_WIDTH => 8,
dout_WIDTH => 28)
port map (
din0 => p_0292_0_i_i_fu_922_p0,
din1 => p_0292_0_i_i_fu_922_p1,
dout => p_0292_0_i_i_fu_922_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_continue = ap_const_logic_1)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_254_p2 = ap_const_lv1_0))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((tmp_i_fu_254_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3)) then
ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state3);
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end if;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter10_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter10 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter11_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter11 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter12_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter12 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter13_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter13 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter14_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter14 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter15_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter15 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter16_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter16 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter17_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter17 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter18_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter18 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter18 <= ap_enable_reg_pp0_iter17;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter19_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter19 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter19 <= ap_enable_reg_pp0_iter18;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter20_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter20 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter20 <= ap_enable_reg_pp0_iter19;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter21_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter21 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter21 <= ap_enable_reg_pp0_iter20;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter22_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter22 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter21;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter23_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter23 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter23 <= ap_enable_reg_pp0_iter22;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter24_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter24 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter24 <= ap_enable_reg_pp0_iter23;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter25_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter25 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter25 <= ap_enable_reg_pp0_iter24;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter26_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter26 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter26 <= ap_enable_reg_pp0_iter25;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter27_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter27 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter27 <= ap_enable_reg_pp0_iter26;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter28_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter28 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter28 <= ap_enable_reg_pp0_iter27;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter29_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter29 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter29 <= ap_enable_reg_pp0_iter28;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter30_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter30 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter30 <= ap_enable_reg_pp0_iter29;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter31_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter31 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter31 <= ap_enable_reg_pp0_iter30;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter32_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter32 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter32 <= ap_enable_reg_pp0_iter31;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter33_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter33 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter33 <= ap_enable_reg_pp0_iter32;
elsif (((tmp_i_fu_254_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_enable_reg_pp0_iter33 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter6 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter7 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter8 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter9 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter28_p_0332_0_i_i_reg_217_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter27 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
if (((ap_reg_pp0_iter26_tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_reg_pp0_iter26_tmp_31_i_reg_1048 = ap_const_lv1_0))) then
ap_phi_reg_pp0_iter28_p_0332_0_i_i_reg_217 <= grp_fu_393_p2;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter28_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter27_p_0332_0_i_i_reg_217;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter29_p_0150_0_i_i_reg_228_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter28 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
if (((ap_reg_pp0_iter27_tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_reg_pp0_iter27_tmp_25_i_reg_1074 = ap_const_lv1_0))) then
ap_phi_reg_pp0_iter29_p_0150_0_i_i_reg_228 <= grp_fu_470_p2;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter29_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter28_p_0150_0_i_i_reg_228;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter29_p_0211_0_i_i_reg_239_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter28 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
if (((ap_reg_pp0_iter27_tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_reg_pp0_iter27_tmp_28_i_reg_1039 = ap_const_lv1_0))) then
ap_phi_reg_pp0_iter29_p_0211_0_i_i_reg_239 <= grp_fu_479_p2;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter29_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter28_p_0211_0_i_i_reg_239;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter5_p_0211_0_i_i_reg_239_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
if (((tmp_28_i_fu_374_p2 = ap_const_lv1_1) and (ap_reg_pp0_iter3_tmp_15_i_reg_947 = ap_const_lv1_1))) then
ap_phi_reg_pp0_iter5_p_0211_0_i_i_reg_239 <= ap_const_lv20_0;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter5_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter4_p_0211_0_i_i_reg_239;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter5_p_0332_0_i_i_reg_217_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
if (((tmp_31_i_fu_386_p2 = ap_const_lv1_1) and (ap_reg_pp0_iter3_tmp_15_i_reg_947 = ap_const_lv1_1))) then
ap_phi_reg_pp0_iter5_p_0332_0_i_i_reg_217 <= ap_const_lv20_0;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter5_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter4_p_0332_0_i_i_reg_217;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter6_p_0150_0_i_i_reg_228_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
if (((tmp_25_i_fu_462_p2 = ap_const_lv1_1) and (ap_reg_pp0_iter4_tmp_15_i_reg_947 = ap_const_lv1_1))) then
ap_phi_reg_pp0_iter6_p_0150_0_i_i_reg_228 <= ap_const_lv20_0;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter6_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter5_p_0150_0_i_i_reg_228;
end if;
end if;
end if;
end process;
i_i_reg_195_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state37)) then
i_i_reg_195 <= i_reg_942;
elsif ((not(((ap_start = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
i_i_reg_195 <= ap_const_lv11_0;
end if;
end if;
end process;
j_i_reg_206_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_15_i_fu_269_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
j_i_reg_206 <= j_fu_274_p2;
elsif (((tmp_i_fu_254_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
j_i_reg_206 <= ap_const_lv11_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter1_tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
G_1_reg_995 <= G_1_fu_302_p3;
G_2_reg_1001 <= G_2_fu_319_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter9 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter10_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter9_p_0150_0_i_i_reg_228;
ap_phi_reg_pp0_iter10_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter9_p_0211_0_i_i_reg_239;
ap_phi_reg_pp0_iter10_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter9_p_0332_0_i_i_reg_217;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter10 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter11_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter10_p_0150_0_i_i_reg_228;
ap_phi_reg_pp0_iter11_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter10_p_0211_0_i_i_reg_239;
ap_phi_reg_pp0_iter11_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter10_p_0332_0_i_i_reg_217;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter11 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter12_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter11_p_0150_0_i_i_reg_228;
ap_phi_reg_pp0_iter12_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter11_p_0211_0_i_i_reg_239;
ap_phi_reg_pp0_iter12_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter11_p_0332_0_i_i_reg_217;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter12 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter13_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter12_p_0150_0_i_i_reg_228;
ap_phi_reg_pp0_iter13_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter12_p_0211_0_i_i_reg_239;
ap_phi_reg_pp0_iter13_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter12_p_0332_0_i_i_reg_217;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter13 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter14_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter13_p_0150_0_i_i_reg_228;
ap_phi_reg_pp0_iter14_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter13_p_0211_0_i_i_reg_239;
ap_phi_reg_pp0_iter14_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter13_p_0332_0_i_i_reg_217;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter14 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter15_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter14_p_0150_0_i_i_reg_228;
ap_phi_reg_pp0_iter15_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter14_p_0211_0_i_i_reg_239;
ap_phi_reg_pp0_iter15_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter14_p_0332_0_i_i_reg_217;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter15 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter16_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter15_p_0150_0_i_i_reg_228;
ap_phi_reg_pp0_iter16_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter15_p_0211_0_i_i_reg_239;
ap_phi_reg_pp0_iter16_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter15_p_0332_0_i_i_reg_217;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter16 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter17_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter16_p_0150_0_i_i_reg_228;
ap_phi_reg_pp0_iter17_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter16_p_0211_0_i_i_reg_239;
ap_phi_reg_pp0_iter17_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter16_p_0332_0_i_i_reg_217;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter17 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter18_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter17_p_0150_0_i_i_reg_228;
ap_phi_reg_pp0_iter18_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter17_p_0211_0_i_i_reg_239;
ap_phi_reg_pp0_iter18_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter17_p_0332_0_i_i_reg_217;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter18 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter19_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter18_p_0150_0_i_i_reg_228;
ap_phi_reg_pp0_iter19_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter18_p_0211_0_i_i_reg_239;
ap_phi_reg_pp0_iter19_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter18_p_0332_0_i_i_reg_217;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter1_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter0_p_0150_0_i_i_reg_228;
ap_phi_reg_pp0_iter1_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter0_p_0211_0_i_i_reg_239;
ap_phi_reg_pp0_iter1_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter0_p_0332_0_i_i_reg_217;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter19 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter20_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter19_p_0150_0_i_i_reg_228;
ap_phi_reg_pp0_iter20_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter19_p_0211_0_i_i_reg_239;
ap_phi_reg_pp0_iter20_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter19_p_0332_0_i_i_reg_217;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter20 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter21_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter20_p_0150_0_i_i_reg_228;
ap_phi_reg_pp0_iter21_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter20_p_0211_0_i_i_reg_239;
ap_phi_reg_pp0_iter21_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter20_p_0332_0_i_i_reg_217;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter21 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter22_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter21_p_0150_0_i_i_reg_228;
ap_phi_reg_pp0_iter22_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter21_p_0211_0_i_i_reg_239;
ap_phi_reg_pp0_iter22_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter21_p_0332_0_i_i_reg_217;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter22 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter23_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter22_p_0150_0_i_i_reg_228;
ap_phi_reg_pp0_iter23_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter22_p_0211_0_i_i_reg_239;
ap_phi_reg_pp0_iter23_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter22_p_0332_0_i_i_reg_217;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter23 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter24_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter23_p_0150_0_i_i_reg_228;
ap_phi_reg_pp0_iter24_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter23_p_0211_0_i_i_reg_239;
ap_phi_reg_pp0_iter24_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter23_p_0332_0_i_i_reg_217;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter24 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter25_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter24_p_0150_0_i_i_reg_228;
ap_phi_reg_pp0_iter25_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter24_p_0211_0_i_i_reg_239;
ap_phi_reg_pp0_iter25_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter24_p_0332_0_i_i_reg_217;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter25 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter26_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter25_p_0150_0_i_i_reg_228;
ap_phi_reg_pp0_iter26_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter25_p_0211_0_i_i_reg_239;
ap_phi_reg_pp0_iter26_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter25_p_0332_0_i_i_reg_217;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter26 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter27_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter26_p_0150_0_i_i_reg_228;
ap_phi_reg_pp0_iter27_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter26_p_0211_0_i_i_reg_239;
ap_phi_reg_pp0_iter27_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter26_p_0332_0_i_i_reg_217;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter27 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter28_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter27_p_0150_0_i_i_reg_228;
ap_phi_reg_pp0_iter28_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter27_p_0211_0_i_i_reg_239;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter2_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter1_p_0150_0_i_i_reg_228;
ap_phi_reg_pp0_iter2_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter1_p_0211_0_i_i_reg_239;
ap_phi_reg_pp0_iter2_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter1_p_0332_0_i_i_reg_217;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter3_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter2_p_0150_0_i_i_reg_228;
ap_phi_reg_pp0_iter3_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter2_p_0211_0_i_i_reg_239;
ap_phi_reg_pp0_iter3_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter2_p_0332_0_i_i_reg_217;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter3 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter4_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter3_p_0150_0_i_i_reg_228;
ap_phi_reg_pp0_iter4_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter3_p_0211_0_i_i_reg_239;
ap_phi_reg_pp0_iter4_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter3_p_0332_0_i_i_reg_217;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter5_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter4_p_0150_0_i_i_reg_228;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter6_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter5_p_0211_0_i_i_reg_239;
ap_phi_reg_pp0_iter6_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter5_p_0332_0_i_i_reg_217;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter6 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter7_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter6_p_0150_0_i_i_reg_228;
ap_phi_reg_pp0_iter7_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter6_p_0211_0_i_i_reg_239;
ap_phi_reg_pp0_iter7_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter6_p_0332_0_i_i_reg_217;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter7 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter8_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter7_p_0150_0_i_i_reg_228;
ap_phi_reg_pp0_iter8_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter7_p_0211_0_i_i_reg_239;
ap_phi_reg_pp0_iter8_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter7_p_0332_0_i_i_reg_217;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter8 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter9_p_0150_0_i_i_reg_228 <= ap_phi_reg_pp0_iter8_p_0150_0_i_i_reg_228;
ap_phi_reg_pp0_iter9_p_0211_0_i_i_reg_239 <= ap_phi_reg_pp0_iter8_p_0211_0_i_i_reg_239;
ap_phi_reg_pp0_iter9_p_0332_0_i_i_reg_217 <= ap_phi_reg_pp0_iter8_p_0332_0_i_i_reg_217;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_0 = ap_block_pp0_stage0_11001)) then
ap_reg_pp0_iter10_diff_reg_1021 <= ap_reg_pp0_iter9_diff_reg_1021;
ap_reg_pp0_iter10_p_Val2_36_reg_1033 <= ap_reg_pp0_iter9_p_Val2_36_reg_1033;
ap_reg_pp0_iter10_sub_V_reg_1068 <= ap_reg_pp0_iter9_sub_V_reg_1068;
ap_reg_pp0_iter10_tmp_15_i_reg_947 <= ap_reg_pp0_iter9_tmp_15_i_reg_947;
ap_reg_pp0_iter10_tmp_25_i_reg_1074 <= ap_reg_pp0_iter9_tmp_25_i_reg_1074;
ap_reg_pp0_iter10_tmp_28_i_reg_1039 <= ap_reg_pp0_iter9_tmp_28_i_reg_1039;
ap_reg_pp0_iter10_tmp_31_i_reg_1048 <= ap_reg_pp0_iter9_tmp_31_i_reg_1048;
ap_reg_pp0_iter10_tmp_33_i_reg_1057 <= ap_reg_pp0_iter9_tmp_33_i_reg_1057;
ap_reg_pp0_iter10_tmp_37_i_reg_1063 <= ap_reg_pp0_iter9_tmp_37_i_reg_1063;
ap_reg_pp0_iter11_diff_reg_1021 <= ap_reg_pp0_iter10_diff_reg_1021;
ap_reg_pp0_iter11_p_Val2_36_reg_1033 <= ap_reg_pp0_iter10_p_Val2_36_reg_1033;
ap_reg_pp0_iter11_sub_V_reg_1068 <= ap_reg_pp0_iter10_sub_V_reg_1068;
ap_reg_pp0_iter11_tmp_15_i_reg_947 <= ap_reg_pp0_iter10_tmp_15_i_reg_947;
ap_reg_pp0_iter11_tmp_25_i_reg_1074 <= ap_reg_pp0_iter10_tmp_25_i_reg_1074;
ap_reg_pp0_iter11_tmp_28_i_reg_1039 <= ap_reg_pp0_iter10_tmp_28_i_reg_1039;
ap_reg_pp0_iter11_tmp_31_i_reg_1048 <= ap_reg_pp0_iter10_tmp_31_i_reg_1048;
ap_reg_pp0_iter11_tmp_33_i_reg_1057 <= ap_reg_pp0_iter10_tmp_33_i_reg_1057;
ap_reg_pp0_iter11_tmp_37_i_reg_1063 <= ap_reg_pp0_iter10_tmp_37_i_reg_1063;
ap_reg_pp0_iter12_diff_reg_1021 <= ap_reg_pp0_iter11_diff_reg_1021;
ap_reg_pp0_iter12_p_Val2_36_reg_1033 <= ap_reg_pp0_iter11_p_Val2_36_reg_1033;
ap_reg_pp0_iter12_sub_V_reg_1068 <= ap_reg_pp0_iter11_sub_V_reg_1068;
ap_reg_pp0_iter12_tmp_15_i_reg_947 <= ap_reg_pp0_iter11_tmp_15_i_reg_947;
ap_reg_pp0_iter12_tmp_25_i_reg_1074 <= ap_reg_pp0_iter11_tmp_25_i_reg_1074;
ap_reg_pp0_iter12_tmp_28_i_reg_1039 <= ap_reg_pp0_iter11_tmp_28_i_reg_1039;
ap_reg_pp0_iter12_tmp_31_i_reg_1048 <= ap_reg_pp0_iter11_tmp_31_i_reg_1048;
ap_reg_pp0_iter12_tmp_33_i_reg_1057 <= ap_reg_pp0_iter11_tmp_33_i_reg_1057;
ap_reg_pp0_iter12_tmp_37_i_reg_1063 <= ap_reg_pp0_iter11_tmp_37_i_reg_1063;
ap_reg_pp0_iter13_diff_reg_1021 <= ap_reg_pp0_iter12_diff_reg_1021;
ap_reg_pp0_iter13_p_Val2_36_reg_1033 <= ap_reg_pp0_iter12_p_Val2_36_reg_1033;
ap_reg_pp0_iter13_sub_V_reg_1068 <= ap_reg_pp0_iter12_sub_V_reg_1068;
ap_reg_pp0_iter13_tmp_15_i_reg_947 <= ap_reg_pp0_iter12_tmp_15_i_reg_947;
ap_reg_pp0_iter13_tmp_25_i_reg_1074 <= ap_reg_pp0_iter12_tmp_25_i_reg_1074;
ap_reg_pp0_iter13_tmp_28_i_reg_1039 <= ap_reg_pp0_iter12_tmp_28_i_reg_1039;
ap_reg_pp0_iter13_tmp_31_i_reg_1048 <= ap_reg_pp0_iter12_tmp_31_i_reg_1048;
ap_reg_pp0_iter13_tmp_33_i_reg_1057 <= ap_reg_pp0_iter12_tmp_33_i_reg_1057;
ap_reg_pp0_iter13_tmp_37_i_reg_1063 <= ap_reg_pp0_iter12_tmp_37_i_reg_1063;
ap_reg_pp0_iter14_diff_reg_1021 <= ap_reg_pp0_iter13_diff_reg_1021;
ap_reg_pp0_iter14_p_Val2_36_reg_1033 <= ap_reg_pp0_iter13_p_Val2_36_reg_1033;
ap_reg_pp0_iter14_sub_V_reg_1068 <= ap_reg_pp0_iter13_sub_V_reg_1068;
ap_reg_pp0_iter14_tmp_15_i_reg_947 <= ap_reg_pp0_iter13_tmp_15_i_reg_947;
ap_reg_pp0_iter14_tmp_25_i_reg_1074 <= ap_reg_pp0_iter13_tmp_25_i_reg_1074;
ap_reg_pp0_iter14_tmp_28_i_reg_1039 <= ap_reg_pp0_iter13_tmp_28_i_reg_1039;
ap_reg_pp0_iter14_tmp_31_i_reg_1048 <= ap_reg_pp0_iter13_tmp_31_i_reg_1048;
ap_reg_pp0_iter14_tmp_33_i_reg_1057 <= ap_reg_pp0_iter13_tmp_33_i_reg_1057;
ap_reg_pp0_iter14_tmp_37_i_reg_1063 <= ap_reg_pp0_iter13_tmp_37_i_reg_1063;
ap_reg_pp0_iter15_diff_reg_1021 <= ap_reg_pp0_iter14_diff_reg_1021;
ap_reg_pp0_iter15_p_Val2_36_reg_1033 <= ap_reg_pp0_iter14_p_Val2_36_reg_1033;
ap_reg_pp0_iter15_sub_V_reg_1068 <= ap_reg_pp0_iter14_sub_V_reg_1068;
ap_reg_pp0_iter15_tmp_15_i_reg_947 <= ap_reg_pp0_iter14_tmp_15_i_reg_947;
ap_reg_pp0_iter15_tmp_25_i_reg_1074 <= ap_reg_pp0_iter14_tmp_25_i_reg_1074;
ap_reg_pp0_iter15_tmp_28_i_reg_1039 <= ap_reg_pp0_iter14_tmp_28_i_reg_1039;
ap_reg_pp0_iter15_tmp_31_i_reg_1048 <= ap_reg_pp0_iter14_tmp_31_i_reg_1048;
ap_reg_pp0_iter15_tmp_33_i_reg_1057 <= ap_reg_pp0_iter14_tmp_33_i_reg_1057;
ap_reg_pp0_iter15_tmp_37_i_reg_1063 <= ap_reg_pp0_iter14_tmp_37_i_reg_1063;
ap_reg_pp0_iter16_diff_reg_1021 <= ap_reg_pp0_iter15_diff_reg_1021;
ap_reg_pp0_iter16_p_Val2_36_reg_1033 <= ap_reg_pp0_iter15_p_Val2_36_reg_1033;
ap_reg_pp0_iter16_sub_V_reg_1068 <= ap_reg_pp0_iter15_sub_V_reg_1068;
ap_reg_pp0_iter16_tmp_15_i_reg_947 <= ap_reg_pp0_iter15_tmp_15_i_reg_947;
ap_reg_pp0_iter16_tmp_25_i_reg_1074 <= ap_reg_pp0_iter15_tmp_25_i_reg_1074;
ap_reg_pp0_iter16_tmp_28_i_reg_1039 <= ap_reg_pp0_iter15_tmp_28_i_reg_1039;
ap_reg_pp0_iter16_tmp_31_i_reg_1048 <= ap_reg_pp0_iter15_tmp_31_i_reg_1048;
ap_reg_pp0_iter16_tmp_33_i_reg_1057 <= ap_reg_pp0_iter15_tmp_33_i_reg_1057;
ap_reg_pp0_iter16_tmp_37_i_reg_1063 <= ap_reg_pp0_iter15_tmp_37_i_reg_1063;
ap_reg_pp0_iter17_diff_reg_1021 <= ap_reg_pp0_iter16_diff_reg_1021;
ap_reg_pp0_iter17_p_Val2_36_reg_1033 <= ap_reg_pp0_iter16_p_Val2_36_reg_1033;
ap_reg_pp0_iter17_sub_V_reg_1068 <= ap_reg_pp0_iter16_sub_V_reg_1068;
ap_reg_pp0_iter17_tmp_15_i_reg_947 <= ap_reg_pp0_iter16_tmp_15_i_reg_947;
ap_reg_pp0_iter17_tmp_25_i_reg_1074 <= ap_reg_pp0_iter16_tmp_25_i_reg_1074;
ap_reg_pp0_iter17_tmp_28_i_reg_1039 <= ap_reg_pp0_iter16_tmp_28_i_reg_1039;
ap_reg_pp0_iter17_tmp_31_i_reg_1048 <= ap_reg_pp0_iter16_tmp_31_i_reg_1048;
ap_reg_pp0_iter17_tmp_33_i_reg_1057 <= ap_reg_pp0_iter16_tmp_33_i_reg_1057;
ap_reg_pp0_iter17_tmp_37_i_reg_1063 <= ap_reg_pp0_iter16_tmp_37_i_reg_1063;
ap_reg_pp0_iter18_diff_reg_1021 <= ap_reg_pp0_iter17_diff_reg_1021;
ap_reg_pp0_iter18_p_Val2_36_reg_1033 <= ap_reg_pp0_iter17_p_Val2_36_reg_1033;
ap_reg_pp0_iter18_sub_V_reg_1068 <= ap_reg_pp0_iter17_sub_V_reg_1068;
ap_reg_pp0_iter18_tmp_15_i_reg_947 <= ap_reg_pp0_iter17_tmp_15_i_reg_947;
ap_reg_pp0_iter18_tmp_25_i_reg_1074 <= ap_reg_pp0_iter17_tmp_25_i_reg_1074;
ap_reg_pp0_iter18_tmp_28_i_reg_1039 <= ap_reg_pp0_iter17_tmp_28_i_reg_1039;
ap_reg_pp0_iter18_tmp_31_i_reg_1048 <= ap_reg_pp0_iter17_tmp_31_i_reg_1048;
ap_reg_pp0_iter18_tmp_33_i_reg_1057 <= ap_reg_pp0_iter17_tmp_33_i_reg_1057;
ap_reg_pp0_iter18_tmp_37_i_reg_1063 <= ap_reg_pp0_iter17_tmp_37_i_reg_1063;
ap_reg_pp0_iter19_diff_reg_1021 <= ap_reg_pp0_iter18_diff_reg_1021;
ap_reg_pp0_iter19_p_Val2_36_reg_1033 <= ap_reg_pp0_iter18_p_Val2_36_reg_1033;
ap_reg_pp0_iter19_sub_V_reg_1068 <= ap_reg_pp0_iter18_sub_V_reg_1068;
ap_reg_pp0_iter19_tmp_15_i_reg_947 <= ap_reg_pp0_iter18_tmp_15_i_reg_947;
ap_reg_pp0_iter19_tmp_25_i_reg_1074 <= ap_reg_pp0_iter18_tmp_25_i_reg_1074;
ap_reg_pp0_iter19_tmp_28_i_reg_1039 <= ap_reg_pp0_iter18_tmp_28_i_reg_1039;
ap_reg_pp0_iter19_tmp_31_i_reg_1048 <= ap_reg_pp0_iter18_tmp_31_i_reg_1048;
ap_reg_pp0_iter19_tmp_33_i_reg_1057 <= ap_reg_pp0_iter18_tmp_33_i_reg_1057;
ap_reg_pp0_iter19_tmp_37_i_reg_1063 <= ap_reg_pp0_iter18_tmp_37_i_reg_1063;
ap_reg_pp0_iter20_diff_reg_1021 <= ap_reg_pp0_iter19_diff_reg_1021;
ap_reg_pp0_iter20_p_Val2_36_reg_1033 <= ap_reg_pp0_iter19_p_Val2_36_reg_1033;
ap_reg_pp0_iter20_sub_V_reg_1068 <= ap_reg_pp0_iter19_sub_V_reg_1068;
ap_reg_pp0_iter20_tmp_15_i_reg_947 <= ap_reg_pp0_iter19_tmp_15_i_reg_947;
ap_reg_pp0_iter20_tmp_25_i_reg_1074 <= ap_reg_pp0_iter19_tmp_25_i_reg_1074;
ap_reg_pp0_iter20_tmp_28_i_reg_1039 <= ap_reg_pp0_iter19_tmp_28_i_reg_1039;
ap_reg_pp0_iter20_tmp_31_i_reg_1048 <= ap_reg_pp0_iter19_tmp_31_i_reg_1048;
ap_reg_pp0_iter20_tmp_33_i_reg_1057 <= ap_reg_pp0_iter19_tmp_33_i_reg_1057;
ap_reg_pp0_iter20_tmp_37_i_reg_1063 <= ap_reg_pp0_iter19_tmp_37_i_reg_1063;
ap_reg_pp0_iter21_diff_reg_1021 <= ap_reg_pp0_iter20_diff_reg_1021;
ap_reg_pp0_iter21_p_Val2_36_reg_1033 <= ap_reg_pp0_iter20_p_Val2_36_reg_1033;
ap_reg_pp0_iter21_sub_V_reg_1068 <= ap_reg_pp0_iter20_sub_V_reg_1068;
ap_reg_pp0_iter21_tmp_15_i_reg_947 <= ap_reg_pp0_iter20_tmp_15_i_reg_947;
ap_reg_pp0_iter21_tmp_25_i_reg_1074 <= ap_reg_pp0_iter20_tmp_25_i_reg_1074;
ap_reg_pp0_iter21_tmp_28_i_reg_1039 <= ap_reg_pp0_iter20_tmp_28_i_reg_1039;
ap_reg_pp0_iter21_tmp_31_i_reg_1048 <= ap_reg_pp0_iter20_tmp_31_i_reg_1048;
ap_reg_pp0_iter21_tmp_33_i_reg_1057 <= ap_reg_pp0_iter20_tmp_33_i_reg_1057;
ap_reg_pp0_iter21_tmp_37_i_reg_1063 <= ap_reg_pp0_iter20_tmp_37_i_reg_1063;
ap_reg_pp0_iter22_diff_reg_1021 <= ap_reg_pp0_iter21_diff_reg_1021;
ap_reg_pp0_iter22_p_Val2_36_reg_1033 <= ap_reg_pp0_iter21_p_Val2_36_reg_1033;
ap_reg_pp0_iter22_sub_V_reg_1068 <= ap_reg_pp0_iter21_sub_V_reg_1068;
ap_reg_pp0_iter22_tmp_15_i_reg_947 <= ap_reg_pp0_iter21_tmp_15_i_reg_947;
ap_reg_pp0_iter22_tmp_25_i_reg_1074 <= ap_reg_pp0_iter21_tmp_25_i_reg_1074;
ap_reg_pp0_iter22_tmp_28_i_reg_1039 <= ap_reg_pp0_iter21_tmp_28_i_reg_1039;
ap_reg_pp0_iter22_tmp_31_i_reg_1048 <= ap_reg_pp0_iter21_tmp_31_i_reg_1048;
ap_reg_pp0_iter22_tmp_33_i_reg_1057 <= ap_reg_pp0_iter21_tmp_33_i_reg_1057;
ap_reg_pp0_iter22_tmp_37_i_reg_1063 <= ap_reg_pp0_iter21_tmp_37_i_reg_1063;
ap_reg_pp0_iter23_diff_reg_1021 <= ap_reg_pp0_iter22_diff_reg_1021;
ap_reg_pp0_iter23_p_Val2_36_reg_1033 <= ap_reg_pp0_iter22_p_Val2_36_reg_1033;
ap_reg_pp0_iter23_sub_V_reg_1068 <= ap_reg_pp0_iter22_sub_V_reg_1068;
ap_reg_pp0_iter23_tmp_15_i_reg_947 <= ap_reg_pp0_iter22_tmp_15_i_reg_947;
ap_reg_pp0_iter23_tmp_25_i_reg_1074 <= ap_reg_pp0_iter22_tmp_25_i_reg_1074;
ap_reg_pp0_iter23_tmp_28_i_reg_1039 <= ap_reg_pp0_iter22_tmp_28_i_reg_1039;
ap_reg_pp0_iter23_tmp_31_i_reg_1048 <= ap_reg_pp0_iter22_tmp_31_i_reg_1048;
ap_reg_pp0_iter23_tmp_33_i_reg_1057 <= ap_reg_pp0_iter22_tmp_33_i_reg_1057;
ap_reg_pp0_iter23_tmp_37_i_reg_1063 <= ap_reg_pp0_iter22_tmp_37_i_reg_1063;
ap_reg_pp0_iter24_diff_reg_1021 <= ap_reg_pp0_iter23_diff_reg_1021;
ap_reg_pp0_iter24_p_Val2_36_reg_1033 <= ap_reg_pp0_iter23_p_Val2_36_reg_1033;
ap_reg_pp0_iter24_sub_V_reg_1068 <= ap_reg_pp0_iter23_sub_V_reg_1068;
ap_reg_pp0_iter24_tmp_15_i_reg_947 <= ap_reg_pp0_iter23_tmp_15_i_reg_947;
ap_reg_pp0_iter24_tmp_25_i_reg_1074 <= ap_reg_pp0_iter23_tmp_25_i_reg_1074;
ap_reg_pp0_iter24_tmp_28_i_reg_1039 <= ap_reg_pp0_iter23_tmp_28_i_reg_1039;
ap_reg_pp0_iter24_tmp_31_i_reg_1048 <= ap_reg_pp0_iter23_tmp_31_i_reg_1048;
ap_reg_pp0_iter24_tmp_33_i_reg_1057 <= ap_reg_pp0_iter23_tmp_33_i_reg_1057;
ap_reg_pp0_iter24_tmp_37_i_reg_1063 <= ap_reg_pp0_iter23_tmp_37_i_reg_1063;
ap_reg_pp0_iter25_diff_reg_1021 <= ap_reg_pp0_iter24_diff_reg_1021;
ap_reg_pp0_iter25_p_Val2_36_reg_1033 <= ap_reg_pp0_iter24_p_Val2_36_reg_1033;
ap_reg_pp0_iter25_sub_V_reg_1068 <= ap_reg_pp0_iter24_sub_V_reg_1068;
ap_reg_pp0_iter25_tmp_15_i_reg_947 <= ap_reg_pp0_iter24_tmp_15_i_reg_947;
ap_reg_pp0_iter25_tmp_25_i_reg_1074 <= ap_reg_pp0_iter24_tmp_25_i_reg_1074;
ap_reg_pp0_iter25_tmp_28_i_reg_1039 <= ap_reg_pp0_iter24_tmp_28_i_reg_1039;
ap_reg_pp0_iter25_tmp_31_i_reg_1048 <= ap_reg_pp0_iter24_tmp_31_i_reg_1048;
ap_reg_pp0_iter25_tmp_33_i_reg_1057 <= ap_reg_pp0_iter24_tmp_33_i_reg_1057;
ap_reg_pp0_iter25_tmp_37_i_reg_1063 <= ap_reg_pp0_iter24_tmp_37_i_reg_1063;
ap_reg_pp0_iter26_diff_reg_1021 <= ap_reg_pp0_iter25_diff_reg_1021;
ap_reg_pp0_iter26_p_Val2_36_reg_1033 <= ap_reg_pp0_iter25_p_Val2_36_reg_1033;
ap_reg_pp0_iter26_sub_V_reg_1068 <= ap_reg_pp0_iter25_sub_V_reg_1068;
ap_reg_pp0_iter26_tmp_15_i_reg_947 <= ap_reg_pp0_iter25_tmp_15_i_reg_947;
ap_reg_pp0_iter26_tmp_25_i_reg_1074 <= ap_reg_pp0_iter25_tmp_25_i_reg_1074;
ap_reg_pp0_iter26_tmp_28_i_reg_1039 <= ap_reg_pp0_iter25_tmp_28_i_reg_1039;
ap_reg_pp0_iter26_tmp_31_i_reg_1048 <= ap_reg_pp0_iter25_tmp_31_i_reg_1048;
ap_reg_pp0_iter26_tmp_33_i_reg_1057 <= ap_reg_pp0_iter25_tmp_33_i_reg_1057;
ap_reg_pp0_iter26_tmp_37_i_reg_1063 <= ap_reg_pp0_iter25_tmp_37_i_reg_1063;
ap_reg_pp0_iter27_diff_reg_1021 <= ap_reg_pp0_iter26_diff_reg_1021;
ap_reg_pp0_iter27_p_Val2_36_reg_1033 <= ap_reg_pp0_iter26_p_Val2_36_reg_1033;
ap_reg_pp0_iter27_tmp_15_i_reg_947 <= ap_reg_pp0_iter26_tmp_15_i_reg_947;
ap_reg_pp0_iter27_tmp_25_i_reg_1074 <= ap_reg_pp0_iter26_tmp_25_i_reg_1074;
ap_reg_pp0_iter27_tmp_28_i_reg_1039 <= ap_reg_pp0_iter26_tmp_28_i_reg_1039;
ap_reg_pp0_iter27_tmp_33_i_reg_1057 <= ap_reg_pp0_iter26_tmp_33_i_reg_1057;
ap_reg_pp0_iter27_tmp_37_i_reg_1063 <= ap_reg_pp0_iter26_tmp_37_i_reg_1063;
ap_reg_pp0_iter28_diff_reg_1021 <= ap_reg_pp0_iter27_diff_reg_1021;
ap_reg_pp0_iter28_p_Val2_36_reg_1033 <= ap_reg_pp0_iter27_p_Val2_36_reg_1033;
ap_reg_pp0_iter28_tmp_15_i_reg_947 <= ap_reg_pp0_iter27_tmp_15_i_reg_947;
ap_reg_pp0_iter29_diff_reg_1021 <= ap_reg_pp0_iter28_diff_reg_1021;
ap_reg_pp0_iter29_p_Val2_36_reg_1033 <= ap_reg_pp0_iter28_p_Val2_36_reg_1033;
ap_reg_pp0_iter29_p_lshr_f_i_reg_1118 <= p_lshr_f_i_reg_1118;
ap_reg_pp0_iter29_tmp_15_i_reg_947 <= ap_reg_pp0_iter28_tmp_15_i_reg_947;
ap_reg_pp0_iter29_tmp_reg_1113 <= tmp_reg_1113;
ap_reg_pp0_iter2_tmp_15_i_reg_947 <= ap_reg_pp0_iter1_tmp_15_i_reg_947;
ap_reg_pp0_iter2_tmp_40_reg_956 <= tmp_40_reg_956;
ap_reg_pp0_iter2_tmp_41_reg_964 <= tmp_41_reg_964;
ap_reg_pp0_iter2_tmp_42_reg_974 <= tmp_42_reg_974;
ap_reg_pp0_iter30_p_Val2_36_reg_1033 <= ap_reg_pp0_iter29_p_Val2_36_reg_1033;
ap_reg_pp0_iter30_tmp_15_i_reg_947 <= ap_reg_pp0_iter29_tmp_15_i_reg_947;
ap_reg_pp0_iter31_p_Val2_36_reg_1033 <= ap_reg_pp0_iter30_p_Val2_36_reg_1033;
ap_reg_pp0_iter31_tmp_15_i_reg_947 <= ap_reg_pp0_iter30_tmp_15_i_reg_947;
ap_reg_pp0_iter32_p_Val2_36_reg_1033 <= ap_reg_pp0_iter31_p_Val2_36_reg_1033;
ap_reg_pp0_iter32_signbit_reg_1149 <= signbit_reg_1149;
ap_reg_pp0_iter32_tmp_15_i_reg_947 <= ap_reg_pp0_iter31_tmp_15_i_reg_947;
ap_reg_pp0_iter3_tmp_15_i_reg_947 <= ap_reg_pp0_iter2_tmp_15_i_reg_947;
ap_reg_pp0_iter3_tmp_40_reg_956 <= ap_reg_pp0_iter2_tmp_40_reg_956;
ap_reg_pp0_iter3_tmp_41_reg_964 <= ap_reg_pp0_iter2_tmp_41_reg_964;
ap_reg_pp0_iter3_tmp_42_reg_974 <= ap_reg_pp0_iter2_tmp_42_reg_974;
ap_reg_pp0_iter4_diff_reg_1021 <= diff_reg_1021;
ap_reg_pp0_iter4_tmp_15_i_reg_947 <= ap_reg_pp0_iter3_tmp_15_i_reg_947;
ap_reg_pp0_iter5_diff_reg_1021 <= ap_reg_pp0_iter4_diff_reg_1021;
ap_reg_pp0_iter5_p_Val2_36_reg_1033 <= p_Val2_36_reg_1033;
ap_reg_pp0_iter5_sub_V_reg_1068 <= sub_V_reg_1068;
ap_reg_pp0_iter5_tmp_15_i_reg_947 <= ap_reg_pp0_iter4_tmp_15_i_reg_947;
ap_reg_pp0_iter5_tmp_28_i_reg_1039 <= tmp_28_i_reg_1039;
ap_reg_pp0_iter5_tmp_31_i_reg_1048 <= tmp_31_i_reg_1048;
ap_reg_pp0_iter5_tmp_33_i_reg_1057 <= tmp_33_i_reg_1057;
ap_reg_pp0_iter5_tmp_37_i_reg_1063 <= tmp_37_i_reg_1063;
ap_reg_pp0_iter6_diff_reg_1021 <= ap_reg_pp0_iter5_diff_reg_1021;
ap_reg_pp0_iter6_p_Val2_36_reg_1033 <= ap_reg_pp0_iter5_p_Val2_36_reg_1033;
ap_reg_pp0_iter6_sub_V_reg_1068 <= ap_reg_pp0_iter5_sub_V_reg_1068;
ap_reg_pp0_iter6_tmp_15_i_reg_947 <= ap_reg_pp0_iter5_tmp_15_i_reg_947;
ap_reg_pp0_iter6_tmp_25_i_reg_1074 <= tmp_25_i_reg_1074;
ap_reg_pp0_iter6_tmp_28_i_reg_1039 <= ap_reg_pp0_iter5_tmp_28_i_reg_1039;
ap_reg_pp0_iter6_tmp_31_i_reg_1048 <= ap_reg_pp0_iter5_tmp_31_i_reg_1048;
ap_reg_pp0_iter6_tmp_33_i_reg_1057 <= ap_reg_pp0_iter5_tmp_33_i_reg_1057;
ap_reg_pp0_iter6_tmp_37_i_reg_1063 <= ap_reg_pp0_iter5_tmp_37_i_reg_1063;
ap_reg_pp0_iter7_diff_reg_1021 <= ap_reg_pp0_iter6_diff_reg_1021;
ap_reg_pp0_iter7_p_Val2_36_reg_1033 <= ap_reg_pp0_iter6_p_Val2_36_reg_1033;
ap_reg_pp0_iter7_sub_V_reg_1068 <= ap_reg_pp0_iter6_sub_V_reg_1068;
ap_reg_pp0_iter7_tmp_15_i_reg_947 <= ap_reg_pp0_iter6_tmp_15_i_reg_947;
ap_reg_pp0_iter7_tmp_25_i_reg_1074 <= ap_reg_pp0_iter6_tmp_25_i_reg_1074;
ap_reg_pp0_iter7_tmp_28_i_reg_1039 <= ap_reg_pp0_iter6_tmp_28_i_reg_1039;
ap_reg_pp0_iter7_tmp_31_i_reg_1048 <= ap_reg_pp0_iter6_tmp_31_i_reg_1048;
ap_reg_pp0_iter7_tmp_33_i_reg_1057 <= ap_reg_pp0_iter6_tmp_33_i_reg_1057;
ap_reg_pp0_iter7_tmp_37_i_reg_1063 <= ap_reg_pp0_iter6_tmp_37_i_reg_1063;
ap_reg_pp0_iter8_diff_reg_1021 <= ap_reg_pp0_iter7_diff_reg_1021;
ap_reg_pp0_iter8_p_Val2_36_reg_1033 <= ap_reg_pp0_iter7_p_Val2_36_reg_1033;
ap_reg_pp0_iter8_sub_V_reg_1068 <= ap_reg_pp0_iter7_sub_V_reg_1068;
ap_reg_pp0_iter8_tmp_15_i_reg_947 <= ap_reg_pp0_iter7_tmp_15_i_reg_947;
ap_reg_pp0_iter8_tmp_25_i_reg_1074 <= ap_reg_pp0_iter7_tmp_25_i_reg_1074;
ap_reg_pp0_iter8_tmp_28_i_reg_1039 <= ap_reg_pp0_iter7_tmp_28_i_reg_1039;
ap_reg_pp0_iter8_tmp_31_i_reg_1048 <= ap_reg_pp0_iter7_tmp_31_i_reg_1048;
ap_reg_pp0_iter8_tmp_33_i_reg_1057 <= ap_reg_pp0_iter7_tmp_33_i_reg_1057;
ap_reg_pp0_iter8_tmp_37_i_reg_1063 <= ap_reg_pp0_iter7_tmp_37_i_reg_1063;
ap_reg_pp0_iter9_diff_reg_1021 <= ap_reg_pp0_iter8_diff_reg_1021;
ap_reg_pp0_iter9_p_Val2_36_reg_1033 <= ap_reg_pp0_iter8_p_Val2_36_reg_1033;
ap_reg_pp0_iter9_sub_V_reg_1068 <= ap_reg_pp0_iter8_sub_V_reg_1068;
ap_reg_pp0_iter9_tmp_15_i_reg_947 <= ap_reg_pp0_iter8_tmp_15_i_reg_947;
ap_reg_pp0_iter9_tmp_25_i_reg_1074 <= ap_reg_pp0_iter8_tmp_25_i_reg_1074;
ap_reg_pp0_iter9_tmp_28_i_reg_1039 <= ap_reg_pp0_iter8_tmp_28_i_reg_1039;
ap_reg_pp0_iter9_tmp_31_i_reg_1048 <= ap_reg_pp0_iter8_tmp_31_i_reg_1048;
ap_reg_pp0_iter9_tmp_33_i_reg_1057 <= ap_reg_pp0_iter8_tmp_33_i_reg_1057;
ap_reg_pp0_iter9_tmp_37_i_reg_1063 <= ap_reg_pp0_iter8_tmp_37_i_reg_1063;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_reg_pp0_iter1_tmp_15_i_reg_947 <= tmp_15_i_reg_947;
tmp_15_i_reg_947 <= tmp_15_i_fu_269_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter2_tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
diff_reg_1021 <= diff_fu_346_p2;
tmp_19_load_2_max_1_s_reg_1007 <= tmp_19_load_2_max_1_s_fu_330_p3;
tmp_19_load_2_min_1_s_reg_1015 <= tmp_19_load_2_min_1_s_fu_340_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
i_reg_942 <= i_fu_259_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter29_tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_0292_0_i_i_reg_1133 <= p_0292_0_i_i_fu_922_p2;
tmp_48_i_reg_1139 <= tmp_48_i_fu_613_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter28_tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_0292_0_i_i_v_v_reg_1123 <= p_0292_0_i_i_v_v_fu_572_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter31_tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_38_i_i_i_i_reg_1198 <= p_38_i_i_i_i_fu_794_p2;
p_39_demorgan_i_i_i_i_reg_1204 <= p_39_demorgan_i_i_i_i_fu_800_p2;
p_Val2_29_reg_1192 <= p_Val2_29_fu_751_p2;
p_Val2_40_reg_1210 <= p_Val2_40_fu_845_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter30_tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_Result_i_i_i_reg_1166 <= p_Val2_s_fu_645_p2(36 downto 27);
p_Val2_33_reg_1177 <= r_V_6_fu_701_p2(26 downto 19);
p_Val2_9_reg_1156 <= p_Val2_s_fu_645_p2(26 downto 19);
p_Val2_s_reg_1144 <= p_Val2_s_fu_645_p2;
phitmp_i_i_i_i_reg_1187 <= phitmp_i_i_i_i_fu_735_p2;
r_V_6_reg_1172 <= r_V_6_fu_701_p2;
signbit_reg_1149 <= p_Val2_s_fu_645_p2(36 downto 36);
tmp_31_reg_1161 <= p_Val2_s_fu_645_p2(18 downto 18);
tmp_34_reg_1182 <= r_V_6_fu_701_p2(18 downto 18);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter3_tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_Val2_23_reg_1027 <= p_Val2_23_fu_358_p2;
p_Val2_36_reg_1033 <= p_Val2_23_fu_358_p2(8 downto 1);
sub_V_reg_1068 <= sub_V_fu_454_p3;
tmp_28_i_reg_1039 <= tmp_28_i_fu_374_p2;
tmp_31_i_reg_1048 <= tmp_31_i_fu_386_p2;
tmp_33_i_reg_1057 <= tmp_33_i_fu_399_p2;
tmp_37_i_reg_1063 <= tmp_37_i_fu_415_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter27_tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_lshr_f_i_reg_1118 <= grp_fu_912_p3(35 downto 1);
tmp_reg_1113 <= grp_fu_912_p3(35 downto 35);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_reg_1113 = ap_const_lv1_1) and (ap_reg_pp0_iter28_tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_lshr_i_reg_1128 <= p_neg_i_fu_580_p2(35 downto 1);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_start = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_src_cols_V_read_reg_928 <= p_src_cols_V_dout;
p_src_rows_V_read_reg_933 <= p_src_rows_V_dout;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter26_tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
r_V_3_i_reg_1093(15 downto 2) <= r_V_3_i_fu_507_p2(15 downto 2);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter3_tmp_15_i_reg_947 = ap_const_lv1_1) and (tmp_28_i_fu_374_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
r_V_i_reg_1043 <= r_V_i_fu_380_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter27_tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter28 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
t_V_reg_1108 <= grp_fu_912_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter4_tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
tmp_25_i_reg_1074 <= tmp_25_i_fu_462_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
tmp_40_reg_956 <= p_src_data_stream_0_V_dout;
tmp_41_reg_964 <= p_src_data_stream_1_V_dout;
tmp_42_reg_974 <= p_src_data_stream_2_V_dout;
tmp_44_i_reg_985 <= tmp_44_i_fu_280_p2;
tmp_50_i_reg_990 <= tmp_50_i_fu_286_p2;
end if;
end if;
end process;
r_V_3_i_reg_1093(1 downto 0) <= "00";
ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, p_src_rows_V_empty_n, p_src_cols_V_empty_n, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter33, tmp_i_fu_254_p2, ap_CS_fsm_state2, tmp_15_i_fu_269_p2, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_subdone, ap_enable_reg_pp0_iter32)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if ((not(((ap_start = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_254_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage0 =>
if ((not(((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (tmp_15_i_fu_269_p2 = ap_const_lv1_0))) and not(((ap_enable_reg_pp0_iter32 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter33 = ap_const_logic_1))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
elsif ((((ap_enable_reg_pp0_iter32 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter33 = ap_const_logic_1)) or ((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (tmp_15_i_fu_269_p2 = ap_const_lv1_0)))) then
ap_NS_fsm <= ap_ST_fsm_state37;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_state37 =>
ap_NS_fsm <= ap_ST_fsm_state2;
when others =>
ap_NS_fsm <= "XXXX";
end case;
end process;
G_1_fu_302_p3 <=
tmp_41_reg_964 when (tmp_44_1_i_fu_297_p2(0) = '1') else
R_tmp_19_load_2_i_fu_292_p3;
G_2_fu_319_p3 <=
tmp_41_reg_964 when (tmp_50_1_i_fu_314_p2(0) = '1') else
R_tmp_19_load_i_fu_309_p3;
OP2_V_4_cast73_i_fu_687_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_0292_0_i_i_reg_1133),37));
R_tmp_19_load_2_i_fu_292_p3 <=
tmp_40_reg_956 when (tmp_44_i_reg_985(0) = '1') else
tmp_42_reg_974;
R_tmp_19_load_i_fu_309_p3 <=
tmp_40_reg_956 when (tmp_50_i_reg_990(0) = '1') else
tmp_42_reg_974;
Range1_all_ones_fu_776_p2 <= "1" when (p_Result_i_i_i_reg_1166 = ap_const_lv10_3FF) else "0";
Range1_all_zeros_fu_781_p2 <= "1" when (p_Result_i_i_i_reg_1166 = ap_const_lv10_0) else "0";
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state37 <= ap_CS_fsm(3);
ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_01001_assign_proc : process(p_src_data_stream_0_V_empty_n, p_src_data_stream_1_V_empty_n, p_src_data_stream_2_V_empty_n, p_dst_data_stream_0_V_full_n, p_dst_data_stream_1_V_full_n, p_dst_data_stream_2_V_full_n, ap_enable_reg_pp0_iter1, tmp_15_i_reg_947, ap_enable_reg_pp0_iter33, ap_reg_pp0_iter32_tmp_15_i_reg_947)
begin
ap_block_pp0_stage0_01001 <= (((ap_enable_reg_pp0_iter33 = ap_const_logic_1) and (((ap_reg_pp0_iter32_tmp_15_i_reg_947 = ap_const_lv1_1) and (p_dst_data_stream_2_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter32_tmp_15_i_reg_947 = ap_const_lv1_1) and (p_dst_data_stream_1_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter32_tmp_15_i_reg_947 = ap_const_lv1_1) and (p_dst_data_stream_0_V_full_n = ap_const_logic_0)))) or ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((tmp_15_i_reg_947 = ap_const_lv1_1) and (p_src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((tmp_15_i_reg_947 = ap_const_lv1_1) and (p_src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((tmp_15_i_reg_947 = ap_const_lv1_1) and (p_src_data_stream_0_V_empty_n = ap_const_logic_0)))));
end process;
ap_block_pp0_stage0_11001_assign_proc : process(p_src_data_stream_0_V_empty_n, p_src_data_stream_1_V_empty_n, p_src_data_stream_2_V_empty_n, p_dst_data_stream_0_V_full_n, p_dst_data_stream_1_V_full_n, p_dst_data_stream_2_V_full_n, ap_enable_reg_pp0_iter1, tmp_15_i_reg_947, ap_enable_reg_pp0_iter33, ap_reg_pp0_iter32_tmp_15_i_reg_947)
begin
ap_block_pp0_stage0_11001 <= (((ap_enable_reg_pp0_iter33 = ap_const_logic_1) and (((ap_reg_pp0_iter32_tmp_15_i_reg_947 = ap_const_lv1_1) and (p_dst_data_stream_2_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter32_tmp_15_i_reg_947 = ap_const_lv1_1) and (p_dst_data_stream_1_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter32_tmp_15_i_reg_947 = ap_const_lv1_1) and (p_dst_data_stream_0_V_full_n = ap_const_logic_0)))) or ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((tmp_15_i_reg_947 = ap_const_lv1_1) and (p_src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((tmp_15_i_reg_947 = ap_const_lv1_1) and (p_src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((tmp_15_i_reg_947 = ap_const_lv1_1) and (p_src_data_stream_0_V_empty_n = ap_const_logic_0)))));
end process;
ap_block_pp0_stage0_subdone_assign_proc : process(p_src_data_stream_0_V_empty_n, p_src_data_stream_1_V_empty_n, p_src_data_stream_2_V_empty_n, p_dst_data_stream_0_V_full_n, p_dst_data_stream_1_V_full_n, p_dst_data_stream_2_V_full_n, ap_enable_reg_pp0_iter1, tmp_15_i_reg_947, ap_enable_reg_pp0_iter33, ap_reg_pp0_iter32_tmp_15_i_reg_947)
begin
ap_block_pp0_stage0_subdone <= (((ap_enable_reg_pp0_iter33 = ap_const_logic_1) and (((ap_reg_pp0_iter32_tmp_15_i_reg_947 = ap_const_lv1_1) and (p_dst_data_stream_2_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter32_tmp_15_i_reg_947 = ap_const_lv1_1) and (p_dst_data_stream_1_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter32_tmp_15_i_reg_947 = ap_const_lv1_1) and (p_dst_data_stream_0_V_full_n = ap_const_logic_0)))) or ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((tmp_15_i_reg_947 = ap_const_lv1_1) and (p_src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((tmp_15_i_reg_947 = ap_const_lv1_1) and (p_src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((tmp_15_i_reg_947 = ap_const_lv1_1) and (p_src_data_stream_0_V_empty_n = ap_const_logic_0)))));
end process;
ap_block_state1_assign_proc : process(ap_start, ap_done_reg, p_src_rows_V_empty_n, p_src_cols_V_empty_n)
begin
ap_block_state1 <= ((ap_start = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
ap_block_state10_pp0_stage0_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state11_pp0_stage0_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state12_pp0_stage0_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state13_pp0_stage0_iter10 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state14_pp0_stage0_iter11 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state15_pp0_stage0_iter12 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state16_pp0_stage0_iter13 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state17_pp0_stage0_iter14 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state18_pp0_stage0_iter15 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state19_pp0_stage0_iter16 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state20_pp0_stage0_iter17 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state21_pp0_stage0_iter18 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state22_pp0_stage0_iter19 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state23_pp0_stage0_iter20 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state24_pp0_stage0_iter21 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state25_pp0_stage0_iter22 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state26_pp0_stage0_iter23 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state27_pp0_stage0_iter24 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state28_pp0_stage0_iter25 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state29_pp0_stage0_iter26 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state30_pp0_stage0_iter27 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state31_pp0_stage0_iter28 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state32_pp0_stage0_iter29 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state33_pp0_stage0_iter30 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state34_pp0_stage0_iter31 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state35_pp0_stage0_iter32 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state36_pp0_stage0_iter33_assign_proc : process(p_dst_data_stream_0_V_full_n, p_dst_data_stream_1_V_full_n, p_dst_data_stream_2_V_full_n, ap_reg_pp0_iter32_tmp_15_i_reg_947)
begin
ap_block_state36_pp0_stage0_iter33 <= (((ap_reg_pp0_iter32_tmp_15_i_reg_947 = ap_const_lv1_1) and (p_dst_data_stream_2_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter32_tmp_15_i_reg_947 = ap_const_lv1_1) and (p_dst_data_stream_1_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter32_tmp_15_i_reg_947 = ap_const_lv1_1) and (p_dst_data_stream_0_V_full_n = ap_const_logic_0)));
end process;
ap_block_state3_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage0_iter1_assign_proc : process(p_src_data_stream_0_V_empty_n, p_src_data_stream_1_V_empty_n, p_src_data_stream_2_V_empty_n, tmp_15_i_reg_947)
begin
ap_block_state4_pp0_stage0_iter1 <= (((tmp_15_i_reg_947 = ap_const_lv1_1) and (p_src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((tmp_15_i_reg_947 = ap_const_lv1_1) and (p_src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((tmp_15_i_reg_947 = ap_const_lv1_1) and (p_src_data_stream_0_V_empty_n = ap_const_logic_0)));
end process;
ap_block_state5_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage0_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp0_stage0_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_condition_pp0_exit_iter0_state3_assign_proc : process(tmp_15_i_fu_269_p2)
begin
if ((tmp_15_i_fu_269_p2 = ap_const_lv1_0)) then
ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_done_reg, tmp_i_fu_254_p2, ap_CS_fsm_state2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_254_p2 = ap_const_lv1_0))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter33, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter28, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9, ap_enable_reg_pp0_iter10, ap_enable_reg_pp0_iter11, ap_enable_reg_pp0_iter12, ap_enable_reg_pp0_iter13, ap_enable_reg_pp0_iter14, ap_enable_reg_pp0_iter15, ap_enable_reg_pp0_iter16, ap_enable_reg_pp0_iter17, ap_enable_reg_pp0_iter18, ap_enable_reg_pp0_iter19, ap_enable_reg_pp0_iter20, ap_enable_reg_pp0_iter21, ap_enable_reg_pp0_iter22, ap_enable_reg_pp0_iter23, ap_enable_reg_pp0_iter24, ap_enable_reg_pp0_iter25, ap_enable_reg_pp0_iter26, ap_enable_reg_pp0_iter27, ap_enable_reg_pp0_iter29, ap_enable_reg_pp0_iter30, ap_enable_reg_pp0_iter31, ap_enable_reg_pp0_iter32)
begin
if (((ap_enable_reg_pp0_iter33 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter32 = ap_const_logic_0) and (ap_enable_reg_pp0_iter31 = ap_const_logic_0) and (ap_enable_reg_pp0_iter30 = ap_const_logic_0) and (ap_enable_reg_pp0_iter29 = ap_const_logic_0) and (ap_enable_reg_pp0_iter27 = ap_const_logic_0) and (ap_enable_reg_pp0_iter26 = ap_const_logic_0) and (ap_enable_reg_pp0_iter25 = ap_const_logic_0) and (ap_enable_reg_pp0_iter24 = ap_const_logic_0) and (ap_enable_reg_pp0_iter23 = ap_const_logic_0) and (ap_enable_reg_pp0_iter22 = ap_const_logic_0) and (ap_enable_reg_pp0_iter21 = ap_const_logic_0) and (ap_enable_reg_pp0_iter20 = ap_const_logic_0) and (ap_enable_reg_pp0_iter19 = ap_const_logic_0) and (ap_enable_reg_pp0_iter18 = ap_const_logic_0) and (ap_enable_reg_pp0_iter17 = ap_const_logic_0) and (ap_enable_reg_pp0_iter16 = ap_const_logic_0) and (ap_enable_reg_pp0_iter15 = ap_const_logic_0) and (ap_enable_reg_pp0_iter14 = ap_const_logic_0) and (ap_enable_reg_pp0_iter13 = ap_const_logic_0) and (ap_enable_reg_pp0_iter12 = ap_const_logic_0) and (ap_enable_reg_pp0_iter11 = ap_const_logic_0) and (ap_enable_reg_pp0_iter10 = ap_const_logic_0) and (ap_enable_reg_pp0_iter9 = ap_const_logic_0) and (ap_enable_reg_pp0_iter8 = ap_const_logic_0) and (ap_enable_reg_pp0_iter7 = ap_const_logic_0) and (ap_enable_reg_pp0_iter6 = ap_const_logic_0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_0) and (ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter28 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_phi_reg_pp0_iter0_p_0150_0_i_i_reg_228 <= "XXXXXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter0_p_0211_0_i_i_reg_239 <= "XXXXXXXXXXXXXXXXXXXX";
ap_phi_reg_pp0_iter0_p_0332_0_i_i_reg_217 <= "XXXXXXXXXXXXXXXXXXXX";
ap_ready_assign_proc : process(tmp_i_fu_254_p2, ap_CS_fsm_state2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_254_p2 = ap_const_lv1_0))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
brmerge_i_i_i_fu_883_p2 <= (p_39_demorgan_i_not_i_fu_878_p2 or neg_src_not_i_i_i_fu_868_p2);
brmerge_i_i_not_i_i_s_fu_873_p2 <= (p_39_demorgan_i_i_i_i_reg_1204 and neg_src_not_i_i_i_fu_868_p2);
carry_1_fu_834_p2 <= (tmp_35_fu_808_p3 and tmp_10_i_i_i_fu_828_p2);
carry_fu_770_p2 <= (tmp_32_fu_744_p3 and tmp_12_i_i_i_fu_764_p2);
deleted_zeros_fu_786_p3 <=
Range1_all_ones_fu_776_p2 when (carry_fu_770_p2(0) = '1') else
Range1_all_zeros_fu_781_p2;
diff_fu_346_p2 <= std_logic_vector(unsigned(tmp_19_load_2_max_1_s_fu_330_p3) - unsigned(tmp_19_load_2_min_1_s_fu_340_p3));
grp_fu_393_ce_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
grp_fu_393_ce <= ap_const_logic_1;
else
grp_fu_393_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_393_p1 <= grp_fu_393_p10(8 - 1 downto 0);
grp_fu_393_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(diff_reg_1021),20));
grp_fu_470_ce_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
grp_fu_470_ce <= ap_const_logic_1;
else
grp_fu_470_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_470_p1 <= grp_fu_470_p10(9 - 1 downto 0);
grp_fu_470_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_Val2_23_reg_1027),20));
grp_fu_479_ce_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
grp_fu_479_ce <= ap_const_logic_1;
else
grp_fu_479_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_479_p1 <= grp_fu_479_p10(9 - 1 downto 0);
grp_fu_479_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(r_V_i_reg_1043),20));
grp_fu_912_p0 <= grp_fu_912_p00(20 - 1 downto 0);
grp_fu_912_p00 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_phi_reg_pp0_iter28_p_0332_0_i_i_reg_217),36));
grp_fu_912_p2 <= grp_fu_912_p20(27 - 1 downto 0);
grp_fu_912_p20 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_Val2_6_fu_532_p3),36));
i_cast_i_cast_fu_250_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_i_reg_195),16));
i_fu_259_p2 <= std_logic_vector(unsigned(i_i_reg_195) + unsigned(ap_const_lv11_1));
j_cast_i_cast_fu_265_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_i_reg_206),16));
j_fu_274_p2 <= std_logic_vector(unsigned(j_i_reg_206) + unsigned(ap_const_lv11_1));
neg_src_fu_858_p2 <= (tmp_13_i_i_i_fu_853_p2 and ap_reg_pp0_iter32_signbit_reg_1149);
neg_src_not_i_i_i_fu_868_p2 <= (signbit_not_fu_863_p2 or p_38_i_i_i_i_reg_1198);
overflow_fu_840_p2 <= (phitmp_i_i_i_i_reg_1187 or carry_1_fu_834_p2);
p_0292_0_i_i_fu_922_p0 <= p_0292_0_i_i_fu_922_p00(20 - 1 downto 0);
p_0292_0_i_i_fu_922_p00 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_0292_0_i_i_v_v_reg_1123),28));
p_0292_0_i_i_fu_922_p1 <= p_0292_0_i_i_fu_922_p10(8 - 1 downto 0);
p_0292_0_i_i_fu_922_p10 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter29_diff_reg_1021),28));
p_0292_0_i_i_v_v_fu_572_p3 <=
ap_phi_reg_pp0_iter29_p_0211_0_i_i_reg_239 when (tmp_30_i_fu_567_p2(0) = '1') else
ap_phi_reg_pp0_iter29_p_0150_0_i_i_reg_228;
p_38_i_i_i_i_fu_794_p2 <= (carry_fu_770_p2 and Range1_all_ones_fu_776_p2);
p_39_demorgan_i_i_i_i_fu_800_p2 <= (signbit_reg_1149 or deleted_zeros_fu_786_p3);
p_39_demorgan_i_not_i_fu_878_p2 <= (p_39_demorgan_i_i_i_i_reg_1204 xor ap_const_lv1_1);
p_Val2_23_fu_358_p2 <= std_logic_vector(unsigned(tmp_17_cast_i_fu_355_p1) + unsigned(tmp_16_cast_i_fu_352_p1));
p_Val2_29_fu_751_p2 <= std_logic_vector(unsigned(p_Val2_9_reg_1156) + unsigned(tmp_11_i_i_i_fu_741_p1));
p_Val2_34_fu_815_p2 <= std_logic_vector(unsigned(p_Val2_33_reg_1177) + unsigned(tmp_i_i66_i_fu_805_p1));
p_Val2_40_fu_845_p3 <=
ap_const_lv8_FF when (overflow_fu_840_p2(0) = '1') else
p_Val2_34_fu_815_p2;
p_Val2_6_fu_532_p3 <= (tmp_s_fu_524_p3 & ap_const_lv19_0);
p_Val2_7_fu_620_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_48_i_reg_1139),37));
p_Val2_s_fu_645_p2 <= std_logic_vector(unsigned(tmp_2_cast_cast_fu_637_p3) + unsigned(p_Val2_7_fu_620_p1));
p_dst_data_stream_0_V_blk_n_assign_proc : process(p_dst_data_stream_0_V_full_n, ap_block_pp0_stage0, ap_enable_reg_pp0_iter33, ap_reg_pp0_iter32_tmp_15_i_reg_947)
begin
if (((ap_reg_pp0_iter32_tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter33 = ap_const_logic_1))) then
p_dst_data_stream_0_V_blk_n <= p_dst_data_stream_0_V_full_n;
else
p_dst_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_dst_data_stream_0_V_din <=
p_mux_i_i_i_fu_889_p3 when (brmerge_i_i_i_fu_883_p2(0) = '1') else
p_i_i_i_fu_896_p3;
p_dst_data_stream_0_V_write_assign_proc : process(ap_enable_reg_pp0_iter33, ap_reg_pp0_iter32_tmp_15_i_reg_947, ap_block_pp0_stage0_11001)
begin
if (((ap_reg_pp0_iter32_tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter33 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_dst_data_stream_0_V_write <= ap_const_logic_1;
else
p_dst_data_stream_0_V_write <= ap_const_logic_0;
end if;
end process;
p_dst_data_stream_1_V_blk_n_assign_proc : process(p_dst_data_stream_1_V_full_n, ap_block_pp0_stage0, ap_enable_reg_pp0_iter33, ap_reg_pp0_iter32_tmp_15_i_reg_947)
begin
if (((ap_reg_pp0_iter32_tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter33 = ap_const_logic_1))) then
p_dst_data_stream_1_V_blk_n <= p_dst_data_stream_1_V_full_n;
else
p_dst_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_dst_data_stream_1_V_din <= ap_reg_pp0_iter32_p_Val2_36_reg_1033;
p_dst_data_stream_1_V_write_assign_proc : process(ap_enable_reg_pp0_iter33, ap_reg_pp0_iter32_tmp_15_i_reg_947, ap_block_pp0_stage0_11001)
begin
if (((ap_reg_pp0_iter32_tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter33 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_dst_data_stream_1_V_write <= ap_const_logic_1;
else
p_dst_data_stream_1_V_write <= ap_const_logic_0;
end if;
end process;
p_dst_data_stream_2_V_blk_n_assign_proc : process(p_dst_data_stream_2_V_full_n, ap_block_pp0_stage0, ap_enable_reg_pp0_iter33, ap_reg_pp0_iter32_tmp_15_i_reg_947)
begin
if (((ap_reg_pp0_iter32_tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter33 = ap_const_logic_1))) then
p_dst_data_stream_2_V_blk_n <= p_dst_data_stream_2_V_full_n;
else
p_dst_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_dst_data_stream_2_V_din <= p_Val2_40_reg_1210;
p_dst_data_stream_2_V_write_assign_proc : process(ap_enable_reg_pp0_iter33, ap_reg_pp0_iter32_tmp_15_i_reg_947, ap_block_pp0_stage0_11001)
begin
if (((ap_reg_pp0_iter32_tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter33 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_dst_data_stream_2_V_write <= ap_const_logic_1;
else
p_dst_data_stream_2_V_write <= ap_const_logic_0;
end if;
end process;
p_i_i_i_fu_896_p3 <=
ap_const_lv8_0 when (neg_src_fu_858_p2(0) = '1') else
p_Val2_29_reg_1192;
p_mux_i_i_i_fu_889_p3 <=
p_Val2_29_reg_1192 when (brmerge_i_i_not_i_i_s_fu_873_p2(0) = '1') else
ap_const_lv8_FF;
p_neg_i_fu_580_p2 <= std_logic_vector(unsigned(ap_const_lv36_0) - unsigned(t_V_reg_1108));
p_neg_t_i_fu_604_p2 <= std_logic_vector(unsigned(ap_const_lv36_0) - unsigned(tmp_2_fu_601_p1));
p_shl4_cast_i_fu_492_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(p_shl4_i_fu_485_p3),16));
p_shl4_i_fu_485_p3 <= (ap_reg_pp0_iter26_sub_V_reg_1068 & ap_const_lv6_0);
p_shl5_cast_i_fu_503_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(p_shl5_i_fu_496_p3),16));
p_shl5_i_fu_496_p3 <= (ap_reg_pp0_iter26_sub_V_reg_1068 & ap_const_lv2_0);
p_shl_cast_i_fu_697_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_shl_i_fu_690_p3),37));
p_shl_i_fu_690_p3 <= (p_0292_0_i_i_reg_1133 & ap_const_lv8_0);
p_src_cols_V_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_src_cols_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_src_cols_V_blk_n <= p_src_cols_V_empty_n;
else
p_src_cols_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_src_cols_V_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_src_rows_V_empty_n, p_src_cols_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_src_cols_V_read <= ap_const_logic_1;
else
p_src_cols_V_read <= ap_const_logic_0;
end if;
end process;
p_src_data_stream_0_V_blk_n_assign_proc : process(p_src_data_stream_0_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, tmp_15_i_reg_947)
begin
if (((tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
p_src_data_stream_0_V_blk_n <= p_src_data_stream_0_V_empty_n;
else
p_src_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_src_data_stream_0_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_15_i_reg_947, ap_block_pp0_stage0_11001)
begin
if (((tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_src_data_stream_0_V_read <= ap_const_logic_1;
else
p_src_data_stream_0_V_read <= ap_const_logic_0;
end if;
end process;
p_src_data_stream_1_V_blk_n_assign_proc : process(p_src_data_stream_1_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, tmp_15_i_reg_947)
begin
if (((tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
p_src_data_stream_1_V_blk_n <= p_src_data_stream_1_V_empty_n;
else
p_src_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_src_data_stream_1_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_15_i_reg_947, ap_block_pp0_stage0_11001)
begin
if (((tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_src_data_stream_1_V_read <= ap_const_logic_1;
else
p_src_data_stream_1_V_read <= ap_const_logic_0;
end if;
end process;
p_src_data_stream_2_V_blk_n_assign_proc : process(p_src_data_stream_2_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, tmp_15_i_reg_947)
begin
if (((tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
p_src_data_stream_2_V_blk_n <= p_src_data_stream_2_V_empty_n;
else
p_src_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_src_data_stream_2_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_15_i_reg_947, ap_block_pp0_stage0_11001)
begin
if (((tmp_15_i_reg_947 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_src_data_stream_2_V_read <= ap_const_logic_1;
else
p_src_data_stream_2_V_read <= ap_const_logic_0;
end if;
end process;
p_src_rows_V_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_src_rows_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_src_rows_V_blk_n <= p_src_rows_V_empty_n;
else
p_src_rows_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_src_rows_V_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_src_rows_V_empty_n, p_src_cols_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_src_rows_V_read <= ap_const_logic_1;
else
p_src_rows_V_read <= ap_const_logic_0;
end if;
end process;
phitmp_i_i_i_i_fu_735_p2 <= "0" when (tmp_6_fu_725_p4 = ap_const_lv10_0) else "1";
r_V_3_i_fu_507_p2 <= std_logic_vector(signed(p_shl4_cast_i_fu_492_p1) - signed(p_shl5_cast_i_fu_503_p1));
r_V_6_fu_701_p2 <= std_logic_vector(unsigned(p_shl_cast_i_fu_697_p1) - unsigned(OP2_V_4_cast73_i_fu_687_p1));
r_V_fu_623_p2 <= std_logic_vector(signed(p_Val2_7_fu_620_p1) + signed(ap_const_lv37_40000));
r_V_i_fu_380_p2 <= std_logic_vector(signed(ap_const_lv9_1FE) - signed(p_Val2_23_fu_358_p2));
sel_tmp1_fu_442_p2 <= (tmp_33_i_fu_399_p2 xor ap_const_lv1_1);
sel_tmp2_fu_448_p2 <= (tmp_37_i_fu_415_p2 and sel_tmp1_fu_442_p2);
sel_tmp_fu_434_p3 <=
tmp_36_i_fu_409_p2 when (tmp_33_i_fu_399_p2(0) = '1') else
tmp_43_i_fu_428_p2;
signbit_not_fu_863_p2 <= (ap_reg_pp0_iter32_signbit_reg_1149 xor ap_const_lv1_1);
sub_V_fu_454_p3 <=
tmp_40_i_fu_422_p2 when (sel_tmp2_fu_448_p2(0) = '1') else
sel_tmp_fu_434_p3;
tmp_10_i_i_i_fu_828_p2 <= (tmp_36_fu_820_p3 xor ap_const_lv1_1);
tmp_11_cast_fu_517_p3 <=
ap_const_lv8_0 when (ap_reg_pp0_iter27_tmp_33_i_reg_1057(0) = '1') else
ap_const_lv8_78;
tmp_11_i_i_i_fu_741_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_31_reg_1161),8));
tmp_12_i_i_i_fu_764_p2 <= (tmp_33_fu_756_p3 xor ap_const_lv1_1);
tmp_13_i_i_i_fu_853_p2 <= (p_38_i_i_i_i_reg_1198 xor ap_const_lv1_1);
tmp_15_i_fu_269_p2 <= "1" when (unsigned(j_cast_i_cast_fu_265_p1) < unsigned(p_src_cols_V_read_reg_928)) else "0";
tmp_16_cast_i_fu_352_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_19_load_2_max_1_s_reg_1007),9));
tmp_17_cast_i_fu_355_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_19_load_2_min_1_s_reg_1015),9));
tmp_19_load_2_max_1_s_fu_330_p3 <=
ap_reg_pp0_iter2_tmp_42_reg_974 when (tmp_44_2_i_fu_326_p2(0) = '1') else
G_1_reg_995;
tmp_19_load_2_min_1_s_fu_340_p3 <=
ap_reg_pp0_iter2_tmp_42_reg_974 when (tmp_50_2_i_fu_336_p2(0) = '1') else
G_2_reg_1001;
tmp_1_fu_513_p2 <= (ap_reg_pp0_iter27_tmp_37_i_reg_1063 or ap_reg_pp0_iter27_tmp_33_i_reg_1057);
tmp_25_i_fu_462_p2 <= "1" when (p_Val2_23_reg_1027 = ap_const_lv9_0) else "0";
tmp_28_i_fu_374_p2 <= "1" when (p_Val2_23_fu_358_p2 = ap_const_lv9_1FE) else "0";
tmp_29_fu_629_p3 <= r_V_fu_623_p2(36 downto 36);
tmp_2_cast_cast_fu_637_p3 <=
ap_const_lv37_5A00000 when (tmp_29_fu_629_p3(0) = '1') else
ap_const_lv37_0;
tmp_2_fu_601_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_lshr_i_reg_1128),36));
tmp_30_i_fu_567_p2 <= "1" when (unsigned(ap_reg_pp0_iter28_p_Val2_36_reg_1033) > unsigned(ap_const_lv8_80)) else "0";
tmp_31_i_fu_386_p2 <= "1" when (tmp_19_load_2_max_1_s_reg_1007 = tmp_19_load_2_min_1_s_reg_1015) else "0";
tmp_32_fu_744_p3 <= p_Val2_s_reg_1144(26 downto 26);
tmp_33_fu_756_p3 <= p_Val2_29_fu_751_p2(7 downto 7);
tmp_33_i_fu_399_p2 <= "1" when (tmp_19_load_2_max_1_s_reg_1007 = ap_reg_pp0_iter3_tmp_40_reg_956) else "0";
tmp_34_i_fu_403_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter3_tmp_41_reg_964),9));
tmp_35_fu_808_p3 <= r_V_6_reg_1172(26 downto 26);
tmp_35_i_fu_406_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter3_tmp_42_reg_974),9));
tmp_36_fu_820_p3 <= p_Val2_34_fu_815_p2(7 downto 7);
tmp_36_i_fu_409_p2 <= std_logic_vector(unsigned(tmp_34_i_fu_403_p1) - unsigned(tmp_35_i_fu_406_p1));
tmp_37_i_fu_415_p2 <= "1" when (tmp_19_load_2_max_1_s_reg_1007 = ap_reg_pp0_iter3_tmp_41_reg_964) else "0";
tmp_39_i_fu_419_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter3_tmp_40_reg_956),9));
tmp_3_fu_610_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter29_p_lshr_f_i_reg_1118),36));
tmp_40_i_fu_422_p2 <= std_logic_vector(unsigned(tmp_35_i_fu_406_p1) - unsigned(tmp_39_i_fu_419_p1));
tmp_43_i_fu_428_p2 <= std_logic_vector(unsigned(tmp_39_i_fu_419_p1) - unsigned(tmp_34_i_fu_403_p1));
tmp_44_1_i_fu_297_p2 <= "1" when (unsigned(tmp_41_reg_964) > unsigned(R_tmp_19_load_2_i_fu_292_p3)) else "0";
tmp_44_2_i_fu_326_p2 <= "1" when (unsigned(ap_reg_pp0_iter2_tmp_42_reg_974) > unsigned(G_1_reg_995)) else "0";
tmp_44_i_fu_280_p2 <= "1" when (unsigned(p_src_data_stream_0_V_dout) > unsigned(p_src_data_stream_2_V_dout)) else "0";
tmp_48_i_fu_613_p3 <=
p_neg_t_i_fu_604_p2 when (ap_reg_pp0_iter29_tmp_reg_1113(0) = '1') else
tmp_3_fu_610_p1;
tmp_50_1_i_fu_314_p2 <= "1" when (unsigned(tmp_41_reg_964) < unsigned(R_tmp_19_load_i_fu_309_p3)) else "0";
tmp_50_2_i_fu_336_p2 <= "1" when (unsigned(ap_reg_pp0_iter2_tmp_42_reg_974) < unsigned(G_2_reg_1001)) else "0";
tmp_50_i_fu_286_p2 <= "1" when (unsigned(p_src_data_stream_0_V_dout) < unsigned(p_src_data_stream_2_V_dout)) else "0";
tmp_6_fu_725_p4 <= r_V_6_fu_701_p2(36 downto 27);
tmp_i_fu_254_p2 <= "1" when (unsigned(i_cast_i_cast_fu_250_p1) < unsigned(p_src_rows_V_read_reg_933)) else "0";
tmp_i_i66_i_fu_805_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_34_reg_1182),8));
tmp_s_fu_524_p3 <=
tmp_11_cast_fu_517_p3 when (tmp_1_fu_513_p2(0) = '1') else
ap_const_lv8_F0;
end behav;
|
mit
|
2dda608d1cb5d65f8fe22f52d75a6e9d
| 0.604416 | 2.513748 | false | false | false | false |
Digilent/vivado-library
|
ip/MIPI_D_PHY_RX/hdl/SyncAsync.vhd
| 2 | 3,165 |
-------------------------------------------------------------------------------
--
-- File: SyncAsync.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module synchronizes the asynchronous signal (aIn) with the OutClk clock
-- domain and provides it on oOut. The number of FFs in the synchronizer chain
-- can be configured with kStages. The reset value for oOut can be configured
-- with kResetTo. The asynchronous reset (aReset) is always active-high.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SyncAsync is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2; --double sync by default
kResetPolarity : std_logic := '1'); --aReset active-high by default
Port (
aReset : in STD_LOGIC; -- active-high/active-low asynchronous reset
aIn : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end SyncAsync;
architecture Behavioral of SyncAsync is
signal oSyncStages : std_logic_vector(kStages-1 downto 0) := (others => kResetTo);
attribute ASYNC_REG : string;
attribute ASYNC_REG of oSyncStages: signal is "TRUE";
begin
Sync: process (OutClk, aReset)
begin
if (aReset = kResetPolarity) then
oSyncStages <= (others => kResetTo);
elsif Rising_Edge(OutClk) then
oSyncStages <= oSyncStages(oSyncStages'high-1 downto 0) & aIn;
end if;
end process Sync;
oOut <= oSyncStages(oSyncStages'high);
end Behavioral;
|
mit
|
70459a065a3c06bbf090b1b98d97e50d
| 0.663823 | 4.654412 | false | false | false | false |
Digilent/vivado-library
|
ip/axi_i2s_adi_1.2/hdl/axi_i2s_adi_S_AXI.vhd
| 2 | 14,057 |
--------------------------------------------------------------------------------
--
-- File:
-- axi_i2s_adi_S_AXI.vhd
--
-- Module:
-- AXIS I2S Controller AXI Slave Interface
--
-- Author:
-- Tinghui Wang (Steve)
-- Sam Bobrowicz
--
-- Description:
-- AXI-Lite Register Interface for AXI I2S Controller
--
-- Copyright notice:
-- Copyright (C) 2014 Digilent Inc.
--
-- License:
-- This program is free software; distributed under the terms of
-- BSD 3-clause license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-- IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
-- OF THE POSSIBILITY OF SUCH DAMAGE.
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity axi_i2s_adi_S_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
rd_addr : out integer range 0 to 12 - 1;
rd_data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
rd_ack : out std_logic;
wr_addr : out integer range 0 to 12 - 1;
wr_data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
wr_stb : out std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end axi_i2s_adi_S_AXI;
architecture arch_imp of axi_i2s_adi_S_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 3;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
wr_data <= S_AXI_WDATA;
wr_addr <= to_integer(unsigned(axi_awaddr((C_S_AXI_ADDR_WIDTH - 1) downto 2)));
wr_stb <= slv_reg_wren;
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
rd_ack <= slv_reg_rden;
reg_data_out <= rd_data;
rd_addr <= to_integer(unsigned(axi_araddr((C_S_AXI_ADDR_WIDTH - 1) downto 2)));
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
-- User logic ends
end arch_imp;
|
mit
|
27b333c1dd178508c95ccd518e825621
| 0.644021 | 3.568672 | false | false | false | false |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx
|
Frecuencimentro/top.vhd
| 1 | 3,206 |
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top is
port(
entrada : in std_logic;
clk : in std_logic;
reset : in std_logic;
led: OUT std_logic_vector(6 downto 0);
led_unidades: OUT std_logic_vector(1 DOWNTO 0);
selector : out std_logic_vector(3 DOWNTO 0)
);
end top;
architecture Behavioral of top is
component clk_mod
Port (
entrada: in STD_LOGIC;
reset : in STD_LOGIC;
salida : out STD_LOGIC
);
end component;
component CountEventsDown
Port (
entrada_clk : in STD_LOGIC;
reset : in STD_LOGIC;
salida : out STD_LOGIC
);
end component;
component Divisor
port(
activacion: in STD_LOGIC;
entrada: in STD_LOGIC_VECTOR (31 downto 0);
salida: out std_logic_vector(31 downto 0);
reset_cont: out STD_LOGIC
);
end component;
component CountEvents
port(
Entrada: in std_logic;
Reset: in std_logic;
Reset_cont: in std_logic;
Output: out std_logic_vector(0 to 31)
);
end component;
component EscaladoPrePresentacion
PORT(
entrada_frec: in std_logic_vector(31 downto 0);
salida_frec: out std_logic_vector(15 downto 0);
salida_uds: out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
COMPONENT ControladorSegmentos
Port (
code : IN std_logic_vector(15 downto 0);
clk: in std_logic;
led : OUT std_logic_vector(6 downto 0);
selector : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
COMPONENT decoder
PORT(
code : IN std_logic_vector(3 downto 0);
led : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
signal s_clk_mod: STD_LOGIC;
signal s_act: STD_LOGIC;
signal s_reset_cont:STD_LOGIC;
signal s_contup: STD_LOGIC_VECTOR(31 downto 0);
signal s_frec: STD_LOGIC_VECTOR(31 downto 0);
signal s_frec_esc: STD_LOGIC_VECTOR(15 downto 0);
begin
clk_modificado: clk_mod PORT MAP(
entrada => clk,
reset => reset,
salida => s_clk_mod);
countdown: CountEventsDown PORT MAP(
entrada_clk => s_clk_mod,
reset => reset,
salida => s_act);
div: Divisor PORT MAP(
activacion => s_act,
entrada => s_contup,
salida => s_frec,
reset_cont => s_reset_cont);
countup: CountEvents PORT MAP(
entrada => entrada,
reset => reset,
reset_cont => s_reset_cont,
output => s_contup);
escalado: EscaladoPrePresentacion PORT MAP(
entrada_frec => s_frec,
salida_frec => s_frec_esc,
salida_uds => led_unidades);
Segmentos: ControladorSegmentos Port MAP(
code => s_frec_esc,
clk => s_clk_mod,
led => led,
selector => selector);
end Behavioral;
|
gpl-2.0
|
136be40791028ab159bc071c96a9396c
| 0.596382 | 3.562222 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_gamma_correction_1_0/hdl/vhdl/fifo_w16_d3_A.vhd
| 1 | 4,437 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w16_d3_A_shiftReg is
generic (
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w16_d3_A_shiftReg;
architecture rtl of fifo_w16_d3_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_w16_d3_A is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w16_d3_A is
component fifo_w16_d3_A_shiftReg is
generic (
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w16_d3_A_shiftReg : fifo_w16_d3_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
8c92a4c16fb912d0c5901f5d2d097ab9
| 0.52558 | 3.4637 | false | false | false | false |
grafi-tt/Maizul
|
src/Unit/FPU/FMul.vhd
| 1 | 3,908 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FMul is
port (
clk : in std_logic;
flt_in1 : in std_logic_vector(31 downto 0);
flt_in2 : in std_logic_vector(31 downto 0);
flt_out : out std_logic_vector(31 downto 0));
end FMul;
architecture dataflow_pipeline of FMul is
signal s1_sgn : std_logic;
signal s1_exp_add : unsigned(8 downto 0);
signal s1_frc_all : unsigned(47 downto 0);
signal s1_zero : std_logic;
signal s2_sgn : std_logic := '0';
signal s2_exp_add : unsigned(8 downto 0) := (others => '0');
signal s2_frc_all : unsigned(47 downto 0) := (others => '0');
signal s2_exp : unsigned(9 downto 0) := (others => '0');
signal s2_exp_up : unsigned(9 downto 0) := (others => '0');
signal s2_ulp : unsigned(24 downto 0) := (others => '0');
signal s2_frc : unsigned(24 downto 0) := (others => '0');
signal s2_frc_up : unsigned(24 downto 0) := (others => '0');
signal s2_zero : std_logic := '0';
signal s2_tail_any : std_logic := '0';
signal s2_round : std_logic := '0';
signal s3_sgn : std_logic := '0';
signal s3_exp : unsigned(9 downto 0) := (others => '0');
signal s3_exp_up : unsigned(9 downto 0) := (others => '0');
signal s3_frc : unsigned(24 downto 0) := (others => '0');
signal s3_frc_up : unsigned(24 downto 0) := (others => '0');
signal s3_round : std_logic := '0';
signal s3_frc_out_tmp : std_logic_vector(24 downto 0);
signal s3_exp_out_tmp : std_logic_vector(9 downto 0);
signal s3_frc_out : std_logic_vector(22 downto 0);
signal s3_exp_out : std_logic_vector(7 downto 0);
constant zero_22 : unsigned(21 downto 0) := (others => '0');
begin
s1_sgn <= flt_in1(31) xor flt_in2(31);
s1_exp_add <= unsigned("0" & flt_in1(30 downto 23)) + unsigned("0" & flt_in2(30 downto 23));
s1_frc_all <= unsigned('1' & flt_in1(22 downto 0)) * unsigned('1' & flt_in2(22 downto 0));
s1_zero <= '1' when flt_in1(30 downto 23) = "00000000" or flt_in2(30 downto 23) = "00000000" else '0';
pipe1 : process(clk)
begin
if rising_edge(clk) then
s2_sgn <= s1_sgn;
s2_exp_add <= s1_exp_add;
s2_frc_all <= s1_frc_all;
s2_zero <= s1_zero;
end if;
end process;
s2_exp <= (('0' & s2_exp_add) - "0001111111") or (s2_zero & "000000000");
s2_exp_up <= (('0' & s2_exp_add) - "0001111110") or (s2_zero & "000000000");
s2_frc <= s2_frc_all(47 downto 23);
s2_ulp <= x"00000" & "00001" when s2_frc_all(47) = '0' else x"00000" & "00010";
s2_frc_up <= s2_frc + s2_ulp;
s2_tail_any <= '0' when s2_frc_all(21 downto 0) = zero_22 else '1';
s2_round <= (s2_frc_all(22) and s2_tail_any) or (s2_frc_all(23) and s2_frc_all(22)) when s2_frc_all(47) = '0' else
(s2_frc_all(23) and (s2_frc_all(22) or s2_tail_any)) or (s2_frc_all(24) and s2_frc_all(23));
pipe2 : process(clk)
begin
if rising_edge(clk) then
s3_sgn <= s2_sgn;
s3_exp <= s2_exp;
s3_exp_up <= s2_exp_up;
s3_frc <= s2_frc;
s3_frc_up <= s2_frc_up;
s3_round <= s2_round;
end if;
end process;
s3_frc_out_tmp <= std_logic_vector(s3_frc) when s3_round = '0' else std_logic_vector(s3_frc_up);
s3_exp_out_tmp <= std_logic_vector(s3_exp) when s3_frc_out_tmp(24) = '0' else std_logic_vector(s3_exp_up);
s3_exp_out <= "00000000" when s3_exp_out_tmp(9) = '1' else
"11111111" when s3_exp_out_tmp(8) = '1' else
s3_exp_out_tmp(7 downto 0);
s3_frc_out <= (others => '0') when s3_exp_out = "00000000" or s3_exp_out = "11111111" else
s3_frc_out_tmp(22 downto 0) when s3_frc_out_tmp(24) = '0' else
s3_frc_out_tmp(23 downto 1);
flt_out <= s3_sgn & s3_exp_out & s3_frc_out;
end dataflow_pipeline;
|
bsd-2-clause
|
329e564b4fdd67a9526eaa18db14bce2
| 0.565251 | 2.70076 | false | false | false | false |
Digilent/vivado-library
|
ip/MIPI_CSI_2_RX/hdl/MIPI_CSI2_RxTop.vhd
| 1 | 10,367 |
-------------------------------------------------------------------------------
--
-- File: MIPI_CSI2_RxTop.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI CSI-2 Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mipi_csi2_rx_top is
Generic (
kVersionMajor : natural := 0; -- TCL-propagated from VLNV
kVersionMinor : natural := 0; -- TCL-propagated from VLNV
kTargetDT : string := "RAW10";
kGenerateAXIL : boolean := false;
kDebug : boolean := true;
--PPI
kLaneCount : natural range 1 to 4 := 2; --[1,2,4]
--Video Format
C_M_AXIS_COMPONENT_WIDTH : natural := 10; -- [8,10]
C_M_AXIS_TDATA_WIDTH : natural := 40;
C_M_MAX_SAMPLES_PER_CLOCK : natural := 4;
-- Parameters of Axi Slave Bus Interface S_AXI_LITE
C_S_AXI_LITE_DATA_WIDTH : integer := 32;
C_S_AXI_LITE_ADDR_WIDTH : integer := 4
);
Port (
--PPI
RxByteClkHS : in STD_LOGIC;
aClkStopstate : in std_logic;
aRxClkActiveHS : in std_logic;
RxDataHSD0 : in STD_LOGIC_VECTOR (7 downto 0);
RxSyncHSD0 : in STD_LOGIC;
RxValidHSD0 : in STD_LOGIC;
RxActiveHSD0 : in STD_LOGIC;
aD0Enable : out STD_LOGIC;
RxDataHSD1 : in STD_LOGIC_VECTOR (7 downto 0);
RxSyncHSD1 : in STD_LOGIC;
RxValidHSD1 : in STD_LOGIC;
RxActiveHSD1 : in STD_LOGIC;
aD1Enable : out STD_LOGIC;
RxDataHSD2 : in STD_LOGIC_VECTOR (7 downto 0);
RxSyncHSD2 : in STD_LOGIC;
RxValidHSD2 : in STD_LOGIC;
RxActiveHSD2 : in STD_LOGIC;
aD2Enable : out STD_LOGIC;
RxDataHSD3 : in STD_LOGIC_VECTOR (7 downto 0);
RxSyncHSD3 : in STD_LOGIC;
RxValidHSD3 : in STD_LOGIC;
RxActiveHSD3 : in STD_LOGIC;
aD3Enable : out STD_LOGIC;
aClkEnable : out STD_LOGIC;
--axi stream signals
m_axis_video_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_video_tvalid : out std_logic;
m_axis_video_tready : in std_logic;
m_axis_video_tlast : out std_logic;
m_axis_video_tuser : out std_logic_vector(0 downto 0);
video_aresetn : in std_logic; --available when the AXI-Lite interface is disabled
video_aclk : in std_logic;
-- Ports of Axi Slave Bus Interface S_AXI_LITE
s_axi_lite_aclk : in std_logic;
s_axi_lite_aresetn : in std_logic;
s_axi_lite_awaddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_awprot : in std_logic_vector(2 downto 0);
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_wstrb : in std_logic_vector((C_S_AXI_LITE_DATA_WIDTH/8)-1 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_araddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_arprot : in std_logic_vector(2 downto 0);
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_rdata : out std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic
);
end mipi_csi2_rx_top;
architecture Behavioral of mipi_csi2_rx_top is
constant kMaxLaneCount : natural := 4;
signal rbRxDataHS : STD_LOGIC_VECTOR (8 * kLaneCount - 1 downto 0);
signal rbRxSyncHS : STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
signal rbRxValidHS : STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
signal rbRxActiveHS : STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
signal aDEnable : STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
signal xSoftEnable, xSoftRst, vSoftEnable, vSoftRst, vRst_n : std_logic;
begin
InputDataGen: for i in 0 to kLaneCount-1 generate
DataLane0: if i = 0 generate
rbRxDataHS(8 * (i + 1) - 1 downto 8 * i) <= RxDataHSD0;
rbRxValidHS(i) <= RxValidHSD0;
rbRxActiveHS(i) <= RxActiveHSD0;
rbRxSyncHS(i) <= RxSyncHSD0;
aD0Enable <= aDEnable(i);
end generate;
DataLane1: if i = 1 generate
rbRxDataHS(8 * (i + 1) - 1 downto 8 * i) <= RxDataHSD1;
rbRxValidHS(i) <= RxValidHSD1;
rbRxActiveHS(i) <= RxActiveHSD1;
rbRxSyncHS(i) <= RxSyncHSD1;
aD1Enable <= aDEnable(i);
end generate;
DataLane2: if i = 2 generate
rbRxDataHS(8 * (i + 1) - 1 downto 8 * i) <= RxDataHSD2;
rbRxValidHS(i) <= RxValidHSD2;
rbRxActiveHS(i) <= RxActiveHSD2;
rbRxSyncHS(i) <= RxSyncHSD2;
aD2Enable <= aDEnable(i);
end generate;
DataLane3: if i = 3 generate
rbRxDataHS(8 * (i + 1) - 1 downto 8 * i) <= RxDataHSD3;
rbRxValidHS(i) <= RxValidHSD3;
rbRxActiveHS(i) <= RxActiveHSD3;
rbRxSyncHS(i) <= RxSyncHSD3;
aD3Enable <= aDEnable(i);
end generate;
end generate InputDataGen;
MIPI_CSI2_Rx_inst: entity work.MIPI_CSI2_Rx
Generic map(
kTargetDT => kTargetDT,
kDebug => kDebug,
--PPI
kLaneCount => kLaneCount, --[1,2,4]
--Video Format
C_M_AXIS_COMPONENT_WIDTH => C_M_AXIS_COMPONENT_WIDTH, -- [8,10]
C_M_AXIS_TDATA_WIDTH => C_M_AXIS_TDATA_WIDTH,
C_M_MAX_SAMPLES_PER_CLOCK => C_M_MAX_SAMPLES_PER_CLOCK
)
Port map(
--PPI
RxByteClkHS => RxByteClkHS,
aClkStopstate => aClkStopstate,
aRxClkActiveHS => aRxClkActiveHS,
rbRxDataHS => rbRxDataHS,
rbRxSyncHS => rbRxSyncHS,
rbRxValidHS => rbRxValidHS,
rbRxActiveHS => rbRxActiveHS,
aDEnable => aDEnable,
aClkEnable => aClkEnable,
--axi stream signals
m_axis_video_tdata => m_axis_video_tdata,
m_axis_video_tvalid => m_axis_video_tvalid,
m_axis_video_tready => m_axis_video_tready,
m_axis_video_tlast => m_axis_video_tlast,
m_axis_video_tuser => m_axis_video_tuser,
video_aresetn => vRst_n,
video_aclk => video_aclk,
vEnable => vSoftEnable
);
-------------------------------------------------------------------------------
-- AXI-Lite interface for control and status
-------------------------------------------------------------------------------
YesAXILITE: if kGenerateAXIL generate
AXI_Lite_Control: entity work.MIPI_CSI_2_RX_S_AXI_LITE
generic map (
kVersionMajor => kVersionMajor,
kVersionMinor => kVersionMinor,
C_S_AXI_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH
)
port map (
xEnable => xSoftEnable,
xRst => xSoftRst,
S_AXI_ACLK => s_axi_lite_aclk,
S_AXI_ARESETN => s_axi_lite_aresetn,
S_AXI_AWADDR => s_axi_lite_awaddr,
S_AXI_AWPROT => s_axi_lite_awprot,
S_AXI_AWVALID => s_axi_lite_awvalid,
S_AXI_AWREADY => s_axi_lite_awready,
S_AXI_WDATA => s_axi_lite_wdata,
S_AXI_WSTRB => s_axi_lite_wstrb,
S_AXI_WVALID => s_axi_lite_wvalid,
S_AXI_WREADY => s_axi_lite_wready,
S_AXI_BRESP => s_axi_lite_bresp,
S_AXI_BVALID => s_axi_lite_bvalid,
S_AXI_BREADY => s_axi_lite_bready,
S_AXI_ARADDR => s_axi_lite_araddr,
S_AXI_ARPROT => s_axi_lite_arprot,
S_AXI_ARVALID => s_axi_lite_arvalid,
S_AXI_ARREADY => s_axi_lite_arready,
S_AXI_RDATA => s_axi_lite_rdata,
S_AXI_RRESP => s_axi_lite_rresp,
S_AXI_RVALID => s_axi_lite_rvalid,
S_AXI_RREADY => s_axi_lite_rready
);
CoreSoftReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => xSoftRst,
OutClk => video_aclk,
oRst => vSoftRst);
SyncAsyncClkEnable: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => '0', --lane-level enable
aIn => xSoftEnable,
OutClk => video_aclk,
oOut => vSoftEnable);
GlitchFreeReset: process(video_aclk)
begin
if Rising_Edge(video_aclk) then
vRst_n <= video_aresetn and not vSoftRst; --combinational logic can produce glitches
end if;
end process;
end generate;
NoAXILITE: if not kGenerateAXIL generate
vSoftEnable <= '1';
vRst_n <= video_aresetn;
end generate;
end Behavioral;
|
mit
|
f7f9d1e08360e916d34fdf105b622774
| 0.597087 | 3.633719 | false | false | false | false |
Digilent/vivado-library
|
ip/video_scaler/hdl/vhdl/video_scaler_mul_jbC.vhd
| 1 | 2,546 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity video_scaler_mul_jbC_MulnS_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(32 - 1 downto 0);
b: in std_logic_vector(16 - 1 downto 0);
p: out std_logic_vector(32 - 1 downto 0));
end entity;
architecture behav of video_scaler_mul_jbC_MulnS_0 is
signal tmp_product : std_logic_vector(32 - 1 downto 0);
signal a_i : std_logic_vector(32 - 1 downto 0);
signal b_i : std_logic_vector(16 - 1 downto 0);
signal p_tmp : std_logic_vector(32 - 1 downto 0);
signal a_reg0 : std_logic_vector(32 - 1 downto 0);
signal b_reg0 : std_logic_vector(16 - 1 downto 0);
signal buff0 : std_logic_vector(32 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff0;
tmp_product <= std_logic_vector(resize(unsigned(std_logic_vector(signed(a_reg0) * signed(b_reg0))), 32));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg0 <= a_i;
b_reg0 <= b_i;
buff0 <= tmp_product;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity video_scaler_mul_jbC is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of video_scaler_mul_jbC is
component video_scaler_mul_jbC_MulnS_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
video_scaler_mul_jbC_MulnS_0_U : component video_scaler_mul_jbC_MulnS_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
|
mit
|
6c2a8150e12cd26ca10ce44791cc2ce7
| 0.546347 | 3.367725 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_contrast_stretch_1_0/hdl/vhdl/CvtColor_1.vhd
| 1 | 58,443 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CvtColor_1 is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_src_rows_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
p_src_rows_V_empty_n : IN STD_LOGIC;
p_src_rows_V_read : OUT STD_LOGIC;
p_src_cols_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
p_src_cols_V_empty_n : IN STD_LOGIC;
p_src_cols_V_read : OUT STD_LOGIC;
p_src_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_0_V_empty_n : IN STD_LOGIC;
p_src_data_stream_0_V_read : OUT STD_LOGIC;
p_src_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_1_V_empty_n : IN STD_LOGIC;
p_src_data_stream_1_V_read : OUT STD_LOGIC;
p_src_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_2_V_empty_n : IN STD_LOGIC;
p_src_data_stream_2_V_read : OUT STD_LOGIC;
p_dst_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_0_V_full_n : IN STD_LOGIC;
p_dst_data_stream_0_V_write : OUT STD_LOGIC;
p_dst_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_1_V_full_n : IN STD_LOGIC;
p_dst_data_stream_1_V_write : OUT STD_LOGIC;
p_dst_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_2_V_full_n : IN STD_LOGIC;
p_dst_data_stream_2_V_write : OUT STD_LOGIC );
end;
architecture behav of CvtColor_1 is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv29_1322D0 : STD_LOGIC_VECTOR (28 downto 0) := "00000000100110010001011010000";
constant ap_const_lv28_74BC6 : STD_LOGIC_VECTOR (27 downto 0) := "0000000001110100101111000110";
constant ap_const_lv30_259168 : STD_LOGIC_VECTOR (29 downto 0) := "000000001001011001000101101000";
constant ap_const_lv32_2DA1CA : STD_LOGIC_VECTOR (31 downto 0) := "00000000001011011010000111001010";
constant ap_const_lv32_20000000 : STD_LOGIC_VECTOR (31 downto 0) := "00100000000000000000000000000000";
constant ap_const_lv32_241893 : STD_LOGIC_VECTOR (31 downto 0) := "00000000001001000001100010010011";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal p_src_rows_V_blk_n : STD_LOGIC;
signal p_src_cols_V_blk_n : STD_LOGIC;
signal p_src_data_stream_0_V_blk_n : STD_LOGIC;
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_block_pp0_stage0 : BOOLEAN;
signal tmp_36_i_reg_692 : STD_LOGIC_VECTOR (0 downto 0);
signal p_src_data_stream_1_V_blk_n : STD_LOGIC;
signal p_src_data_stream_2_V_blk_n : STD_LOGIC;
signal p_dst_data_stream_0_V_blk_n : STD_LOGIC;
signal ap_enable_reg_pp0_iter8 : STD_LOGIC := '0';
signal ap_reg_pp0_iter7_tmp_36_i_reg_692 : STD_LOGIC_VECTOR (0 downto 0);
signal p_dst_data_stream_1_V_blk_n : STD_LOGIC;
signal p_dst_data_stream_2_V_blk_n : STD_LOGIC;
signal j_i_reg_176 : STD_LOGIC_VECTOR (10 downto 0);
signal p_src_cols_V_read_reg_673 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_block_state1 : BOOLEAN;
signal p_src_rows_V_read_reg_678 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_i_fu_191_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal i_fu_196_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal i_reg_687 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_36_i_fu_206_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state5_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_state6_pp0_stage0_iter3 : BOOLEAN;
signal ap_block_state7_pp0_stage0_iter4 : BOOLEAN;
signal ap_block_state8_pp0_stage0_iter5 : BOOLEAN;
signal ap_block_state9_pp0_stage0_iter6 : BOOLEAN;
signal ap_block_state10_pp0_stage0_iter7 : BOOLEAN;
signal ap_block_state11_pp0_stage0_iter8 : BOOLEAN;
signal ap_block_pp0_stage0_11001 : BOOLEAN;
signal ap_reg_pp0_iter1_tmp_36_i_reg_692 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter2_tmp_36_i_reg_692 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter3_tmp_36_i_reg_692 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter4_tmp_36_i_reg_692 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter5_tmp_36_i_reg_692 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter6_tmp_36_i_reg_692 : STD_LOGIC_VECTOR (0 downto 0);
signal j_fu_211_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal tmp_23_reg_701 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_tmp_23_reg_701 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_23_reg_701 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_tmp_23_reg_701 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_24_reg_707 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_tmp_24_reg_707 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_24_reg_707 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_25_reg_712 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_tmp_25_reg_712 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_25_reg_712 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_tmp_25_reg_712 : STD_LOGIC_VECTOR (7 downto 0);
signal r_V_6_i_fu_626_p2 : STD_LOGIC_VECTOR (28 downto 0);
signal r_V_6_i_reg_718 : STD_LOGIC_VECTOR (28 downto 0);
signal grp_fu_632_p3 : STD_LOGIC_VECTOR (28 downto 0);
signal p_Val2_2_reg_723 : STD_LOGIC_VECTOR (28 downto 0);
signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
signal grp_fu_639_p3 : STD_LOGIC_VECTOR (29 downto 0);
signal r_V_1_reg_728 : STD_LOGIC_VECTOR (29 downto 0);
signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
signal p_Val2_4_reg_733 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_reg_738 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_20_fu_280_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Val2_20_reg_743 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_p_Val2_20_reg_743 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_p_Val2_20_reg_743 : STD_LOGIC_VECTOR (7 downto 0);
signal i_op_assign_5_fu_295_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal i_op_assign_5_reg_748 : STD_LOGIC_VECTOR (8 downto 0);
signal i_op_assign_6_fu_304_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal i_op_assign_6_reg_753 : STD_LOGIC_VECTOR (8 downto 0);
signal grp_fu_649_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal r_V_2_reg_758 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter6 : STD_LOGIC := '0';
signal signbit_reg_763 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter7_signbit_reg_763 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_7_reg_770 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_13_reg_775 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_s_reg_780 : STD_LOGIC_VECTOR (1 downto 0);
signal grp_fu_661_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal r_V_3_reg_786 : STD_LOGIC_VECTOR (31 downto 0);
signal signbit_1_reg_791 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter7_signbit_1_reg_791 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_16_reg_798 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_17_reg_803 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_reg_808 : STD_LOGIC_VECTOR (1 downto 0);
signal p_Val2_8_fu_390_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Val2_8_reg_814 : STD_LOGIC_VECTOR (7 downto 0);
signal p_38_i_i_i_i_fu_433_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_38_i_i_i_i_reg_820 : STD_LOGIC_VECTOR (0 downto 0);
signal p_39_demorgan_i_i_i_i_fu_439_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_39_demorgan_i_i_i_i_reg_826 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_18_fu_454_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Val2_18_reg_832 : STD_LOGIC_VECTOR (7 downto 0);
signal p_38_i_i_i15_i_fu_497_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_38_i_i_i15_i_reg_838 : STD_LOGIC_VECTOR (0 downto 0);
signal p_39_demorgan_i_i_i_fu_503_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_39_demorgan_i_i_i_reg_844 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_pp0_stage0_subdone : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC;
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter5 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter7 : STD_LOGIC := '0';
signal i_i_reg_165 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_CS_fsm_state12 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none";
signal ap_block_pp0_stage0_01001 : BOOLEAN;
signal i_cast_i_cast_fu_187_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal j_cast_i_cast_fu_202_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_19_i_i_i_fu_245_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Val2_5_fu_255_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_10_fu_248_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_11_fu_260_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Result_2_i_i_not_fu_268_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal not_carry_i_fu_274_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_30_cast_i_fu_288_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_31_cast_i_fu_291_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_33_cast_i_fu_301_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_16_i_i_i_fu_380_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_15_fu_395_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_14_fu_383_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_17_i_i_i_fu_403_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal carry_fu_409_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal Range1_all_ones_fu_415_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal Range1_all_zeros_fu_420_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal deleted_zeros_fu_425_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_16_i_i6_i_fu_444_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_19_fu_459_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_18_fu_447_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_17_i_i10_i_fu_467_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal carry_1_fu_473_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal Range1_all_ones_1_fu_479_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal Range1_all_zeros_1_fu_484_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal deleted_zeros_1_fu_489_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_18_i_i_i_fu_508_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal signbit_not_i_i_fu_518_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal neg_src_not_i_i_i_fu_523_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_39_demorgan_i_not_i_fu_533_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i_not_i_i_s_fu_528_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal neg_src_fu_513_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i_i_fu_538_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_mux_i_i2_i_fu_544_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_i_i_i_fu_551_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_18_i_i16_i_fu_567_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal signbit_not_i19_i_fu_577_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal neg_src_not_i_i20_i_fu_582_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_39_demorgan_i_not_i_1_fu_592_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i_not_i_i2_fu_587_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal neg_src_4_fu_572_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i23_i_fu_597_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_mux_i_i24_i_fu_603_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_i_i25_i_fu_610_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal r_V_6_i_fu_626_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal r_V_6_i_fu_626_p1 : STD_LOGIC_VECTOR (21 downto 0);
signal grp_fu_632_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_632_p1 : STD_LOGIC_VECTOR (19 downto 0);
signal grp_fu_639_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_639_p1 : STD_LOGIC_VECTOR (22 downto 0);
signal grp_fu_639_p2 : STD_LOGIC_VECTOR (28 downto 0);
signal grp_fu_649_p1 : STD_LOGIC_VECTOR (22 downto 0);
signal grp_fu_649_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal grp_fu_661_p1 : STD_LOGIC_VECTOR (22 downto 0);
signal grp_fu_661_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
signal grp_fu_632_p00 : STD_LOGIC_VECTOR (27 downto 0);
signal grp_fu_639_p00 : STD_LOGIC_VECTOR (29 downto 0);
signal grp_fu_639_p20 : STD_LOGIC_VECTOR (29 downto 0);
signal r_V_6_i_fu_626_p00 : STD_LOGIC_VECTOR (28 downto 0);
component hls_contrast_strebkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (7 downto 0);
din1 : IN STD_LOGIC_VECTOR (21 downto 0);
dout : OUT STD_LOGIC_VECTOR (28 downto 0) );
end component;
component hls_contrast_strecud IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (7 downto 0);
din1 : IN STD_LOGIC_VECTOR (19 downto 0);
din2 : IN STD_LOGIC_VECTOR (28 downto 0);
dout : OUT STD_LOGIC_VECTOR (28 downto 0) );
end component;
component hls_contrast_stredEe IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (7 downto 0);
din1 : IN STD_LOGIC_VECTOR (22 downto 0);
din2 : IN STD_LOGIC_VECTOR (28 downto 0);
dout : OUT STD_LOGIC_VECTOR (29 downto 0) );
end component;
component hls_contrast_streeOg IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (8 downto 0);
din1 : IN STD_LOGIC_VECTOR (22 downto 0);
din2 : IN STD_LOGIC_VECTOR (30 downto 0);
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
hls_contrast_strebkb_U30 : component hls_contrast_strebkb
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 8,
din1_WIDTH => 22,
dout_WIDTH => 29)
port map (
din0 => r_V_6_i_fu_626_p0,
din1 => r_V_6_i_fu_626_p1,
dout => r_V_6_i_fu_626_p2);
hls_contrast_strecud_U31 : component hls_contrast_strecud
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 8,
din1_WIDTH => 20,
din2_WIDTH => 29,
dout_WIDTH => 29)
port map (
din0 => grp_fu_632_p0,
din1 => grp_fu_632_p1,
din2 => r_V_6_i_reg_718,
dout => grp_fu_632_p3);
hls_contrast_stredEe_U32 : component hls_contrast_stredEe
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 8,
din1_WIDTH => 23,
din2_WIDTH => 29,
dout_WIDTH => 30)
port map (
din0 => grp_fu_639_p0,
din1 => grp_fu_639_p1,
din2 => grp_fu_639_p2,
dout => grp_fu_639_p3);
hls_contrast_streeOg_U33 : component hls_contrast_streeOg
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 9,
din1_WIDTH => 23,
din2_WIDTH => 31,
dout_WIDTH => 32)
port map (
din0 => i_op_assign_5_reg_748,
din1 => grp_fu_649_p1,
din2 => grp_fu_649_p2,
dout => grp_fu_649_p3);
hls_contrast_streeOg_U34 : component hls_contrast_streeOg
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 9,
din1_WIDTH => 23,
din2_WIDTH => 31,
dout_WIDTH => 32)
port map (
din0 => i_op_assign_6_reg_753,
din1 => grp_fu_661_p1,
din2 => grp_fu_661_p2,
dout => grp_fu_661_p3);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_continue = ap_const_logic_1)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_191_p2 = ap_const_lv1_0))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((tmp_i_fu_191_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3)) then
ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state3);
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end if;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter6 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter7 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter8 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7;
elsif (((tmp_i_fu_191_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_enable_reg_pp0_iter8 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
i_i_reg_165_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state12)) then
i_i_reg_165 <= i_reg_687;
elsif ((not(((ap_start = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
i_i_reg_165 <= ap_const_lv11_0;
end if;
end if;
end process;
j_i_reg_176_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_i_fu_206_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
j_i_reg_176 <= j_fu_211_p2;
elsif (((tmp_i_fu_191_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
j_i_reg_176 <= ap_const_lv11_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_reg_pp0_iter1_tmp_36_i_reg_692 <= tmp_36_i_reg_692;
tmp_36_i_reg_692 <= tmp_36_i_fu_206_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_0 = ap_block_pp0_stage0_11001)) then
ap_reg_pp0_iter2_tmp_23_reg_701 <= tmp_23_reg_701;
ap_reg_pp0_iter2_tmp_24_reg_707 <= tmp_24_reg_707;
ap_reg_pp0_iter2_tmp_25_reg_712 <= tmp_25_reg_712;
ap_reg_pp0_iter2_tmp_36_i_reg_692 <= ap_reg_pp0_iter1_tmp_36_i_reg_692;
ap_reg_pp0_iter3_tmp_23_reg_701 <= ap_reg_pp0_iter2_tmp_23_reg_701;
ap_reg_pp0_iter3_tmp_24_reg_707 <= ap_reg_pp0_iter2_tmp_24_reg_707;
ap_reg_pp0_iter3_tmp_25_reg_712 <= ap_reg_pp0_iter2_tmp_25_reg_712;
ap_reg_pp0_iter3_tmp_36_i_reg_692 <= ap_reg_pp0_iter2_tmp_36_i_reg_692;
ap_reg_pp0_iter4_tmp_23_reg_701 <= ap_reg_pp0_iter3_tmp_23_reg_701;
ap_reg_pp0_iter4_tmp_25_reg_712 <= ap_reg_pp0_iter3_tmp_25_reg_712;
ap_reg_pp0_iter4_tmp_36_i_reg_692 <= ap_reg_pp0_iter3_tmp_36_i_reg_692;
ap_reg_pp0_iter5_tmp_36_i_reg_692 <= ap_reg_pp0_iter4_tmp_36_i_reg_692;
ap_reg_pp0_iter6_p_Val2_20_reg_743 <= p_Val2_20_reg_743;
ap_reg_pp0_iter6_tmp_36_i_reg_692 <= ap_reg_pp0_iter5_tmp_36_i_reg_692;
ap_reg_pp0_iter7_p_Val2_20_reg_743 <= ap_reg_pp0_iter6_p_Val2_20_reg_743;
ap_reg_pp0_iter7_signbit_1_reg_791 <= signbit_1_reg_791;
ap_reg_pp0_iter7_signbit_reg_763 <= signbit_reg_763;
ap_reg_pp0_iter7_tmp_36_i_reg_692 <= ap_reg_pp0_iter6_tmp_36_i_reg_692;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter4_tmp_36_i_reg_692 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
i_op_assign_5_reg_748 <= i_op_assign_5_fu_295_p2;
i_op_assign_6_reg_753 <= i_op_assign_6_fu_304_p2;
p_Val2_20_reg_743 <= p_Val2_20_fu_280_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
i_reg_687 <= i_fu_196_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter6_tmp_36_i_reg_692 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_38_i_i_i15_i_reg_838 <= p_38_i_i_i15_i_fu_497_p2;
p_38_i_i_i_i_reg_820 <= p_38_i_i_i_i_fu_433_p2;
p_39_demorgan_i_i_i_i_reg_826 <= p_39_demorgan_i_i_i_i_fu_439_p2;
p_39_demorgan_i_i_i_reg_844 <= p_39_demorgan_i_i_i_fu_503_p2;
p_Val2_18_reg_832 <= p_Val2_18_fu_454_p2;
p_Val2_8_reg_814 <= p_Val2_8_fu_390_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter5_tmp_36_i_reg_692 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_Val2_16_reg_798 <= grp_fu_661_p3(29 downto 22);
p_Val2_7_reg_770 <= grp_fu_649_p3(29 downto 22);
signbit_1_reg_791 <= grp_fu_661_p3(31 downto 31);
signbit_reg_763 <= grp_fu_649_p3(31 downto 31);
tmp_13_reg_775 <= grp_fu_649_p3(21 downto 21);
tmp_17_reg_803 <= grp_fu_661_p3(21 downto 21);
tmp_1_reg_808 <= grp_fu_661_p3(31 downto 30);
tmp_s_reg_780 <= grp_fu_649_p3(31 downto 30);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter2_tmp_36_i_reg_692 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_Val2_2_reg_723 <= grp_fu_632_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter3_tmp_36_i_reg_692 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_Val2_4_reg_733 <= grp_fu_639_p3(29 downto 22);
tmp_reg_738 <= grp_fu_639_p3(21 downto 21);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_start = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_src_cols_V_read_reg_673 <= p_src_cols_V_dout;
p_src_rows_V_read_reg_678 <= p_src_rows_V_dout;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter3_tmp_36_i_reg_692 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
r_V_1_reg_728 <= grp_fu_639_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter5_tmp_36_i_reg_692 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter6 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
r_V_2_reg_758 <= grp_fu_649_p3;
r_V_3_reg_786 <= grp_fu_661_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter1_tmp_36_i_reg_692 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
r_V_6_i_reg_718 <= r_V_6_i_fu_626_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_36_i_reg_692 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
tmp_23_reg_701 <= p_src_data_stream_0_V_dout;
tmp_24_reg_707 <= p_src_data_stream_1_V_dout;
tmp_25_reg_712 <= p_src_data_stream_2_V_dout;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, p_src_rows_V_empty_n, p_src_cols_V_empty_n, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter8, tmp_i_fu_191_p2, ap_CS_fsm_state2, tmp_36_i_fu_206_p2, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_subdone, ap_enable_reg_pp0_iter7)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if ((not(((ap_start = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_191_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage0 =>
if ((not(((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (tmp_36_i_fu_206_p2 = ap_const_lv1_0))) and not(((ap_enable_reg_pp0_iter7 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter8 = ap_const_logic_1))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
elsif ((((ap_enable_reg_pp0_iter7 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter8 = ap_const_logic_1)) or ((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (tmp_36_i_fu_206_p2 = ap_const_lv1_0)))) then
ap_NS_fsm <= ap_ST_fsm_state12;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_state12 =>
ap_NS_fsm <= ap_ST_fsm_state2;
when others =>
ap_NS_fsm <= "XXXX";
end case;
end process;
Range1_all_ones_1_fu_479_p2 <= "1" when (tmp_1_reg_808 = ap_const_lv2_3) else "0";
Range1_all_ones_fu_415_p2 <= "1" when (tmp_s_reg_780 = ap_const_lv2_3) else "0";
Range1_all_zeros_1_fu_484_p2 <= "1" when (tmp_1_reg_808 = ap_const_lv2_0) else "0";
Range1_all_zeros_fu_420_p2 <= "1" when (tmp_s_reg_780 = ap_const_lv2_0) else "0";
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state12 <= ap_CS_fsm(3);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_01001_assign_proc : process(p_src_data_stream_0_V_empty_n, p_src_data_stream_1_V_empty_n, p_src_data_stream_2_V_empty_n, p_dst_data_stream_0_V_full_n, p_dst_data_stream_1_V_full_n, p_dst_data_stream_2_V_full_n, ap_enable_reg_pp0_iter1, tmp_36_i_reg_692, ap_enable_reg_pp0_iter8, ap_reg_pp0_iter7_tmp_36_i_reg_692)
begin
ap_block_pp0_stage0_01001 <= (((ap_enable_reg_pp0_iter8 = ap_const_logic_1) and (((ap_reg_pp0_iter7_tmp_36_i_reg_692 = ap_const_lv1_1) and (p_dst_data_stream_2_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter7_tmp_36_i_reg_692 = ap_const_lv1_1) and (p_dst_data_stream_1_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter7_tmp_36_i_reg_692 = ap_const_lv1_1) and (p_dst_data_stream_0_V_full_n = ap_const_logic_0)))) or ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((tmp_36_i_reg_692 = ap_const_lv1_1) and (p_src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((tmp_36_i_reg_692 = ap_const_lv1_1) and (p_src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((tmp_36_i_reg_692 = ap_const_lv1_1) and (p_src_data_stream_0_V_empty_n = ap_const_logic_0)))));
end process;
ap_block_pp0_stage0_11001_assign_proc : process(p_src_data_stream_0_V_empty_n, p_src_data_stream_1_V_empty_n, p_src_data_stream_2_V_empty_n, p_dst_data_stream_0_V_full_n, p_dst_data_stream_1_V_full_n, p_dst_data_stream_2_V_full_n, ap_enable_reg_pp0_iter1, tmp_36_i_reg_692, ap_enable_reg_pp0_iter8, ap_reg_pp0_iter7_tmp_36_i_reg_692)
begin
ap_block_pp0_stage0_11001 <= (((ap_enable_reg_pp0_iter8 = ap_const_logic_1) and (((ap_reg_pp0_iter7_tmp_36_i_reg_692 = ap_const_lv1_1) and (p_dst_data_stream_2_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter7_tmp_36_i_reg_692 = ap_const_lv1_1) and (p_dst_data_stream_1_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter7_tmp_36_i_reg_692 = ap_const_lv1_1) and (p_dst_data_stream_0_V_full_n = ap_const_logic_0)))) or ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((tmp_36_i_reg_692 = ap_const_lv1_1) and (p_src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((tmp_36_i_reg_692 = ap_const_lv1_1) and (p_src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((tmp_36_i_reg_692 = ap_const_lv1_1) and (p_src_data_stream_0_V_empty_n = ap_const_logic_0)))));
end process;
ap_block_pp0_stage0_subdone_assign_proc : process(p_src_data_stream_0_V_empty_n, p_src_data_stream_1_V_empty_n, p_src_data_stream_2_V_empty_n, p_dst_data_stream_0_V_full_n, p_dst_data_stream_1_V_full_n, p_dst_data_stream_2_V_full_n, ap_enable_reg_pp0_iter1, tmp_36_i_reg_692, ap_enable_reg_pp0_iter8, ap_reg_pp0_iter7_tmp_36_i_reg_692)
begin
ap_block_pp0_stage0_subdone <= (((ap_enable_reg_pp0_iter8 = ap_const_logic_1) and (((ap_reg_pp0_iter7_tmp_36_i_reg_692 = ap_const_lv1_1) and (p_dst_data_stream_2_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter7_tmp_36_i_reg_692 = ap_const_lv1_1) and (p_dst_data_stream_1_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter7_tmp_36_i_reg_692 = ap_const_lv1_1) and (p_dst_data_stream_0_V_full_n = ap_const_logic_0)))) or ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((tmp_36_i_reg_692 = ap_const_lv1_1) and (p_src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((tmp_36_i_reg_692 = ap_const_lv1_1) and (p_src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((tmp_36_i_reg_692 = ap_const_lv1_1) and (p_src_data_stream_0_V_empty_n = ap_const_logic_0)))));
end process;
ap_block_state1_assign_proc : process(ap_start, ap_done_reg, p_src_rows_V_empty_n, p_src_cols_V_empty_n)
begin
ap_block_state1 <= ((ap_start = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
ap_block_state10_pp0_stage0_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state11_pp0_stage0_iter8_assign_proc : process(p_dst_data_stream_0_V_full_n, p_dst_data_stream_1_V_full_n, p_dst_data_stream_2_V_full_n, ap_reg_pp0_iter7_tmp_36_i_reg_692)
begin
ap_block_state11_pp0_stage0_iter8 <= (((ap_reg_pp0_iter7_tmp_36_i_reg_692 = ap_const_lv1_1) and (p_dst_data_stream_2_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter7_tmp_36_i_reg_692 = ap_const_lv1_1) and (p_dst_data_stream_1_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter7_tmp_36_i_reg_692 = ap_const_lv1_1) and (p_dst_data_stream_0_V_full_n = ap_const_logic_0)));
end process;
ap_block_state3_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage0_iter1_assign_proc : process(p_src_data_stream_0_V_empty_n, p_src_data_stream_1_V_empty_n, p_src_data_stream_2_V_empty_n, tmp_36_i_reg_692)
begin
ap_block_state4_pp0_stage0_iter1 <= (((tmp_36_i_reg_692 = ap_const_lv1_1) and (p_src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((tmp_36_i_reg_692 = ap_const_lv1_1) and (p_src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((tmp_36_i_reg_692 = ap_const_lv1_1) and (p_src_data_stream_0_V_empty_n = ap_const_logic_0)));
end process;
ap_block_state5_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage0_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp0_stage0_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_condition_pp0_exit_iter0_state3_assign_proc : process(tmp_36_i_fu_206_p2)
begin
if ((tmp_36_i_fu_206_p2 = ap_const_lv1_0)) then
ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_done_reg, tmp_i_fu_191_p2, ap_CS_fsm_state2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_191_p2 = ap_const_lv1_0))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter7)
begin
if (((ap_enable_reg_pp0_iter8 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter7 = ap_const_logic_0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter6 = ap_const_logic_0) and (ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(tmp_i_fu_191_p2, ap_CS_fsm_state2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_191_p2 = ap_const_lv1_0))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
brmerge_i_i23_i_fu_597_p2 <= (p_39_demorgan_i_not_i_1_fu_592_p2 or neg_src_not_i_i20_i_fu_582_p2);
brmerge_i_i_i_fu_538_p2 <= (p_39_demorgan_i_not_i_fu_533_p2 or neg_src_not_i_i_i_fu_523_p2);
brmerge_i_i_not_i_i2_fu_587_p2 <= (p_39_demorgan_i_i_i_reg_844 and neg_src_not_i_i20_i_fu_582_p2);
brmerge_i_i_not_i_i_s_fu_528_p2 <= (p_39_demorgan_i_i_i_i_reg_826 and neg_src_not_i_i_i_fu_523_p2);
carry_1_fu_473_p2 <= (tmp_18_fu_447_p3 and tmp_17_i_i10_i_fu_467_p2);
carry_fu_409_p2 <= (tmp_17_i_i_i_fu_403_p2 and tmp_14_fu_383_p3);
deleted_zeros_1_fu_489_p3 <=
Range1_all_ones_1_fu_479_p2 when (carry_1_fu_473_p2(0) = '1') else
Range1_all_zeros_1_fu_484_p2;
deleted_zeros_fu_425_p3 <=
Range1_all_ones_fu_415_p2 when (carry_fu_409_p2(0) = '1') else
Range1_all_zeros_fu_420_p2;
grp_fu_632_p0 <= grp_fu_632_p00(8 - 1 downto 0);
grp_fu_632_p00 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter2_tmp_25_reg_712),28));
grp_fu_632_p1 <= ap_const_lv28_74BC6(20 - 1 downto 0);
grp_fu_639_p0 <= grp_fu_639_p00(8 - 1 downto 0);
grp_fu_639_p00 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter3_tmp_24_reg_707),30));
grp_fu_639_p1 <= ap_const_lv30_259168(23 - 1 downto 0);
grp_fu_639_p2 <= grp_fu_639_p20(29 - 1 downto 0);
grp_fu_639_p20 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_Val2_2_reg_723),30));
grp_fu_649_p1 <= ap_const_lv32_2DA1CA(23 - 1 downto 0);
grp_fu_649_p2 <= ap_const_lv32_20000000(31 - 1 downto 0);
grp_fu_661_p1 <= ap_const_lv32_241893(23 - 1 downto 0);
grp_fu_661_p2 <= ap_const_lv32_20000000(31 - 1 downto 0);
i_cast_i_cast_fu_187_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_i_reg_165),16));
i_fu_196_p2 <= std_logic_vector(unsigned(i_i_reg_165) + unsigned(ap_const_lv11_1));
i_op_assign_5_fu_295_p2 <= std_logic_vector(unsigned(tmp_30_cast_i_fu_288_p1) - unsigned(tmp_31_cast_i_fu_291_p1));
i_op_assign_6_fu_304_p2 <= std_logic_vector(unsigned(tmp_33_cast_i_fu_301_p1) - unsigned(tmp_31_cast_i_fu_291_p1));
j_cast_i_cast_fu_202_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_i_reg_176),16));
j_fu_211_p2 <= std_logic_vector(unsigned(j_i_reg_176) + unsigned(ap_const_lv11_1));
neg_src_4_fu_572_p2 <= (tmp_18_i_i16_i_fu_567_p2 and ap_reg_pp0_iter7_signbit_1_reg_791);
neg_src_fu_513_p2 <= (tmp_18_i_i_i_fu_508_p2 and ap_reg_pp0_iter7_signbit_reg_763);
neg_src_not_i_i20_i_fu_582_p2 <= (signbit_not_i19_i_fu_577_p2 or p_38_i_i_i15_i_reg_838);
neg_src_not_i_i_i_fu_523_p2 <= (signbit_not_i_i_fu_518_p2 or p_38_i_i_i_i_reg_820);
not_carry_i_fu_274_p2 <= (tmp_11_fu_260_p3 or p_Result_2_i_i_not_fu_268_p2);
p_38_i_i_i15_i_fu_497_p2 <= (carry_1_fu_473_p2 and Range1_all_ones_1_fu_479_p2);
p_38_i_i_i_i_fu_433_p2 <= (carry_fu_409_p2 and Range1_all_ones_fu_415_p2);
p_39_demorgan_i_i_i_fu_503_p2 <= (signbit_1_reg_791 or deleted_zeros_1_fu_489_p3);
p_39_demorgan_i_i_i_i_fu_439_p2 <= (signbit_reg_763 or deleted_zeros_fu_425_p3);
p_39_demorgan_i_not_i_1_fu_592_p2 <= (p_39_demorgan_i_i_i_reg_844 xor ap_const_lv1_1);
p_39_demorgan_i_not_i_fu_533_p2 <= (p_39_demorgan_i_i_i_i_reg_826 xor ap_const_lv1_1);
p_Result_2_i_i_not_fu_268_p2 <= (tmp_10_fu_248_p3 xor ap_const_lv1_1);
p_Val2_18_fu_454_p2 <= std_logic_vector(unsigned(p_Val2_16_reg_798) + unsigned(tmp_16_i_i6_i_fu_444_p1));
p_Val2_20_fu_280_p3 <=
p_Val2_5_fu_255_p2 when (not_carry_i_fu_274_p2(0) = '1') else
ap_const_lv8_FF;
p_Val2_5_fu_255_p2 <= std_logic_vector(unsigned(p_Val2_4_reg_733) + unsigned(tmp_19_i_i_i_fu_245_p1));
p_Val2_8_fu_390_p2 <= std_logic_vector(unsigned(p_Val2_7_reg_770) + unsigned(tmp_16_i_i_i_fu_380_p1));
p_dst_data_stream_0_V_blk_n_assign_proc : process(p_dst_data_stream_0_V_full_n, ap_block_pp0_stage0, ap_enable_reg_pp0_iter8, ap_reg_pp0_iter7_tmp_36_i_reg_692)
begin
if (((ap_reg_pp0_iter7_tmp_36_i_reg_692 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter8 = ap_const_logic_1))) then
p_dst_data_stream_0_V_blk_n <= p_dst_data_stream_0_V_full_n;
else
p_dst_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_dst_data_stream_0_V_din <= ap_reg_pp0_iter7_p_Val2_20_reg_743;
p_dst_data_stream_0_V_write_assign_proc : process(ap_enable_reg_pp0_iter8, ap_reg_pp0_iter7_tmp_36_i_reg_692, ap_block_pp0_stage0_11001)
begin
if (((ap_reg_pp0_iter7_tmp_36_i_reg_692 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter8 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_dst_data_stream_0_V_write <= ap_const_logic_1;
else
p_dst_data_stream_0_V_write <= ap_const_logic_0;
end if;
end process;
p_dst_data_stream_1_V_blk_n_assign_proc : process(p_dst_data_stream_1_V_full_n, ap_block_pp0_stage0, ap_enable_reg_pp0_iter8, ap_reg_pp0_iter7_tmp_36_i_reg_692)
begin
if (((ap_reg_pp0_iter7_tmp_36_i_reg_692 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter8 = ap_const_logic_1))) then
p_dst_data_stream_1_V_blk_n <= p_dst_data_stream_1_V_full_n;
else
p_dst_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_dst_data_stream_1_V_din <=
p_mux_i_i2_i_fu_544_p3 when (brmerge_i_i_i_fu_538_p2(0) = '1') else
p_i_i_i_fu_551_p3;
p_dst_data_stream_1_V_write_assign_proc : process(ap_enable_reg_pp0_iter8, ap_reg_pp0_iter7_tmp_36_i_reg_692, ap_block_pp0_stage0_11001)
begin
if (((ap_reg_pp0_iter7_tmp_36_i_reg_692 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter8 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_dst_data_stream_1_V_write <= ap_const_logic_1;
else
p_dst_data_stream_1_V_write <= ap_const_logic_0;
end if;
end process;
p_dst_data_stream_2_V_blk_n_assign_proc : process(p_dst_data_stream_2_V_full_n, ap_block_pp0_stage0, ap_enable_reg_pp0_iter8, ap_reg_pp0_iter7_tmp_36_i_reg_692)
begin
if (((ap_reg_pp0_iter7_tmp_36_i_reg_692 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter8 = ap_const_logic_1))) then
p_dst_data_stream_2_V_blk_n <= p_dst_data_stream_2_V_full_n;
else
p_dst_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_dst_data_stream_2_V_din <=
p_mux_i_i24_i_fu_603_p3 when (brmerge_i_i23_i_fu_597_p2(0) = '1') else
p_i_i25_i_fu_610_p3;
p_dst_data_stream_2_V_write_assign_proc : process(ap_enable_reg_pp0_iter8, ap_reg_pp0_iter7_tmp_36_i_reg_692, ap_block_pp0_stage0_11001)
begin
if (((ap_reg_pp0_iter7_tmp_36_i_reg_692 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter8 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_dst_data_stream_2_V_write <= ap_const_logic_1;
else
p_dst_data_stream_2_V_write <= ap_const_logic_0;
end if;
end process;
p_i_i25_i_fu_610_p3 <=
ap_const_lv8_0 when (neg_src_4_fu_572_p2(0) = '1') else
p_Val2_18_reg_832;
p_i_i_i_fu_551_p3 <=
ap_const_lv8_0 when (neg_src_fu_513_p2(0) = '1') else
p_Val2_8_reg_814;
p_mux_i_i24_i_fu_603_p3 <=
p_Val2_18_reg_832 when (brmerge_i_i_not_i_i2_fu_587_p2(0) = '1') else
ap_const_lv8_FF;
p_mux_i_i2_i_fu_544_p3 <=
p_Val2_8_reg_814 when (brmerge_i_i_not_i_i_s_fu_528_p2(0) = '1') else
ap_const_lv8_FF;
p_src_cols_V_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_src_cols_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_src_cols_V_blk_n <= p_src_cols_V_empty_n;
else
p_src_cols_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_src_cols_V_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_src_rows_V_empty_n, p_src_cols_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_src_cols_V_read <= ap_const_logic_1;
else
p_src_cols_V_read <= ap_const_logic_0;
end if;
end process;
p_src_data_stream_0_V_blk_n_assign_proc : process(p_src_data_stream_0_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, tmp_36_i_reg_692)
begin
if (((tmp_36_i_reg_692 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
p_src_data_stream_0_V_blk_n <= p_src_data_stream_0_V_empty_n;
else
p_src_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_src_data_stream_0_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_36_i_reg_692, ap_block_pp0_stage0_11001)
begin
if (((tmp_36_i_reg_692 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_src_data_stream_0_V_read <= ap_const_logic_1;
else
p_src_data_stream_0_V_read <= ap_const_logic_0;
end if;
end process;
p_src_data_stream_1_V_blk_n_assign_proc : process(p_src_data_stream_1_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, tmp_36_i_reg_692)
begin
if (((tmp_36_i_reg_692 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
p_src_data_stream_1_V_blk_n <= p_src_data_stream_1_V_empty_n;
else
p_src_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_src_data_stream_1_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_36_i_reg_692, ap_block_pp0_stage0_11001)
begin
if (((tmp_36_i_reg_692 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_src_data_stream_1_V_read <= ap_const_logic_1;
else
p_src_data_stream_1_V_read <= ap_const_logic_0;
end if;
end process;
p_src_data_stream_2_V_blk_n_assign_proc : process(p_src_data_stream_2_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, tmp_36_i_reg_692)
begin
if (((tmp_36_i_reg_692 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
p_src_data_stream_2_V_blk_n <= p_src_data_stream_2_V_empty_n;
else
p_src_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_src_data_stream_2_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_36_i_reg_692, ap_block_pp0_stage0_11001)
begin
if (((tmp_36_i_reg_692 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_src_data_stream_2_V_read <= ap_const_logic_1;
else
p_src_data_stream_2_V_read <= ap_const_logic_0;
end if;
end process;
p_src_rows_V_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_src_rows_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_src_rows_V_blk_n <= p_src_rows_V_empty_n;
else
p_src_rows_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_src_rows_V_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_src_rows_V_empty_n, p_src_cols_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_src_rows_V_read <= ap_const_logic_1;
else
p_src_rows_V_read <= ap_const_logic_0;
end if;
end process;
r_V_6_i_fu_626_p0 <= r_V_6_i_fu_626_p00(8 - 1 downto 0);
r_V_6_i_fu_626_p00 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_23_reg_701),29));
r_V_6_i_fu_626_p1 <= ap_const_lv29_1322D0(22 - 1 downto 0);
signbit_not_i19_i_fu_577_p2 <= (ap_reg_pp0_iter7_signbit_1_reg_791 xor ap_const_lv1_1);
signbit_not_i_i_fu_518_p2 <= (ap_reg_pp0_iter7_signbit_reg_763 xor ap_const_lv1_1);
tmp_10_fu_248_p3 <= r_V_1_reg_728(29 downto 29);
tmp_11_fu_260_p3 <= p_Val2_5_fu_255_p2(7 downto 7);
tmp_14_fu_383_p3 <= r_V_2_reg_758(29 downto 29);
tmp_15_fu_395_p3 <= p_Val2_8_fu_390_p2(7 downto 7);
tmp_16_i_i6_i_fu_444_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_17_reg_803),8));
tmp_16_i_i_i_fu_380_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_13_reg_775),8));
tmp_17_i_i10_i_fu_467_p2 <= (tmp_19_fu_459_p3 xor ap_const_lv1_1);
tmp_17_i_i_i_fu_403_p2 <= (tmp_15_fu_395_p3 xor ap_const_lv1_1);
tmp_18_fu_447_p3 <= r_V_3_reg_786(29 downto 29);
tmp_18_i_i16_i_fu_567_p2 <= (p_38_i_i_i15_i_reg_838 xor ap_const_lv1_1);
tmp_18_i_i_i_fu_508_p2 <= (p_38_i_i_i_i_reg_820 xor ap_const_lv1_1);
tmp_19_fu_459_p3 <= p_Val2_18_fu_454_p2(7 downto 7);
tmp_19_i_i_i_fu_245_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_reg_738),8));
tmp_30_cast_i_fu_288_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter4_tmp_23_reg_701),9));
tmp_31_cast_i_fu_291_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(p_Val2_20_fu_280_p3),9));
tmp_33_cast_i_fu_301_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter4_tmp_25_reg_712),9));
tmp_36_i_fu_206_p2 <= "1" when (unsigned(j_cast_i_cast_fu_202_p1) < unsigned(p_src_cols_V_read_reg_673)) else "0";
tmp_i_fu_191_p2 <= "1" when (unsigned(i_cast_i_cast_fu_187_p1) < unsigned(p_src_rows_V_read_reg_678)) else "0";
end behav;
|
mit
|
9ff823acacf90e67174ed2626c0d0fe2
| 0.601133 | 2.563065 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodAWGController/src/ConfigDAC.vhd
| 1 | 16,873 |
-------------------------------------------------------------------------------
--
-- File: ConfigDAC.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodAWG1411_Controller
-- Date: 15 January 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module writes an intial configuration into the DAC registers and then
-- manages the optional SPI Indirect Access Port.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use work.PkgZmodDAC.all;
entity ConfigDAC is
generic (
--The number of data bits for the data phase of the SPI transaction:
--only 8 data bits currently supported.
kDataWidth : integer range 8 to 8 := 8;
-- The number of bits of the command phase of the SPI transaction.
kCommandWidth : integer range 8 to 8 := 8
);
Port (
-- 100MHZ clock input.
SysClk100 : in std_logic;
-- Asynchronous active low reset.
asRst_n : in std_logic;
-- Initialization done active low indicator.
sInitDoneDAC : out std_logic := '0';
-- DAC initialization error signaling.
sConfigError : out STD_LOGIC := '0';
-- SPI Indirect access port; it provides the means to indirectly access
-- the DAC registers. It is designed to interface with 2 AXI StreamFIFOs,
-- one that stores commands to be transmitted and one to store the received data.
-- TX command AXI stream interface
sCmdTxAxisTvalid: IN STD_LOGIC;
sCmdTxAxisTready: OUT STD_LOGIC := '0';
sCmdTxAxisTdata: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-- RX command AXI stream interface
sCmdRxAxisTvalid: OUT STD_LOGIC := '0';
sCmdRxAxisTready: IN STD_LOGIC;
sCmdRxAxisTdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-- AD9717 SPI interface
sZmodDAC_CS : out std_logic;
sZmodDAC_SCLK : out std_logic;
sZmodDAC_SDIO : inout std_logic
);
end ConfigDAC;
architecture Behavioral of ConfigDAC is
signal sInitDoneDAC_Fsm : std_logic := '0';
signal sConfigErrorFsm : std_logic;
signal sCurrentState, sNextState : FsmStates_t;
-- signals used for debug purposes
-- signal fsmcfg_state, DAC_FSM_STATE_R : std_logic_vector(5 downto 0);
signal sCmdCnt : unsigned(4 downto 0);
signal sCmdCntInt : integer range 0 to 31;
signal sIncCmdCnt, sRstCmdCnt_n : std_logic;
-- SPI Interface signals
signal sDAC_SPI_ApStartR, sDAC_SPI_ApStart :std_logic;
signal sDAC_SPI_RdWr, sDAC_SPI_RdWrR :std_logic;
signal sDAC_SPI_Done :std_logic;
signal sDAC_SPI_Busy :std_logic;
signal sDAC_SPI_RdData, sDAC_SPI_WrData, sDAC_SPI_WrDataR : std_logic_vector (7 downto 0);
signal sDAC_SPI_Width, sDAC_SPI_WidthR : std_logic_vector (1 downto 0);
signal sDAC_SPI_Addr, sDAC_SPI_AddrR : std_logic_vector (4 downto 0);
--External Command FIFO Interface
signal sLdCmdTxData: std_logic;
signal sCmdTxDataReg: std_logic_vector(23 downto 0);
signal sCmdTxAxisTreadyLoc: std_logic;
signal sCmdRxAxisTvalidLoc: std_logic;
signal sCmdRxAxisTdataLoc : STD_LOGIC_VECTOR(7 DOWNTO 0);
--Timers
signal sCfgTimer : unsigned (23 downto 0);
signal sCfgTimerRst_n : std_logic;
begin
----------------------------Zmod Configuration-----------------------------------------------------------------------------------------
-- Instantiate the SPI controller.
DAC_SPI_inst: entity work.ADI_SPI
Generic Map(
kSysClkDiv => kSPI_SysClkDiv,
kDataWidth => kDataWidth,
kCommandWidth => kCommandWidth
)
Port Map(
--
SysClk100 => SysClk100,
asRst_n => asRst_n,
sSPI_Clk => sZmodDAC_Sclk,
sSDIO => sZmodDAC_SDIO,
sCS => sZmodDAC_CS,
sApStart => sDAC_SPI_ApStartR,
sRdData => sDAC_SPI_RdData,
sWrData => sDAC_SPI_WrDataR,
sAddr => sDAC_SPI_AddrR,
sWidth => sDAC_SPI_WidthR, --tested only for width = "00"
sRdWr => sDAC_SPI_RdWrR,
sDone => sDAC_SPI_Done,
sBusy => sDAC_SPI_Busy
);
-- Register the SPI controller inputs.
ProcSPI_ControllerRegister: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sDAC_SPI_RdWrR <= '0';
sDAC_SPI_WrDataR <= (others => '0');
sDAC_SPI_AddrR <= (others => '0');
sDAC_SPI_WidthR <= (others => '0');
sDAC_SPI_ApStartR <= '0';
elsif (rising_edge(SysClk100)) then
sDAC_SPI_RdWrR <= sDAC_SPI_RdWr;
sDAC_SPI_WrDataR <= sDAC_SPI_WrData;
sDAC_SPI_AddrR <= sDAC_SPI_Addr;
sDAC_SPI_WidthR <= sDAC_SPI_Width;
sDAC_SPI_ApStartR <= sDAC_SPI_ApStart;
end if;
end process;
-- Register the SPI Indirect Access Port receive interface outputs.
ProcRxExtFIFO_Reg: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCmdRxAxisTvalid <= '0';
sCmdRxAxisTdata <= (others => '0');
elsif (rising_edge(SysClk100)) then
sCmdRxAxisTvalid <= sCmdRxAxisTvalidLoc;
sCmdRxAxisTdata <= x"000000" & sCmdRxAxisTdataLoc;
end if;
end process;
-- Register the SPI Indirect Access Port transmit interface outputs.
ProcCmdAxisTreadyReg: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCmdTxAxisTready <= '0';
elsif (rising_edge(SysClk100)) then
sCmdTxAxisTready <= sCmdTxAxisTreadyLoc;
end if;
end process;
-- Register the next SPI Indirect Access Port command on the transmit
-- interface when the configuration state machine is capable of processing it.
ProcLdCmdTxData: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCmdTxDataReg <= (others => '0');
elsif (rising_edge(SysClk100)) then
if (sLdCmdTxData = '1') then
sCmdTxDataReg <= sCmdTxAxisTdata(23 downto 0);
end if;
end if;
end process;
ProcCmdConter: process (SysClk100, asRst_n) -- Succesfully sent SPI command counter
begin
if (asRst_n = '0') then
sCmdCnt <= (others => '0');
elsif (rising_edge(SysClk100)) then
if (sRstCmdCnt_n = '0') then
sCmdCnt <= (others => '0');
else
if (sIncCmdCnt = '1') then
sCmdCnt <= sCmdCnt + 1;
end if;
end if;
end if;
end process;
sCmdCntInt <= to_integer(sCmdCnt);
-- Timer used to determine timeout conditions for SPI transfers.
-- When a command is sent to the DAC a certain amount of time is allowed for the state
-- machine to read back the expected value in order to make sure the register was correctly
-- configured. Some commands do not take effect immediately, so this mechanism is necessary
-- (SPI Port Config register (address 0x00) soft reset write for example).
ProcCfgTimer: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCfgTimer <= (others =>'0');
elsif (rising_edge(SysClk100)) then
if (sCfgTimerRst_n = '0') then
sCfgTimer <= (others =>'0');
else
sCfgTimer <= sCfgTimer + 1;
end if;
end if;
end process;
------------------------------------------------------------------------------------------
-- Configuration state machine
------------------------------------------------------------------------------------------
-- State machine synchronous process
ProcFsmSync: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCurrentState <= StStart;
--DAC_FSM_STATE_R <= (others => '0');
elsif (rising_edge(SysClk100)) then
sCurrentState <= sNextState;
--DAC_FSM_STATE_R <= fsmcfg_state;
end if;
end process;
-- Next State an output decode
procNextStateAndOutput: process (sCurrentState, sCmdCntInt, sDAC_SPI_Done, sDAC_SPI_RdData,
sCmdTxAxisTvalid, sCmdTxAxisTdata, sCmdTxDataReg, sCmdRxAxisTready, sDAC_SPI_Busy, sCfgTimer)
begin
sNextState <= sCurrentState;
--fsmcfg_state <= "000000";
sRstCmdCnt_n <= '0';
sIncCmdCnt <= '0';
sDAC_SPI_ApStart <= '0';
sDAC_SPI_WrData <= (others => '0');
sDAC_SPI_Addr <= (others => '0');
sDAC_SPI_Width <= (others => '0');
sDAC_SPI_RdWr <= '0';
sCmdTxAxisTreadyLoc <= '0';
sCmdRxAxisTvalidLoc <= '0';
sCmdRxAxisTdataLoc <= (others => '0');
sLdCmdTxData <= '0';
sCfgTimerRst_n <= '0';
sInitDoneDAC_Fsm <= '0';
sConfigErrorFsm <= '0';
case (sCurrentState) is
when StStart =>
--fsmcfg_state <= "000000";
sNextState <= StWriteConfigReg;
-- Perform a register write operation for the sCmdCntInt'th command in the queue.
-- For some sCmdCntInt only register reads are required.
when StWriteConfigReg =>
--fsmcfg_state <= "000001";
sRstCmdCnt_n <= '1';
if (sCmdCntInt = kCmdRdCalstatIndex) then
sNextState <= StReadControlReg;
else
if (sDAC_SPI_Busy = '0') then
sDAC_SPI_ApStart <= '1';
sDAC_SPI_WrData <= kDAC_SPI_Cmd(sCmdCntInt)(7 downto 0);--x"84";
sDAC_SPI_Addr <= kDAC_SPI_Cmd(sCmdCntInt)(12 downto 8);--"00010";
sDAC_SPI_Width <= "00";
sNextState <= StWaitDoneWriteReg;
end if;
end if;
-- Wait for register write command to be completed
when StWaitDoneWriteReg =>
--fsmcfg_state <= "000010";
sRstCmdCnt_n <= '1';
sCfgTimerRst_n <= '1';
if (sDAC_SPI_Done = '1') then
sNextState <= StReadControlReg;
end if;
-- Read back the register value configured in the StWriteControlReg state.
when StReadControlReg =>
--fsmcfg_state <= "000011";
sRstCmdCnt_n <= '1';
sCfgTimerRst_n <= '1';
if (sDAC_SPI_Busy = '0') then
sDAC_SPI_ApStart <= '1';
sDAC_SPI_Addr <= kDAC_SPI_Cmd(sCmdCntInt)(12 downto 8);
sDAC_SPI_Width <= "00";
sDAC_SPI_RdWr <= '1';
sNextState <= StWaitDoneReadReg;
end if;
-- Wait for SPI command to be completed and compare the read data against
-- the expected value.
when StWaitDoneReadReg =>
--fsmcfg_state <= "000100";
sRstCmdCnt_n <= '1';
sCfgTimerRst_n <= '1';
if (sDAC_SPI_Done = '1') then
if ((sDAC_SPI_RdData or DAC_SPI_mask(sCmdCntInt)) = (kDAC_SPI_Cmd(sCmdCntInt)(7 downto 0) or DAC_SPI_mask(sCmdCntInt))) then
sNextState <= StCheckCmdCnt;
elsif (sCfgTimer >= kCfgTimeout) then
sNextState <= StError;
else
sNextState <= StReadControlReg;
end if;
end if;
-- Check if the command sequence has completed.
when StCheckCmdCnt =>
--fsmcfg_state <= "000101";
sRstCmdCnt_n <= '1';
if (sCmdCntInt = kCmdTotal) then
sNextState <= StInitDone;
sRstCmdCnt_n <= '0';
else
sIncCmdCnt <= '1';
sNextState <= StWriteConfigReg;
end if;
-- Indicate that the initialization sequence has completed.
when StInitDone =>
--fsmcfg_state <= "000110";
sInitDoneDAC_Fsm <= '1';
sNextState <= StIdle;
-- IDLE state; wait for changes on the SPI Indirect Access Port.
when StIdle =>
--fsmcfg_state <= "000111";
sInitDoneDAC_Fsm <= '1';
if ((sCmdTxAxisTvalid = '1') and (sDAC_SPI_Busy = '0')) then
sLdCmdTxData <= '1';
if (sCmdTxAxisTdata(23) = '0') then
sNextState <= StExtSPI_WrCmd;
else
sNextState <= StExtSPI_RdCmd;
end if;
end if;
-- Execute the register write command requested on the SPI Indirect Access Port.
when StExtSPI_WrCmd =>
--fsmcfg_state <= "001000";
sInitDoneDAC_Fsm <= '1';
sDAC_SPI_ApStart <= '1';
sDAC_SPI_WrData <= sCmdTxDataReg(7 downto 0);
sDAC_SPI_Addr <= sCmdTxDataReg(12 downto 8);
sDAC_SPI_Width <= sCmdTxDataReg(22 downto 21);
sDAC_SPI_RdWr <= '0';
sNextState <= StWaitDoneExtWrReg;
-- Wait for the register write command to complete
when StWaitDoneExtWrReg =>
--fsmcfg_state <= "001001";
sInitDoneDAC_Fsm <= '1';
if (sDAC_SPI_Done = '1') then
sCmdTxAxisTreadyLoc <= '1';
sNextState <= StIdle;
end if;
-- Execute the register read command requested on the SPI Indirect Access Port.
when StExtSPI_RdCmd =>
--fsmcfg_state <= "001010";
sInitDoneDAC_Fsm <= '1';
sDAC_SPI_ApStart <= '1';
sDAC_SPI_Addr <= sCmdTxDataReg(12 downto 8);
sDAC_SPI_Width <= sCmdTxDataReg(22 downto 21);
sDAC_SPI_RdWr <= '1';
sNextState <= StWaitDoneExtRdReg;
-- Wait for the register read command to complete.
when StWaitDoneExtRdReg =>
--fsmcfg_state <= "001011";
sInitDoneDAC_Fsm <= '1';
if (sDAC_SPI_Done = '1') then
sCmdTxAxisTreadyLoc <= '1';
sNextState <= StRegExtRxData;
end if;
-- State used to register the incoming SPI data.
when StRegExtRxData =>
--fsmcfg_state <= "001100";
sInitDoneDAC_Fsm <= '1';
sCmdRxAxisTvalidLoc <= '1';
sCmdRxAxisTdataLoc <= sDAC_SPI_RdData;
if (sCmdRxAxisTready = '1') then
sNextState <= StIdle;
end if;
-- When an error condition is detected the state machine stalls in this state.
-- An external reset condition is necessary to exit this state.
when StError =>
--fsmcfg_state <= "111111";
sConfigErrorFsm <= '1';
report "DAC Configuration readback error." & LF & HT & HT
severity ERROR;
when others =>
sNextState <= StStart;
end case;
end process;
-- Register FSM output flags.
ProcInitDone: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sInitDoneDAC <= '0';
sConfigError <= '0';
elsif (rising_edge (SysClk100)) then
sInitDoneDAC <= sInitDoneDAC_Fsm;
sConfigError <= sConfigErrorFsm;
end if;
end process;
end Behavioral;
|
mit
|
92a2c215e35890c064452bf11f32a46f
| 0.57192 | 4.63544 | false | false | false | false |
Digilent/vivado-library
|
ip/video_scaler/hdl/vhdl/video_scaler_sdivhbi.vhd
| 1 | 9,408 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity video_scaler_sdivhbi_div_u is
generic (
in0_WIDTH : INTEGER :=32;
in1_WIDTH : INTEGER :=32;
out_WIDTH : INTEGER :=32);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
start : in STD_LOGIC;
dividend : in STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
divisor : in STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
sign_i : in STD_LOGIC_VECTOR(1 downto 0);
sign_o : out STD_LOGIC_VECTOR(1 downto 0);
done : out STD_LOGIC;
quot : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
remd : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0));
function max (left, right : INTEGER) return INTEGER is
begin
if left > right then return left;
else return right;
end if;
end max;
end entity;
architecture rtl of video_scaler_sdivhbi_div_u is
constant cal_WIDTH : INTEGER := max(in0_WIDTH, in1_WIDTH);
signal dividend0 : UNSIGNED(in0_WIDTH-1 downto 0);
signal divisor0 : UNSIGNED(in1_WIDTH-1 downto 0);
signal sign0 : UNSIGNED(1 downto 0);
signal dividend_tmp : UNSIGNED(in0_WIDTH-1 downto 0);
signal remd_tmp : UNSIGNED(in0_WIDTH-1 downto 0);
signal dividend_tmp_mux : UNSIGNED(in0_WIDTH-1 downto 0);
signal remd_tmp_mux : UNSIGNED(in0_WIDTH-1 downto 0);
signal comb_tmp : UNSIGNED(in0_WIDTH-1 downto 0);
signal cal_tmp : UNSIGNED(cal_WIDTH downto 0);
signal r_stage : UNSIGNED(in0_WIDTH downto 0);
begin
quot <= STD_LOGIC_VECTOR(RESIZE(dividend_tmp, out_WIDTH));
remd <= STD_LOGIC_VECTOR(RESIZE(remd_tmp, out_WIDTH));
sign_o <= STD_LOGIC_VECTOR(sign0);
tran0_proc : process (clk)
begin
if (clk'event and clk='1') then
if (start = '1') then
dividend0 <= UNSIGNED(dividend);
divisor0 <= UNSIGNED(divisor);
sign0 <= UNSIGNED(sign_i);
end if;
end if;
end process;
-- r_stage(0)=1:accept input; r_stage(in0_WIDTH)=1:done
done <= r_stage(in0_WIDTH);
one_hot : process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
r_stage <= (others => '0');
elsif (ce = '1') then
r_stage <= r_stage(in0_WIDTH-1 downto 0) & start;
end if;
end if;
end process;
-- MUXs
dividend_tmp_mux <= dividend_tmp when (r_stage(0) = '0') else
dividend0;
remd_tmp_mux <= remd_tmp when (r_stage(0) = '0') else
(others => '0');
comb_tmp <= remd_tmp_mux(in0_WIDTH-2 downto 0) & dividend_tmp_mux(in0_WIDTH-1);
cal_tmp <= ('0' & comb_tmp) - ('0' & divisor0);
process (clk)
begin
if (clk'event and clk='1') then
if (ce = '1') then
dividend_tmp <= dividend_tmp_mux(in0_WIDTH-2 downto 0) & (not cal_tmp(cal_WIDTH));
if cal_tmp(cal_WIDTH) = '1' then
remd_tmp <= comb_tmp;
else
remd_tmp <= cal_tmp(in0_WIDTH-1 downto 0);
end if;
end if;
end if;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity video_scaler_sdivhbi_div is
generic (
in0_WIDTH : INTEGER :=32;
in1_WIDTH : INTEGER :=32;
out_WIDTH : INTEGER :=32);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
start : in STD_LOGIC;
done : out STD_LOGIC;
dividend : in STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
divisor : in STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
quot : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
remd : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0));
end entity;
architecture rtl of video_scaler_sdivhbi_div is
component video_scaler_sdivhbi_div_u is
generic (
in0_WIDTH : INTEGER :=32;
in1_WIDTH : INTEGER :=32;
out_WIDTH : INTEGER :=32);
port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
start : in STD_LOGIC;
done : out STD_LOGIC;
dividend : in STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
divisor : in STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
sign_i : in STD_LOGIC_VECTOR(1 downto 0);
sign_o : out STD_LOGIC_VECTOR(1 downto 0);
quot : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
remd : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0));
end component;
signal start0 : STD_LOGIC := '0';
signal done0 : STD_LOGIC;
signal dividend0 : STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
signal divisor0 : STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
signal dividend_u : STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
signal divisor_u : STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
signal quot_u : STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
signal remd_u : STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
signal sign_i : STD_LOGIC_VECTOR(1 downto 0);
signal sign_o : STD_LOGIC_VECTOR(1 downto 0);
begin
video_scaler_sdivhbi_div_u_0 : video_scaler_sdivhbi_div_u
generic map(
in0_WIDTH => in0_WIDTH,
in1_WIDTH => in1_WIDTH,
out_WIDTH => out_WIDTH)
port map(
clk => clk,
reset => reset,
ce => ce,
start => start0,
done => done0,
dividend => dividend_u,
divisor => divisor_u,
sign_i => sign_i,
sign_o => sign_o,
quot => quot_u,
remd => remd_u);
sign_i <= (dividend0(in0_WIDTH-1) xor divisor0(in1_WIDTH-1)) & dividend0(in0_WIDTH-1);
dividend_u <= STD_LOGIC_VECTOR(UNSIGNED(not dividend0) + 1) when dividend0(in0_WIDTH-1) = '1' else dividend0;
divisor_u <= STD_LOGIC_VECTOR(UNSIGNED(not divisor0) + 1) when divisor0(in1_WIDTH-1) = '1' else divisor0;
process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
dividend0 <= dividend;
divisor0 <= divisor;
start0 <= start;
end if;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
done <= done0;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if (done0 = '1') then
if (sign_o(1) = '1') then
quot <= STD_LOGIC_VECTOR(UNSIGNED(not quot_u) + 1);
else
quot <= quot_u;
end if;
end if;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if (done0 = '1') then
if (sign_o(0) = '1') then
remd <= STD_LOGIC_VECTOR(UNSIGNED(not remd_u) + 1);
else
remd <= remd_u;
end if;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity video_scaler_sdivhbi is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
start : IN STD_LOGIC;
done : OUT STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of video_scaler_sdivhbi is
component video_scaler_sdivhbi_div is
generic (
in0_WIDTH : INTEGER;
in1_WIDTH : INTEGER;
out_WIDTH : INTEGER);
port (
dividend : IN STD_LOGIC_VECTOR;
divisor : IN STD_LOGIC_VECTOR;
quot : OUT STD_LOGIC_VECTOR;
remd : OUT STD_LOGIC_VECTOR;
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
reset : IN STD_LOGIC;
start : IN STD_LOGIC;
done : OUT STD_LOGIC);
end component;
signal sig_quot : STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0);
signal sig_remd : STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0);
begin
video_scaler_sdivhbi_div_U : component video_scaler_sdivhbi_div
generic map (
in0_WIDTH => din0_WIDTH,
in1_WIDTH => din1_WIDTH,
out_WIDTH => dout_WIDTH)
port map (
dividend => din0,
divisor => din1,
quot => dout,
remd => sig_remd,
clk => clk,
ce => ce,
reset => reset,
start => start,
done => done);
end architecture;
|
mit
|
4c0eb1b07993f6d66b9b10959fba6a80
| 0.524447 | 3.522276 | false | false | false | false |
Digilent/vivado-library
|
ip/Sync_v1_0/src/Sync.vhd
| 4 | 2,353 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/28/2015 07:22:57 PM
-- Design Name:
-- Module Name: Sync - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Sync is
Generic (
kRstActiveHigh : boolean := true; --'1' if aRst (active-high) is in use, '0' if aRst_n (active_low)
kResetTo : std_logic := '0'; --the reset value of oOut when aRst/aRst_n is asserted
kRegisterInput : boolean := true; --should iIn be re-registered on the InClk domain
kStages : natural := 2); --how many synchronizer stages to use
Port (
aRst : in STD_LOGIC;
aRst_n : in STD_LOGIC;
iIn : in STD_LOGIC;
InClk :in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end Sync;
architecture Behavioral of Sync is
signal aRst_int, iIn_q : std_logic;
begin
ResetActiveLow: if not kRstActiveHigh generate
aRst_int <= not aRst_n;
end generate ResetActiveLow;
ResetActiveHigh: if kRstActiveHigh generate
aRst_int <= aRst;
end generate ResetActiveHigh;
ReRegister: if kRegisterInput generate
--By re-registering iIn on its own domain, we make sure iIn_q is glitch-free
SyncSource: process(aRst_int, InClk)
begin
if (aRst_int = '1') then
iIn_q <= kResetTo;
elsif Rising_Edge(InClk) then
iIn_q <= iIn;
end if;
end process SyncSource;
end generate ReRegister;
DontRegister: if not kRegisterInput generate
iIn_q <= iIn;
end generate DontRegister;
--Crossing clock boundary here
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => kResetTo,
kStages => kStages)
port map (
aReset => aRst_int,
aIn => iIn_q,
OutClk => OutClk,
oOut => oOut);
end Behavioral;
|
mit
|
3ba77d16986ae43be33535b5243f621d
| 0.622609 | 4.001701 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
segment_run/segment.vhdl
| 1 | 2,384 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity segment is
Port
(
clock : in std_logic;
selector : out std_logic_vector( 2 downto 0 );
segment_data : out std_logic_vector( 7 downto 0 )
);
end segment;
architecture Behavioral of segment is
signal number:std_logic_vector( 3 downto 0 ); -- decimal 0 to 15
signal count:std_logic_vector( 15 downto 0 );
begin
process( clock ) begin
if clock'event and clock = '1' then
count <= count + 1;
if count = 0 then
if number = 0 then
selector <= "000";
elsif number = 1 then
selector <= "001";
elsif number = 2 then
selector <= "010";
elsif number = 3 then
selector <= "011";
elsif number = 4 then
selector <= "100";
elsif number = 5 then
selector <= "101";------------
elsif number = 6 then
selector <= "000";
elsif number = 7 then
selector <= "001";
elsif number = 8 then
selector <= "010";
elsif number = 9 then
selector <= "011";
elsif number = 10 then
selector <= "100";
elsif number = 11 then
selector <= "101";-------
elsif number = 12 then
selector <= "000";
elsif number = 13 then
selector <= "001";
elsif number = 14 then
selector <= "010";
elsif number = 15 then
selector <= "011";
end if;
number <= number + 1;
end if;
end if;
end process;
segment_data <=
"01000000" when number = 0 else --0
"01111001" when number = 1 else --1
"00100100" when number = 2 else --2
"00110000" when number = 3 else --3
"00011001" when number = 4 else --4
"00010010" when number = 5 else --5
"00000010" when number = 6 else --6
"01111000" when number = 7 else --7
"00000000" when number = 8 else --8
"00010000" when number = 9 else --9
"00001000" when number = 10 else --A
"00000011" when number = 11 else --B
"01000110" when number = 12 else --C
"00100001" when number = 13 else --D
"00000110" when number = 14 else --E
"00001110"; --F
end Behavioral;
|
mit
|
fa2ae6311730a4cc584c551b5838e26d
| 0.581795 | 3.357746 | false | false | false | false |
Digilent/vivado-library
|
ip/MIPI_D_PHY_RX/hdl/GlitchFilter.vhd
| 1 | 3,250 |
-------------------------------------------------------------------------------
--
-- File: GlitchFilter.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI D-PHY Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module filters any pulses on sIn lasting less than the number of
-- periods specified in kNoOfPeriodsToFilter. The output sOut will be
-- delayed by kNoOfPeriodsToFilter cycles, but glitch-free.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity GlitchFilter is
Generic (
kNoOfPeriodsToFilter : natural);
Port (
SampleClk : in STD_LOGIC;
sIn : in STD_LOGIC;
sOut : out STD_LOGIC;
sRst : in STD_LOGIC);
end GlitchFilter;
architecture Behavioral of GlitchFilter is
signal cntPeriods : natural range 0 to kNoOfPeriodsToFilter - 1 := kNoOfPeriodsToFilter - 1;
signal sIn_q : std_logic;
begin
Bypass: if kNoOfPeriodsToFilter = 0 generate
sOut <= sIn;
end generate Bypass;
Filter: if kNoOfPeriodsToFilter > 0 generate
process (SampleClk)
begin
if Rising_Edge(SampleClk) then
sIn_q <= sIn;
if (cntPeriods = 0) then
sOut <= sIn_q;
end if;
end if;
end process;
PeriodCounter: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (sIn_q /= sIn or sRst = '1') then --edge detected
cntPeriods <= kNoOfPeriodsToFilter - 1; --reset counter
elsif (cntPeriods /= 0) then
cntPeriods <= cntPeriods - 1; --count down
end if;
end if;
end process PeriodCounter;
end generate Filter;
end Behavioral;
|
mit
|
f61a865752124228eba41e19a032dce9
| 0.641846 | 4.79351 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodDigitizerController/tb/AD96xx_92xx_RegisterDecode.vhd
| 1 | 22,016 |
-------------------------------------------------------------------------------
--
-- File: AD96xx_92xx_RegisterDecode.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module implements the register set for the AD96xx and AD92xx
-- simulation models
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.PkgZmodDigitizer.all;
entity AD96xx_92xx_RegisterDecode is
Generic (
-- Parameter identifying the Zmod:
-- 0 -> Zmod Scope 1410 - 105 (AD9648)
-- 1 -> Zmod Scope 1010 - 40 (AD9204)
-- 2 -> Zmod Scope 1010 - 125 (AD9608)
-- 3 -> Zmod Scope 1210 - 40 (AD9231)
-- 4 -> Zmod Scope 1210 - 125 (AD9628)
-- 5 -> Zmod Scope 1410 - 40 (AD9251)
-- 6 -> Zmod Scope 1410 - 125 (AD9648)
kZmodID : integer range 0 to 6 := 6;
-- Register address width
kAddrWidth : integer range 0 to 32 := 13;
-- Register data width: only 8 data bits currently supported
kRegDataWidth : integer range 0 to 32 := 8
);
Port (
-- 100MHZ clock input
SysClk100 : in STD_LOGIC;
-- Reset signal asynchronously asserted and synchronously
-- de-asserted (in SysClk100 domain)
asRst_n : in STD_LOGIC;
-- When InsertError is asserted the model produces an erroneous reading for register address x01
InsertError : in STD_LOGIC;
-- Signal indicating that the data phase of he register write SPI transaction is completed and aDataDecode is valid
sDataWriteDecodeReady : in STD_LOGIC;
-- Signal indicating that the address phase of the SPI transaction is completed and aAddrDecode is valid
sAddrDecodeReady : in STD_LOGIC;
-- Input register data used to update internal egister values for write register operations
sDataDecode : in STD_LOGIC_VECTOR (kRegDataWidth-1 downto 0);
-- Register address input
sAddrDecode : in STD_LOGIC_VECTOR (kAddrWidth-1 downto 0);
-- Output register data produced by this module upon address decode for register read operations
sRegDataOut : out STD_LOGIC_VECTOR (kRegDataWidth-1 downto 0)
);
end AD96xx_92xx_RegisterDecode;
architecture Behavioral of AD96xx_92xx_RegisterDecode is
signal sAddrDecodeReadyPulse, sAddrDecodeReadyDly : std_logic := '0';
signal sDataWriteDecodeReadyPulse, sDataWriteDecodeReadyDly : std_logic := '0';
signal sReg00 : std_logic_vector(7 downto 0) := x"18";
signal sReg01 : std_logic_vector(7 downto 0) := SelADC_ID(kZmodID);
signal sReg02 : std_logic_vector(7 downto 0) := SelADC_Grade(kZmodID);
signal sReg05 : std_logic_vector(7 downto 0) := x"03";
signal sRegFF : std_logic_vector(7 downto 0) := x"00";
signal sReg08ChA : std_logic_vector(7 downto 0) := x"00";
signal sReg08ChB : std_logic_vector(7 downto 0) := x"00";
signal sReg09 : std_logic_vector(7 downto 0) := x"01";
signal sReg0B : std_logic_vector(7 downto 0) := x"00";
signal sReg0C : std_logic_vector(7 downto 0) := x"00";
signal sReg0DChA : std_logic_vector(7 downto 0) := x"00";
signal sReg0DChB : std_logic_vector(7 downto 0) := x"00";
signal sReg10ChA : std_logic_vector(7 downto 0) := x"00";
signal sReg10ChB : std_logic_vector(7 downto 0) := x"00";
signal sReg14ChA : std_logic_vector(7 downto 0) := x"00";
signal sReg14ChB : std_logic_vector(7 downto 0) := x"00";
signal sReg15 : std_logic_vector(7 downto 0) := x"00";
signal sReg16 : std_logic_vector(7 downto 0) := x"00";
signal sReg17 : std_logic_vector(7 downto 0) := x"00";
signal sReg18 : std_logic_vector(7 downto 0) := x"04";
signal sReg19 : std_logic_vector(7 downto 0) := x"00";
signal sReg1A : std_logic_vector(7 downto 0) := x"00";
signal sReg1B : std_logic_vector(7 downto 0) := x"00";
signal sReg1C : std_logic_vector(7 downto 0) := x"00";
signal sReg2A : std_logic_vector(7 downto 0) := x"01";
signal sReg2EChA : std_logic_vector(7 downto 0) := x"01";
signal sReg2EChB : std_logic_vector(7 downto 0) := x"01";
signal sReg3A : std_logic_vector(7 downto 0) := x"01";
signal sReg100 : std_logic_vector(7 downto 0) := x"00";
signal sReg101 : std_logic_vector(7 downto 0) := x"80";
signal sReg102 : std_logic_vector(7 downto 0) := x"00";
signal sReg00_TimerRst_n : std_logic;
signal sResetReg00 : std_logic;
signal sReg00_Timer : unsigned (23 downto 0);
signal sAddrAux : integer range 0 to 511;
begin
sAddrAux <= to_integer (unsigned (std_logic_vector'((sAddrDecode))));
-- The following section generates a pulse when sAddrDecodeReady is asserted.
-- This pulse indicates that the command phase of the SPI read transaction is
-- completed and that sAddrDecode contains valid data.
ProcAddrDecodeDly: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sAddrDecodeReadyDly <= '0';
elsif (rising_edge(SysClk100)) then
sAddrDecodeReadyDly <= sAddrDecodeReady;
end if;
end process;
sAddrDecodeReadyPulse <= sAddrDecodeReady and (not sAddrDecodeReadyDly);
-- Timer used to reset the soft reset bit of the SPI port config register
-- (Reg00).
ProcReg00Timer: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sReg00_Timer <= (others => '0');
elsif (rising_edge(SysClk100)) then
if (sReg00_TimerRst_n = '0') then
sReg00_Timer <= (others => '0');
else
sReg00_Timer <= sReg00_Timer + 1;
end if;
end if;
end process;
-- If the soft reset bit of Reg00 is set over the command interface, it is reset by the AD96xx when the
-- reset operation completes. The amount of time required not specified (20us considered for this model).
ProcResetReg00: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sResetReg00 <= '0';
elsif (rising_edge(SysClk100)) then
if (sReg00_Timer = kCountResetResumeSim) then
sResetReg00 <= '1';
else
sResetReg00 <= '0';
end if;
end if;
end process;
-- Process managing register read operations
ReadRegister: process(SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sRegDataOut <= (others => '0');
elsif (rising_edge (SysClk100)) then
if (sAddrDecodeReadyPulse = '1') then
case (sAddrDecode) is
when "0000000000000" =>
sRegDataOut <= sReg00;
when "0000000000001" =>
if (InsertError = '0') then
sRegDataOut <= sReg01;
else
sRegDataOut <= x"00";
end if;
when "0000000000010" =>
sRegDataOut <= sReg02;
when "0000000000101" =>
sRegDataOut <= sReg05;
when "0000011111111" =>
sRegDataOut <= sRegFF;
when "0000000001000" =>
if (sReg05(1 downto 0) = "00") then
sRegDataOut <= x"00";
report "Attempt to read local register (x08) with device index set to b00." & LF & HT & HT
severity ERROR;
elsif (sReg05(1 downto 0) = "01") then
sRegDataOut <= sReg08ChA;
elsif (sReg05(1 downto 0) = "10") then
sRegDataOut <= sReg08ChB;
elsif (sReg05(1 downto 0) = "11") then
sRegDataOut <= x"00";
report "Attempt to read local register (x08) with device index set to b11." & LF & HT & HT
severity ERROR;
end if;
when "0000000010001" =>
sRegDataOut <= sReg09;
when "0000000001011" =>
sRegDataOut <= sReg0B;
when "0000000001100" =>
sRegDataOut <= sReg0C;
when "0000000001101" =>
if (sReg05(1 downto 0) = "00") then
sRegDataOut <= x"00";
report "Attempt to read local register (x0D) with device index set to b00." & LF & HT & HT
severity ERROR;
elsif (sReg05(1 downto 0) = "01") then
sRegDataOut <= sReg0DChA;
elsif (sReg05(1 downto 0) = "10") then
sRegDataOut <= sReg0DChB;
elsif (sReg05(1 downto 0) = "11") then
sRegDataOut <= x"00";
report "Attempt to read local register (x0D) with device index set to b11." & LF & HT & HT
severity ERROR;
end if;
when "0000000010000" =>
if (sReg05(1 downto 0) = "00") then
sRegDataOut <= x"00";
report "Attempt to read local register (x10) with device index set to b00." & LF & HT & HT
severity ERROR;
elsif (sReg05(1 downto 0) = "01") then
sRegDataOut <= sReg10ChA;
elsif (sReg05(1 downto 0) = "10") then
sRegDataOut <= sReg10ChB;
elsif (sReg05(1 downto 0) = "11") then
sRegDataOut <= x"00";
report "Attempt to read local register (x10) with device index set to b11." & LF & HT & HT
severity ERROR;
end if;
when "0000000010100" =>
if (sReg05(1 downto 0) = "00") then
sRegDataOut <= x"00";
report "Attempt to read local register (x14) with device index set to b00." & LF & HT & HT
severity ERROR;
elsif (sReg05(1 downto 0) = "01") then
sRegDataOut <= sReg14ChA;
elsif (sReg05(1 downto 0) = "10") then
sRegDataOut <= sReg14ChB;
elsif (sReg05(1 downto 0) = "11") then
sRegDataOut <= x"00";
report "Attempt to read local register (x14) with device index set to b11." & LF & HT & HT
severity ERROR;
end if;
when "0000000010101" =>
sRegDataOut <= sReg15;
when "0000000010110" =>
sRegDataOut <= sReg16;
when "0000000010111" =>
sRegDataOut <= sReg17;
when "0000000011000" =>
sRegDataOut <= sReg18;
when "0000000011001" =>
sRegDataOut <= sReg19;
when "0000000011010" =>
sRegDataOut <= sReg1A;
when "0000000011011" =>
sRegDataOut <= sReg1B;
when "0000000011100" =>
sRegDataOut <= sReg1C;
when "0000000101010" =>
sRegDataOut <= sReg2A;
when "0000000101110" =>
if (sReg05(1 downto 0) = "00") then
sRegDataOut <= x"00";
report "Attempt to read local register (x14) with device index set to b00." & LF & HT & HT
severity ERROR;
elsif (sReg05(1 downto 0) = "01") then
sRegDataOut <= sReg2EChA;
elsif (sReg05(1 downto 0) = "10") then
sRegDataOut <= sReg2EChB;
elsif (sReg05(1 downto 0) = "11") then
sRegDataOut <= x"00";
report "Attempt to read local register (x14) with device index set to b11." & LF & HT & HT
severity ERROR;
end if;
when "0000000111010" =>
sRegDataOut <= sReg3A;
when "0000100000000" =>
sRegDataOut <= sReg100;
when "0000100000001" =>
sRegDataOut <= sReg101;
when "0000100000010" =>
sRegDataOut <= sReg102;
when others =>
sRegDataOut <= x"00";
report "Invalid Read Address." & LF & HT & HT
severity ERROR;
end case;
end if;
end if;
end process ReadRegister;
-- The following section generates a pulse when sDataWriteDecodeReady is asserted.
-- This pulse indicates that the command phase of the SPI write transaction is
-- completed and that sAddrDecode contains valid data.
ProcDataDecodeDly: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sDataWriteDecodeReadyDly <= '0';
elsif (rising_edge(SysClk100)) then
sDataWriteDecodeReadyDly <= sDataWriteDecodeReady;
end if;
end process;
sDataWriteDecodeReadyPulse <= sDataWriteDecodeReady and (not sDataWriteDecodeReadyDly);
-- Process managing register write operations (Reg00 is treated separately).
WriteRegister: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sReg01 <= SelADC_ID(kZmodID);
sReg02 <= SelADC_Grade(kZmodID);
sReg05 <= x"03";
sRegFF <= x"00";
sReg08ChA <= x"00";
sReg08ChB <= x"00";
sReg09 <= x"01";
sReg0B <= x"00";
sReg0C <= x"00";
sReg0DChA <= x"00";
sReg0DChB <= x"00";
sReg10ChA <= x"00";
sReg10ChB <= x"00";
sReg14ChA <= x"00";
sReg14ChB <= x"00";
sReg15 <= x"00";
sReg16 <= x"00";
sReg17 <= x"00";
sReg18 <= x"04";
sReg19 <= x"00";
sReg1A <= x"00";
sReg1B <= x"00";
sReg1C <= x"00";
sReg2A <= x"01";
sReg2EChA <= x"01";
sReg2EChB <= x"01";
sReg3A <= x"01";
sReg100 <=x"00";
sReg101 <= x"80";
sReg102 <= x"00";
elsif (rising_edge (SysClk100)) then
if (sDataWriteDecodeReadyPulse = '1') then
case (sAddrDecode) is
when "0000000000000" =>
--Reg00 treated separately
when "0000000000001" =>
report "Attempt to write to a READ ONLY location." & integer'image(sAddrAux) & LF & HT & HT
severity ERROR;
when "0000000000010" =>
report "Attempt to write to a READ ONLY location." & integer'image(sAddrAux) & LF & HT & HT
severity ERROR;
when "0000000000101" =>
sReg05 <= sDataDecode;
when "0000011111111" =>
--The transfer register auto clears in an unspecified amount
--of time. For the IP simulation purpose this register can be
--considered constant (x"00").
--sRegFF <= sDataDecode;
when "0000000001000" =>
if (sReg05(1 downto 0) = "00") then
report "Attempt to write local register (x08) with device index set to b00." & LF & HT & HT
severity ERROR;
elsif (sReg05(1 downto 0) = "01") then
sReg08ChA <= sDataDecode;
elsif (sReg05(1 downto 0) = "10") then
sReg08ChB <= sDataDecode;
elsif (sReg05(1 downto 0) = "11") then
sReg08ChA <= sDataDecode;
sReg08ChB <= sDataDecode;
end if;
when "0000000010001" =>
sReg09 <= sDataDecode;
when "0000000001011" =>
sReg0B <= sDataDecode;
when "0000000001100" =>
sReg0C <= sDataDecode;
when "0000000001101" =>
if (sReg05(1 downto 0) = "00") then
report "Attempt to write local register (x0D) with device index set to b00." & LF & HT & HT
severity ERROR;
elsif (sReg05(1 downto 0) = "01") then
sReg0DChA <= sDataDecode;
elsif (sReg05(1 downto 0) = "10") then
sReg0DChB <= sDataDecode;
elsif (sReg05(1 downto 0) = "11") then
sReg0DChA <= sDataDecode;
sReg0DChB <= sDataDecode;
end if;
when "0000000010000" =>
if (sReg05(1 downto 0) = "00") then
report "Attempt to write local register (x10) with device index set to b00." & LF & HT & HT
severity ERROR;
elsif (sReg05(1 downto 0) = "01") then
sReg10ChA <= sDataDecode;
elsif (sReg05(1 downto 0) = "10") then
sReg10ChB <= sDataDecode;
elsif (sReg05(1 downto 0) = "11") then
sReg10ChA <= sDataDecode;
sReg10ChB <= sDataDecode;
end if;
when "0000000010100" =>
sReg14ChA(1 downto 0) <= sDataDecode(1 downto 0);
sReg14ChB(1 downto 0) <= sDataDecode(1 downto 0);
sReg14ChA(3) <= sDataDecode(3);
sReg14ChB(3) <= sDataDecode(3);
sReg14ChA(7 downto 5) <= sDataDecode(7 downto 5);
sReg14ChB(7 downto 5) <= sDataDecode(7 downto 5);
if (sReg05(1 downto 0) = "00") then
report "Attempt to write local register (x10) with device index set to b00." & LF & HT & HT
severity ERROR;
elsif (sReg05(1 downto 0) = "01") then
sReg14ChA(2) <= sDataDecode(2);
sReg14ChA(4) <= sDataDecode(4);
elsif (sReg05(1 downto 0) = "10") then
sReg14ChB(2) <= sDataDecode(2);
sReg14ChB(4) <= sDataDecode(4);
elsif (sReg05(1 downto 0) = "11") then
sReg14ChA(2) <= sDataDecode(2);
sReg14ChA(4) <= sDataDecode(4);
sReg14ChB(2) <= sDataDecode(2);
sReg14ChB(4) <= sDataDecode(4);
end if;
when "0000000010101" =>
sReg15 <= sDataDecode;
when "0000000010110" =>
sReg16 <= sDataDecode;
when "0000000010111" =>
sReg17 <= sDataDecode;
when "0000000011000" =>
sReg18 <= sDataDecode;
when "0000000011001" =>
sReg19 <= sDataDecode;
when "0000000011010" =>
sReg1A <= sDataDecode;
when "0000000011011" =>
sReg1B <= sDataDecode;
when "0000000011100" =>
sReg1C <= sDataDecode;
when "0000000101010" =>
sReg2A <= sDataDecode;
when "0000000101110" =>
if (sReg05(1 downto 0) = "00") then
report "Attempt to write local register (x2E) with device index set to b00." & LF & HT & HT
severity ERROR;
elsif (sReg05(1 downto 0) = "01") then
sReg2EChA <= sDataDecode;
elsif (sReg05(1 downto 0) = "10") then
sReg2EChB <= sDataDecode;
elsif (sReg05(1 downto 0) = "11") then
sReg2EChA <= sDataDecode;
sReg2EChB <= sDataDecode;
end if;
when "0000000111010" =>
sReg3A <= sDataDecode;
when "0000100000000" =>
sReg100 <= sDataDecode;
when "0000100000001" =>
sReg101 <= sDataDecode;
when "0000100000010" =>
sReg102 <= sDataDecode;
when others =>
report "Invalid Write Address." & integer'image(sAddrAux) & LF & HT & HT
severity ERROR;
end case;
end if;
end if;
end process WriteRegister;
-- Process managing register write operation for Reg00 individually
WriteRegister00: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sReg00 <= x"18";
sReg00_TimerRst_n <= '0';
elsif (rising_edge (SysClk100)) then
if (sDataWriteDecodeReady = '1') then
if (sAddrDecode = "0000000000000") then
sReg00 <= sReg00 or (sDataDecode and aReg00_Mask);
if (sDataDecode(5) = '1' and sDataDecode(2) = '1') then
sReg00_TimerRst_n <= '1';
elsif (sDataDecode(5) = '1' and sDataDecode(2) = '0') then
report "Reg00 bit 5 and 2 must be mirrored." & LF & HT & HT
severity ERROR;
elsif (sDataDecode(5) = '0' and sDataDecode(2) = '1') then
report "Reg00 bit 5 and 2 must be mirrored." & LF & HT & HT
severity ERROR;
end if;
end if;
elsif (sResetReg00 = '1') then
sReg00(5) <= '0';
sReg00(2) <= '0';
sReg00_TimerRst_n <= '0';
end if;
end if;
end process WriteRegister00;
end Behavioral;
|
mit
|
9a55bd79a471bdd1c30a2de60949a38e
| 0.561501 | 4.283268 | false | false | false | false |
scottlbaker/Nova-SOC
|
src/rand8.vhd
| 2 | 3,281 |
--======================================================================
-- rand8.vhd :: Random Number Generator
--
-- (c) Scott L. Baker, Sierra Circuit Design
--======================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity RAND8 is
port(
CS : in std_logic; -- chip select
WE : in std_logic; -- write enable
REG_SEL : in std_logic; -- register select
WR_DATA : in std_logic_vector(7 downto 0); -- write data
RD_DATA : out std_logic_vector(7 downto 0); -- read data
RESET : in std_logic; -- system reset
FEN : in std_logic; -- clock enable
FCLK : in std_logic -- fast clock
);
end entity RAND8;
architecture BEHAVIORAL of RAND8 is
--=================================================================
-- Signal definitions
--=================================================================
signal MASK : std_logic_vector(7 downto 0); -- mask
signal CX : std_logic_vector(8 downto 0); -- counter
signal CEN : std_logic; -- count enable
begin
--=============================================
-- Register Write
--=============================================
REGISTER_WRITE:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
if (CS = '1' and WE = '1') then
if (REG_SEL = '1') then
MASK <= WR_DATA;
else
CEN <= WR_DATA(0);
end if;
end if;
if (RESET = '1') then
MASK <= (others => '1');
CEN <= '0';
end if;
end if;
end process;
--==================================================
-- Counter
--==================================================
COUNTER:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
if (CEN = '1') then
-- linear-feedback counter
CX(0) <= CX(8) xnor CX(3);
CX(8 downto 1) <= CX(7 downto 0);
end if;
-- reset state
if (RESET = '1') then
CX <= (others => '0');
end if;
end if;
end process;
--==================================================
-- Output Register
--==================================================
OUTPUT_REG:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
if (CS = '1' and FEN = '1') then
RD_DATA(7) <= CX(7) and MASK(7);
RD_DATA(6) <= CX(3) and MASK(6);
RD_DATA(5) <= CX(5) and MASK(5);
RD_DATA(4) <= CX(1) and MASK(4);
RD_DATA(3) <= CX(0) and MASK(3);
RD_DATA(2) <= CX(4) and MASK(2);
RD_DATA(1) <= CX(2) and MASK(1);
RD_DATA(0) <= CX(6) and MASK(0);
end if;
-- reset state
if (RESET = '1') then
RD_DATA <= (others => '0');
end if;
end if;
end process;
end architecture BEHAVIORAL;
|
gpl-3.0
|
31e3f4a5b5b4ae35ecef42443f169095
| 0.352941 | 4.463946 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/start_for_Loop_lotde.vhd
| 1 | 4,490 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity start_for_Loop_lotde_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end start_for_Loop_lotde_shiftReg;
architecture rtl of start_for_Loop_lotde_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity start_for_Loop_lotde is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of start_for_Loop_lotde is
component start_for_Loop_lotde_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_start_for_Loop_lotde_shiftReg : start_for_Loop_lotde_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
ab0d7d9743ec6b1411009e15728a8cdb
| 0.53118 | 3.549407 | false | false | false | false |
grafi-tt/Maizul
|
fpu-misc/original/fsqrt.vhd
| 1 | 1,437 |
-- written by panooz
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fsqrt is
port (
clk : in std_logic;
flt_in : in std_logic_vector(31 downto 0);
flt_out : out std_logic_vector(31 downto 0));
end fsqrt;
architecture blackbox of fsqrt is
component fsqrtTable is
port (
clk : in std_logic;
addr : in std_logic_vector(9 downto 0);
output : out std_logic_vector(35 downto 0));
end component;
signal sign: std_logic;
signal exp_out,exp_in : std_logic_vector(7 downto 0);
signal frac_out : std_logic_vector(22 downto 0);
signal key : std_logic_vector(9 downto 0);
signal rest : std_logic_vector(13 downto 0);
signal tvalue : std_logic_vector(35 downto 0);
signal const : std_logic_vector(22 downto 0);
signal grad : std_logic_vector(12 downto 0);
signal temp : std_logic_vector(26 downto 0);
begin
table : fsqrtTable port map(clk, key, tvalue);
sign <= flt_in(31);
exp_in <= flt_in(30 downto 23);
key <= flt_in(23 downto 14);
rest <= flt_in(13 downto 0);
const <= tvalue(35 downto 13);
grad <= tvalue(12 downto 0);
temp <= grad * rest;
frac_out <= const + ("000000000"&temp(26 downto 13));
exp_out <= (others => '1') when exp_in = 255 or exp_in = 0
else ('0' & exp_in(7 downto 1)) + 64 when exp_in(0) = '1'
else ('0' & exp_in(7 downto 1)) + 63;
flt_out <= sign & exp_out & frac_out;
end blackbox;
|
bsd-2-clause
|
895a74803d6a0394312971c69cfbbea8
| 0.653445 | 3.057447 | false | false | false | false |
scottlbaker/Nova-SOC
|
src/timer16.vhd
| 2 | 5,005 |
--======================================================================
-- timer.vhd :: A simple 16-bit Timer
--
-- (c) Scott L. Baker, Sierra Circuit Design
--======================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity TIMER is
port(
CS : in std_logic; -- chip select
WE : in std_logic; -- write enable
WR_DATA : in std_logic_vector(15 downto 0); -- write data
RD_DATA : out std_logic_vector(15 downto 0); -- read data
IRQ : out std_logic; -- Timer Interrupt
SEL_IC : in std_logic; -- select initial count
RESET : in std_logic; -- system reset
FCLK : in std_logic -- fast clock
);
end entity TIMER;
architecture BEHAVIORAL of TIMER is
--=================================================================
-- Signal definitions
--=================================================================
-- Registers
signal IC_REG : std_logic_vector(15 downto 0); -- initial count
-- Counters
signal PRE : std_logic_vector(14 downto 0); -- prescaler
signal CTR : std_logic_vector(15 downto 0); -- timer count
-- Counter Control
signal PEN : std_logic; -- Prescaler count enable
signal CEN : std_logic; -- Timer count enable
signal DBG : std_logic; -- Debug mode (no prescaler)
signal TRQ : std_logic; -- Timer interrupt
signal LOAD : std_logic; -- load counter
-- Terminal Counts
signal TC : std_logic; -- Timer terminal count
-- Terminal Count Constant
constant PRE_TC : std_logic_vector(14 downto 0) := "100101011100000";
constant DBG_TC : std_logic_vector(14 downto 0) := "000010101010101";
begin
--=============================================
-- Register Writes
--=============================================
REGISTER_WRITES:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
LOAD <= '0';
if (CS = '1' and WE = '1') then
if (SEL_IC = '1') then
IC_REG <= WR_DATA;
LOAD <= '1';
else
TRQ <= '0';
DBG <= WR_DATA(1);
CEN <= WR_DATA(0);
end if;
end if;
-- set timer interrupt
if (TC = '1') then
TRQ <= '1';
end if;
if (RESET = '1') then
TRQ <= '0';
DBG <= '0';
CEN <= '0';
IC_REG <= (others => '0');
end if;
end if;
end process;
IRQ <= TRQ;
RD_DATA <= "000000000000000" & TRQ;
--==================================================
-- Prescaler (divide by 16000)
--==================================================
PRESCALER:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
PEN <= '0';
-- If the counter is enabled then count
if (CEN = '1') then
-- linear-feedback counter
PRE(0) <= PRE(14) xnor PRE(0);
PRE(14 downto 1) <= PRE(13 downto 0);
-- use PRE_TC terminal count for 1-msec
-- use DBG_TC terminal count for debug
if (((DBG = '0') and (PRE = PRE_TC)) or
((DBG = '1') and (PRE = DBG_TC))) then
PRE <= (others => '0');
PEN <= '1';
end if;
end if;
-- reset state
if (RESET = '1') then
PRE <= (others => '0');
PEN <= '0';
end if;
end if;
end process;
--==================================================
-- Timer
--==================================================
TIMER_COUNTER:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
TC <= '0';
-- count at each prescaler terminal count
if (PEN = '1') then
CTR <= CTR - 1;
end if;
-- terminal count
if ((PEN = '1') and (CTR = "0000000000000001")) then
TC <= '1';
-- Reload the counter when the
-- terminal count is reached
CTR <= IC_REG;
end if;
-- load the counter on uP write
if (LOAD = '1') then
CTR <= IC_REG;
end if;
-- reset state
if (RESET = '1') then
CTR <= (others => '1');
TC <= '0';
end if;
end if;
end process;
end architecture BEHAVIORAL;
|
gpl-3.0
|
a6023ecf2a4e2aea33d04771136cba2b
| 0.385215 | 4.690722 | false | false | false | false |
Digilent/vivado-library
|
ip/video_scaler/hdl/vhdl/video_scaler_mul_kbM.vhd
| 1 | 2,718 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity video_scaler_mul_kbM_MulnS_1 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(28 - 1 downto 0);
b: in std_logic_vector(20 - 1 downto 0);
p: out std_logic_vector(48 - 1 downto 0));
end entity;
architecture behav of video_scaler_mul_kbM_MulnS_1 is
signal tmp_product : std_logic_vector(48 - 1 downto 0);
signal a_i : std_logic_vector(28 - 1 downto 0);
signal b_i : std_logic_vector(20 - 1 downto 0);
signal p_tmp : std_logic_vector(48 - 1 downto 0);
signal a_reg0 : std_logic_vector(28 - 1 downto 0);
signal b_reg0 : std_logic_vector(20 - 1 downto 0);
signal buff0 : std_logic_vector(48 - 1 downto 0);
signal buff1 : std_logic_vector(48 - 1 downto 0);
signal buff2 : std_logic_vector(48 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff2;
tmp_product <= std_logic_vector(resize(unsigned(std_logic_vector(signed(a_reg0) * signed(b_reg0))), 48));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg0 <= a_i;
b_reg0 <= b_i;
buff0 <= tmp_product;
buff1 <= buff0;
buff2 <= buff1;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity video_scaler_mul_kbM is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of video_scaler_mul_kbM is
component video_scaler_mul_kbM_MulnS_1 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
video_scaler_mul_kbM_MulnS_1_U : component video_scaler_mul_kbM_MulnS_1
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
|
mit
|
d07af151be885beb3893730939283637
| 0.544886 | 3.380597 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
Interpolation_not_complete/Gout.vhd
| 1 | 4,517 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:59:03 07/14/05
-- Design Name:
-- Module Name: Gout - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Gout is
generic
(
width : integer := 8
);
Port
(
-- Dhor42
g1 : in std_logic_vector( width downto 0 ); -- G41
g2 : in std_logic_vector( width downto 0 ); -- G43
b1 : in std_logic_vector( width downto 0 ); -- R40
b2 : in std_logic_vector( width downto 0 ); -- R42
b3 : in std_logic_vector( width downto 0 ); -- R44
b4 : in std_logic_vector( width downto 0 ); -- R42
-- Dver42
g1_2 : in std_logic_vector( width downto 0 ); -- G32
g2_2 : in std_logic_vector( width downto 0 ); -- G52
b1_2 : in std_logic_vector( width downto 0 ); -- R22
b2_2 : in std_logic_vector( width downto 0 ); -- R42
b3_2 : in std_logic_vector( width downto 0 ); -- R62
b4_2 : in std_logic_vector( width downto 0 ); -- R42
-- Dhor44
g3 : in std_logic_vector( width downto 0 ); -- G43
g4 : in std_logic_vector( width downto 0 ); -- G45
b5 : in std_logic_vector( width downto 0 ); -- R42
b6 : in std_logic_vector( width downto 0 ); -- R44
b7 : in std_logic_vector( width downto 0 ); -- R46
b8 : in std_logic_vector( width downto 0 ); -- R44
-- Dver44
g3_2 : in std_logic_vector( width downto 0 ); -- G34
g4_2 : in std_logic_vector( width downto 0 ); -- G54
b5_2 : in std_logic_vector( width downto 0 ); -- R24
b6_2 : in std_logic_vector( width downto 0 ); -- R44
b7_2 : in std_logic_vector( width downto 0 ); -- R64
b8_2 : in std_logic_vector( width downto 0 ); -- R44
G_bar1 : out std_logic_vector( width downto 0 );
G_bar2 : out std_logic_vector( width downto 0 )
-- E_in1 : in std_logic_vector( width downto 0 ); -- G22
-- E_in2 : in std_logic_vector( width downto 0 ); -- G23
-- E_in3 : in std_logic_vector( width downto 0 ); -- G43
-- E_in4 : in std_logic_vector( width downto 0 ); -- G24
-- E : out std_logic_vector( 18 downto 0 )
);
end Gout;
architecture Behavioral of Gout is
component combine_g_bar
Port ( g1 : in std_logic_vector(8 downto 0);
g2 : in std_logic_vector(8 downto 0);
b1 : in std_logic_vector(8 downto 0);
b2 : in std_logic_vector(8 downto 0);
b3 : in std_logic_vector(8 downto 0);
b4 : in std_logic_vector(8 downto 0);
g1_2 : in std_logic_vector(8 downto 0);
g2_2 : in std_logic_vector(8 downto 0);
b1_2 : in std_logic_vector(8 downto 0);
b2_2 : in std_logic_vector(8 downto 0);
b3_2 : in std_logic_vector(8 downto 0);
b4_2 : in std_logic_vector(8 downto 0);
g_bar : out std_logic_vector(8 downto 0));
end component;
--component combine_E_out_G_in
-- Port ( G1 : in std_logic_vector(8 downto 0);
-- G_bar1 : in std_logic_vector(8 downto 0);
-- G2 : in std_logic_vector(8 downto 0);
-- G3 : in std_logic_vector(8 downto 0);
-- G4 : in std_logic_vector(8 downto 0);
-- G_bar2 : in std_logic_vector(8 downto 0);
-- E : out std_logic_vector(18 downto 0));
--end component;
--signal G_bar1:std_logic_vector(8 downto 0);
--signal G_bar2:std_logic_vector(8 downto 0);
--signal E_OUT:std_logic_vector(18 downto 0);
begin
element1: combine_g_bar port map(g1 , g2 , b1 , b2 , b3 , b4 ,g1_2 , g2_2 , b1_2 , b2_2 , b3_2 , b4_2 , G_bar1); -- ~G42
element2: combine_g_bar port map(g3 , g4 , b5 , b6 , b7 , b8 ,g3_2 , g4_2 , b5_2 , b6_2 , b7_2 , b8_2 , G_bar2); -- ~G44
--G_bar1 <= G_bar1;
--G_bar2 <= G_bar2;
-- Ehor = ( | G22 - ~G42 | + 2 * | G23 - G43 | + | G24 - ~G44 | * 256 / ( G23 + G43 )
--element3: combine_E_out_G_in port map(E_in1 , G_bar1 , E_in2 , E_in3 , E_in4 , G_bar2 ,E_OUT);
--E <= E_OUT;
end Behavioral;
|
mit
|
a12d3a2fe9417c1de574c34ad9737f7f
| 0.550365 | 2.772867 | false | false | false | false |
grafi-tt/Maizul
|
src/Unit/FPU/FtoI.vhd
| 1 | 1,944 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FtoI is
port (
clk : in std_logic;
f : in std_logic_vector(31 downto 0);
i : out std_logic_vector(31 downto 0));
end FtoI;
architecture dataflow of FtoI is
signal x_len : std_logic_vector(8 downto 0);
signal u_frc_4, u_frc_3, u_frc_2, u_frc_1, u_frc_0, u_frc_o, u_frc_v : unsigned(31 downto 0);
signal any_4, any_3, any_2, any_1, any_0, any_o : std_logic;
signal round : std_logic;
begin
x_len <= std_logic_vector(unsigned('0' & f(30 downto 23)) - "001111110");
any_4 <= '0';
u_frc_4 <= unsigned('1' & f(22 downto 0) & "00000000");
any_3 <= '1' when x_len(4) = '0' and u_frc_4(15 downto 0) /= 0 else any_4;
u_frc_3 <= u_frc_4 srl 16 when x_len(4) = '0' else u_frc_4;
any_2 <= '1' when x_len(3) = '0' and u_frc_3( 7 downto 0) /= 0 else any_3;
u_frc_2 <= u_frc_3 srl 8 when x_len(3) = '0' else u_frc_3;
any_1 <= '1' when x_len(2) = '0' and u_frc_2( 3 downto 0) /= 0 else any_2;
u_frc_1 <= u_frc_2 srl 4 when x_len(2) = '0' else u_frc_2;
any_0 <= '1' when x_len(1) = '0' and u_frc_1( 1 downto 0) /= 0 else any_1;
u_frc_0 <= u_frc_1 srl 2 when x_len(1) = '0' else u_frc_1;
any_o <= '1' when x_len(0) = '0' and u_frc_0( 0 downto 0) /= 0 else any_0;
u_frc_o <= u_frc_0 srl 1 when x_len(0) = '0' else u_frc_0;
u_frc_v <= u_frc_o srl 1;
round <= (u_frc_o(0) and any_o) or (u_frc_o(1) and u_frc_o(0));
i <= x"00000000" when x_len(8) = '1' else
x"7FFFFFFF" when f(31) = '0' and x_len(7 downto 5) /= "000" else
x"80000000" when f(31) = '1' and x_len(7 downto 5) /= "000" else
std_logic_vector(u_frc_v) when f(31) = '0' and round = '0' else
std_logic_vector(u_frc_v + 1) when f(31) = '0' and round = '1' else
std_logic_vector(0 - u_frc_v) when round = '0' else
std_logic_vector(not u_frc_v);
end dataflow;
|
bsd-2-clause
|
2d6ee4dab7287a45bb90f995ed56ac61
| 0.55144 | 2.364964 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
Interpolation_not_complete/CalculateG.vhd
| 1 | 1,474 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
entity CalculateG is
generic
(
width : integer := 8
);
port
(
Difference0 : in std_logic_vector( 18 downto 0 );
Difference01 : in std_logic_vector( 18 downto 0 );
IHorizontal : in std_logic_vector( width downto 0 );
IVertical : in std_logic_vector( width downto 0 );
Difference7 : in std_logic_vector( width downto 0 );
DifferenceDver : in std_logic_vector( width + 2 downto 0 );
DifferenceDhor : in std_logic_vector( width + 2 downto 0 );
ElementG : out std_logic_vector( width downto 0 )
);
end CalculateG;
architecture Behavioral of CalculateG is
--signal PosThreshold : std_logic_vector( 10 downto 0 ) := "01111111111"; -- 1023
signal PosThreshold : std_logic_vector( 18 downto 0 ) := "0000000001111111111"; -- 1023
begin
process( Difference0, Difference01, IHorizontal, IVertical, Difference7, DifferenceDver, DifferenceDhor )
begin
if( Difference0( 18 ) /= '1' ) and ( Difference0>= PosThreshold ) then
ElementG <= IHorizontal;
elsif( Difference01( 18 ) /= '1' ) and ( Difference01 >= PosThreshold ) then
ElementG <= IVertical;
elsif DifferenceDhor < DifferenceDver then
ElementG <= IHorizontal;
elsif DifferenceDhor > DifferenceDver then
ElementG <= IVertical;
else
ElementG <= Difference7;
end if;
end process;
end Behavioral;
|
mit
|
0bc29bae377d55db7026dd782543a8ec
| 0.675034 | 3.694236 | false | false | false | false |
grafi-tt/Maizul
|
fpu-misc/original/fadd.vhd
| 1 | 2,990 |
-- written by panooz
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity fadd is
port (
clk : in std_logic;
go_in : in std_logic;
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
c : out std_logic_vector(31 downto 0);
go_out : out std_logic);
end fadd;
architecture blackbox of fadd is
signal state : std_logic_vector(3 downto 0) := "0000";
signal a_sign : std_logic;
signal a_exp : std_logic_vector(7 downto 0);
signal a_frac : std_logic_vector(24 downto 0);
signal b_sign : std_logic;
signal b_exp : std_logic_vector(7 downto 0);
signal b_frac : std_logic_vector(24 downto 0);
signal c_sign : std_logic;
signal c_exp : std_logic_vector(7 downto 0);
signal c_frac : std_logic_vector(24 downto 0);
signal zero : std_logic_vector(24 downto 0) := "0000000000000000000000000";
begin -- blackbox
setgo : process(clk)
begin
if rising_edge(clk) then
if state = "0110" then
go_out <= '1';
else
go_out <= '0';
end if;
end if;
end process;
main : process(clk)
begin
if rising_edge(clk) then
case state is
when "0000" =>
if go_in = '1' then
state <= "0001";
end if;
when "0001" =>
if a(30 downto 23) > b(30 downto 23) then
a_sign <= a(31);
a_exp <= a(30 downto 23);
a_frac <= "01" & a(22 downto 0);
b_sign <= b(31);
b_exp <= b(30 downto 23);
b_frac <= "01" & b(22 downto 0);
else
a_sign <= b(31);
a_exp <= b(30 downto 23);
a_frac <= "01" & b(22 downto 0);
b_sign <= a(31);
b_exp <= a(30 downto 23);
b_frac <= "01" & a(22 downto 0);
end if;
state <= "0010";
when "0010" =>
if conv_integer(a_exp - b_exp) < 24
then
b_frac <= zero(24 downto 24-conv_integer(a_exp - b_exp)) & b_frac(23 downto conv_integer(a_exp - b_exp));
else
b_frac <= zero;
end if;
state <= "0011";
when "0011" =>
if a_sign = b_sign then
c_frac <= a_frac + b_frac;
else
c_frac <= a_frac - b_frac;
end if;
c_exp <= a_exp;
c_sign <= a_sign;
state <= "0100";
when "0100" =>
if c_frac(24) = '1' then
c_exp <= c_exp + 1;
c_frac <= '0' & c_frac(24 downto 1);
end if;
state <= "0101";
when "0101" =>
c <= c_sign & c_exp & c_frac(22 downto 0);
state <= "0110";
when others => state <= "0000";
end case;
end if;
end process;
end blackbox;
|
bsd-2-clause
|
891e3dbd03dd26b1ed86dd69c3dc98aa
| 0.479933 | 3.424971 | false | false | false | false |
olajep/oh
|
src/adi/hdl/library/common/axi_streaming_dma_rx_fifo.vhd
| 1 | 3,554 |
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
--
-- In this HDL repository, there are many different and unique modules, consisting
-- of various HDL (Verilog or VHDL) components. The individual modules are
-- developed independently, and may be accompanied by separate and unique license
-- terms.
--
-- The user should read each of these license terms, and understand the
-- freedoms and responsibilities that he or she has by using this source/core.
--
-- This core is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-- A PARTICULAR PURPOSE.
--
-- Redistribution and use of source or resulting binaries, with or without modification
-- of this file, are permitted under one of the following two license terms:
--
-- 1. The GNU General Public License version 2 as published by the
-- Free Software Foundation, which can be found in the top level directory
-- of this repository (LICENSE_GPL2), and also online at:
-- <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
--
-- OR
--
-- 2. An ADI specific BSD license, which can be found in the top level directory
-- of this repository (LICENSE_ADIBSD), and also on-line at:
-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
-- This will allow to generate bit files and not release the source code,
-- as long as it attaches to an ADI device.
--
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dma_fifo;
entity axi_streaming_dma_rx_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable DMA interface
enable : in Boolean;
period_len : in integer range 0 to 65535;
-- Read port
m_axis_aclk : in std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(FIFO_DWIDTH-1 downto 0);
m_axis_tlast : out std_logic;
m_axis_tvalid : out std_logic;
m_axis_tkeep : out std_logic_vector(3 downto 0);
-- Write port
in_stb : in std_logic;
in_ack : out std_logic;
in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0)
);
end;
architecture imp of axi_streaming_dma_rx_fifo is
signal out_stb : std_logic;
signal period_count : integer range 0 to 65535;
signal last : std_logic;
begin
m_axis_tvalid <= out_stb;
fifo: entity dma_fifo
generic map (
RAM_ADDR_WIDTH => RAM_ADDR_WIDTH,
FIFO_DWIDTH => FIFO_DWIDTH
)
port map (
clk => clk,
resetn => resetn,
fifo_reset => fifo_reset,
in_stb => in_stb,
in_ack => in_ack,
in_data => in_data,
out_stb => out_stb,
out_ack => m_axis_tready,
out_data => m_axis_tdata
);
m_axis_tkeep <= "1111";
m_axis_tlast <= '1' when period_count = 0 else '0';
period_counter: process(m_axis_aclk) is
begin
if rising_edge(m_axis_aclk) then
if resetn = '0' then
period_count <= period_len;
else
if out_stb = '1' and m_axis_tready = '1' then
if period_count = 0 then
period_count <= period_len;
else
period_count <= period_count - 1;
end if;
end if;
end if;
end if;
end process;
end;
|
mit
|
f8cc1d1c79e7d4e16f0b4b8b383a56f2
| 0.615644 | 3.420597 | false | false | false | false |
JL-Grande/Ascensor_SED
|
ASCENSOR/tb_antirrebote.vhd
| 1 | 1,555 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_antirrebote IS
END tb_antirrebote;
ARCHITECTURE behavior OF tb_antirrebote IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT antirrebote
PORT(
CLK : IN std_logic;
RST : IN std_logic;
logic_IN : IN std_logic;
logic_OUT : OUT std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
signal logic_IN : std_logic := '0';
--Outputs
signal logic_OUT : std_logic;
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: antirrebote PORT MAP (
CLK => CLK,
RST => RST,
logic_IN => logic_IN,
logic_OUT => logic_OUT
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
RST <= '0';
logic_IN <= '0';
WAIT FOR 40 ns;
logic_IN <= '1';
WAIT FOR 10 ns;
RST <= '1';
WAIT FOR 10 ns;
logic_IN <= '0';
WAIT FOR 2 ns;
logic_IN <= '1';
WAIT FOR 3 ns;
RST <= '0';
WAIT FOR 47 ns;
logic_IN <= '0';
WAIT FOR 4 ns;
logic_IN <= '1';
WAIT FOR 2 ns;
logic_IN <= '0';
WAIT FOR 3 ns;
logic_IN <= '1';
WAIT FOR 20 ns;
logic_IN <= '0';
WAIT FOR 50 ns;
ASSERT false
REPORT "Simulación finalizada. Test superado."
SEVERITY FAILURE;
end process;
END;
|
gpl-3.0
|
cfb8b9eb0339a2fa55a5aa0d59ef0062
| 0.57492 | 3.179959 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_gamma_correction_1_0/hdl/vhdl/Loop_loop_height_dEe.vhd
| 1 | 9,702 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Loop_loop_height_dEe_rom is
generic(
dwidth : integer := 8;
awidth : integer := 8;
mem_size : integer := 256
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
addr2 : in std_logic_vector(awidth-1 downto 0);
ce2 : in std_logic;
q2 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of Loop_loop_height_dEe_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
signal addr2_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem0 : mem_array := (
0 to 73=> "00000000", 74 to 91=> "00000001", 92 to 101=> "00000010", 102 to 108=> "00000011",
109 to 113=> "00000100", 114 to 118=> "00000101", 119 to 122=> "00000110", 123 to 125=> "00000111",
126 to 129=> "00001000", 130 to 132=> "00001001", 133 to 134=> "00001010", 135 to 137=> "00001011",
138 to 139=> "00001100", 140 to 141=> "00001101", 142 to 143=> "00001110", 144 to 145=> "00001111",
146 to 147=> "00010000", 148 to 149=> "00010001", 150 => "00010010", 151 to 152=> "00010011",
153 to 154=> "00010100", 155 => "00010101", 156 => "00010110", 157 to 158=> "00010111",
159 => "00011000", 160 => "00011001", 161 to 162=> "00011010", 163 => "00011011",
164 => "00011100", 165 => "00011101", 166 => "00011110", 167 => "00011111",
168 => "00100000", 169 => "00100001", 170 => "00100010", 171 => "00100011",
172 => "00100100", 173 => "00100101", 174 => "00100110", 175 => "00100111",
176 => "00101000", 177 => "00101001", 178 => "00101010", 179 => "00101011",
180 => "00101101", 181 => "00101110", 182 => "00101111", 183 => "00110001",
184 => "00110010", 185 => "00110011", 186 => "00110101", 187 => "00110110",
188 => "00111000", 189 => "00111001", 190 => "00111011", 191 => "00111100",
192 => "00111110", 193 => "00111111", 194 => "01000001", 195 => "01000011",
196 => "01000100", 197 => "01000110", 198 => "01001000", 199 => "01001010",
200 => "01001100", 201 => "01001110", 202 => "01010000", 203 => "01010010",
204 => "01010100", 205 => "01010110", 206 => "01011000", 207 => "01011010",
208 => "01011100", 209 => "01011110", 210 => "01100001", 211 => "01100011",
212 => "01100101", 213 => "01101000", 214 => "01101010", 215 => "01101101",
216 => "01101111", 217 => "01110010", 218 => "01110100", 219 => "01110111",
220 => "01111010", 221 => "01111101", 222 => "10000000", 223 => "10000010",
224 => "10000101", 225 => "10001000", 226 => "10001011", 227 => "10001111",
228 => "10010010", 229 => "10010101", 230 => "10011000", 231 => "10011100",
232 => "10011111", 233 => "10100010", 234 => "10100110", 235 => "10101010",
236 => "10101101", 237 => "10110001", 238 => "10110101", 239 => "10111000",
240 => "10111100", 241 => "11000000", 242 => "11000100", 243 => "11001000",
244 => "11001101", 245 => "11010001", 246 => "11010101", 247 => "11011001",
248 => "11011110", 249 => "11100010", 250 => "11100111", 251 => "11101100",
252 => "11110000", 253 => "11110101", 254 => "11111010", 255 => "11111111" );
signal mem1 : mem_array := (
0 to 73=> "00000000", 74 to 91=> "00000001", 92 to 101=> "00000010", 102 to 108=> "00000011",
109 to 113=> "00000100", 114 to 118=> "00000101", 119 to 122=> "00000110", 123 to 125=> "00000111",
126 to 129=> "00001000", 130 to 132=> "00001001", 133 to 134=> "00001010", 135 to 137=> "00001011",
138 to 139=> "00001100", 140 to 141=> "00001101", 142 to 143=> "00001110", 144 to 145=> "00001111",
146 to 147=> "00010000", 148 to 149=> "00010001", 150 => "00010010", 151 to 152=> "00010011",
153 to 154=> "00010100", 155 => "00010101", 156 => "00010110", 157 to 158=> "00010111",
159 => "00011000", 160 => "00011001", 161 to 162=> "00011010", 163 => "00011011",
164 => "00011100", 165 => "00011101", 166 => "00011110", 167 => "00011111",
168 => "00100000", 169 => "00100001", 170 => "00100010", 171 => "00100011",
172 => "00100100", 173 => "00100101", 174 => "00100110", 175 => "00100111",
176 => "00101000", 177 => "00101001", 178 => "00101010", 179 => "00101011",
180 => "00101101", 181 => "00101110", 182 => "00101111", 183 => "00110001",
184 => "00110010", 185 => "00110011", 186 => "00110101", 187 => "00110110",
188 => "00111000", 189 => "00111001", 190 => "00111011", 191 => "00111100",
192 => "00111110", 193 => "00111111", 194 => "01000001", 195 => "01000011",
196 => "01000100", 197 => "01000110", 198 => "01001000", 199 => "01001010",
200 => "01001100", 201 => "01001110", 202 => "01010000", 203 => "01010010",
204 => "01010100", 205 => "01010110", 206 => "01011000", 207 => "01011010",
208 => "01011100", 209 => "01011110", 210 => "01100001", 211 => "01100011",
212 => "01100101", 213 => "01101000", 214 => "01101010", 215 => "01101101",
216 => "01101111", 217 => "01110010", 218 => "01110100", 219 => "01110111",
220 => "01111010", 221 => "01111101", 222 => "10000000", 223 => "10000010",
224 => "10000101", 225 => "10001000", 226 => "10001011", 227 => "10001111",
228 => "10010010", 229 => "10010101", 230 => "10011000", 231 => "10011100",
232 => "10011111", 233 => "10100010", 234 => "10100110", 235 => "10101010",
236 => "10101101", 237 => "10110001", 238 => "10110101", 239 => "10111000",
240 => "10111100", 241 => "11000000", 242 => "11000100", 243 => "11001000",
244 => "11001101", 245 => "11010001", 246 => "11010101", 247 => "11011001",
248 => "11011110", 249 => "11100010", 250 => "11100111", 251 => "11101100",
252 => "11110000", 253 => "11110101", 254 => "11111010", 255 => "11111111" );
attribute syn_rom_style : string;
attribute syn_rom_style of mem0 : signal is "block_rom";
attribute syn_rom_style of mem1 : signal is "block_rom";
attribute ROM_STYLE : string;
attribute ROM_STYLE of mem0 : signal is "block";
attribute ROM_STYLE of mem1 : signal is "block";
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
memory_access_guard_2: process (addr2)
begin
addr2_tmp <= addr2;
--synthesis translate_off
if (CONV_INTEGER(addr2) > mem_size-1) then
addr2_tmp <= (others => '0');
else
addr2_tmp <= addr2;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem0(CONV_INTEGER(addr0_tmp));
end if;
if (ce1 = '1') then
q1 <= mem0(CONV_INTEGER(addr1_tmp));
end if;
if (ce2 = '1') then
q2 <= mem1(CONV_INTEGER(addr2_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity Loop_loop_height_dEe is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 256;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address2 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of Loop_loop_height_dEe is
component Loop_loop_height_dEe_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR;
addr2 : IN STD_LOGIC_VECTOR;
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR);
end component;
begin
Loop_loop_height_dEe_rom_U : component Loop_loop_height_dEe_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1,
addr2 => address2,
ce2 => ce2,
q2 => q2);
end architecture;
|
mit
|
3159016be041ed676813515a95eeb430
| 0.554525 | 3.616101 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodScopeController/src/ResetBridge.vhd
| 2 | 5,822 |
-------------------------------------------------------------------------------
--
-- File: ResetBridge.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
-- Last modification date: 05 October 2022
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a reset-bridge. It takes a reset signal asynchronous to the
-- target clock domain (OutClk) and provides a safe asynchronous or synchronous
-- reset for the OutClk domain (aoRst). The signal aoRst is asserted immediately
-- as aRst arrives, but is de-asserted synchronously with the OutClk rising
-- edge. This means it can be used to safely reset any FF in the OutClk domain,
-- respecting recovery time specs for FFs.
-- The additional output register does not have placement and overly
-- restrictive delay constraints, so that the tools can freely replicate it,
-- if needed.
-- Constraints:
-- # Replace <InstResetBridge> with path to ResetBridge instance, keep rest unchanged
-- # Begin scope to ResetBridge instance
-- current_instance [get_cells <InstResetBridge>]
-- # Reset input to the synchronizer must be ignored for timing analysis
-- set_false_path -through [get_ports -scoped_to_current_instance aRst]
-- # Constrain internal synchronizer paths to half-period, which is expected to be easily met with ASYNC_REG=true
-- set ClkPeriod [get_property PERIOD [get_clocks -of_objects [get_ports -scoped_to_current_instance OutClk]]]
-- set_max_delay -from [get_cells OutputFF*.SyncAsyncx/oSyncStages_reg[*]] -to [get_cells OutputFF*.SyncAsyncx/oSyncStages_reg[*]] [expr $ClkPeriod/2]
-- current_instance -quiet
-- # End scope to ResetBridge instance
--
-- Changelog:
-- 2020-Dec-14: Changed file name to ResetBridge
-- 2022-Oct-05: Replaced KEEP with keep_hierarchy. Added the possibility to
-- specify the number of output synchronization stages. Added the
-- possibility to specify an output FF, for replication purposes.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ResetBridge is
Generic (
kPolarity : std_logic := '1';
kStages : natural := 2;
kOutputFF : boolean := false); -- additional output FF for replication
Port (
aRst : in STD_LOGIC; -- asynchronous reset; active-high, if kPolarity=1
OutClk : in STD_LOGIC;
aoRst : out STD_LOGIC);
attribute keep_hierarchy : string;
attribute keep_hierarchy of ResetBridge : entity is "yes";
end ResetBridge;
architecture Behavioral of ResetBridge is
signal aRst_int, aoRst_int : std_logic;
begin
aRst_int <= kPolarity xnor aRst; --SyncAsync uses active-high reset
OutputFF_Yes: if kOutputFF generate
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => kStages) --use double FF synchronizer
port map (
aoReset => aRst_int,
aIn => '0',
OutClk => OutClk,
oOut => aoRst_int);
-- Output FF that can be replicated by the tools, if needed
OutputFF: process (OutClk, aoRst_int)
begin
if (aoRst_int = '1') then
aoRst <= kPolarity;
elsif Rising_Edge(OutClk) then
aoRst <= not kPolarity;
end if;
end process;
end generate OutputFF_Yes;
OutputFF_No: if not kOutputFF generate
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => kPolarity,
kStages => kStages) --use double FF synchronizer
port map (
aoReset => aRst_int,
aIn => not kPolarity,
OutClk => OutClk,
oOut => aoRst);
end generate OutputFF_No;
end Behavioral;
|
mit
|
af0d65a45d44e1a3bb3f6434de8cc9a0
| 0.685847 | 4.577044 | false | false | false | false |
Digilent/vivado-library
|
ip/AXI_DPTI_1.0/src/AXI_S_To_DPTI_Converter.vhd
| 1 | 9,941 |
------------------------------------------------------------------------------
--
-- File: AXI_S_to_DPTI_converter.vhd
-- Author: Sergiu Arpadi
-- Original Project: AXI DPTI
-- Date: 8 June 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module reads data from the AXI STREAM interface and sends it to the DPTI
-- interface. It will require a 32 bit TDATA bus, 4 bit TKEEP, TVALID and TLAST
-- as inputs and it will output the TREADY signal. It uses the DPTI clock of 60 MHz
-- to perform all the operations and it will use the maximum bandwidth of the DPTI
-- interface which is 480 mbps as long as valid data is received from the AXI STREAM
-- interface. In order to achieve this, FOR loops have been used which will generate
-- combinational logic that allows the simultaneous verification of all of the 4 TKEEP
-- bits received. Along with the DPTI clock, the module also reads the PROG_TXEN
-- signal and it will generate the PROG_D bus and PROG_WRN signal. In order to control
-- the module, two AXI Lite registers are used, one for direction/control and one for
-- the lenght of the transfer, which are synchronized in the top module.
-- The module also uses a reset signal aResetTx which is generated in the top module.
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.std_logic_arith.all;
entity AXI_S_to_DPTI_converter is
Port (
-- clock, reset and DPTI signals
pResetnTx : in std_logic;
PROG_CLK : in std_logic;
pTxe : in std_logic;
pWr : out std_logic;
pDataOut : out std_logic_vector (7 downto 0);
-- AXI Stream signals
pOutTready : out std_logic;
pInTdata : in std_logic_vector (31 downto 0);
pInTvalid : in std_logic;
pInTlast : in std_logic;
pInTkeep : in std_logic_vector (3 downto 0);
-- AXI Lite registers
pAXI_L_Length : in std_logic_vector (31 downto 0);
pOvalidLength : in std_logic;
pAXI_L_Control : in std_logic_vector (31 downto 0);
pOvalidControl : in std_logic;
pTxLengthEmpty : out std_logic
);
end AXI_S_to_DPTI_converter;
architecture Behavioral of AXI_S_to_DPTI_converter is
--------------------------------------------------------------------------------------------------------------------------
signal pTxEnDir : std_logic := '0';
signal pLengthTxCnt : std_logic_vector (22 downto 0) := (others => '0');
signal Index : integer range 0 to 3;
signal pCtlOutTready : std_logic := '0';
signal pCtlWr : std_logic := '1';
signal pTransferInvalidFlag : std_logic := '1';
signal pAuxTdata : std_logic_vector(31 downto 0);
signal pAuxTkeep : std_logic_vector(3 downto 0) := (others => '0');
--------------------------------------------------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------------------------------------------------
pWr <= pCtlWr;
pOutTready <= pCtlOutTready;
--------------------------------------------------------------------------------------------------------------------------
pTxLengthEmpty <= '1' when pLengthTxCnt = 0 else '0'; -- we check to see if we are currently doing a tranfer. this will be a part of the AXI Lite status register
-- Generating TREADY signal which will request data from the AXI STREAM interface
pCtlOutTready <= '1' when (pAuxTkeep = "0001" or pAuxTkeep = "0010" or pAuxTkeep = "0100" or pAuxTkeep = "1000" or (pAuxTkeep = "0000" )) and pTxe = '0' and pLengthTxCnt > 0 else '0';
-- new data will be requested when we have at most one valid data byte in the current TDATA bus. other conditions are that a transfer must be in progress and the DPTI interface can accept more data
pTransferInvalidFlag <= '1' when pTxe = '1' and pCtlWr = '0' else '0'; -- detecting if a transfer has failed because the FT_TXE signal from FTDI was '1'
--------------------------------------------------------------------------------------------------------------------------
generate_WR: process (PROG_CLK, pLengthTxCnt, pResetnTx) -- PROG_WRN is generated
begin
if pResetnTx = '0' then
pCtlWr <= '1';
else if rising_edge (PROG_CLK) then
if pAuxTkeep /= 0 and pLengthTxCnt > 0 then -- check if the transfer is not finnished and there is at least one valid data byte
pCtlWr <= '0'; -- when the signal is 0 then the byte currently on the PROG_D bus is valid
else -- if valid data is not available or the transfer is completed
pCtlWr <= '1'; -- PROG_WRN is '1'
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------------------
read_Tkeep_and_Tdata: process (PROG_CLK, pResetnTx)
variable aux_tkindex : integer;
begin
if pResetnTx = '0' then
aux_tkindex := 0;
pAuxTkeep <= (others => '0');
pAuxTdata <= (others => '0');
else if rising_edge(PROG_CLK)then
if pLengthTxCnt > 0 and pTxe = '0' and pTxEnDir = '1' then -- check to see if a transfer is in progress
if (pAuxTkeep = 0 or pAuxTkeep = 1 or pAuxTkeep = 2 or pAuxTkeep = 4 or pAuxTkeep = 8) and pInTvalid = '1' then -- check if the current set of TDATA and TKEEP contains at most one valid byte of data
pAuxTkeep <= pInTkeep; --new tkeep is read
pAuxTdata <= pInTdata; --new data is read
-- TDATA and TKEEP are used in the "generate_pDataOut" process below
else -- if more than one valid bytes exist
for Index in 3 downto 0 loop -- we use a FOR loop to check all of the bytes simultaneously
if pAuxTkeep (Index) = '1' then -- each valid byte is identified by checking TKEEP
aux_tkindex := Index;
end if;
end loop;
pAuxTkeep(aux_tkindex) <= '0'; --reset one bit at a time after sending the corresponding valid byte to the DPTI interface
end if;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------------------
generate_pDataOut: process (PROG_CLK, pResetnTx)
begin
if pResetnTx = '0' then
pDataOut <= (others => '0');
pLengthTxCnt <= (others=>'0');
else if rising_edge(PROG_CLK) then
if pOvalidControl = '1' and pLengthTxCnt = 0 then -- the control bit (and the direction) can only be changed when the module is idle
pTxEnDir <= pAXI_L_Control(0); -- Reading control byte from AXI LITE register. Bit (0) sets the transfer's direction.
end if;
if pOvalidLength = '1' and pTxEnDir = '1' then -- checking if the module was enabled and if valid value is present in register
pLengthTxCnt (22 downto 0) <= pAXI_L_Length(22 downto 0); -- LENGTH register is read
end if;
if pLengthTxCnt > 0 and pTxe = '0' and pTxEnDir = '1' then -- conditions for starting transfer
for Index in 3 downto 0 loop -- the FOR loop allows us to check all of the bytes simultaneously
if pAuxTkeep (Index) = '1' then -- we identify the valid byte's position
pDataOut(7 downto 0) <= pAuxTdata((8 * (Index + 1)) -1 downto (8 * (Index))); -- the valid byte is extracted and sent to the DPTI interface
pLengthTxCnt <= pLengthTxCnt - '1'; -- since one valid byte was transferred, length is decremented
end if;
end loop;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------------------
end Behavioral;
|
mit
|
edc9f0d74b2e7bbea7f1fc5689f396b8
| 0.577004 | 4.610853 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
comparator/com/truth4x5.vhd
| 1 | 933 |
package TRUTH4x5 is
constant NUM_OUTPUTS: INTEGER:=5;
constant NUM_INPUTS: INTEGER:=4;
constant NUM_ROWS: INTEGER:= 2 ** NUM_INPUTS;
type WORD is array(NUM_OUTPUTS-1 downto 0) of BIT;
type ADDR is array(NUM_INPUTS-1 downto 0) of BIT;
type MEM is array (0 to NUM_ROWS-1) of WORD;
constant TRUTH: MEM :=
("11100", "01001", "01001", "01001",
"10010", "11100", "01001", "01001",
"10010", "10010", "11100", "01001",
"10010", "10010", "10010", "11100");
function INTVAL(VAL:ADDR) return INTEGER;
end TRUTH4x5;
package body TRUTH4x5 is
function INTVAL(VAL: ADDR) return INTEGER is
variable SUM: INTEGER:=0;
begin
for N in VAL'LOW to VAL'HIGH loop
if VAL(N) = '1' then
SUM := SUM + (2 ** N);
end if;
end loop;
return SUM;
end INTVAL;
end TRUTH4x5;
-- Description of COM using table lookup.
|
mit
|
db0b44dc887f0aca79afb9bfaaa273e9
| 0.584137 | 3.468401 | false | false | false | false |
Digilent/vivado-library
|
ip/MIPI_CSI_2_RX/hdl/LLP.vhd
| 1 | 23,772 |
-------------------------------------------------------------------------------
--
-- File: LLP.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI CSI-2 Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DebugLib;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity LLP is
Generic(
kMaxLaneCount : natural := 4;
--PPI
kLaneCount : natural range 1 to 4 := 2; --[1,2,4];
kTargetDT : string := "RAW10"
);
Port (
SAxisClk : in STD_LOGIC;
--Slave AXI-Stream
sAxisTdata : in std_logic_vector(8 * kMaxLaneCount - 1 downto 0);
sAxisTkeep : in std_logic_vector(kMaxLaneCount - 1 downto 0);
sAxisTvalid : in std_logic;
sAxisTready : out std_logic;
sAxisTlast : in std_logic;
MAxisClk : in std_logic;
--Master AXI-Stream
mAxisTdata : out std_logic_vector(40 - 1 downto 0);
mAxisTvalid : out std_logic;
mAxisTready : in std_logic;
mAxisTlast : out std_logic;
mAxisTuser : out std_logic_vector(0 downto 0);
sOverflow : out std_logic;
aRst : in std_logic; -- global asynchronous reset; synchronized internally to both clock domains
dbgLLP : out DebugLib.DebugLLP_t
);
end LLP;
architecture Behavioral of LLP is
COMPONENT cdc_fifo
PORT (
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT line_buffer
PORT (
s_axis_aresetn : IN STD_LOGIC;
s_axis_aclk : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(39 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
subtype data_type_t is std_logic_vector(5 downto 0);
constant kDTFrameStart : data_type_t := "000000";
constant kDTFrameEnd : data_type_t := "000001";
constant kDTLineStart : data_type_t := "000010";
constant kDTLineEnd : data_type_t := "000011";
constant kDT_RAW10 : data_type_t := "101011";
constant kDT_RGB565 : data_type_t := "100010";
signal kTargetDTInt : data_type_t;
signal mRst, sRst, sFIFO_Rstn : std_logic;
signal mIsHeader : std_logic;
signal mECC_Ready, mECC_Valid, mECC_Error, mECC_En: std_logic;
signal mECC_HeaderOut : std_logic_vector(31 downto 0);
signal mWordCount : unsigned(15 downto 0);
signal mDataType : std_logic_vector(5 downto 0);
signal mCRC_Rst, mCRC_En : std_logic;
signal mCRC_Out, mCRC_Sent : std_logic_vector(15 downto 0);
signal sAxisTreadyInt : std_logic;
signal mFIFO_Tdata : std_logic_vector(8 * kMaxLaneCount - 1 downto 0);
signal mFIFO_Tlast, mFIFO_Tvalid, mFIFO_Tready : std_logic;
signal mFIFO_Tkeep : std_logic_vector(kMaxLaneCount - 1 downto 0);
signal mPkt_Tdata : std_logic_vector(8 * kMaxLaneCount - 1 downto 0);
signal mPkt_Tlast, mPkt_Tvalid, mPkt_Tready : std_logic;
signal mPkt_Tkeep : std_logic_vector(kMaxLaneCount - 1 downto 0);
signal mReg_Tdata : std_logic_vector(8 * kMaxLaneCount - 1 downto 0);
signal mReg_Tlast, mReg_Tvalid, mReg_Tready : std_logic;
signal mReg_Tkeep : std_logic_vector(kMaxLaneCount - 1 downto 0);
signal mReg_Tuser : std_logic_vector(0 downto 0);
signal mFmt_Tdata : std_logic_vector(4 * 10 - 1 downto 0); -- Four RAW10 pixels per beat supported
signal mFmt_Tlast, mFmt_Tvalid, mFmt_Tready : std_logic;
signal mFmt_Tuser : std_logic_vector(0 downto 0);
signal mBuf_Tready : std_logic;
signal mFlush, mKeep : std_logic;
signal mVC : std_logic_vector(1 downto 0);
signal mDT : std_logic_vector(5 downto 0);
signal mWC : std_logic_vector(15 downto 0);
signal mECC : std_logic_vector(7 downto 0);
signal mBufDataCnt : std_logic_vector(31 downto 0);
begin
-- Data Flow
-- -> sAxis
-- FIFO -> mFIFO_*
-- ECC -> mECC_*
-- Header stripping, byte counting -> mPkt_*
-- Packet register -> mReg_*
-- CRC processing -> mCRC_Out
-- Video formatter -> mFmt_*
-- Line Buffer -> mAxis_*
assert (kMaxLaneCount = 4) report "LLP module only supports a maximum of four lanes" severity failure;
RAW10_DT: if (kTargetDT = "RAW10") generate
kTargetDTInt <= kDT_RAW10;
end generate;
-- Synchronize aRst into the MAxis domain
SyncMReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aRst,
OutClk => MAxisClk,
oRst => mRst);
-- Synchronize aRst into the SAxis domain
SyncSReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aRst,
OutClk => SAxisClk,
oRst => sRst);
sOverflow <= sAxisTvalid and not sAxisTreadyInt;
-- Gate sAxisTready because FIFO Generator below does not guarantee de-assertion
-- during reset
process(sFIFO_Rstn, SAxisClk)
constant kTreadyDelay : natural := 1;
variable delay : std_logic_vector(kTreadyDelay downto 0);
begin
sAxisTready <= delay(delay'high);
if (sFIFO_Rstn = '0') then
delay := (others => '0');
elsif Rising_Edge(SAxisClk) then
delay := delay(delay'high - 1) & sAxisTreadyInt;
end if;
end process;
-- This FIFO provides buffering for data from lane merge before header decoding and other
-- processing can happen.
-- It also separates the MIPI RxByteClkHS domain from the internal video pipeline clock
-- This buffer must always be able to accept data on the slave port, since the MIPI stream cannot
-- be stopped. If overflow occurs, error is signaled.
-- Underflow is not an error condition.
-- PG057: The value of s_axis_tready (...) is 1 when s_aresetn is 0.
sFIFO_Rstn <= not sRst;
DataFIFO: CDC_fifo
PORT MAP (
m_aclk => MAxisClk,
s_aclk => SAxisClk,
s_aresetn => sFIFO_Rstn, --asynchronous reset; initial reset has to be provided
s_axis_tvalid => sAxisTvalid,
s_axis_tready => sAxisTreadyInt, -- not de-asserted when aresetn = 0; need to gate it before sending upstream
s_axis_tdata => sAxisTdata,
s_axis_tkeep => sAxisTkeep,
s_axis_tlast => sAxisTlast,
m_axis_tvalid => mFIFO_Tvalid,
m_axis_tready => mFIFO_Tready,
m_axis_tdata => mFIFO_Tdata,
m_axis_tkeep => mFIFO_Tkeep,
m_axis_tlast => mFIFO_Tlast
);
-- Since the header is 32-bit wide, the first word in a stream is the header
PacketFlag: process(MAxisClk)
begin
if Rising_Edge(MAxisClk) then
if (mRst = '1') then
mIsHeader <= '1';
else
if (mFIFO_Tvalid = '1' and mFIFO_Tready = '1') then
if (mFIFO_Tlast = '1') then
mIsHeader <= '1';
else
mIsHeader <= '0';
end if;
end if;
end if;
end if;
end process;
mFIFO_Tready <= '1' when (mECC_En = '1' and mECC_Ready = '1') or -- pop header into ECC block
(mFlush = '1' and mKeep = '0') or -- flush unneeded data
(mKeep = '1' and mPkt_Tready = '1') -- pop data when accepted downstream
else '0';
mECC_En <= mIsHeader and mFIFO_Tvalid;
-- Send header to processing while popping it from the FIFO
-- in 3 cycles we will get a corrected one back
ECCx: entity work.ECC
Port map (
StreamClk => MAxisClk,
sHeaderIn => mFIFO_Tdata,
sCE => mECC_En,
sReady => mECC_Ready,
sHeaderOut => mECC_HeaderOut,
sValid => mECC_Valid,
sError => mECC_Error,
sRst => mRst
);
--Waiting on Santa to bring us VHDL-2008 support
--(mECC, mWC, mVC, mDT) <= mECC_HeaderOut;
mECC <= mECC_HeaderOut(31 downto 24);
mWC <= mECC_HeaderOut(23 downto 8);
mVC <= mECC_HeaderOut(7 downto 6);
mDT <= mECC_HeaderOut(5 downto 0);
-- Short packet processing, assert Tuser for Start-of-Frame
FrameStart: process(MAxisClk)
begin
if Rising_Edge(MAxisClk) then
if (mRst = '1') then
mReg_Tuser(0) <= '0';
elsif (mECC_Valid = '1' and mDT = kDTFrameStart) then
mReg_Tuser(0) <= '1';
elsif (mReg_Tvalid = '1' and mReg_Tready = '1') then --first word transmitted
mReg_Tuser(0) <= '0';
end if;
end if;
end process;
-- Once ECC check result comes back, start emptying the FIFO until Tlast is observed
-- Flush happens regardless of the validness of the header/packet.
FlushFIFO: process(MAxisClk)
begin
if Rising_Edge(MAxisClk) then
if (mRst = '1') then
mFlush <= '0';
else
if (mFIFO_Tlast = '1' and mFIFO_Tvalid = '1' and mFIFO_Tready = '1') then -- last byte of packet read
mFlush <= '0';
elsif ((mECC_Valid = '1' or mECC_Error = '1') and mIsHeader = '0') then --if there are extra bytes after the header
mFlush <= '1';
end if;
end if;
end if;
end process;
-- If the header checks out and we have a recognized data type, forward data
-- Also register the Data Type from the header
KeepData: process(MAxisClk)
begin
if Rising_Edge(MAxisClk) then
if (mRst = '1') then
mKeep <= '0';
mDataType <= (others => '0');
else
if (mECC_Valid = '1') then
if (mDT = kTargetDTInt) then -- supported long packet data types
mKeep <= '1';
mDataType <= mDT;
else --unsupported data type or short packet
mKeep <= '0';
end if;
elsif (mECC_Error = '1') then --uncorrectable header error
mKeep <= '0';
elsif (mPkt_Tlast = '1' and mPkt_Tvalid = '1' and mPkt_Tready = '1') then -- when the packet ends according to word count
mKeep <= '0';
end if;
end if;
end if;
end process;
-- Once the ECC check is complete, register the Word Count from the header
-- Count down the number of bytes forwarded
WordCountFromHeader: process (MAxisClk)
begin
if Rising_Edge(MAxisClk) then
if (mRst = '1') then
mWordCount <= to_unsigned(0, 16);
elsif (mECC_Valid = '1') then
if (not std_match(mDT, "00----")) then -- not short packet == long packet
mWordCount <= unsigned(mWC);
end if;
elsif (mPkt_Tvalid = '1' and mPkt_Tready = '1') then -- count down the bytes forwarded
if std_match(mFIFO_Tkeep, "1111") then
mWordCount <= mWordCount - 4;
elsif std_match(mFIFO_Tkeep, "0111") then
mWordCount <= mWordCount - 3;
elsif std_match(mFIFO_Tkeep, "-011") then
mWordCount <= mWordCount - 2;
elsif std_match(mFIFO_Tkeep, "--01") then
mWordCount <= mWordCount - 1;
end if;
end if;
end if;
end process;
-- Generate AXI4-Stream for recognized data packet after counting data bytes, stripping header and CRC.
mPkt_Tvalid <= mFIFO_Tvalid and mKeep;
mPkt_Tready <= mReg_Tready;
mPkt_Tdata <= mFIFO_Tdata;
process(mWordCount, mFIFO_Tkeep, mFIFO_Tlast)
begin
if mFIFO_Tlast = '1' then -- if data count incorrect and input ends sooner, end packet too
mPkt_Tlast <= '1';
mPkt_Tkeep <= mFIFO_Tkeep;
elsif mWordCount = 1 then
mPkt_Tlast <= '1';
mPkt_Tkeep <= "0001";
elsif mWordCount = 2 then
mPkt_Tlast <= '1';
mPkt_Tkeep <= "0011";
elsif mWordCount = 3 then
mPkt_Tlast <= '1';
mPkt_Tkeep <= "0111";
elsif mWordCount = 4 then
mPkt_Tlast <= '1';
mPkt_Tkeep <= "1111";
else
mPkt_Tlast <= '0';
mPkt_Tkeep <= mFIFO_Tkeep;
end if;
end process;
-- Register packet data to improve timing
mReg_Tready <= mFmt_Tready;
PacketReg: process (MAxisClk)
begin
if Rising_Edge(MAxisClk) then
if (mRst = '1') then
mReg_Tvalid <= '0';
elsif (mReg_Tready = '1') then
if (mPkt_Tvalid = '1') then
mReg_Tlast <= mPkt_Tlast;
mReg_Tdata <= mPkt_Tdata;
mReg_Tkeep <= mPkt_Tkeep;
mReg_Tvalid <= '1';
else
mReg_Tvalid <= '0';
end if;
end if;
end if;
end process;
-- Register two bytes after the data packet ends, this will be the transmitted CRC
RegisterCRC: process(MAxisClk)
variable CRCRemains : natural;
begin
if Rising_Edge(MAxisClk) then
if (mCRC_Rst = '1') then
CRCRemains := 0;
elsif (CRCRemains /= 0 and mFIFO_Tvalid = '1') then -- we have CRC bytes left to read; set when last encountered
if (CRCRemains = 2) then
mCRC_Sent <= mFIFO_Tdata(15 downto 0);
elsif (CRCRemains = 1) then
mCRC_Sent(15 downto 8) <= mFIFO_Tdata(7 downto 0);
end if;
CRCRemains := 0;
elsif (mPkt_Tvalid = '1' and mPkt_Tready = '1' and mPkt_Tlast = '1') then --last valid data
if (mWordCount = kMaxLaneCount) then
CRCRemains := 2;
elsif (mWordCount = kMaxLaneCount - 1) then
CRCRemains := 1;
mCRC_Sent(7 downto 0) <= mFIFO_Tdata(kMaxLaneCount * 8 - 1 downto (kMaxLaneCount - 1) * 8);
elsif (mWordCount <= kMaxLaneCount - 2) then
CRCRemains := 0;
mCRC_Sent <= mFIFO_Tdata(kMaxLaneCount * 8 - 1 downto (kMaxLaneCount - 2) * 8);
end if;
end if;
end if;
end process;
-- Generate Reset signal for CRC module. It should be reset before every new data packet.
mCRC_Rst <= mIsHeader and mFIFO_Tready; -- when a new header is popped
-- Pipe data written to DataFIFO into CRC module for data integrity verification at the end
mCRC_En <= mReg_Tvalid and mFmt_Tready;
CRC16x: entity work.CRC16
generic map (kLaneCount => 4)
port map (
ByteClk => MAxisClk,
bData => mReg_Tdata,
bDataEnable => mCRC_En,
bKeep => mReg_Tkeep,
bCRC => mCRC_Out,
bRst => mCRC_Rst
);
--TODO do CRC compare for statistics
--CSI-2 RAW10 spec: The length of each packet must be a multiple of 4 pixels, 5 bytes
mFmt_Tready <= mBuf_Tready;
RAW10Formatter: process(MAxisClk)
constant kPixelWidth : natural := 10;
constant kNoPixels : natural := 4;
constant kNoBytes : natural := 5;
type pixels_t is array (natural range <>) of std_logic_vector(kPixelWidth downto 0);
variable pix_mux : pixels_t(0 to kNoPixels-1);
variable cnt : natural range 0 to kNoBytes-1 := 0;
begin
if Rising_Edge(MAxisClk) then
dbgLLP.mFmt_cnt <= std_logic_vector(to_unsigned(cnt, 3));
if (mRst = '1') then
cnt := 0;
mFmt_Tvalid <= '0';
mFmt_Tuser <= "0";
elsif (mFmt_Tready = '1') then
mFmt_Tvalid <= mReg_Tvalid;
if (mFmt_Tvalid = '1') then --first pixels transmitted
mFmt_Tuser <= "0";
elsif (mReg_Tuser = "1") then
mFmt_Tuser <= "1";
end if;
if (mReg_Tvalid = '1') then
case (cnt) is
when 0 =>
pix_mux(3)(9 downto 2) := mReg_Tdata(31 downto 24);
pix_mux(2)(9 downto 2) := mReg_Tdata(23 downto 16);
pix_mux(1)(9 downto 2) := mReg_Tdata(15 downto 8);
pix_mux(0)(9 downto 2) := mReg_Tdata(7 downto 0);
mFmt_Tvalid <= '0';
mFmt_Tlast <= mReg_Tlast; -- if there is last here, error
when 1 =>
for i in 0 to 3 loop
mFmt_Tdata((i+1)*10-1 downto i*10+2) <= pix_mux(i)(9 downto 2); -- from previous word
end loop;
pix_mux(2)(9 downto 2) := mReg_Tdata(31 downto 24);
pix_mux(1)(9 downto 2) := mReg_Tdata(23 downto 16);
pix_mux(0)(9 downto 2) := mReg_Tdata(15 downto 8);
pix_mux(3)(1 downto 0) := mReg_Tdata(7 downto 6);
pix_mux(2)(1 downto 0) := mReg_Tdata(5 downto 4);
pix_mux(1)(1 downto 0) := mReg_Tdata(3 downto 2);
pix_mux(0)(1 downto 0) := mReg_Tdata(1 downto 0);
for i in 0 to 3 loop
mFmt_Tdata((i*10+1) downto i*10) <= pix_mux(i)(1 downto 0); -- from current word
end loop;
mFmt_Tvalid <= '1';
mFmt_Tlast <= mReg_Tlast;
when 2 =>
for i in 0 to 2 loop
mFmt_Tdata((i+1)*10-1 downto i*10+2) <= pix_mux(i)(9 downto 2); -- from previous word
end loop;
pix_mux(1)(9 downto 2) := mReg_Tdata(31 downto 24);
pix_mux(0)(9 downto 2) := mReg_Tdata(23 downto 16);
pix_mux(3)(1 downto 0) := mReg_Tdata(15 downto 14);
pix_mux(2)(1 downto 0) := mReg_Tdata(13 downto 12);
pix_mux(1)(1 downto 0) := mReg_Tdata(11 downto 10);
pix_mux(0)(1 downto 0) := mReg_Tdata(9 downto 8);
pix_mux(3)(9 downto 2) := mReg_Tdata(7 downto 0);
for i in 3 to 3 loop
mFmt_Tdata((i+1)*10-1 downto i*10+2) <= pix_mux(i)(9 downto 2); -- from current word
end loop;
for i in 0 to 3 loop
mFmt_Tdata((i*10+1) downto i*10) <= pix_mux(i)(1 downto 0); -- from current word
end loop;
mFmt_Tvalid <= '1';
mFmt_Tlast <= mReg_Tlast;
when 3 =>
for i in 0 to 1 loop
mFmt_Tdata((i+1)*10-1 downto i*10+2) <= pix_mux(i)(9 downto 2); -- from previous word
end loop;
pix_mux(0)(9 downto 2) := mReg_Tdata(31 downto 24);
pix_mux(3)(1 downto 0) := mReg_Tdata(23 downto 22);
pix_mux(2)(1 downto 0) := mReg_Tdata(21 downto 20);
pix_mux(1)(1 downto 0) := mReg_Tdata(19 downto 18);
pix_mux(0)(1 downto 0) := mReg_Tdata(17 downto 16);
pix_mux(3)(9 downto 2) := mReg_Tdata(15 downto 8);
pix_mux(2)(9 downto 2) := mReg_Tdata(7 downto 0);
for i in 2 to 3 loop
mFmt_Tdata((i+1)*10-1 downto i*10+2) <= pix_mux(i)(9 downto 2); -- from current word
end loop;
for i in 0 to 3 loop
mFmt_Tdata((i*10+1) downto i*10) <= pix_mux(i)(1 downto 0); -- from current word
end loop;
mFmt_Tvalid <= '1';
mFmt_Tlast <= mReg_Tlast;
when 4 =>
for i in 0 to 0 loop
mFmt_Tdata((i+1)*10-1 downto i*10+2) <= pix_mux(i)(9 downto 2); -- from previous word
end loop;
pix_mux(3)(1 downto 0) := mReg_Tdata(31 downto 30);
pix_mux(2)(1 downto 0) := mReg_Tdata(29 downto 28);
pix_mux(1)(1 downto 0) := mReg_Tdata(27 downto 26);
pix_mux(0)(1 downto 0) := mReg_Tdata(25 downto 24);
pix_mux(3)(9 downto 2) := mReg_Tdata(23 downto 16);
pix_mux(2)(9 downto 2) := mReg_Tdata(15 downto 8);
pix_mux(1)(9 downto 2) := mReg_Tdata(7 downto 0);
for i in 1 to 3 loop
mFmt_Tdata((i+1)*10-1 downto i*10+2) <= pix_mux(i)(9 downto 2); -- from current word
end loop;
for i in 0 to 3 loop
mFmt_Tdata((i*10+1) downto i*10) <= pix_mux(i)(1 downto 0); -- from current word
end loop;
mFmt_Tvalid <= '1';
mFmt_Tlast <= mReg_Tlast;
end case;
if (cnt < kNoBytes-1 and mReg_Tlast = '0') then
cnt := cnt + 1;
else
cnt := 0;
end if;
end if;
end if;
end if;
end process;
LineBufferFIFO: line_buffer
PORT MAP (
s_axis_aclk => MAxisClk,
s_axis_aresetn => not mRst, -- active-low synchronous reset
s_axis_tvalid => mFmt_Tvalid,
s_axis_tready => mBuf_Tready, -- de-asserted properly when aresetn = 0
s_axis_tdata => mFmt_Tdata,
s_axis_tlast => mFmt_Tlast,
s_axis_tuser => mFmt_Tuser,
m_axis_tvalid => mAxisTvalid, -- de-asserted properly when aresetn = 0
m_axis_tready => mAxisTready,
m_axis_tdata => mAxisTdata,
m_axis_tlast => mAxisTlast,
m_axis_tuser => mAxisTuser,
axis_wr_data_count => mBufDataCnt,
axis_rd_data_count => open
);
-- Debug signals
dbgLLP.rbRst <= sRst;
dbgLLP.rbFIFO_Rstn <= sFIFO_Rstn;
dbgLLP.mRst <= mRst;
dbgLLP.mFIFO_Tvalid <= mFIFO_Tvalid;
dbgLLP.mFIFO_Tready <= mFIFO_Tready;
dbgLLP.mFIFO_Tlast <= mFIFO_Tlast;
dbgLLP.mFIFO_Tdata <= mFIFO_Tdata;
dbgLLP.mFIFO_Tkeep <= mFIFO_Tkeep;
dbgLLP.mIsHeader <= mIsHeader;
dbgLLP.mECC_En <= mECC_En;
dbgLLP.mECC_Ready <= mECC_Ready;
dbgLLP.mECC_Valid <= mECC_Valid;
dbgLLP.mECC_Error <= mECC_Error;
dbgLLP.mWC <= mWC;
dbgLLP.mDT <= mDT;
dbgLLP.mFlush <= mFlush;
dbgLLP.mKeep <= mKeep;
dbgLLP.mWordCount <= std_logic_vector(mWordCount);
dbgLLP.mReg_Tvalid <= mReg_Tvalid;
dbgLLP.mReg_Tready <= mReg_Tready;
dbgLLP.mReg_Tlast <= mReg_Tlast;
dbgLLP.mReg_Tuser <= mReg_Tuser(0);
dbgLLP.mReg_Tdata <= mReg_Tdata;
dbgLLP.mReg_Tkeep <= mReg_Tkeep;
dbgLLP.mCRC_Sent <= mCRC_Sent;
dbgLLP.mCRC_En <= mCRC_En;
dbgLLP.mCRC_Rst <= mCRC_Rst;
dbgLLP.mCRC_Out <= mCRC_Out;
dbgLLP.mFmt_Tvalid <= mFmt_Tvalid;
dbgLLP.mFmt_Tready <= mFmt_Tready;
dbgLLP.mFmt_Tlast <= mFmt_Tlast;
dbgLLP.mFmt_Tuser <= mFmt_Tuser(0);
dbgLLP.mFmt_Tdata <= mFmt_Tdata;
dbgLLP.mBufDataCnt <= mBufDataCnt(10 downto 0);
end Behavioral;
|
mit
|
d5649c6644d22cbf7ffe817fd330412e
| 0.586488 | 3.751894 | false | false | false | false |
grafi-tt/Maizul
|
src/BlkRAM.vhd
| 1 | 1,997 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;
entity BlkRAM is
port (
clk : in std_logic;
addr : in blkram_addr;
inst : out instruction_t := (others => '0');
w : in blkram_write_t);
end entity;
architecture behavioral of BlkRAM is
type blkram_t is array (0 to 16383) of instruction_t;
signal RAM : blkram_t := (
0 => "01010000000000000011111111101011",
16363 => "00010100000111100000000000000000",
16364 => "00101000000111010000000000001100",
16365 => "01011100000000010000000000000010",
16366 => "01011100000000100000000000000010",
16367 => "00011100001000010000000000001000",
16368 => "01000000001000100000100000000101",
16369 => "01011100000000000000000000000100",
16370 => "00010100000000100000000000000000",
16371 => "00000000010000100000000000000001",
16372 => "01011100000000110000000000000010",
16373 => "00011100011000110000000000001000",
16374 => "01011100000001000000000000000010",
16375 => "01000000100000110001100000000101",
16376 => "00011100011000110000000000001000",
16377 => "01011100000001000000000000000010",
16378 => "01000000100000110001100000000101",
16379 => "00011100011000110000000000001000",
16380 => "01011100000001000000000000000010",
16381 => "01000000100000110001100000000101",
16382 => "01011100011000000000000000000101",
16383 => "10001000010000010011111111110011",
others => (others => '0'));
attribute ram_style : string;
attribute ram_style of RAM : signal is "block";
begin
blk : process(clk)
begin
if rising_edge(clk) then
inst <= RAM(to_integer(unsigned(addr(13 downto 0))));
if w.enable then
RAM(to_integer(unsigned(w.addr(13 downto 0)))) <= w.inst;
end if;
end if;
end process;
end behavioral;
|
bsd-2-clause
|
bafdeedb7d7034937c2cc541f5548921
| 0.649975 | 4.612009 | false | false | false | false |
Digilent/vivado-library
|
ip/MIPI_D_PHY_RX/tb/tb_MIPI_DPHY_Receiver.vhd
| 1 | 21,767 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04/26/2016 01:54:29 PM
-- Design Name:
-- Module Name: tb_MIPI_DPHY_Receiver - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_MIPI_DPHY_Receiver is
-- Port ( );
end tb_MIPI_DPHY_Receiver;
architecture Behavioral of tb_MIPI_DPHY_Receiver is
component MIPI_DPHY_Receiver is
generic (
-- Users to add parameters here
kVersionMajor : natural := 0; -- TCL-propagated from VLNV
kVersionMinor : natural := 0; -- TCL-propagated from VLNV
kNoOfDataLanes : natural range 1 to 2:= 2;
kGenerateMMCM : boolean := false;
kGenerateAXIL : boolean := false;
kAddDelayClk_ps : integer := 0;
kAddDelayData0_ps : integer := 0;
kAddDelayData1_ps : integer := 0;
kRefClkFreqHz : integer := 200_000_000; -- TCL-propagated
kDebug : boolean := true;
kLPFromLane0 : boolean := true;
kSharedLogic : boolean := true;
-- Parameters of Axi Slave Bus Interface S_AXI_LITE
C_S_AXI_LITE_DATA_WIDTH : integer := 32;
C_S_AXI_LITE_ADDR_WIDTH : integer := 4;
C_S_AXI_LITE_FREQ_HZ : integer := 100_000_000 -- TCL-propagated
);
port (
-- Users to add ports here
dphy_clk_hs_p : in std_logic;
dphy_clk_hs_n : in std_logic;
dphy_clk_lp_p : in std_logic;
dphy_clk_lp_n : in std_logic;
dphy_data_hs_p : in std_logic_vector(kNoOfDataLanes-1 downto 0);
dphy_data_hs_n : in std_logic_vector(kNoOfDataLanes-1 downto 0);
dphy_data_lp_p : in std_logic_vector(kNoOfDataLanes-1 downto 0);
dphy_data_lp_n : in std_logic_vector(kNoOfDataLanes-1 downto 0);
RefClk : in std_logic; --200MHz
aRst : in std_logic; --Only to be de-asserted when RefClk is valid
rDlyCtrlLockedIn : in std_logic; --if IDELAYCTRL instantiated externally, input its locked signal
rDlyCtrlLockedOut : out std_logic; --if IDELAYCTRL instantiated internally, output its locked signal
--PHY-Protocol Interface (PPI)
--Clock lane
RxDDRClkHS : out std_logic; --Receiver DDR Clock (may be used by the protocol)
aRxClkActiveHS : out std_logic; --Receiver Clock Active
aClkStopstate : out std_logic; --Lane is in Stop state
aClkEnable : in std_logic; --Enable Lane Module
aClkUlpsActiveNot : out std_logic; --ULP State (not) Active
aRxUlpsClkNot : out std_logic; --Receive Ultra-Low Power State on Clock Lane
aClkForceRxmode : in std_logic; --Force Lane Module Into Receive mode / Wait for Stop state
aClkErrControl : out std_logic; --Control Error
RxByteClkHS : out std_logic; --High-Speed Receive Byte Clock
--Data lane 0
aD0Stopstate : out std_logic; --Lane is in Stop state
aD0Enable : in std_logic; --Enable Lane Module
aD0UlpsActiveNot : out std_logic; --ULP State (not) Active
rbD0RxDataHS : out std_logic_vector(7 downto 0); --High-Speed Receive Data (least-significant first)
rbD0RxValidHS : out std_logic; --High-Speed Receive Data Valid
rbD0RxActiveHS : out std_logic; --High-Speed Reception Active
rbD0RxSyncHS : out std_logic; --Receiver Synchronization Observed (pulse)
rbD0ErrSotHS : out std_logic; --Start-of-Transmission (SoT) Error (pulse)
rbD0ErrSotSyncHS : out std_logic; --Start-of-Transmission (SoT) Synchronization Error (pulse)
aD0ForceRxmode : in std_logic; --Force Lane Module Into Receive mode / Wait for Stop state
D0RxClkEsc : out std_logic; --Escape mode Receive Clock (not periodic)
aD0RxDataEsc : out std_logic_vector(7 downto 0); --Escape mode Receive Data
aD0RxValidEsc : out std_logic; --Escape mode Receive Data Valid
aD0RxLpdtEsc : out std_logic; --Escape Low-Power Data Receive Mode
aD0RxUlpsEsc : out std_logic; --Escape Ultra-Low Power (Receive) mode
aD0RxTriggerEsc : out std_logic_vector(3 downto 0); --Escape mode Receive Trigger 3-0
aD0ErrEsc : out std_logic; --Escape Entry Error
aD0ErrControl : out std_logic; --Control Error
--Data lane 1
aD1Stopstate : out std_logic; --Lane is in Stop state
aD1Enable : in std_logic; --Enable Lane Module
aD1UlpsActiveNot : out std_logic; --ULP State (not) Active
rbD1RxDataHS : out std_logic_vector(7 downto 0); --High-Speed Receive Data (least-significant first)
rbD1RxValidHS : out std_logic; --High-Speed Receive Data Valid
rbD1RxActiveHS : out std_logic; --High-Speed Reception Active
rbD1RxSyncHS : out std_logic; --Receiver Synchronization Observed (pulse)
rbD1ErrSotHS : out std_logic; --Start-of-Transmission (SoT) Error (pulse)
rbD1ErrSotSyncHS : out std_logic; --Start-of-Transmission (SoT) Synchronization Error (pulse)
aD1ForceRxmode : in std_logic; --Force Lane Module Into Receive mode / Wait for Stop state
D1RxClkEsc : out std_logic; --Escape mode Receive Clock (not periodic)
aD1RxDataEsc : out std_logic_vector(7 downto 0); --Escape mode Receive Data
aD1RxValidEsc : out std_logic; --Escape mode Receive Data Valid
aD1RxLpdtEsc : out std_logic; --Escape Low-Power Data Receive Mode
aD1RxUlpsEsc : out std_logic; --Escape Ultra-Low Power (Receive) mode
aD1RxTriggerEsc : out std_logic_vector(3 downto 0); --Escape mode Receive Trigger 3-0
aD1ErrEsc : out std_logic; --Escape Entry Error
aD1ErrControl : out std_logic; --Control Error
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S_AXI_LITE
s_axi_lite_aclk : in std_logic;
s_axi_lite_aresetn : in std_logic;
s_axi_lite_awaddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_awprot : in std_logic_vector(2 downto 0);
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_wstrb : in std_logic_vector((C_S_AXI_LITE_DATA_WIDTH/8)-1 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_araddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_arprot : in std_logic_vector(2 downto 0);
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_rdata : out std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic
);
end component MIPI_DPHY_Receiver;
function max(l : time; r : time) return time is
begin
if (l > r) then
return l;
else
return r;
end if;
end function max;
constant kUI : time := 2 ns; --500Mbps
constant kNoOfDataLanes : natural := 2;
constant kRefClkPeriod : time := 5 ns;
constant kTRst : time := 1us;
constant kT_LPX : time := 50 ns;
constant kT_HS_PREPARE : time := 40 ns + 4*kUI;
constant kT_HS_ZERO : time := 100 ns + 6*kUI;
constant kT_HS_TRAIL : time := max(1*8*kUI, 60 ns + 1*4*kUI);
constant kT_HS_EXIT : time := 100 ns;
constant kTInit : time := 100 us;
constant kT_CLK_PREPARE : time := 38ns; --max 95ns
constant kT_CLK_ZERO : time := 300ns - kT_CLK_PREPARE;
constant kT_CLK_PRE : time := 8*kUI;
constant kT_CLK_POST : time := 60 ns + 52*kUI;
constant kT_CLK_TRAIL : time := 60ns;
constant kSyncSeq : std_logic_vector(7 downto 0) := "10111000"; --least significant bit
type mem is array (natural range <>) of std_logic_vector(15 downto 0);
constant data_stim : mem := (x"78CC", x"0F00",
x"00FF", x"0200", x"DCB9", x"72F3", x"D4BB", x"5AB8", x"75C8", x"7CC2", x"F881", x"DF05", x"00FF", x"0100",
x"00F0",
--dummy data
x"04fc", x"3729"
);
type vector1 is array (natural range <>) of std_logic;
type vector2 is array (natural range <>) of std_logic_vector(1 downto 0);
type vector4 is array (natural range <>) of std_logic_vector(3 downto 0);
type vector8 is array (natural range <>) of std_logic_vector(7 downto 0);
signal RefClk, aRst : std_logic := '0';
signal DPHY_DataHS : std_logic_vector(0 to kNoOfDataLanes-1);
signal DPHY_DataLP : vector2(0 to kNoOfDataLanes-1);
signal DPHY_ClkHS : std_logic;
signal DPHY_ClkLP : std_logic_vector(1 downto 0);
signal RxDDRClkHS, RxByteClkHS : std_logic;
signal aRxClkActiveHS, aClkStopstate, aClkUlpsActiveNot, aRxUlpsClkNot, aClkErrControl : std_logic;
signal aClkEnable, aClkForceRxmode : std_logic;
signal aDxStopstate, aDxForceRxmode, aDxEnable, aDxUlpsActiveNot, rbDxRxValidHS, rbDxRxActiveHS, rbDxRxSyncHS,
aDxErrEsc, aDxErrControl, rbDxErrSotHS, rbDxErrSotSyncHS : vector1(0 to kNoOfDataLanes-1);
signal rbDxRxDataHS : vector8(0 to kNoOfDataLanes-1);
signal fClockReady,fData0Ready, fData1Ready : boolean := false;
procedure Stopstate(dur : in time; signal LP : out std_logic_vector(1 downto 0); signal HS : out std_logic) is
begin
LP <= "11";
HS <= 'X';
wait for dur;
end procedure;
procedure HS_Rqst(signal LP : out std_logic_vector(1 downto 0)) is
begin
LP <= "01";
wait for kT_LPX;
end procedure;
procedure HS_Prepare(signal LP : out std_logic_vector(1 downto 0)) is
begin
LP <= "00";
wait for kT_HS_PREPARE;
end procedure;
procedure HS_Zero(signal HS : out std_logic) is
begin
HS <= '0';
wait for kT_HS_ZERO;
end procedure;
procedure HS_Send0(nbits : in natural; signal HS : out std_logic) is
begin
for i in 0 to nbits-1 loop
HS <= '0';
wait until DPHY_ClkHS'event;
end loop;
end procedure;
procedure HS_Send(byte : in std_logic_vector(7 downto 0); signal HS : out std_logic) is
begin
for i in 0 to 7 loop
wait for kUI / 2; --90deg phase difference between data and clock
HS <= byte(i);
wait until DPHY_ClkHS'event;
end loop;
end procedure;
procedure HS_Trail(signal HS : out std_logic) is
begin
wait for kUI / 2;
HS <= '0';
wait for kT_HS_TRAIL;
end procedure;
begin
--200MHz reference clock
RefClk <= not RefClk after kRefClkPeriod / 2;
--Startup reset
aRst <= '1', '0' after kTRst;
aClkEnable <= '0', '1' after kTRst;
aDxEnable(0) <= '0', '1' after kTRst;
aDxEnable(1) <= '0', '1' after kTRst;
aClkForceRxmode <= '0';
aDxForceRxmode(0) <= '0';
aDxForceRxmode(1) <= '0';
ClockStimulus: process
procedure HS_Prepare is
begin
DPHY_ClkLP <= "00";
wait for kT_CLK_PREPARE;
end procedure;
procedure HS_Zero is
begin
DPHY_ClkHS <= '0';
wait for kT_CLK_ZERO;
end procedure;
procedure HS_ClkPrePost(t : in time) is
variable start : time;
begin
start := now;
loop
DPHY_ClkHS <= not DPHY_ClkHS;
wait for kUI;
if (now - start > t) then
exit;
end if;
end loop;
end procedure;
procedure HS_Trail is
begin
wait for kUI / 2;
DPHY_ClkHS <= '0';
wait for kT_CLK_TRAIL;
end procedure;
begin
Stopstate(kTInit + 1 us, DPHY_ClkLP, DPHY_ClkHS);
HS_Rqst(DPHY_ClkLP);
HS_Prepare;
HS_Zero;
HS_ClkPrePost(kT_CLK_PRE);
fClockReady <= true;
loop
DPHY_ClkHS <= not DPHY_ClkHS;
wait for kUI;
if (fData0Ready and fData1Ready) then
exit;
end if;
end loop;
HS_ClkPrePost(kT_CLK_POST);
HS_Trail;
Stopstate(kT_HS_EXIT, DPHY_ClkLP, DPHY_ClkHS);
wait;
end process ClockStimulus;
DataStimulus0: process
variable seed1, seed2: positive; -- seed values for random generator
variable rand: real; -- random real-number value in range 0 to 1.0
variable range_of_rand : real := 10.0; -- the range of random values created will be 0 to +1000.
variable to_send : natural;
begin
Stopstate(kTInit + 1 us, DPHY_DataLP(0), DPHY_DataHS(0));
wait until fClockReady;
HS_Rqst(DPHY_DataLP(0));
HS_Prepare(DPHY_DataLP(0));
wait for kUI; -- this will test different word alignments
HS_Zero(DPHY_DataHS(0));
wait until Falling_Edge(DPHY_ClkHS);
HS_Send(kSyncSeq, DPHY_DataHS(0));
uniform(seed1, seed2, rand); -- generate random number
for j in data_stim'range loop
HS_Send(data_stim(j)(7 downto 0), DPHY_DataHS(0));
end loop;
-- for j in 0 to integer(rand*range_of_rand) loop
-- case (j) is
-- when 0 => HS_Send(x"DE",DPHY_DataHS(0));
-- when 1 => HS_Send(x"AD",DPHY_DataHS(0));
-- when 2 => HS_Send(x"BE",DPHY_DataHS(0));
-- when 3 => HS_Send(x"EF",DPHY_DataHS(0));
-- when others => HS_Send(std_logic_vector(to_unsigned(j-4,8)), DPHY_DataHS(0));
-- end case;
-- end loop;
HS_Trail(DPHY_DataHS(0));
Stopstate(kT_HS_EXIT, DPHY_DataLP(0), DPHY_DataHS(0));
HS_Rqst(DPHY_DataLP(0));
HS_Prepare(DPHY_DataLP(0));
wait for kUI; -- this will test different word alignments
HS_Zero(DPHY_DataHS(0));
wait until Falling_Edge(DPHY_ClkHS);
HS_Send(kSyncSeq, DPHY_DataHS(0));
uniform(seed1, seed2, rand); -- generate random number
for j in data_stim'range loop
HS_Send(data_stim(j)(7 downto 0), DPHY_DataHS(0));
end loop;
-- for j in 0 to integer(rand*range_of_rand) loop
-- case (j) is
-- when 0 => HS_Send(x"DE",DPHY_DataHS(0));
-- when 1 => HS_Send(x"AD",DPHY_DataHS(0));
-- when 2 => HS_Send(x"BE",DPHY_DataHS(0));
-- when 3 => HS_Send(x"EF",DPHY_DataHS(0));
-- when others => HS_Send(std_logic_vector(to_unsigned(j-4,8)), DPHY_DataHS(0));
-- end case;
-- end loop;
HS_Trail(DPHY_DataHS(0));
Stopstate(kT_HS_EXIT, DPHY_DataLP(0), DPHY_DataHS(0));
fData0Ready <= true;
wait;
end process DataStimulus0;
DataStimulus1: process
variable seed1, seed2: positive; -- seed values for random generator
variable rand: real; -- random real-number value in range 0 to 1.0
variable range_of_rand : real := 10.0; -- the range of random values created will be 0 to +1000.
variable to_send : natural;
begin
Stopstate(kTInit + 1 us, DPHY_DataLP(1), DPHY_DataHS(1));
wait until fClockReady;
HS_Rqst(DPHY_DataLP(1));
HS_Prepare(DPHY_DataLP(1));
wait for kUI; -- this will test different word alignments
HS_Zero(DPHY_DataHS(1));
wait until Falling_Edge(DPHY_ClkHS);
HS_Send(kSyncSeq, DPHY_DataHS(1));
uniform(seed1, seed2, rand); -- generate random number
for j in data_stim'range loop
HS_Send(data_stim(j)(15 downto 8), DPHY_DataHS(1));
end loop;
-- for j in 0 to integer(rand*range_of_rand) loop
-- case (j) is
-- when 0 => HS_Send(x"DE",DPHY_DataHS(1));
-- when 1 => HS_Send(x"AD",DPHY_DataHS(1));
-- when 2 => HS_Send(x"BE",DPHY_DataHS(1));
-- when 3 => HS_Send(x"EF",DPHY_DataHS(1));
-- when others => HS_Send(std_logic_vector(to_unsigned(j-4,8)), DPHY_DataHS(1));
-- end case;
-- end loop;
HS_Trail(DPHY_DataHS(1));
Stopstate(kT_HS_EXIT, DPHY_DataLP(1), DPHY_DataHS(1));
HS_Rqst(DPHY_DataLP(1));
HS_Prepare(DPHY_DataLP(1));
wait for kUI; -- this will test different word alignments
HS_Zero(DPHY_DataHS(1));
wait until Falling_Edge(DPHY_ClkHS);
HS_Send(kSyncSeq, DPHY_DataHS(1));
uniform(seed1, seed2, rand); -- generate random number
for j in data_stim'range loop
HS_Send(data_stim(j)(15 downto 8), DPHY_DataHS(1));
end loop;
-- for j in 0 to integer(rand*range_of_rand) loop
-- case (j) is
-- when 0 => HS_Send(x"DE",DPHY_DataHS(1));
-- when 1 => HS_Send(x"AD",DPHY_DataHS(1));
-- when 2 => HS_Send(x"BE",DPHY_DataHS(1));
-- when 3 => HS_Send(x"EF",DPHY_DataHS(1));
-- when others => HS_Send(std_logic_vector(to_unsigned(j-4,8)), DPHY_DataHS(1));
-- end case;
-- end loop;
HS_Trail(DPHY_DataHS(1));
Stopstate(kT_HS_EXIT, DPHY_DataLP(1), DPHY_DataHS(1));
fData1Ready <= true;
wait;
end process DataStimulus1;
DUT: MIPI_DPHY_Receiver
generic map (
kNoOfDataLanes => kNoOfDataLanes,
kDebug => false,
kSharedLogic => true,
kGenerateMMCM => false,
kAddDelayClk_ps => 0,
kAddDelayData0_ps => 0,
kAddDelayData1_ps => -500
)
port map (
dphy_clk_hs_p => DPHY_ClkHS,
dphy_clk_hs_n => not DPHY_ClkHS,
dphy_clk_lp_n => DPHY_ClkLP(0), --Dn is LP(0)
dphy_clk_lp_p => DPHY_ClkLP(1), --Dp is LP(1)
dphy_data_hs_p => DPHY_DataHS,
dphy_data_hs_n => not DPHY_DataHS,
dphy_data_lp_n => DPHY_DataLP(0)(0) & DPHY_DataLP(1)(0), --Dn is LP(0)
dphy_data_lp_p => DPHY_DataLP(0)(1) & DPHY_DataLP(1)(1), --Dp is LP(1)
RefClk => RefClk,
aRst => aRst,
rDlyCtrlLockedIn => '0', --unused if kSharedLogic=true
--PHY-Protocol Interface (PPI)
--Clock lane
RxDDRClkHS => RxDDRClkHS, --Receiver DDR Clock (may be used by the protocol)
aRxClkActiveHS => aRxClkActiveHS, --Receiver Clock Active
aClkStopstate => aClkStopstate, --Lane is in Stop state
aClkEnable => aClkEnable, --Enable Lane Module
aClkUlpsActiveNot => aClkUlpsActiveNot, --ULP State (not) Active
aRxUlpsClkNot => aRxUlpsClkNot, --Receive Ultra-Low Power State on Clock Lane
aClkForceRxmode => aClkForceRxmode, --Force Lane Module Into Receive mode / Wait for Stop state
aClkErrControl => aClkErrControl, --Control Error
RxByteClkHS => RxByteClkHS, --High-Speed Receive Byte Clock
--Data lane 0
aD0Stopstate => aDxStopstate(0), --Lane is in Stop state
aD0Enable => aDxEnable(0), --Enable Lane Module
aD0UlpsActiveNot => aDxUlpsActiveNot(0), --ULP State (not) Active
rbD0RxDataHS => rbDxRxDataHS(0), --High-Speed Receive Data (least-significant first)
rbD0RxValidHS => rbDxRxValidHS(0), --High-Speed Receive Data Valid
rbD0RxActiveHS => rbDxRxActiveHS(0), --High-Speed Reception Active
rbD0RxSyncHS => rbDxRxSyncHS(0), --Receiver Synchronization Observed (pulse)
rbD0ErrSotHS => rbDxErrSotHS(0), --Start-of-Transmission (SoT) Error (pulse)
rbD0ErrSotSyncHS => rbDxErrSotSyncHS(0), --Start-of-Transmission (SoT) Synchronization Error (pulse)
aD0ForceRxmode => aDxForceRxmode(0), --Force Lane Module Into Receive mode / Wait for Stop state
D0RxClkEsc => open, --Escape mode Receive Clock (not periodic)
aD0RxDataEsc => open, --Escape mode Receive Data
aD0RxValidEsc => open, --Escape mode Receive Data Valid
aD0RxLpdtEsc => open, --Escape Low-Power Data Receive Mode
aD0RxUlpsEsc => open, --Escape Ultra-Low Power (Receive) mode
aD0RxTriggerEsc => open, --Escape mode Receive Trigger 3-0
aD0ErrEsc => aDxErrEsc(0), --Escape Entry Error
aD0ErrControl => aDxErrControl(0), --Control Error
--Data lane 1
aD1Stopstate => aDxStopstate(1), --Lane is in Stop state
aD1Enable => aDxEnable(1), --Enable Lane Module
aD1UlpsActiveNot => aDxUlpsActiveNot(1), --ULP State (not) Active
rbD1RxDataHS => rbDxRxDataHS(1), --High-Speed Receive Data (least-significant first)
rbD1RxValidHS => rbDxRxValidHS(1), --High-Speed Receive Data Valid
rbD1RxActiveHS => rbDxRxActiveHS(1), --High-Speed Reception Active
rbD1RxSyncHS => rbDxRxSyncHS(1), --Receiver Synchronization Observed (pulse)
rbD1ErrSotHS => rbDxErrSotHS(1), --Start-of-Transmission (SoT) Error (pulse)
rbD1ErrSotSyncHS => rbDxErrSotSyncHS(1), --Start-of-Transmission (SoT) Synchronization Error (pulse)
aD1ForceRxmode => aDxForceRxmode(1), --Force Lane Module Into Receive mode / Wait for Stop state
D1RxClkEsc => open, --Escape mode Receive Clock (not periodic)
aD1RxDataEsc => open, --Escape mode Receive Data
aD1RxValidEsc => open, --Escape mode Receive Data Valid
aD1RxLpdtEsc => open, --Escape Low-Power Data Receive Mode
aD1RxUlpsEsc => open, --Escape Ultra-Low Power (Receive) mode
aD1RxTriggerEsc => open, --Escape mode Receive Trigger 3-0
aD1ErrEsc => aDxErrEsc(1), --Escape Entry Error
aD1ErrControl => aDxErrControl(1), --Control Error
-- -- Ports of Axi Slave Bus Interface S_AXI_LITE
s_axi_lite_aclk => '0',
s_axi_lite_aresetn => '0',
s_axi_lite_awaddr => (others => '0'),
s_axi_lite_awprot => (others => '0'),
s_axi_lite_awvalid => '0',
s_axi_lite_awready => open,
s_axi_lite_wdata => (others => '0'),
s_axi_lite_wstrb => (others => '0'),
s_axi_lite_wvalid => '0',
s_axi_lite_wready => open,
s_axi_lite_bresp => open,
s_axi_lite_bvalid => open,
s_axi_lite_bready => '0',
s_axi_lite_araddr => (others => '0'),
s_axi_lite_arprot => (others => '0'),
s_axi_lite_arvalid => '0',
s_axi_lite_arready => open,
s_axi_lite_rdata => open,
s_axi_lite_rresp => open,
s_axi_lite_rvalid => open,
s_axi_lite_rready => '0'
);
end Behavioral;
|
mit
|
3e2d01ef3a7070dde9c7d4de11ba344a
| 0.640051 | 3.446327 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_contrast_stretch_1_0/hdl/vhdl/start_for_Mat2AXIlbW.vhd
| 1 | 4,490 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity start_for_Mat2AXIlbW_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 6);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end start_for_Mat2AXIlbW_shiftReg;
architecture rtl of start_for_Mat2AXIlbW_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity start_for_Mat2AXIlbW is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 6);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of start_for_Mat2AXIlbW is
component start_for_Mat2AXIlbW_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 6);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_start_for_Mat2AXIlbW_shiftReg : start_for_Mat2AXIlbW_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
fcdf798a089d6ec55bce0ea002382c85
| 0.532962 | 3.549407 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodDigitizerController/tb/DataPathLatency.vhd
| 1 | 5,182 |
-------------------------------------------------------------------------------
--
-- File: DataPathLatency.vhd
-- Author: Tudor Gherman, Robert Bocos
-- Original Project: ZmodScopeController
-- Date: 20 May 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module emulates the DataPah.vhd module latency. This operation is
-- necessary to test the calibrated outputs in the tb_TestTop top level test bench
-- of the ZmodScopeController.
-- The FIFO data latency is specified (is it? not sure...) in
-- Xilinx pg057 Table 3-26 (Read Port Flags Update Latency Due to a Write Operation)
-- Latency = 1 wr_clk + (N + 4) rd_clk (+1 rd_clk)
-- The latency is defined in Fig. 3-40 of the same document. A register stage
-- corresponds to 0 cycles of latency. Thus, for a latency of 1 wr_clk, 2 register
-- stages have to be implemented in the write clock domain to emulate the FIFO write
-- latency. An extra cycle needs to be considered for the IDDR primitives in the data
-- path. Thus, a total of 3 register stages are added on the write clock domain to
-- emulate the DataPath module write domain latency.
-- Considering the same definition for the read clock domain latency, N+4+1
-- register stages are added on the read clock domain.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DataPathLatency is
Generic (
-- FIFO number of synchronization stages
kNumFIFO_Stages : integer := 0;
-- Channel data width
kDataWidth : integer := 14
);
Port (
ZmodDcoClk : in STD_LOGIC;
ZmodDcoClkDly : std_logic;
doDataIn : in STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
doChA_DataOut : out STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
doChB_DataOut : out STD_LOGIC_VECTOR (kDataWidth-1 downto 0)
);
end DataPathLatency;
architecture Behavioral of DataPathLatency is
signal doChA_DataIn, doChB_DataIn, doChB_DataInFalling : STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
type cDlyArray_t is array (kNumFIFO_Stages+4 downto 0) of std_logic_vector(kDataWidth-1 downto 0);
signal cChA_DataDly, cChB_DataDly : cDlyArray_t := (others => (others => '0'));
type dDlyArray_t is array (1 downto 0) of std_logic_vector(kDataWidth-1 downto 0);
signal dChA_DataDly, dChB_DataDly : dDlyArray_t := (others => (others => '0'));
begin
-- Emulate IDDR on ChA (sampled on rising edge)
ProcIDDR_ChA : process (ZmodDcoClkDly)
begin
if (rising_edge(ZmodDcoClkDly)) then
doChA_DataIn <= doDataIn;
end if;
end process;
-- Emulate IDDR on ChB (sampled on falling edge)
ProcIDDR_ChB_Falling : process (ZmodDcoClkDly)
begin
if (falling_edge(ZmodDcoClkDly)) then
doChB_DataInFalling <= doDataIn;
end if;
end process;
ProcIDDR_ChB_Rising : process (ZmodDcoClkDly)
begin
if (rising_edge(ZmodDcoClkDly)) then
doChB_DataIn <= doChB_DataInFalling;
end if;
end process;
--Emulate the D Flip-Flops which are the last stages of the DataPath module
ProcDelayDcoClkOut: process (ZmodDcoClk)
begin
if (rising_edge(ZmodDcoClk)) then
doChA_DataOut <= doChA_DataIn;
doChB_DataOut <= doChB_DataIn;
end if;
end process;
end Behavioral;
|
mit
|
9bcc26c53a7e2ad89334e8fd8d6c3df9
| 0.676573 | 4.482699 | false | false | false | false |
Digilent/vivado-library
|
ip/video_scaler/hdl/vhdl/start_for_Mat2AXImb6.vhd
| 1 | 4,650 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity start_for_Mat2AXImb6_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end start_for_Mat2AXImb6_shiftReg;
architecture rtl of start_for_Mat2AXImb6_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity start_for_Mat2AXImb6 is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of start_for_Mat2AXImb6 is
component start_for_Mat2AXImb6_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - conv_std_logic_vector(1, 3);
if (mOutPtr = conv_std_logic_vector(0, 3)) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + conv_std_logic_vector(1, 3);
internal_empty_n <= '1';
if (mOutPtr = conv_std_logic_vector(DEPTH, 3) - conv_std_logic_vector(2, 3)) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_start_for_Mat2AXImb6_shiftReg : start_for_Mat2AXImb6_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
9ad1ea840a3fa7fdd1ece9c61c7c0bef
| 0.54 | 3.480539 | false | false | false | false |
JL-Grande/Ascensor_SED
|
ASCENSOR/tb_motor_ascensor.vhd
| 1 | 1,910 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_motor_ascensor IS
END tb_motor_ascensor;
ARCHITECTURE behavior OF tb_motor_ascensor IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT motor_ascensor
PORT(
CLK : IN std_logic;
RST : IN std_logic;
accionar_bajar : IN std_logic;
accionar_subir : IN std_logic;
motor_subir : OUT std_logic;
motor_bajar : OUT std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
signal accionar_bajar : std_logic := '0';
signal accionar_subir : std_logic := '0';
--Outputs
signal motor_subir : std_logic;
signal motor_bajar : std_logic;
-- Clock period definitions
constant CLK_period : time := 1 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: motor_ascensor PORT MAP (
CLK => CLK,
RST => RST,
accionar_bajar => accionar_bajar,
accionar_subir => accionar_subir,
motor_subir => motor_subir,
motor_bajar => motor_bajar
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
RST <= '0';
WAIT FOR 2 ns;
accionar_bajar <= '0';
accionar_subir<= '0';
WAIT FOR 5 ns;
accionar_bajar <= '0';
accionar_subir<= '1';
WAIT FOR 5 ns;
accionar_bajar <= '1';
accionar_subir<= '0';
WAIT FOR 5 ns;
accionar_bajar <= '1';
accionar_subir<= '1';
WAIT FOR 5 ns;
RST <= '1';
WAIT FOR 3 ns;
RST <= '0';
WAIT FOR 2 ns;
accionar_bajar <= '0';
accionar_subir<= '0';
WAIT FOR 5 ns;
ASSERT false
REPORT "Simulación finalizada. Test superado."
SEVERITY FAILURE;
end process;
END;
|
gpl-3.0
|
3c2c4889c457f710fd30410fcc2f5280
| 0.580628 | 3.479053 | false | false | false | false |
Digilent/vivado-library
|
ip/dvi2rgb/src/PhaseAlign.vhd
| 5 | 14,475 |
-------------------------------------------------------------------------------
--
-- File: PhaseAlign.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 7 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module receives a DVI-encoded stream of 10-bit deserialized words
-- and tries to change the phase of the serial data to shift the sampling
-- event to the middle of the "eye", ie. the part of the bit period where
-- data is stable. Alignment is achieved by incrementing the tap count of
-- the IDELAYE2 primitives, delaying data by kIDLY_TapValuePs in each step.
-- In Artix-7 architecture each tap (step) accounts to 78 ps.
-- Data is considered valid when control tokens are recognized in the
-- stream. Alignment lock is achieved when the middle of the valid eye is
-- found. When this happens, pAligned will go high. If the whole range of
-- delay values had been exhausted and alignment lock could still not be
-- achieved, pError will go high. Resetting the module with pRst will
-- restart the alignment process.
-- The port pEyeSize provides an approximation of the width of the
-- eye in units of tap count. The larger the number, the better the signal
-- quality of the DVI stream.
-- Since the IDELAYE2 primitive only allows a fine alignment, the bitslip
-- feature of the ISERDES primitives complements the PhaseAlign module acting
-- as coarse alignment to find the 10-bit word boundary in the data stream.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PhaseAlign is
Generic (
kUseFastAlgorithm : boolean := false;
kCtlTknCount : natural := 128; --how many subsequent control tokens make a valid blank detection
kIDLY_TapValuePs : natural := 78; --delay in ps per tap
kIDLY_TapWidth : natural := 5); --number of bits for IDELAYE2 tap counter
Port (
pRst : in STD_LOGIC;
pTimeoutOvf : in std_logic; --50ms timeout expired
pTimeoutRst : out std_logic; --reset timeout
PixelClk : in STD_LOGIC;
pData : in STD_LOGIC_VECTOR (9 downto 0);
pIDLY_CE : out STD_LOGIC;
pIDLY_INC : out STD_LOGIC;
pIDLY_CNT : in STD_LOGIC_VECTOR (kIDLY_TapWidth-1 downto 0);
pIDLY_LD : out STD_LOGIC; --load default tap value
pAligned : out STD_LOGIC;
pError : out STD_LOGIC;
pEyeSize : out STD_LOGIC_VECTOR(kIDLY_TapWidth-1 downto 0));
end PhaseAlign;
architecture Behavioral of PhaseAlign is
-- Control Token Counter
signal pCtlTknCnt : natural range 0 to kCtlTknCount-1;
signal pCtlTknRst, pCtlTknOvf : std_logic;
-- Control Token Detection Pipeline
signal pTkn0Flag, pTkn1Flag, pTkn2Flag, pTkn3Flag : std_logic;
signal pTkn0FlagQ, pTkn1FlagQ, pTkn2FlagQ, pTkn3FlagQ : std_logic;
signal pTknFlag, pTknFlagQ, pBlankBegin : std_logic;
signal pDataQ : std_logic_vector(pData'high downto pData'low);
constant kTapCntEnd : std_logic_vector(pIDLY_CNT'range) := (others => '0');
constant kFastTapCntEnd : std_logic_vector(pIDLY_CNT'range) := std_logic_vector(to_unsigned(20, pIDLY_CNT'length)); -- fast search limit; if token not found in 20 taps, fail earlier and bitslip
signal pIDLY_CNT_Q : std_logic_vector(pIDLY_CNT'range);
signal pDelayOvf, pDelayFastOvf, pDelayCenter : std_logic;
-- IDELAY increment/decrement wait counter
-- CE, INC registered outputs + CNTVALUEOUT registered input + CNTVALUEOUT registered comparison
constant kDelayWaitEnd : natural := 3;
signal pDelayWaitCnt : natural range 0 to kDelayWaitEnd - 1;
signal pDelayWaitRst, pDelayWaitOvf : std_logic;
constant kEyeOpenCntMin : natural := 3;
constant kEyeOpenCntEnough : natural := 16;
signal pEyeOpenCnt : unsigned(kIDLY_TapWidth-1 downto 0);
signal pCenterTap : unsigned(kIDLY_TapWidth downto 0); -- 1 extra bit to increment with 1/2 for every open eye tap
signal pEyeOpenRst, pEyeOpenEn : std_logic;
--Flags
signal pFoundJtrFlag, pFoundEyeFlag : std_logic;
--FSM
--type state_t is (ResetSt, IdleSt, TokenSt, EyeOpenSt, JtrZoneSt, DlyIncSt, DlyTstOvfSt, DlyDecSt, DlyTstCenterSt, AlignedSt, AlignErrorSt);
subtype state_t is std_logic_vector(10 downto 0);
signal pState, pStateNxt : state_t;
-- Ugh, manual state encoding, since Vivado won't tell me the result of automatic encoding; we need this for debugging.
constant ResetSt : state_t := "00000000001";
constant IdleSt : state_t := "00000000010";
constant TokenSt : state_t := "00000000100";
constant EyeOpenSt : state_t := "00000001000";
constant JtrZoneSt : state_t := "00000010000";
constant DlyIncSt : state_t := "00000100000";
constant DlyTstOvfSt : state_t := "00001000000";
constant DlyDecSt : state_t := "00010000000";
constant DlyTstCenterSt : state_t :="00100000000";
constant AlignedSt : state_t := "01000000000";
constant AlignErrorSt : state_t := "10000000000";
begin
ControlTokenCounter: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pCtlTknRst = '1') then
pCtlTknCnt <= 0;
else
pCtlTknCnt <= pCtlTknCnt + 1;
-- Overflow
if (pCtlTknCnt = kCtlTknCount - 1) then
pCtlTknOvf <= '1';
else
pCtlTknOvf <= '0';
end if;
end if;
end if;
end process ControlTokenCounter;
-- Control Token Detection
pTkn0Flag <= '1' when pDataQ = kCtlTkn0 else '0';
pTkn1Flag <= '1' when pDataQ = kCtlTkn1 else '0';
pTkn2Flag <= '1' when pDataQ = kCtlTkn2 else '0';
pTkn3Flag <= '1' when pDataQ = kCtlTkn3 else '0';
-- Register pipeline
ControlTokenDetect: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
pDataQ <= pData; -- level 1
pTkn0FlagQ <= pTkn0Flag;
pTkn1FlagQ <= pTkn1Flag;
pTkn2FlagQ <= pTkn2Flag;
pTkn3FlagQ <= pTkn3Flag; -- level 2
pTknFlag <= pTkn0Flag or pTkn1Flag or pTkn2Flag or pTkn3Flag; -- level 3
pTknFlagQ <= pTknFlag;
pBlankBegin <= not pTknFlagQ and pTknFlag; -- level 4
end if;
end process ControlTokenDetect;
-- Open Eye Width Counter
EyeOpenCnt: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pEyeOpenRst = '1') then
pEyeOpenCnt <= (others => '0');
pCenterTap <= unsigned(pIDLY_CNT_Q) & '1'; -- 1 extra bit for 1/2 increments; start with 1/2
elsif (pEyeOpenEn = '1') then
pEyeOpenCnt <= pEyeOpenCnt + 1;
pCenterTap <= pCenterTap + 1;
end if;
end if;
end process EyeOpenCnt;
pEyeSize <= std_logic_vector(pEyeOpenCnt);
-- Tap Delay Overflow
TapDelayCnt: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
pIDLY_CNT_Q <= pIDLY_CNT;
if (pIDLY_CNT_Q = kTapCntEnd) then
pDelayOvf <= '1';
else
pDelayOvf <= '0';
end if;
if (pIDLY_CNT_Q = kFastTapCntEnd) then
pDelayFastOvf <= '1';
else
pDelayFastOvf <= '0';
end if;
end if;
end process TapDelayCnt;
-- Tap Delay Center
TapDelayCenter: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (unsigned(pIDLY_CNT_Q) = SHIFT_RIGHT(pCenterTap, 1)) then
pDelayCenter <= '1';
else
pDelayCenter <= '0';
end if;
end if;
end process TapDelayCenter;
DelayIncWaitCounter: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pDelayWaitRst = '1') then
pDelayWaitCnt <= 0;
else
pDelayWaitCnt <= pDelayWaitCnt + 1;
if (pDelayWaitCnt = kDelayWaitEnd - 1) then
pDelayWaitOvf <= '1';
else
pDelayWaitOvf <= '0';
end if;
end if;
end if;
end process DelayIncWaitCounter;
-- FSM
FSM_Sync: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pRst = '1') then
pState <= ResetSt;
else
pState <= pStateNxt;
end if;
end if;
end process FSM_Sync;
--FSM Outputs
pTimeoutRst <= '0' when pState = IdleSt or pState = TokenSt else '1';
pCtlTknRst <= '0' when pState = TokenSt else '1';
pDelayWaitRst <= '0' when pState = DlyTstOvfSt or pState = DlyTstCenterSt else '1';
pEyeOpenRst <= '1' when pState = ResetSt or (pState = JtrZoneSt and pFoundEyeFlag = '0') else '0';
pEyeOpenEn <= '1' when pState = EyeOpenSt else '0';
--FSM Registered Outputs
FSM_RegOut: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pState = ResetSt) then
pIDLY_LD <= '1';
else
pIDLY_LD <= '0';
end if;
if (pState = DlyIncSt) then
pIDLY_INC <= '1';
pIDLY_CE <= '1';
elsif (pState = DlyDecSt) then
pIDLY_INC <= '0';
pIDLY_CE <= '1';
else
pIDLY_CE <= '0';
end if;
if (pState = AlignedSt) then
pAligned <= '1';
else
pAligned <= '0';
end if;
if (pState = AlignErrorSt) then
pError <= '1';
else
pError <= '0';
end if;
end if;
end process FSM_RegOut;
FSM_Flags: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
case (pState) is
when ResetSt =>
pFoundEyeFlag <= '0';
pFoundJtrFlag <= '0';
when JtrZoneSt =>
pFoundJtrFlag <= '1';
when EyeOpenSt =>
-- We consider the eye found, if we had found jitter before and the eye is at least kEyeOpenCntMin wide OR
-- We have not seen jitter yet (because tap 0 was already in the eye) and the eye is at least kEyeOpenCntEnough wide
if ((pFoundJtrFlag = '1' and pEyeOpenCnt = kEyeOpenCntMin) or (pEyeOpenCnt = kEyeOpenCntEnough)) then
pFoundEyeFlag <= '1';
end if;
when others =>
end case;
end if;
end process FSM_Flags;
FSM_NextState: process (pState, pBlankBegin, pTimeoutOvf, pCtlTknOvf, pDelayOvf, pDelayFastOvf, pDelayWaitOvf,
pEyeOpenCnt, pDelayCenter, pFoundEyeFlag, pTknFlagQ)
begin
pStateNxt <= pState; --default is to stay in current state
case (pState) is
when ResetSt =>
pStateNxt <= IdleSt;
when IdleSt => -- waiting for a token with timeout
if (pBlankBegin = '1') then
pStateNxt <= TokenSt;
elsif (pTimeoutOvf = '1') then
pStateNxt <= JtrZoneSt; -- we didn't find a proper blank, must be in jitter zone
end if;
when TokenSt => -- waiting for kCtlTknCount tokens with timeout
if (pTknFlagQ = '0') then
pStateNxt <= IdleSt;
elsif (pCtlTknOvf = '1') then
pStateNxt <= EyeOpenSt;
end if;
when JtrZoneSt =>
if (pFoundEyeFlag = '1') then
pStateNxt <= DlyDecSt; -- this jitter zone ends an open eye, go back to the middle of the eye
elsif (kUseFastAlgorithm and pDelayFastOvf = '1' and pFoundEyeFlag = '0') then
pStateNxt <= AlignErrorSt;
else
pStateNxt <= DlyIncSt;
end if;
when EyeOpenSt =>
-- If our eye is already kEyeOpenCntEnough wide, consider the search finished and consider the current tap value
-- the end of our eye = jitter zone
if (pEyeOpenCnt = kEyeOpenCntEnough) then
pStateNxt <= JtrZoneSt;
else
pStateNxt <= DlyIncSt;
end if;
when DlyIncSt =>
pStateNxt <= DlyTstOvfSt;
when DlyTstOvfSt =>
if (pDelayWaitOvf = '1') then
if (pDelayOvf = '1') then
pStateNxt <= AlignErrorSt; -- we went through all the delay taps
else
pStateNxt <= IdleSt;
end if;
end if;
when DlyDecSt =>
pStateNxt <= DlyTstCenterSt;
when DlyTstCenterSt =>
if (pDelayWaitOvf = '1') then
if (pDelayCenter = '1') then
pStateNxt <= AlignedSt; -- we went back to the center of the eye, done
else
pStateNxt <= DlyDecSt;
end if;
end if;
when AlignedSt =>
null; --stay here
when AlignErrorSt =>
null; --stay here
when others =>
pStateNxt <= ResetSt;
end case;
end process FSM_NextState;
end Behavioral;
|
mit
|
a2894af56c1997794a041cb81989ed54
| 0.639378 | 4.411765 | false | false | false | false |
grafi-tt/Maizul
|
src/Unit/Fetch.vhd
| 1 | 1,921 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;
entity Fetch is
port (
clk : in std_logic;
d : in fetch_in_t;
q : out fetch_out_t);
end Fetch;
architecture twoproc of Fetch is
component BlkRAM is
port (
clk : in std_logic;
addr : in blkram_addr;
inst : out instruction_t := (others => '0');
w : in blkram_write_t);
end component;
component Predict is
port (
clk : in std_logic;
d : in predict_in_t;
q : out predict_out_t);
end component;
signal pc, pci : blkram_addr := (others => '0');
signal dp : predict_in_t := (
pc => (others => '0'),
inst => (others => '0'),
target => (others => '0'),
enable_fetch => false,
enable_target => false);
signal qp : predict_out_t;
signal inst : instruction_t;
signal inited : boolean := false;
begin
blkram_map : BlkRAM port map (
clk => clk,
addr => pc,
inst => inst,
w => d.w);
predict_map : Predict port map (
clk => clk,
d => dp,
q => qp);
sequential : process(clk)
begin
if rising_edge(clk) then
pci <= pc;
inited <= true;
end if;
end process;
combinatorial : process(d, qp, pci, inst, inited)
variable pc_inc : blkram_addr;
begin
pc_inc := blkram_addr(unsigned(pci) + 1);
dp.pc <= pc_inc;
dp.inst <= inst;
dp.target <= d.addr;
dp.enable_target <= d.enable_addr;
q.jump <= not qp.succeed and inited;
dp.enable_fetch <= d.enable_fetch;
q.pc <= pc_inc;
q.inst <= inst;
if d.enable_fetch and inited then
pc <= qp.addr;
else
pc <= pci;
end if;
end process;
end twoproc;
|
bsd-2-clause
|
fb09d9f173867e5554e4dac9d50065f3
| 0.498699 | 3.652091 | false | false | false | false |
rickyzhangNYC/Pipelined_Multimedia_Cell_Lite_Unit
|
thirtytwobit_module.vhd
| 1 | 2,307 |
-------------------------------------------------------------------------------
--
-- Title : thirtytwobit_module
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\thirtytwobit_module.vhd
-- Generated : Mon Nov 21 11:04:28 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {thirtytwobit_module} architecture {structural}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity thirtytwobit_module is
port(
c0: in std_logic;
a: in std_logic_vector (63 downto 0);
b: in std_logic_vector (63 downto 0);
s: out std_logic_vector (63 downto 0);
Carry: out std_logic
);
end thirtytwobit_module;
--}} End of automatically maintained section
architecture structural of thirtytwobit_module is
signal P, G: std_logic_vector (3 downto 0);
signal C: std_logic_vector (3 downto 1);
signal carry_or: std_logic;
begin
carry_or <= Carry or c0;
first16bitCLA: entity sixteenbit_module port map(a => a(15 downto 0), b => b(15 downto 0), s => s(15 downto 0), c0 => carry_or, P64bit => P(0), G64bit => G(0));
second16bitCLA: entity sixteenbit_module port map(a=> a(31 downto 16), b => b(31 downto 16), s=> s(31 downto 16), c0 => C(1), P64bit => P(1), G64bit => G(1));
third16bitCLA: entity sixteenbit_module port map(a => a(47 downto 32), b => b(47 downto 32), s => s(47 downto 32), c0 => C(2), P64bit => P(2), G64bit => G(2));
fourth16bitCLA: entity sixteenbit_module port map(a => a(63 downto 48), b => b(63 downto 48), s => s(63 downto 48), c0 => C(3), P64bit => P(3), G64bit => G(3));
third_level_cla: entity third_level_CLA port map(p0 => P(0), p1 => P(1), p2 => P(2), p3 => P(3), g0 => G(0), g1 => G(1), g2 => G(2), g3 => G(3) , carry_in => c0, Ci(1) => C(1), Ci(2) => C(2), Ci(3) => C(3), Ci(4) => Carry);
end structural;
|
apache-2.0
|
37bd65d271b58cb8ad144519f565058d
| 0.522323 | 3.244726 | false | false | false | false |
igormacedo/vhdlstudy
|
somadorNbits.vhd
| 1 | 732 |
entity somadornbits is
generic(n: integer := 32);
port(
a, b : in bit_vector(n-1 downto 0);
te : in bit;
s : out bit_vector(n-1 downto 0);
ts : out bit
);
end entity;
architecture estrutura of somadornbits is
signal t: bit_vector(n downto 0);
begin
process(a,b,t,te)
begin
t(0) <= te;
for i in 0 to n-1 loop
s(i) <= a(i) xor (b(i) xor t(i));
t(i+1) <= (a(i) and b(i)) or (a(i) and t(i)) or (b(i) and t(i));
end loop;
ts <= t(n);
--t(0) <= te;
--s(0) <= a(0) xor b(0) xor t(0);
--t(1) <= (a(0) and b(0)) or (a(0) and t(0)) or (b(0) and t(0));
--s(1) <= a(1) xor b(1) xor t(1);
--t(2) <= (a(1) and b(1)) or (a(1) and t(1)) or (b(1) and t(1));
--ts <= t(2);
end process;
end architecture;
|
mit
|
3804fedc61738ec92848deb9802d33e2
| 0.51776 | 2.005479 | false | false | false | false |
olajep/oh
|
src/adi/hdl/library/common/axi_streaming_dma_tx_fifo.vhd
| 1 | 3,427 |
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
--
-- In this HDL repository, there are many different and unique modules, consisting
-- of various HDL (Verilog or VHDL) components. The individual modules are
-- developed independently, and may be accompanied by separate and unique license
-- terms.
--
-- The user should read each of these license terms, and understand the
-- freedoms and responsibilities that he or she has by using this source/core.
--
-- This core is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-- A PARTICULAR PURPOSE.
--
-- Redistribution and use of source or resulting binaries, with or without modification
-- of this file, are permitted under one of the following two license terms:
--
-- 1. The GNU General Public License version 2 as published by the
-- Free Software Foundation, which can be found in the top level directory
-- of this repository (LICENSE_GPL2), and also online at:
-- <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
--
-- OR
--
-- 2. An ADI specific BSD license, which can be found in the top level directory
-- of this repository (LICENSE_ADIBSD), and also on-line at:
-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
-- This will allow to generate bit files and not release the source code,
-- as long as it attaches to an ADI device.
--
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dma_fifo;
entity axi_streaming_dma_tx_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable DMA interface
enable : in Boolean;
-- Write port
s_axis_aclk : in std_logic;
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector(FIFO_DWIDTH-1 downto 0);
s_axis_tlast : in std_logic;
s_axis_tvalid : in std_logic;
-- Read port
out_stb : out std_logic;
out_ack : in std_logic;
out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0)
);
end;
architecture imp of axi_streaming_dma_tx_fifo is
signal in_ack : std_logic;
signal drain_dma : Boolean;
begin
fifo: entity dma_fifo
generic map (
RAM_ADDR_WIDTH => RAM_ADDR_WIDTH,
FIFO_DWIDTH => FIFO_DWIDTH
)
port map (
clk => clk,
resetn => resetn,
fifo_reset => fifo_reset,
in_stb => s_axis_tvalid,
in_ack => in_ack,
in_data => s_axis_tdata,
out_stb => out_stb,
out_ack => out_ack,
out_data => out_data
);
drain_process: process (s_axis_aclk) is
variable enable_d1 : Boolean;
begin
if rising_edge(s_axis_aclk) then
if resetn = '0' then
drain_dma <= False;
else
if s_axis_tlast = '1' then
drain_dma <= False;
elsif not enable_d1 and enable then
drain_dma <= False;
elsif enable_d1 and not enable then
drain_dma <= True;
end if;
enable_d1 := enable;
end if;
end if;
end process;
s_axis_tready <= '1' when in_ack = '1' or drain_dma else '0';
end;
|
mit
|
45ddc05780664ccddd323df68c601fa3
| 0.615407 | 3.461616 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/Loop_loop_height_fYi.vhd
| 1 | 6,097 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Loop_loop_height_fYi_rom is
generic(
dwidth : integer := 8;
awidth : integer := 8;
mem_size : integer := 256
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of Loop_loop_height_fYi_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem : mem_array := (
0 => "00000000", 1 => "00000010", 2 => "00000100", 3 => "00000111",
4 => "00001001", 5 => "00001011", 6 => "00001101", 7 => "00001111",
8 => "00010001", 9 => "00010011", 10 => "00010110", 11 => "00011000",
12 => "00011010", 13 => "00011100", 14 => "00011110", 15 => "00100000",
16 => "00100010", 17 => "00100100", 18 => "00100110", 19 => "00101000",
20 => "00101010", 21 => "00101100", 22 => "00101110", 23 => "00110000",
24 => "00110010", 25 => "00110100", 26 => "00110110", 27 => "00111000",
28 => "00111010", 29 => "00111100", 30 => "00111110", 31 => "01000000",
32 => "01000010", 33 => "01000011", 34 => "01000101", 35 => "01000111",
36 => "01001001", 37 => "01001011", 38 => "01001101", 39 => "01001111",
40 => "01010000", 41 => "01010010", 42 => "01010100", 43 => "01010110",
44 => "01011000", 45 => "01011001", 46 => "01011011", 47 => "01011101",
48 => "01011111", 49 => "01100001", 50 => "01100010", 51 => "01100100",
52 => "01100110", 53 => "01100111", 54 => "01101001", 55 => "01101011",
56 => "01101100", 57 => "01101110", 58 => "01110000", 59 => "01110001",
60 => "01110011", 61 => "01110101", 62 => "01110110", 63 => "01111000",
64 => "01111010", 65 => "01111011", 66 => "01111101", 67 => "01111110",
68 => "10000000", 69 => "10000001", 70 => "10000011", 71 => "10000100",
72 => "10000110", 73 => "10001000", 74 => "10001001", 75 => "10001011",
76 => "10001100", 77 => "10001101", 78 => "10001111", 79 => "10010000",
80 => "10010010", 81 => "10010011", 82 => "10010101", 83 => "10010110",
84 => "10011000", 85 => "10011001", 86 => "10011010", 87 => "10011100",
88 => "10011101", 89 => "10011111", 90 => "10100000", 91 => "10100001",
92 => "10100011", 93 => "10100100", 94 => "10100101", 95 => "10100111",
96 => "10101000", 97 => "10101001", 98 => "10101010", 99 => "10101100",
100 => "10101101", 101 => "10101110", 102 => "10101111", 103 => "10110001",
104 => "10110010", 105 => "10110011", 106 => "10110100", 107 => "10110110",
108 => "10110111", 109 => "10111000", 110 => "10111001", 111 => "10111010",
112 => "10111011", 113 => "10111101", 114 => "10111110", 115 => "10111111",
116 => "11000000", 117 => "11000001", 118 => "11000010", 119 => "11000011",
120 => "11000100", 121 => "11000101", 122 => "11000110", 123 => "11000111",
124 => "11001000", 125 => "11001001", 126 => "11001010", 127 => "11001011",
128 => "11001100", 129 => "11001101", 130 => "11001110", 131 => "11001111",
132 => "11010000", 133 => "11010001", 134 => "11010010", 135 => "11010011",
136 => "11010100", 137 => "11010101", 138 => "11010110", 139 => "11010111",
140 => "11011000", 141 => "11011001", 142 to 143=> "11011010", 144 => "11011011",
145 => "11011100", 146 => "11011101", 147 => "11011110", 148 to 149=> "11011111",
150 => "11100000", 151 => "11100001", 152 to 153=> "11100010", 154 => "11100011",
155 => "11100100", 156 to 157=> "11100101", 158 => "11100110", 159 => "11100111",
160 to 161=> "11101000", 162 => "11101001", 163 to 164=> "11101010", 165 => "11101011",
166 to 167=> "11101100", 168 to 169=> "11101101", 170 => "11101110", 171 to 172=> "11101111",
173 to 174=> "11110000", 175 to 176=> "11110001", 177 to 178=> "11110010", 179 => "11110011",
180 to 181=> "11110100", 182 to 184=> "11110101", 185 to 186=> "11110110", 187 to 188=> "11110111",
189 to 190=> "11111000", 191 to 193=> "11111001", 194 to 196=> "11111010", 197 to 199=> "11111011",
200 to 202=> "11111100", 203 to 205=> "11111101", 206 to 210=> "11111110", 211 to 255=> "11111111" );
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity Loop_loop_height_fYi is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 256;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of Loop_loop_height_fYi is
component Loop_loop_height_fYi_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
Loop_loop_height_fYi_rom_U : component Loop_loop_height_fYi_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0);
end architecture;
|
mit
|
d0317b581511b07412711af1a3d1675f
| 0.541414 | 3.642174 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodScopeController/tb/tb_TestConfigRelay_all.vhd
| 1 | 4,054 |
-------------------------------------------------------------------------------
--
-- File: tb_TestConfigRelay_all.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This test bench is used instantiate the tb_ConfigRelay test bench with
-- various configuration options.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_TestConfigRelay_all is
-- Port ( );
end tb_TestConfigRelay_all;
architecture Behavioral of tb_TestConfigRelay_all is
begin
-- Test the Relay configuration module with static relay setting.
-- All relays are configured in the set state.
InstConfigRelayStatic0: entity work.tb_TestConfigRelay
Generic Map(
kExtRelayConfigEn => false,
kCh1CouplingConfigInit => '0',
kCh2CouplingConfigInit =>'0',
kCh1GainConfigInit => '0',
kCh2GainConfigInit => '0'
);
-- Test the Relay configuration module with static relay setting.
-- All relays are configured in the reset state.
InstConfigRelayStatic1: entity work.tb_TestConfigRelay
Generic Map(
kExtRelayConfigEn => false,
kCh1CouplingConfigInit => '1',
kCh2CouplingConfigInit =>'1',
kCh1GainConfigInit => '1',
kCh2GainConfigInit => '1'
);
-- Test the Relay configuration module with the external configuration
-- enabled. The initial value of the configuration signals is '0'.
InstConfigRelayInit0: entity work.tb_TestConfigRelay
Generic Map(
kExtRelayConfigEn => true,
kCh1CouplingConfigInit => '0',
kCh2CouplingConfigInit =>'0',
kCh1GainConfigInit => '0',
kCh2GainConfigInit => '0'
);
-- Test the Relay configuration module with the external configuration
-- enabled. The initial value of the configuration signals is '1'.
InstConfigRelayInit1: entity work.tb_TestConfigRelay
Generic Map(
kExtRelayConfigEn => true,
kCh1CouplingConfigInit => '1',
kCh2CouplingConfigInit =>'1',
kCh1GainConfigInit => '1',
kCh2GainConfigInit => '1'
);
end Behavioral;
|
mit
|
8c8c41f61e23662354fdd8f4ad3f2d59
| 0.673656 | 4.820452 | false | true | false | false |
scottlbaker/Nova-SOC
|
src/fifo16.vhd
| 2 | 4,269 |
--========================================================================
-- fifo.vhd :: FIFO (16-deep)
--
-- (c) Scott L. Baker, Sierra Circuit Design
--========================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity FIFO is
port(
FIFO_OUT : out std_logic_vector(7 downto 0);
FIFO_IN : in std_logic_vector(7 downto 0);
OVFL : out std_logic; -- overflow
LAST : out std_logic; -- nearly full
EMPTY : out std_logic; -- empty
FIFO_OP : in std_logic; -- 1==push 0==pop
CKEN : in std_logic; -- clock enable
CLK : in std_logic; -- clock
RESET : in std_logic -- Reset
);
end FIFO;
architecture BEHAVIORAL of FIFO is
signal RD_ADDR : std_logic_vector(3 downto 0);
signal WR_ADDR : std_logic_vector(3 downto 0);
signal DEPTH : std_logic_vector(3 downto 0);
type Memtype is array (integer range 0 to 15) of std_logic_vector(7 downto 0);
signal MEM : Memtype;
begin
--================================================================
-- FIFO pointers
--================================================================
FIFO_POINTERS:
process(CLK)
begin
if (CLK = '0' and CLK'event) then
-- increment write pointer on push
-- and increment the depth.. if not full (no overflow)
if ((FIFO_OP = '1') and (CKEN = '1') and (DEPTH /= "1111")) then
WR_ADDR <= WR_ADDR + 1;
DEPTH <= DEPTH + 1;
end if;
-- increment read pointer on pop
-- and decrement the depth.. if not empty (no underflow)
if ((FIFO_OP = '0') and (CKEN = '1') and (DEPTH /= "0000")) then
RD_ADDR <= RD_ADDR + 1;
DEPTH <= DEPTH - 1;
end if;
-- reset state
if (RESET = '1') then
WR_ADDR <= (others => '0');
RD_ADDR <= (others => '0');
DEPTH <= (others => '0');
end if;
end if;
end process;
--================================================================
-- FIFO flags
--================================================================
FIFO_FLAGS:
process(CLK)
begin
if (CLK = '0' and CLK'event) then
OVFL <= '0';
LAST <= '0';
EMPTY <= '0';
if (DEPTH = "1111") then
OVFL <= '1';
end if;
if ((DEPTH = "1110") or (DEPTH = "1111")) then
LAST <= '1';
end if;
if (DEPTH = "0000") then
EMPTY <= '1';
end if;
end if;
end process;
--================================================================
-- Fifo RAM
--================================================================
FIFO_RAM:
process(CLK)
begin
if (CLK = '0' and CLK'event) then
if ((CKEN = '1') and (FIFO_OP = '1')) then
MEM(conv_integer(WR_ADDR)) <= FIFO_IN;
end if;
if (RESET = '1') then
MEM(0) <= (others => '0');
MEM(1) <= (others => '0');
MEM(2) <= (others => '0');
MEM(3) <= (others => '0');
MEM(4) <= (others => '0');
MEM(5) <= (others => '0');
MEM(6) <= (others => '0');
MEM(7) <= (others => '0');
MEM(8) <= (others => '0');
MEM(9) <= (others => '0');
MEM(10) <= (others => '0');
MEM(11) <= (others => '0');
MEM(12) <= (others => '0');
MEM(13) <= (others => '0');
MEM(14) <= (others => '0');
MEM(15) <= (others => '0');
end if;
end if;
end process;
FIFO_OUT <= MEM(conv_integer(RD_ADDR));
end BEHAVIORAL;
|
gpl-3.0
|
6b0b1f5613252edb2f75b266b5623ed9
| 0.35301 | 4.303427 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
Interpolation_not_complete/CSAFullAdder.vhd
| 2 | 1,076 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CSAFullAdder is
generic( width : integer := 8 );
port
(
x_1 : in std_logic_vector( width downto 0 );
x_2 : in std_logic_vector( width downto 0 );
x_3 : in std_logic_vector( width downto 0 );
Sum : out std_logic_vector( width downto 0 );
Carry : out std_logic_vector( width downto 0 )
);
end CSAFullAdder;
architecture Behavioral of CSAFullAdder is
begin
process( x_1, x_2, x_3 )
variable s1 : std_logic;
variable s2 : std_logic;
variable s3 : std_logic;
begin
for i in 0 to width loop
s1 := ( x_1( i ) xor x_2( i ) );
s2 := ( x_3( i ) and s1 );
s3 := ( x_1( i ) and x_2( i ) );
Sum( i ) <= ( s1 xor x_3( i ) );
Carry( i ) <= ( s2 or s3 );
end loop;
end process;
end Behavioral;
|
mit
|
e02d37e9540fd124b8a726925cb852de
| 0.590149 | 2.972376 | false | false | false | false |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx
|
Frecuencimentro/RelojEscalado.vhd
| 2 | 1,268 |
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk_mod is
Port (
entrada: in STD_LOGIC;
reset : in STD_LOGIC;
salida : out STD_LOGIC
);
end clk_mod;
architecture Behavioral of clk_mod is
signal temporal: STD_LOGIC;
signal contador: integer range 0 to 20 := 0;
begin
divisor_frecuencia: process (reset, entrada) begin
if (reset = '1') then
temporal <= '0';
contador <= 0;
elsif rising_edge(entrada) then
if (contador = 20) then
temporal <= NOT(temporal);
contador <= 0;
else
contador <= contador+1;
end if;
end if;
end process;
salida <= temporal;
end Behavioral;
|
gpl-2.0
|
6de0c434b47a5537c912f88d7368c8f0
| 0.504732 | 4.972549 | false | false | false | false |
grafi-tt/Maizul
|
fpu-misc/original/fadd-grafi/fadd/u232c_recv.vhd
| 1 | 1,699 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity U232C_RECV is
generic (
WTIME : std_logic_vector(15 downto 0) := x"1B17");
port (
CLK : in std_logic;
OK : in std_logic;
RX : in std_logic;
DATA : out std_logic_vector (7 downto 0);
RECVED : out std_logic);
end U232C_RECV;
architecture blackbox of U232C_RECV is
signal countdown : std_logic_vector(15 downto 0);
signal recvbuf : std_logic_vector(8 downto 0) := (others => '0');
signal state : integer range 0 to 11 := 11;
signal sig_recved : std_logic := '0';
begin
RECVED <= sig_recved;
recvbuf(8) <= RX;
statemachine : process(CLK)
begin
if rising_edge(CLK) then
case state is
when 11 =>
if recvbuf(8) = '1' then
-- read start bit at half of wtime
countdown <= "0"&WTIME(15 downto 1);
state <= 10;
end if;
when 10 =>
if recvbuf(8) = '0' then
if countdown = 0 then
countdown <= WTIME;
state <= state-1;
else
countdown <= countdown-1;
end if;
else
countdown <= "0"&WTIME(15 downto 1);
end if;
when 1 =>
if countdown = 0 then
if recvbuf(8) = '1' then
sig_recved <= '1';
state <= 0;
else
state <= 11;
end if;
else
countdown <= countdown-1;
end if;
when 0 =>
if OK = '1' then
DATA <= recvbuf(7 downto 0);
sig_recved <= '0';
state <= 11;
end if;
when others =>
if countdown = 0 then
recvbuf(7 downto 0) <= recvbuf(8 downto 1);
countdown <= WTIME;
state <= state-1;
else
countdown <= countdown-1;
end if;
end case;
end if;
end process;
end blackbox;
|
bsd-2-clause
|
39853a752dbe73c9240cf426bd90d73e
| 0.569158 | 2.92931 | false | false | false | false |
JL-Grande/Ascensor_SED
|
ASCENSOR/FSM.vhd
| 1 | 2,919 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity FSM is
PORT(
clock,reset,nivel, abierto, cerrado: IN std_logic;
piso,boton: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
boton_memoria: out STD_LOGIC_VECTOR (1 DOWNTO 0);
accionador_puerta: out STD_LOGIC;
accionador_subir, accionador_bajar: out STD_LOGIC
);
end FSM;
architecture Behavioral of FSM is
TYPE estado IS (inicial,parado,cerrando,marcha,abriendo);
SIGNAL presente: estado:=inicial;
SIGNAL bot: std_logic_vector(1 DOWNTO 0); -- Almacena botón pulsado
SIGNAL piso_ini: std_logic_vector(1 DOWNTO 0); -- Piso de partida
begin
estados:
PROCESS(reset,clock)
BEGIN
IF reset='1' THEN presente<=inicial;
ELSIF clock='1' AND clock'event THEN
CASE presente IS
WHEN inicial=> -- Estado inicial para que se nivele
IF nivel='1' then presente<=parado;
END IF;
WHEN parado=> -- Espera la pulsación de un botón
IF (bot/="00") AND (bot/=piso) THEN presente<=cerrando;
END IF;
WHEN cerrando=> -- Cierra la puerta
IF cerrado='1' THEN presente<=marcha;
END IF;
WHEN marcha=> -- Lleva el ascensor a su piso
IF (bot=piso) AND (nivel='1') THEN presente<=abriendo;
END IF;
WHEN abriendo=> -- Abre las puertas
IF abierto='1' THEN presente<=parado;
END IF;
END CASE;
END IF;
END PROCESS estados;
salida:
PROCESS(clock)
BEGIN
if rising_edge(clock) then
boton_memoria<=bot;
CASE presente IS
WHEN inicial=> -- Al encender puede que este entre dos pisos
IF piso/="01" THEN
accionador_subir<='0'; -- Bajamos
accionador_bajar<='1';
END IF;
accionador_puerta<='0'; -- Cerrada
WHEN parado=>
accionador_subir<='0'; -- Parado
accionador_bajar<='0';
accionador_puerta<='1'; -- Abierta
WHEN cerrando=>
accionador_subir<='0'; -- Parado
accionador_bajar<='0';
accionador_puerta<='0';
WHEN marcha=>
IF bot<piso_ini THEN
accionador_subir<='0'; -- Bajamos
accionador_bajar<='1';
ELSE
accionador_subir<='1'; -- Subimos
accionador_bajar<='0';
END IF;
accionador_puerta<='0'; -- Cerrada
WHEN abriendo=>
accionador_subir<='0'; -- Parado
accionador_bajar<='0';
accionador_puerta<='1'; -- Abrir
END CASE;
end if;
END PROCESS salida;
memoria:
PROCESS(reset,clock,piso) -- Captura la pulsación del botón
BEGIN -- y el piso donde se encuentra
IF reset='1' THEN
bot<="00";
piso_ini<=piso;
ELSIF clock='1' AND clock'event THEN
IF presente=parado THEN
IF (boton="01") OR (boton="10") OR (boton="11") THEN bot<=boton;
ELSE bot<="00"; -- Cualquier otra combinación no vale
END IF;
piso_ini<=piso;
END IF;
END IF;
END PROCESS memoria;
end Behavioral;
|
gpl-3.0
|
7f9e956557fa9aa4163cba0925cc7211
| 0.624186 | 3.218302 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_gamma_correction_1_0/hdl/vhdl/Loop_loop_height_g8j.vhd
| 1 | 13,484 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Loop_loop_height_g8j_rom is
generic(
dwidth : integer := 8;
awidth : integer := 8;
mem_size : integer := 256
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
addr2 : in std_logic_vector(awidth-1 downto 0);
ce2 : in std_logic;
q2 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of Loop_loop_height_g8j_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
signal addr2_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem0 : mem_array := (
0 => "00000000", 1 => "00001000", 2 => "00001100", 3 => "00010000",
4 => "00010011", 5 => "00010110", 6 => "00011000", 7 => "00011011",
8 => "00011101", 9 => "00100000", 10 => "00100010", 11 => "00100100",
12 => "00100110", 13 => "00101000", 14 => "00101010", 15 => "00101011",
16 => "00101101", 17 => "00101111", 18 => "00110001", 19 => "00110010",
20 => "00110100", 21 => "00110110", 22 => "00110111", 23 => "00111001",
24 => "00111010", 25 => "00111100", 26 => "00111101", 27 => "00111111",
28 => "01000000", 29 => "01000010", 30 => "01000011", 31 => "01000100",
32 => "01000110", 33 => "01000111", 34 => "01001000", 35 => "01001010",
36 => "01001011", 37 => "01001100", 38 => "01001110", 39 => "01001111",
40 => "01010000", 41 => "01010001", 42 => "01010011", 43 => "01010100",
44 => "01010101", 45 => "01010110", 46 => "01010111", 47 => "01011001",
48 => "01011010", 49 => "01011011", 50 => "01011100", 51 => "01011101",
52 => "01011110", 53 => "01100000", 54 => "01100001", 55 => "01100010",
56 => "01100011", 57 => "01100100", 58 => "01100101", 59 => "01100110",
60 => "01100111", 61 => "01101000", 62 => "01101001", 63 => "01101010",
64 => "01101011", 65 => "01101101", 66 => "01101110", 67 => "01101111",
68 => "01110000", 69 => "01110001", 70 => "01110010", 71 => "01110011",
72 => "01110100", 73 => "01110101", 74 => "01110110", 75 => "01110111",
76 => "01111000", 77 => "01111001", 78 => "01111010", 79 => "01111011",
80 => "01111100", 81 to 82=> "01111101", 83 => "01111110", 84 => "01111111",
85 => "10000000", 86 => "10000001", 87 => "10000010", 88 => "10000011",
89 => "10000100", 90 => "10000101", 91 => "10000110", 92 => "10000111",
93 => "10001000", 94 => "10001001", 95 to 96=> "10001010", 97 => "10001011",
98 => "10001100", 99 => "10001101", 100 => "10001110", 101 => "10001111",
102 => "10010000", 103 => "10010001", 104 to 105=> "10010010", 106 => "10010011",
107 => "10010100", 108 => "10010101", 109 => "10010110", 110 => "10010111",
111 to 112=> "10011000", 113 => "10011001", 114 => "10011010", 115 => "10011011",
116 => "10011100", 117 => "10011101", 118 to 119=> "10011110", 120 => "10011111",
121 => "10100000", 122 => "10100001", 123 to 124=> "10100010", 125 => "10100011",
126 => "10100100", 127 => "10100101", 128 => "10100110", 129 to 130=> "10100111",
131 => "10101000", 132 => "10101001", 133 => "10101010", 134 to 135=> "10101011",
136 => "10101100", 137 => "10101101", 138 => "10101110", 139 to 140=> "10101111",
141 => "10110000", 142 => "10110001", 143 to 144=> "10110010", 145 => "10110011",
146 => "10110100", 147 to 148=> "10110101", 149 => "10110110", 150 => "10110111",
151 => "10111000", 152 to 153=> "10111001", 154 => "10111010", 155 => "10111011",
156 to 157=> "10111100", 158 => "10111101", 159 => "10111110", 160 to 161=> "10111111",
162 => "11000000", 163 => "11000001", 164 to 165=> "11000010", 166 => "11000011",
167 to 168=> "11000100", 169 => "11000101", 170 => "11000110", 171 to 172=> "11000111",
173 => "11001000", 174 => "11001001", 175 to 176=> "11001010", 177 => "11001011",
178 to 179=> "11001100", 180 => "11001101", 181 => "11001110", 182 to 183=> "11001111",
184 => "11010000", 185 to 186=> "11010001", 187 => "11010010", 188 to 189=> "11010011",
190 => "11010100", 191 => "11010101", 192 to 193=> "11010110", 194 => "11010111",
195 to 196=> "11011000", 197 => "11011001", 198 to 199=> "11011010", 200 => "11011011",
201 to 202=> "11011100", 203 => "11011101", 204 to 205=> "11011110", 206 => "11011111",
207 => "11100000", 208 to 209=> "11100001", 210 => "11100010", 211 to 212=> "11100011",
213 => "11100100", 214 to 215=> "11100101", 216 => "11100110", 217 to 218=> "11100111",
219 => "11101000", 220 to 221=> "11101001", 222 => "11101010", 223 to 224=> "11101011",
225 to 226=> "11101100", 227 => "11101101", 228 to 229=> "11101110", 230 => "11101111",
231 to 232=> "11110000", 233 => "11110001", 234 to 235=> "11110010", 236 => "11110011",
237 to 238=> "11110100", 239 => "11110101", 240 to 241=> "11110110", 242 to 243=> "11110111",
244 => "11111000", 245 to 246=> "11111001", 247 => "11111010", 248 to 249=> "11111011",
250 to 251=> "11111100", 252 => "11111101", 253 to 254=> "11111110", 255 => "11111111" );
signal mem1 : mem_array := (
0 => "00000000", 1 => "00001000", 2 => "00001100", 3 => "00010000",
4 => "00010011", 5 => "00010110", 6 => "00011000", 7 => "00011011",
8 => "00011101", 9 => "00100000", 10 => "00100010", 11 => "00100100",
12 => "00100110", 13 => "00101000", 14 => "00101010", 15 => "00101011",
16 => "00101101", 17 => "00101111", 18 => "00110001", 19 => "00110010",
20 => "00110100", 21 => "00110110", 22 => "00110111", 23 => "00111001",
24 => "00111010", 25 => "00111100", 26 => "00111101", 27 => "00111111",
28 => "01000000", 29 => "01000010", 30 => "01000011", 31 => "01000100",
32 => "01000110", 33 => "01000111", 34 => "01001000", 35 => "01001010",
36 => "01001011", 37 => "01001100", 38 => "01001110", 39 => "01001111",
40 => "01010000", 41 => "01010001", 42 => "01010011", 43 => "01010100",
44 => "01010101", 45 => "01010110", 46 => "01010111", 47 => "01011001",
48 => "01011010", 49 => "01011011", 50 => "01011100", 51 => "01011101",
52 => "01011110", 53 => "01100000", 54 => "01100001", 55 => "01100010",
56 => "01100011", 57 => "01100100", 58 => "01100101", 59 => "01100110",
60 => "01100111", 61 => "01101000", 62 => "01101001", 63 => "01101010",
64 => "01101011", 65 => "01101101", 66 => "01101110", 67 => "01101111",
68 => "01110000", 69 => "01110001", 70 => "01110010", 71 => "01110011",
72 => "01110100", 73 => "01110101", 74 => "01110110", 75 => "01110111",
76 => "01111000", 77 => "01111001", 78 => "01111010", 79 => "01111011",
80 => "01111100", 81 to 82=> "01111101", 83 => "01111110", 84 => "01111111",
85 => "10000000", 86 => "10000001", 87 => "10000010", 88 => "10000011",
89 => "10000100", 90 => "10000101", 91 => "10000110", 92 => "10000111",
93 => "10001000", 94 => "10001001", 95 to 96=> "10001010", 97 => "10001011",
98 => "10001100", 99 => "10001101", 100 => "10001110", 101 => "10001111",
102 => "10010000", 103 => "10010001", 104 to 105=> "10010010", 106 => "10010011",
107 => "10010100", 108 => "10010101", 109 => "10010110", 110 => "10010111",
111 to 112=> "10011000", 113 => "10011001", 114 => "10011010", 115 => "10011011",
116 => "10011100", 117 => "10011101", 118 to 119=> "10011110", 120 => "10011111",
121 => "10100000", 122 => "10100001", 123 to 124=> "10100010", 125 => "10100011",
126 => "10100100", 127 => "10100101", 128 => "10100110", 129 to 130=> "10100111",
131 => "10101000", 132 => "10101001", 133 => "10101010", 134 to 135=> "10101011",
136 => "10101100", 137 => "10101101", 138 => "10101110", 139 to 140=> "10101111",
141 => "10110000", 142 => "10110001", 143 to 144=> "10110010", 145 => "10110011",
146 => "10110100", 147 to 148=> "10110101", 149 => "10110110", 150 => "10110111",
151 => "10111000", 152 to 153=> "10111001", 154 => "10111010", 155 => "10111011",
156 to 157=> "10111100", 158 => "10111101", 159 => "10111110", 160 to 161=> "10111111",
162 => "11000000", 163 => "11000001", 164 to 165=> "11000010", 166 => "11000011",
167 to 168=> "11000100", 169 => "11000101", 170 => "11000110", 171 to 172=> "11000111",
173 => "11001000", 174 => "11001001", 175 to 176=> "11001010", 177 => "11001011",
178 to 179=> "11001100", 180 => "11001101", 181 => "11001110", 182 to 183=> "11001111",
184 => "11010000", 185 to 186=> "11010001", 187 => "11010010", 188 to 189=> "11010011",
190 => "11010100", 191 => "11010101", 192 to 193=> "11010110", 194 => "11010111",
195 to 196=> "11011000", 197 => "11011001", 198 to 199=> "11011010", 200 => "11011011",
201 to 202=> "11011100", 203 => "11011101", 204 to 205=> "11011110", 206 => "11011111",
207 => "11100000", 208 to 209=> "11100001", 210 => "11100010", 211 to 212=> "11100011",
213 => "11100100", 214 to 215=> "11100101", 216 => "11100110", 217 to 218=> "11100111",
219 => "11101000", 220 to 221=> "11101001", 222 => "11101010", 223 to 224=> "11101011",
225 to 226=> "11101100", 227 => "11101101", 228 to 229=> "11101110", 230 => "11101111",
231 to 232=> "11110000", 233 => "11110001", 234 to 235=> "11110010", 236 => "11110011",
237 to 238=> "11110100", 239 => "11110101", 240 to 241=> "11110110", 242 to 243=> "11110111",
244 => "11111000", 245 to 246=> "11111001", 247 => "11111010", 248 to 249=> "11111011",
250 to 251=> "11111100", 252 => "11111101", 253 to 254=> "11111110", 255 => "11111111" );
attribute syn_rom_style : string;
attribute syn_rom_style of mem0 : signal is "block_rom";
attribute syn_rom_style of mem1 : signal is "block_rom";
attribute ROM_STYLE : string;
attribute ROM_STYLE of mem0 : signal is "block";
attribute ROM_STYLE of mem1 : signal is "block";
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
memory_access_guard_2: process (addr2)
begin
addr2_tmp <= addr2;
--synthesis translate_off
if (CONV_INTEGER(addr2) > mem_size-1) then
addr2_tmp <= (others => '0');
else
addr2_tmp <= addr2;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem0(CONV_INTEGER(addr0_tmp));
end if;
if (ce1 = '1') then
q1 <= mem0(CONV_INTEGER(addr1_tmp));
end if;
if (ce2 = '1') then
q2 <= mem1(CONV_INTEGER(addr2_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity Loop_loop_height_g8j is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 256;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address2 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of Loop_loop_height_g8j is
component Loop_loop_height_g8j_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR;
addr2 : IN STD_LOGIC_VECTOR;
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR);
end component;
begin
Loop_loop_height_g8j_rom_U : component Loop_loop_height_g8j_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1,
addr2 => address2,
ce2 => ce2,
q2 => q2);
end architecture;
|
mit
|
54bbb6c94175a2d9408c214964b1c87f
| 0.549985 | 3.594775 | false | false | false | false |
scottlbaker/Nova-SOC
|
src/reset.vhd
| 2 | 2,914 |
--======================================================================
-- reset.vhd :: Debounce and Synchonize Reset
--
-- (c) Scott L. Baker, Sierra Circuit Design
--======================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity XRESET is
port (
RST_OUT1 : out std_logic; -- (active low)
RST_OUT2 : out std_logic; -- (active low)
RST_IN : in std_logic; -- (active low)
CLK : in std_logic
);
end XRESET;
architecture BEHAVIORAL of XRESET is
--=================================================================
-- Signal definitions
--=================================================================
signal DLY_CNTR : std_logic_vector(3 downto 0);
signal RST_DLY1 : std_logic;
signal RST_DLY2 : std_logic;
signal RST_INT1 : std_logic;
signal RST_INT2 : std_logic;
begin
--================================================================
-- Debounce and Synchonize the (active-low) Reset Input
--================================================================
-- Depending on the reset and power-supply circuits of the host
-- system, we may need to wait for the power supply to stabilize
-- before starting to fetch opcodes. A simple LFSR counter is
-- provided for this purpose. Here are the states
--
-- 0 0000 4 1010 8 0110 12 1110
-- 1 0001 5 0100 9 1101 13 1100
-- 2 0010 6 1001 10 1011 14 1000
-- 3 0101 7 0011 11 0111
--
--================================================================
DEBOUNCE_AND_SYNCHRONIZE_RESET:
process(CLK)
begin
if (CLK = '0' and CLK'event) then
RST_DLY1 <= RST_IN;
RST_DLY2 <= RST_DLY1;
-- count
if (RST_INT2 = '1') then
-- linear-feedback counter
DLY_CNTR(0) <= DLY_CNTR(3) xnor DLY_CNTR(0);
DLY_CNTR(1) <= DLY_CNTR(0);
DLY_CNTR(2) <= DLY_CNTR(1);
DLY_CNTR(3) <= DLY_CNTR(2);
end if;
-- release early reset
if (DLY_CNTR = "0110") then
RST_INT1 <= '0';
end if;
-- release late reset
if (DLY_CNTR = "1000") then
RST_INT2 <= '0';
DLY_CNTR <= "0000";
end if;
-- initiatialize the reset counter
if (RST_DLY1 = '0' and RST_DLY2 = '0') then
RST_INT1 <= '1';
RST_INT2 <= '1';
DLY_CNTR <= "0000";
end if;
end if;
end process;
RST_OUT1 <= not RST_INT1;
RST_OUT2 <= not RST_INT2;
end architecture BEHAVIORAL;
|
gpl-3.0
|
ba8341a625ee0f9fd34d64a85fad8367
| 0.40151 | 4.310651 | false | false | false | false |
Digilent/vivado-library
|
ip/rgb2dvi/src/ClockGen.vhd
| 1 | 10,787 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/03/2014 06:27:16 PM
-- Design Name:
-- Module Name: ClockGen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity ClockGen is
Generic (
kClkRange : natural := 1; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3, >=30MHz=4, >=25MHz=5
kClkPrimitive : string := "MMCM"); -- "MMCM" or "PLL" to instantiate, if kGenerateSerialClk true
Port (
PixelClkIn : in STD_LOGIC;
PixelClkOut : out STD_LOGIC;
SerialClk : out STD_LOGIC;
aRst : in STD_LOGIC;
aLocked : out STD_LOGIC);
end ClockGen;
architecture Behavioral of ClockGen is
component SyncAsync is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
Port (
aReset : in STD_LOGIC; -- active-high asynchronous reset
aIn : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end component SyncAsync;
component ResetBridge is
Generic (
kPolarity : std_logic := '1');
Port (
aRst : in STD_LOGIC; -- asynchronous reset; active-high, if kPolarity=1
OutClk : in STD_LOGIC;
oRst : out STD_LOGIC);
end component ResetBridge;
signal PixelClkInX1, PixelClkInX5, FeedbackClkIn, FeedbackClkOut : std_logic;
signal aLocked_int, pLocked, pRst, pLockWasLost, pLockGained : std_logic;
signal pLocked_q : std_logic_vector(2 downto 0) := (others => '1');
attribute CLOCK_BUFFER_TYPE : string;
attribute CLOCK_BUFFER_TYPE of PixelClkInX5: signal is "NONE";
attribute CLOCK_BUFFER_TYPE of PixelClkInX1: signal is "NONE";
begin
-- We need a reset bridge to use the asynchronous aRst signal to reset our circuitry
-- and decrease the chance of metastability. The signal pRst can be used as
-- asynchronous reset for any flip-flop in the PixelClkIn domain, since it will be de-asserted
-- synchronously.
LockLostReset: ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aRst,
OutClk => PixelClkIn,
oRst => pRst);
PLL_LockSyncAsync: SyncAsync
port map (
aReset => '0',
aIn => aLocked_int,
OutClk => PixelClkIn,
oOut => pLocked);
PLL_LockLostDetect: process(PixelClkIn, pRst)
begin
if (pRst = '1') then
pLocked_q <= (others => '0');
pLockWasLost <= '1';
pLockGained <= '0';
elsif Rising_Edge(PixelClkIn) then
pLocked_q <= pLocked_q(pLocked_q'high-1 downto 0) & pLocked;
pLockWasLost <= (not pLocked_q(0) or not pLocked_q(1)) and pLocked_q(2); --two-pulse
pLockGained <= (pLocked_q(0) and not pLocked_q(1));
end if;
end process;
-- The TMDS Clk channel carries a character-rate frequency reference
-- In a single Clk period a whole character (10 bits) is transmitted
-- on each data channel. For deserialization of data channel a faster,
-- serial clock needs to be generated. In 7-series architecture an
-- OSERDESE2 primitive doing a 10:1 deserialization in DDR mode needs
-- a fast 5x clock and a slow 1x clock. These two clocks are generated
-- below with an MMCME2_ADV/PLLE2_ADV.
-- Caveats:
-- 1. The primitive uses a multiply-by-5 and divide-by-1 to generate
-- a 5x fast clock.
-- While changes in the frequency of the TMDS Clk are tracked by the
-- MMCM, for some TMDS Clk frequencies the datasheet specs for the VCO
-- frequency limits are not met. In other words, there is no single
-- set of MMCM multiply and divide values that can work for the whole
-- range of resolutions and pixel clock frequencies.
-- For example: MMCM_FVCOMIN = 600 MHz
-- MMCM_FVCOMAX = 1200 MHz for Artix-7 -1 speed grade
-- while FVCO = FIN * MULT_F
-- The TMDS Clk for 720p resolution in 74.25 MHz
-- FVCO = 74.25 * 10 = 742.5 MHz, which is between FVCOMIN and FVCOMAX
-- However, the TMDS Clk for 1080p resolution in 148.5 MHz
-- FVCO = 148.5 * 10 = 1480 MHZ, which is above FVCOMAX
-- In the latter case, MULT_F = 5, DIVIDE_F = 5, DIVIDE = 1 would result
-- in a correct VCO frequency, while still generating 5x and 1x clocks
-- 2. The MMCM+BUFIO+BUFR combination results in the highest possible
-- frequencies. PLLE2_ADV could work only with BUFGs, which limits
-- the maximum achievable frequency. The reason is that only the MMCM
-- has dedicated route to BUFIO.
-- If a PLLE2_ADV with BUFGs are used a second CLKOUTx can be used to
-- generate the 1x clock.
GenMMCM: if kClkPrimitive = "MMCM" generate
DVI_ClkGenerator: MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => real(kClkRange) * 5.0,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => real(kClkRange) * 1.0,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => kClkRange * 5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT1_PHASE => 0.0,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => real(kClkRange) * 6.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(
CLKFBOUT => FeedbackClkOut,
CLKFBOUTB => open,
CLKOUT0 => PixelClkInX5,
CLKOUT0B => open,
CLKOUT1 => PixelClkInX1,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => FeedbackClkIn,
CLKIN1 => PixelClkIn,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => aLocked_int,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => pLockWasLost);
-- MMCM is able to drive BUFIO, which is the fastest buffer available
-- 5x fast serial clock
SerialClkBuffer: BUFIO
port map (
O => SerialClk, -- 1-bit output: Clock output (connect to I/O clock loads).
I => PixelClkInX5 -- 1-bit input: Clock input (connect to an IBUF or BUFMR).
);
-- 1x slow parallel clock
PixelClkBuffer: BUFR
generic map (
BUFR_DIVIDE => "5", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => PixelClkOut, -- 1-bit output: Clock output port
CE => '1', -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => pLockGained, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => PixelClkInX5 -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
-- Adding a divide-by-one BUFR in the feedback will de-skew SerialClk and PixelClkOut resulting in better timing
Deskew: BUFR
generic map (
BUFR_DIVIDE => "1", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => FeedbackClkIn, -- 1-bit output: Clock output port
CE => '1', -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => '0', -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => FeedbackClkOut -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
aLocked <= aLocked_int;
end generate;
GenPLL: if kClkPrimitive /= "MMCM" generate
DVI_ClkGenerator: PLLE2_ADV
generic map (
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT => (kClkRange + 1) * 5,
CLKFBOUT_PHASE => 0.000,
CLKIN1_PERIOD => real(kClkRange) * 6.25,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
REF_JITTER1 => 0.010,
STARTUP_WAIT => "FALSE",
CLKOUT0_DIVIDE => (kClkRange + 1) * 1,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => (kClkRange + 1) * 5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT1_PHASE => 0.0)
port map
-- Output clocks
(
CLKFBOUT => FeedbackClkOut,
CLKOUT0 => PixelClkInX5,
CLKOUT1 => PixelClkInX1,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
-- Input clock control
CLKFBIN => FeedbackClkIn,
CLKIN1 => PixelClkIn,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Other control and status signals
LOCKED => aLocked_int,
PWRDWN => '0',
RST => pLockWasLost);
--No buffering used
--These clocks will only drive the OSERDESE2 primitives
SerialClk <= PixelClkInX5;
PixelClkOut <= PixelClkInX1;
FeedbackClkIn <= FeedbackClkOut;
aLocked <= aLocked_int;
end generate;
end Behavioral;
|
mit
|
73714c176de5cb67cc84d63d95a44ac8
| 0.571799 | 4.075179 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodAWGController/tb/SPI_IAP_AD9717_TestModule.vhd
| 1 | 9,552 |
-------------------------------------------------------------------------------
--
-- File: SPI_IAP_AD9717_TestModule.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodAWG1411_Controller
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module is designed to emulate the upper level IP for the SPI indirect
-- access port to facilitate the testing of the ConfigDAC module.
-- The Axi Stream command FIFO is loaded with kCmdFIFO_NoWrCmds commands and the
-- data read back from the ADI_3WireSPI_Model is compared against the expected
-- data.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.PkgZmodDAC.all;
entity SPI_IAP_AD9717_TestModule is
Generic (
-- Parameter identifying the Zmod (for future use).
kZmodID : integer range 7 to 7 := 7
);
Port (
-- 100MHZ clock input.
SysClk100 : in STD_LOGIC;
-- Reset signal asynchronously asserted and synchronously
-- de-asserted (in SysClk100 domain).
asRst_n : in STD_LOGIC;
-- DAC initialization complete flag.
sInitDoneDAC : in std_logic;
-- SPI Indirect access port; it provides the means to indirectly access
-- the DAC registers. It is designed to interface with 2 AXI StreamFIFOs,
-- one that stores commands to be transmitted and one to store the received data.
-- TX command AXI stream interface
sCmdTxAxisTvalid: out STD_LOGIC;
sCmdTxAxisTready: in STD_LOGIC;
sCmdTxAxisTdata: out STD_LOGIC_VECTOR(31 DOWNTO 0);
-- TX command AXI stream interface
sCmdRxAxisTvalid: in STD_LOGIC;
sCmdRxAxisTready: out STD_LOGIC;
sCmdRxAxisTdata : in STD_LOGIC_VECTOR(31 DOWNTO 0)
);
end SPI_IAP_AD9717_TestModule;
architecture Behavioral of SPI_IAP_AD9717_TestModule is
COMPONENT ADC_CommandFIFO
PORT (
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
signal sCmdTxWrRstBusy, sCmdTxRdRstBusy : std_logic;
signal sCmdRxWrRstBusy, sCmdRxRdRstBusy : std_logic;
signal sMasterTxAxisTvalid, sMasterTxAxisTready : std_logic;
signal sMasterTxAxisTdata : std_logic_vector (31 downto 0);
signal sMasterTxAxisTvalidSR : std_logic_vector (kCmdFIFO_NoWrCmds downto 0);
signal sTestCmdRxAxisTvalid : STD_LOGIC;
signal sTestCmdRxAxisTready : STD_LOGIC;
signal sTestCmdRxAxisTdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal RxCmdIndex : unsigned (kCmdFIFO_NoWrCmds downto 0);
signal sTransactionTimer : unsigned (23 downto 0) := (others => '0');
signal sRxTransactionTimeExpired: std_logic := '0';
signal RxCmdDone, RxCmdOverflow, RxCmdRdbkErr : std_logic := '0';
signal sComandList : CmdFIFO_WrCmdList_t;
-- chip grade, chip ID
begin
InstTxFIFO : ADC_CommandFIFO
PORT MAP (
wr_rst_busy => sCmdTxWrRstBusy,
rd_rst_busy => sCmdTxRdRstBusy,
m_aclk => SysClk100,
s_aclk => SysClk100,
s_aresetn => asRst_n,
s_axis_tvalid => sMasterTxAxisTvalid,
s_axis_tready => sMasterTxAxisTready,
s_axis_tdata => sMasterTxAxisTdata,
m_axis_tvalid => sCmdTxAxisTvalid,
m_axis_tready => sCmdTxAxisTready,
m_axis_tdata => sCmdTxAxisTdata
);
sTestCmdRxAxisTready <= '1';
InstRxFIFO : ADC_CommandFIFO
PORT MAP (
wr_rst_busy => sCmdRxWrRstBusy,
rd_rst_busy => sCmdRxRdRstBusy,
m_aclk => SysClk100,
s_aclk => SysClk100,
s_aresetn => asRst_n,
s_axis_tvalid => sCmdRxAxisTvalid,
s_axis_tready => sCmdRxAxisTready,
s_axis_tdata => sCmdRxAxisTdata,
m_axis_tvalid => sTestCmdRxAxisTvalid,
m_axis_tready => sTestCmdRxAxisTready,
m_axis_tdata => sTestCmdRxAxisTdata
);
-- Load the TX command FIFO with the same command list used for the AD9717 initialization
-- The command list is truncated kNumCommands.
-- A shift register on kNumCommands+1 bits will be used to generate the TX command FIFO
-- master interface valid signal.
ProcTxCmdTvalid: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sMasterTxAxisTvalidSR(kCmdFIFO_NoWrCmds downto 1) <= (others => '1');
sMasterTxAxisTvalidSR(0) <= '0';
for i in 0 to kCmdFIFO_NoWrCmds loop
sComandList(i) <= kCmdFIFO_WrList(i);
end loop;
elsif (rising_edge(SysClk100)) then
if (sMasterTxAxisTready = '1') then -- sCmdTxWrRstBusy always in Hi-Z in simulation
sMasterTxAxisTvalidSR <= '0' & sMasterTxAxisTvalidSR(kCmdFIFO_NoWrCmds downto 1);
for i in 0 to kCmdFIFO_NoWrCmds-1 loop
sComandList(i) <= sComandList(i+1);
end loop;
sComandList(kCmdFIFO_NoWrCmds) <= (others => '0');
end if;
end if;
end process;
sMasterTxAxisTvalid <= sMasterTxAxisTvalidSR(0);
sMasterTxAxisTdata <= x"00" & sComandList(0);
-- This process verifies if the expected number of read commands have been
-- completed. An index is incremented as data is extracted from the RX
-- command FIFO.
ProcCmdIndex: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
RxCmdIndex <= (others => '0');
RxCmdDone <= '0';
RxCmdOverflow <= '0';
elsif (rising_edge(SysClk100)) then
if ((sTestCmdRxAxisTready = '1') and (sTestCmdRxAxisTvalid = '1')) then
RxCmdIndex <= RxCmdIndex + 1;
if (to_integer(RxCmdIndex) = kCmdFIFO_NoRdCmds - 1) then
RxCmdDone <= '1';
elsif (to_integer(RxCmdIndex) > kCmdFIFO_NoRdCmds - 1) then
RxCmdOverflow <= '1';
end if;
end if;
end if;
end process;
-- Data checker process; Reads the data available in the Rx command FIFO,
-- compares it against the expected values and asserts a flag if all
-- received commands match the expected values.
ProcDataChecker: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
RxCmdRdbkErr <= '0';
elsif (rising_edge(SysClk100)) then
if ((sTestCmdRxAxisTready = '1') and (sTestCmdRxAxisTvalid = '1')) then
if ((kCmdFIFO_RdList(to_integer(RxCmdIndex)) or kCmdFIFO_RdListMask(to_integer(RxCmdIndex))) /= (sTestCmdRxAxisTdata(7 downto 0) or kCmdFIFO_RdListMask(to_integer(RxCmdIndex)))) then
RxCmdRdbkErr <= '1';
end if;
end if;
end if;
end process;
-- Timer used to determine a timeout condition for the SPI indirect
-- access port transactions to complete.
ProcClkCounter: process (SysClk100, asRst_n) --clock frequency divider
begin
if (asRst_n = '0') then
sTransactionTimer <= (others => '0');
sRxTransactionTimeExpired <= '0';
elsif (rising_edge(SysClk100)) then
if (sInitDoneDAC = '0') then
sTransactionTimer <= (others => '0');
else
if (sTransactionTimer = kCmdFIFO_Timeout) then
sRxTransactionTimeExpired <= '1';
else
sTransactionTimer <= sTransactionTimer + 1;
end if;
end if;
end if;
end process;
-- Process checking relevant status flags and determining if the
-- expected data was correctly received.
ProcMain: process
begin
wait until rising_edge(sRxTransactionTimeExpired);
assert (RxCmdDone = '1' and RxCmdOverflow = '0' and RxCmdRdbkErr = '0')
report "RX FIFO SPI indirect access port command read back error" & LF & HT & HT
severity ERROR;
wait;
end process;
end Behavioral;
|
mit
|
4a9d69a8c6d7b5e9bb12e7d83c86a84f
| 0.671587 | 4.330009 | false | true | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodScopeController/src/ADI_SPI.vhd
| 1 | 15,875 |
-------------------------------------------------------------------------------
--
-- File: ADI_SPI.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module manages the SPI communication with the Analog Devices 3 wire SPI
-- configuration interface
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
use IEEE.math_real.all;
use work.PkgZmodADC.all;
entity ADI_SPI is
Generic
(
-- The sSPI_Clk signal is obtained by dividing SysClk100 to 2^kSysClkDiv.
kSysClkDiv : integer range 2 to 63 := 4;
-- The number of data bits for the data phase of the transaction:
-- only 8 data bits currently supported.
kDataWidth : integer range 8 to 8 := 8;
-- The number of bits of the command phase of the SPI transaction.
kCommandWidth : integer range 8 to 16 := 16
);
Port (
-- input clock (100MHZ).
SysClk100 : in STD_LOGIC;
-- active low synchronous reset signal.
asRst_n : in STD_LOGIC;
--AD92xx/AD96xx SPI interface signals.
sSPI_Clk : out STD_LOGIC;
sSDIO : inout STD_LOGIC;
sCS : out STD_LOGIC := '1';
--Upper layer Interface signals
--a pulse on this input initiates the transfers, also used to register upper layer interface inputs.
sApStart : in STD_LOGIC;
--SPI read data output.
sRdData : out std_logic_vector(kDataWidth - 1 downto 0);
--SPI command data.
sWrData : in std_logic_vector(kDataWidth - 1 downto 0);
--SPI command register address.
sAddr : in std_logic_vector(kCommandWidth - 4 downto 0);
--Number of data bytes + 1; not currently used (for future development).
sWidth : in std_logic_vector(1 downto 0);
--Select between Read/Write operations.
sRdWr : in STD_LOGIC;
--A pulse is generated on this output once the SPI transfer is successfully completed.
sDone : out STD_LOGIC;
--Busy flag; sApStart ignored while this signal is asserted .
sBusy : out STD_LOGIC);
end ADI_SPI;
architecture Behavioral of ADI_SPI is
function MAX(In1 : integer; In2 : integer)
return integer is
begin
if (In1 > In2) then
return In1;
else
return In2;
end if;
end function;
constant kZeros : unsigned (kSysClkDiv - 1 downto 0) := (others => '0');
constant kOnes : unsigned (kSysClkDiv - 1 downto 0) := (others => '1');
signal sClkCounter : unsigned(kSysClkDiv - 1 downto 0) := (others => '0');
signal sSPI_ClkRst: std_logic;
signal sRdDataR : std_logic_vector(kDataWidth - 1 downto 0);
signal sTxVector : std_logic_vector (kDataWidth + kCommandWidth - 1 downto 0);
signal sRxData : std_logic;
signal sTxData : std_logic := '0';
signal sTxShift, sRxShift : std_logic;
signal sLdTx : std_logic;
signal sApStartR, sApStartPulse : std_logic;
constant kCounterMax : integer := MAX((kDataWidth + kCommandWidth + 1), kCS_PulseWidthHigh);
constant kCounterNumBits : integer := integer(ceil(log2(real(kCounterMax))));
signal sCounter : unsigned (kCounterNumBits-1 downto 0);
signal sCounterInt : integer range 0 to (2**kCounterNumBits-1);
signal sCntRst_n, sTxCntEn, sRxCntEn, sDoneCntEn : std_logic := '0';
signal sBitCount : integer range 0 to kDataWidth; --Maximum 4 byte transfers for Analog Devices 2 Wire SPI
signal sDir : std_logic := '0';
signal sDirFsm : std_logic;
signal sCS_Fsm : std_logic;
signal sDoneFsm : std_logic;
signal sBusyFsm : std_logic;
signal sCurrentState : FsmStatesSPI_t := StIdle;
signal sNextState : FsmStatesSPI_t;
-- signals used for debug purposes
-- signal fsm_state, fsm_state_r : std_logic_vector(3 downto 0);
signal kHalfScale : unsigned (kSysClkDiv - 1 downto 0);
begin
kHalfScale <= '1' & kZeros(kSysClkDiv - 2 downto 0);
------------------------------------------------------------------------------------------
-- SPI interface signal assignment
------------------------------------------------------------------------------------------
InstIOBUF : IOBUF -- instantiate SDIO three state output buffer.
generic map (
DRIVE => 12,
IOSTANDARD => "LVCMOS18",
SLEW => "SLOW")
port map (
O => sRxData, -- Buffer output
IO => sSDIO, -- Buffer inout port (connect directly to top-level port)
I => sTxData, -- Buffer input
T => sDir -- 3-state enable input, high=input, low=output
);
-- Three state buffer direction control register.
ProcDir: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sDir <= '0';
elsif (rising_edge(SysClk100)) then
if (sLdTx = '1') then
sDir <= sDirFsm;
else
if ((sClkCounter = kOnes) or (sCS_Fsm = '1')) then
sDir <= sDirFsm;
end if;
end if;
end if;
end process;
ProcRegCS: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCS <= '1';
--fsm_state_r <= (others => '0');
elsif (rising_edge (SysClk100)) then
sCS <= sCS_Fsm;
--fsm_state_r <= fsm_state;
end if;
end process;
sSPI_Clk <= sClkCounter(kSysClkDiv - 1 );
------------------------------------------------------------------------------------------
-- Input clock frequency divider
------------------------------------------------------------------------------------------
ProcClkCounter: process (SysClk100, asRst_n) --clock frequency divider
begin
if (asRst_n = '0') then
sClkCounter <= (others => '0');
elsif (rising_edge(SysClk100)) then
if (sSPI_ClkRst = '1') then
sClkCounter <= (others => '0');
else
sClkCounter <= sClkCounter + 1;
end if;
end if;
end process;
------------------------------------------------------------------------------------------
-- Transmit logic
------------------------------------------------------------------------------------------
sBitCount <= kDataWidth;
ProcApStartReg: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sApStartR <= '0';
elsif (rising_edge(SysClk100)) then
sApStartR <= sApStart;
end if;
end process;
sApStartPulse <= sApStart and (not sApStartR);
ProcShiftTx: process (SysClk100, asRst_n) --Transmit shift register
begin
if (asRst_n = '0') then
sTxVector <= (others => '0');--sRdWr & "00" & sAddr & sWrData;
sTxData <= '0';
elsif (rising_edge(SysClk100)) then
if (sApStartPulse = '1') then
--sTxVector <= sRdWr & sWidth & sAddr & sWrData;
sTxVector <= sRdWr & "00" & sAddr & sWrData;
sTxData <= '0';
else
if(sTxShift = '1') then
--data is placed on the falling edge (sClkCounter = kZeros) of sSPI_Clk for the transmit phase.
if ((sClkCounter = kZeros) and (sCounterInt <= kDataWidth+kCommandWidth)) then
sTxVector(kDataWidth + kCommandWidth - 1 downto 0) <= sTxVector(kDataWidth + kCommandWidth - 2 downto 0) & '0';
sTxData <= sTxVector(kDataWidth + kCommandWidth - 1);
elsif (sCounterInt > kDataWidth+kCommandWidth) then
sTxData <= '0';
end if;
else
sTxData <= '0';
end if;
end if;
end if;
end process;
ProcTxCount: process (asRst_n, sTxShift, sLdTx, sClkCounter) --Transmit bit count
begin
if ((asRst_n = '0') or (sLdTx = '1')) then
sTxCntEn <= '0';
else
if(sTxShift = '1') then
--The TX bit count incremented on the falling edge of the sSPI_Clk (sClkCounter = kZeros).
if (sClkCounter = kZeros) then
sTxCntEn <= '1';
else
sTxCntEn <= '0';
end if;
else
sTxCntEn <= '0';
end if;
end if;
end process;
------------------------------------------------------------------------------------------
-- Receive logic
------------------------------------------------------------------------------------------
-- Receive deserializer.
ProcShiftRx: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sRdDataR <= (others =>'0');
elsif (rising_edge(SysClk100)) then
if (sRxShift = '0') then
sRdDataR <= (others =>'0');
else
if ((sRxShift = '1') and (sClkCounter = kHalfScale)) then
--The read data is sampled on the rising edge of the sSPI_Clk (sClkCounter = kHalfScale).
sRdDataR(kDataWidth - 1 downto 0) <= sRdDataR(kDataWidth - 2 downto 0) & sRxData;
end if;
end if;
end if;
end process;
ProcRxCount: process (asRst_n, sRxShift, sClkCounter, kHalfScale) --Receive bit count
begin
if ((asRst_n = '0') or (sRxShift = '0')) then
sRxCntEn <= '0';
else
if (sRxShift = '1') then
--The RX bit count is incremented on the rising edge of the sSPI_Clk (sClkCounter = kHalfScale).
if (sClkCounter = kHalfScale) then
sRxCntEn <= '1';
else
sRxCntEn <= '0';
end if;
else
sRxCntEn <= '0';
end if;
end if;
end process;
-- Register SPI read data once read instruction is completed.
ProcRdData: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sRdData <= (others => '0');
sDone <= '0';
elsif (rising_edge (SysClk100)) then
sDone <= sDoneFsm;
if (sDoneFsm = '1') then
sRdData <= sRdDataR;
end if;
end if;
end process;
ProcBusy: process (SysClk100, asRst_n) --register sBusyFsm output
begin
if (asRst_n = '0') then
sBusy <= '1';
elsif (rising_edge (SysClk100)) then
sBusy <= sBusyFsm;
end if;
end process;
--Counter used by both transmit and receive logic; sCS minimum pulse width high is also timed by this counter.
ProcCounter: process (SysClk100, asRst_n)
begin
if (asRst_n = '0') then
sCounter <= (others => '0');
elsif (rising_edge(SysClk100)) then
if (sCntRst_n = '0') then
sCounter <= (others => '0');
else
if ((sTxCntEn = '1') or (sRxCntEn = '1') or (sDoneCntEn = '1')) then
sCounter <= sCounter + 1;
end if;
end if;
end if;
end process;
sCounterInt <= to_integer (sCounter);
------------------------------------------------------------------------------------------
-- SPI State Machine
------------------------------------------------------------------------------------------
ProcFsmSync: process (SysClk100, asRst_n) --State machine synchronous process
begin
if (asRst_n = '0') then
sCurrentState <= StIdle;
elsif (rising_edge (SysClk100)) then
sCurrentState <= sNextState;
end if;
end process;
--Next State decode logic
ProcNextStateAndOutputDecode: process (sCurrentState, sApStart, sRdWr, sCounterInt, sClkCounter, sBitCount)
begin
sNextState <= sCurrentState;
sDirFsm <= '0';
sCS_Fsm <= '1';
sDoneFsm <= '0';
sRxShift <= '0';
sTxShift <= '0';
--fsm_state <= (others => '0');
sLdTx <= '0';
sSPI_ClkRst <= '1';
sCntRst_n <= '0';
sDoneCntEn <= '0';
sBusyFsm <= '1';
case (sCurrentState) is
when StIdle =>
--fsm_state <= "0000";
sBusyFsm <= '0';
sLdTx <= '1';
if (sApStart = '1') then
if (sRdWr = '1') then
sNextState <= StRead1;
else
sNextState <= StWrite;
end if;
end if;
when StRead1 => --send command bytes
--fsm_state <= "0001";
sCS_Fsm <= '0';
sTxShift <= '1';
sSPI_ClkRst <= '0';
sCntRst_n <= '1';
if (sCounterInt = kCommandWidth) then
sDirFsm <= '1';
sNextState <= StRead2;
end if;
when StRead2 => --send last command bit; change three state buffer direction
--fsm_state <= "0010";
sDirFsm <= '1';
sCS_Fsm <= '0';
sTxShift <= '1';
sSPI_ClkRst <= '0';
sCntRst_n <= '1';
if (sCounterInt = kCommandWidth + 1) then
sNextState <= StRead3;
sCntRst_n <= '0';
end if;
when StRead3 => --receive register read data
--fsm_state <= "0011";
sDirFsm <= '1';
sCS_Fsm <= '0';
sRxShift <= '1';
sSPI_ClkRst <= '0';
sCntRst_n <= '1';
if ((sCounterInt = sBitCount) and (sClkCounter = kOnes + 1)) then
--this condition assures a sSPI_Clk pulse width low of 2 SysClk100 cycles for last data bit
sCntRst_n <= '0';
sDirFsm <= '0';
sNextState <= StDone;
end if;
when StWrite => --send SPI command and register data
--fsm_state <= "0100";
sCS_Fsm <= '0';
sTxShift <= '1';
sSPI_ClkRst <= '0';
sCntRst_n <= '1';
if (sCounterInt = (sBitCount + kCommandWidth + 1)) then
sSPI_ClkRst <= '1';
sNextState <= StDone;
end if;
when StDone => --signal SPI instruction complete
--fsm_state <= "0101";
sDoneFsm <= '1';
sNextState <= StAssertCS;
when StAssertCS => --hold CS high for at least kCS_PulseWidthHigh SysClk100 cycles
--fsm_state <= "0111";
sCntRst_n <= '1';
sDoneCntEn <= '1';
if (sCounterInt = kCS_PulseWidthHigh) then
sNextState <= StIdle;
end if;
when others =>
--fsm_state <= (others => '1');
sNextState <= StIdle;
end case;
end process;
end Behavioral;
|
mit
|
faad7c9d72eef76cf3d092c179132e75
| 0.549921 | 4.464286 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/fifo_w8_d3_A.vhd
| 2 | 4,426 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w8_d3_A_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w8_d3_A_shiftReg;
architecture rtl of fifo_w8_d3_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_w8_d3_A is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w8_d3_A is
component fifo_w8_d3_A_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 4);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w8_d3_A_shiftReg : fifo_w8_d3_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
76c734689fe1c1010d5931ac1cfaa64a
| 0.524401 | 3.455113 | false | false | false | false |
Digilent/vivado-library
|
ip/rgb2dpvid_v1_0/src/rgb2dpvid.vhd
| 2 | 4,161 |
-------------------------------------------------------------------------------
--
-- File: rgb2dpvid.vhd
-- Author: Mihaita Nagy
-- Original Project: RGB to Displayport Video
-- Date: 12 November 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- Converts a kDataWidth-bit RGB interface (VGA compatible) given as input to a
-- Displayport Video interface
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity rgb2dpvid is
generic(
-- Width of the input data bus
kDataWidth : integer := 24
);
port(
-- RGB interface
PixelClk : in std_logic;
pData : in std_logic_vector((kDataWidth-1) downto 0);
pHSync : in std_logic;
pVSync : in std_logic;
pVde : in std_logic;
-- Displayport Video interface
pVidClk : out std_logic;
pVidPixel0 : out std_logic_vector(47 downto 0);
pVidHSync : out std_logic;
pVidVSync : out std_logic;
pVidOddEven : out std_logic;
pVidRst : out std_logic;
pVidEnable : out std_logic
);
end rgb2dpvid;
architecture rtl of rgb2dpvid is
begin
-- Video clock the same as the pixel clock
pVidClk <= PixelClk;
-- Odd/Even qualifier not used
pVidOddEven <= '0';
-- Also reset is not used
pVidRst <= '0';
-- Synchronous process to distribute the video data
SyncIns: process(PixelClk)
begin
if rising_edge(PixelClk) then
pVidHSync <= pHSync;
pVidVSync <= pVSync;
pVidEnable <= pVde;
-- Red component
pVidPixel0(47 downto 47-((kDataWidth/3)-1)) <= pData((kDataWidth-1) downto (kDataWidth-kDataWidth/3));
pVidPixel0(39 downto 32) <= (others => '0');
-- Green component
pVidPixel0(31 downto 31-((kDataWidth/3)-1)) <= pData(((kDataWidth-2*kDataWidth/3)-1) downto 0);
pVidPixel0(23 downto 16) <= (others => '0');
-- Blue component
pVidPixel0(15 downto 15-((kDataWidth/3)-1)) <= pData(((kDataWidth-kDataWidth/3)-1) downto (kDataWidth-2*kDataWidth/3));
pVidPixel0(7 downto 0) <= (others => '0');
end if;
end process SyncIns;
end rtl;
|
mit
|
9a56e53ad43d3424ba48b0a935bc5bcb
| 0.623408 | 4.436034 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodDigitizerController/src/ZmodDigitizerController.vhd
| 1 | 25,078 |
-------------------------------------------------------------------------------
--
-- File: ZmodDigitizerController.vhd
-- Author: Tudor Gherman, Robert Bocos
-- Original Project: ZmodDigitizerController
-- Date: 2021
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module interfaces directly with the Zmod Digitizer 1410-105, Zmod Digitizer
-- 1010-40, Zmod Digitizer 1010-125, Zmod Digitizer 1210-40, Zmod Digitizer 1210-125,
-- Zmod Digitizer 1410-40 and the Zmod Digitizer 1410-125.
-- It configures the clock generator over I2C, writes an initial
-- configuration to the AD96xx/AD92xx on the Zmod via the SPI interface,
-- demultiplexes the data received over the ADC's parallel interface and
-- forwards it to the upper levels.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VComponents.all;
library work;
use work.PkgZmodDigitizer.all;
entity ZmodDigitizerController is
Generic (
-- Parameter identifying the Zmod:
-- 6 -> Zmod Digitizer 1430 - 125 (AD9648)
kZmodID : integer range 6 to 6 := 6;
-- ADC Clock divider ratio (Register 0x0B).
kADC_ClkDiv : integer range 1 to 1 := 1;
-- ADC number of bits.
kADC_Width : integer range 14 to 14 := 14;
-- ADC dynamic/static calibration
kExtCalibEn : boolean := true;
-- Enable/Disable SPI Indirect Access Port.
kExtCmdInterfaceEn : boolean := false;
-- Channel1 high gain multiplicative (gain) compensation coefficient parameter.
kCh1HgMultCoefStatic : std_logic_vector (19 downto 0) := "00010000000000000000";
-- Channel1 high gain additive (offset) compensation coefficient parameter.
kCh1HgAddCoefStatic : std_logic_vector (19 downto 0) := "00000000000000000000";
-- Channel2 high gain multiplicative (gain) compensation coefficient parameter.
kCh2HgMultCoefStatic : std_logic_vector (19 downto 0) := "00010000000000000000";
-- Channel2 high gain additive (offset) compensation coefficient parameter.
kCh2HgAddCoefStatic : std_logic_vector (19 downto 0) := "00000000000000000000";
-- Clock Generator I2C shortened config for simulation
kCG_SimulationConfig : boolean := false;
-- Clock Generator I2C shortened configuration number of commands to send over I2C for simulation (zero based), range should have been
--0 to kCDCE_RegNrZeroBased := kCDCE_RegNrZeroBased, however Vivado IP GUI does not accept expressions
kCG_SimulationCmdTotal : integer range 0 to 85 := 85;
-- Clock Generator I2C 8 bit config address (0xCE(Fall-Back Mode), 0xD0(Default Mode), 0xD2)
kCGI2C_Addr : std_logic_vector(7 downto 0) := x"CE";
-- Clock Generator input reference clock selection parameter ('0' selects SECREF(XTAL) and '1' selects PRIREF(FPGA))
kRefSel : std_logic := '0';
-- Clock Generator EEPROM Page selection parameter ('0' selects Page 0 and '1' selects Page 1)
kHwSwCtrlSel : std_logic := '1';
-- Parameter identifying the CDCE output frequency with SECREF(XTAL) as reference frequency, range should have been
--0 to CDCE_I2C_Cmds'length, however Vivado IP GUI does not accept expressions:
-- 0 -> 122.88MHz
-- 1 -> 50MHz
-- 2 -> 80MHz
-- 3 -> 100MHz
-- 4 -> 110MHz
-- 5 -> 120MHz
-- 6 -> 125MHz
kCDCEFreqSel : integer range 0 to 6 := 0
);
Port (
-- 100MHZ clock input.
SysClk100 : in std_logic;
-- Primary Reference Clock for the Clock Generator present on the Zmod Pod.
-- Due to the fact that there is also an XTAL connected to the SECREF port
-- of the Clock Generator and that it is the one used by default, another
-- source of clock signals, namely ClockGenPriRefClk, is entirely optional.
-- This reference clock is only used if kRefSel(REFSEL) is HIGH or if PRIREF is set in the R2 register (Address 0x02) of the CDCE6214-Q1
ClockGenPriRefClk : in std_logic;
-- Clock Generator config done succesful signal
sInitDoneClockGen : out std_logic;
-- Clock Generator PLL lock signal sent via the GPIO1 or GPIO4 port and synchronized in the SysClock100 domain
sPLL_LockClockGen : out std_logic;
-- MMCM output clock buffered by a BUFG
ZmodDcoClkOut : out std_logic;
sZmodDcoPLL_Lock : out std_logic;
-- Asynchronous reset signal (negative polarity).
aRst_n : in std_logic;
-- ADC initialization complete signaling.
sInitDoneADC : out std_logic;
-- ADC initialization error signaling.
sConfigError : out std_logic;
-- When logic '1', this signal enables data acquisition from the ADC. This signal
-- should be kept in logic '0' until the downstream IP (e.g. DMA controller) is
-- ready to receive the ADC data.
sEnableAcquisition : in std_logic;
--AXI Stream (master) data interface
doDataAxisTvalid: OUT STD_LOGIC;
doDataAxisTready: IN STD_LOGIC;
doDataAxisTdata: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Channel1 high gain multiplicative (gain) compensation coefficient external port.
doExtCh1HgMultCoef : in std_logic_vector (17 downto 0);
--Channel1 high gain additive (offset) compensation coefficient external port.
doExtCh1HgAddCoef : in std_logic_vector (17 downto 0);
--Channel2 high gain multiplicative (gain) compensation coefficient external port.
doExtCh2HgMultCoef : in std_logic_vector (17 downto 0);
--Channel2 high gain additive (offset) compensation coefficient external port.
doExtCh2HgAddCoef : in std_logic_vector (17 downto 0);
-- sTestMode is used to bypass the calibration block. When this signal
-- is asserted, raw samples are provided on the data interface.
sTestMode : in std_logic;
-- SPI Indirect access port; it provides the means to indirectly access
-- the ADC registers. It is designed to interface with 2 AXI StreamFIFOs,
-- one that stores commands to be transmitted and one to store the received data.
-- TX command AXI stream interface
sCmdTxAxisTvalid: IN STD_LOGIC;
sCmdTxAxisTready: OUT STD_LOGIC;
sCmdTxAxisTdata: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-- RX command AXI stream interface
sCmdRxAxisTvalid: OUT STD_LOGIC;
sCmdRxAxisTready: IN STD_LOGIC;
sCmdRxAxisTdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--- ADC signals (see AD96xx data sheet) ---
-- ADC Sync signal.
aZmodSync : out std_logic;
-- ADC DCO.
DcoClkIn : in std_logic;
-- ADC Data.
diZmodADC_Data : in std_logic_vector(kADC_Width-1 downto 0);
-- ADC SPI interface.
sZmodADC_SDIO : inout std_logic;
sZmodADC_CS : out std_logic;
sZmodADC_Sclk : out std_logic;
--- ClockGen Signals (see CDCE6214-Q1 datasheet)---
-- ClockGen differential input reference clock (PRIREF), only matters if REFSEL is set to '1' or if PRIREF is set in the R2 register (Address 0x02) of the CDCE6214-Q1
CG_InputClk_p : out std_logic;
CG_InputClk_n : out std_logic;
-- Clock Generator PLL lock signal sent via the GPIO1 or GPIO4 port
aCG_PLL_Lock : in std_logic;
-- Clock Generator reference selection signal ('0' selects SECREF(XTAL) and '1' selects PRIREF(FPGA))
aREFSEL : out std_logic;
-- Clock Generator EEPROM Page selection signal
aHW_SW_CTRL : out std_logic;
-- Clock Generator power down signal, passthrough output
sPDNout_n : out std_logic;
----------------------------------------------------------------------------------
-- IIC bus signals
----------------------------------------------------------------------------------
s_scl_i : in std_logic; -- IIC Serial Clock Input from 3-state buffer (required)
s_scl_o : out std_logic; -- IIC Serial Clock Output to 3-state buffer (required)
s_scl_t : out std_logic; -- IIC Serial Clock Output Enable to 3-state buffer (required)
s_sda_i : in std_logic; -- IIC Serial Data Input from 3-state buffer (required)
s_sda_o : out std_logic; -- IIC Serial Data Output to 3-state buffer (required)
s_sda_t : out std_logic -- IIC Serial Data Output Enable to 3-state buffer (required)
);
end ZmodDigitizerController;
architecture Behavioral of ZmodDigitizerController is
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO of sCmdTxAxisTdata: SIGNAL is "xilinx.com:interface:axis:1.0 SPI_IAP_TX TDATA";
ATTRIBUTE X_INTERFACE_INFO of sCmdTxAxisTvalid: SIGNAL is "xilinx.com:interface:axis:1.0 SPI_IAP_TX TVALID";
ATTRIBUTE X_INTERFACE_INFO of sCmdTxAxisTready: SIGNAL is "xilinx.com:interface:axis:1.0 SPI_IAP_TX TREADY";
ATTRIBUTE X_INTERFACE_INFO of sCmdRxAxisTdata: SIGNAL is "xilinx.com:interface:axis:1.0 SPI_IAP_RX TDATA";
ATTRIBUTE X_INTERFACE_INFO of sCmdRxAxisTvalid: SIGNAL is "xilinx.com:interface:axis:1.0 SPI_IAP_RX TVALID";
ATTRIBUTE X_INTERFACE_INFO of sCmdRxAxisTready: SIGNAL is "xilinx.com:interface:axis:1.0 SPI_IAP_RX TREADY";
ATTRIBUTE X_INTERFACE_INFO of doDataAxisTdata: SIGNAL is "xilinx.com:interface:axis:1.0 DataStream TDATA";
ATTRIBUTE X_INTERFACE_INFO of doDataAxisTvalid: SIGNAL is "xilinx.com:interface:axis:1.0 DataStream TVALID";
ATTRIBUTE X_INTERFACE_INFO of doDataAxisTready: SIGNAL is "xilinx.com:interface:axis:1.0 DataStream TREADY";
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER of sCmdTxAxisTdata: SIGNAL is "CLK_DOMAIN SysClk100";
ATTRIBUTE X_INTERFACE_PARAMETER of sCmdTxAxisTvalid: SIGNAL is "CLK_DOMAIN SysClk100";
ATTRIBUTE X_INTERFACE_PARAMETER of sCmdTxAxisTready: SIGNAL is "CLK_DOMAIN SysClk100";
ATTRIBUTE X_INTERFACE_PARAMETER of sCmdRxAxisTdata: SIGNAL is "CLK_DOMAIN SysClk100";
ATTRIBUTE X_INTERFACE_PARAMETER of sCmdRxAxisTvalid: SIGNAL is "CLK_DOMAIN SysClk100";
ATTRIBUTE X_INTERFACE_PARAMETER of sCmdRxAxisTready: SIGNAL is "CLK_DOMAIN SysClk100";
ATTRIBUTE X_INTERFACE_PARAMETER of doDataAxisTdata: SIGNAL is "CLK_DOMAIN DcoClkOut";
ATTRIBUTE X_INTERFACE_PARAMETER of doDataAxisTvalid: SIGNAL is "CLK_DOMAIN DcoClkOut";
ATTRIBUTE X_INTERFACE_PARAMETER of doDataAxisTready: SIGNAL is "CLK_DOMAIN DcoClkOut";
ATTRIBUTE X_INTERFACE_INFO of s_scl_i: SIGNAL is "xilinx.com:interface:iic:1.0 CDCE_IIC SCL_I";
ATTRIBUTE X_INTERFACE_INFO of s_scl_o: SIGNAL is "xilinx.com:interface:iic:1.0 CDCE_IIC SCL_O";
ATTRIBUTE X_INTERFACE_INFO of s_scl_t: SIGNAL is "xilinx.com:interface:iic:1.0 CDCE_IIC SCL_T";
ATTRIBUTE X_INTERFACE_INFO of s_sda_i: SIGNAL is "xilinx.com:interface:iic:1.0 CDCE_IIC SDA_I";
ATTRIBUTE X_INTERFACE_INFO of s_sda_o: SIGNAL is "xilinx.com:interface:iic:1.0 CDCE_IIC SDA_O";
ATTRIBUTE X_INTERFACE_INFO of s_sda_t: SIGNAL is "xilinx.com:interface:iic:1.0 CDCE_IIC SDA_T";
--Reset signals
signal adoRst_n, asRst_n, adoRst, asRst, aRst, aiRst : std_logic;
--PLL&Clock signals
signal DcoClkOut : std_logic;
signal ZmodDcoPostBufg, ZmodDcoPostBufio : std_logic;
signal ZmodDcoPLL_LockState : std_logic;
--Initialization complete flags
signal cInitDone, sInitDone, dInitDone : std_logic := '0';
signal sInitDoneADC_Loc : std_logic := '0';
--Data Path
signal OddrClk : std_logic;
signal doDataValid, doDataCalibValid : std_logic;
signal dFIFO_WrRstBusy, sFIFO_WrRstBusy, sFIFO_WrRstBusyDly: std_logic;
signal cFIFO_RdEn: std_logic;
signal dDataOverflow: std_logic;
signal sInitDoneClockGen_Loc : std_logic;
signal sConfigADCEnable : std_logic;
signal doEnableAcquisition: std_logic := '0';
--Calibration
signal doChannelA, doChannelB : std_logic_vector(kADC_Width-1 downto 0);
signal doCh1Calib, doCh2Calib : std_logic_vector(15 downto 0);
signal doTestMode : std_logic;
--Sync OSERDES input
signal doADC_SyncOserdes : std_logic_vector(7 downto 0);
constant kDummy : std_logic_vector(8 downto 0) := (others => '0');
constant kSamplingPeriod : integer := integer(DCO_ClockPeriod(kCDCEFreqSel));
constant kSamplingPeriodReal : real := (real(kSamplingPeriod)*0.001);
-- Removing padding (i.e. most significant 2 bits) from the static calibration constants.
-- The padding is necessary only to be able to enter hexadecimal calibration constants
-- from the GUI.
-- Channel1 high gain multiplicative (gain) compensation coefficient parameter.
constant kCh1HgMultCoefStaticNoPad : std_logic_vector(17 downto 0) :=
kCh1HgMultCoefStatic(17 downto 0);
-- Channel1 high gain additive (offset) compensation coefficient parameter.
constant kCh1HgAddCoefStaticNoPad : std_logic_vector(17 downto 0) :=
kCh1HgAddCoefStatic(17 downto 0);
-- Channel2 high gain multiplicative (gain) compensation coefficient parameter.
constant kCh2HgMultCoefStaticNoPad : std_logic_vector(17 downto 0) :=
kCh2HgMultCoefStatic(17 downto 0);
-- Channel2 high gain additive (offset) compensation coefficient parameter.
constant kCh2HgAddCoefStaticNoPad : std_logic_vector(17 downto 0) :=
kCh2HgAddCoefStatic(17 downto 0);
begin
------------------------------------------------------------------------------------------
-- Reset tree
------------------------------------------------------------------------------------------
-- The asynchronous reset input is converted to an RSD (reset with synchronous
-- de-assertion) in the SysClk100 domain, in the DcoClkOut domain and in
-- the ClockGenPriRefClk domain.
InstDigitizerSysReset : entity work.ResetBridge
Generic map(
kPolarity => '0')
Port map(
aRst => aRst_n,
OutClk => SysClk100,
aoRst => asRst_n);
asRst <= not asRst_n;
InstDigitizerSamplingReset : entity work.ResetBridge
Generic map(
kPolarity => '0')
Port map(
aRst => aRst_n,
OutClk => DcoClkOut,
aoRst => adoRst_n);
adoRst <= not adoRst_n;
aRst <= not aRst_n;
InstClockGenPriRefClkReset : entity work.ResetBridge
Generic map(
kPolarity => '1')
Port map(
aRst => aRst,
OutClk => ClockGenPriRefClk,
aoRst => aiRst);
------------------------------------------------------------------------------------------
-- Clock Generator I2C configuration
------------------------------------------------------------------------------------------
InstConfigCDCE: entity work.ConfigClockGen
Generic Map(
kCDCE_SimulationConfig => kCG_SimulationConfig,
kCDCE_SimulationCmdTotal => kCG_SimulationCmdTotal,
kCDCEI2C_Addr => kCGI2C_Addr,
kRefSel => kRefSel,
kHwSwCtrlSel => kHwSwCtrlSel,
kFreqSel => kCDCEFreqSel
)
Port Map(
RefClk => SysClk100,
-- Reset signal asynchronously asserted and synchronously
-- de-asserted (in SysClk100 domain).
arRst => asRst,
rInitConfigDoneClockGen => sInitDoneClockGen_Loc,
aCG_PLL_Lock => aCG_PLL_Lock,
rPLL_LockClockGen => sPLL_LockClockGen,
rConfigADCEnable => sConfigADCEnable,
aREFSEL => aREFSEL,
aHW_SW_CTRL => aHW_SW_CTRL,
rPDNout_n => sPDNout_n,
----------------------------------------------------------------------------------
-- I2C bus signals
----------------------------------------------------------------------------------
s_scl_i => s_scl_i,
s_scl_o => s_scl_o,
s_scl_t => s_scl_t,
s_sda_i => s_sda_i,
s_sda_o => s_sda_o,
s_sda_t => s_sda_t
);
sInitDoneClockGen <= sInitDoneClockGen_Loc;
------------------------------------------------------------------------------------------
-- ADC SPI configuration
------------------------------------------------------------------------------------------
InstConfigADC: entity work.ConfigADC
Generic Map(
kZmodID => kZmodID,
kADC_ClkDiv => kADC_ClkDiv,
kDataWidth => kSPI_DataWidth,
kCommandWidth => kSPI_CommandWidth,
kSimulation => kCG_SimulationConfig
)
Port Map(
--
SysClk100 => SysClk100,
asRst_n => asRst_n,
sInitDoneADC => sInitDoneADC_Loc,
sConfigError => sConfigError,
sConfigADCEnable => sConfigADCEnable,
--ADC SPI interface signals
sADC_Sclk => sZmodADC_Sclk,
sADC_SDIO => sZmodADC_SDIO,
sADC_CS => sZmodADC_CS,
sCmdTxAxisTvalid => sCmdTxAxisTvalid,
sCmdTxAxisTready => sCmdTxAxisTready,
sCmdTxAxisTdata => sCmdTxAxisTdata,
sCmdRxAxisTvalid => sCmdRxAxisTvalid,
sCmdRxAxisTready => sCmdRxAxisTready,
sCmdRxAxisTdata => sCmdRxAxisTdata
);
sInitDoneADC <= sInitDoneADC_Loc;
------------------------------------------------------------------------------------------
-- DATA PATH
------------------------------------------------------------------------------------------
-- Since the reset value of the InstSyncAsyncEnableAcquisitionDco module is known,
-- the reset can be safely left permanently de-asserted
InstSyncAsyncEnableAcquisitionDco: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aoReset => '0',
aIn => sEnableAcquisition,
OutClk => DcoClkOut,
oOut => doEnableAcquisition);
InstDataPath : entity work.DataPath
Generic Map(
kSamplingPeriod => kSamplingPeriodReal,
kADC_Width => kADC_Width
)
Port Map(
RefClk => SysClk100,
arRst => asRst,
adoRst => adoRst,
DcoClkIn => DcoClkIn,
DcoClkOut => DcoClkOut,
rDcoMMCM_LockState => sZmodDcoPLL_Lock,
doEnableAcquisition => doEnableAcquisition,
diADC_Data => diZmodADC_Data,
doChannelA => doChannelA,
doChannelB => doChannelB,
doDataOutValid => doDataValid
);
ZmodDcoClkOut <= DcoClkOut;
------------------------------------------------------------------------------------------
-- Clock Generator CLKIN (PRIREF)
------------------------------------------------------------------------------------------
InstCG_ClkODDR : ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '0', -- Initial value for Q port ('1' or '0')
SRTYPE => "ASYNC") -- Reset Type ("ASYNC" or "SYNC")
port map (
Q => OddrClk, -- 1-bit DDR output
C => ClockGenPriRefClk, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D1 => '1', -- 1-bit data input (positive edge)
D2 => '0', -- 1-bit data input (negative edge)
R => aiRst, -- 1-bit reset input
S => '0' -- 1-bit set input
);
InstCG_ClkOBUFDS : OBUFDS
generic map (
IOSTANDARD => "DEFAULT", -- Specify the output I/O standard
SLEW => "SLOW") -- Specify the output slew rate
port map (
O => CG_InputClk_p, -- Diff_p output (connect directly to top-level port)
OB => CG_InputClk_n, -- Diff_n output (connect directly to top-level port)
I => OddrClk -- Buffer input
);
------------------------------------------------------------------------------------------
-- Calibration
------------------------------------------------------------------------------------------
-- Synchronize sTestMode in the DcoClkOut domain.
InstDigitizerTestModeSync: entity work.SyncBase
generic map (
kResetTo => '0',
kStages => 2)
port map (
aiReset => asRst,
InClk => SysClk100,
iIn => sTestMode,
aoReset => adoRst,
OutClk => DcoClkOut,
oOut => doTestMode);
-- Instantiate the calibration modules for both channels.
InstCh1ADC_Calibration : entity work.GainOffsetCalib
Generic Map(
kWidth => kADC_Width,
kExtCalibEn => kExtCalibEn,
kInvert => true,
kLgMultCoefStatic => (others => '0'),
kLgAddCoefStatic => (others => '0'),
kHgMultCoefStatic => kCh1HgMultCoefStaticNoPad,
kHgAddCoefStatic => kCh1HgAddCoefStaticNoPad
)
Port Map
(
SamplingClk => DcoClkOut,
acRst_n => adoRst_n,
cTestMode => doTestMode,
cDataAcceptanceReady => doDataAxisTready,
cExtLgMultCoef => (others => '0'),
cExtLgAddCoef => (others => '0'),
cExtHgMultCoef => doExtCh1HgMultCoef,
cExtHgAddCoef => doExtCh1HgAddCoef,
cGainState => '1', --Force High Gain
cDataRaw => doChannelA,
cDataInValid => doDataValid,
cCalibDataOut => doCh1Calib,
cDataCalibValid => doDataCalibValid
);
InstCh2ADC_Calibration : entity work.GainOffsetCalib
Generic Map(
kWidth => kADC_Width,
kExtCalibEn => kExtCalibEn,
kInvert => false,
kLgMultCoefStatic => (others => '0'),
kLgAddCoefStatic => (others => '0'),
kHgMultCoefStatic => kCh2HgMultCoefStaticNoPad,
kHgAddCoefStatic => kCh2HgAddCoefStaticNoPad
)
Port Map
(
SamplingClk => DcoClkOut,
acRst_n => adoRst_n,
cTestMode => doTestMode,
cDataAcceptanceReady => doDataAxisTready,
cExtLgMultCoef => (others => '0'),
cExtLgAddCoef => (others => '0'),
cExtHgMultCoef => doExtCh2HgMultCoef,
cExtHgAddCoef => doExtCh2HgAddCoef,
cGainState => '1', --Force High Gain
cDataRaw => doChannelB,
cDataInValid => doDataValid,
cCalibDataOut => doCh2Calib,
cDataCalibValid => open --both channels share the same valid signal
);
doDataAxisTdata <= doCh1Calib & doCh2Calib;
doDataAxisTvalid <= doDataCalibValid;
SDR_SyncGenerate: if(kADC_ClkDiv = 1) generate
aZmodSync <= '1';
end generate;
end Behavioral;
|
mit
|
0306a51b0eeae89121454107dc159aef
| 0.59614 | 4.898047 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
serial_addition/serial_addition.vhd
| 1 | 2,480 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity serial_addition is
Port
(
clock : in std_logic;
shift : in std_logic;
reset : in std_logic;
serial_input : in std_logic;
signal_augend : out std_logic;
signal_addend : out std_logic;
signal_c_in : out std_logic;
signal_c_out : out std_logic;
signal_sum : out std_logic
);
end serial_addition;
architecture Behavioral of serial_addition is
component srg4
Port
(
clk : in std_logic;
reset : in std_logic;
din : in std_logic;
dout : out std_logic
);
end component ;
component d_flip_flop
Port
(
clk : in std_logic;
reset : in std_logic;
din : in std_logic;
dout : out std_logic
);
end component ;
component full_adder
Port
(
a : in std_logic;
b : in std_logic;
c_in : in std_logic;
sum : out std_logic;
c_out : out std_logic;
for_augend : out std_logic;
for_addend : out std_logic;
for_c_in : out std_logic;
for_c_out : out std_logic;
for_sum : out std_logic
);
end component ;
component inverter
Port
(
x : in std_logic;
y : out std_logic
);
end component ;
component or_gate_2
Port
(
x : in std_logic;
y : in std_logic;
z : out std_logic
);
end component ;
signal shift_inverse: std_logic;
signal enable_shift_motion: std_logic;
signal augend: std_logic;
signal addend: std_logic;
signal carry_in: std_logic;
signal carry_out: std_logic;
signal sum: std_logic;
begin
LABEL1: inverter port map ( x => shift, y => shift_inverse );
LABEL2: or_gate_2 port map ( x => shift_inverse, y => clock, z => enable_shift_motion );
LABEL3: srg4 port map ( clk => enable_shift_motion, reset => reset, din => sum, dout => augend );
LABEL4: srg4 port map ( clk => enable_shift_motion, reset => reset, din => serial_input, dout => addend );
LABEL5: d_flip_flop port map ( clk => enable_shift_motion, reset => reset, din => carry_out, dout => carry_in );
LABEL6: full_adder port map ( a => augend, b => addend, c_in => carry_in, sum => sum, c_out => carry_out,
for_augend => signal_augend, for_addend => signal_addend, for_c_in => signal_c_in, for_c_out => signal_c_out, for_sum => signal_sum );
end Behavioral;
|
mit
|
47c936a01c366901704052c330bd2e19
| 0.643548 | 2.921084 | false | false | false | false |
rickyzhangNYC/Pipelined_Multimedia_Cell_Lite_Unit
|
cnth.vhd
| 1 | 2,171 |
-------------------------------------------------------------------------------
--
-- Title : cnth
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\cnth.vhd
-- Generated : Mon Dec 5 17:43:49 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {cnth} architecture {behavioral}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity cnth is
port(
rs1: in std_logic_vector(63 downto 0);
rd: out std_logic_vector (63 downto 0)
);
end cnth;
--}} End of automatically maintained section
architecture behavioral of cnth is
begin
process (rs1)
variable counter: integer range 0 to 16;
variable counter2: integer range 0 to 16;
variable counter3: integer range 0 to 16;
variable counter4: integer range 0 to 16;
begin
for i in 0 to 15 loop
if (rs1(i) = '1') then
counter := counter + 1;
end if;
end loop;
rd(15 downto 0) <= std_logic_vector(to_unsigned(counter,16));
counter := 0;
for i in 16 to 31 loop
if (rs1(i) = '1') then
counter2:= counter2 + 1;
end if;
end loop;
rd(31 downto 16) <= std_logic_vector(to_unsigned(counter2,16));
counter2 := 0;
for i in 32 to 47 loop
if (rs1(i) = '1') then
counter3:= counter3 + 1;
end if;
end loop;
rd(47 downto 32) <= std_logic_vector(to_unsigned(counter3,16));
counter3 := 0;
for i in 48 to 63 loop
if (rs1(i) = '1') then
counter4 := counter4 + 1;
end if;
end loop;
rd(63 downto 48) <= std_logic_vector(to_unsigned(counter4,16));
counter4 := 0;
end process;
end behavioral;
|
apache-2.0
|
2399fe30a0322230aa01bbb69db5fc33
| 0.501152 | 3.518639 | false | false | false | false |
Digilent/vivado-library
|
ip/dvi2rgb/src/TMDS_Decoder.vhd
| 1 | 10,949 |
-------------------------------------------------------------------------------
--
-- File: TMDS_Decoder.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module connects to one TMDS data channel and decodes TMDS data
-- according to DVI specifications. It phase aligns the data channel,
-- deserializes the stream, eliminates skew between data channels and decodes
-- data in the end.
-- sDataIn_p/n -> buffer -> de-serialize -> channel de-skew -> decode -> pData
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TMDS_Decoder is
Generic (
kCtlTknCount : natural := 128; --how many subsequent control tokens make a valid blank detection
kTimeoutMs : natural := 50; --what is the maximum time interval for a blank to be detected
kRefClkFrqMHz : natural := 200; --what is the RefClk frequency
kIDLY_TapValuePs : natural := 78; --delay in ps per tap
kIDLY_TapWidth : natural := 5); --number of bits for IDELAYE2 tap counter
Port (
PixelClk : in std_logic; --Recovered TMDS clock x1 (CLKDIV)
SerialClk : in std_logic; --Recovered TMDS clock x5 (CLK)
RefClk : std_logic; --200 MHz reference clock
aRst : in std_logic; --asynchronous reset; must be reset when PixelClk/SerialClk is not within spec
--Encoded serial data
sDataIn_p : in std_logic; --TMDS data channel positive
sDataIn_n : in std_logic; --TMDS data channel negative
--Decoded parallel data
pDataIn : out std_logic_vector(7 downto 0);
pC0 : out std_logic;
pC1 : out std_logic;
pVde : out std_logic;
-- Channel bonding (three data channels in total)
pOtherChVld : in std_logic_vector(1 downto 0);
pOtherChRdy : in std_logic_vector(1 downto 0);
pMeVld : out std_logic;
pMeRdy : out std_logic;
--Status and debug
pRst : in std_logic; -- Synchronous reset to restart lock procedure
dbg_pAlignErr : out std_logic;
dbg_pEyeSize : out STD_LOGIC_VECTOR(kIDLY_TapWidth-1 downto 0);
dbg_pBitslip : out std_logic
);
end TMDS_Decoder;
architecture Behavioral of TMDS_Decoder is
constant kBitslipDelay : natural := 3; --three-period delay after bitslip
signal pAlignRst, pLockLostRst_n : std_logic;
signal pBitslipCnt : natural range 0 to kBitslipDelay - 1 := kBitslipDelay - 1;
signal pDataIn8b : std_logic_vector(7 downto 0);
signal pDataInBnd : std_logic_vector(9 downto 0);
signal pDataInRaw : std_logic_vector(9 downto 0);
signal pMeRdy_int, pAligned, pAlignErr_int, pAlignErr_q, pBitslip : std_logic;
signal pIDLY_LD, pIDLY_CE, pIDLY_INC : std_logic;
signal pIDLY_CNT : std_logic_vector(kIDLY_TapWidth-1 downto 0);
-- Timeout Counter End
constant kTimeoutEnd : natural := kTimeoutMs * 1000 * kRefClkFrqMHz;
signal rTimeoutCnt : natural range 0 to kTimeoutEnd-1;
signal pTimeoutRst, pTimeoutOvf, rTimeoutRst, rTimeoutOvf : std_logic;
begin
dbg_pAlignErr <= pAlignErr_int;
dbg_pBitslip <= pBitslip;
-- Deserialization block
InputSERDES_X: entity work.InputSERDES
generic map (
kIDLY_TapWidth => kIDLY_TapWidth,
kParallelWidth => 10 -- TMDS uses 1:10 serialization
)
port map (
PixelClk => PixelClk,
SerialClk => SerialClk,
sDataIn_p => sDataIn_p,
sDataIn_n => sDataIn_n,
--Encoded parallel data (raw)
pDataIn => pDataInRaw,
--Control for phase alignment
pBitslip => pBitslip,
pIDLY_LD => pIDLY_LD,
pIDLY_CE => pIDLY_CE,
pIDLY_INC => pIDLY_INC,
pIDLY_CNT => pIDLY_CNT,
aRst => aRst
);
-- reset min two period (ISERDESE2 requirement)
-- de-assert synchronously with CLKDIV, min two period (ISERDESE2 requirement)
--The timeout counter runs on RefClk, because it's a fixed frequency we can measure timeout
--independently of the TMDS Clk
--The xTimeoutRst and xTimeoutOvf signals need to be synchronized back-and-forth
TimeoutCounter: process(RefClk)
begin
if Rising_Edge(RefClk) then
if (rTimeoutRst = '1') then
rTimeoutCnt <= 0;
elsif (rTimeoutOvf = '0') then
rTimeoutCnt <= rTimeoutCnt + 1;
end if;
end if;
end process TimeoutCounter;
rTimeoutOvf <= '0' when rTimeoutCnt /= kTimeoutEnd - 1 else
'1';
SyncBaseOvf: entity work.SyncBase
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => aRst,
InClk => RefClk,
iIn => rTimeoutOvf,
OutClk => PixelClk,
oOut => pTimeoutOvf);
SyncBaseRst: entity work.SyncBase
generic map (
kResetTo => '1',
kStages => 2) --use double FF synchronizer
port map (
aReset => aRst,
InClk => PixelClk,
iIn => pTimeoutRst,
OutClk => RefClk,
oOut => rTimeoutRst);
-- Phase alignment controller to lock onto data stream
PhaseAlignX: entity work.PhaseAlign
generic map (
kUseFastAlgorithm => false,
kCtlTknCount => kCtlTknCount,
kIDLY_TapValuePs => kIDLY_TapValuePs,
kIDLY_TapWidth => kIDLY_TapWidth
)
port map (
pRst => pAlignRst,
PixelClk => PixelClk,
pTimeoutOvf => pTimeoutOvf,
pTimeoutRst => pTimeoutRst,
pData => pDataInRaw,
pIDLY_CE => pIDLY_CE,
pIDLY_INC => pIDLY_INC,
pIDLY_CNT => pIDLY_CNT,
pIDLY_LD => pIDLY_LD,
pAligned => pAligned,
pError => pAlignErr_int,
pEyeSize => dbg_pEyeSize);
pMeVld <= pAligned;
-- Bitslip when phase alignment exhausted the whole tap range and still no lock
Bitslip: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
pAlignErr_q <= pAlignErr_int;
pBitslip <= not pAlignErr_q and pAlignErr_int; -- single pulse bitslip on failed alignment attempt
end if;
end process Bitslip;
ResetAlignment: process(PixelClk, aRst)
begin
if (aRst = '1') then
pAlignRst <= '1';
elsif Rising_Edge(PixelClk) then
if (pRst = '1' or pBitslip = '1') then
pAlignRst <= '1';
elsif (pBitslipCnt = 0) then
pAlignRst <= '0';
end if;
end if;
end process ResetAlignment;
-- Reset phase aligment module after bitslip + 3 CLKDIV cycles (ISERDESE2 requirement)
BitslipDelay: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pBitslip = '1') then
pBitslipCnt <= kBitslipDelay - 1;
elsif (pBitslipCnt /= 0) then
pBitslipCnt <= pBitslipCnt - 1;
end if;
end if;
end process BitslipDelay;
-- Channel de-skew (bonding)
ChannelBondX: entity work.ChannelBond
port map (
PixelClk => PixelClk,
pDataInRaw => pDataInRaw,
pMeVld => pAligned,
pOtherChVld => pOtherChVld,
pOtherChRdy => pOtherChRdy,
pDataInBnd => pDataInBnd,
pMeRdy => pMeRdy_int);
pMeRdy <= pMeRdy_int;
-- Below performs the 10B-8B decoding function
-- DVI Specification: Section 3.3.3, Figure 3-6, page 31.
pDataIn8b <= pDataInBnd(7 downto 0) when pDataInBnd(9) = '0' else
not pDataInBnd(7 downto 0);
TMDS_Decode: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pMeRdy_int = '1' and pOtherChRdy = "11") then
pDataIn <= x"00"; --added for VGA-compatibility (blank pixel needed during blanking)
case (pDataInBnd) is
--Control tokens decode straight to C0, C1 values
when kCtlTkn0 =>
pC0 <= '0';
pC1 <= '0';
pVde <= '0';
when kCtlTkn1 =>
pC0 <= '1';
pC1 <= '0';
pVde <= '0';
when kCtlTkn2 =>
pC0 <= '0';
pC1 <= '1';
pVde <= '0';
when kCtlTkn3 =>
pC0 <= '1';
pC1 <= '1';
pVde <= '0';
--If not control token, it's encoded data
when others =>
pVde <= '1';
pDataIn(0) <= pDataIn8b(0);
for iBit in 1 to 7 loop
if (pDataInBnd(8) = '1') then
pDataIn(iBit) <= pDataIn8b(iBit) xor pDataIn8b(iBit-1);
else
pDataIn(iBit) <= pDataIn8b(iBit) xnor pDataIn8b(iBit-1);
end if;
end loop;
end case;
else --if we are not aligned on all channels, gate outputs
pC0 <= '0';
pC1 <= '0';
pVde <= '0';
pDataIn <= x"00";
end if;
end if;
end process;
end Behavioral;
|
mit
|
903527c730e305102c02e794fb1a782b
| 0.622157 | 4.370858 | false | false | false | false |
igormacedo/vhdlstudy
|
simpleshifter/shifter.vhdl
| 1 | 587 |
library ieee;
use ieee.std_logic_1164.all;
entity shifter is
port( serial_in, cp : in std_logic;
q0 : out std_logic);
end entity;
architecture arc of shifter is
signal aux3, aux2, aux1 : std_logic;
component dflipflop
port( d, clk : in std_logic;
q : out std_logic );
end component;
begin
ff3: dflipflop port map (d=>serial_in, clk=>cp, q=> aux3);
ff2: dflipflop port map (d=>aux3, clk=>cp, q=> aux2);
ff1: dflipflop port map (d=>aux2, clk=>cp, q=> aux1);
ff0: dflipflop port map (d=>aux1, clk=>cp, q=> q0);
end architecture;
|
mit
|
a38b39b0dbd15fc7ac92b013d17d8e0b
| 0.620102 | 2.935 | false | false | false | false |
mtaygur/vhdl-alu-averagefilter-prng
|
alu.vhd
| 1 | 4,319 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
entity alu is
generic (WIDTH: integer := 8);
port (a,b: in std_logic_vector(WIDTH-1 downto 0); --Inputs
opsel: in std_logic_vector(3 downto 0):="0000"; --Operation selection bits
oflw: out std_logic; --Overflow flag
clk: in std_logic; --Clock input
Ylow: out std_logic_vector(WIDTH-1 downto 0); --Low 8-bit of output
Yhigh: out std_logic_vector(WIDTH-1 downto 0)); --High 8-bit of output
end alu;
architecture Behavioral of alu is
signal Ytemp: std_logic_vector(2*WIDTH-1 downto 0); --Temporary register for output
signal div_res:std_logic:='0'; --Division reset flag
signal a_prev: std_logic_vector(WIDTH-1 downto 0); --Previous value of input A
signal b_prev: std_logic_vector(WIDTH-1 downto 0); --Previous value of input B
signal div_res_clk: integer:=0; --Clock counter for division reset
signal clk_cnt:integer :=0; --Global clock counter
signal div:integer range 0 to 2**WIDTH-1 :=0; --Quotient of division
signal remn:integer range 0 to 2**WIDTH-1:=0; --Remainder of division
begin
Ytemp <= std_logic_vector(to_unsigned(to_integer(unsigned(a))+to_integer(unsigned(b)),Ytemp'length)) when opsel="0000" else --Addition
std_logic_vector(to_unsigned(to_integer(unsigned(a))-to_integer(unsigned(b)),Ytemp'length)) when opsel="0001" else --Subtraction
std_logic_vector(to_unsigned(to_integer(unsigned(a))*to_integer(unsigned(b)),Ytemp'length)) when opsel="0010" else --Multiplication
std_logic_vector(to_unsigned(remn,WIDTH)) & std_logic_vector(to_unsigned(div,WIDTH)) when opsel="0011" else --Division
std_logic_vector(to_unsigned(0,Ytemp'length/2)) & (a and b) when opsel="0100" else --AND
std_logic_vector(to_unsigned(0,Ytemp'length/2)) & (a or b) when opsel="0101" else --OR
std_logic_vector(to_unsigned(0,Ytemp'length/2)) & (a xor b) when opsel="0110" else --XOR
std_logic_vector(to_unsigned(0,Ytemp'length/2)) & (not a) when opsel="0111" else --NOT A
std_logic_vector(to_unsigned(0,Ytemp'length/2)) & a(WIDTH-2 downto 0) & '0' when opsel="1000"else --shift left
std_logic_vector(to_unsigned(0,Ytemp'length/2)) & '0' & a(WIDTH-1 downto 1) when opsel="1001"else --shift right
std_logic_vector(to_unsigned(0,Ytemp'length/2)) & a(WIDTH-2 downto 0) & a(WIDTH-1) when opsel="1010"else --rotate left
std_logic_vector(to_unsigned(0,Ytemp'length/2)) & a(0) & a(WIDTH-1 downto 1) when opsel="1011" else --rotate right
std_logic_vector(to_unsigned(0,Ytemp'length-2)) & '0' & '1' when opsel="1100" and (a=b) else --A=B
std_logic_vector(to_unsigned(0,Ytemp'length-2)) & '1' & '0' when opsel="1100" and (a>b) else --A>B
std_logic_vector(to_unsigned(0,Ytemp'length-2)) & '1' & '1' when opsel="1100" and (a<b) else --A<B
std_logic_vector(to_unsigned(0,Ytemp'length)); --Idle output
oflw <= '1' when opsel="0000" and Ytemp(2*WIDTH-1 downto WIDTH)>std_logic_vector(to_unsigned(0,Ytemp'length/2)) else --Addition carry
'1' when opsel="0001" and b>a else --Negative subtraction
'1' when opsel="0010" and to_unsigned(to_integer(unsigned(a))*to_integer(unsigned(b)),Ytemp'length)>2**WIDTH-1 else --Multiplication overflows 8 bits
'1' when opsel="0011" and remn>0 else --Remainder of division is not zero
'1' when opsel="1000" and a(WIDTH-1)='1' else --Shift left, MSB of A is 1
'1' when opsel="1001" and a(0)='1' else --Shift right, LSB of A is 1
'0';
process(clk,div_res)
begin
if div_res='1' then --If division reset flag is set
remn<=to_integer(unsigned(a)); --Reset division variables
div<=0;
elsif rising_edge(clk) then
if remn>=to_integer(unsigned(b)) and div_res='0' then --Perform division at each clock
remn<=remn-to_integer(unsigned(b));
div<=div+1;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
clk_cnt<=clk_cnt+1; --Global clock counter
a_prev<=a; --Monitor A and B at each clock
b_prev<=b;
if div_res='1' and abs(div_res_clk-clk_cnt)>5 then --If division set is active for 5 cycles, set to low
div_res<='0';
div_res_clk<=0;
end if;
if (a_prev/=a or b_prev/=b) and div_res='0' then --If A or B or both has changed, division reset flag is set
div_res<='1';
div_res_clk<=clk_cnt;
end if;
end if;
end process;
Ylow <= Ytemp(WIDTH-1 downto 0); --Outputs are transmitted
Yhigh <= Ytemp(2*WIDTH-1 downto WIDTH);
end Behavioral;
|
gpl-2.0
|
64b0abecad1b4b3308ab7de1775381cf
| 0.698541 | 2.900604 | false | false | false | false |
Digilent/vivado-library
|
ip/usb2device_v1_0/src/FIFO.vhd
| 2 | 5,097 |
-------------------------------------------------------------------------------
--
-- File: FIFO.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- RX FIFO instantiation
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FIFO is
generic (
NUM_TX_FIFO : integer := 1
);
PORT (
resetn : IN STD_LOGIC;
rx_fifo_s_aresetn : IN STD_LOGIC;
rx_fifo_m_aclk : IN STD_LOGIC;
rx_fifo_s_aclk : IN STD_LOGIC;
rx_fifo_s_axis_tvalid : IN STD_LOGIC;
rx_fifo_s_axis_tready : OUT STD_LOGIC;
rx_fifo_s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
rx_fifo_s_axis_tkeep : IN std_logic_vector (3 downto 0);
rx_fifo_s_axis_tlast : IN STD_LOGIC;
rx_fifo_s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rx_fifo_m_axis_tvalid : OUT STD_LOGIC;
rx_fifo_m_axis_tready : IN STD_LOGIC;
rx_fifo_m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rx_fifo_m_axis_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rx_fifo_m_axis_tlast : OUT STD_LOGIC;
rx_fifo_m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rx_fifo_axis_overflow : OUT STD_LOGIC;
rx_fifo_axis_underflow : OUT STD_LOGIC
);
end FIFO;
architecture Behavioral of FIFO is
COMPONENT fifo_generator_0
PORT (
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC
);
END COMPONENT;
begin
RX_FIFO : fifo_generator_0
PORT MAP (
m_aclk => rx_fifo_m_aclk,
s_aclk => rx_fifo_s_aclk,
s_aresetn => rx_fifo_s_aresetn,
s_axis_tvalid => rx_fifo_s_axis_tvalid,
s_axis_tready => rx_fifo_s_axis_tready,
s_axis_tdata => rx_fifo_s_axis_tdata,
s_axis_tkeep => rx_fifo_s_axis_tkeep,
s_axis_tlast => rx_fifo_s_axis_tlast,
s_axis_tuser => rx_fifo_s_axis_tuser,
m_axis_tvalid => rx_fifo_m_axis_tvalid,
m_axis_tready => rx_fifo_m_axis_tready,
m_axis_tdata => rx_fifo_m_axis_tdata,
m_axis_tkeep => rx_fifo_m_axis_tkeep,
m_axis_tlast => rx_fifo_m_axis_tlast,
m_axis_tuser => rx_fifo_m_axis_tuser,
axis_overflow => rx_fifo_axis_overflow,
axis_underflow => rx_fifo_axis_underflow
);
end Behavioral;
|
mit
|
a62cf8e384b365e2f1a9c47d27011ceb
| 0.65568 | 3.576842 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_contrast_stretch_1_0/hdl/vhdl/hls_contrast_stretch.vhd
| 1 | 66,954 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hls_contrast_stretch is
generic (
C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32 );
port (
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
stream_in_TDATA : IN STD_LOGIC_VECTOR (23 downto 0);
stream_in_TKEEP : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TSTRB : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TID : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
stream_out_TDATA : OUT STD_LOGIC_VECTOR (23 downto 0);
stream_out_TKEEP : OUT STD_LOGIC_VECTOR (2 downto 0);
stream_out_TSTRB : OUT STD_LOGIC_VECTOR (2 downto 0);
stream_out_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_in_TVALID : IN STD_LOGIC;
stream_in_TREADY : OUT STD_LOGIC;
stream_out_TVALID : OUT STD_LOGIC;
stream_out_TREADY : IN STD_LOGIC );
end;
architecture behav of hls_contrast_stretch is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"hls_contrast_stretch,hls_ip_2017_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg400-1,HLS_INPUT_CLOCK=6.670000,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=6.380000,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=0,HLS_SYN_DSP=9,HLS_SYN_FF=3094,HLS_SYN_LUT=4583}";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant C_S_AXI_WSTRB_WIDTH : INTEGER range 63 downto 0 := 4;
constant C_S_AXI_ADDR_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_lv24_0 : STD_LOGIC_VECTOR (23 downto 0) := "000000000000000000000000";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_logic_0 : STD_LOGIC := '0';
signal ap_rst_n_inv : STD_LOGIC;
signal height : STD_LOGIC_VECTOR (15 downto 0);
signal width : STD_LOGIC_VECTOR (15 downto 0);
signal min : STD_LOGIC_VECTOR (7 downto 0);
signal max : STD_LOGIC_VECTOR (7 downto 0);
signal Block_Mat_exit1573_p_U0_ap_start : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_start_full_n : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_ap_done : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_ap_continue : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_ap_idle : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_ap_ready : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_start_out : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_start_write : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_min_out_din : STD_LOGIC_VECTOR (7 downto 0);
signal Block_Mat_exit1573_p_U0_min_out_write : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_img0_rows_V_out_din : STD_LOGIC_VECTOR (15 downto 0);
signal Block_Mat_exit1573_p_U0_img0_rows_V_out_write : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_img0_cols_V_out_din : STD_LOGIC_VECTOR (15 downto 0);
signal Block_Mat_exit1573_p_U0_img0_cols_V_out_write : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_img2_rows_V_out_din : STD_LOGIC_VECTOR (15 downto 0);
signal Block_Mat_exit1573_p_U0_img2_rows_V_out_write : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_img2_cols_V_out_din : STD_LOGIC_VECTOR (15 downto 0);
signal Block_Mat_exit1573_p_U0_img2_cols_V_out_write : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_img3_rows_V_out_din : STD_LOGIC_VECTOR (15 downto 0);
signal Block_Mat_exit1573_p_U0_img3_rows_V_out_write : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_img3_cols_V_out_din : STD_LOGIC_VECTOR (15 downto 0);
signal Block_Mat_exit1573_p_U0_img3_cols_V_out_write : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_p_cols_assign_cast_out_out_din : STD_LOGIC_VECTOR (11 downto 0);
signal Block_Mat_exit1573_p_U0_p_cols_assign_cast_out_out_write : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_p_rows_assign_cast_out_out_din : STD_LOGIC_VECTOR (11 downto 0);
signal Block_Mat_exit1573_p_U0_p_rows_assign_cast_out_out_write : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_tmp_3_cast_out_out_din : STD_LOGIC_VECTOR (7 downto 0);
signal Block_Mat_exit1573_p_U0_tmp_3_cast_out_out_write : STD_LOGIC;
signal Block_Mat_exit1573_p_U0_max_out_din : STD_LOGIC_VECTOR (7 downto 0);
signal Block_Mat_exit1573_p_U0_max_out_write : STD_LOGIC;
signal AXIvideo2Mat_U0_ap_start : STD_LOGIC;
signal AXIvideo2Mat_U0_ap_done : STD_LOGIC;
signal AXIvideo2Mat_U0_ap_continue : STD_LOGIC;
signal AXIvideo2Mat_U0_ap_idle : STD_LOGIC;
signal AXIvideo2Mat_U0_ap_ready : STD_LOGIC;
signal AXIvideo2Mat_U0_start_out : STD_LOGIC;
signal AXIvideo2Mat_U0_start_write : STD_LOGIC;
signal AXIvideo2Mat_U0_stream_in_TREADY : STD_LOGIC;
signal AXIvideo2Mat_U0_img_rows_V_read : STD_LOGIC;
signal AXIvideo2Mat_U0_img_cols_V_read : STD_LOGIC;
signal AXIvideo2Mat_U0_img_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal AXIvideo2Mat_U0_img_data_stream_0_V_write : STD_LOGIC;
signal AXIvideo2Mat_U0_img_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal AXIvideo2Mat_U0_img_data_stream_1_V_write : STD_LOGIC;
signal AXIvideo2Mat_U0_img_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal AXIvideo2Mat_U0_img_data_stream_2_V_write : STD_LOGIC;
signal AXIvideo2Mat_U0_img_rows_V_out_din : STD_LOGIC_VECTOR (15 downto 0);
signal AXIvideo2Mat_U0_img_rows_V_out_write : STD_LOGIC;
signal AXIvideo2Mat_U0_img_cols_V_out_din : STD_LOGIC_VECTOR (15 downto 0);
signal AXIvideo2Mat_U0_img_cols_V_out_write : STD_LOGIC;
signal CvtColor_1_U0_ap_start : STD_LOGIC;
signal CvtColor_1_U0_ap_done : STD_LOGIC;
signal CvtColor_1_U0_ap_continue : STD_LOGIC;
signal CvtColor_1_U0_ap_idle : STD_LOGIC;
signal CvtColor_1_U0_ap_ready : STD_LOGIC;
signal CvtColor_1_U0_p_src_rows_V_read : STD_LOGIC;
signal CvtColor_1_U0_p_src_cols_V_read : STD_LOGIC;
signal CvtColor_1_U0_p_src_data_stream_0_V_read : STD_LOGIC;
signal CvtColor_1_U0_p_src_data_stream_1_V_read : STD_LOGIC;
signal CvtColor_1_U0_p_src_data_stream_2_V_read : STD_LOGIC;
signal CvtColor_1_U0_p_dst_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal CvtColor_1_U0_p_dst_data_stream_0_V_write : STD_LOGIC;
signal CvtColor_1_U0_p_dst_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal CvtColor_1_U0_p_dst_data_stream_1_V_write : STD_LOGIC;
signal CvtColor_1_U0_p_dst_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal CvtColor_1_U0_p_dst_data_stream_2_V_write : STD_LOGIC;
signal Loop_loop_height_pro_U0_ap_start : STD_LOGIC;
signal Loop_loop_height_pro_U0_ap_done : STD_LOGIC;
signal Loop_loop_height_pro_U0_ap_continue : STD_LOGIC;
signal Loop_loop_height_pro_U0_ap_idle : STD_LOGIC;
signal Loop_loop_height_pro_U0_ap_ready : STD_LOGIC;
signal Loop_loop_height_pro_U0_max_read : STD_LOGIC;
signal Loop_loop_height_pro_U0_p_rows_assign_cast_loc_read : STD_LOGIC;
signal Loop_loop_height_pro_U0_p_cols_assign_cast_loc_read : STD_LOGIC;
signal Loop_loop_height_pro_U0_img2_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal Loop_loop_height_pro_U0_img2_data_stream_0_V_write : STD_LOGIC;
signal Loop_loop_height_pro_U0_img2_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal Loop_loop_height_pro_U0_img2_data_stream_1_V_write : STD_LOGIC;
signal Loop_loop_height_pro_U0_img2_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal Loop_loop_height_pro_U0_img2_data_stream_2_V_write : STD_LOGIC;
signal Loop_loop_height_pro_U0_img1_data_stream_0_V_read : STD_LOGIC;
signal Loop_loop_height_pro_U0_img1_data_stream_1_V_read : STD_LOGIC;
signal Loop_loop_height_pro_U0_img1_data_stream_2_V_read : STD_LOGIC;
signal Loop_loop_height_pro_U0_min_read : STD_LOGIC;
signal Loop_loop_height_pro_U0_tmp_3_cast_loc_read : STD_LOGIC;
signal CvtColor_U0_ap_start : STD_LOGIC;
signal CvtColor_U0_ap_done : STD_LOGIC;
signal CvtColor_U0_ap_continue : STD_LOGIC;
signal CvtColor_U0_ap_idle : STD_LOGIC;
signal CvtColor_U0_ap_ready : STD_LOGIC;
signal CvtColor_U0_p_src_rows_V_read : STD_LOGIC;
signal CvtColor_U0_p_src_cols_V_read : STD_LOGIC;
signal CvtColor_U0_p_src_data_stream_0_V_read : STD_LOGIC;
signal CvtColor_U0_p_src_data_stream_1_V_read : STD_LOGIC;
signal CvtColor_U0_p_src_data_stream_2_V_read : STD_LOGIC;
signal CvtColor_U0_p_dst_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal CvtColor_U0_p_dst_data_stream_0_V_write : STD_LOGIC;
signal CvtColor_U0_p_dst_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal CvtColor_U0_p_dst_data_stream_1_V_write : STD_LOGIC;
signal CvtColor_U0_p_dst_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal CvtColor_U0_p_dst_data_stream_2_V_write : STD_LOGIC;
signal Mat2AXIvideo_U0_ap_start : STD_LOGIC;
signal Mat2AXIvideo_U0_ap_done : STD_LOGIC;
signal Mat2AXIvideo_U0_ap_continue : STD_LOGIC;
signal Mat2AXIvideo_U0_ap_idle : STD_LOGIC;
signal Mat2AXIvideo_U0_ap_ready : STD_LOGIC;
signal Mat2AXIvideo_U0_img_rows_V_read : STD_LOGIC;
signal Mat2AXIvideo_U0_img_cols_V_read : STD_LOGIC;
signal Mat2AXIvideo_U0_img_data_stream_0_V_read : STD_LOGIC;
signal Mat2AXIvideo_U0_img_data_stream_1_V_read : STD_LOGIC;
signal Mat2AXIvideo_U0_img_data_stream_2_V_read : STD_LOGIC;
signal Mat2AXIvideo_U0_stream_out_TDATA : STD_LOGIC_VECTOR (23 downto 0);
signal Mat2AXIvideo_U0_stream_out_TVALID : STD_LOGIC;
signal Mat2AXIvideo_U0_stream_out_TKEEP : STD_LOGIC_VECTOR (2 downto 0);
signal Mat2AXIvideo_U0_stream_out_TSTRB : STD_LOGIC_VECTOR (2 downto 0);
signal Mat2AXIvideo_U0_stream_out_TUSER : STD_LOGIC_VECTOR (0 downto 0);
signal Mat2AXIvideo_U0_stream_out_TLAST : STD_LOGIC_VECTOR (0 downto 0);
signal Mat2AXIvideo_U0_stream_out_TID : STD_LOGIC_VECTOR (0 downto 0);
signal Mat2AXIvideo_U0_stream_out_TDEST : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sync_continue : STD_LOGIC;
signal min_c_full_n : STD_LOGIC;
signal min_c_dout : STD_LOGIC_VECTOR (7 downto 0);
signal min_c_empty_n : STD_LOGIC;
signal img0_rows_V_c_full_n : STD_LOGIC;
signal img0_rows_V_c_dout : STD_LOGIC_VECTOR (15 downto 0);
signal img0_rows_V_c_empty_n : STD_LOGIC;
signal img0_cols_V_c_full_n : STD_LOGIC;
signal img0_cols_V_c_dout : STD_LOGIC_VECTOR (15 downto 0);
signal img0_cols_V_c_empty_n : STD_LOGIC;
signal img2_rows_V_c_full_n : STD_LOGIC;
signal img2_rows_V_c_dout : STD_LOGIC_VECTOR (15 downto 0);
signal img2_rows_V_c_empty_n : STD_LOGIC;
signal img2_cols_V_c_full_n : STD_LOGIC;
signal img2_cols_V_c_dout : STD_LOGIC_VECTOR (15 downto 0);
signal img2_cols_V_c_empty_n : STD_LOGIC;
signal img3_rows_V_c_full_n : STD_LOGIC;
signal img3_rows_V_c_dout : STD_LOGIC_VECTOR (15 downto 0);
signal img3_rows_V_c_empty_n : STD_LOGIC;
signal img3_cols_V_c_full_n : STD_LOGIC;
signal img3_cols_V_c_dout : STD_LOGIC_VECTOR (15 downto 0);
signal img3_cols_V_c_empty_n : STD_LOGIC;
signal p_cols_assign_cast_lo_full_n : STD_LOGIC;
signal p_cols_assign_cast_lo_dout : STD_LOGIC_VECTOR (11 downto 0);
signal p_cols_assign_cast_lo_empty_n : STD_LOGIC;
signal p_rows_assign_cast_lo_full_n : STD_LOGIC;
signal p_rows_assign_cast_lo_dout : STD_LOGIC_VECTOR (11 downto 0);
signal p_rows_assign_cast_lo_empty_n : STD_LOGIC;
signal tmp_3_cast_loc_c_full_n : STD_LOGIC;
signal tmp_3_cast_loc_c_dout : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_3_cast_loc_c_empty_n : STD_LOGIC;
signal max_c_full_n : STD_LOGIC;
signal max_c_dout : STD_LOGIC_VECTOR (7 downto 0);
signal max_c_empty_n : STD_LOGIC;
signal img0_data_stream_0_s_full_n : STD_LOGIC;
signal img0_data_stream_0_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img0_data_stream_0_s_empty_n : STD_LOGIC;
signal img0_data_stream_1_s_full_n : STD_LOGIC;
signal img0_data_stream_1_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img0_data_stream_1_s_empty_n : STD_LOGIC;
signal img0_data_stream_2_s_full_n : STD_LOGIC;
signal img0_data_stream_2_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img0_data_stream_2_s_empty_n : STD_LOGIC;
signal img0_rows_V_c83_full_n : STD_LOGIC;
signal img0_rows_V_c83_dout : STD_LOGIC_VECTOR (15 downto 0);
signal img0_rows_V_c83_empty_n : STD_LOGIC;
signal img0_cols_V_c84_full_n : STD_LOGIC;
signal img0_cols_V_c84_dout : STD_LOGIC_VECTOR (15 downto 0);
signal img0_cols_V_c84_empty_n : STD_LOGIC;
signal img1_data_stream_0_s_full_n : STD_LOGIC;
signal img1_data_stream_0_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img1_data_stream_0_s_empty_n : STD_LOGIC;
signal img1_data_stream_1_s_full_n : STD_LOGIC;
signal img1_data_stream_1_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img1_data_stream_1_s_empty_n : STD_LOGIC;
signal img1_data_stream_2_s_full_n : STD_LOGIC;
signal img1_data_stream_2_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img1_data_stream_2_s_empty_n : STD_LOGIC;
signal img2_data_stream_0_s_full_n : STD_LOGIC;
signal img2_data_stream_0_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img2_data_stream_0_s_empty_n : STD_LOGIC;
signal img2_data_stream_1_s_full_n : STD_LOGIC;
signal img2_data_stream_1_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img2_data_stream_1_s_empty_n : STD_LOGIC;
signal img2_data_stream_2_s_full_n : STD_LOGIC;
signal img2_data_stream_2_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img2_data_stream_2_s_empty_n : STD_LOGIC;
signal img3_data_stream_0_s_full_n : STD_LOGIC;
signal img3_data_stream_0_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img3_data_stream_0_s_empty_n : STD_LOGIC;
signal img3_data_stream_1_s_full_n : STD_LOGIC;
signal img3_data_stream_1_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img3_data_stream_1_s_empty_n : STD_LOGIC;
signal img3_data_stream_2_s_full_n : STD_LOGIC;
signal img3_data_stream_2_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img3_data_stream_2_s_empty_n : STD_LOGIC;
signal start_for_Loop_loop_height_pro_U0_din : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_Loop_loop_height_pro_U0_full_n : STD_LOGIC;
signal start_for_Loop_loop_height_pro_U0_dout : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_Loop_loop_height_pro_U0_empty_n : STD_LOGIC;
signal start_for_CvtColor_U0_din : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_CvtColor_U0_full_n : STD_LOGIC;
signal start_for_CvtColor_U0_dout : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_CvtColor_U0_empty_n : STD_LOGIC;
signal start_for_Mat2AXIvideo_U0_din : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_Mat2AXIvideo_U0_full_n : STD_LOGIC;
signal start_for_Mat2AXIvideo_U0_dout : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_Mat2AXIvideo_U0_empty_n : STD_LOGIC;
signal start_for_CvtColor_1_U0_din : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_CvtColor_1_U0_full_n : STD_LOGIC;
signal start_for_CvtColor_1_U0_dout : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_CvtColor_1_U0_empty_n : STD_LOGIC;
signal CvtColor_1_U0_start_full_n : STD_LOGIC;
signal CvtColor_1_U0_start_write : STD_LOGIC;
signal Loop_loop_height_pro_U0_start_full_n : STD_LOGIC;
signal Loop_loop_height_pro_U0_start_write : STD_LOGIC;
signal CvtColor_U0_start_full_n : STD_LOGIC;
signal CvtColor_U0_start_write : STD_LOGIC;
signal Mat2AXIvideo_U0_start_full_n : STD_LOGIC;
signal Mat2AXIvideo_U0_start_write : STD_LOGIC;
component Block_Mat_exit1573_p IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
start_full_n : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
start_out : OUT STD_LOGIC;
start_write : OUT STD_LOGIC;
height : IN STD_LOGIC_VECTOR (15 downto 0);
width : IN STD_LOGIC_VECTOR (15 downto 0);
min : IN STD_LOGIC_VECTOR (7 downto 0);
max : IN STD_LOGIC_VECTOR (7 downto 0);
min_out_din : OUT STD_LOGIC_VECTOR (7 downto 0);
min_out_full_n : IN STD_LOGIC;
min_out_write : OUT STD_LOGIC;
img0_rows_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img0_rows_V_out_full_n : IN STD_LOGIC;
img0_rows_V_out_write : OUT STD_LOGIC;
img0_cols_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img0_cols_V_out_full_n : IN STD_LOGIC;
img0_cols_V_out_write : OUT STD_LOGIC;
img2_rows_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img2_rows_V_out_full_n : IN STD_LOGIC;
img2_rows_V_out_write : OUT STD_LOGIC;
img2_cols_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img2_cols_V_out_full_n : IN STD_LOGIC;
img2_cols_V_out_write : OUT STD_LOGIC;
img3_rows_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img3_rows_V_out_full_n : IN STD_LOGIC;
img3_rows_V_out_write : OUT STD_LOGIC;
img3_cols_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img3_cols_V_out_full_n : IN STD_LOGIC;
img3_cols_V_out_write : OUT STD_LOGIC;
p_cols_assign_cast_out_out_din : OUT STD_LOGIC_VECTOR (11 downto 0);
p_cols_assign_cast_out_out_full_n : IN STD_LOGIC;
p_cols_assign_cast_out_out_write : OUT STD_LOGIC;
p_rows_assign_cast_out_out_din : OUT STD_LOGIC_VECTOR (11 downto 0);
p_rows_assign_cast_out_out_full_n : IN STD_LOGIC;
p_rows_assign_cast_out_out_write : OUT STD_LOGIC;
tmp_3_cast_out_out_din : OUT STD_LOGIC_VECTOR (7 downto 0);
tmp_3_cast_out_out_full_n : IN STD_LOGIC;
tmp_3_cast_out_out_write : OUT STD_LOGIC;
max_out_din : OUT STD_LOGIC_VECTOR (7 downto 0);
max_out_full_n : IN STD_LOGIC;
max_out_write : OUT STD_LOGIC );
end component;
component AXIvideo2Mat IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
start_full_n : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
start_out : OUT STD_LOGIC;
start_write : OUT STD_LOGIC;
stream_in_TDATA : IN STD_LOGIC_VECTOR (23 downto 0);
stream_in_TVALID : IN STD_LOGIC;
stream_in_TREADY : OUT STD_LOGIC;
stream_in_TKEEP : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TSTRB : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TID : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
img_rows_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
img_rows_V_empty_n : IN STD_LOGIC;
img_rows_V_read : OUT STD_LOGIC;
img_cols_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
img_cols_V_empty_n : IN STD_LOGIC;
img_cols_V_read : OUT STD_LOGIC;
img_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_full_n : IN STD_LOGIC;
img_data_stream_0_V_write : OUT STD_LOGIC;
img_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_full_n : IN STD_LOGIC;
img_data_stream_1_V_write : OUT STD_LOGIC;
img_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_full_n : IN STD_LOGIC;
img_data_stream_2_V_write : OUT STD_LOGIC;
img_rows_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img_rows_V_out_full_n : IN STD_LOGIC;
img_rows_V_out_write : OUT STD_LOGIC;
img_cols_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img_cols_V_out_full_n : IN STD_LOGIC;
img_cols_V_out_write : OUT STD_LOGIC );
end component;
component CvtColor_1 IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_src_rows_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
p_src_rows_V_empty_n : IN STD_LOGIC;
p_src_rows_V_read : OUT STD_LOGIC;
p_src_cols_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
p_src_cols_V_empty_n : IN STD_LOGIC;
p_src_cols_V_read : OUT STD_LOGIC;
p_src_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_0_V_empty_n : IN STD_LOGIC;
p_src_data_stream_0_V_read : OUT STD_LOGIC;
p_src_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_1_V_empty_n : IN STD_LOGIC;
p_src_data_stream_1_V_read : OUT STD_LOGIC;
p_src_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_2_V_empty_n : IN STD_LOGIC;
p_src_data_stream_2_V_read : OUT STD_LOGIC;
p_dst_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_0_V_full_n : IN STD_LOGIC;
p_dst_data_stream_0_V_write : OUT STD_LOGIC;
p_dst_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_1_V_full_n : IN STD_LOGIC;
p_dst_data_stream_1_V_write : OUT STD_LOGIC;
p_dst_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_2_V_full_n : IN STD_LOGIC;
p_dst_data_stream_2_V_write : OUT STD_LOGIC );
end component;
component Loop_loop_height_pro IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
max_dout : IN STD_LOGIC_VECTOR (7 downto 0);
max_empty_n : IN STD_LOGIC;
max_read : OUT STD_LOGIC;
p_rows_assign_cast_loc_dout : IN STD_LOGIC_VECTOR (11 downto 0);
p_rows_assign_cast_loc_empty_n : IN STD_LOGIC;
p_rows_assign_cast_loc_read : OUT STD_LOGIC;
p_cols_assign_cast_loc_dout : IN STD_LOGIC_VECTOR (11 downto 0);
p_cols_assign_cast_loc_empty_n : IN STD_LOGIC;
p_cols_assign_cast_loc_read : OUT STD_LOGIC;
img2_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img2_data_stream_0_V_full_n : IN STD_LOGIC;
img2_data_stream_0_V_write : OUT STD_LOGIC;
img2_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img2_data_stream_1_V_full_n : IN STD_LOGIC;
img2_data_stream_1_V_write : OUT STD_LOGIC;
img2_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img2_data_stream_2_V_full_n : IN STD_LOGIC;
img2_data_stream_2_V_write : OUT STD_LOGIC;
img1_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img1_data_stream_0_V_empty_n : IN STD_LOGIC;
img1_data_stream_0_V_read : OUT STD_LOGIC;
img1_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img1_data_stream_1_V_empty_n : IN STD_LOGIC;
img1_data_stream_1_V_read : OUT STD_LOGIC;
img1_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img1_data_stream_2_V_empty_n : IN STD_LOGIC;
img1_data_stream_2_V_read : OUT STD_LOGIC;
min_dout : IN STD_LOGIC_VECTOR (7 downto 0);
min_empty_n : IN STD_LOGIC;
min_read : OUT STD_LOGIC;
tmp_3_cast_loc_dout : IN STD_LOGIC_VECTOR (7 downto 0);
tmp_3_cast_loc_empty_n : IN STD_LOGIC;
tmp_3_cast_loc_read : OUT STD_LOGIC );
end component;
component CvtColor IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_src_rows_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
p_src_rows_V_empty_n : IN STD_LOGIC;
p_src_rows_V_read : OUT STD_LOGIC;
p_src_cols_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
p_src_cols_V_empty_n : IN STD_LOGIC;
p_src_cols_V_read : OUT STD_LOGIC;
p_src_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_0_V_empty_n : IN STD_LOGIC;
p_src_data_stream_0_V_read : OUT STD_LOGIC;
p_src_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_1_V_empty_n : IN STD_LOGIC;
p_src_data_stream_1_V_read : OUT STD_LOGIC;
p_src_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_2_V_empty_n : IN STD_LOGIC;
p_src_data_stream_2_V_read : OUT STD_LOGIC;
p_dst_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_0_V_full_n : IN STD_LOGIC;
p_dst_data_stream_0_V_write : OUT STD_LOGIC;
p_dst_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_1_V_full_n : IN STD_LOGIC;
p_dst_data_stream_1_V_write : OUT STD_LOGIC;
p_dst_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_2_V_full_n : IN STD_LOGIC;
p_dst_data_stream_2_V_write : OUT STD_LOGIC );
end component;
component Mat2AXIvideo IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
img_rows_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
img_rows_V_empty_n : IN STD_LOGIC;
img_rows_V_read : OUT STD_LOGIC;
img_cols_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
img_cols_V_empty_n : IN STD_LOGIC;
img_cols_V_read : OUT STD_LOGIC;
img_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_empty_n : IN STD_LOGIC;
img_data_stream_0_V_read : OUT STD_LOGIC;
img_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_empty_n : IN STD_LOGIC;
img_data_stream_1_V_read : OUT STD_LOGIC;
img_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_empty_n : IN STD_LOGIC;
img_data_stream_2_V_read : OUT STD_LOGIC;
stream_out_TDATA : OUT STD_LOGIC_VECTOR (23 downto 0);
stream_out_TVALID : OUT STD_LOGIC;
stream_out_TREADY : IN STD_LOGIC;
stream_out_TKEEP : OUT STD_LOGIC_VECTOR (2 downto 0);
stream_out_TSTRB : OUT STD_LOGIC_VECTOR (2 downto 0);
stream_out_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component fifo_w8_d3_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component fifo_w16_d1_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (15 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (15 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component fifo_w16_d4_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (15 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (15 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component fifo_w16_d5_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (15 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (15 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component fifo_w12_d3_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component fifo_w8_d1_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component start_for_Loop_lojbC IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (0 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (0 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component start_for_CvtColokbM IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (0 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (0 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component start_for_Mat2AXIlbW IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (0 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (0 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component start_for_CvtColomb6 IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (0 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (0 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component hls_contrast_stretch_AXILiteS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
height : OUT STD_LOGIC_VECTOR (15 downto 0);
width : OUT STD_LOGIC_VECTOR (15 downto 0);
min : OUT STD_LOGIC_VECTOR (7 downto 0);
max : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
begin
hls_contrast_stretch_AXILiteS_s_axi_U : component hls_contrast_stretch_AXILiteS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH)
port map (
AWVALID => s_axi_AXILiteS_AWVALID,
AWREADY => s_axi_AXILiteS_AWREADY,
AWADDR => s_axi_AXILiteS_AWADDR,
WVALID => s_axi_AXILiteS_WVALID,
WREADY => s_axi_AXILiteS_WREADY,
WDATA => s_axi_AXILiteS_WDATA,
WSTRB => s_axi_AXILiteS_WSTRB,
ARVALID => s_axi_AXILiteS_ARVALID,
ARREADY => s_axi_AXILiteS_ARREADY,
ARADDR => s_axi_AXILiteS_ARADDR,
RVALID => s_axi_AXILiteS_RVALID,
RREADY => s_axi_AXILiteS_RREADY,
RDATA => s_axi_AXILiteS_RDATA,
RRESP => s_axi_AXILiteS_RRESP,
BVALID => s_axi_AXILiteS_BVALID,
BREADY => s_axi_AXILiteS_BREADY,
BRESP => s_axi_AXILiteS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
height => height,
width => width,
min => min,
max => max);
Block_Mat_exit1573_p_U0 : component Block_Mat_exit1573_p
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => Block_Mat_exit1573_p_U0_ap_start,
start_full_n => Block_Mat_exit1573_p_U0_start_full_n,
ap_done => Block_Mat_exit1573_p_U0_ap_done,
ap_continue => Block_Mat_exit1573_p_U0_ap_continue,
ap_idle => Block_Mat_exit1573_p_U0_ap_idle,
ap_ready => Block_Mat_exit1573_p_U0_ap_ready,
start_out => Block_Mat_exit1573_p_U0_start_out,
start_write => Block_Mat_exit1573_p_U0_start_write,
height => height,
width => width,
min => min,
max => max,
min_out_din => Block_Mat_exit1573_p_U0_min_out_din,
min_out_full_n => min_c_full_n,
min_out_write => Block_Mat_exit1573_p_U0_min_out_write,
img0_rows_V_out_din => Block_Mat_exit1573_p_U0_img0_rows_V_out_din,
img0_rows_V_out_full_n => img0_rows_V_c_full_n,
img0_rows_V_out_write => Block_Mat_exit1573_p_U0_img0_rows_V_out_write,
img0_cols_V_out_din => Block_Mat_exit1573_p_U0_img0_cols_V_out_din,
img0_cols_V_out_full_n => img0_cols_V_c_full_n,
img0_cols_V_out_write => Block_Mat_exit1573_p_U0_img0_cols_V_out_write,
img2_rows_V_out_din => Block_Mat_exit1573_p_U0_img2_rows_V_out_din,
img2_rows_V_out_full_n => img2_rows_V_c_full_n,
img2_rows_V_out_write => Block_Mat_exit1573_p_U0_img2_rows_V_out_write,
img2_cols_V_out_din => Block_Mat_exit1573_p_U0_img2_cols_V_out_din,
img2_cols_V_out_full_n => img2_cols_V_c_full_n,
img2_cols_V_out_write => Block_Mat_exit1573_p_U0_img2_cols_V_out_write,
img3_rows_V_out_din => Block_Mat_exit1573_p_U0_img3_rows_V_out_din,
img3_rows_V_out_full_n => img3_rows_V_c_full_n,
img3_rows_V_out_write => Block_Mat_exit1573_p_U0_img3_rows_V_out_write,
img3_cols_V_out_din => Block_Mat_exit1573_p_U0_img3_cols_V_out_din,
img3_cols_V_out_full_n => img3_cols_V_c_full_n,
img3_cols_V_out_write => Block_Mat_exit1573_p_U0_img3_cols_V_out_write,
p_cols_assign_cast_out_out_din => Block_Mat_exit1573_p_U0_p_cols_assign_cast_out_out_din,
p_cols_assign_cast_out_out_full_n => p_cols_assign_cast_lo_full_n,
p_cols_assign_cast_out_out_write => Block_Mat_exit1573_p_U0_p_cols_assign_cast_out_out_write,
p_rows_assign_cast_out_out_din => Block_Mat_exit1573_p_U0_p_rows_assign_cast_out_out_din,
p_rows_assign_cast_out_out_full_n => p_rows_assign_cast_lo_full_n,
p_rows_assign_cast_out_out_write => Block_Mat_exit1573_p_U0_p_rows_assign_cast_out_out_write,
tmp_3_cast_out_out_din => Block_Mat_exit1573_p_U0_tmp_3_cast_out_out_din,
tmp_3_cast_out_out_full_n => tmp_3_cast_loc_c_full_n,
tmp_3_cast_out_out_write => Block_Mat_exit1573_p_U0_tmp_3_cast_out_out_write,
max_out_din => Block_Mat_exit1573_p_U0_max_out_din,
max_out_full_n => max_c_full_n,
max_out_write => Block_Mat_exit1573_p_U0_max_out_write);
AXIvideo2Mat_U0 : component AXIvideo2Mat
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => AXIvideo2Mat_U0_ap_start,
start_full_n => start_for_CvtColor_1_U0_full_n,
ap_done => AXIvideo2Mat_U0_ap_done,
ap_continue => AXIvideo2Mat_U0_ap_continue,
ap_idle => AXIvideo2Mat_U0_ap_idle,
ap_ready => AXIvideo2Mat_U0_ap_ready,
start_out => AXIvideo2Mat_U0_start_out,
start_write => AXIvideo2Mat_U0_start_write,
stream_in_TDATA => stream_in_TDATA,
stream_in_TVALID => stream_in_TVALID,
stream_in_TREADY => AXIvideo2Mat_U0_stream_in_TREADY,
stream_in_TKEEP => stream_in_TKEEP,
stream_in_TSTRB => stream_in_TSTRB,
stream_in_TUSER => stream_in_TUSER,
stream_in_TLAST => stream_in_TLAST,
stream_in_TID => stream_in_TID,
stream_in_TDEST => stream_in_TDEST,
img_rows_V_dout => img0_rows_V_c_dout,
img_rows_V_empty_n => img0_rows_V_c_empty_n,
img_rows_V_read => AXIvideo2Mat_U0_img_rows_V_read,
img_cols_V_dout => img0_cols_V_c_dout,
img_cols_V_empty_n => img0_cols_V_c_empty_n,
img_cols_V_read => AXIvideo2Mat_U0_img_cols_V_read,
img_data_stream_0_V_din => AXIvideo2Mat_U0_img_data_stream_0_V_din,
img_data_stream_0_V_full_n => img0_data_stream_0_s_full_n,
img_data_stream_0_V_write => AXIvideo2Mat_U0_img_data_stream_0_V_write,
img_data_stream_1_V_din => AXIvideo2Mat_U0_img_data_stream_1_V_din,
img_data_stream_1_V_full_n => img0_data_stream_1_s_full_n,
img_data_stream_1_V_write => AXIvideo2Mat_U0_img_data_stream_1_V_write,
img_data_stream_2_V_din => AXIvideo2Mat_U0_img_data_stream_2_V_din,
img_data_stream_2_V_full_n => img0_data_stream_2_s_full_n,
img_data_stream_2_V_write => AXIvideo2Mat_U0_img_data_stream_2_V_write,
img_rows_V_out_din => AXIvideo2Mat_U0_img_rows_V_out_din,
img_rows_V_out_full_n => img0_rows_V_c83_full_n,
img_rows_V_out_write => AXIvideo2Mat_U0_img_rows_V_out_write,
img_cols_V_out_din => AXIvideo2Mat_U0_img_cols_V_out_din,
img_cols_V_out_full_n => img0_cols_V_c84_full_n,
img_cols_V_out_write => AXIvideo2Mat_U0_img_cols_V_out_write);
CvtColor_1_U0 : component CvtColor_1
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => CvtColor_1_U0_ap_start,
ap_done => CvtColor_1_U0_ap_done,
ap_continue => CvtColor_1_U0_ap_continue,
ap_idle => CvtColor_1_U0_ap_idle,
ap_ready => CvtColor_1_U0_ap_ready,
p_src_rows_V_dout => img0_rows_V_c83_dout,
p_src_rows_V_empty_n => img0_rows_V_c83_empty_n,
p_src_rows_V_read => CvtColor_1_U0_p_src_rows_V_read,
p_src_cols_V_dout => img0_cols_V_c84_dout,
p_src_cols_V_empty_n => img0_cols_V_c84_empty_n,
p_src_cols_V_read => CvtColor_1_U0_p_src_cols_V_read,
p_src_data_stream_0_V_dout => img0_data_stream_0_s_dout,
p_src_data_stream_0_V_empty_n => img0_data_stream_0_s_empty_n,
p_src_data_stream_0_V_read => CvtColor_1_U0_p_src_data_stream_0_V_read,
p_src_data_stream_1_V_dout => img0_data_stream_1_s_dout,
p_src_data_stream_1_V_empty_n => img0_data_stream_1_s_empty_n,
p_src_data_stream_1_V_read => CvtColor_1_U0_p_src_data_stream_1_V_read,
p_src_data_stream_2_V_dout => img0_data_stream_2_s_dout,
p_src_data_stream_2_V_empty_n => img0_data_stream_2_s_empty_n,
p_src_data_stream_2_V_read => CvtColor_1_U0_p_src_data_stream_2_V_read,
p_dst_data_stream_0_V_din => CvtColor_1_U0_p_dst_data_stream_0_V_din,
p_dst_data_stream_0_V_full_n => img1_data_stream_0_s_full_n,
p_dst_data_stream_0_V_write => CvtColor_1_U0_p_dst_data_stream_0_V_write,
p_dst_data_stream_1_V_din => CvtColor_1_U0_p_dst_data_stream_1_V_din,
p_dst_data_stream_1_V_full_n => img1_data_stream_1_s_full_n,
p_dst_data_stream_1_V_write => CvtColor_1_U0_p_dst_data_stream_1_V_write,
p_dst_data_stream_2_V_din => CvtColor_1_U0_p_dst_data_stream_2_V_din,
p_dst_data_stream_2_V_full_n => img1_data_stream_2_s_full_n,
p_dst_data_stream_2_V_write => CvtColor_1_U0_p_dst_data_stream_2_V_write);
Loop_loop_height_pro_U0 : component Loop_loop_height_pro
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => Loop_loop_height_pro_U0_ap_start,
ap_done => Loop_loop_height_pro_U0_ap_done,
ap_continue => Loop_loop_height_pro_U0_ap_continue,
ap_idle => Loop_loop_height_pro_U0_ap_idle,
ap_ready => Loop_loop_height_pro_U0_ap_ready,
max_dout => max_c_dout,
max_empty_n => max_c_empty_n,
max_read => Loop_loop_height_pro_U0_max_read,
p_rows_assign_cast_loc_dout => p_rows_assign_cast_lo_dout,
p_rows_assign_cast_loc_empty_n => p_rows_assign_cast_lo_empty_n,
p_rows_assign_cast_loc_read => Loop_loop_height_pro_U0_p_rows_assign_cast_loc_read,
p_cols_assign_cast_loc_dout => p_cols_assign_cast_lo_dout,
p_cols_assign_cast_loc_empty_n => p_cols_assign_cast_lo_empty_n,
p_cols_assign_cast_loc_read => Loop_loop_height_pro_U0_p_cols_assign_cast_loc_read,
img2_data_stream_0_V_din => Loop_loop_height_pro_U0_img2_data_stream_0_V_din,
img2_data_stream_0_V_full_n => img2_data_stream_0_s_full_n,
img2_data_stream_0_V_write => Loop_loop_height_pro_U0_img2_data_stream_0_V_write,
img2_data_stream_1_V_din => Loop_loop_height_pro_U0_img2_data_stream_1_V_din,
img2_data_stream_1_V_full_n => img2_data_stream_1_s_full_n,
img2_data_stream_1_V_write => Loop_loop_height_pro_U0_img2_data_stream_1_V_write,
img2_data_stream_2_V_din => Loop_loop_height_pro_U0_img2_data_stream_2_V_din,
img2_data_stream_2_V_full_n => img2_data_stream_2_s_full_n,
img2_data_stream_2_V_write => Loop_loop_height_pro_U0_img2_data_stream_2_V_write,
img1_data_stream_0_V_dout => img1_data_stream_0_s_dout,
img1_data_stream_0_V_empty_n => img1_data_stream_0_s_empty_n,
img1_data_stream_0_V_read => Loop_loop_height_pro_U0_img1_data_stream_0_V_read,
img1_data_stream_1_V_dout => img1_data_stream_1_s_dout,
img1_data_stream_1_V_empty_n => img1_data_stream_1_s_empty_n,
img1_data_stream_1_V_read => Loop_loop_height_pro_U0_img1_data_stream_1_V_read,
img1_data_stream_2_V_dout => img1_data_stream_2_s_dout,
img1_data_stream_2_V_empty_n => img1_data_stream_2_s_empty_n,
img1_data_stream_2_V_read => Loop_loop_height_pro_U0_img1_data_stream_2_V_read,
min_dout => min_c_dout,
min_empty_n => min_c_empty_n,
min_read => Loop_loop_height_pro_U0_min_read,
tmp_3_cast_loc_dout => tmp_3_cast_loc_c_dout,
tmp_3_cast_loc_empty_n => tmp_3_cast_loc_c_empty_n,
tmp_3_cast_loc_read => Loop_loop_height_pro_U0_tmp_3_cast_loc_read);
CvtColor_U0 : component CvtColor
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => CvtColor_U0_ap_start,
ap_done => CvtColor_U0_ap_done,
ap_continue => CvtColor_U0_ap_continue,
ap_idle => CvtColor_U0_ap_idle,
ap_ready => CvtColor_U0_ap_ready,
p_src_rows_V_dout => img2_rows_V_c_dout,
p_src_rows_V_empty_n => img2_rows_V_c_empty_n,
p_src_rows_V_read => CvtColor_U0_p_src_rows_V_read,
p_src_cols_V_dout => img2_cols_V_c_dout,
p_src_cols_V_empty_n => img2_cols_V_c_empty_n,
p_src_cols_V_read => CvtColor_U0_p_src_cols_V_read,
p_src_data_stream_0_V_dout => img2_data_stream_0_s_dout,
p_src_data_stream_0_V_empty_n => img2_data_stream_0_s_empty_n,
p_src_data_stream_0_V_read => CvtColor_U0_p_src_data_stream_0_V_read,
p_src_data_stream_1_V_dout => img2_data_stream_1_s_dout,
p_src_data_stream_1_V_empty_n => img2_data_stream_1_s_empty_n,
p_src_data_stream_1_V_read => CvtColor_U0_p_src_data_stream_1_V_read,
p_src_data_stream_2_V_dout => img2_data_stream_2_s_dout,
p_src_data_stream_2_V_empty_n => img2_data_stream_2_s_empty_n,
p_src_data_stream_2_V_read => CvtColor_U0_p_src_data_stream_2_V_read,
p_dst_data_stream_0_V_din => CvtColor_U0_p_dst_data_stream_0_V_din,
p_dst_data_stream_0_V_full_n => img3_data_stream_0_s_full_n,
p_dst_data_stream_0_V_write => CvtColor_U0_p_dst_data_stream_0_V_write,
p_dst_data_stream_1_V_din => CvtColor_U0_p_dst_data_stream_1_V_din,
p_dst_data_stream_1_V_full_n => img3_data_stream_1_s_full_n,
p_dst_data_stream_1_V_write => CvtColor_U0_p_dst_data_stream_1_V_write,
p_dst_data_stream_2_V_din => CvtColor_U0_p_dst_data_stream_2_V_din,
p_dst_data_stream_2_V_full_n => img3_data_stream_2_s_full_n,
p_dst_data_stream_2_V_write => CvtColor_U0_p_dst_data_stream_2_V_write);
Mat2AXIvideo_U0 : component Mat2AXIvideo
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => Mat2AXIvideo_U0_ap_start,
ap_done => Mat2AXIvideo_U0_ap_done,
ap_continue => Mat2AXIvideo_U0_ap_continue,
ap_idle => Mat2AXIvideo_U0_ap_idle,
ap_ready => Mat2AXIvideo_U0_ap_ready,
img_rows_V_dout => img3_rows_V_c_dout,
img_rows_V_empty_n => img3_rows_V_c_empty_n,
img_rows_V_read => Mat2AXIvideo_U0_img_rows_V_read,
img_cols_V_dout => img3_cols_V_c_dout,
img_cols_V_empty_n => img3_cols_V_c_empty_n,
img_cols_V_read => Mat2AXIvideo_U0_img_cols_V_read,
img_data_stream_0_V_dout => img3_data_stream_0_s_dout,
img_data_stream_0_V_empty_n => img3_data_stream_0_s_empty_n,
img_data_stream_0_V_read => Mat2AXIvideo_U0_img_data_stream_0_V_read,
img_data_stream_1_V_dout => img3_data_stream_1_s_dout,
img_data_stream_1_V_empty_n => img3_data_stream_1_s_empty_n,
img_data_stream_1_V_read => Mat2AXIvideo_U0_img_data_stream_1_V_read,
img_data_stream_2_V_dout => img3_data_stream_2_s_dout,
img_data_stream_2_V_empty_n => img3_data_stream_2_s_empty_n,
img_data_stream_2_V_read => Mat2AXIvideo_U0_img_data_stream_2_V_read,
stream_out_TDATA => Mat2AXIvideo_U0_stream_out_TDATA,
stream_out_TVALID => Mat2AXIvideo_U0_stream_out_TVALID,
stream_out_TREADY => stream_out_TREADY,
stream_out_TKEEP => Mat2AXIvideo_U0_stream_out_TKEEP,
stream_out_TSTRB => Mat2AXIvideo_U0_stream_out_TSTRB,
stream_out_TUSER => Mat2AXIvideo_U0_stream_out_TUSER,
stream_out_TLAST => Mat2AXIvideo_U0_stream_out_TLAST,
stream_out_TID => Mat2AXIvideo_U0_stream_out_TID,
stream_out_TDEST => Mat2AXIvideo_U0_stream_out_TDEST);
min_c_U : component fifo_w8_d3_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit1573_p_U0_min_out_din,
if_full_n => min_c_full_n,
if_write => Block_Mat_exit1573_p_U0_min_out_write,
if_dout => min_c_dout,
if_empty_n => min_c_empty_n,
if_read => Loop_loop_height_pro_U0_min_read);
img0_rows_V_c_U : component fifo_w16_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit1573_p_U0_img0_rows_V_out_din,
if_full_n => img0_rows_V_c_full_n,
if_write => Block_Mat_exit1573_p_U0_img0_rows_V_out_write,
if_dout => img0_rows_V_c_dout,
if_empty_n => img0_rows_V_c_empty_n,
if_read => AXIvideo2Mat_U0_img_rows_V_read);
img0_cols_V_c_U : component fifo_w16_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit1573_p_U0_img0_cols_V_out_din,
if_full_n => img0_cols_V_c_full_n,
if_write => Block_Mat_exit1573_p_U0_img0_cols_V_out_write,
if_dout => img0_cols_V_c_dout,
if_empty_n => img0_cols_V_c_empty_n,
if_read => AXIvideo2Mat_U0_img_cols_V_read);
img2_rows_V_c_U : component fifo_w16_d4_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit1573_p_U0_img2_rows_V_out_din,
if_full_n => img2_rows_V_c_full_n,
if_write => Block_Mat_exit1573_p_U0_img2_rows_V_out_write,
if_dout => img2_rows_V_c_dout,
if_empty_n => img2_rows_V_c_empty_n,
if_read => CvtColor_U0_p_src_rows_V_read);
img2_cols_V_c_U : component fifo_w16_d4_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit1573_p_U0_img2_cols_V_out_din,
if_full_n => img2_cols_V_c_full_n,
if_write => Block_Mat_exit1573_p_U0_img2_cols_V_out_write,
if_dout => img2_cols_V_c_dout,
if_empty_n => img2_cols_V_c_empty_n,
if_read => CvtColor_U0_p_src_cols_V_read);
img3_rows_V_c_U : component fifo_w16_d5_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit1573_p_U0_img3_rows_V_out_din,
if_full_n => img3_rows_V_c_full_n,
if_write => Block_Mat_exit1573_p_U0_img3_rows_V_out_write,
if_dout => img3_rows_V_c_dout,
if_empty_n => img3_rows_V_c_empty_n,
if_read => Mat2AXIvideo_U0_img_rows_V_read);
img3_cols_V_c_U : component fifo_w16_d5_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit1573_p_U0_img3_cols_V_out_din,
if_full_n => img3_cols_V_c_full_n,
if_write => Block_Mat_exit1573_p_U0_img3_cols_V_out_write,
if_dout => img3_cols_V_c_dout,
if_empty_n => img3_cols_V_c_empty_n,
if_read => Mat2AXIvideo_U0_img_cols_V_read);
p_cols_assign_cast_lo_U : component fifo_w12_d3_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit1573_p_U0_p_cols_assign_cast_out_out_din,
if_full_n => p_cols_assign_cast_lo_full_n,
if_write => Block_Mat_exit1573_p_U0_p_cols_assign_cast_out_out_write,
if_dout => p_cols_assign_cast_lo_dout,
if_empty_n => p_cols_assign_cast_lo_empty_n,
if_read => Loop_loop_height_pro_U0_p_cols_assign_cast_loc_read);
p_rows_assign_cast_lo_U : component fifo_w12_d3_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit1573_p_U0_p_rows_assign_cast_out_out_din,
if_full_n => p_rows_assign_cast_lo_full_n,
if_write => Block_Mat_exit1573_p_U0_p_rows_assign_cast_out_out_write,
if_dout => p_rows_assign_cast_lo_dout,
if_empty_n => p_rows_assign_cast_lo_empty_n,
if_read => Loop_loop_height_pro_U0_p_rows_assign_cast_loc_read);
tmp_3_cast_loc_c_U : component fifo_w8_d3_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit1573_p_U0_tmp_3_cast_out_out_din,
if_full_n => tmp_3_cast_loc_c_full_n,
if_write => Block_Mat_exit1573_p_U0_tmp_3_cast_out_out_write,
if_dout => tmp_3_cast_loc_c_dout,
if_empty_n => tmp_3_cast_loc_c_empty_n,
if_read => Loop_loop_height_pro_U0_tmp_3_cast_loc_read);
max_c_U : component fifo_w8_d3_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit1573_p_U0_max_out_din,
if_full_n => max_c_full_n,
if_write => Block_Mat_exit1573_p_U0_max_out_write,
if_dout => max_c_dout,
if_empty_n => max_c_empty_n,
if_read => Loop_loop_height_pro_U0_max_read);
img0_data_stream_0_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => AXIvideo2Mat_U0_img_data_stream_0_V_din,
if_full_n => img0_data_stream_0_s_full_n,
if_write => AXIvideo2Mat_U0_img_data_stream_0_V_write,
if_dout => img0_data_stream_0_s_dout,
if_empty_n => img0_data_stream_0_s_empty_n,
if_read => CvtColor_1_U0_p_src_data_stream_0_V_read);
img0_data_stream_1_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => AXIvideo2Mat_U0_img_data_stream_1_V_din,
if_full_n => img0_data_stream_1_s_full_n,
if_write => AXIvideo2Mat_U0_img_data_stream_1_V_write,
if_dout => img0_data_stream_1_s_dout,
if_empty_n => img0_data_stream_1_s_empty_n,
if_read => CvtColor_1_U0_p_src_data_stream_1_V_read);
img0_data_stream_2_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => AXIvideo2Mat_U0_img_data_stream_2_V_din,
if_full_n => img0_data_stream_2_s_full_n,
if_write => AXIvideo2Mat_U0_img_data_stream_2_V_write,
if_dout => img0_data_stream_2_s_dout,
if_empty_n => img0_data_stream_2_s_empty_n,
if_read => CvtColor_1_U0_p_src_data_stream_2_V_read);
img0_rows_V_c83_U : component fifo_w16_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => AXIvideo2Mat_U0_img_rows_V_out_din,
if_full_n => img0_rows_V_c83_full_n,
if_write => AXIvideo2Mat_U0_img_rows_V_out_write,
if_dout => img0_rows_V_c83_dout,
if_empty_n => img0_rows_V_c83_empty_n,
if_read => CvtColor_1_U0_p_src_rows_V_read);
img0_cols_V_c84_U : component fifo_w16_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => AXIvideo2Mat_U0_img_cols_V_out_din,
if_full_n => img0_cols_V_c84_full_n,
if_write => AXIvideo2Mat_U0_img_cols_V_out_write,
if_dout => img0_cols_V_c84_dout,
if_empty_n => img0_cols_V_c84_empty_n,
if_read => CvtColor_1_U0_p_src_cols_V_read);
img1_data_stream_0_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => CvtColor_1_U0_p_dst_data_stream_0_V_din,
if_full_n => img1_data_stream_0_s_full_n,
if_write => CvtColor_1_U0_p_dst_data_stream_0_V_write,
if_dout => img1_data_stream_0_s_dout,
if_empty_n => img1_data_stream_0_s_empty_n,
if_read => Loop_loop_height_pro_U0_img1_data_stream_0_V_read);
img1_data_stream_1_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => CvtColor_1_U0_p_dst_data_stream_1_V_din,
if_full_n => img1_data_stream_1_s_full_n,
if_write => CvtColor_1_U0_p_dst_data_stream_1_V_write,
if_dout => img1_data_stream_1_s_dout,
if_empty_n => img1_data_stream_1_s_empty_n,
if_read => Loop_loop_height_pro_U0_img1_data_stream_1_V_read);
img1_data_stream_2_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => CvtColor_1_U0_p_dst_data_stream_2_V_din,
if_full_n => img1_data_stream_2_s_full_n,
if_write => CvtColor_1_U0_p_dst_data_stream_2_V_write,
if_dout => img1_data_stream_2_s_dout,
if_empty_n => img1_data_stream_2_s_empty_n,
if_read => Loop_loop_height_pro_U0_img1_data_stream_2_V_read);
img2_data_stream_0_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Loop_loop_height_pro_U0_img2_data_stream_0_V_din,
if_full_n => img2_data_stream_0_s_full_n,
if_write => Loop_loop_height_pro_U0_img2_data_stream_0_V_write,
if_dout => img2_data_stream_0_s_dout,
if_empty_n => img2_data_stream_0_s_empty_n,
if_read => CvtColor_U0_p_src_data_stream_0_V_read);
img2_data_stream_1_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Loop_loop_height_pro_U0_img2_data_stream_1_V_din,
if_full_n => img2_data_stream_1_s_full_n,
if_write => Loop_loop_height_pro_U0_img2_data_stream_1_V_write,
if_dout => img2_data_stream_1_s_dout,
if_empty_n => img2_data_stream_1_s_empty_n,
if_read => CvtColor_U0_p_src_data_stream_1_V_read);
img2_data_stream_2_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Loop_loop_height_pro_U0_img2_data_stream_2_V_din,
if_full_n => img2_data_stream_2_s_full_n,
if_write => Loop_loop_height_pro_U0_img2_data_stream_2_V_write,
if_dout => img2_data_stream_2_s_dout,
if_empty_n => img2_data_stream_2_s_empty_n,
if_read => CvtColor_U0_p_src_data_stream_2_V_read);
img3_data_stream_0_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => CvtColor_U0_p_dst_data_stream_0_V_din,
if_full_n => img3_data_stream_0_s_full_n,
if_write => CvtColor_U0_p_dst_data_stream_0_V_write,
if_dout => img3_data_stream_0_s_dout,
if_empty_n => img3_data_stream_0_s_empty_n,
if_read => Mat2AXIvideo_U0_img_data_stream_0_V_read);
img3_data_stream_1_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => CvtColor_U0_p_dst_data_stream_1_V_din,
if_full_n => img3_data_stream_1_s_full_n,
if_write => CvtColor_U0_p_dst_data_stream_1_V_write,
if_dout => img3_data_stream_1_s_dout,
if_empty_n => img3_data_stream_1_s_empty_n,
if_read => Mat2AXIvideo_U0_img_data_stream_1_V_read);
img3_data_stream_2_s_U : component fifo_w8_d1_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => CvtColor_U0_p_dst_data_stream_2_V_din,
if_full_n => img3_data_stream_2_s_full_n,
if_write => CvtColor_U0_p_dst_data_stream_2_V_write,
if_dout => img3_data_stream_2_s_dout,
if_empty_n => img3_data_stream_2_s_empty_n,
if_read => Mat2AXIvideo_U0_img_data_stream_2_V_read);
start_for_Loop_lojbC_U : component start_for_Loop_lojbC
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => start_for_Loop_loop_height_pro_U0_din,
if_full_n => start_for_Loop_loop_height_pro_U0_full_n,
if_write => Block_Mat_exit1573_p_U0_start_write,
if_dout => start_for_Loop_loop_height_pro_U0_dout,
if_empty_n => start_for_Loop_loop_height_pro_U0_empty_n,
if_read => Loop_loop_height_pro_U0_ap_ready);
start_for_CvtColokbM_U : component start_for_CvtColokbM
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => start_for_CvtColor_U0_din,
if_full_n => start_for_CvtColor_U0_full_n,
if_write => Block_Mat_exit1573_p_U0_start_write,
if_dout => start_for_CvtColor_U0_dout,
if_empty_n => start_for_CvtColor_U0_empty_n,
if_read => CvtColor_U0_ap_ready);
start_for_Mat2AXIlbW_U : component start_for_Mat2AXIlbW
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => start_for_Mat2AXIvideo_U0_din,
if_full_n => start_for_Mat2AXIvideo_U0_full_n,
if_write => Block_Mat_exit1573_p_U0_start_write,
if_dout => start_for_Mat2AXIvideo_U0_dout,
if_empty_n => start_for_Mat2AXIvideo_U0_empty_n,
if_read => Mat2AXIvideo_U0_ap_ready);
start_for_CvtColomb6_U : component start_for_CvtColomb6
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => start_for_CvtColor_1_U0_din,
if_full_n => start_for_CvtColor_1_U0_full_n,
if_write => AXIvideo2Mat_U0_start_write,
if_dout => start_for_CvtColor_1_U0_dout,
if_empty_n => start_for_CvtColor_1_U0_empty_n,
if_read => CvtColor_1_U0_ap_ready);
AXIvideo2Mat_U0_ap_continue <= ap_const_logic_1;
AXIvideo2Mat_U0_ap_start <= ap_const_logic_1;
Block_Mat_exit1573_p_U0_ap_continue <= ap_const_logic_1;
Block_Mat_exit1573_p_U0_ap_start <= ap_const_logic_1;
Block_Mat_exit1573_p_U0_start_full_n <= (start_for_Mat2AXIvideo_U0_full_n and start_for_Loop_loop_height_pro_U0_full_n and start_for_CvtColor_U0_full_n);
CvtColor_1_U0_ap_continue <= ap_const_logic_1;
CvtColor_1_U0_ap_start <= start_for_CvtColor_1_U0_empty_n;
CvtColor_1_U0_start_full_n <= ap_const_logic_1;
CvtColor_1_U0_start_write <= ap_const_logic_0;
CvtColor_U0_ap_continue <= ap_const_logic_1;
CvtColor_U0_ap_start <= start_for_CvtColor_U0_empty_n;
CvtColor_U0_start_full_n <= ap_const_logic_1;
CvtColor_U0_start_write <= ap_const_logic_0;
Loop_loop_height_pro_U0_ap_continue <= ap_const_logic_1;
Loop_loop_height_pro_U0_ap_start <= start_for_Loop_loop_height_pro_U0_empty_n;
Loop_loop_height_pro_U0_start_full_n <= ap_const_logic_1;
Loop_loop_height_pro_U0_start_write <= ap_const_logic_0;
Mat2AXIvideo_U0_ap_continue <= ap_const_logic_1;
Mat2AXIvideo_U0_ap_start <= start_for_Mat2AXIvideo_U0_empty_n;
Mat2AXIvideo_U0_start_full_n <= ap_const_logic_1;
Mat2AXIvideo_U0_start_write <= ap_const_logic_0;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
ap_sync_continue <= ap_const_logic_0;
start_for_CvtColor_1_U0_din <= (0=>ap_const_logic_1, others=>'-');
start_for_CvtColor_U0_din <= (0=>ap_const_logic_1, others=>'-');
start_for_Loop_loop_height_pro_U0_din <= (0=>ap_const_logic_1, others=>'-');
start_for_Mat2AXIvideo_U0_din <= (0=>ap_const_logic_1, others=>'-');
stream_in_TREADY <= AXIvideo2Mat_U0_stream_in_TREADY;
stream_out_TDATA <= Mat2AXIvideo_U0_stream_out_TDATA;
stream_out_TDEST <= Mat2AXIvideo_U0_stream_out_TDEST;
stream_out_TID <= Mat2AXIvideo_U0_stream_out_TID;
stream_out_TKEEP <= Mat2AXIvideo_U0_stream_out_TKEEP;
stream_out_TLAST <= Mat2AXIvideo_U0_stream_out_TLAST;
stream_out_TSTRB <= Mat2AXIvideo_U0_stream_out_TSTRB;
stream_out_TUSER <= Mat2AXIvideo_U0_stream_out_TUSER;
stream_out_TVALID <= Mat2AXIvideo_U0_stream_out_TVALID;
end behav;
|
mit
|
55987727621b8ae0fd2990d443149f75
| 0.616184 | 2.698344 | false | false | false | false |
grafi-tt/Maizul
|
src/Unit/FPU/FAddHelper.vhd
| 1 | 3,233 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FractionLeftTrimming is
port (
frc_in : in std_logic_vector(23 downto 0);
nlz : out std_logic_vector( 4 downto 0);
frc_out : out std_logic_vector(22 downto 0));
end FractionLeftTrimming;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FractionRightShifter is
port (
frc_in : in std_logic_vector(23 downto 0);
len : in std_logic_vector( 4 downto 0);
frc_out : out std_logic_vector(23 downto 0);
fst_over_out : out std_logic;
snd_over_out : out std_logic;
tail_any_out : out std_logic);
end FractionRightShifter;
architecture TrimmingL24 of FractionLeftTrimming is
type ufrc_step_vector is array (3 downto 0) of unsigned(23 downto 0);
signal u_frc : ufrc_step_vector;
signal u_frc_in : unsigned(23 downto 0);
signal u_frc_out : unsigned(23 downto 0);
begin
u_frc_in <= unsigned(frc_in);
nlz(4) <= '1' when u_frc_in(23 downto 8) = 0 else '0';
u_frc(3) <= u_frc_in sll 16 when u_frc_in(23 downto 8) = 0 else u_frc_in;
nlz(3) <= '1' when u_frc(3)(23 downto 16) = 0 else '0';
u_frc(2) <= u_frc(3) sll 8 when u_frc(3)(23 downto 16) = 0 else u_frc(3);
nlz(2) <= '1' when u_frc(2)(23 downto 20) = 0 else '0';
u_frc(1) <= u_frc(2) sll 4 when u_frc(2)(23 downto 20) = 0 else u_frc(2);
nlz(1) <= '1' when u_frc(1)(23 downto 22) = 0 else '0';
u_frc(0) <= u_frc(1) sll 2 when u_frc(1)(23 downto 22) = 0 else u_frc(1);
nlz(0) <= '1' when u_frc(0)(23 downto 23) = 0 else '0';
u_frc_out <= u_frc(0) sll 1 when u_frc(0)(23 downto 23) = 0 else u_frc(0);
frc_out <= std_logic_vector(u_frc_out(22 downto 0));
end TrimmingL24;
architecture BarrelShifterR24Mod of FractionRightShifter is
type ufrc_step_vector is array (3 downto 0) of unsigned(25 downto 0);
signal u_frc: ufrc_step_vector;
signal u_frc_in: unsigned(25 downto 0);
signal u_frc_out: unsigned(25 downto 0);
signal tail_any: std_logic_vector (3 downto 0);
begin
u_frc_in <= unsigned(frc_in) & "00";
tail_any(3) <= '1' when len(4) = '1' and u_frc_in(15 downto 0) /= 0 else '0';
u_frc(3) <= u_frc_in srl 16 when len(4) = '1' else u_frc_in;
tail_any(2) <= '1' when len(3) = '1' and u_frc(3)( 7 downto 0) /= 0 else tail_any(3);
u_frc(2) <= u_frc(3) srl 8 when len(3) = '1' else u_frc(3);
tail_any(1) <= '1' when len(2) = '1' and u_frc(2)( 3 downto 0) /= 0 else tail_any(2);
u_frc(1) <= u_frc(2) srl 4 when len(2) = '1' else u_frc(2);
tail_any(0) <= '1' when len(1) = '1' and u_frc(1)( 1 downto 0) /= 0 else tail_any(1);
u_frc(0) <= u_frc(1) srl 2 when len(1) = '1' else u_frc(1);
tail_any_out <= '1' when len(0) = '1' and u_frc(0)( 0 downto 0) /= 0 else tail_any(0);
u_frc_out <= u_frc(0) srl 1 when len(0) = '1' else u_frc(0);
snd_over_out <= u_frc_out(0);
fst_over_out <= u_frc_out(1);
frc_out <= std_logic_vector(u_frc_out(25 downto 2));
end BarrelShifterR24Mod;
|
bsd-2-clause
|
bcc4a6145b2a9263915dc6e8cea08036
| 0.5648 | 2.685216 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/Loop_loop_height_hbi.vhd
| 1 | 7,308 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Loop_loop_height_hbi_rom is
generic(
dwidth : integer := 8;
awidth : integer := 8;
mem_size : integer := 256
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of Loop_loop_height_hbi_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem : mem_array := (
0 => "00000000", 1 => "00000001", 2 => "00000010", 3 => "00000100",
4 => "00000101", 5 => "00000110", 6 => "00000111", 7 => "00001000",
8 => "00001010", 9 => "00001011", 10 => "00001100", 11 => "00001101",
12 => "00001110", 13 => "00001111", 14 => "00010001", 15 => "00010010",
16 => "00010011", 17 => "00010100", 18 => "00010101", 19 => "00010111",
20 => "00011000", 21 => "00011001", 22 => "00011010", 23 => "00011011",
24 => "00011100", 25 => "00011110", 26 => "00011111", 27 => "00100000",
28 => "00100001", 29 => "00100010", 30 => "00100011", 31 => "00100100",
32 => "00100110", 33 => "00100111", 34 => "00101000", 35 => "00101001",
36 => "00101010", 37 => "00101011", 38 => "00101100", 39 => "00101110",
40 => "00101111", 41 => "00110000", 42 => "00110001", 43 => "00110010",
44 => "00110011", 45 => "00110100", 46 => "00110110", 47 => "00110111",
48 => "00111000", 49 => "00111001", 50 => "00111010", 51 => "00111011",
52 => "00111100", 53 => "00111101", 54 => "00111111", 55 => "01000000",
56 => "01000001", 57 => "01000010", 58 => "01000011", 59 => "01000100",
60 => "01000101", 61 => "01000110", 62 => "01000111", 63 => "01001000",
64 => "01001010", 65 => "01001011", 66 => "01001100", 67 => "01001101",
68 => "01001110", 69 => "01001111", 70 => "01010000", 71 => "01010001",
72 => "01010010", 73 => "01010011", 74 => "01010101", 75 => "01010110",
76 => "01010111", 77 => "01011000", 78 => "01011001", 79 => "01011010",
80 => "01011011", 81 => "01011100", 82 => "01011101", 83 => "01011110",
84 => "01011111", 85 => "01100000", 86 => "01100001", 87 => "01100010",
88 => "01100100", 89 => "01100101", 90 => "01100110", 91 => "01100111",
92 => "01101000", 93 => "01101001", 94 => "01101010", 95 => "01101011",
96 => "01101100", 97 => "01101101", 98 => "01101110", 99 => "01101111",
100 => "01110000", 101 => "01110001", 102 => "01110010", 103 => "01110011",
104 => "01110100", 105 => "01110101", 106 => "01110110", 107 => "01110111",
108 => "01111000", 109 => "01111001", 110 => "01111011", 111 => "01111100",
112 => "01111101", 113 => "01111110", 114 => "01111111", 115 => "10000000",
116 => "10000001", 117 => "10000010", 118 => "10000011", 119 => "10000100",
120 => "10000101", 121 => "10000110", 122 => "10000111", 123 => "10001000",
124 => "10001001", 125 => "10001010", 126 => "10001011", 127 => "10001100",
128 => "10001101", 129 => "10001110", 130 => "10001111", 131 => "10010000",
132 => "10010001", 133 => "10010010", 134 => "10010011", 135 => "10010100",
136 => "10010101", 137 => "10010110", 138 => "10010111", 139 => "10011000",
140 => "10011001", 141 => "10011010", 142 => "10011011", 143 => "10011100",
144 => "10011101", 145 to 146=> "10011110", 147 => "10011111", 148 => "10100000",
149 => "10100001", 150 => "10100010", 151 => "10100011", 152 => "10100100",
153 => "10100101", 154 => "10100110", 155 => "10100111", 156 => "10101000",
157 => "10101001", 158 => "10101010", 159 => "10101011", 160 => "10101100",
161 => "10101101", 162 => "10101110", 163 => "10101111", 164 => "10110000",
165 => "10110001", 166 => "10110010", 167 to 168=> "10110011", 169 => "10110100",
170 => "10110101", 171 => "10110110", 172 => "10110111", 173 => "10111000",
174 => "10111001", 175 => "10111010", 176 => "10111011", 177 => "10111100",
178 => "10111101", 179 => "10111110", 180 => "10111111", 181 to 182=> "11000000",
183 => "11000001", 184 => "11000010", 185 => "11000011", 186 => "11000100",
187 => "11000101", 188 => "11000110", 189 => "11000111", 190 => "11001000",
191 to 192=> "11001001", 193 => "11001010", 194 => "11001011", 195 => "11001100",
196 => "11001101", 197 => "11001110", 198 => "11001111", 199 => "11010000",
200 => "11010001", 201 to 202=> "11010010", 203 => "11010011", 204 => "11010100",
205 => "11010101", 206 => "11010110", 207 => "11010111", 208 => "11011000",
209 to 210=> "11011001", 211 => "11011010", 212 => "11011011", 213 => "11011100",
214 => "11011101", 215 => "11011110", 216 to 217=> "11011111", 218 => "11100000",
219 => "11100001", 220 => "11100010", 221 => "11100011", 222 => "11100100",
223 to 224=> "11100101", 225 => "11100110", 226 => "11100111", 227 => "11101000",
228 => "11101001", 229 => "11101010", 230 to 231=> "11101011", 232 => "11101100",
233 => "11101101", 234 => "11101110", 235 => "11101111", 236 to 237=> "11110000",
238 => "11110001", 239 => "11110010", 240 => "11110011", 241 to 242=> "11110100",
243 => "11110101", 244 => "11110110", 245 => "11110111", 246 => "11111000",
247 to 248=> "11111001", 249 => "11111010", 250 => "11111011", 251 => "11111100",
252 to 253=> "11111101", 254 => "11111110", 255 => "11111111" );
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity Loop_loop_height_hbi is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 256;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of Loop_loop_height_hbi is
component Loop_loop_height_hbi_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
Loop_loop_height_hbi_rom_U : component Loop_loop_height_hbi_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0);
end architecture;
|
mit
|
a4585ac3f5ebdb94e440f453d2e0f1bb
| 0.538998 | 3.685325 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
lab3_six_segment/lab3_six_segment.vhd
| 1 | 6,300 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lab3_six_segment is
Port (
sw1_low_in : in std_logic_vector(3 downto 0);
sw1_high_in : in std_logic_vector(3 downto 0);
sw2_low_in : in std_logic_vector(3 downto 0);
sw2_high_in : in std_logic_vector(3 downto 0);
sw3_low_in : in std_logic_vector(3 downto 0);
sw3_high_in : in std_logic_vector(3 downto 0);
clock : in std_logic;
selector : out std_logic_vector(2 downto 0);
segment : out std_logic_vector(7 downto 0)
);
end lab3_six_segment;
architecture Behavioral of lab3_six_segment is
signal number : std_logic_vector( 2 downto 0 ) := "000";-- decimal 0 to 7
signal count : std_logic_vector(15 downto 0) := "0000000000000000";
begin
process( clock ) begin
if clock'event and clock = '1' then
count <= count + 1;
if count = 0 then
number <= number + 1;
if number = 0 then
case sw1_low_in is
when "0000" => segment <= "11000000";
when "0001" => segment <= "11111001";
when "0010" => segment <= "10100100";
when "0011" => segment <= "10110000";
when "0100" => segment <= "10011001";
when "0101" => segment <= "10010010";
when "0110" => segment <= "10000010";
when "0111" => segment <= "11111000";
when "1000" => segment <= "10000000";
when "1001" => segment <= "10010000";
when "1010" => segment <= "10001000";
when "1011" => segment <= "10000011";
when "1100" => segment <= "11000110";
when "1101" => segment <= "10100001";
when "1110" => segment <= "10000110";
when others => segment <= "10001110";
end case;
selector <= "000";
elsif number = 1 then
case sw1_high_in is
when "0000" => segment <= "11000000";
when "0001" => segment <= "11111001";
when "0010" => segment <= "10100100";
when "0011" => segment <= "10110000";
when "0100" => segment <= "10011001";
when "0101" => segment <= "10010010";
when "0110" => segment <= "10000010";
when "0111" => segment <= "11111000";
when "1000" => segment <= "10000000";
when "1001" => segment <= "10010000";
when "1010" => segment <= "10001000";
when "1011" => segment <= "10000011";
when "1100" => segment <= "11000110";
when "1101" => segment <= "10100001";
when "1110" => segment <= "10000110";
when others => segment <= "10001110";
end case;
selector <= "001";
elsif number = 2 then
case sw2_low_in is
when "0000" => segment <= "11000000";
when "0001" => segment <= "11111001";
when "0010" => segment <= "10100100";
when "0011" => segment <= "10110000";
when "0100" => segment <= "10011001";
when "0101" => segment <= "10010010";
when "0110" => segment <= "10000010";
when "0111" => segment <= "11111000";
when "1000" => segment <= "10000000";
when "1001" => segment <= "10010000";
when "1010" => segment <= "10001000";
when "1011" => segment <= "10000011";
when "1100" => segment <= "11000110";
when "1101" => segment <= "10100001";
when "1110" => segment <= "10000110";
when others => segment <= "10001110";
end case;
selector <= "010";
elsif number = 3 then
case sw2_high_in is
when "0000" => segment <= "11000000";
when "0001" => segment <= "11111001";
when "0010" => segment <= "10100100";
when "0011" => segment <= "10110000";
when "0100" => segment <= "10011001";
when "0101" => segment <= "10010010";
when "0110" => segment <= "10000010";
when "0111" => segment <= "11111000";
when "1000" => segment <= "10000000";
when "1001" => segment <= "10010000";
when "1010" => segment <= "10001000";
when "1011" => segment <= "10000011";
when "1100" => segment <= "11000110";
when "1101" => segment <= "10100001";
when "1110" => segment <= "10000110";
when others => segment <= "10001110";
end case;
selector <= "011";
elsif number = 4 then
case sw3_low_in is
when "0000" => segment <= "11000000";
when "0001" => segment <= "11111001";
when "0010" => segment <= "10100100";
when "0011" => segment <= "10110000";
when "0100" => segment <= "10011001";
when "0101" => segment <= "10010010";
when "0110" => segment <= "10000010";
when "0111" => segment <= "11111000";
when "1000" => segment <= "10000000";
when "1001" => segment <= "10010000";
when "1010" => segment <= "10001000";
when "1011" => segment <= "10000011";
when "1100" => segment <= "11000110";
when "1101" => segment <= "10100001";
when "1110" => segment <= "10000110";
when others => segment <= "10001110";
end case;
selector <= "100";
elsif number = 5 then
case sw3_high_in is
when "0000" => segment <= "11000000";
when "0001" => segment <= "11111001";
when "0010" => segment <= "10100100";
when "0011" => segment <= "10110000";
when "0100" => segment <= "10011001";
when "0101" => segment <= "10010010";
when "0110" => segment <= "10000010";
when "0111" => segment <= "11111000";
when "1000" => segment <= "10000000";
when "1001" => segment <= "10010000";
when "1010" => segment <= "10001000";
when "1011" => segment <= "10000011";
when "1100" => segment <= "11000110";
when "1101" => segment <= "10100001";
when "1110" => segment <= "10000110";
when others => segment <= "10001110";
end case;
selector <= "101";
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
ee4e8a5a234226addac71c420bb438d7
| 0.524603 | 3.667055 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_gamma_correction_1_0/hdl/vhdl/Loop_loop_height_hbi.vhd
| 1 | 13,204 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Loop_loop_height_hbi_rom is
generic(
dwidth : integer := 8;
awidth : integer := 8;
mem_size : integer := 256
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
addr2 : in std_logic_vector(awidth-1 downto 0);
ce2 : in std_logic;
q2 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of Loop_loop_height_hbi_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
signal addr2_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem0 : mem_array := (
0 => "00000000", 1 => "00001100", 2 => "00010001", 3 => "00010110",
4 => "00011001", 5 => "00011101", 6 => "00100000", 7 => "00100011",
8 => "00100101", 9 => "00101000", 10 => "00101010", 11 => "00101100",
12 => "00101111", 13 => "00110001", 14 => "00110011", 15 => "00110101",
16 => "00110111", 17 => "00111001", 18 => "00111010", 19 => "00111100",
20 => "00111110", 21 => "01000000", 22 => "01000001", 23 => "01000011",
24 => "01000101", 25 => "01000110", 26 => "01001000", 27 => "01001001",
28 => "01001011", 29 => "01001100", 30 => "01001110", 31 => "01001111",
32 => "01010000", 33 => "01010010", 34 => "01010011", 35 => "01010101",
36 => "01010110", 37 => "01010111", 38 => "01011001", 39 => "01011010",
40 => "01011011", 41 => "01011100", 42 => "01011110", 43 => "01011111",
44 => "01100000", 45 => "01100001", 46 => "01100010", 47 => "01100100",
48 => "01100101", 49 => "01100110", 50 => "01100111", 51 => "01101000",
52 => "01101001", 53 => "01101011", 54 => "01101100", 55 => "01101101",
56 => "01101110", 57 => "01101111", 58 => "01110000", 59 => "01110001",
60 => "01110010", 61 => "01110011", 62 => "01110100", 63 => "01110101",
64 => "01110110", 65 => "01110111", 66 => "01111000", 67 => "01111001",
68 => "01111010", 69 => "01111011", 70 => "01111100", 71 => "01111101",
72 => "01111110", 73 => "01111111", 74 => "10000000", 75 => "10000001",
76 => "10000010", 77 => "10000011", 78 => "10000100", 79 => "10000101",
80 => "10000110", 81 => "10000111", 82 => "10001000", 83 => "10001001",
84 => "10001010", 85 to 86=> "10001011", 87 => "10001100", 88 => "10001101",
89 => "10001110", 90 => "10001111", 91 => "10010000", 92 => "10010001",
93 to 94=> "10010010", 95 => "10010011", 96 => "10010100", 97 => "10010101",
98 => "10010110", 99 => "10010111", 100 to 101=> "10011000", 102 => "10011001",
103 => "10011010", 104 => "10011011", 105 => "10011100", 106 to 107=> "10011101",
108 => "10011110", 109 => "10011111", 110 => "10100000", 111 to 112=> "10100001",
113 => "10100010", 114 => "10100011", 115 => "10100100", 116 to 117=> "10100101",
118 => "10100110", 119 => "10100111", 120 => "10101000", 121 to 122=> "10101001",
123 => "10101010", 124 => "10101011", 125 to 126=> "10101100", 127 => "10101101",
128 => "10101110", 129 to 130=> "10101111", 131 => "10110000", 132 => "10110001",
133 to 134=> "10110010", 135 => "10110011", 136 => "10110100", 137 to 138=> "10110101",
139 => "10110110", 140 to 141=> "10110111", 142 => "10111000", 143 => "10111001",
144 to 145=> "10111010", 146 => "10111011", 147 to 148=> "10111100", 149 => "10111101",
150 => "10111110", 151 to 152=> "10111111", 153 => "11000000", 154 to 155=> "11000001",
156 => "11000010", 157 to 158=> "11000011", 159 => "11000100", 160 => "11000101",
161 to 162=> "11000110", 163 => "11000111", 164 to 165=> "11001000", 166 => "11001001",
167 to 168=> "11001010", 169 => "11001011", 170 to 171=> "11001100", 172 => "11001101",
173 to 174=> "11001110", 175 => "11001111", 176 to 177=> "11010000", 178 to 179=> "11010001",
180 => "11010010", 181 to 182=> "11010011", 183 => "11010100", 184 to 185=> "11010101",
186 => "11010110", 187 to 188=> "11010111", 189 => "11011000", 190 to 191=> "11011001",
192 to 193=> "11011010", 194 => "11011011", 195 to 196=> "11011100", 197 => "11011101",
198 to 199=> "11011110", 200 to 201=> "11011111", 202 => "11100000", 203 to 204=> "11100001",
205 to 206=> "11100010", 207 => "11100011", 208 to 209=> "11100100", 210 => "11100101",
211 to 212=> "11100110", 213 to 214=> "11100111", 215 => "11101000", 216 to 217=> "11101001",
218 to 219=> "11101010", 220 => "11101011", 221 to 222=> "11101100", 223 to 224=> "11101101",
225 to 226=> "11101110", 227 => "11101111", 228 to 229=> "11110000", 230 to 231=> "11110001",
232 => "11110010", 233 to 234=> "11110011", 235 to 236=> "11110100", 237 to 238=> "11110101",
239 => "11110110", 240 to 241=> "11110111", 242 to 243=> "11111000", 244 to 245=> "11111001",
246 => "11111010", 247 to 248=> "11111011", 249 to 250=> "11111100", 251 to 252=> "11111101",
253 to 254=> "11111110", 255 => "11111111" );
signal mem1 : mem_array := (
0 => "00000000", 1 => "00001100", 2 => "00010001", 3 => "00010110",
4 => "00011001", 5 => "00011101", 6 => "00100000", 7 => "00100011",
8 => "00100101", 9 => "00101000", 10 => "00101010", 11 => "00101100",
12 => "00101111", 13 => "00110001", 14 => "00110011", 15 => "00110101",
16 => "00110111", 17 => "00111001", 18 => "00111010", 19 => "00111100",
20 => "00111110", 21 => "01000000", 22 => "01000001", 23 => "01000011",
24 => "01000101", 25 => "01000110", 26 => "01001000", 27 => "01001001",
28 => "01001011", 29 => "01001100", 30 => "01001110", 31 => "01001111",
32 => "01010000", 33 => "01010010", 34 => "01010011", 35 => "01010101",
36 => "01010110", 37 => "01010111", 38 => "01011001", 39 => "01011010",
40 => "01011011", 41 => "01011100", 42 => "01011110", 43 => "01011111",
44 => "01100000", 45 => "01100001", 46 => "01100010", 47 => "01100100",
48 => "01100101", 49 => "01100110", 50 => "01100111", 51 => "01101000",
52 => "01101001", 53 => "01101011", 54 => "01101100", 55 => "01101101",
56 => "01101110", 57 => "01101111", 58 => "01110000", 59 => "01110001",
60 => "01110010", 61 => "01110011", 62 => "01110100", 63 => "01110101",
64 => "01110110", 65 => "01110111", 66 => "01111000", 67 => "01111001",
68 => "01111010", 69 => "01111011", 70 => "01111100", 71 => "01111101",
72 => "01111110", 73 => "01111111", 74 => "10000000", 75 => "10000001",
76 => "10000010", 77 => "10000011", 78 => "10000100", 79 => "10000101",
80 => "10000110", 81 => "10000111", 82 => "10001000", 83 => "10001001",
84 => "10001010", 85 to 86=> "10001011", 87 => "10001100", 88 => "10001101",
89 => "10001110", 90 => "10001111", 91 => "10010000", 92 => "10010001",
93 to 94=> "10010010", 95 => "10010011", 96 => "10010100", 97 => "10010101",
98 => "10010110", 99 => "10010111", 100 to 101=> "10011000", 102 => "10011001",
103 => "10011010", 104 => "10011011", 105 => "10011100", 106 to 107=> "10011101",
108 => "10011110", 109 => "10011111", 110 => "10100000", 111 to 112=> "10100001",
113 => "10100010", 114 => "10100011", 115 => "10100100", 116 to 117=> "10100101",
118 => "10100110", 119 => "10100111", 120 => "10101000", 121 to 122=> "10101001",
123 => "10101010", 124 => "10101011", 125 to 126=> "10101100", 127 => "10101101",
128 => "10101110", 129 to 130=> "10101111", 131 => "10110000", 132 => "10110001",
133 to 134=> "10110010", 135 => "10110011", 136 => "10110100", 137 to 138=> "10110101",
139 => "10110110", 140 to 141=> "10110111", 142 => "10111000", 143 => "10111001",
144 to 145=> "10111010", 146 => "10111011", 147 to 148=> "10111100", 149 => "10111101",
150 => "10111110", 151 to 152=> "10111111", 153 => "11000000", 154 to 155=> "11000001",
156 => "11000010", 157 to 158=> "11000011", 159 => "11000100", 160 => "11000101",
161 to 162=> "11000110", 163 => "11000111", 164 to 165=> "11001000", 166 => "11001001",
167 to 168=> "11001010", 169 => "11001011", 170 to 171=> "11001100", 172 => "11001101",
173 to 174=> "11001110", 175 => "11001111", 176 to 177=> "11010000", 178 to 179=> "11010001",
180 => "11010010", 181 to 182=> "11010011", 183 => "11010100", 184 to 185=> "11010101",
186 => "11010110", 187 to 188=> "11010111", 189 => "11011000", 190 to 191=> "11011001",
192 to 193=> "11011010", 194 => "11011011", 195 to 196=> "11011100", 197 => "11011101",
198 to 199=> "11011110", 200 to 201=> "11011111", 202 => "11100000", 203 to 204=> "11100001",
205 to 206=> "11100010", 207 => "11100011", 208 to 209=> "11100100", 210 => "11100101",
211 to 212=> "11100110", 213 to 214=> "11100111", 215 => "11101000", 216 to 217=> "11101001",
218 to 219=> "11101010", 220 => "11101011", 221 to 222=> "11101100", 223 to 224=> "11101101",
225 to 226=> "11101110", 227 => "11101111", 228 to 229=> "11110000", 230 to 231=> "11110001",
232 => "11110010", 233 to 234=> "11110011", 235 to 236=> "11110100", 237 to 238=> "11110101",
239 => "11110110", 240 to 241=> "11110111", 242 to 243=> "11111000", 244 to 245=> "11111001",
246 => "11111010", 247 to 248=> "11111011", 249 to 250=> "11111100", 251 to 252=> "11111101",
253 to 254=> "11111110", 255 => "11111111" );
attribute syn_rom_style : string;
attribute syn_rom_style of mem0 : signal is "block_rom";
attribute syn_rom_style of mem1 : signal is "block_rom";
attribute ROM_STYLE : string;
attribute ROM_STYLE of mem0 : signal is "block";
attribute ROM_STYLE of mem1 : signal is "block";
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
memory_access_guard_2: process (addr2)
begin
addr2_tmp <= addr2;
--synthesis translate_off
if (CONV_INTEGER(addr2) > mem_size-1) then
addr2_tmp <= (others => '0');
else
addr2_tmp <= addr2;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem0(CONV_INTEGER(addr0_tmp));
end if;
if (ce1 = '1') then
q1 <= mem0(CONV_INTEGER(addr1_tmp));
end if;
if (ce2 = '1') then
q2 <= mem1(CONV_INTEGER(addr2_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity Loop_loop_height_hbi is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 256;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address2 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of Loop_loop_height_hbi is
component Loop_loop_height_hbi_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR;
addr2 : IN STD_LOGIC_VECTOR;
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR);
end component;
begin
Loop_loop_height_hbi_rom_U : component Loop_loop_height_hbi_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1,
addr2 => address2,
ce2 => ce2,
q2 => q2);
end architecture;
|
mit
|
7f1a013188c14fce76786ec9c8c28402
| 0.55256 | 3.594882 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/CvtColor_1_sectorocq.vhd
| 1 | 2,646 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity CvtColor_1_sectorocq_rom is
generic(
dwidth : integer := 2;
awidth : integer := 3;
mem_size : integer := 6
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of CvtColor_1_sectorocq_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem : mem_array := (
0 to 1=> "01", 2 => "11", 3 to 4=> "00", 5 => "10" );
attribute syn_rom_style : string;
attribute syn_rom_style of mem : signal is "select_rom";
attribute ROM_STYLE : string;
attribute ROM_STYLE of mem : signal is "distributed";
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity CvtColor_1_sectorocq is
generic (
DataWidth : INTEGER := 2;
AddressRange : INTEGER := 6;
AddressWidth : INTEGER := 3);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of CvtColor_1_sectorocq is
component CvtColor_1_sectorocq_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
CvtColor_1_sectorocq_rom_U : component CvtColor_1_sectorocq_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0);
end architecture;
|
mit
|
c67c60cf3aadeb185e1a282700bff3df
| 0.553288 | 3.57085 | false | false | false | false |
Digilent/vivado-library
|
ip/axi_dynclk/src/axi_dynclk_S00_AXI.vhd
| 1 | 19,407 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_dynclk_S00_AXI is
generic (
-- Users to add parameters here
kRefClkFreqHz : natural := 100_000_000;
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
-- Users to add ports here
CTRL_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
STAT_REG :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_O_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FB_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FRAC_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_DIV_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_LOCK_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FLTR_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end axi_dynclk_S00_AXI;
architecture arch_imp of axi_dynclk_S00_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 3;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 8
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := std_logic_vector(to_unsigned(kRefClkFreqHz, 32));
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
--slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"0000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
-- when b"0001" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
-- slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
when b"0010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
-- when b"1000" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 7
-- slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
when others =>
slv_reg0 <= slv_reg0;
--slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"0000" =>
reg_data_out <= slv_reg0;
when b"0001" =>
reg_data_out <= slv_reg1;
when b"0010" =>
reg_data_out <= slv_reg2;
when b"0011" =>
reg_data_out <= slv_reg3;
when b"0100" =>
reg_data_out <= slv_reg4;
when b"0101" =>
reg_data_out <= slv_reg5;
when b"0110" =>
reg_data_out <= slv_reg6;
when b"0111" =>
reg_data_out <= slv_reg7;
when b"1000" =>
reg_data_out <= slv_reg8;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
-- Users to add ports here
CTRL_REG <= slv_reg0;
slv_reg1 <= STAT_REG;
CLK_O_REG <= slv_reg2;
CLK_FB_REG <= slv_reg3;
CLK_FRAC_REG <= slv_reg4;
CLK_DIV_REG <= slv_reg5;
CLK_LOCK_REG <= slv_reg6;
CLK_FLTR_REG <= slv_reg7;
-- User logic ends
end arch_imp;
|
mit
|
99a60138179a3ba9e228423836405a0f
| 0.591024 | 3.423355 | false | false | false | false |
pollow/Multi_Cycle_CPU
|
ipcore_dir/Mem_B/simulation/Mem_B_synth.vhd
| 1 | 8,152 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Mem_B_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY Mem_B_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE Mem_B_synth_ARCH OF Mem_B_synth IS
COMPONENT Mem_B_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 32,
READ_WIDTH => 32 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: Mem_B_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
gpl-3.0
|
43b381410bea5a9f2fb59fcc8cd296a5
| 0.544038 | 3.751496 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/Block_Mat_exit1573_p.vhd
| 1 | 22,957 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Block_Mat_exit1573_p is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
start_full_n : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
start_out : OUT STD_LOGIC;
start_write : OUT STD_LOGIC;
height : IN STD_LOGIC_VECTOR (15 downto 0);
width : IN STD_LOGIC_VECTOR (15 downto 0);
sat : IN STD_LOGIC_VECTOR (7 downto 0);
img0_rows_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img0_rows_V_out_full_n : IN STD_LOGIC;
img0_rows_V_out_write : OUT STD_LOGIC;
img0_cols_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img0_cols_V_out_full_n : IN STD_LOGIC;
img0_cols_V_out_write : OUT STD_LOGIC;
img2_rows_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img2_rows_V_out_full_n : IN STD_LOGIC;
img2_rows_V_out_write : OUT STD_LOGIC;
img2_cols_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img2_cols_V_out_full_n : IN STD_LOGIC;
img2_cols_V_out_write : OUT STD_LOGIC;
img3_rows_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img3_rows_V_out_full_n : IN STD_LOGIC;
img3_rows_V_out_write : OUT STD_LOGIC;
img3_cols_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img3_cols_V_out_full_n : IN STD_LOGIC;
img3_cols_V_out_write : OUT STD_LOGIC;
p_cols_assign_cast_out_out_din : OUT STD_LOGIC_VECTOR (11 downto 0);
p_cols_assign_cast_out_out_full_n : IN STD_LOGIC;
p_cols_assign_cast_out_out_write : OUT STD_LOGIC;
p_rows_assign_cast_out_out_din : OUT STD_LOGIC_VECTOR (11 downto 0);
p_rows_assign_cast_out_out_full_n : IN STD_LOGIC;
p_rows_assign_cast_out_out_write : OUT STD_LOGIC;
sat_out_din : OUT STD_LOGIC_VECTOR (7 downto 0);
sat_out_full_n : IN STD_LOGIC;
sat_out_write : OUT STD_LOGIC );
end;
architecture behav of Block_Mat_exit1573_p is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
signal real_start : STD_LOGIC;
signal start_once_reg : STD_LOGIC := '0';
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "1";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal internal_ap_ready : STD_LOGIC;
signal img0_rows_V_out_blk_n : STD_LOGIC;
signal img0_cols_V_out_blk_n : STD_LOGIC;
signal img2_rows_V_out_blk_n : STD_LOGIC;
signal img2_cols_V_out_blk_n : STD_LOGIC;
signal img3_rows_V_out_blk_n : STD_LOGIC;
signal img3_cols_V_out_blk_n : STD_LOGIC;
signal p_cols_assign_cast_out_out_blk_n : STD_LOGIC;
signal p_rows_assign_cast_out_out_blk_n : STD_LOGIC;
signal sat_out_blk_n : STD_LOGIC;
signal ap_block_state1 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
begin
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_continue = ap_const_logic_1)) then
ap_done_reg <= ap_const_logic_0;
elsif ((not(((sat_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
start_once_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
start_once_reg <= ap_const_logic_0;
else
if (((internal_ap_ready = ap_const_logic_0) and (real_start = ap_const_logic_1))) then
start_once_reg <= ap_const_logic_1;
elsif ((internal_ap_ready = ap_const_logic_1)) then
start_once_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (real_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, sat_out_full_n)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_block_state1_assign_proc : process(real_start, ap_done_reg, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, sat_out_full_n)
begin
ap_block_state1 <= ((sat_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
ap_done_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, sat_out_full_n)
begin
if ((not(((sat_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_idle_assign_proc : process(real_start, ap_CS_fsm_state1)
begin
if (((real_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready <= internal_ap_ready;
img0_cols_V_out_blk_n_assign_proc : process(ap_CS_fsm_state1, img0_cols_V_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
img0_cols_V_out_blk_n <= img0_cols_V_out_full_n;
else
img0_cols_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img0_cols_V_out_din <= width;
img0_cols_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, sat_out_full_n)
begin
if ((not(((sat_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img0_cols_V_out_write <= ap_const_logic_1;
else
img0_cols_V_out_write <= ap_const_logic_0;
end if;
end process;
img0_rows_V_out_blk_n_assign_proc : process(ap_CS_fsm_state1, img0_rows_V_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
img0_rows_V_out_blk_n <= img0_rows_V_out_full_n;
else
img0_rows_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img0_rows_V_out_din <= height;
img0_rows_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, sat_out_full_n)
begin
if ((not(((sat_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img0_rows_V_out_write <= ap_const_logic_1;
else
img0_rows_V_out_write <= ap_const_logic_0;
end if;
end process;
img2_cols_V_out_blk_n_assign_proc : process(ap_CS_fsm_state1, img2_cols_V_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
img2_cols_V_out_blk_n <= img2_cols_V_out_full_n;
else
img2_cols_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img2_cols_V_out_din <= width;
img2_cols_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, sat_out_full_n)
begin
if ((not(((sat_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img2_cols_V_out_write <= ap_const_logic_1;
else
img2_cols_V_out_write <= ap_const_logic_0;
end if;
end process;
img2_rows_V_out_blk_n_assign_proc : process(ap_CS_fsm_state1, img2_rows_V_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
img2_rows_V_out_blk_n <= img2_rows_V_out_full_n;
else
img2_rows_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img2_rows_V_out_din <= height;
img2_rows_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, sat_out_full_n)
begin
if ((not(((sat_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img2_rows_V_out_write <= ap_const_logic_1;
else
img2_rows_V_out_write <= ap_const_logic_0;
end if;
end process;
img3_cols_V_out_blk_n_assign_proc : process(ap_CS_fsm_state1, img3_cols_V_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
img3_cols_V_out_blk_n <= img3_cols_V_out_full_n;
else
img3_cols_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img3_cols_V_out_din <= width;
img3_cols_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, sat_out_full_n)
begin
if ((not(((sat_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img3_cols_V_out_write <= ap_const_logic_1;
else
img3_cols_V_out_write <= ap_const_logic_0;
end if;
end process;
img3_rows_V_out_blk_n_assign_proc : process(ap_CS_fsm_state1, img3_rows_V_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
img3_rows_V_out_blk_n <= img3_rows_V_out_full_n;
else
img3_rows_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img3_rows_V_out_din <= height;
img3_rows_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, sat_out_full_n)
begin
if ((not(((sat_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img3_rows_V_out_write <= ap_const_logic_1;
else
img3_rows_V_out_write <= ap_const_logic_0;
end if;
end process;
internal_ap_ready_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, sat_out_full_n)
begin
if ((not(((sat_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
internal_ap_ready <= ap_const_logic_1;
else
internal_ap_ready <= ap_const_logic_0;
end if;
end process;
p_cols_assign_cast_out_out_blk_n_assign_proc : process(ap_CS_fsm_state1, p_cols_assign_cast_out_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
p_cols_assign_cast_out_out_blk_n <= p_cols_assign_cast_out_out_full_n;
else
p_cols_assign_cast_out_out_blk_n <= ap_const_logic_1;
end if;
end process;
p_cols_assign_cast_out_out_din <= width(12 - 1 downto 0);
p_cols_assign_cast_out_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, sat_out_full_n)
begin
if ((not(((sat_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_cols_assign_cast_out_out_write <= ap_const_logic_1;
else
p_cols_assign_cast_out_out_write <= ap_const_logic_0;
end if;
end process;
p_rows_assign_cast_out_out_blk_n_assign_proc : process(ap_CS_fsm_state1, p_rows_assign_cast_out_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
p_rows_assign_cast_out_out_blk_n <= p_rows_assign_cast_out_out_full_n;
else
p_rows_assign_cast_out_out_blk_n <= ap_const_logic_1;
end if;
end process;
p_rows_assign_cast_out_out_din <= height(12 - 1 downto 0);
p_rows_assign_cast_out_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, sat_out_full_n)
begin
if ((not(((sat_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_rows_assign_cast_out_out_write <= ap_const_logic_1;
else
p_rows_assign_cast_out_out_write <= ap_const_logic_0;
end if;
end process;
real_start_assign_proc : process(ap_start, start_full_n, start_once_reg)
begin
if (((start_full_n = ap_const_logic_0) and (start_once_reg = ap_const_logic_0))) then
real_start <= ap_const_logic_0;
else
real_start <= ap_start;
end if;
end process;
sat_out_blk_n_assign_proc : process(ap_CS_fsm_state1, sat_out_full_n)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state1)) then
sat_out_blk_n <= sat_out_full_n;
else
sat_out_blk_n <= ap_const_logic_1;
end if;
end process;
sat_out_din <= sat;
sat_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img0_rows_V_out_full_n, img0_cols_V_out_full_n, img2_rows_V_out_full_n, img2_cols_V_out_full_n, img3_rows_V_out_full_n, img3_cols_V_out_full_n, p_cols_assign_cast_out_out_full_n, p_rows_assign_cast_out_out_full_n, sat_out_full_n)
begin
if ((not(((sat_out_full_n = ap_const_logic_0) or (p_rows_assign_cast_out_out_full_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (p_cols_assign_cast_out_out_full_n = ap_const_logic_0) or (img3_cols_V_out_full_n = ap_const_logic_0) or (img3_rows_V_out_full_n = ap_const_logic_0) or (img2_cols_V_out_full_n = ap_const_logic_0) or (img2_rows_V_out_full_n = ap_const_logic_0) or (img0_cols_V_out_full_n = ap_const_logic_0) or (img0_rows_V_out_full_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
sat_out_write <= ap_const_logic_1;
else
sat_out_write <= ap_const_logic_0;
end if;
end process;
start_out <= real_start;
start_write_assign_proc : process(real_start, start_once_reg)
begin
if (((start_once_reg = ap_const_logic_0) and (real_start = ap_const_logic_1))) then
start_write <= ap_const_logic_1;
else
start_write <= ap_const_logic_0;
end if;
end process;
end behav;
|
mit
|
e488d1152900f5c14875bdc7659a1620
| 0.622555 | 2.502125 | false | false | false | false |
hangmann/fpga-heater
|
simple_timebase_v1_00_a/hdl/vhdl/user_logic.vhd
| 1 | 1,660 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
entity user_logic is
generic
(
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 1
);
port
(
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
architecture IMP of user_logic is
signal timer : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
begin
process (Bus2IP_Clk, Bus2IP_Reset) is
begin
if Bus2IP_Reset = '1' then
timer <= (others => '0');
elsif rising_edge(Bus2IP_Clk) then
timer <= timer + 1;
if Bus2IP_WrCE(0) = '1' then
timer <= (others => '0');
end if;
end if;
end process;
IP2Bus_Data <= timer;
IP2Bus_WrAck <= Bus2IP_WrCE(0);
IP2Bus_RdAck <= Bus2IP_RdCE(0);
IP2Bus_Error <= '0';
end IMP;
|
mit
|
b55940643375065535198d0224e9d4eb
| 0.56506 | 2.857143 | false | false | false | false |
Digilent/vivado-library
|
ip/video_scaler/hdl/vhdl/video_scaler_mul_lbW.vhd
| 1 | 1,506 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity video_scaler_mul_lbW_DSP48_0 is
port (
a: in std_logic_vector(20 - 1 downto 0);
b: in std_logic_vector(8 - 1 downto 0);
p: out std_logic_vector(28 - 1 downto 0));
end entity;
architecture behav of video_scaler_mul_lbW_DSP48_0 is
signal a_cvt: signed(20 - 1 downto 0);
signal b_cvt: unsigned(8 - 1 downto 0);
signal p_cvt: signed(28 - 1 downto 0);
begin
a_cvt <= signed(a);
b_cvt <= unsigned(b);
p_cvt <= signed (resize(unsigned (signed (a_cvt) * signed ('0' & b_cvt)), 28));
p <= std_logic_vector(p_cvt);
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity video_scaler_mul_lbW is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of video_scaler_mul_lbW is
component video_scaler_mul_lbW_DSP48_0 is
port (
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
video_scaler_mul_lbW_DSP48_0_U : component video_scaler_mul_lbW_DSP48_0
port map (
a => din0,
b => din1,
p => dout);
end architecture;
|
mit
|
b313ae0d22deec4b015c3c9533578f72
| 0.60425 | 3.124481 | false | false | false | false |
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