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hardware/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_vdma_1_0/synth/design_1_axi_vdma_1_0.vhd
| 1 | 28,345 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_vdma:6.2
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_vdma_v6_2;
USE axi_vdma_v6_2.axi_vdma;
ENTITY design_1_axi_vdma_1_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
s_axis_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC
);
END design_1_axi_vdma_1_0;
ARCHITECTURE design_1_axi_vdma_1_0_arch OF design_1_axi_vdma_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_vdma_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_vdma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_VIDPRMTR_READS : INTEGER;
C_DYNAMIC_RESOLUTION : INTEGER;
C_NUM_FSTORES : INTEGER;
C_USE_FSYNC : INTEGER;
C_USE_MM2S_FSYNC : INTEGER;
C_USE_S2MM_FSYNC : INTEGER;
C_FLUSH_ON_FSYNC : INTEGER;
C_INCLUDE_INTERNAL_GENLOCK : INTEGER;
C_INCLUDE_SG : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_MM2S_GENLOCK_MODE : INTEGER;
C_MM2S_GENLOCK_NUM_MASTERS : INTEGER;
C_MM2S_GENLOCK_REPEAT_EN : INTEGER;
C_MM2S_SOF_ENABLE : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_LINEBUFFER_DEPTH : INTEGER;
C_MM2S_LINEBUFFER_THRESH : INTEGER;
C_MM2S_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TUSER_BITS : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_S2MM_GENLOCK_MODE : INTEGER;
C_S2MM_GENLOCK_NUM_MASTERS : INTEGER;
C_S2MM_GENLOCK_REPEAT_EN : INTEGER;
C_S2MM_SOF_ENABLE : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_LINEBUFFER_DEPTH : INTEGER;
C_S2MM_LINEBUFFER_THRESH : INTEGER;
C_S2MM_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TUSER_BITS : INTEGER;
C_ENABLE_DEBUG_ALL : INTEGER;
C_ENABLE_DEBUG_INFO_0 : INTEGER;
C_ENABLE_DEBUG_INFO_1 : INTEGER;
C_ENABLE_DEBUG_INFO_2 : INTEGER;
C_ENABLE_DEBUG_INFO_3 : INTEGER;
C_ENABLE_DEBUG_INFO_4 : INTEGER;
C_ENABLE_DEBUG_INFO_5 : INTEGER;
C_ENABLE_DEBUG_INFO_6 : INTEGER;
C_ENABLE_DEBUG_INFO_7 : INTEGER;
C_ENABLE_DEBUG_INFO_8 : INTEGER;
C_ENABLE_DEBUG_INFO_9 : INTEGER;
C_ENABLE_DEBUG_INFO_10 : INTEGER;
C_ENABLE_DEBUG_INFO_11 : INTEGER;
C_ENABLE_DEBUG_INFO_12 : INTEGER;
C_ENABLE_DEBUG_INFO_13 : INTEGER;
C_ENABLE_DEBUG_INFO_14 : INTEGER;
C_ENABLE_DEBUG_INFO_15 : INTEGER;
C_INSTANCE : STRING;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
s_axis_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_fsync : IN STD_LOGIC;
mm2s_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_fsync : IN STD_LOGIC;
s2mm_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_buffer_empty : OUT STD_LOGIC;
mm2s_buffer_almost_empty : OUT STD_LOGIC;
s2mm_buffer_full : OUT STD_LOGIC;
s2mm_buffer_almost_full : OUT STD_LOGIC;
mm2s_fsync_out : OUT STD_LOGIC;
s2mm_fsync_out : OUT STD_LOGIC;
mm2s_prmtr_update : OUT STD_LOGIC;
s2mm_prmtr_update : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_vdma_tstvec : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT axi_vdma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_vdma_1_0_arch: ARCHITECTURE IS "axi_vdma,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_vdma_1_0_arch : ARCHITECTURE IS "design_1_axi_vdma_1_0,axi_vdma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_vdma_1_0_arch: ARCHITECTURE IS "design_1_axi_vdma_1_0,axi_vdma,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_vdma,x_ipVersion=6.2,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=9,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=0,C_ENABLE_VIDPRMTR_READS=1,C_DYNAMIC_RESOLUTION=1,C_NUM_FSTORES=3,C_USE_FSYNC=1,C_USE_MM2S_FSYNC=0,C_USE_S2MM_FSYNC=2,C_FLUSH_ON_FSYNC=1,C_INCLUDE_INTERNAL_GENLOCK=1,C_INCLUDE_SG=0,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=32,C_INCLUDE_MM2S=1,C_MM2S_GENLOCK_MODE=3,C_MM2S_GENLOCK_NUM_MASTERS=1,C_MM2S_GENLOCK_REPEAT_EN=0,C_MM2S_SOF_ENABLE=1,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_MM2S_SF=0,C_MM2S_LINEBUFFER_DEPTH=512,C_MM2S_LINEBUFFER_THRESH=4,C_MM2S_MAX_BURST_LENGTH=8,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=64,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_M_AXIS_MM2S_TUSER_BITS=1,C_INCLUDE_S2MM=1,C_S2MM_GENLOCK_MODE=2,C_S2MM_GENLOCK_NUM_MASTERS=1,C_S2MM_GENLOCK_REPEAT_EN=1,C_S2MM_SOF_ENABLE=1,C_INCLUDE_S2MM_DRE=0,C_INCLUDE_S2MM_SF=1,C_S2MM_LINEBUFFER_DEPTH=512,C_S2MM_LINEBUFFER_THRESH=4,C_S2MM_MAX_BURST_LENGTH=8,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=32,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_S_AXIS_S2MM_TUSER_BITS=1,C_ENABLE_DEBUG_ALL=0,C_ENABLE_DEBUG_INFO_0=0,C_ENABLE_DEBUG_INFO_1=0,C_ENABLE_DEBUG_INFO_2=0,C_ENABLE_DEBUG_INFO_3=0,C_ENABLE_DEBUG_INFO_4=0,C_ENABLE_DEBUG_INFO_5=0,C_ENABLE_DEBUG_INFO_6=1,C_ENABLE_DEBUG_INFO_7=1,C_ENABLE_DEBUG_INFO_8=0,C_ENABLE_DEBUG_INFO_9=0,C_ENABLE_DEBUG_INFO_10=0,C_ENABLE_DEBUG_INFO_11=0,C_ENABLE_DEBUG_INFO_12=0,C_ENABLE_DEBUG_INFO_13=0,C_ENABLE_DEBUG_INFO_14=1,C_ENABLE_DEBUG_INFO_15=1,C_INSTANCE=axi_vdma,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXIS_S2MM_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_out: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_OUT FRAME_PTR";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_frame_ptr_out: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 S2MM_FRAME_PTR_OUT FRAME_PTR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TUSER";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
BEGIN
U0 : axi_vdma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 9,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_VIDPRMTR_READS => 1,
C_DYNAMIC_RESOLUTION => 1,
C_NUM_FSTORES => 3,
C_USE_FSYNC => 1,
C_USE_MM2S_FSYNC => 0,
C_USE_S2MM_FSYNC => 2,
C_FLUSH_ON_FSYNC => 1,
C_INCLUDE_INTERNAL_GENLOCK => 1,
C_INCLUDE_SG => 0,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_INCLUDE_MM2S => 1,
C_MM2S_GENLOCK_MODE => 3,
C_MM2S_GENLOCK_NUM_MASTERS => 1,
C_MM2S_GENLOCK_REPEAT_EN => 0,
C_MM2S_SOF_ENABLE => 1,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_MM2S_SF => 0,
C_MM2S_LINEBUFFER_DEPTH => 512,
C_MM2S_LINEBUFFER_THRESH => 4,
C_MM2S_MAX_BURST_LENGTH => 8,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 64,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_M_AXIS_MM2S_TUSER_BITS => 1,
C_INCLUDE_S2MM => 1,
C_S2MM_GENLOCK_MODE => 2,
C_S2MM_GENLOCK_NUM_MASTERS => 1,
C_S2MM_GENLOCK_REPEAT_EN => 1,
C_S2MM_SOF_ENABLE => 1,
C_INCLUDE_S2MM_DRE => 0,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_LINEBUFFER_DEPTH => 512,
C_S2MM_LINEBUFFER_THRESH => 4,
C_S2MM_MAX_BURST_LENGTH => 8,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_TUSER_BITS => 1,
C_ENABLE_DEBUG_ALL => 0,
C_ENABLE_DEBUG_INFO_0 => 0,
C_ENABLE_DEBUG_INFO_1 => 0,
C_ENABLE_DEBUG_INFO_2 => 0,
C_ENABLE_DEBUG_INFO_3 => 0,
C_ENABLE_DEBUG_INFO_4 => 0,
C_ENABLE_DEBUG_INFO_5 => 0,
C_ENABLE_DEBUG_INFO_6 => 1,
C_ENABLE_DEBUG_INFO_7 => 1,
C_ENABLE_DEBUG_INFO_8 => 0,
C_ENABLE_DEBUG_INFO_9 => 0,
C_ENABLE_DEBUG_INFO_10 => 0,
C_ENABLE_DEBUG_INFO_11 => 0,
C_ENABLE_DEBUG_INFO_12 => 0,
C_ENABLE_DEBUG_INFO_13 => 0,
C_ENABLE_DEBUG_INFO_14 => 1,
C_ENABLE_DEBUG_INFO_15 => 1,
C_INSTANCE => "axi_vdma",
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axis_mm2s_aclk => m_axis_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
s_axis_s2mm_aclk => s_axis_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
mm2s_fsync => '0',
mm2s_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
mm2s_frame_ptr_out => mm2s_frame_ptr_out,
s2mm_fsync => '0',
s2mm_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
s2mm_frame_ptr_out => s2mm_frame_ptr_out,
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tuser => m_axis_mm2s_tuser,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tuser => s_axis_s2mm_tuser,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut
);
END design_1_axi_vdma_1_0_arch;
|
gpl-2.0
|
6c26c1c25ca172c85e5ee241bd95e425
| 0.677509 | 2.730995 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ipshared/f627/hdl/axi_ethernetlite_v3_0_vh_rfs.vhd
| 1 | 587,018 |
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 08/01 -- First version
--
-- FO 11/14/01 -- Cosmetic improvements
--
-- FO 02/22/02 -- Switched from MUXCY_L primitive to MUXCY.
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD : in std_logic; -- Enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD.)
);
end ld_arith_reg;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <= '0' when C_ADD_SUB_NOT else OP;
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
-- Adder case
------------------------------------------------------------------------
Q_I_GEN_ADD: if C_ADD_SUB_NOT generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case
------------------------------------------------------------------------
Q_I_GEN_SUB: if not C_ADD_SUB_NOT generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= LOAD or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
-- mux_onehot_f - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot_f.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines.
--
-- Please refer to the entity interface while reading the
-- remainder of this description.
--
-- If n is the index of the single select line of S(0 to C_NB-1)
-- that is asserted, then
--
-- Y(0 to C_DW-1) <= D(n*C_DW to n*C_DW + C_DW -1)
--
-- That is, Y selects the nth group of C_DW consecutive
-- bits of D.
--
-- Note that C_NB = 1 is handled as a special case in which
-- Y <= D, without regard to the select line, S.
--
-- The Implementation depends on the C_FAMILY parameter.
-- If the target family supports the needed primitives,
-- a carry-chain structure will be implemented. Otherwise,
-- an implementation dependent on synthesis inferral will
-- be generated.
--
-------------------------------------------------------------------------------
-- Structure:
-- mux_onehot_f
--------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 11/30/05 -- First version derived from mux_onehot.vhd
-- -- by BLT and ALS.
--
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Generic and Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics and Ports
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- input D -- input data bus
-- input S -- input select bus
-- output Y -- output bus
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- Y = (Bus0Data0, Bus0Data1) if S(0)=1 else
-- (Bus1Data0, Bus1Data1) if S(1)=1 else
-- (Bus2Data0, Bus2Data1) if S(2)=1 else
-- (Bus3Data0, Bus3Data1) if S(3)=1
--
-- Only one bit of S should be asserted at a time.
--
-------------------------------------------------------------------------------
entity mux_onehot_f is
generic( C_DW: integer := 32;
C_NB: integer := 5;
C_FAMILY : string := "virtexe");
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot_f;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture imp of mux_onehot_f is
constant NLS : natural := 6;--native_lut_size(fam_as_string => C_FAMILY,
-- no_lut_return_val => 2*C_NB);
function lut_val(D, S : std_logic_vector) return std_logic is
variable rn : std_logic := '0';
begin
for i in D'range loop
rn := rn or (S(i) and D(i));
end loop;
return not rn;
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-----------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*C_NB-1);
signal sel: std_logic_vector(0 to C_DW*C_NB-1);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin
-- Reorder data buses
WA_GEN : if C_DW > 0 generate -- XST WA
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
end generate;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
GEN: if C_NB > 1 generate
constant BPL : positive := NLS / 2; -- Buses per LUT is the native lut
-- size divided by two.signals per bus.
constant NUMLUTS : positive := (C_NB+(BPL-1))/BPL;
begin
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout : std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '0';
NUM_BUSES_GEN: for j in 0 to NUMLUTS - 1 generate
constant BTL : positive := min(BPL, C_NB - j*BPL);
-- Number of Buses This Lut (for last LUT this may be less than BPL)
begin
lutout(j) <= lut_val(D => Dreord(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1),
S => sel(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1)
);
MUXCY_GEN : if NUMLUTS > 1 generate
MUXCY_I : component MUXCY
port map (CI=>cyout(j),
DI=> '1',
S=>lutout(j),
O=>cyout(j+1));
end generate;
end generate;
Y(i) <= cyout(NUMLUTS) when NUMLUTS > 1 else not lutout(0); -- If just one
-- LUT, then take value from
-- lutout rather than cyout.
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
end imp;
-------------------------------------------------------------------------------
-- mac_pkg - Package
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : mac_pkg.vhd
-- Version : v2.0
-- Description : This file contains the constants used in the design of the
-- Ethernet MAC.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package mac_pkg is
type tx_state_name is
(idle,txEnCheck,loadByteCnt,checkByteCnt,checkByteCntOvrWrtSrcAdr,
requestFifoRd,requestFifoRdOvrWrtSrcAdr,waitFifoEmpty,decByteCnt,
decByteCntOvrWrtSrcAdr,checkBusFifoFull,checkBusFifoFullOvrWrtSrcAdr,
loadBusFifo,loadBusFifoOvrWrtSrcAdr,txDone,preamble,SFD,loadBusFifoSrcAdr,
loadBusFifoJam,checkBusFifoFullSrcAdr,loadBusFifoPad,checkBusFifoFullPad,
loadBusFifoCrc,checkBusFifoFullCrc,checkBusFifoFullJam,lateCollision,
excessDeferal,collisionRetry,cleanPacketCheckByteCnt,
cleanPacketRequestFifoRd,cleanPacketDecByteCnt,retryWaitFifoEmpty,
retryReset,tlrRead,checkBusFifoFullSFD,txDone2);
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant XEMAC_MAJOR_VERSION : std_logic_vector(0 to 3) := "0001"; -- 1
-- binary encoded major version number
constant XEMAC_MINOR_VERSION : std_logic_vector(0 to 6) := "0000000";-- 00
-- binary encoded minor version number
constant XEMAC_REVISION : std_logic_vector(0 to 4) := "00001";-- rev b
-- binary encoded revision letter. a = "00000" z = "11001"
constant XEMAC_BLOCK_TYPE : std_logic_vector(0 to 7) := "00000001";-- 1
-- value that indentifies this device as a 10/100 Ethernet IP
constant RESET_ACTIVE : std_logic := '1';
-- the RESET_ACTIVE constant should denote the
-- logic level of an active reset
constant MinimumPacketLength : std_logic_vector (0 to 15) := "0000000000111100";
-- 60 = 3c in hex
constant MAXENetPktLength : natural := 1500;
constant MINENetPktLength : natural := 46;
-------------------------------------------------------------------------------
-- these constants give data and address bus sizes for 3 widths of data
-- such that the largest ethernet frame will be addressable
-------------------------------------------------------------------------------
constant dbw4 : natural := 4;
constant abw4 : natural := 12;
constant dbw8 : natural := 8;
constant abw8 : natural := 11;
constant dbw16 : natural := 16;
constant abw16 : natural := 10;
constant CRCDataWidth : natural := 32; -- crc output data width
subtype UNSIGNED30BIT is std_logic_vector (0 to 29);
subtype UNSIGNED29BIT is std_logic_vector (0 to 28);
subtype UNSIGNED27BIT is std_logic_vector (0 to 26);
subtype UNSIGNED24BIT is std_logic_vector (0 to 23);
subtype UNSIGNED23BIT is std_logic_vector (0 to 22);
subtype UNSIGNED22BIT is std_logic_vector (0 to 21);
subtype UNSIGNED21BIT is std_logic_vector (0 to 20);
subtype UNSIGNED20BIT is std_logic_vector (0 to 19);
subtype UNSIGNED18BIT is std_logic_vector (0 to 17);
subtype UNSIGNED16BIT is std_logic_vector (0 to 15);
subtype UNSIGNED12BIT is std_logic_vector (0 to 11);
subtype UNSIGNED11BIT is std_logic_vector (0 to 10);
subtype UNSIGNED10BIT is std_logic_vector (0 to 9);
subtype UNSIGNED9BIT is std_logic_vector (0 to 8);
subtype UNSIGNED8BIT is std_logic_vector (0 to 7);
subtype UNSIGNED6BIT is std_logic_vector (0 to 5);
subtype ENetAddr is std_logic_vector (47 downto 0); -- ethernet address
subtype IPAddress is std_logic_vector(31 downto 0);
subtype TwoBit is std_logic_vector (1 downto 0); -- half a Nibble
subtype Nibble is std_logic_vector (3 downto 0); -- half a byte
subtype Byte is std_logic_vector (7 downto 0); -- single byte
subtype Monk is std_logic_vector (8 downto 0); -- monkey (500, for 512)
subtype Deck is std_logic_vector (9 downto 0); -- a 10 digit binary number
subtype Word is std_logic_vector (15 downto 0); -- double byte
subtype DWord is std_logic_vector (31 downto 0); -- quadruple byte
subtype CRCData is std_logic_vector(CRCDataWidth - 1 downto 0);
-------------------------------------------------------------------------------
-- these standard types are used for the address bus declarations
-------------------------------------------------------------------------------
subtype NibbleAddress is std_logic_vector(abw4 - 1 downto 0);
subtype ByteAddress is std_logic_vector(abw8 - 1 downto 0);
subtype WordAddress is std_logic_vector(abw16 - 1 downto 0);
function getENetAddr (eaddr : string) return ENetAddr;
function revBitOrder (arg : std_logic_vector) return std_logic_vector;
function convENetAddr(arg : ENetAddr) return bit_vector;
-- By ben 06/28/2000
function revNibOrder(arg : std_logic_vector) return std_logic_vector;
-- by ben 07/04/2000
function getIPAddr (ipaddr : string) return IPAddress;
function allZeroes (inp : std_logic_vector) return boolean;
function allOnes (inp : std_logic_vector) return boolean;
function zExtend (arg1 : std_logic_vector; size : natural)
return std_logic_vector;
function maxNat (arg1, arg2 : natural) return natural;
function netOrder (arg : Word) return Word; --by Ying
function netOrder (arg : bit_vector(15 downto 0)) return bit_vector;
function GetInitString4 ( idx : integer;
init_00 : bit_vector(15 downto 0); init_01 : bit_vector(15 downto 0);
init_02 : bit_vector(15 downto 0); init_03 : bit_vector(15 downto 0))
return string;
function GetInitVector4 ( idx : integer;
init_00 : bit_vector(15 downto 0); init_01 : bit_vector(15 downto 0);
init_02 : bit_vector(15 downto 0); init_03 : bit_vector(15 downto 0))
return bit_vector;
function to_string (bv : bit_vector) return string;
function to_string (b : bit) return string;
function to_character (bv : bit_vector(3 downto 0)) return character;
end mac_pkg;
package body mac_pkg is
-- coverage off
-- Convert 4-bit vector to a character
function to_character (
bv : bit_vector(3 downto 0))
return character is
begin -- to_character
case bv is
when b"0000" => return '0';
when b"0001" => return '1';
when b"0010" => return '2';
when b"0011" => return '3';
when b"0100" => return '4';
when b"0101" => return '5';
when b"0110" => return '6';
when b"0111" => return '7';
when b"1000" => return '8';
when b"1001" => return '9';
when b"1010" => return 'a';
when b"1011" => return 'b';
when b"1100" => return 'c';
when b"1101" => return 'd';
when b"1110" => return 'e';
when b"1111" => return 'f';
end case;
end to_character;
-- Convert n-bits vector to n/4-character string
function to_string (bv : bit_vector) return string is
constant strlen : integer := bv'length / 4;
variable str : string(1 to strlen);
begin -- to_string
for i in 0 to strlen - 1 loop
str(strlen-i) := to_character(bv((i * 4) + 3 downto (i * 4)));
end loop; -- i
return str;
end to_string;
-- Convert 1-bit to 1-character string
function to_string (b : bit) return string is
begin
case b is
when '0' => return "0";
when '1' => return "1";
when others => assert false report "unrecognised bit value" severity failure;
end case;
return "0";
end to_string;
function netOrder (arg : bit_vector(15 downto 0))
return bit_vector is
variable res : bit_vector(15 downto 0);
begin -- netOrder
res(15 downto 12) := arg(11 downto 8);
res(11 downto 8) := arg(15 downto 12);
res(7 downto 4) := arg(3 downto 0);
res(3 downto 0) := arg(7 downto 4);
return res;
end netOrder;
-- Generate the label string for LUT ROM 16x4 from the init strings
function GetInitString4 ( idx : integer;
init_00 : bit_vector(15 downto 0); init_01 : bit_vector(15 downto 0);
init_02 : bit_vector(15 downto 0); init_03 : bit_vector(15 downto 0))
return string is
variable bitvalue : bit_vector(15 downto 0) ;
begin
bitvalue(0) := INIT_00(idx+12); bitvalue(1) := INIT_00(idx+8);
bitvalue(2) := INIT_00(idx+4); bitvalue(3) := INIT_00(idx);
bitvalue(4) := INIT_01(idx+12); bitvalue(5) := INIT_01(idx+8);
bitvalue(6) := INIT_01(idx+4); bitvalue(7) := INIT_01(idx);
bitvalue(8) := INIT_02(idx+12); bitvalue(9) := INIT_02(idx+8);
bitvalue(10) := INIT_02(idx+4); bitvalue(11) := INIT_02(idx);
bitvalue(12) := INIT_03(idx+12); bitvalue(13) := INIT_03(idx+8);
bitvalue(14) := INIT_03(idx+4); bitvalue(15) := INIT_03(idx);
return to_string(bitvalue);
end function GetInitString4;
-- Generate the generic init vector for the LUT ROM 16x4 from the
-- init strings
function GetInitVector4( idx : integer;
init_00 : bit_vector(15 downto 0); init_01 : bit_vector(15 downto 0);
init_02 : bit_vector(15 downto 0); init_03 : bit_vector(15 downto 0))
return bit_vector is
variable bitvalue : bit_vector(15 downto 0) ;
begin
bitvalue(0) := INIT_00(idx+12); bitvalue(1) := INIT_00(idx+8);
bitvalue(2) := INIT_00(idx+4); bitvalue(3) := INIT_00(idx);
bitvalue(4) := INIT_01(idx+12); bitvalue(5) := INIT_01(idx+8);
bitvalue(6) := INIT_01(idx+4); bitvalue(7) := INIT_01(idx);
bitvalue(8) := INIT_02(idx+12); bitvalue(9) := INIT_02(idx+8);
bitvalue(10) := INIT_02(idx+4); bitvalue(11) := INIT_02(idx);
bitvalue(12) := INIT_03(idx+12); bitvalue(13) := INIT_03(idx+8);
bitvalue(14) := INIT_03(idx+4); bitvalue(15) := INIT_03(idx);
return bitvalue;
end function GetInitVector4;
function conv_std_logic_vector (ch : character) return std_logic_vector is
begin
case ch is
when '0' => return "0000";
when '1' => return "0001";
when '2' => return "0010";
when '3' => return "0011";
when '4' => return "0100";
when '5' => return "0101";
when '6' => return "0110";
when '7' => return "0111";
when '8' => return "1000";
when '9' => return "1001";
when 'a' => return "1010";
when 'b' => return "1011";
when 'c' => return "1100";
when 'd' => return "1101";
when 'e' => return "1110";
when 'f' => return "1111";
when others => assert false report "unrecognised character"
severity failure;
end case;
return "0000";
end conv_std_logic_vector;
function getENetAddr (eaddr : string) return ENetAddr is
variable tmp : ENetAddr := (others => '0');
variable bptr : natural := 0;
variable nptr : natural := 0;
variable indx : natural := 0;
begin -- getENetAddr
tmp := (others => '0');
bptr := 0;
nptr := 0;
indx := 0;
if eaddr'length = 17 then
lp0 : for i in eaddr'reverse_range loop
-- lsbyte first
if eaddr(i) = ':' then
bptr := bptr + 1;
nptr := 0;
else
indx := (bptr * 8) + (nptr * 4);
tmp(indx + 3 downto indx) := conv_std_logic_vector(eaddr(i));
nptr := nptr + 1;
end if;
end loop lp0;
else
assert false report "ethernet address format is 01 : 23 : 45 : 67 : 89 : ab msb- > lsb" severity failure;
end if;
return tmp;
end getENetAddr;
-------------------------------------------------------------------------------
-- A function which can change the order of ENetAddr to
-- the order of smallrom init -- BY ben 06/28
-------------------------------------------------------------------------------
function convENetAddr(arg: ENetAddr) return bit_vector is
variable tmp : std_logic_vector(63 downto 0) :=(others => '0');
begin
lp0: for i in 0 to 11 loop
tmp(59-i) := arg(3 + i*4);
tmp(43 -i) := arg(2 + i*4);
tmp(27 -i) := arg(1 + i*4);
tmp(11 -i) := arg(i*4);
end loop lp0;
return to_bitvector(tmp);
end convENetAddr;
-------------------------------------------------------------------------------
-- A function which can reverse the bit order
-- order -- BY ben 07/04
-------------------------------------------------------------------------------
function revBitOrder( arg : std_logic_vector) return std_logic_vector is -- By ben 07/04/2000
variable tmp : std_logic_vector(arg'range);
begin
lp0 : for i in arg'range loop
tmp(arg'high - i) := arg(i);
end loop lp0;
return tmp;
end revBitOrder;
-------------------------------------------------------------------------------
-- A function which can swap the Nibble order
-- order -- BY ben 07/04
-------------------------------------------------------------------------------
function swapNibbles (
arg : std_logic_vector)
return std_logic_vector is
variable tmp : std_logic_vector(arg'length -1 downto 0);
variable j : integer;
begin -- swapNibbles
for i in 0 to (arg'length / 8) - 1 loop
j := i * 8;
tmp(j + 3 downto j) := arg(j + 7 downto j + 4);
tmp(j + 7 downto j + 4) := arg(j + 3 downto j);
end loop; -- i
return tmp;
end swapNibbles;
-------------------------------------------------------------------------------
-- A function which can reverse the Nibble order
-- order -- BY ben 07/04
-------------------------------------------------------------------------------
function revNibOrder( arg : std_logic_vector) return std_logic_vector is -- By ben 07/04/2000
variable tmp : std_logic_vector(arg'high downto 0); -- length is numNubs
variable numNibs : integer;
begin
numNibs := arg'length/4;
lp0: for i in 0 to numNibs -1 loop
tmp( (4*(numNibs-i)-1) downto 4*(numNibs-i-1) ) := arg( (4*i+3) downto 4*i);
end loop lp0;
return tmp ;
end revNibOrder;
-------------------------------------------------------------------------------
-- Afunction to parse IP address
-------------------------------------------------------------------------------
function getIPAddr (ipaddr : string) return IPAddress is
variable tmp : IPAddress := (others => '0');
variable bptr : natural := 3;
variable nptr : natural := 2;
variable indx : natural := 0;
begin
bptr := 3;
nptr := 2;
indx := 0;
-- similar to above, take a fixed length string and parse it for
-- expected characters. We anticipate hex numbers if the format,
-- hh.hh.hh.hh
if ipaddr'length = 11 then
for i in ipaddr'range loop
if ipaddr(i) = '.' then
bptr := bptr - 1;
nptr := 2;
else
indx := (bptr * 8) + ((nptr - 1) * 4);
tmp(indx + 3 downto indx) := conv_std_logic_vector(ipaddr(i));
nptr := nptr - 1;
end if;
end loop; -- i
else
assert false report "IP address format is 01.23.45.67 msb- > lsb" severity failure;
end if;
return tmp;
end getIPAddr;
-------------------------------------------------------------------------------
-- couple of useful functions, move them to utils eventually
-------------------------------------------------------------------------------
function allZeroes (inp : std_logic_vector) return boolean is
variable t : boolean := true;
begin
t := true; -- for synopsys
for i in inp'range loop
if inp(i) = '1' then
t := false;
end if;
end loop;
return t;
end allZeroes;
function allOnes (inp : std_logic_vector) return boolean is
variable t : boolean := true;
begin
t := true; -- for synopsys
for i in inp'range loop
if inp(i) = '0' then
t := false;
end if;
end loop;
return t;
end allOnes;
-------------------------------------------------------------------------------
-- returns the maximum of two naturals
-------------------------------------------------------------------------------
function maxNat (arg1, arg2 : natural)
return natural is
begin -- maxNat
if arg1 >= arg2 then
return arg1;
else
return arg2;
end if;
end maxNat;
-------------------------------------------------------------------------------
-- zero extend a std_logic_vector
-------------------------------------------------------------------------------
function zExtend (
arg1 : std_logic_vector;
size : natural)
return std_logic_vector is
variable result : std_logic_vector(size - 1 downto 0);
begin -- extend
result := (others => '0');
result(arg1'length - 1 downto 0) := arg1;
return result;
end zExtend;
-------------------------------------------------------------------------------
-- Switch the word order between Correct-Word-Order and Net-Word-Order.
-- If arg is (Hex)1234,
-- then netOrder(arg) is (Hex)2143.
-------------------------------------------------------------------------------
-- function netOrder (arg : Word)
-- return Word is
-- begin -- netOrder
-- return arg(11 downto 8) & arg(15 downto 12) &
-- arg(3 downto 0) & arg(7 downto 4);
-- end netOrder;
-- function netOrder (arg : std_logic_vector (15 downto 0))
-- return std_logic_vector is
-- variable res : std_logic_vector (15 downto 0);
-- begin -- netOrder
-- res(15 downto 12) := arg(11 downto 8);
-- res(11 downto 8) := arg(15 downto 12);
-- res(7 downto 4) := arg(3 downto 0);
-- res(3 downto 0) := arg(7 downto 4);
-- return res;
-- end netOrder;
function netOrder (arg : Word)
return Word is
variable res : Word;--(15 downto 0);
begin -- netOrder
res(15 downto 12) := arg(11 downto 8);
res(11 downto 8) := arg(15 downto 12);
res(7 downto 4) := arg(3 downto 0);
res(3 downto 0) := arg(7 downto 4);
return res;
end netOrder;
-- coverage on
end mac_pkg;
-------------------------------------------------------------------------------
-- lfsr16 - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : lfsr16.vhd
-- Version : v2.0
-- Description : This is a 15 bit random number generator.
-- In simulation we need to reset first, then give the enable signal.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- This is a 15 bit random number generator.
-- In simulation we need to reset first, then give the enable signal.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0_9 library is used for axi_ethernetlite_v3_0_9
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0_9;
use axi_ethernetlite_v3_0_9.mac_pkg.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Clken -- Clock enable
-- Enbl -- LFSR enable
-- Shftout -- Shift data output
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity lfsr16 is
port
(
Clk : in std_logic;
Rst : in std_logic;
Clken : in std_logic; -- tx Clk based. Assumed to be 2.5 or 25 MHz
Enbl : in std_logic;
Shftout : out std_logic
);
end lfsr16;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- No Generics were used for this Entity.
--
-- Definition of Ports:
--
-------------------------------------------------------------------------------
architecture imp of lfsr16 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Constants used in this design are found in mac_pkg.vhd
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Bit1 : std_logic;
signal Bit15 : std_logic;
signal Bit14 : std_logic;
signal XNORGateOutput : std_logic;
signal zero : std_logic;
signal one : std_logic;
signal combo_enbl : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- The following components are the building blocks of the 16 bit lfsr
component SRL16E
-- synthesis translate_off
generic (INIT : bit_vector := X"0000");
-- synthesis translate_on
port (
Q : out std_logic;
A0 : in std_logic; -- Set the address to 12.
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
D : in std_logic;
Clk : in std_logic;
CE : in std_logic);
end component;
begin
zero <= '0';
one <= '1';
SHREG0 : SRL16E
-- synthesis translate_off
generic map (INIT => X"5a5a")
-- synthesis translate_on
port map(
Q => Bit14,
A0 => zero,
A1 => zero,
A2 => one,
A3 => one,
D => Bit1,
CE => combo_enbl,
Clk => Clk);
combo_enbl <= Enbl and Clken;
-------------------------------------------------------------------------------
-- determine bit 15 value
-------------------------------------------------------------------------------
REG0_PROCESS:process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
Bit15 <= '0';
elsif combo_enbl = '1' then
Bit15 <= Bit14;
end if;
end if;
end process REG0_PROCESS;
-------------------------------------------------------------------------------
-- determine bit 1 value
-------------------------------------------------------------------------------
REG1_PROCESS:process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
Bit1 <= '0';
elsif combo_enbl = '1' then
Bit1 <= XNORGateOutput;
end if;
end if;
end process REG1_PROCESS;
XNORGateOutput <= Bit14 XNOR Bit15;
Shftout <= Bit1;
end imp;
-------------------------------------------------------------------------------
-- defer_state - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : defer_state.vhd
-- Version : v2.0
-- Description : This file contains the transmit deferral state machine.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0_9 library is used for axi_ethernetlite_v3_0_9
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0_9;
use axi_ethernetlite_v3_0_9.mac_pkg.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- TxEn -- Transmit enable
-- Txrst -- Transmit reset
-- Ifgp2Done -- Interframe gap2 done
-- Ifgp1Done -- Interframe gap1 done
-- BackingOff -- Backing off
-- Crs -- Carrier sense
-- Full_half_n -- Full/Half duplex indicator
-- Deferring -- Deffering for the tx data
-- CntrEnbl -- Counter enable
-- CntrLd -- Counter load
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity defer_state is
port (
Clk : in std_logic;
Rst : in std_logic;
TxEn : in std_logic;
Txrst : in std_logic;
Ifgp2Done : in std_logic;
Ifgp1Done : in std_logic;
BackingOff : in std_logic;
Crs : in std_logic;
Full_half_n : in std_logic;
Deferring : out std_logic;
CntrEnbl : out std_logic;
CntrLd : out std_logic
);
end defer_state;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- No Generics were used for this Entity.
--
-- Definition of Ports:
--
-------------------------------------------------------------------------------
architecture implementation of defer_state is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Constants used in this design are found in mac_pkg.vhd
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
type StateName is (loadCntr,startIfgp1Cnt,startIfgp2Cnt,cntDone);
signal thisState : StateName;
signal nextState : StateName;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- The following components are the building blocks of the tx state machine
begin
----------------------------------------------------------------------------
-- FSMR Process
----------------------------------------------------------------------------
-- An FSM that deals with transmitting data
----------------------------------------------------------------------------
FSMR : process (Clk)
begin --
if (Clk'event and Clk = '1') then -- rising clock edge
if (Rst = '1' or Txrst = '1') then
thisState <= loadCntr;
else
thisState <= nextState;
end if;
end if;
end process FSMR;
----------------------------------------------------------------------------
-- FSMC Process
----------------------------------------------------------------------------
FSMC : process (thisState,TxEn,Ifgp2Done,Ifgp1Done,BackingOff,Crs,
Full_half_n)
begin --
case thisState is
when loadCntr =>
if (((TxEn = '0') and (Full_half_n = '1')) or
((Crs = '0') and (Full_half_n = '0') and
(BackingOff = '0'))) and
Ifgp1Done = '0' and Ifgp2Done = '0' then
nextState <= startIfgp1Cnt;
else
nextState <= loadCntr; -- wait for end of transmission
end if;
when startIfgp1Cnt =>
if (((Crs = '1') and (Full_half_n = '0')) or
((BackingOff = '1') and (Full_half_n = '0'))) then
nextState <= loadCntr;
elsif (Ifgp1Done = '1') then -- gap done
nextState <= startIfgp2Cnt;
else
nextState <= startIfgp1Cnt; -- still counting
end if;
when startIfgp2Cnt =>
-- Added check for CRS to reset counter in when CRS goes low.
if (((Crs = '1') and (Full_half_n = '0')) or
((BackingOff = '1') and (Full_half_n = '0'))) then
nextState <= loadCntr;
elsif (Ifgp2Done = '1') then -- gap done
nextState <= cntDone;
else
nextState <= startIfgp2Cnt; -- still counting
end if;
when cntDone =>
if (TxEn = '1' or Crs = '1') then -- transmission started
nextState <= loadCntr;
else
nextState <= cntDone;
end if;
-- coverage off
when others => null;
nextState <= loadCntr;
-- coverage on
end case;
end process FSMC;
----------------------------------------------------------------------------
-- FSMD Process
----------------------------------------------------------------------------
FSMD : process(thisState)
begin --
if ((thisState = loadCntr) or (thisState = startIfgp1Cnt) or
(thisState = startIfgp2Cnt)) then
Deferring <= '1';
else
Deferring <= '0';
end if;
if ((thisState = startIfgp1Cnt) or (thisState = startIfgp2Cnt)) then
CntrEnbl <= '1';
else
CntrEnbl <= '0';
end if;
if (thisState = loadCntr) then
CntrLd <= '1';
else
CntrLd <= '0';
end if;
end process FSMD;
end implementation;
-------------------------------------------------------------------------------
-- crcnibshiftreg - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename : crcnibshiftreg.vhd
-- Version : v2.0
-- Description : CRC Nible Shift Register
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Clke -- Clock enable
-- Din -- Data in
-- Load -- Data load
-- Shift -- Data shift enable
-- Dout -- data out
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity crcnibshiftreg is
port (
Clk : in std_logic;
Rst : in std_logic;
Clken : in std_logic;
Din : in std_logic_vector(31 downto 0);
Load : in std_logic;
Shift : in std_logic;
Dout : out std_logic_vector(31 downto 0)
);
end crcnibshiftreg;
architecture implementation of crcnibshiftreg is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal nibData : std_logic_vector (31 downto 0);
begin
----------------------------------------------------------------------------
-- PROCESS : SHIFTER
----------------------------------------------------------------------------
-- The process shifts the nibble data when shift is enabled.
----------------------------------------------------------------------------
SHIFTER : process (Clk)
begin --
if (Clk'event and Clk = '1') then
if Rst = '1' then
nibData <= (others => '0');
elsif (Clken = '1') then
if (Load = '1') then
nibData <= Din;
elsif (Shift = '1') then
nibData(3 downto 0) <= nibData(7 downto 4);
nibData(7 downto 4) <= nibData(11 downto 8);
nibData(11 downto 8) <= nibData(15 downto 12);
nibData(15 downto 12) <= nibData(19 downto 16);
nibData(19 downto 16) <= nibData(23 downto 20);
nibData(23 downto 20) <= nibData(27 downto 24);
nibData(27 downto 24) <= nibData(31 downto 28);
nibData(31 downto 28) <= (others => '0');
end if;
end if;
end if;
end process SHIFTER;
Dout <= nibData;
end implementation;
-------------------------------------------------------------------------------
-- cntr5bit - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : cntr5bit.vhd
-- Version : v2.0
--
-- Description : This file contains the a 5 bit resetable, loadable
-- down counter by 1.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0_9 library is used for axi_ethernetlite_v3_0_9
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0_9;
use axi_ethernetlite_v3_0_9.mac_pkg.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Cntout -- Counter output
-- En -- Counter enable
-- Ld -- Counter load enable
-- Load_in -- Counter load data
-- Zero -- Terminal count
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity cntr5bit is
port (
Clk : in std_logic; -- input clock
Rst : in std_logic; -- reset counter
Cntout : out std_logic_vector (0 to 4);
En : in std_logic; -- counter down enable by 1
Ld : in std_logic; -- load enable
Load_in : in std_logic_vector (0 to 4); -- load input value
Zero : out std_logic -- terminal count
);
end cntr5bit;
architecture implementation of cntr5bit is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Constants used in this design are found in mac_pkg.vhd
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal count : std_logic_vector(0 to 4);
signal zero_i : std_logic;
begin
Cntout <= count;
-------------------------------------------------------------------------------
-- INT_count_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal control register signals to the out port
-------------------------------------------------------------------------------
INT_COUNT_PROCESS1: process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
count <= (others => '1');
elsif (Ld = '1') then
count <= Load_in;
elsif (En = '1' and zero_i = '0') then
count <= count - 1;
else
null;
end if;
end if;
end process INT_COUNT_PROCESS1;
INT_COUNT_PROCESS2: process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
zero_i <= '1';
else
if (count = "00001") then
zero_i <= '1';
else
zero_i <= '0';
end if;
end if;
end if;
end process INT_COUNT_PROCESS2;
Zero <= zero_i;
end implementation;
-------------------------------------------------------------------------------
-- tx_statemachine - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : tx_statemachine.vhd
-- Version : v2.0
-- Description : This file contains the transmit control state machine.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0_9 library is used for axi_ethernetlite_v3_0_9
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0_9;
use axi_ethernetlite_v3_0_9.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- TxClkEn -- Transmit clocl enable
-- Jam_rst -- Jam reset
-- TxRst -- Transmit reset
-- Deferring -- Deffering
-- ColRetryCnt -- Collision retry coun
-- ColWindowNibCnt -- Collision window nibble count
-- JamTxNibCnt -- TX Jam nibble count
-- TxNibbleCnt -- TX Nibble count
-- BusFifoWrNibbleCnt -- Bus FIFO write nibble count
-- CrcCnt -- CRC count
-- BusFifoFull -- Bus FIFO full
-- BusFifoEmpty -- Bus FIFO empty
-- PhyCollision -- Phy collision
-- Tx_pong_ping_l -- TX Ping/Pong buffer enable
-- InitBackoff -- Initialize back off
-- TxRetryRst -- TX retry reset
-- TxExcessDefrlRst -- TX excess defer reset
-- TxLateColnRst -- TX late collision reset
-- TxColRetryCntRst_n -- TX collision retry counter reset
-- TxColRetryCntEnbl -- TX collision retry counter enable
-- TxNibbleCntRst -- TX nibble counter reset
-- TxEnNibbleCnt -- TX nibble count
-- TxNibbleCntLd -- TX nibble counter load
-- BusFifoWrCntRst -- Bus FIFO write counter reset
-- BusFifoWrCntEn -- Bus FIFO write counter enable
-- EnblPre -- Enable Preamble
-- EnblSFD -- Enable SFD
-- EnblData -- Enable Data
-- EnblJam -- Enable Jam
-- EnblCRC -- Enable CRC
-- BusFifoWr -- Bus FIFO write enable
-- Phytx_en -- PHY transmit enable
-- TxCrcEn -- TX CRC enable
-- TxCrcShftOutEn -- TX CRC shift out enable
-- Tx_addr_en -- TX buffer address enable
-- Tx_start -- Trasnmit start
-- Tx_done -- Transmit done
-- Tx_idle -- Transmit idle
-- Tx_DPM_ce -- TX buffer chip enable
-- Tx_DPM_wr_data -- TX buffer write data
-- Tx_DPM_wr_rd_n -- TX buffer write/read enable
-- Enblclear -- Enable clear
-- Transmit_start -- Transmit start
-- Mac_program_start -- MAC Program start
-- Mac_addr_ram_we -- MAC Address RAM write enable
-- Mac_addr_ram_addr_wr -- MAC Address RAM write address
-- Pre_sfd_done -- Pre SFD done
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity tx_statemachine is
generic
(
C_DUPLEX : integer := 1
-- 1 = full duplex, 0 = half duplex
);
port
(
Clk : in std_logic;
Rst : in std_logic;
TxClkEn : in std_logic;
Jam_rst : out std_logic;
TxRst : in std_logic;
Deferring : in std_logic;
ColRetryCnt : in std_logic_vector (0 to 4);
ColWindowNibCnt : in std_logic_vector (0 to 7);
JamTxNibCnt : in std_logic_vector (0 to 3);
TxNibbleCnt : in std_logic_vector (0 to 11);
BusFifoWrNibbleCnt : in std_logic_vector (0 to 11);
CrcCnt : in std_logic_vector (0 to 3);
BusFifoFull : in std_logic;
BusFifoEmpty : in std_logic;
PhyCollision : in std_logic;
Tx_pong_ping_l : in std_logic;
InitBackoff : out std_logic;
TxRetryRst : out std_logic;
TxExcessDefrlRst : out std_logic;
TxLateColnRst : out std_logic;
TxColRetryCntRst_n : out std_logic;
TxColRetryCntEnbl : out std_logic;
TxNibbleCntRst : out std_logic;
TxEnNibbleCnt : out std_logic;
TxNibbleCntLd : out std_logic;
BusFifoWrCntRst : out std_logic;
BusFifoWrCntEn : out std_logic;
EnblPre : out std_logic;
EnblSFD : out std_logic;
EnblData : out std_logic;
EnblJam : out std_logic;
EnblCRC : out std_logic;
BusFifoWr : out std_logic;
Phytx_en : out std_logic;
TxCrcEn : out std_logic;
TxCrcShftOutEn : out std_logic;
Tx_addr_en : out std_logic;
Tx_start : out std_logic;
Tx_done : out std_logic;
Tx_idle : out std_logic;
Tx_DPM_ce : out std_logic;
Tx_DPM_wr_data : out std_logic_vector (0 to 3);
Tx_DPM_wr_rd_n : out std_logic;
Enblclear : out std_logic;
Transmit_start : in std_logic;
Mac_program_start : in std_logic;
Mac_addr_ram_we : out std_logic;
Mac_addr_ram_addr_wr : out std_logic_vector(0 to 3);
Pre_sfd_done : out std_logic
);
end tx_statemachine;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- No Generics were used for this Entity.
--
-- Definition of Ports:
--
-------------------------------------------------------------------------------
architecture implementation of tx_statemachine is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Constants used in this design are found in mac_pkg.vhd
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal idle : std_logic; -- state 0
signal lngthDelay1 : std_logic; -- state 5
signal lngthDelay2 : std_logic; -- state 6
signal ldLngthCntr : std_logic; -- state 7
signal preamble : std_logic; -- state 8
signal checkBusFifoFullSFD : std_logic; -- state 9
signal SFD : std_logic; -- state 10
signal checkBusFifoFull : std_logic; -- state 11
signal loadBusFifo : std_logic; -- state 12
signal checkCrc : std_logic; -- state 13
signal checkBusFifoFullCrc : std_logic; -- state 14
signal loadBusFifoCrc : std_logic; -- state 15
signal waitFifoEmpty : std_logic; -- state 16
signal txDone : std_logic; -- state 17
signal checkBusFifoFullJam : std_logic; -- state 18
signal loadBusFifoJam : std_logic; -- state 19
signal half_dup_error : std_logic; -- state 20
signal collisionRetry : std_logic; -- state 21
signal retryWaitFifoEmpty : std_logic; -- state 22
signal retryReset : std_logic; -- state 23
signal txDone2 : std_logic; -- state 24
signal txDonePause : std_logic; -- state 25
signal chgMacAdr1 : std_logic; -- state 26
signal chgMacAdr2 : std_logic; -- state 27
signal chgMacAdr3 : std_logic; -- state 28
signal chgMacAdr4 : std_logic; -- state 29
signal chgMacAdr5 : std_logic; -- state 30
signal chgMacAdr6 : std_logic; -- state 31
signal chgMacAdr7 : std_logic; -- state 32
signal chgMacAdr8 : std_logic; -- state 33
signal chgMacAdr9 : std_logic; -- state 34
signal chgMacAdr10 : std_logic; -- state 35
signal chgMacAdr11 : std_logic; -- state 36
signal chgMacAdr12 : std_logic; -- state 37
signal chgMacAdr13 : std_logic; -- state 38
signal chgMacAdr14 : std_logic; -- state 39
signal idle_D : std_logic; -- state 0
signal txLngthRdNib1_D : std_logic; -- state 1
signal lngthDelay1_D : std_logic; -- state 5
signal lngthDelay2_D : std_logic; -- state 6
signal ldLngthCntr_D : std_logic; -- state 7
signal preamble_D : std_logic; -- state 8
signal checkBusFifoFullSFD_D : std_logic; -- state 9
signal SFD_D : std_logic; -- state 10
signal checkBusFifoFull_D : std_logic; -- state 11
signal loadBusFifo_D : std_logic; -- state 12
signal checkCrc_D : std_logic; -- state 13
signal checkBusFifoFullCrc_D : std_logic; -- state 14
signal loadBusFifoCrc_D : std_logic; -- state 15
signal waitFifoEmpty_D : std_logic; -- state 16
signal txDone_D : std_logic; -- state 17
signal checkBusFifoFullJam_D : std_logic; -- state 18
signal loadBusFifoJam_D : std_logic; -- state 19
signal half_dup_error_D : std_logic; -- state 20
signal collisionRetry_D : std_logic; -- state 21
signal retryWaitFifoEmpty_D : std_logic; -- state 22
signal retryReset_D : std_logic; -- state 23
signal txDone2_D : std_logic; -- state 24
signal txDonePause_D : std_logic; -- state 25
signal chgMacAdr1_D : std_logic; -- state 26
signal chgMacAdr2_D : std_logic; -- state 27
signal chgMacAdr3_D : std_logic; -- state 28
signal chgMacAdr4_D : std_logic; -- state 29
signal chgMacAdr5_D : std_logic; -- state 30
signal chgMacAdr6_D : std_logic; -- state 31
signal chgMacAdr7_D : std_logic; -- state 32
signal chgMacAdr8_D : std_logic; -- state 33
signal chgMacAdr9_D : std_logic; -- state 34
signal chgMacAdr10_D : std_logic; -- state 35
signal chgMacAdr11_D : std_logic; -- state 36
signal chgMacAdr12_D : std_logic; -- state 37
signal chgMacAdr13_D : std_logic; -- state 38
signal chgMacAdr14_D : std_logic; -- state 39
signal txNibbleCntRst_i : std_logic;
signal txEnNibbleCnt_i : std_logic;
signal txNibbleCntLd_i : std_logic;
signal busFifoWr_i : std_logic;
signal phytx_en_i : std_logic;
signal phytx_en_i_n : std_logic;
signal txCrcEn_i : std_logic;
signal retrying_i : std_logic;
signal phytx_en_reg : std_logic;
signal busFifoWrCntRst_reg : std_logic;
signal retrying_reg : std_logic;
signal txCrcEn_reg : std_logic;
signal busFifoWrCntRst_i : std_logic;
signal state_machine_rst : std_logic;
signal full_half_n : std_logic;
signal goto_idle : std_logic; -- state 0
signal stay_idle : std_logic; -- state 0
signal goto_txLngthRdNib1_1 : std_logic; -- state 1
signal goto_txLngthRdNib1_2 : std_logic; -- state 1
signal goto_lngthDelay1 : std_logic; -- state 5
signal goto_lngthDelay2 : std_logic; -- state 6
signal goto_ldLngthCntr : std_logic; -- state 7
signal stay_ldLngthCntr : std_logic; -- state 7
signal goto_preamble : std_logic; -- state 8
signal stay_preamble : std_logic; -- state 8
signal goto_checkBusFifoFullSFD : std_logic; -- state 9
signal stay_checkBusFifoFullSFD : std_logic; -- state 9
signal goto_SFD : std_logic; -- state 10
signal stay_SFD : std_logic; -- state 10
signal goto_checkBusFifoFull_1 : std_logic; -- state 11
signal goto_checkBusFifoFull_2 : std_logic; -- state 11
signal stay_checkBusFifoFull : std_logic; -- state 11
signal goto_loadBusFifo : std_logic; -- state 12
signal goto_checkCrc : std_logic; -- state 13
signal goto_checkBusFifoFullCrc_1 : std_logic; -- state 14
signal goto_checkBusFifoFullCrc_2 : std_logic; -- state 14
signal stay_checkBusFifoFullCrc : std_logic; -- state 14
signal goto_loadBusFifoCrc_1 : std_logic; -- state 15
signal goto_waitFifoEmpty_2 : std_logic; -- state 16
signal stay_waitFifoEmpty : std_logic; -- state 16
signal goto_txDone_1 : std_logic; -- state 17
signal goto_txDone_2 : std_logic; -- state 17
signal goto_checkBusFifoFullJam_1 : std_logic; -- state 18
signal goto_checkBusFifoFullJam_2 : std_logic; -- state 18
signal stay_checkBusFifoFullJam : std_logic; -- state 18
signal goto_loadBusFifoJam : std_logic; -- state 19
signal goto_half_dup_error_1 : std_logic; -- state 20
signal goto_half_dup_error_2 : std_logic; -- state 20
signal goto_collisionRetry : std_logic; -- state 21
signal goto_retryWaitFifoEmpty : std_logic; -- state 22
signal stay_retryWaitFifoEmpty : std_logic; -- state 22
signal goto_retryReset : std_logic; -- state 23
signal goto_txDone2 : std_logic; -- state 24
signal goto_txDonePause : std_logic; -- state 25
signal goto_chgMacAdr1 : std_logic; -- state 26
signal goto_chgMacAdr2 : std_logic; -- state 27
signal goto_chgMacAdr3 : std_logic; -- state 28
signal goto_chgMacAdr4 : std_logic; -- state 29
signal goto_chgMacAdr5 : std_logic; -- state 30
signal goto_chgMacAdr6 : std_logic; -- state 31
signal goto_chgMacAdr7 : std_logic; -- state 32
signal goto_chgMacAdr8 : std_logic; -- state 33
signal goto_chgMacAdr9 : std_logic; -- state 34
signal goto_chgMacAdr10 : std_logic; -- state 35
signal goto_chgMacAdr11 : std_logic; -- state 36
signal goto_chgMacAdr12 : std_logic; -- state 37
signal goto_chgMacAdr13 : std_logic; -- state 38
signal goto_chgMacAdr14 : std_logic; -- state 39
signal txNibbleCnt_is_1 : std_logic;
signal busFifoWrNibbleCnt_is_14 : std_logic;
signal busFifoWrNibbleCnt_not_14 : std_logic;
signal busFifoWrNibbleCnt_is_15 : std_logic;
signal busFifoWrNibbleCnt_not_15 : std_logic;
signal crcCnt_not_0 : std_logic;
signal crcCnt_is_0 : std_logic;
signal jamTxNibCnt_not_0 : std_logic;
signal jamTxNibCnt_is_0 : std_logic;
signal colWindowNibCnt_not_0 : std_logic;
signal colWindowNibCnt_is_0 : std_logic;
signal colRetryCnt_is_15 : std_logic;
signal pre_SFD_zero : std_logic;
signal waitdone_pre_sfd : std_logic;
signal transmit_start_reg : std_logic;
signal mac_program_start_reg : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- The following components are the building blocks of the tx state machine
component FDR
port
(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component FDS
port
(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic
);
end component;
component FDRE
port
(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
begin
Tx_DPM_wr_data <= (others => '0');
-- Trnasmit Done indicator
-- added txDone for ping pong control
Tx_done <= txDone and not retrying_reg;
-- Full/Half duplex indicator
full_half_n <= '1'when C_DUPLEX = 1 else '0';
-- Wait for Pre SFD
--waitdone_pre_sfd <= PhyCollision and not(full_half_n) and not(pre_sfd_zero);
Pre_sfd_done <= pre_SFD_zero;
-- PHY tx enable
phytx_en_i_n <= not(phytx_en_i);
----------------------------------------------------------------------------
-- Signal Assignment
----------------------------------------------------------------------------
TxNibbleCntRst <= txNibbleCntRst_i;
TxEnNibbleCnt <= txEnNibbleCnt_i;
TxNibbleCntLd <= txNibbleCntLd_i;
BusFifoWr <= busFifoWr_i;
Phytx_en <= phytx_en_i;
TxCrcEn <= txCrcEn_i;
BusFifoWrCntRst <= busFifoWrCntRst_i;
----------------------------------------------------------------------------
-- Pre SFD Counter
----------------------------------------------------------------------------
PRE_SFD_count: entity axi_ethernetlite_v3_0_9.cntr5bit
port map
(
cntout => open,
Clk => Clk,
Rst => Rst,
en => TxClkEn,
ld => phytx_en_i_n,
load_in => "10011",
zero => pre_SFD_zero
);
-- State machine reset
state_machine_rst <= Rst;
----------------------------------------------------------------------------
-- Counter enable generation
----------------------------------------------------------------------------
-- Transmit Nibble Counte=1
txNibbleCnt_is_1 <= not(TxNibbleCnt(0)) and not(TxNibbleCnt(1)) and
not(TxNibbleCnt(2)) and not(TxNibbleCnt(3)) and
not(TxNibbleCnt(4)) and not(TxNibbleCnt(5)) and
not(TxNibbleCnt(6)) and not(TxNibbleCnt(7)) and
not(TxNibbleCnt(8)) and not(TxNibbleCnt(9)) and
not(TxNibbleCnt(10))and TxNibbleCnt(11);
-- Bus FIFO write Nibble Counte=14
busFifoWrNibbleCnt_is_14 <= BusFifoWrNibbleCnt(8) and
BusFifoWrNibbleCnt(9) and
BusFifoWrNibbleCnt(10) and
not(BusFifoWrNibbleCnt(11));
-- Bus FIFO write Nibble Counte/=14
busFifoWrNibbleCnt_not_14 <= not(busFifoWrNibbleCnt_is_14);
-- Bus FIFO write Nibble Counte=15
busFifoWrNibbleCnt_is_15 <= (BusFifoWrNibbleCnt(8) and
BusFifoWrNibbleCnt(9) and
BusFifoWrNibbleCnt(10) and
BusFifoWrNibbleCnt(11));
-- Bus FIFO write Nibble Counte/=15
busFifoWrNibbleCnt_not_15 <= not(busFifoWrNibbleCnt_is_15);
-- CRC Count/=0
crcCnt_not_0 <= CrcCnt(0) or CrcCnt(1) or CrcCnt(2) or CrcCnt(3);
-- CRC Count=0
crcCnt_is_0 <= not crcCnt_not_0;
-- Jam Transmit Nibble count/=0
jamTxNibCnt_not_0 <= JamTxNibCnt(0) or JamTxNibCnt(1) or JamTxNibCnt(2) or
JamTxNibCnt(3);
-- Jam Transmit Nibble count=0
jamTxNibCnt_is_0 <= not(jamTxNibCnt_not_0);
-- Collision windo Nibble count/=0
colWindowNibCnt_not_0 <= ColWindowNibCnt(0) or ColWindowNibCnt(1) or
ColWindowNibCnt(2) or ColWindowNibCnt(3) or
ColWindowNibCnt(4) or ColWindowNibCnt(5) or
ColWindowNibCnt(6) or ColWindowNibCnt(7);
-- Collision windo Nibble count=0
colWindowNibCnt_is_0 <= not(colWindowNibCnt_not_0);
-- Collision retry count=15
colRetryCnt_is_15 <= not(ColRetryCnt(0)) and ColRetryCnt(1) and
ColRetryCnt(2) and ColRetryCnt(3) and
ColRetryCnt(4);
----------------------------------------------------------------------------
-- idle state
----------------------------------------------------------------------------
goto_idle <= txDonePause;
stay_idle <= idle and not(Transmit_start) and not Mac_program_start;
idle_D <= goto_idle or stay_idle;
----------------------------------------------------------------------------
-- idle state
----------------------------------------------------------------------------
STATE0A: FDS
port map
(
Q => idle, --[out]
C => Clk, --[in]
D => idle_D, --[in]
S => state_machine_rst --[in]
);
Tx_idle <= idle;
----------------------------------------------------------------------------
-- txLngthRdNib1 state
----------------------------------------------------------------------------
--goto_txLngthRdNib1_1 <= idle and Transmit_start and not transmit_start_reg;
goto_txLngthRdNib1_1 <= idle and
((transmit_start and not transmit_start_reg)
or
(transmit_start and retrying_reg));
goto_txLngthRdNib1_2 <= retryReset;
txLngthRdNib1_D <= goto_txLngthRdNib1_1 or goto_txLngthRdNib1_2;
goto_lngthDelay1 <= txLngthRdNib1_D;
----------------------------------------------------------------------------
-- lngthDelay1 state
----------------------------------------------------------------------------
lngthDelay1_D <= goto_lngthDelay1;
STATE5A: FDR
port map
(
Q => lngthDelay1, --[out]
C => Clk, --[in]
D => lngthDelay1_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- lngthDelay2 state
----------------------------------------------------------------------------
goto_lngthDelay2 <= lngthDelay1;
lngthDelay2_D <= goto_lngthDelay2;
STATE6A: FDR
port map
(
Q => lngthDelay2, --[out]
C => Clk, --[in]
D => lngthDelay2_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- ldLngthCntr state
----------------------------------------------------------------------------
goto_ldLngthCntr <= lngthDelay1;
stay_ldLngthCntr <= ldLngthCntr and Deferring;
ldLngthCntr_D <= goto_ldLngthCntr or stay_ldLngthCntr;
STATE7A: FDR
port map
(
Q => ldLngthCntr, --[out]
C => Clk, --[in]
D => ldLngthCntr_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- preamble state
----------------------------------------------------------------------------
goto_preamble <= (ldLngthCntr and (not(Deferring)));
stay_preamble <= preamble and busFifoWrNibbleCnt_not_14;
preamble_D <= goto_preamble or stay_preamble;
STATE8A: FDR
port map
(
Q => preamble, --[out]
C => Clk, --[in]
D => preamble_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- checkBusFifoFullSFD state
----------------------------------------------------------------------------
goto_checkBusFifoFullSFD <= preamble and busFifoWrNibbleCnt_is_14;
stay_checkBusFifoFullSFD <= checkBusFifoFullSFD and BusFifoFull;
checkBusFifoFullSFD_D <= goto_checkBusFifoFullSFD or
stay_checkBusFifoFullSFD;
STATE9A: FDR
port map
(
Q => checkBusFifoFullSFD, --[out]
C => Clk, --[in]
D => checkBusFifoFullSFD_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- SFD state
----------------------------------------------------------------------------
goto_SFD <= checkBusFifoFullSFD and not (BusFifoFull);
stay_SFD <= SFD and busFifoWrNibbleCnt_not_15;
SFD_D <= goto_SFD or stay_SFD;
STATE10A: FDR
port map
(
Q => SFD, --[out]
C => Clk, --[in]
D => SFD_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- checkBusFifoFull state
----------------------------------------------------------------------------
goto_checkBusFifoFull_1 <= loadBusFifo and not(goto_checkCrc) and
not(goto_checkBusFifoFullJam_1);
goto_checkBusFifoFull_2 <= SFD and busFifoWrNibbleCnt_is_15;
stay_checkBusFifoFull <= checkBusFifoFull and BusFifoFull and
not (goto_checkBusFifoFullJam_1);
checkBusFifoFull_D <= goto_checkBusFifoFull_1 or
goto_checkBusFifoFull_2 or
stay_checkBusFifoFull;
STATE11A: FDR
port map
(
Q => checkBusFifoFull, --[out]
C => Clk, --[in]
D => checkBusFifoFull_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- loadBusFifo state
----------------------------------------------------------------------------
goto_loadBusFifo <= checkBusFifoFull and not(BusFifoFull) and
not(goto_checkCrc) and not(goto_checkBusFifoFullJam_1);
loadBusFifo_D <= goto_loadBusFifo;
STATE12A: FDR
port map
(
Q => loadBusFifo, --[out]
C => Clk, --[in]
D => loadBusFifo_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- checkCrc state
----------------------------------------------------------------------------
goto_checkCrc <= loadBusFifo and txNibbleCnt_is_1 and
not(goto_checkBusFifoFullJam_1);
checkCrc_D <= goto_checkCrc;
STATE13A: FDR
port map
(
Q => checkCrc, --[out]
C => Clk, --[in]
D => checkCrc_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- checkBusFifoFullCrc state
----------------------------------------------------------------------------
goto_checkBusFifoFullCrc_1 <= checkCrc and not(goto_checkBusFifoFullJam_1);
goto_checkBusFifoFullCrc_2 <= loadBusFifoCrc and
not(goto_checkBusFifoFullJam_1);
stay_checkBusFifoFullCrc <= checkBusFifoFullCrc and BusFifoFull and
not(goto_checkBusFifoFullJam_1);
checkBusFifoFullCrc_D <= goto_checkBusFifoFullCrc_1 or
goto_checkBusFifoFullCrc_2 or
stay_checkBusFifoFullCrc;
STATE14A: FDR
port map
(
Q => checkBusFifoFullCrc, --[out]
C => Clk, --[in]
D => checkBusFifoFullCrc_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- loadBusFifoCrc state
----------------------------------------------------------------------------
goto_loadBusFifoCrc_1 <= checkBusFifoFullCrc and not(BusFifoFull) and
crcCnt_not_0 and not(goto_checkBusFifoFullJam_1);
loadBusFifoCrc_D <= goto_loadBusFifoCrc_1;
STATE15A: FDR
port map
(
Q => loadBusFifoCrc, --[out]
C => Clk, --[in]
D => loadBusFifoCrc_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- waitFifoEmpty state
----------------------------------------------------------------------------
goto_waitFifoEmpty_2 <= checkBusFifoFullCrc and crcCnt_is_0 and
not(BusFifoFull) and not(goto_checkBusFifoFullJam_1);
stay_waitFifoEmpty <= waitFifoEmpty and not(BusFifoEmpty) and
not(goto_checkBusFifoFullJam_1);
waitFifoEmpty_D <= goto_waitFifoEmpty_2 or stay_waitFifoEmpty;
STATE16A: FDR
port map
(
Q => waitFifoEmpty, --[out]
C => Clk, --[in]
D => waitFifoEmpty_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- txDone state
----------------------------------------------------------------------------
goto_txDone_1 <= waitFifoEmpty and BusFifoEmpty and
not(goto_checkBusFifoFullJam_1);
goto_txDone_2 <= half_dup_error or chgMacAdr14;
txDone_D <= goto_txDone_1 or goto_txDone_2;
STATE17A: FDR
port map
(
Q => txDone, --[out]
C => Clk, --[in]
D => txDone_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- checkBusFifoFullJam state
----------------------------------------------------------------------------
goto_checkBusFifoFullJam_1 <= (checkBusFifoFull or loadBusFifo or checkCrc
or checkBusFifoFullCrc or waitFifoEmpty) and
PhyCollision and not(full_half_n);
goto_checkBusFifoFullJam_2 <= loadBusFifoJam;
stay_checkBusFifoFullJam <= checkBusFifoFullJam and (BusFifoFull or
not(pre_SFD_zero));
checkBusFifoFullJam_D <= goto_checkBusFifoFullJam_1 or
goto_checkBusFifoFullJam_2 or
stay_checkBusFifoFullJam;
STATE18A: FDR
port map
(
Q => checkBusFifoFullJam, --[out]
C => Clk, --[in]
D => checkBusFifoFullJam_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- loadBusFifoJam state
----------------------------------------------------------------------------
goto_loadBusFifoJam <= checkBusFifoFullJam and
not(stay_checkBusFifoFullJam) and
jamTxNibCnt_not_0;
loadBusFifoJam_D <= goto_loadBusFifoJam;
STATE19A: FDR
port map
(
Q => loadBusFifoJam, --[out]
C => Clk, --[in]
D => loadBusFifoJam_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- half_dup_error state
----------------------------------------------------------------------------
goto_half_dup_error_1 <= checkBusFifoFullJam and not(BusFifoFull or
not(pre_SFD_zero)) and jamTxNibCnt_is_0 and
colWindowNibCnt_not_0 and colRetryCnt_is_15;
goto_half_dup_error_2 <= checkBusFifoFullJam and not(BusFifoFull or
not(pre_SFD_zero)) and jamTxNibCnt_is_0 and
colWindowNibCnt_is_0;
half_dup_error_D <= goto_half_dup_error_1 or goto_half_dup_error_2;
STATE20A: FDR
port map
(
Q => half_dup_error, --[out]
C => Clk, --[in]
D => half_dup_error_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- collisionRetry state
----------------------------------------------------------------------------
goto_collisionRetry <= checkBusFifoFullJam and not(stay_checkBusFifoFullJam)
and not(goto_half_dup_error_1) and
not(goto_half_dup_error_2) and
not(goto_loadBusFifoJam);
collisionRetry_D <= goto_collisionRetry;
STATE21A: FDR
port map
(
Q => collisionRetry, --[out]
C => Clk, --[in]
D => collisionRetry_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- retryWaitFifoEmpty state
----------------------------------------------------------------------------
goto_retryWaitFifoEmpty <= collisionRetry;
stay_retryWaitFifoEmpty <= retryWaitFifoEmpty and not(BusFifoEmpty);
retryWaitFifoEmpty_D <= goto_retryWaitFifoEmpty or stay_retryWaitFifoEmpty;
STATE22A: FDR
port map
(
Q => retryWaitFifoEmpty, --[out]
C => Clk, --[in]
D => retryWaitFifoEmpty_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- retryReset state
----------------------------------------------------------------------------
goto_retryReset <= retryWaitFifoEmpty and BusFifoEmpty;
retryReset_D <= goto_retryReset;
STATE23A: FDR
port map
(
Q => retryReset, --[out]
C => Clk, --[in]
D => retryReset_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- txDone2 state
----------------------------------------------------------------------------
goto_txDone2 <= txDone;
txDone2_D <= goto_txDone2;
STATE24A: FDR
port map
(
Q => txDone2, --[out]
C => Clk, --[in]
D => txDone2_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- txDonePause state
----------------------------------------------------------------------------
goto_txDonePause <= txDone2;
txDonePause_D <= goto_txDonePause;
STATE25A: FDR
port map
(
Q => txDonePause, --[out]
C => Clk, --[in]
D => txDonePause_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr1 state
----------------------------------------------------------------------------
goto_chgMacAdr1 <= idle and Mac_program_start and not mac_program_start_reg;
chgMacAdr1_D <= goto_chgMacAdr1 ;
STATE26A: FDR
port map
(
Q => chgMacAdr1, --[out]
C => Clk, --[in]
D => chgMacAdr1_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr2 state
----------------------------------------------------------------------------
goto_chgMacAdr2 <= chgMacAdr1;
chgMacAdr2_D <= goto_chgMacAdr2 ;
STATE27A: FDR
port map
(
Q => chgMacAdr2, --[out]
C => Clk, --[in]
D => chgMacAdr2_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr3 state
----------------------------------------------------------------------------
goto_chgMacAdr3 <= chgMacAdr2;
chgMacAdr3_D <= goto_chgMacAdr3 ;
STATE28A: FDR
port map
(
Q => chgMacAdr3, --[out]
C => Clk, --[in]
D => chgMacAdr3_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr4 state
----------------------------------------------------------------------------
goto_chgMacAdr4 <= chgMacAdr3;
chgMacAdr4_D <= goto_chgMacAdr4 ;
STATE29A: FDR
port map
(
Q => chgMacAdr4, --[out]
C => Clk, --[in]
D => chgMacAdr4_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr5 state
----------------------------------------------------------------------------
goto_chgMacAdr5 <= chgMacAdr4;
chgMacAdr5_D <= goto_chgMacAdr5 ;
STATE30A: FDR
port map
(
Q => chgMacAdr5, --[out]
C => Clk, --[in]
D => chgMacAdr5_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr6 state
----------------------------------------------------------------------------
goto_chgMacAdr6 <= chgMacAdr5;
chgMacAdr6_D <= goto_chgMacAdr6 ;
STATE31A: FDR
port map
(
Q => chgMacAdr6, --[out]
C => Clk, --[in]
D => chgMacAdr6_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr7 state
----------------------------------------------------------------------------
goto_chgMacAdr7 <= chgMacAdr6;
chgMacAdr7_D <= goto_chgMacAdr7 ;
STATE32A: FDR
port map
(
Q => chgMacAdr7, --[out]
C => Clk, --[in]
D => chgMacAdr7_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr8 state
----------------------------------------------------------------------------
goto_chgMacAdr8 <= chgMacAdr7;
chgMacAdr8_D <= goto_chgMacAdr8 ;
STATE33A: FDR
port map
(
Q => chgMacAdr8, --[out]
C => Clk, --[in]
D => chgMacAdr8_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr9 state
----------------------------------------------------------------------------
goto_chgMacAdr9 <= chgMacAdr8;
chgMacAdr9_D <= goto_chgMacAdr9 ;
STATE34A: FDR
port map
(
Q => chgMacAdr9, --[out]
C => Clk, --[in]
D => chgMacAdr9_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr10 state
----------------------------------------------------------------------------
goto_chgMacAdr10 <= chgMacAdr9;
chgMacAdr10_D <= goto_chgMacAdr10 ;
STATE35A: FDR
port map
(
Q => chgMacAdr10, --[out]
C => Clk, --[in]
D => chgMacAdr10_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr11 state
----------------------------------------------------------------------------
goto_chgMacAdr11 <= chgMacAdr10;
chgMacAdr11_D <= goto_chgMacAdr11 ;
STATE36A: FDR
port map
(
Q => chgMacAdr11, --[out]
C => Clk, --[in]
D => chgMacAdr11_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr12 state
----------------------------------------------------------------------------
goto_chgMacAdr12 <= chgMacAdr11;
chgMacAdr12_D <= goto_chgMacAdr12 ;
STATE37A: FDR
port map
(
Q => chgMacAdr12, --[out]
C => Clk, --[in]
D => chgMacAdr12_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr13 state
----------------------------------------------------------------------------
goto_chgMacAdr13 <= chgMacAdr12;
chgMacAdr13_D <= goto_chgMacAdr13 ;
STATE38A: FDR
port map
(
Q => chgMacAdr13, --[out]
C => Clk, --[in]
D => chgMacAdr13_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr14 state
----------------------------------------------------------------------------
goto_chgMacAdr14 <= chgMacAdr13;
chgMacAdr14_D <= goto_chgMacAdr14 ;
STATE39A: FDR
port map
(
Q => chgMacAdr14, --[out]
C => Clk, --[in]
D => chgMacAdr14_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- end of states
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- REG_PROCESS
----------------------------------------------------------------------------
-- This process registers all the signals on the bus clock.
----------------------------------------------------------------------------
REG_PROCESS : process (Clk)
begin --
if (Clk'event and Clk = '1') then -- rising clock edge
if (Rst = '1') then
phytx_en_reg <= '0';
busFifoWrCntRst_reg <= '0';
retrying_reg <= '0';
txCrcEn_reg <= '0';
transmit_start_reg <= '0';
mac_program_start_reg <= '0';
else
phytx_en_reg <= phytx_en_i;
busFifoWrCntRst_reg <= busFifoWrCntRst_i;
retrying_reg <= retrying_i;
txCrcEn_reg <= txCrcEn_i;
transmit_start_reg <= Transmit_start;
mac_program_start_reg <= Mac_program_start;
end if;
end if;
end process REG_PROCESS;
----------------------------------------------------------------------------
-- COMB_PROCESS
----------------------------------------------------------------------------
-- This process generate control signals for the state machine.
----------------------------------------------------------------------------
COMB_PROCESS : process (phytx_en_reg, busFifoWrCntRst_reg,
txCrcEn_reg, txDone, idle, preamble,
half_dup_error, checkBusFifoFull,
collisionRetry, retrying_reg,
checkBusFifoFullCrc, SFD, loadBusFifoCrc,
checkBusFifoFullSFD)
begin
-- Generate PHY Tx Enable
if (txDone='1' or idle='1') then
phytx_en_i <= '0';
elsif (preamble = '1') then
phytx_en_i <= '1';
else
phytx_en_i <= phytx_en_reg;
end if;
-- Generate BusFifo Write Counter reset
if (half_dup_error='1' or txDone='1' or idle='1') then
busFifoWrCntRst_i <= '1';
elsif (preamble = '1') then
busFifoWrCntRst_i <= '0';
else
busFifoWrCntRst_i <= busFifoWrCntRst_reg;
end if;
-- Generate retry signal in case of collision
if (collisionRetry='1') then
retrying_i <= '1';
elsif (idle = '1') then
retrying_i <= '0';
else
retrying_i <= retrying_reg;
end if;
-- Generate transmit CRC enable
if (checkBusFifoFull='1') then
txCrcEn_i <= '1';
elsif (checkBusFifoFullSFD='1' or checkBusFifoFullCRC='1' or SFD='1' or
idle='1' or loadBusFifoCrc='1' or preamble='1') then
txCrcEn_i <= '0';
else
txCrcEn_i <= txCrcEn_reg;
end if;
end process COMB_PROCESS;
----------------------------------------------------------------------------
-- FSMD_PROCESS
----------------------------------------------------------------------------
-- This process generate control signals for the state machine for
-- transmit operation
----------------------------------------------------------------------------
FSMD_PROCESS : process(crcCnt_is_0, JamTxNibCnt, goto_checkBusFifoFullCrc_1,
pre_SFD_zero, checkBusFifoFullJam, full_half_n,
retryReset, txDonePause, loadBusFifo, loadBusFifoJam,
checkCrc, txDone2, chgMacAdr2, chgMacAdr3,
chgMacAdr4, chgMacAdr5, chgMacAdr6, chgMacAdr7,
chgMacAdr8, chgMacAdr9, chgMacAdr10, chgMacAdr11,
chgMacAdr12, chgMacAdr13, chgMacAdr14, chgMacAdr1,
lngthDelay1, lngthDelay2, idle, checkBusFifoFull,
txDone, ldLngthCntr,half_dup_error, collisionRetry,
checkBusFifoFullCrc, loadBusFifoCrc, retrying_reg,
preamble, SFD)
begin
-- Enable JAM reset
if (checkBusFifoFullJam = '1' and pre_SFD_zero = '1' and
full_half_n = '0' and (JamTxNibCnt = "0111")) then
Jam_rst <= '1';
else
Jam_rst <= '0';
end if;
-- Bus FIFO write counte enable
BusFifoWrCntEn <= '1'; -- temp
-- Enable TX late collision reset
TxLateColnRst <= '0';
-- Enable TX deffer reset
TxExcessDefrlRst <= '0';
-- Enable back off and TX collision retry counter
if (collisionRetry = '1') then
InitBackoff <= '1';
TxColRetryCntEnbl <= '1';
else
InitBackoff <= '0';
TxColRetryCntEnbl <= '0';
end if;
-- Enable TX retry reset
if (retryReset = '1') or
(txDonePause = '1') then -- clear up any built up garbage in async
-- FIFOs at the end of a packet
TxRetryRst <= '1';
else
TxRetryRst <= '0';
end if;
-- Enable TX nibble counter reset
if (idle = '1') then
txNibbleCntRst_i <= '1';
else
txNibbleCntRst_i <= '0';
end if;
-- Enable TX collision retry reset
if (idle = '1' and retrying_reg = '0') then
TxColRetryCntRst_n <= '0';
else
TxColRetryCntRst_n <= '1';
end if;
-- Enable TX CRC counter shift
if ((checkBusFifoFullCrc = '1') or (loadBusFifoCrc = '1')) then
TxCrcShftOutEn <= '1';
else
TxCrcShftOutEn <= '0';
end if;
-- Enable Preamble in the frame
if (preamble = '1') then
EnblPre <= '1';
else
EnblPre <= '0';
end if;
-- Enable SFD in the frame
if (SFD = '1') then
EnblSFD <= '1';
else
EnblSFD <= '0';
end if;
-- Enable Data in the frame
if (loadBusFifo = '1') then
EnblData <= '1';
else
EnblData <= '0';
end if;
-- Enable CRC
if (loadBusFifoCrc = '1') then
EnblCRC <= '1';
else
EnblCRC <= '0';
end if;
-- Enable TX nibble counter load
if (SFD = '1') then
txNibbleCntLd_i <= '1';
else
txNibbleCntLd_i <= '0';
end if;
-- Enable clear for TX interface FIFO
if (checkBusFifoFullCrc = '1' and crcCnt_is_0 = '1') or
((checkBusFifoFullJam='1' or loadBusFifoJam='1')
and pre_SFD_zero = '1' and full_half_n = '0') or
(collisionRetry = '1' ) or (half_dup_error = '1') or
(checkCrc = '1' and goto_checkBusFifoFullCrc_1 = '0') then
Enblclear <= '1';
else
Enblclear <= '0';
end if;
-- Enable Bus FIFO write
if ((loadBusFifo = '1') or
(preamble = '1') or
(SFD = '1') or
(loadBusFifoCrc = '1')
) then
busFifoWr_i <= '1';
else
busFifoWr_i <= '0';
end if;
-- Enable JAM TX nibble
if (loadBusFifo = '1') then
txEnNibbleCnt_i <= '1';
else
txEnNibbleCnt_i <= '0';
end if;
-- Enable TX buffer address increment
if (loadBusFifo = '1') or (chgMacAdr2 = '1') or (chgMacAdr3 = '1') or
(chgMacAdr4 = '1') or (chgMacAdr5 = '1') or (chgMacAdr6 = '1') or
(chgMacAdr7 = '1') or (chgMacAdr8 = '1') or (chgMacAdr9 = '1') or
(chgMacAdr10 = '1') or (chgMacAdr11 = '1') or (chgMacAdr12 = '1') or
(chgMacAdr13 = '1') or (chgMacAdr14 = '1') then
Tx_addr_en <= '1';
else
Tx_addr_en <= '0';
end if;
-- Generate TX start after preamble
if (preamble = '1') or
(chgMacAdr1 = '1') then
Tx_start <= '1'; -- reset address to 0 for start of transmit
else
Tx_start <= '0';
end if;
-- TX DPM buffer CE
if (idle = '1') or
(lngthDelay1 = '1') or (lngthDelay2 = '1') or
(checkBusFifoFull = '1') or (ldLngthCntr = '1') or
(txDone = '1') or (txDone2 = '1') or (txDonePause = '1') or
(chgMacAdr1 = '1') or (chgMacAdr2 = '1') or (chgMacAdr3 = '1') or
(chgMacAdr4 = '1') or (chgMacAdr5 = '1') or (chgMacAdr6 = '1') or
(chgMacAdr7 = '1') or (chgMacAdr8 = '1') or (chgMacAdr9 = '1') or
(chgMacAdr10 = '1') or (chgMacAdr11 = '1') or (chgMacAdr12 = '1') or
(chgMacAdr13 = '1') or (chgMacAdr14 = '1') then
Tx_DPM_ce <= '1';
else
Tx_DPM_ce <= '0';
end if;
-- Enable JAM
if (loadBusFifoJam = '1') then
EnblJam <= '1';
else
EnblJam <= '0';
end if;
-- TX DPM write enable
Tx_DPM_wr_rd_n <= '0';
end process FSMD_PROCESS;
----------------------------------------------------------------------------
-- OUTPUT_REG1
----------------------------------------------------------------------------
-- This process generate mack address RAM write enable
----------------------------------------------------------------------------
OUTPUT_REG1:process (Clk)
begin
if (Clk'event and Clk='1') then
if (Rst = '1') then
Mac_addr_ram_we <= '0';
elsif (idle_D = '1') then
Mac_addr_ram_we <= '0';
elsif (chgMacAdr3_D = '1') or
(chgMacAdr4_D = '1') or
(chgMacAdr5_D = '1') or
(chgMacAdr6_D = '1') or
(chgMacAdr7_D = '1') or
(chgMacAdr8_D = '1') or
(chgMacAdr9_D = '1') or
(chgMacAdr10_D = '1') or
(chgMacAdr11_D = '1') or
(chgMacAdr12_D = '1') or
(chgMacAdr13_D = '1') or
(chgMacAdr14_D = '1') then
Mac_addr_ram_we <= '1';
else
Mac_addr_ram_we <= '0';
end if;
end if;
end process OUTPUT_REG1;
----------------------------------------------------------------------------
-- OUTPUT_REG2
----------------------------------------------------------------------------
-- This process MAC Addr RAM write Adrress to update the MAC address of
-- EMACLite Core.
----------------------------------------------------------------------------
OUTPUT_REG2:process (Clk)
begin
if (Clk'event and Clk='1') then
if (Rst = '1') then
Mac_addr_ram_addr_wr <= x"0";
else
if idle_D = '1' then
Mac_addr_ram_addr_wr <= x"0";
elsif chgMacAdr3_D = '1' then
Mac_addr_ram_addr_wr <= x"0";
elsif chgMacAdr4_D = '1' then
Mac_addr_ram_addr_wr <= x"1";
elsif chgMacAdr5_D = '1' then
Mac_addr_ram_addr_wr <= x"2";
elsif chgMacAdr6_D = '1' then
Mac_addr_ram_addr_wr <= x"3";
elsif chgMacAdr7_D = '1' then
Mac_addr_ram_addr_wr <= x"4";
elsif chgMacAdr8_D = '1' then
Mac_addr_ram_addr_wr <= x"5";
elsif chgMacAdr9_D = '1' then
Mac_addr_ram_addr_wr <= x"6";
elsif chgMacAdr10_D = '1' then
Mac_addr_ram_addr_wr <= x"7";
elsif chgMacAdr11_D = '1' then
Mac_addr_ram_addr_wr <= x"8";
elsif chgMacAdr12_D = '1' then
Mac_addr_ram_addr_wr <= x"9";
elsif chgMacAdr13_D = '1' then
Mac_addr_ram_addr_wr <= x"a";
elsif chgMacAdr14_D = '1' then
Mac_addr_ram_addr_wr <= x"b";
else
Mac_addr_ram_addr_wr <= x"0";
end if;
end if;
end if;
end process OUTPUT_REG2;
end implementation;
-------------------------------------------------------------------------------
-- tx_intrfce - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : tx_intrfce.vhd
-- Version : v2.0
-- Description : This is the ethernet transmit interface.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0_9 library is used for axi_ethernetlite_v3_0_9
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0_9;
use axi_ethernetlite_v3_0_9.all;
-------------------------------------------------------------------------------
library lib_cdc_v1_0_2;
library lib_fifo_v1_0_7;
--library fifo_generator_v11_0; --FIFO Hier
--use fifo_generator_v11_0.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Phy_tx_clk -- PHY TX Clock
-- Emac_tx_wr_data -- Ethernet transmit data
-- Tx_er -- Transmit error
-- Phy_tx_en -- Ethernet transmit enable
-- Tx_en -- Transmit enable
-- Emac_tx_wr -- TX FIFO write enable
-- Fifo_empty -- TX FIFO empty
-- Fifo_almost_emp -- TX FIFP almost empty
-- Fifo_full -- TX FIFO full
-- Phy_tx_data -- Ethernet transmit data
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity tx_intrfce is
generic
(
C_FAMILY : string := "virtex6"
);
port
(
Clk : in std_logic;
Rst : in std_logic;
Phy_tx_clk : in std_logic;
Emac_tx_wr_data : in std_logic_vector (0 to 3);
Tx_er : in std_logic;
PhyTxEn : in std_logic;
Tx_en : in std_logic;
Emac_tx_wr : in std_logic;
Fifo_empty : out std_logic;
Fifo_full : out std_logic;
Phy_tx_data : out std_logic_vector (0 to 5)
);
end tx_intrfce;
architecture implementation of tx_intrfce is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal bus_combo : std_logic_vector (0 to 5);
signal fifo_empty_i : std_logic;
signal fifo_empty_c : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- The following components are the building blocks of the EMAC
-------------------------------------------------------------------------------
component FDR
port
(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
--FIFO HIER
--component async_fifo_eth
-- port (
-- rst : in std_logic;
-- wr_clk : in std_logic;
-- rd_clk : in std_logic;
-- din : in std_logic_vector(5 downto 0);
-- wr_en : in std_logic;
-- rd_en : in std_logic;
-- dout : out std_logic_vector(5 downto 0);
-- full : out std_logic;
-- empty : out std_logic;
-- valid : out std_logic
-- );
--end component;
begin
I_TX_FIFO: entity lib_fifo_v1_0_7.async_fifo_fg
generic map(
C_ALLOW_2N_DEPTH => 0, -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY => C_FAMILY, -- new for FIFO Gen
C_DATA_WIDTH => 6,
C_ENABLE_RLOCS => 0, -- not supported in FG
C_FIFO_DEPTH => 15,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 0,
C_EN_SAFETY_CKT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => 2,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => 0, -- 0 = distributed RAM, 1 = BRAM
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => 2,
C_WR_ERR_LOW => 0
)
port map(
Din => bus_combo,
Wr_en => Emac_tx_wr,
Wr_clk => Clk,
Rd_en => Tx_en,
Rd_clk => Phy_tx_clk,
Ainit => Rst,
Dout => Phy_tx_data,
Full => Fifo_full,
Empty => fifo_empty_i,
Almost_full => open,
Almost_empty => open,
Wr_count => open,
Rd_count => open,
Rd_ack => open,
Rd_err => open,
Wr_ack => open,
Wr_err => open
);
-- I_TX_FIFO : async_fifo_eth
-- port map(
-- din => bus_combo,
-- wr_en => Emac_tx_wr,
-- wr_clk => Clk,
-- rd_en => Tx_en,
-- rd_clk => Phy_tx_clk,
-- rst => Rst,
-- dout => Phy_tx_data,
-- full => Fifo_full,
-- empty => fifo_empty_i,
-- valid => open
-- );
pipeIt: FDR
port map
(
Q => Fifo_empty, --[out]
C => Clk, --[in]
D => fifo_empty_c, --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- CDC module for syncing tx_en_i in fifo_empty domain
----------------------------------------------------------------------------
CDC_FIFO_EMPTY: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 3
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => fifo_empty_i,
prmry_ack => open,
scndry_out => fifo_empty_c,
scndry_aclk => Clk,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
bus_combo <= (Emac_tx_wr_data & Tx_er & PhyTxEn);
end implementation;
-------------------------------------------------------------------------------
-- rx_statemachine - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : rx_statemachine.vhd
-- Version : v2.0
-- Description : This file contains the receive control state machine.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std."+";
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0_9 library is used for axi_ethernetlite_v3_0_9
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0_9;
use axi_ethernetlite_v3_0_9.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Emac_rx_rd_data -- RX FIFO read data to controller
-- Rcv_en -- Receive enable
-- RxBusFifoRdAck -- RX FIFO read ack
-- BusFifoEmpty -- RX FIFO empty
-- Collision -- Collision detected
-- DataValid -- Data valid from PHY
-- RxError -- Receive error
-- BusFifoData -- RX FIFO data
-- CrcOk -- CRC correct in the receive data
-- BusFifoRd -- RX FIFO read
-- RxAbortRst -- Receive abort
-- RxCrcRst -- Receive CRC reset
-- RxCrcEn -- RX CRC enable
-- Rx_addr_en -- Receive address enable
-- Rx_start -- Receive start
-- Rx_done -- Receive complete
-- Rx_pong_ping_l -- RX Ping/Pong buffer enable
-- Rx_DPM_ce -- RX buffer chip enable
-- Rx_DPM_wr_data -- RX buffer write data
-- Rx_DPM_rd_data -- RX buffer read data
-- Rx_DPM_wr_rd_n -- RX buffer write read enable
-- Rx_idle -- RX idle
-- Mac_addr_ram_addr_rd -- MAC Addr RAM read address
-- Mac_addr_ram_data -- MAC Addr RAM read data
-- Rx_buffer_ready -- RX buffer ready to accept new packet
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity rx_statemachine is
generic (
C_DUPLEX : integer := 1
-- 1 = full duplex, 0 = half duplex
);
port (
Clk : in std_logic;
Rst : in std_logic;
Emac_rx_rd_data_d1 : in std_logic_vector(0 to 5); -- 03-26-04
Receive_enable : out std_logic; -- 03-26-04
RxBusFifoRdAck : in std_logic;
BusFifoEmpty : in std_logic;
Collision : in std_logic;
DataValid : in std_logic;
RxError : in std_logic;
BusFifoData : in std_logic_vector(0 to 3);
CrcOk : in std_logic;
BusFifoRd : out std_logic;
RxAbortRst : out std_logic;
RxCrcRst : out std_logic;
RxCrcEn : out std_logic;
Rx_addr_en : out std_logic;
Rx_start : out std_logic;
Rx_done : out std_logic;
Rx_pong_ping_l : in std_logic;
Rx_DPM_ce : out std_logic;
Rx_DPM_wr_data : out std_logic_vector (0 to 3);
Rx_DPM_rd_data : in std_logic_vector (0 to 3);
Rx_DPM_wr_rd_n : out std_logic;
Rx_idle : out std_logic;
Mac_addr_ram_addr_rd : out std_logic_vector(0 to 3);
Mac_addr_ram_data : in std_logic_vector (0 to 3);
Rx_buffer_ready : in std_logic
);
end rx_statemachine;
architecture imp of rx_statemachine is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
signal idle : std_logic; -- state 0
signal waitForSfd1 : std_logic; -- state 1
signal sfd1CheckBusFifoEmpty : std_logic; -- state 2
signal waitForSfd2 : std_logic; -- state 3
signal startReadDestAdrNib : std_logic; -- state 4
signal rdDestAddrNib_eq_0 : std_logic;
signal rdDestAddrNib_eq_12 : std_logic;
signal startReadDataNib : std_logic; -- state 17
signal crcCheck : std_logic; -- state 18
signal rxDone : std_logic; -- state 20
signal receiveRst : std_logic; -- state 21
signal rxCollision : std_logic; -- state 22
signal idle_D : std_logic; -- state 0
signal waitForSfd1_D : std_logic; -- state 1
signal sfd1CheckBusFifoEmpty_D : std_logic; -- state 2
signal waitForSfd2_D : std_logic; -- state 3
signal startReadDestAdrNib_D : std_logic; -- state 4
signal startReadDataNib_D : std_logic; -- state 17
signal crcCheck_D : std_logic; -- state 18
signal rxDone_D : std_logic; -- state 20
signal receiveRst_D : std_logic; -- state 21
signal rxCollision_D : std_logic; -- state 22
signal goto_idle_1 : std_logic; -- state 0
signal goto_idle_2 : std_logic; -- state 0
signal goto_idle_3 : std_logic; -- state 0
signal goto_idle_4 : std_logic; -- state 0
signal goto_waitForSfd1 : std_logic; -- state 1
signal goto_sfd1CheckBusFifoEmpty_1 : std_logic; -- state 2
signal goto_sfd1CheckBusFifoEmpty_2 : std_logic; -- state 2
signal goto_waitForSfd2 : std_logic; -- state 3
signal goto_startReadDestAdrNib_1 : std_logic; -- state 4
signal goto_readDestAdrNib1 : std_logic; -- state 5
signal goto_startReadDataNib_2 : std_logic; -- state 17
signal goto_crcCheck : std_logic; -- state 18
signal goto_rxDone_3 : std_logic; -- state 20
signal goto_receiveRst_1 : std_logic; -- state 21
signal goto_receiveRst_2 : std_logic; -- state 21
signal goto_receiveRst_3 : std_logic; -- state 21
signal goto_receiveRst_5 : std_logic; -- state 21
signal goto_receiveRst_9 : std_logic; -- state 21
signal goto_receiveRst_10 : std_logic; -- state 21
signal goto_receiveRst_14 : std_logic; -- state 21
signal goto_rxCollision_1 : std_logic; -- state 22
signal goto_rxCollision_2 : std_logic; -- state 22
signal goto_rxCollision_5 : std_logic; -- state 22
signal stay_idle : std_logic; -- state 0
signal stay_sfd1CheckBusFifoEmpty : std_logic; -- state 2
signal stay_startReadDestAdrNib : std_logic; -- state 4
signal stay_startReadDataNib : std_logic; -- state 17
signal state_machine_rst : std_logic;
signal full_half_n : std_logic;
signal checkingBroadcastAdr_i : std_logic;
signal checkingBroadcastAdr_reg : std_logic;
signal busFifoData_is_5 : std_logic;
signal busFifoData_is_13 : std_logic;
signal busFifoData_not_5 : std_logic;
signal busFifoData_not_13 : std_logic;
signal bcastAddrGood : std_logic;
signal ucastAddrGood : std_logic;
signal crcokr1 : std_logic;
signal crcokin : std_logic;
signal rxCrcEn_i : std_logic;
signal mac_addr_ram_addr_rd_D : std_logic_vector(0 to 3);
signal rdDestAddrNib_D_t : std_logic_vector(0 to 3);
signal rdDestAddrNib_D_t_q : std_logic_vector(0 to 3);
signal rxDone_i : std_logic;
signal preamble_valid : std_logic;
signal preamble_error_reg : std_logic;
signal preamble_error : std_logic;
signal busFifoData_is_5_d1 : std_logic;
signal busFifoData_is_5_d2 : std_logic;
signal busFifoData_is_5_d3 : std_logic;
signal pkt_length_cnt : integer range 0 to 127;
signal crc_rst : std_logic;
component FDR
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component FDS
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic
);
end component;
component FDRE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------
-- CRC check
----------------------------------------------------------------------------
crcokin <= ((CrcOk -- set
or crcokr1) -- keep
and (not(rxCrcEn_i) or CrcOk)); -- clear when 0
crcokdelay: FDR
port map (
Q => crcokr1, --[out]
C => Clk, --[in]
D => crcokin, --[in]
R => crc_rst --[in]
);
-- Added this to reset CRCokr1 before starting the next packet reception.
crc_rst <= Rst or (not CrcOk and crcokr1);
-- RX Complete indicator
Rx_done <= rxDone_i; -- added Rx_done output for ping pong control
-- Generate rxdone only if received framelength is greater than minimum
-- frame length
rxDone_i <= '1' when rxDone='1' and pkt_length_cnt=0 else
'0';
-- Check start of Frame
-- If receive data=5
busFifoData_is_5 <= not(BusFifoData(0)) and BusFifoData(1) and
not(BusFifoData(2)) and BusFifoData(3);
-- If receive data/=5
busFifoData_not_5 <= not(busFifoData_is_5);
-- If receive data=13
busFifoData_is_13 <= BusFifoData(0) and BusFifoData(1) and
not(BusFifoData(2)) and BusFifoData(3);
-- If receive data/=13
busFifoData_not_13 <= not(busFifoData_is_13);
-- State Machine Reset
state_machine_rst <= Rst;
----------------------------------------------------------------------------
-- idle state
----------------------------------------------------------------------------
goto_idle_1 <= rxDone;
goto_idle_2 <= receiveRst;
goto_idle_3 <= waitForSfd1 and (not(DataValid) or busFifoData_not_5);
goto_idle_4 <= waitForSfd2 and (not(DataValid) or
(busFifoData_not_5 and busFifoData_not_13));
stay_idle <= idle and not(goto_waitForSfd1);
idle_D <= goto_idle_1 or goto_idle_2 or goto_idle_3 or goto_idle_4
or stay_idle;
state0a: FDS
port map (
Q => idle, --[out]
C => Clk, --[in]
D => idle_D, --[in]
S => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- waitForSfd1 state
----------------------------------------------------------------------------
goto_waitForSfd1 <= idle and (RxBusFifoRdAck or not(BusFifoEmpty))
and (Rx_buffer_ready);
waitForSfd1_D <= goto_waitForSfd1;
state1a: FDR
port map (
Q => waitForSfd1, --[out]
C => Clk, --[in]
D => waitForSfd1_D, --[in]
R => state_machine_rst --[in]
);
Rx_idle <= idle or waitForSfd1;
----------------------------------------------------------------------------
-- sfd1CheckBusFifoEmpty state
----------------------------------------------------------------------------
goto_sfd1CheckBusFifoEmpty_1 <= waitForSfd1 and busFifoData_is_5
and DataValid;
goto_sfd1CheckBusFifoEmpty_2 <= waitForSfd2 and busFifoData_is_5
and DataValid;
stay_sfd1CheckBusFifoEmpty <= sfd1CheckBusFifoEmpty and
not(goto_rxCollision_1) and
not(goto_receiveRst_1) and
not(goto_waitForSfd2);
sfd1CheckBusFifoEmpty_D <= goto_sfd1CheckBusFifoEmpty_1 or
goto_sfd1CheckBusFifoEmpty_2 or
stay_sfd1CheckBusFifoEmpty;
state2a: FDR
port map (
Q => sfd1CheckBusFifoEmpty, --[out]
C => Clk, --[in]
D => sfd1CheckBusFifoEmpty_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- waitForSfd2 state
----------------------------------------------------------------------------
goto_waitForSfd2 <= sfd1CheckBusFifoEmpty and not(goto_rxCollision_1) and
not(goto_receiveRst_1) and (RxBusFifoRdAck or
not(BusFifoEmpty)) and
busFifoData_is_5;
waitForSfd2_D <= goto_waitForSfd2;
state3a: FDR
port map (
Q => waitForSfd2, --[out]
C => Clk, --[in]
D => waitForSfd2_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
--startReadDestAdrNib state
----------------------------------------------------------------------------
goto_startReadDestAdrNib_1 <= waitForSfd2 and busFifoData_is_13
and preamble_valid
and DataValid;
stay_startReadDestAdrNib <= startReadDestAdrNib and
not(goto_rxCollision_2) and
not(goto_receiveRst_2) and
not(goto_readDestAdrNib1);
startReadDestAdrNib_D <= goto_startReadDestAdrNib_1 or
stay_startReadDestAdrNib;
state4a: FDR
port map (
Q => startReadDestAdrNib, --[out]
C => Clk, --[in]
D => startReadDestAdrNib_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
--readDestAdrNib1 state
----------------------------------------------------------------------------
goto_readDestAdrNib1 <= startReadDestAdrNib and
not(goto_rxCollision_2) and
not(goto_receiveRst_2) and
RxBusFifoRdAck;
rdDestAddrNib_eq_0 <= bo2sl(rdDestAddrNib_D_t_q = "0000");
rdDestAddrNib_eq_12 <= bo2sl(rdDestAddrNib_D_t_q = "1011");
----------------------------------------------------------------------------
-- STATE_REG_PROCESS
----------------------------------------------------------------------------
-- Registeting the read destination address.
----------------------------------------------------------------------------
STATE_REG_PROCESS : process (Clk)
begin
if (Clk'event and Clk='1') then
if (state_machine_rst = '1' or
goto_startReadDestAdrNib_1 = '1') then
rdDestAddrNib_D_t_q <= "0000";
else
rdDestAddrNib_D_t_q <= rdDestAddrNib_D_t;
end if;
end if;
end process STATE_REG_PROCESS;
----------------------------------------------------------------------------
-- FSM_CMB_PROCESS
----------------------------------------------------------------------------
-- This process generate read destination address for the MAC address RAM
-- for the received frame.
----------------------------------------------------------------------------
FSM_CMB_PROCESS : process (startReadDestAdrNib,goto_rxCollision_2,
goto_receiveRst_2,RxBusFifoRdAck,goto_receiveRst_3,bcastAddrGood,
ucastAddrGood,goto_receiveRst_5,
rdDestAddrNib_D_t_q)
begin
----
rdDestAddrNib_D_t <= rdDestAddrNib_D_t_q;
case (rdDestAddrNib_D_t_q) is
when "0000" =>
if (startReadDestAdrNib and not(goto_rxCollision_2) and
not(goto_receiveRst_2) and RxBusFifoRdAck) = '1' then
rdDestAddrNib_D_t <= "0001";
else
rdDestAddrNib_D_t <= "0000";
end if;
when "0001" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0010";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0001";
end if;
when "0010" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0011";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0010";
end if;
when "0011" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0100";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0011";
end if;
when "0100" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0101";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0100";
end if;
when "0101" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0110";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0101";
end if;
when "0110" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0111";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0110";
end if;
when "0111" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "1000";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0111";
end if;
when "1000" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "1001";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "1000";
end if;
when "1001" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "1010";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "1001";
end if;
when "1010" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "1011";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "1010";
end if;
when "1011" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "1100";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "1011";
end if;
when "1100" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0000";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "1100";
end if;
when others => null;
end case;
end process FSM_CMB_PROCESS;
----------------------------------------------------------------------------
--startReadDataNib state
----------------------------------------------------------------------------
goto_startReadDataNib_2 <= rdDestAddrNib_eq_12 and RxBusFifoRdAck and
(bcastAddrGood or ucastAddrGood) and not(goto_receiveRst_5) and
not(goto_receiveRst_3);
stay_startReadDataNib <= startReadDataNib and not(goto_rxCollision_5)
and not(goto_receiveRst_9) and DataValid;
startReadDataNib_D <= goto_startReadDataNib_2
or stay_startReadDataNib;
state17a: FDR
port map (
Q => startReadDataNib, --[out]
C => Clk, --[in]
D => startReadDataNib_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
--crcCheck state
----------------------------------------------------------------------------
goto_crcCheck <= startReadDataNib and not(DataValid) ;
goto_receiveRst_1 <= sfd1CheckBusFifoEmpty and not(goto_rxCollision_1)
and RxError;
goto_receiveRst_2 <= startReadDestAdrNib and not(goto_rxCollision_2)
and RxError;
goto_receiveRst_9 <= startReadDataNib and not(goto_rxCollision_5)
and RxError;
crcCheck_D <= goto_crcCheck or goto_receiveRst_1 or
goto_receiveRst_2 or
goto_receiveRst_9;
state18a: FDR
port map (
Q => crcCheck, --[out]
C => Clk, --[in]
D => crcCheck_D, --[in]
R => state_machine_rst --[in]
);
-------------------------------------------------------------------------------
--rxDone state
-------------------------------------------------------------------------------
--goto_rxDone_3 <= writeFinalData ;
goto_rxDone_3 <= crcCheck and crcokr1;
rxDone_D <= goto_rxDone_3 ;
state20a: FDR
port map (
Q => rxDone, --[out]
C => Clk, --[in]
D => rxDone_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
--rxCollision state
----------------------------------------------------------------------------
full_half_n <= '1'when C_DUPLEX = 1 else
'0';
goto_rxCollision_1 <= sfd1CheckBusFifoEmpty and Collision
and not(full_half_n);
goto_rxCollision_2 <= startReadDestAdrNib and Collision
and not(full_half_n);
goto_rxCollision_5 <= startReadDataNib and Collision
and not(full_half_n);
rxCollision_D <= goto_rxCollision_1 or goto_rxCollision_2 or
goto_rxCollision_5;
state21a: FDR
port map (
Q => rxCollision, --[out]
C => Clk, --[in]
D => rxCollision_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
--receiveRst state
----------------------------------------------------------------------------
goto_receiveRst_3 <= not rdDestAddrNib_eq_0 and not(DataValid);
goto_receiveRst_5 <= not rdDestAddrNib_eq_0 and
not(BusFifoEmpty) and
not(bcastAddrGood or ucastAddrGood);
goto_receiveRst_10<= crcCheck and not(crcokr1);
goto_receiveRst_14<= rxCollision;
receiveRst_D <= goto_receiveRst_3 or
goto_receiveRst_5 or
goto_receiveRst_10 or
goto_receiveRst_14 or
preamble_error_reg;
state22a: FDR
port map (
Q => receiveRst, --[out]
C => Clk, --[in]
D => receiveRst_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- end of states
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- BROADCAST_ADDR_REG
----------------------------------------------------------------------------
-- This process generate control signals for the state machine.
----------------------------------------------------------------------------
BROADCAST_ADDR_REG : process (Clk)
begin --
if (Clk'event and Clk = '1') then -- rising clock edge
if (Rst = '1') then
checkingBroadcastAdr_reg <= '0';
else
checkingBroadcastAdr_reg <= checkingBroadcastAdr_i;
end if;
end if;
end process BROADCAST_ADDR_REG;
----------------------------------------------------------------------------
-- RX_FSMD_PROCESS
----------------------------------------------------------------------------
-- This process generate control signals for the state machine.
----------------------------------------------------------------------------
RX_FSMD_PROCESS : process( DataValid,RxBusFifoRdAck,idle,
startReadDestAdrNib, startReadDataNib,
sfd1CheckBusFifoEmpty, rxDone, receiveRst,
waitForSfd2, Emac_rx_rd_data_d1,
checkingBroadcastAdr_reg, rdDestAddrNib_eq_0,
rdDestAddrNib_D_t_q)
begin
-- Reset RX CRC in idle state
if (idle = '1') then
RxCrcRst <= '1';
else
RxCrcRst <= '0';
end if;
-- RX CRC enable
if ((( startReadDestAdrNib or (not rdDestAddrNib_eq_0) or
(startReadDataNib and DataValid))
and RxBusFifoRdAck) = '1') then
RxCrcEn <= '1';
rxCrcEn_i <= '1';
else
RxCrcEn <= '0';
rxCrcEn_i <= '0';
end if;
-- RX buffer FIFO read enable
if ((idle = '1') or
(sfd1CheckBusFifoEmpty = '1') or
(not rdDestAddrNib_eq_0 = '1') or
(rxDone = '1') or -- 03-26-04
(startReadDestAdrNib = '1') or
(startReadDataNib = '1')) and (RxBusFifoRdAck = '0')then
BusFifoRd <= '1';
else
BusFifoRd <= '0';
end if;
-- RX abort reset
if (receiveRst = '1') then
RxAbortRst <= '1';
else
RxAbortRst <= '0';
end if;
-- RX buffer address enable
if RxBusFifoRdAck = '1' and
(
(startReadDestAdrNib = '1') or -- 03-26-04
(not rdDestAddrNib_eq_0 = '1') or
(startReadDataNib = '1')
) then
Rx_addr_en <= '1'; --enable address increment
else
Rx_addr_en <= '0';
end if;
-- Generate RX start after SFD is detected
if (waitForSfd2 = '1')then
Rx_start <= '1'; -- reset address to 0 for start of receive
else
Rx_start <= '0';
end if;
-- RX buffer chip enable
if (idle = '1') or
((
(startReadDestAdrNib = '1') or -- 03-26-04
(not rdDestAddrNib_eq_0 = '1') or
(startReadDataNib = '1')
) and (RxBusFifoRdAck = '1')
) then
Rx_DPM_ce <= '1';
else
Rx_DPM_ce <= '0';
end if;
-- RX buffer read/write enable
if (startReadDestAdrNib = '1') or -- 03-26-04
(not rdDestAddrNib_eq_0 = '1') or
(startReadDataNib = '1') then
Rx_DPM_wr_rd_n <= '1';
else
Rx_DPM_wr_rd_n <= '0';
end if;
-- RX buffer chip enable
if (idle = '1') then
checkingBroadcastAdr_i <= '0'; -- reset
-- 06-09-04 Use delayed data for compare
elsif (rdDestAddrNib_D_t_q = x"1" and
Emac_rx_rd_data_d1(0 to 3) = x"f") then
checkingBroadcastAdr_i <= '1'; -- set
else
checkingBroadcastAdr_i <= checkingBroadcastAdr_reg; -- stay the same
end if;
end process RX_FSMD_PROCESS;
-- write data to Receive DPRAM
Rx_DPM_wr_data <= BusFifoData;
----------------------------------------------------------------------------
-- MARAR_PROC
----------------------------------------------------------------------------
-- This process generate MAC RAM address to get mac addres to compare with
-- incoming frame destination address
----------------------------------------------------------------------------
MARAR_PROC : process (rdDestAddrNib_D_t, idle_D, startReadDestAdrNib_D)
begin
case rdDestAddrNib_D_t is
when "0001" => mac_addr_ram_addr_rd_D <= x"0";
when "0010" => mac_addr_ram_addr_rd_D <= x"1";
when "0011" => mac_addr_ram_addr_rd_D <= x"2";
when "0100" => mac_addr_ram_addr_rd_D <= x"3";
when "0101" => mac_addr_ram_addr_rd_D <= x"4";
when "0110" => mac_addr_ram_addr_rd_D <= x"5";
when "0111" => mac_addr_ram_addr_rd_D <= x"6";
when "1000" => mac_addr_ram_addr_rd_D <= x"7";
when "1001" => mac_addr_ram_addr_rd_D <= x"8";
when "1010" => mac_addr_ram_addr_rd_D <= x"9";
when "1011" => mac_addr_ram_addr_rd_D <= x"a";
when "1100" => mac_addr_ram_addr_rd_D <= x"b";
when others => mac_addr_ram_addr_rd_D <= x"0";
end case;
-- Reset the address in idle or start of new frame
if (idle_D or startReadDestAdrNib_D) = '1' then
mac_addr_ram_addr_rd_D <= x"0";
end if;
end process MARAR_PROC;
----------------------------------------------------------------------------
-- OUTPUT_REG
----------------------------------------------------------------------------
-- Registerit the mac_addr_ram_addr_rd
----------------------------------------------------------------------------
OUTPUT_REG:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
Mac_addr_ram_addr_rd <= (others => '0');
else
Mac_addr_ram_addr_rd <= mac_addr_ram_addr_rd_D;
end if;
end if;
end process OUTPUT_REG;
----------------------------------------------------------------------------
-- Check if the incoming packet is broadcast packet
----------------------------------------------------------------------------
bcastAddrGood <= '1' when checkingBroadcastAdr_i = '1' and
Emac_rx_rd_data_d1(0 to 3) = x"F" else -- 03-26-04
'0';
----------------------------------------------------------------------------
-- Check if the incoming packet is unicast and address matches to core
-- MAC address
----------------------------------------------------------------------------
ucastAddrGood <= '1' when checkingBroadcastAdr_i = '0' and
(Emac_rx_rd_data_d1(0 to 3) = Mac_addr_ram_data)
else -- 03-26-04
'0';
-- Genarate Receive enable
Receive_enable <= not(crcCheck or rxDone or receiveRst);
----------------------------------------------------------------------------
-- PROCESS : PKT_LENGTH_COUNTER
----------------------------------------------------------------------------
-- This counter is used to check if the receive packet length is greater
-- minimum packet length (64 byte - 128 nibble)
----------------------------------------------------------------------------
PKT_LENGTH_COUNTER : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1' or preamble_error_reg = '1' ) then
pkt_length_cnt <= 0;
elsif goto_readDestAdrNib1 = '1' then -- load the counter for
pkt_length_cnt <= 127; -- minimum packet length
elsif (rxCrcEn_i='1') then -- Enable Down Counter
if (pkt_length_cnt = 0) then
pkt_length_cnt <= 0;
else
pkt_length_cnt <= pkt_length_cnt - 1;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : SFD_CHECK_REG
----------------------------------------------------------------------------
-- This process registers the preamble nibble to checl if atleast last 2
-- preamble nibbles are valid before the SFD nibble.
----------------------------------------------------------------------------
SFD_CHECK_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1' ) then
busFifoData_is_5_d1 <= '0';
busFifoData_is_5_d2 <= '0';
busFifoData_is_5_d3 <= '0';
elsif RxBusFifoRdAck = '1' then
busFifoData_is_5_d1 <= busFifoData_is_5;
busFifoData_is_5_d2 <= busFifoData_is_5_d1;
busFifoData_is_5_d3 <= busFifoData_is_5_d2;
end if;
end if;
end process;
preamble: FDR
port map (
Q => preamble_error_reg, --[out]
C => Clk, --[in]
D => preamble_error, --[in]
R => state_machine_rst --[in]
);
-- Premable valid
preamble_valid <= (busFifoData_is_5_d1) and
busFifoData_is_13;
-- Premable Error
preamble_error <= (not busFifoData_is_5 and
busFifoData_is_5_d1 and
not busFifoData_is_13) and waitForSfd2 ;
end imp;
-------------------------------------------------------------------------------
-- rx_intrfce - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : rx_intrfce.vhd
-- Version : v2.0
-- Description : This is the ethernet receive interface.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0_9 library is used for axi_ethernetlite_v3_0_9
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0_9;
use axi_ethernetlite_v3_0_9.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library lib_cdc_v1_0_2;
use lib_cdc_v1_0_2.all;
library lib_fifo_v1_0_7;
use lib_fifo_v1_0_7.all;
--library fifo_generator_v11_0; -- FIFO HIER
--use fifo_generator_v11_0.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
library unisim;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Phy_rx_clk -- PHY RX Clock
-- InternalWrapEn -- Internal wrap enable
-- Phy_rx_er -- Receive error
-- Phy_dv -- Ethernet receive enable
-- Phy_rx_data -- Ethernet receive data
-- Rcv_en -- Receive enable
-- Fifo_empty -- RX FIFO empty
-- Fifo_full -- RX FIFO full
-- Emac_rx_rd -- RX FIFO Read enable
-- Emac_rx_rd_data -- RX FIFO read data to controller
-- RdAck -- RX FIFO read ack
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity rx_intrfce is
generic
(
C_FAMILY : string := "virtex6"
);
port (
Clk : in std_logic;
Rst : in std_logic;
Phy_rx_clk : in std_logic;
InternalWrapEn : in std_logic;
Phy_rx_er : in std_logic;
Phy_dv : in std_logic;
Phy_rx_data : in std_logic_vector (0 to 3);
Rcv_en : in std_logic;
Fifo_empty : out std_logic;
Fifo_full : out std_logic;
Emac_rx_rd : in std_logic;
Emac_rx_rd_data : out std_logic_vector (0 to 5);
RdAck : out std_logic
);
end rx_intrfce;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- No Generics were used for this Entity.
--
-- Definition of Ports:
--
-------------------------------------------------------------------------------
architecture implementation of rx_intrfce is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal rxBusCombo : std_logic_vector (0 to 5);
signal rx_wr_en : std_logic;
signal rx_data : std_logic_vector (0 to 5);
signal rx_fifo_full : std_logic;
signal rx_fifo_empty : std_logic;
signal rx_rd_ack : std_logic;
signal rst_s : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- The following components are the building blocks of the EMAC
-------------------------------------------------------------------------------
--FIFI HIER
--component async_fifo_eth
-- port (
-- rst : in std_logic;
-- wr_clk : in std_logic;
-- rd_clk : in std_logic;
-- din : in std_logic_vector(5 downto 0);
-- wr_en : in std_logic;
-- rd_en : in std_logic;
-- dout : out std_logic_vector(5 downto 0);
-- full : out std_logic;
-- empty : out std_logic;
-- valid : out std_logic
-- );
--end component;
begin
----------------------------------------------------------------------------
-- CDC module for syncing reset in wr clk domain
----------------------------------------------------------------------------
CDC_FIFO_RST: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => Rst,
prmry_ack => open,
scndry_out => rst_s,
scndry_aclk => Phy_rx_clk,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
I_RX_FIFO: entity lib_fifo_v1_0_7.async_fifo_fg
generic map(
C_ALLOW_2N_DEPTH => 0, -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY => C_FAMILY, -- new for FIFO Gen
C_DATA_WIDTH => 6,
C_ENABLE_RLOCS => 0, -- not supported in FG
C_FIFO_DEPTH => 15,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 0,
C_EN_SAFETY_CKT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => 2,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => 0, -- 0 = distributed RAM, 1 = BRAM
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => 2,
C_WR_ERR_LOW => 0
)
port map(
Din => rxBusCombo,
Wr_en => rx_wr_en,
Wr_clk => Phy_rx_clk,
Rd_en => Emac_rx_rd,
Rd_clk => Clk,
Ainit => rst_s,
Dout => rx_data,
Full => rx_fifo_full,
Empty => rx_fifo_empty,
Almost_full => open,
Almost_empty => open,
Wr_count => open,
Rd_count => open,
Rd_ack => rx_rd_ack,
Rd_err => open,
Wr_ack => open,
Wr_err => open
);
-- FIFO HIER
-- I_RX_FIFO : async_fifo_eth
-- port map(
-- din => rxBusCombo,
-- wr_en => rx_wr_en,
-- wr_clk => Phy_rx_clk,
-- rd_en => Emac_rx_rd,
-- rd_clk => Clk,
-- rst => Rst,
-- dout => rx_data,
-- full => rx_fifo_full,
-- empty => rx_fifo_empty,
-- valid => rx_rd_ack
-- );
rxBusCombo <= (Phy_rx_data & Phy_dv & Phy_rx_er);
Emac_rx_rd_data <= rx_data;
RdAck <= rx_rd_ack;
Fifo_full <= rx_fifo_full;
Fifo_empty <= rx_fifo_empty;
--rx_wr_en <= Rcv_en;
rx_wr_en <= not(rx_fifo_full); -- having this as Rcv_en is generated in lite_clock domain and passing to FIFO working in rx_clk domain
end implementation;
-------------------------------------------------------------------------------
-- ram16x4 - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2007, 2008, 2009 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename : ram16x4.vhd
-- Version : v4.00.a
-- Description: This is a LUT RAM design to provide 4 bits wide and 16 bits
-- deep memory structue. The initial string for rom16x4 is
-- specially designed to ease the initialization of this memory.
-- The initialization value is taken from the "INIT_XX" string.
-- Each string is read in the standard Xilinx format, which is to
-- take the right-most character as the least significant bit.
-- INIT_00 is for address 0 to address 3, INIT_01 is for address
-- 4 to address 7, ..., INIT_03 is for address 12 to address 15.
-- Uses 16 LUTs (16 RAM16x1)
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0_9 library is used for axi_ethernetlite_v3_0_9
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0_9;
use axi_ethernetlite_v3_0_9.mac_pkg.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity ram16x4 is
generic(
INIT_00 : bit_vector(15 downto 0) :=x"0000";-- for addr(3 downto 0)
INIT_01 : bit_vector(15 downto 0) :=x"0000";-- for addr(7 downto 4)
INIT_02 : bit_vector(15 downto 0) :=x"0000";-- for addr(11 downto 8)
INIT_03 : bit_vector(15 downto 0) :=x"0000" -- for addr(15 downto 12)
);
port(
Addr : in std_logic_vector(3 downto 0);
D : in std_logic_vector(3 downto 0);
We : in std_logic;
Clk : in std_logic;
Q : out std_logic_vector(3 downto 0));
end entity ram16x4 ;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of ram16x4 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
attribute INIT : string ;
attribute INIT of ram16x1_0 : label is GetInitString4(0, INIT_00,INIT_01,
INIT_02, INIT_03);
attribute INIT of ram16x1_1 : label is GetInitString4(1, INIT_00,INIT_01,
INIT_02, INIT_03);
attribute INIT of ram16x1_2 : label is GetInitString4(2, INIT_00,INIT_01,
INIT_02, INIT_03);
attribute INIT of ram16x1_3 : label is GetInitString4(3, INIT_00,INIT_01,
INIT_02, INIT_03);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic ( init : bit_vector);
-- synopsys translate_on
-- synthesis translate_on
port (
a0 : in std_logic;
a1 : in std_logic;
a2 : in std_logic;
a3 : in std_logic;
d : in std_logic;
we : in std_logic;
wclk : in std_logic;
o : out std_logic);
end component;
begin
-----------------------------------------------------------------------------
-- RAM 0
-----------------------------------------------------------------------------
ram16x1_0 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(0, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(0), we => We, wclk => Clk, o => Q(0));
-----------------------------------------------------------------------------
-- RAM 1
-----------------------------------------------------------------------------
ram16x1_1 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(1, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(1), we => We, wclk => Clk, o => Q(1));
-----------------------------------------------------------------------------
-- RAM 2
-----------------------------------------------------------------------------
ram16x1_2 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(2, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(2), we => We, wclk => Clk, o => Q(2));
-----------------------------------------------------------------------------
-- RAM 3
-----------------------------------------------------------------------------
ram16x1_3 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(3, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(3), we => We, wclk => Clk, o => Q(3));
end imp;
-------------------------------------------------------------------------------
-- msh_cnt - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : msh_cnt.vhd
-- Version : v2.0
-- Description : A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the Rst signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_ADD_SUB_NOT -- 1 = Arith Add, 0 = Arith Substract
-- C_REG_WIDTH -- Width of data
-- C_RESET_VALUE -- Default value for the operation. Must be specified.
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Q -- Counter data out
-- Z -- Indicates '0' when decrementing
-- LD -- Counter load data
-- AD -- Counter load arithmatic data
-- LOAD -- Counter load enable
-- OP -- Counter arith operation enable
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity msh_cnt is
generic
(
-----------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
-----------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 8;
-----------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector
-----------------------------------------------------------------------
);
port
(
Clk : in std_logic;
Rst : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
Z : out std_logic; -- indicates 0 when decrementing
LD : in std_logic_vector(0 to C_REG_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_REG_WIDTH-1); -- Arith data.
LOAD : in std_logic; -- Enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD.)
);
end msh_cnt;
architecture imp of msh_cnt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MULT_AND
port
(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic
);
end component;
component MUXCY_L is
port
(
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic
);
end component MUXCY_L;
component XORCY is
port
(
LI : in std_logic;
CI : in std_logic;
O : out std_logic
);
end component XORCY;
component FDRE is
port
(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port
(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i : std_logic_vector(0 to C_REG_WIDTH-1);
signal q_i_ns : std_logic_vector(0 to C_REG_WIDTH-1);
signal xorcy_out : std_logic_vector(0 to C_REG_WIDTH-1);
signal gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
signal z_i : std_logic;
begin
Q <= q_i;
cry(C_REG_WIDTH) <= '0' when C_ADD_SUB_NOT else OP;
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, ClkEn : std_logic;
begin
-----------------------------------------------------------------------
-- Assign to load_bit the bit from input port LD.
-----------------------------------------------------------------------
load_bit <= LD(j);
-----------------------------------------------------------------------
-- Assign to arith_bit the bit from input port AD.
-----------------------------------------------------------------------
arith_bit <= AD(j);
-----------------------------------------------------------------------
-- LUT output generation.
-- Adder case
-----------------------------------------------------------------------
Q_I_GEN_ADD: if C_ADD_SUB_NOT generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
-----------------------------------------------------------------------
-- Subtractor case
-----------------------------------------------------------------------
Q_I_GEN_SUB: if not C_ADD_SUB_NOT generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
-----------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
-----------------------------------------------------------------------
MULT_AND_i1: MULT_AND
port map
(
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
-----------------------------------------------------------------------
-- Propagate the carry (borrow) out.
-----------------------------------------------------------------------
MUXCY_L_i1: MUXCY_L
port map
(
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
LO => cry(j)
);
-----------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
-----------------------------------------------------------------------
XORCY_i1: XORCY
port map
(
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
STOP_AT_0_SUB: if not C_ADD_SUB_NOT generate
ClkEn <= (LOAD or OP) when (not (conv_integer(q_i) = 0)) else '0';
end generate STOP_AT_0_SUB;
STOP_AT_MSB_ADD : if C_ADD_SUB_NOT generate
ClkEn <= LOAD or OP;
end generate STOP_AT_MSB_ADD;
-----------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
-----------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map
(
Q => q_i(j),
C => Clk,
CE => ClkEn,
D => xorcy_out(j),
R => Rst
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map
(
Q => q_i(j),
C => Clk,
CE => ClkEn,
D => xorcy_out(j),
S => Rst
);
end generate;
end generate;
z_i <= '1' when ((conv_integer(q_i) = 1)) else '0';
z_ff: FDSE
port map
(
Q => Z,
C => Clk,
CE => '1',
D => z_i,
S => Rst
);
end imp;
-------------------------------------------------------------------------------
-- deferral - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : deferral.vhd
-- Version : v2.0
-- Description : This file contains the transmit deferral control.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0_9 library is used for axi_ethernetlite_v3_0_9
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0_9;
use axi_ethernetlite_v3_0_9.mac_pkg.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- TxEn -- Transmit enable
-- Txrst -- Transmit reset
-- Tx_clk_en -- Transmit clock enable
-- BackingOff -- Backing off
-- Crs -- Carrier sense
-- Full_half_n -- Full/Half duplex indicator
-- Ifgp1 -- Interframe gap delay
-- Ifgp2 -- Interframe gap delay
-- Deferring -- Deffering for the tx data
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity deferral is
port
(
Clk : in std_logic;
Rst : in std_logic;
TxEn : in std_logic;
Txrst : in std_logic;
Tx_clk_en : in std_logic;
BackingOff : in std_logic;
Crs : in std_logic;
Full_half_n : in std_logic;
Ifgp1 : in std_logic_vector(0 to 4);
Ifgp2 : in std_logic_vector(0 to 4);
Deferring : out std_logic
);
end deferral;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- No Generics were used for this Entity.
--
-- Definition of Ports:
--
-------------------------------------------------------------------------------
architecture implementation of deferral is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal cntrLd_i : std_logic;
signal cntrEn : std_logic;
signal comboCntrEn : std_logic;
signal comboCntrEn2 : std_logic;
signal ifgp1_zero : std_logic;
signal ifgp2_zero : std_logic;
signal comboRst : std_logic;
begin
comboRst <= Rst or Txrst;
comboCntrEn <= Tx_clk_en and cntrEn;
comboCntrEn2 <= Tx_clk_en and cntrEn and ifgp1_zero;
-------------------------------------------------------------------------------
-- Ifgp1 counter
-------------------------------------------------------------------------------
inst_ifgp1_count: entity axi_ethernetlite_v3_0_9.cntr5bit
port map
(
Clk => Clk,
Rst => comboRst,
En => comboCntrEn,
Ld => cntrLd_i,
Load_in => Ifgp1,
Zero => ifgp1_zero
);
-------------------------------------------------------------------------------
-- Ifgp2 counter
-------------------------------------------------------------------------------
inst_ifgp2_count: entity axi_ethernetlite_v3_0_9.cntr5bit
port map
(
Clk => Clk,
Rst => comboRst,
En => comboCntrEn2,
Ld => cntrLd_i,
Load_in => Ifgp2,
Zero => ifgp2_zero
);
-------------------------------------------------------------------------------
-- deferral state machine
-------------------------------------------------------------------------------
inst_deferral_state: entity axi_ethernetlite_v3_0_9.defer_state
port map
(
Clk => Clk,
Rst => Rst,
TxEn => TxEn,
Txrst => Txrst,
Ifgp2Done => ifgp2_zero,
Ifgp1Done => ifgp1_zero,
BackingOff => BackingOff,
Crs => Crs,
Full_half_n => Full_half_n,
Deferring => Deferring,
CntrEnbl => cntrEn,
CntrLd => cntrLd_i
);
end implementation;
-------------------------------------------------------------------------------
-- crcgentx - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : crcgentx.vhd
-- Version : v4.00.a
-- Description : This module does an 4-bit parallel CRC generation.
-- The polynomial is that specified for IEEE 802.3 (ethernet)
-- LANs and other standards.
--
-- I. Functionality:
-- 1. The module does an 4-bit parallel CRC generation.
-- 2. The module provides a synchronous 4-bit per clock load and
-- unload function.
-- 3. The polynomial is that specified for 802.3 LANs and other
-- standards.
-- The polynomial computed is:
-- G(x)=X**32+X**26+X**23+X**22+X**16+X**12+X**11+X**10+X**8
-- +X**7+X**5+X**4+X** >2+X+1
--
-- II. Module I/O
-- Inputs: Clk, Clken, RESET, LOAD, COMPUTE, DATA_IN[3:0]
-- outputs: CRC_OK, DATA_OUT[3:0], CRC[31:0]
--
-- III.Truth Table:
--
-- Clken RESET COMPUTE LOAD | DATA_OUT
-- ------------------------------------------
-- 0 X X X | No change
-- 1 0 0 0 | No change
-- 1 1 X X | 0xFFFF (all ones)
-- 1 0 X 1 | load and shift 1 nibble of crc
-- 1 0 1 0 | Compute CRC
--
-- 0 0 1 1 | unload 4 byte crc
-- NOT IMPLEMENTED)
--
-- Loading and unloading of the 32-bit CRC register is done one
-- nibble at a time by asserting LOAD and Clken. The Data on
-- data_in is shifted into the the LSB of the CRC register. The
-- MSB of the CRC register is available on data_out.
--
-- Signals ending in _n are active low.
--
-- Copyright 1997 VAutomation Inc. Nashua NH USA (603) 882-2282.
-- Modification for 4 Bit done by Ronald Hecht @ Xilinx Inc.
-- This software is provided AS-IS and free of charge with the restriction that
-- this copyright notice remain in all copies of the Source Code at all times.
-- Visit HTTP://www.vautomation.com for more information on our cores.
-------------------------------------------------------------------------------
-- We add a nibble shift register into this module.
-- This module contains two parts.
--
-- 1. parallel_crc function which is a function will calculate the crc value.
-- 2. nibShitReg is a nibble shift register which has two operations
-- when DataEn goes high it will act as a normal register,
-- when OutEn goes high it will stop load new Data and shift out current
-- register Data by nibbles.
--
-- Some specification on module and port
--
-- 1. For nibShiftReg, give initial value to all zeros. This is because the initial
-- value for parallel_crc need to be all ones. Because we put a not on both
-- side of nibShiftReg, so we need to set it's value to all zeros at the
-- beginning.
-- 2. Don't shift the nibShiftReg at the first OutEn clock cycle, because the
-- first nibble is already there.
--
-- THE INTERFACE REQUIREMENTS OF THIS MODULE
--
-- Rst reset everything to initial value. We must give this reset
-- before we use crc module, otherwise the result will incorrect.
-- dataClk For use with mactx module, it will be 2.5 MHZ.
-- Data Input Data from other module in nibbles.
-- DataEn Enable crcgenrx. Make sure your enable and first Data can be
-- captured at the beginning of Data stream.
-- crcOk At the end of Data stream, this will go high if the crc is
-- correct.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- xemac.vhd
-- \
-- \-- axi_ipif_interface.vhd
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ ethernetlite_v3_0_dmem_v2.edn
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- ethernetlite_v3_0_dmem_v2.edn
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0_9 library is used for axi_ethernetlite_v3_0_9
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0_9;
use axi_ethernetlite_v3_0_9.mac_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Clke -- Clock enable
-- Data -- Data in
-- DataEn -- Data valid
-- OutEn -- Dataout enable
-- CrcNibs -- CRC nibble out
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity crcgentx is
port
(
Clk : in std_logic;
Rst : in std_logic;
Clken : in std_logic;
Data : in std_logic_vector(3 downto 0);
DataEn : in std_logic;
OutEn : in std_logic; -- NSR shift out enable
CrcNibs : out std_logic_vector(3 downto 0)
);
end crcgentx;
architecture arch1 of crcgentx is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of arch1 : architecture is "yes";
constant CRC_REMAINDER : std_logic_vector(31 downto 0) :=
"11000111000001001101110101111011"; -- 0xC704DD7B
function parallel_crc (crc_in : std_logic_vector(31 downto 0);
data_in : std_logic_vector(3 downto 0)
) return std_logic_vector is
variable c, crc_out : std_logic_vector(31 downto 0);
variable x : std_logic_vector (31 downto 28);
variable d : std_logic_vector (3 downto 0);
begin
-- Because the equations are long I am keeping the name of the incoming
-- CRC and the XOR vector short.
c := crc_in;
d := data_in;
-- the first thing that a parallel CRC needs to do is to develop the
-- vector formed by XORing the input vector by the current CRC. This
-- vector is then used during the CRC calculation.
x := (c(31) xor d(3)) & (c(30) xor d(2)) &
(c(29) xor d(1)) & (c(28) xor d(0));
-- The parellel CRC is a function of the X vector and the current CRC.
crc_out :=
(c(27) ) &
(c(26) ) &
(c(25) xor x(31) ) &
(c(24) xor x(30) ) &
(c(23) xor x(29) ) &
(c(22) xor x(31) xor x(28) ) &
(c(21) xor x(31) xor x(30) ) &
(c(20) xor x(30) xor x(29) ) &
(c(19) xor x(29) xor x(28) ) &
(c(18) xor x(28) ) &
(c(17) ) &
(c(16) ) &
(c(15) xor x(31) ) &
(c(14) xor x(30) ) &
(c(13) xor x(29) ) &
(c(12) xor x(28) ) &
(c(11) xor x(31) ) &
(c(10) xor x(31) xor x(30) ) &
(c(9 ) xor x(31) xor x(30) xor x(29) ) &
(c(8 ) xor x(30) xor x(29) xor x(28) ) &
(c(7 ) xor x(31) xor x(29) xor x(28) ) &
(c(6 ) xor x(31) xor x(30) xor x(28) ) &
(c(5 ) xor x(30) xor x(29) ) &
(c(4 ) xor x(31) xor x(29) xor x(28) ) &
(c(3 ) xor x(31) xor x(30) xor x(28) ) &
(c(2 ) xor x(30) xor x(29) ) &
(c(1 ) xor x(31) xor x(29) xor x(28) ) &
(c(0 ) xor x(31) xor x(30) xor x(28) ) &
( x(31) xor x(30) xor x(29) ) &
( x(30) xor x(29) xor x(28) ) &
( x(29) xor x(28) ) &
( x(28) );
return(crc_out);
end parallel_crc;
---------------------------------------------------------
-- A function which can reverse the bit order
-- order -- BY ben 07/04
---------------------------------------------------------
function revBitOrder( arg : std_logic_vector) return std_logic_vector is -- By ben 07/04/2000
variable tmp : std_logic_vector(arg'range);
begin
lp0 : for i in arg'range loop
tmp(arg'high - i) := arg(i);
end loop lp0;
return tmp;
end revBitOrder;
signal regDataIn, regDataOut, crcFuncIn, crcFuncOut: std_logic_vector(31 downto 0);
signal data_transpose : std_logic_vector(3 downto 0);
signal shiftEnable : std_logic;
-- component crcnibshiftreg
-- port (
-- Clk : in std_logic;
-- Clken : in std_logic;
-- Rst : in std_logic;
-- din : in std_logic_vector(31 downto 0);
-- load : in std_logic;
-- shift : in std_logic;
-- dout : out std_logic_vector(31 downto 0)
-- );
-- end component;
begin ----------------------------------------------------------------------
-----------------------------------------------------------------------------
-- This nibble shift register act as a normal register when DataEn is
-- high. When shiftEnable goes high, this register will stop load Data
-- and begin to shift Data out in nibbles.
-- Rember to check the initial value of this register which should be
-- all '0', otherwise the initial value for parallel_crc will not be
-- all '1'. This is related with the functions we put on input and output
-- of this register.
-----------------------------------------------------------------------------
NSR : entity axi_ethernetlite_v3_0_9.crcnibshiftreg
port map
(
Clk => Clk,
Clken => Clken,
Rst => Rst,
Din => regDataIn,
Load => DataEn,
Shift => shiftEnable,
Dout => regDataOut
);
shiftEnable <= OutEn and not DataEn;
crcFuncOut <= parallel_crc(crcFuncIn,data_transpose);
---------------------------------------------------------------------------------
-- These two sets of functions at input/output are balanced and the synthesis
-- tool will optimize them. The purpose is to let the register have all the Data
-- in right order before shift them.
---------------------------------------------------------------------------------
regDataIn <= not revBitOrder(crcFuncOut);
crcFuncIn <= not revBitOrder(regDataOut);
CrcNibs <= regDataOut(3 downto 0);
data_transpose <= Data(0) & Data(1) & Data(2) & Data(3);
end arch1;
-------------------------------------------------------------------------------
-- crcgenrx - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : crcgenrx.vhd
-- Version : v4.00.a
-- Description : This module does an 4-bit parallel CRC generation.
-- The polynomial is that specified for IEEE 802.3 (ethernet)
-- LANs and other standards.
--
-- I. Functionality:
-- 1. The module does an 4-bit parallel CRC generation.
-- 2. The module provides a synchronous 4-bit per clock load and
-- unload function.
-- 3. The polynomial is that specified for 802.3 LANs and other
-- standards.
-- The polynomial computed is:
-- G(x)=X**32+X**26+X**23+X**22+X**16+X**12+X**11+X**10+X**8
-- +X**7+X**5+X**4+X** >2+X+1
--
-- II. Module I/O
-- Inputs: Clk, CLKEN, Rst, LOAD, COMPUTE, DATA_IN[3:0]
-- outputs: CRC_OK, DATA_OUT[3:0], CRC[31:0]
--
-- III.Truth Table:
--
-- CLKEN Rst COMPUTE LOAD | DATA_OUT
-- ------------------------------------------
-- 0 X X X | No change
-- 1 0 0 0 | No change
-- 1 1 X X | 0xFFFF (all ones)
-- 1 0 X 1 | load and shift 1 nibble of crc
-- 1 0 1 0 | Compute CRC
--
-- 0 0 1 1 | unload 4 byte crc
-- NOT IMPLEMENTED)
--
-- Loading and unloading of the 32-bit CRC register is done one
-- nibble at a time by asserting LOAD and CLKEN. The Data on
-- data_in is shifted into the the LSB of the CRC register. The
-- MSB of the CRC register is available on data_out.
--
-- Signals ending in _n are active low.
--
-- Copyright 1997 VAutomation Inc. Nashua NH USA (603) 882-2282.
-- Modification for 4 Bit done by Ronald Hecht @ Xilinx Inc.
-- This software is provided AS-IS and free of charge with the restriction that
-- this copyright notice remain in all copies of the Source Code at all times.
-- Visit HTTP://www.vautomation.com for more information on our cores.
-------------------------------------------------------------------------------
-- We remove the 32 bits register which restore the crc value in the old code.
-- For receive part we only need to know the crc is ok or not, so remove the
-- register for restoring crc value will save some resources.
--
-- THE INTERFACE REQUIREMENTS OF THIS MODULE
--
-- Rst reset everything to initial value. We must give this reset
-- before we use crc module, otherwise the result will incorrect.
-- Clk For use with mactx module, it will be 2.5 MHZ.
-- Data Input Data from other module in nibbles.
-- DataEn Enable crcgenrx. Make sure your enable and first Data can be
-- captured at the beginning of Data stream.
-- CrcOk At the end of Data stream, this will go high if the crc is
-- correct.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- xemac.vhd
-- \
-- \-- axi_ipif_interface.vhd
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ ethernetlite_v3_0_dmem_v2.edn
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- ethernetlite_v3_0_dmem_v2.edn
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0_9 library is used for axi_ethernetlite_v3_0_9
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0_9;
use axi_ethernetlite_v3_0_9.mac_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Data -- Data in
-- DataEn -- Data enable
-- CrcOk -- CRC valid
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity crcgenrx is
port
(
Clk : in std_logic;
Rst : in std_logic;
Data : in std_logic_vector(3 downto 0);
DataEn : in std_logic;
CrcOk : out std_logic
);
end crcgenrx;
architecture arch1 of crcgenrx is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of arch1 : architecture is "yes";
constant CRC_REMAINDER : std_logic_vector(31 downto 0) :=
"11000111000001001101110101111011";
-- 0xC704DD7B
signal crc_local : std_logic_vector(31 downto 0); -- local version
signal data_transpose : std_logic_vector(3 downto 0);
function parallel_crc (crc_in : std_logic_vector(31 downto 0);
data_in : std_logic_vector(3 downto 0)
) return std_logic_vector is
variable c, crc_out : std_logic_vector(31 downto 0);
variable x : std_logic_vector (31 downto 28);
variable d : std_logic_vector (3 downto 0);
begin
-- Because the equations are long I am keeping the name of the incoming
-- CRC and the XOR vector short.
c := crc_in;
d := data_in;
-- the first thing that a parallel CRC needs to do is to develop the
-- vector formed by XORing the input vector by the current CRC. This
-- vector is then used during the CRC calculation.
x := (c(31) xor d(3)) & (c(30) xor d(2)) &
(c(29) xor d(1)) & (c(28) xor d(0));
-- The parellel CRC is a function of the X vector and the current CRC.
crc_out :=
(c(27) ) &
(c(26) ) &
(c(25) xor x(31) ) &
(c(24) xor x(30) ) &
(c(23) xor x(29) ) &
(c(22) xor x(31) xor x(28) ) &
(c(21) xor x(31) xor x(30) ) &
(c(20) xor x(30) xor x(29) ) &
(c(19) xor x(29) xor x(28) ) &
(c(18) xor x(28) ) &
(c(17) ) &
(c(16) ) &
(c(15) xor x(31) ) &
(c(14) xor x(30) ) &
(c(13) xor x(29) ) &
(c(12) xor x(28) ) &
(c(11) xor x(31) ) &
(c(10) xor x(31) xor x(30) ) &
(c(9 ) xor x(31) xor x(30) xor x(29) ) &
(c(8 ) xor x(30) xor x(29) xor x(28) ) &
(c(7 ) xor x(31) xor x(29) xor x(28) ) &
(c(6 ) xor x(31) xor x(30) xor x(28) ) &
(c(5 ) xor x(30) xor x(29) ) &
(c(4 ) xor x(31) xor x(29) xor x(28) ) &
(c(3 ) xor x(31) xor x(30) xor x(28) ) &
(c(2 ) xor x(30) xor x(29) ) &
(c(1 ) xor x(31) xor x(29) xor x(28) ) &
(c(0 ) xor x(31) xor x(30) xor x(28) ) &
( x(31) xor x(30) xor x(29) ) &
( x(30) xor x(29) xor x(28) ) &
( x(29) xor x(28) ) &
( x(28) );
return(crc_out);
end parallel_crc;
begin ------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Xilinx modification, use asynchronous clear
-------------------------------------------------------------------------------
data_transpose <= Data(0) & Data(1) & Data(2) & Data(3);
-- Reverse the bit order
-- Create the 32 Flip flops (with clock enable flops)
CRC_REG : process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
crc_local <= (others=>'1');
elsif DataEn = '1' then
crc_local <= parallel_crc(crc_local, data_transpose);
end if;
end if;
end process CRC_REG;
-------------------------------------------------------------------------------
-- Xilinx modification, remove reset from mux
-------------------------------------------------------------------------------
CrcOk <= '1' when crc_local = CRC_REMAINDER else '0';
-- This is a 32-bit wide AND
-- function, so proper
-- attention should be paid
-- when synthesizing to
-- achieve good results. If
-- there are cycles available
-- pipeling this gate would be
-- appropriate.
end arch1;
-------------------------------------------------------------------------------
-- bocntr - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : bocntr.vhd
-- Version : v2.0
-- Description : This is the transmit collision back off counter
-- the back off delay for retry n (1 <= n <= 16) is defined as
-- delay where delay is a uniformly distributed integer number
-- of slot times (512 bit times) defined as
-- 0 <= delay <= 2^k where k is min(n, 10) i.e., k is equal
-- to the retry attempt up to 10 and then remains at 10 for
-- retry attempts 11 through 16. So the delay for retry 1
-- would be 0, 1, or 2 slot times. The delay for retry 2
-- would be 0, 1, 2, 3, or 4 slot times.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0_9 library is used for axi_ethernetlite_v3_0_9
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0_9;
use axi_ethernetlite_v3_0_9.mac_pkg.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Clken -- Clock enable
-- InitBackoff -- Backoff initialized
-- RetryCnt -- Retry count
-- BackingOff -- Backing off from transmit
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity bocntr is
port (
Clk : in std_logic; -- tx Clk based (2.5 or 25 MHz)
Clken : in std_logic;
Rst : in std_logic;
InitBackoff : in std_logic;
RetryCnt : in std_logic_vector(0 to 4);
BackingOff : out std_logic);
end bocntr;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- No Generics were used for this Entity.
--
-- Definition of Ports:
--
-------------------------------------------------------------------------------
architecture implementation of bocntr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Constants used in this design are found in mac_pkg.vhd
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
type StateName is (idle, shifting, inBackoff);
signal thisState : StateName;
signal nextState : StateName;
signal initBackoffLtch : std_logic;
signal initBackoffLtchRst : std_logic;
signal backingOff_i : std_logic;
signal lfsrOut : std_logic;
signal slotCntRst : std_logic;
signal slotCntEnbl : std_logic;
signal slotCnt : std_logic_vector(0 to 6);
signal backOffCntLd : std_logic;
signal backOffCntEnbl : std_logic;
signal backOffCnt : std_logic_vector(0 to 9);
signal shftCntLd : std_logic;
signal shftCntEnbl : std_logic;
signal shftCnt : std_logic_vector(0 to 3);
signal shftRst : std_logic;
signal shftEnbl : std_logic;
signal shftData : std_logic_vector(0 to 9);
signal slotDone : std_logic;
signal numRetries : std_logic_vector(0 to 3);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
LFSRP : entity axi_ethernetlite_v3_0_9.lfsr16
port map(
Rst => Rst,
Clk => Clk,
Clken => Clken,
Enbl => shftEnbl,
Shftout => lfsrOut);
numRetries <= "1010" when (((RetryCnt(1) = '1') and -- 8 or larger and
((RetryCnt(3) = '1') or -- 10, 11, 14, 15 or
(RetryCnt(2) = '1'))) or -- 12 thru 15
(RetryCnt(0) = '1')) else -- 12 thru 15
RetryCnt(1 to 4); -- 9 or less
-------------------------------------------------------------------------------
-- INT_SHFT_PROCESS
-------------------------------------------------------------------------------
INT_SHFT_PROCESS : process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Clken = '1') then
if shftRst = '1' then
shftData <= (others => '0');
elsif (shftEnbl = '1') then
shftData(9) <= lfsrOut;
shftData(8) <= shftData(9);
shftData(7) <= shftData(8);
shftData(6) <= shftData(7);
shftData(5) <= shftData(6);
shftData(4) <= shftData(5);
shftData(3) <= shftData(4);
shftData(2) <= shftData(3);
shftData(1) <= shftData(2);
shftData(0) <= shftData(1);
-- coverage off
else
null;
-- coverage on
end if;
end if;
end if;
end process INT_SHFT_PROCESS;
-------------------------------------------------------------------------------
-- INT_SLOT_COUNT_PROCESS
-------------------------------------------------------------------------------
INT_SLOT_COUNT_PROCESS: process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Clken = '1') then
if ((slotCntRst = '1') or (slotDone = '1')) then
slotCnt <= "1111111";
elsif (slotCntEnbl = '1' and not(slotCnt = "0000000")) then
slotCnt <= slotCnt - 1;
-- coverage off
else
null;
-- coverage on
end if;
end if;
end if;
end process INT_SLOT_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- INT_BACKOFF_COUNT_PROCESS
-------------------------------------------------------------------------------
INT_BACKOFF_COUNT_PROCESS: process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Clken = '1') then
if (backOffCntLd = '1') then
backOffCnt <= shftData;
elsif (backOffCntEnbl = '1' and not(backOffCnt = "0000000000") and
(slotDone = '1')) then
backOffCnt <= backOffCnt - 1;
-- coverage off
else
null;
-- coverage on
end if;
end if;
end if;
end process INT_BACKOFF_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- INT_SHIFT_COUNT_PROCESS
-------------------------------------------------------------------------------
INT_SHIFT_COUNT_PROCESS: process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Clken = '1') then
if (shftCntLd = '1') then
shftCnt <= numRetries;
elsif (shftCntEnbl = '1' and not(shftCnt = "0000")) then
shftCnt <= shftCnt - 1;
-- coverage off
else
null;
-- coverage on
end if;
end if;
end if;
end process INT_SHIFT_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- INT_BACKOFFDONE_PROCESS
-------------------------------------------------------------------------------
INT_BACKOFFDONE_PROCESS: process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Rst = '1') then
backingOff_i <= '0';
elsif (InitBackoff = '1') then
backingOff_i <= '1';
elsif ((backOffCntEnbl = '1') and (backOffCnt = "000000000")) then
backingOff_i <= '0';
-- coverage off
else
null;
-- coverage on
end if;
end if;
end process INT_BACKOFFDONE_PROCESS;
BackingOff <= backingOff_i;
-------------------------------------------------------------------------------
-- INT_SLOT_TIME_DONE_PROCESS
-------------------------------------------------------------------------------
INT_SLOT_TIME_DONE_PROCESS: process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Rst = '1') then
slotDone <= '0';
elsif (slotCntEnbl = '0') then
slotDone <= '0';
elsif ((slotDone = '1') and (Clken = '1')) then
slotDone <= '0';
elsif ((slotCntEnbl = '1') and (slotCnt = "0000000")) then
slotDone <= '1';
else
null;
end if;
end if;
end process INT_SLOT_TIME_DONE_PROCESS;
-------------------------------------------------------------------------------
-- INT_LATCH_PROCESS
-------------------------------------------------------------------------------
INT_LATCH_PROCESS: process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Rst = '1') then
initBackoffLtch <= '0';
elsif (InitBackoff = '1') then
initBackoffLtch <= '1';
elsif (initBackoffLtchRst = '1') then
initBackoffLtch <= '0';
-- coverage off
else
null;
-- coverage on
-- coverage on
end if;
end if;
end process INT_LATCH_PROCESS;
-------------------------------------------------------------------------------
-- An FSM that deals with backing off
-------------------------------------------------------------------------------
FSMR : process (Clk)
begin --
if (Clk'event and Clk = '1') then -- rising clock edge
if (Rst = '1') then
thisState <= idle;
elsif (Clken = '1') then
thisState <= nextState;
end if;
end if;
end process FSMR;
-------------------------------------------------------------------------------
-- State Machine
-------------------------------------------------------------------------------
FSMC : process (thisState,initBackoffLtch,shftCnt,backOffCnt)
begin --
case thisState is
when idle =>
if (initBackoffLtch = '1') then
nextState <= shifting;
else
nextState <= idle;
end if;
when shifting =>
if (shftCnt = "0000") then
nextState <= inBackoff;
else
nextState <= shifting;
end if;
when inBackoff =>
if (backOffCnt = "000000000") then
nextState <= idle;
else
nextState <= inBackoff;
end if;
-- coverage off
when others => null;
nextState <= idle;
-- coverage on
end case;
end process FSMC;
-------------------------------------------------------------------------------
-- State Machine Control signals generation
-------------------------------------------------------------------------------
FSMD : process(thisState)
begin
if (thisState = idle) then
shftRst <= '1';
shftCntLd <= '1';
else
shftRst <= '0';
shftCntLd <= '0';
end if;
if ((thisState = idle) or (thisState = shifting)) then
slotCntRst <= '1';
backOffCntLd <= '1';
else
slotCntRst <= '0';
backOffCntLd <= '0';
end if;
if (thisState = shifting) then
shftCntEnbl <= '1';
shftEnbl <= '1';
initBackoffLtchRst <= '1';
else
shftCntEnbl <= '0';
shftEnbl <= '0';
initBackoffLtchRst <= '0';
end if;
if (thisState = inBackoff) then
slotCntEnbl <= '1';
backOffCntEnbl <= '1';
else
slotCntEnbl <= '0';
backOffCntEnbl <= '0';
end if;
end process FSMD;
end implementation;
-------------------------------------------------------------------------------
-- transmit - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : transmit.vhd
-- Version : v2.0
-- Description : This is the transmit path portion of the design
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use ieee.numeric_std."-";
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0_9 library is used for axi_ethernetlite_v3_0_9
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0_9;
use axi_ethernetlite_v3_0_9.mac_pkg.all;
-------------------------------------------------------------------------------
library lib_cdc_v1_0_2;
use lib_cdc_v1_0_2.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
--library simprim;
-- synopsys translate_on
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-- C_FAMILY -- Target device family
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- NibbleLength -- Transmit frame nibble length
-- NibbleLength_orig -- Transmit nibble length before pkt adjustment
-- En_pad -- Enable padding
-- TxClkEn -- Transmit clock enable
-- Phy_tx_clk -- PHY TX Clock
-- Phy_crs -- Ethernet carrier sense
-- Phy_col -- Ethernet collision indicator
-- Phy_tx_en -- Ethernet transmit enable
-- Phy_tx_data -- Ethernet transmit data
-- Tx_addr_en -- TX buffer address enable
-- Tx_start -- TX start
-- Tx_done -- TX complete
-- Tx_pong_ping_l -- TX Ping/Pong buffer enable
-- Tx_idle -- TX idle
-- Tx_DPM_ce -- TX buffer chip enable
-- Tx_DPM_wr_data -- TX buffer write data
-- Tx_DPM_rd_data -- TX buffer read data
-- Tx_DPM_wr_rd_n -- TX buffer write/read enable
-- Transmit_start -- Transmit start
-- Mac_program_start -- MAC Program start
-- Mac_addr_ram_we -- MAC Address RAM write enable
-- Mac_addr_ram_addr_wr -- MAC Address RAM write address
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity transmit is
generic
(
C_DUPLEX : integer := 1; -- 1 = full duplex, 0 = half duplex
C_FAMILY : string := "virtex6"
);
port
(
Clk : in std_logic;
Rst : in std_logic;
NibbleLength : in std_logic_vector(0 to 11);
NibbleLength_orig : in std_logic_vector(0 to 11);
En_pad : in std_logic;
TxClkEn : in std_logic;
Phy_tx_clk : in std_logic;
Phy_crs : in std_logic;
Phy_col : in std_logic;
Phy_tx_en : out std_logic;
Phy_tx_data : out std_logic_vector (0 to 3);
Tx_addr_en : out std_logic;
Tx_start : out std_logic;
Tx_done : out std_logic;
Tx_pong_ping_l : in std_logic;
Tx_idle : out std_logic;
Tx_DPM_ce : out std_logic;
Tx_DPM_wr_data : out std_logic_vector (0 to 3);
Tx_DPM_rd_data : in std_logic_vector (0 to 3);
Tx_DPM_wr_rd_n : out std_logic;
Transmit_start : in std_logic;
Mac_program_start : in std_logic;
Mac_addr_ram_we : out std_logic;
Mac_addr_ram_addr_wr : out std_logic_vector(0 to 3)
);
end transmit;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- No Generics were used for this Entity.
--
-- Definition of Ports:
--
-------------------------------------------------------------------------------
architecture imp of transmit is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant logic_one :std_logic := '1';
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal tx_d_rst : std_logic;
signal full_half_n : std_logic;
signal bus_combo : std_logic_vector (0 to 5);
signal txChannelReset : std_logic;
signal emac_tx_wr_i : std_logic;
signal txfifo_full : std_logic;
signal txfifo_empty : std_logic;
signal tx_en_i : std_logic;
signal tx_en_i_tx_clk : std_logic;
signal fifo_tx_en : std_logic;
signal axi_fifo_tx_en : std_logic;
signal txNibbleCntLd : std_logic;
signal txNibbleCntEn : std_logic;
signal txNibbleCntRst : std_logic;
signal txComboNibbleCntRst : std_logic;
--signal phy_tx_en_i : std_logic;
signal phy_tx_en_i_p : std_logic;
signal axi_phy_tx_en_i_p : std_logic;
signal deferring : std_logic;
signal txBusFifoWrCntRst : std_logic;
signal txBusFifoWrCntEn : std_logic;
signal txComboBusFifoWrCntRst : std_logic;
signal txComboBusFifoWrCntEn : std_logic;
signal txComboColRetryCntRst_n : std_logic;
signal txComboBusFifoRst : std_logic;
signal txColRetryCntRst_n : std_logic;
signal enblPreamble : std_logic;
signal enblSFD : std_logic;
signal enblData : std_logic;
signal enblJam : std_logic;
signal enblCRC : std_logic;
signal txCntEnbl : std_logic;
signal txColRetryCntEnbl : std_logic;
signal jamTxComboNibCntEnbl : std_logic;
signal txRetryRst : std_logic;
signal txLateColnRst : std_logic;
signal initBackoff : std_logic;
signal backingOff_i : std_logic;
signal txCrcShftOutEn : std_logic;
signal txCrcEn : std_logic;
signal crcComboRst : std_logic;
signal emac_tx_wr_data_i : std_logic_vector (0 to 3);
signal crcCnt : std_logic_vector(0 to 3);
signal collisionRetryCnt : std_logic_vector(0 to 4);
signal jamTxNibbleCnt : std_logic_vector(0 to 3);
signal colWindowNibbleCnt : std_logic_vector(0 to 7);
signal prb : std_logic_vector(0 to 3);
signal sfd : std_logic_vector(0 to 3);
signal jam : std_logic_vector(0 to 3);
signal crc : std_logic_vector(0 to 3);
signal currentTxBusFifoWrCnt : std_logic_vector(0 to 11);
signal currentTxNibbleCnt : std_logic_vector (0 to 11);
signal phy_tx_en_n : std_logic;
signal txComboColRetryCntRst : std_logic;
signal phy_tx_en_i_n : std_logic;
signal jam_rst : std_logic;
signal txExcessDefrlRst : std_logic;
signal enblclear : std_logic;
signal tx_en_mod : std_logic;
signal emac_tx_wr_mod : std_logic;
signal pre_sfd_done : std_logic;
signal mux_in_data : std_logic_vector (0 to 6*4-1);
signal mux_in_sel : std_logic_vector (0 to 5);
signal transmit_data : std_logic_vector (0 to 3);
signal txNibbleCnt_pad : unsigned (0 to 11);
signal tx_idle_i : std_logic;
signal emac_tx_wr_data_d1 : std_logic_vector (0 to 3);
signal emac_tx_wr_d1 : std_logic;
signal txcrcen_d1 : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component FDRE
port
(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component FDCE
port
(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end component;
begin
----------------------------------------------------------------------------
-- tx crc generator
----------------------------------------------------------------------------
INST_CRCGENTX: entity axi_ethernetlite_v3_0_9.crcgentx
port map
(
Clk => Clk,
Rst => crcComboRst,
Clken => emac_tx_wr_d1,
Data => emac_tx_wr_data_d1,
DataEn => txcrcen_d1,
OutEn => txCrcShftOutEn,
CrcNibs => crc
);
crcComboRst <= Rst or not (tx_en_i); -- having tx_en form same clock domain as Clk
-- crcComboRst <= Rst or not (fifo_tx_en);
----------------------------------------------------------------------------
-- tx interface contains the ethernet tx fifo
----------------------------------------------------------------------------
INST_TX_INTRFCE: entity axi_ethernetlite_v3_0_9.tx_intrfce
generic map
(
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Rst => txComboBusFifoRst,
Phy_tx_clk => Phy_tx_clk,
Emac_tx_wr_data => emac_tx_wr_data_i,
Tx_er => '0',
PhyTxEn => tx_en_mod,
Tx_en => fifo_tx_en,
Fifo_empty => txfifo_empty,
Fifo_full => txfifo_full,
Emac_tx_wr => emac_tx_wr_mod,
Phy_tx_data => bus_combo
);
txComboBusFifoRst <= Rst or txRetryRst or
(jam_rst and not(full_half_n) and
Phy_col and pre_sfd_done);
jam <= "0110"; -- arbitrary
prb <= "0101"; -- transmitted as 1010
sfd <= "1101"; -- transmitted as 1011
----------------------------------------------------------------------------
-- PHY output selection
----------------------------------------------------------------------------
mux_in_sel <= enblPreamble & enblSFD & enblData & enblJam & enblCRC &
logic_one;
mux_in_data <= prb & sfd & transmit_data & jam & crc & "0000";
transmit_data <= "0000" when (txNibbleCnt_pad = 0) else
Tx_DPM_rd_data;
Tx_idle <= tx_idle_i;
----------------------------------------------------------------------------
-- Multiplexing PHY transmit data
----------------------------------------------------------------------------
ONR_HOT_MUX:entity axi_ethernetlite_v3_0_9.mux_onehot_f
generic map
(
C_DW => 4,
C_NB => 6,
C_FAMILY => C_FAMILY
)
port map
(
D => mux_in_data,
S => mux_in_sel,
Y => emac_tx_wr_data_i
);
----------------------------------------------------------------------------
-- PHY transmit data
----------------------------------------------------------------------------
Phy_tx_data <= "0110" when (Phy_col = '1' or
not(jamTxNibbleCnt(0) = '1' and
jamTxNibbleCnt(1) = '0' and
jamTxNibbleCnt(2) = '0' and
jamTxNibbleCnt(3) = '1')) and
full_half_n = '0' and
not (jamTxNibbleCnt = "0000") and
pre_sfd_done = '1' else
"0000" when jamTxNibbleCnt = "0000" and
full_half_n = '0' else
"0000" when axi_phy_tx_en_i_p = '0' else
bus_combo(0 to 3);
----------------------------------------------------------------------------
-- PHY transmit enable
----------------------------------------------------------------------------
Phy_tx_en <= '1' when (Phy_col = '1' or
not(jamTxNibbleCnt(0) = '1' and
jamTxNibbleCnt(1) = '0' and
jamTxNibbleCnt(2) = '0' and
jamTxNibbleCnt(3) = '1')) and
full_half_n = '0' and
not (jamTxNibbleCnt = "0000") and
pre_sfd_done = '1' else
'0' when jamTxNibbleCnt = "0000" and
full_half_n = '0' else
'0' when axi_phy_tx_en_i_p = '0' else
bus_combo(5);
----------------------------------------------------------------------------
-- transmit packet fifo read nibble counter
----------------------------------------------------------------------------
INST_TXNIBBLECOUNT: entity axi_ethernetlite_v3_0_9.ld_arith_reg
generic map
(
C_ADD_SUB_NOT => false,
C_REG_WIDTH => 12,
C_RESET_VALUE => "000000000000",
C_LD_WIDTH => 12,
C_LD_OFFSET => 0,
C_AD_WIDTH => 12,
C_AD_OFFSET => 0
)
port map
(
CK => Clk,
Rst => txComboNibbleCntRst,
Q => currentTxNibbleCnt,
LD => NibbleLength,
AD => "000000000001",
LOAD => txNibbleCntLd,
OP => txNibbleCntEn
);
txComboNibbleCntRst <= Rst or txNibbleCntRst or txRetryRst;
----------------------------------------------------------------------------
-- PROCESS : PKT_TX_PAD_COUNTER
----------------------------------------------------------------------------
-- This counter is used to check if the receive packet length is greater
-- minimum packet length (64 byte - 128 nibble)
----------------------------------------------------------------------------
PKT_TX_PAD_COUNTER : process(Clk)
begin
if (Clk'event and Clk='1') then
if (Rst=RESET_ACTIVE) then
txNibbleCnt_pad <= (others=>'0');
elsif (enblSFD='1') then -- load the counter for minimum
txNibbleCnt_pad <= unsigned(NibbleLength_orig); -- packet length
elsif (enblData='1' and En_pad='1') then -- Enable Down Counter
if (txNibbleCnt_pad=0 ) then
txNibbleCnt_pad <= (others=>'0');
else
txNibbleCnt_pad <= txNibbleCnt_pad-1;
end if;
end if;
end if;
end process PKT_TX_PAD_COUNTER;
----------------------------------------------------------------------------
-- transmit state machine
----------------------------------------------------------------------------
INST_TX_STATE_MACHINE: entity axi_ethernetlite_v3_0_9.tx_statemachine
generic map
(
C_DUPLEX => C_DUPLEX
)
port map
(
Clk => Clk,
Rst => txChannelReset,
TxClkEn => TxClkEn,
Jam_rst => jam_rst,
TxRst => txChannelReset,
Deferring => deferring,
ColRetryCnt => collisionRetryCnt,
ColWindowNibCnt => colWindowNibbleCnt,
JamTxNibCnt => jamTxNibbleCnt,
TxNibbleCnt => currentTxNibbleCnt,
BusFifoWrNibbleCnt => currentTxBusFifoWrCnt,
CrcCnt => crcCnt,
BusFifoFull => txfifo_full,
BusFifoEmpty => txfifo_empty,
PhyCollision => Phy_col,
InitBackoff => initBackoff,
TxRetryRst => txRetryRst,
TxExcessDefrlRst => txExcessDefrlRst,
TxLateColnRst => txLateColnRst,
TxColRetryCntRst_n => txColRetryCntRst_n,
TxColRetryCntEnbl => txColRetryCntEnbl,
TxNibbleCntRst => txNibbleCntRst,
TxEnNibbleCnt => txNibbleCntEn,
TxNibbleCntLd => txNibbleCntLd,
BusFifoWrCntRst => txBusFifoWrCntRst,
BusFifoWrCntEn => txBusFifoWrCntEn,
EnblPre => enblPreamble,
EnblSFD => enblSFD,
EnblData => enblData,
EnblJam => enblJam,
EnblCRC => enblCRC,
BusFifoWr => emac_tx_wr_i,
Phytx_en => tx_en_i,
TxCrcEn => txCrcEn,
TxCrcShftOutEn => txCrcShftOutEn,
Tx_addr_en => Tx_addr_en,
Tx_start => Tx_start,
Tx_done => Tx_done,
Tx_pong_ping_l => Tx_pong_ping_l,
Tx_idle => tx_idle_i,
Tx_DPM_ce => Tx_DPM_ce,
Tx_DPM_wr_data => Tx_DPM_wr_data,
Tx_DPM_wr_rd_n => Tx_DPM_wr_rd_n,
Enblclear => enblclear,
Transmit_start => Transmit_start,
Mac_program_start => Mac_program_start,
Mac_addr_ram_we => Mac_addr_ram_we,
Mac_addr_ram_addr_wr => Mac_addr_ram_addr_wr,
Pre_sfd_done => pre_sfd_done
);
----------------------------------------------------------------------------
-- deferral control
----------------------------------------------------------------------------
full_half_n <= '1'when C_DUPLEX = 1 else
'0';
INST_DEFERRAL_CONTROL: entity axi_ethernetlite_v3_0_9.deferral
port map
(
Clk => Clk,
Rst => Rst,
TxEn => tx_en_i,
TxRst => txChannelReset,
Tx_clk_en => TxClkEn,
BackingOff => backingOff_i,
Crs => Phy_crs,
Full_half_n => full_half_n,
Ifgp1 => "10000",
Ifgp2 => "01000",
Deferring => deferring
);
----------------------------------------------------------------------------
-- transmit bus fifo write nibble counter
----------------------------------------------------------------------------
INST_TXBUSFIFOWRITENIBBLECOUNT: entity axi_ethernetlite_v3_0_9.ld_arith_reg
generic map
(
C_ADD_SUB_NOT => true,
C_REG_WIDTH => 12,
C_RESET_VALUE => "000000000000",
C_LD_WIDTH => 12,
C_LD_OFFSET => 0,
C_AD_WIDTH => 12,
C_AD_OFFSET => 0
)
port map
(
CK => Clk,
Rst => txComboBusFifoWrCntRst,
Q => currentTxBusFifoWrCnt,
LD => "000000000000",
AD => "000000000001",
LOAD => '0',
OP => txComboBusFifoWrCntEn
);
txComboBusFifoWrCntRst <= Rst or txBusFifoWrCntRst
or txRetryRst;
txComboBusFifoWrCntEn <= txBusFifoWrCntEn and emac_tx_wr_i;
----------------------------------------------------------------------------
-- crc down counter
----------------------------------------------------------------------------
phy_tx_en_n <= not(tx_en_i); -- modified to have this in lite clock domain
INST_CRCCOUNTER: entity axi_ethernetlite_v3_0_9.ld_arith_reg
generic map
(
C_ADD_SUB_NOT => false,
C_REG_WIDTH => 4,
C_RESET_VALUE => "1000",
C_LD_WIDTH => 4,
C_LD_OFFSET => 0,
C_AD_WIDTH => 4,
C_AD_OFFSET => 0
)
port map
(
CK => Clk,
Rst => Rst,
Q => crcCnt,
LD => "1000",
AD => "0001",
LOAD => phy_tx_en_n,
OP => enblCRC
);
----------------------------------------------------------------------------
-- Full Duplex mode operation
----------------------------------------------------------------------------
TX3_NOT_GENERATE: if(C_DUPLEX = 1) generate --Set outputs to zero
begin
collisionRetryCnt <= (others=> '0');
colWindowNibbleCnt <= (others=> '0');
jamTxNibbleCnt <= (others=> '0');
backingOff_i <= '0';
end generate TX3_NOT_GENERATE;
----------------------------------------------------------------------------
-- Half Duplex mode operation
----------------------------------------------------------------------------
tx3_generate: if(C_DUPLEX = 0) generate --Include collision cnts when 1
----------------------------------------------------------------------------
-- transmit collision retry down counter
----------------------------------------------------------------------------
INST_COLRETRYCNT: entity axi_ethernetlite_v3_0_9.msh_cnt
generic map
(
C_ADD_SUB_NOT => true,
C_REG_WIDTH => 5,
C_RESET_VALUE => "00000"
)
port map
(
Clk => Clk,
Rst => txComboColRetryCntRst,
Q => collisionRetryCnt,
Z => open,
LD => "00000",
AD => "00001",
LOAD => '0',
OP => txColRetryCntEnbl
);
txComboColRetryCntRst_n <= not(Rst) and txColRetryCntRst_n;
txComboColRetryCntRst <= not txComboColRetryCntRst_n;
----------------------------------------------------------------------------
-- transmit collision window nibble down counter
----------------------------------------------------------------------------
INST_COLWINDOWNIBCNT: entity axi_ethernetlite_v3_0_9.msh_cnt
generic map
(
C_ADD_SUB_NOT => false,
C_REG_WIDTH => 8,
C_RESET_VALUE => "10001111"
)
port map
(
Clk => Clk,
Rst => phy_tx_en_i_n,
Q => colWindowNibbleCnt,
Z => open,
LD => "10001111",
AD => "00000001",
LOAD => '0',
OP => txCntEnbl
);
phy_tx_en_i_n <= not(axi_phy_tx_en_i_p);
----------------------------------------------------------------------------
-- jam transmit nibble down counter
----------------------------------------------------------------------------
INST_JAMTXNIBCNT: entity axi_ethernetlite_v3_0_9.msh_cnt
generic map
(
C_ADD_SUB_NOT => false,
C_REG_WIDTH => 4,
C_RESET_VALUE => "1001"
)
port map
(
Clk => Clk,
Rst => phy_tx_en_i_n,
Q => jamTxNibbleCnt,
Z => open,
LD => "1001",
AD => "0001",
LOAD => '0',
OP => jamTxComboNibCntEnbl
);
----------------------------------------------------------------------------
-- tx collision back off counter
----------------------------------------------------------------------------
INST_BOCNT: entity axi_ethernetlite_v3_0_9.bocntr
port map
(
Clk => Clk,
Clken => TxClkEn,
Rst => Rst,
InitBackoff => initBackoff,
RetryCnt => collisionRetryCnt,
BackingOff => backingOff_i
);
end generate tx3_generate;
----------------------------------------------------------------------------
-- CDC module for syncing tx_en_i in PHY_tx_clk domain
----------------------------------------------------------------------------
CDC_TX_EN: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 2
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => tx_en_i,
prmry_ack => open,
scndry_out => tx_en_i_tx_clk,
scndry_aclk => Phy_tx_clk,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
--- ----------------------------------------------------------------------------
--- -- CDC module for syncing phy_tx_en_i in Clk domain
--- ----------------------------------------------------------------------------
--- CDC_PHY_TX_EN: entity lib_cdc_v1_0_2.cdc_sync
--- generic map (
--- C_CDC_TYPE => 1,
--- C_RESET_STATE => 0,
--- C_SINGLE_BIT => 1,
--- C_FLOP_INPUT => 0,
--- C_VECTOR_WIDTH => 1,
--- C_MTBF_STAGES => 4
--- )
--- port map(
--- prmry_aclk => '1',
--- prmry_resetn => '1',
--- prmry_in => phy_tx_en_i_p,
--- prmry_ack => open,
--- scndry_out => phy_tx_en_i,
--- scndry_aclk => Clk,
--- scndry_resetn => '1',
--- prmry_vect_in => (OTHERS => '0'),
--- scndry_vect_out => open
--- );
--- ----------------------------------------------------------------------------
-- CDC module for syncing rst in tx_clk domain
----------------------------------------------------------------------------
CDC_PHY_TX_RST: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 2
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => Rst,
prmry_ack => open,
scndry_out => tx_d_rst,
scndry_aclk => Phy_tx_clk,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
----------------------------------------------------------------------------
-- INT_tx_en_PROCESS
----------------------------------------------------------------------------
-- This process assigns the outputs the phy enable
----------------------------------------------------------------------------
INT_TX_EN_PROCESS: process (Phy_tx_clk)
begin --
if (Phy_tx_clk'event and Phy_tx_clk = '1') then
if (tx_d_rst = RESET_ACTIVE) then
phy_tx_en_i_p <= '0';
fifo_tx_en <= '0';
else
fifo_tx_en <= tx_en_i_tx_clk; -- having cdc sync for tx_en_i for MTBF
phy_tx_en_i_p <= fifo_tx_en and tx_en_i_tx_clk;
-- fifo_tx_en <= tx_en_i;
-- phy_tx_en_i <= fifo_tx_en and tx_en_i;
end if;
end if;
end process INT_TX_EN_PROCESS;
AXI_INT_TX_EN_PROCESS: process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
axi_fifo_tx_en <= '0';
axi_phy_tx_en_i_p <= '0';
else
axi_fifo_tx_en <= tx_en_i;
axi_phy_tx_en_i_p <= axi_fifo_tx_en and tx_en_i;
end if;
end if;
end process AXI_INT_TX_EN_PROCESS;
emac_tx_wr_mod <= emac_tx_wr_i or enblclear;
tx_en_mod <= '0' when enblclear = '1' else
tx_en_i;
txChannelReset <= Rst;
txCntEnbl <= TxClkEn and axi_phy_tx_en_i_p and
not(not(full_half_n) and Phy_col);
----------------------------------------------------------------------------
-- jam transmit nibble down counter enable
----------------------------------------------------------------------------
jamTxComboNibCntEnbl <= (Phy_col or not(jamTxNibbleCnt(0) and
not(jamTxNibbleCnt(1)) and
not(jamTxNibbleCnt(2)) and
jamTxNibbleCnt(3))) and
pre_sfd_done and TxClkEn and not(full_half_n);
----------------------------------------------------------------------------
-- INT_CRC_DATA_REG_PROCESS
----------------------------------------------------------------------------
-- This process registers the emac data going to CRCgen Module to break long
-- timing path.
----------------------------------------------------------------------------
INT_CRC_DATA_REG_PROCESS: process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
emac_tx_wr_data_d1 <= (others=>'0');
emac_tx_wr_d1 <= '0';
txcrcen_d1 <= '0';
else
emac_tx_wr_data_d1 <= emac_tx_wr_data_i;
emac_tx_wr_d1 <= emac_tx_wr_i;
txcrcen_d1 <= txCrcEn;
end if;
end if;
end process INT_CRC_DATA_REG_PROCESS;
end imp;
-------------------------------------------------------------------------------
-- receive - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : receive.vhd
-- Version : v2.0
-- Description : This is the receive path portion of the design
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0_9 library is used for axi_ethernetlite_v3_0_9
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0_9;
use axi_ethernetlite_v3_0_9.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
library unisim;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-- C_FAMILY -- Target device family
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Phy_rx_clk -- Ethernet receive clock
-- Phy_dv -- Ethernet receive enable
-- Phy_rx_data -- Ethernet receive data
-- Phy_rx_col -- Ethernet collision indicator
-- Phy_rx_er -- Ethernet receive error
-- Rx_addr_en -- RX buufer address enable
-- Rx_start -- Receive start
-- Rx_done -- Receive complete
-- Rx_pong_ping_l -- RX Ping/Pong buffer enable
-- Rx_DPM_ce -- RX buffer chip enable
-- Rx_DPM_wr_data -- RX buffer write data
-- Rx_DPM_rd_data -- RX buffer read data
-- Rx_DPM_wr_rd_n -- RX buffer write read enable
-- Rx_idle -- RX idle
-- Mac_addr_ram_addr_rd -- MAC Addr RAM read address
-- Mac_addr_ram_data -- MAC Addr RAM read data
-- Rx_buffer_ready -- RX buffer ready to accept new packet
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity receive is
generic
(
C_DUPLEX : integer := 1;
-- 1 = full duplex, 0 = half duplex
C_FAMILY : string := "virtex6"
);
port
(
Clk : in std_logic;
Rst : in std_logic;
Phy_rx_clk : in std_logic;
Phy_dv : in std_logic;
Phy_rx_data : in std_logic_vector (0 to 3);
Phy_rx_col : in std_logic;
Phy_rx_er : in std_logic;
Rx_addr_en : out std_logic;
Rx_start : out std_logic;
Rx_done : out std_logic;
Rx_pong_ping_l : in std_logic;
Rx_DPM_ce : out std_logic;
Rx_DPM_wr_data : out std_logic_vector (0 to 3);
Rx_DPM_rd_data : in std_logic_vector (0 to 3);
Rx_DPM_wr_rd_n : out std_logic;
Rx_idle : out std_logic;
Mac_addr_ram_addr_rd : out std_logic_vector(0 to 3);
Mac_addr_ram_data : in std_logic_vector (0 to 3);
Rx_buffer_ready : in std_logic
);
end receive;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of receive is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal fifo_empty_i : std_logic;
signal fifo_full_i : std_logic;
signal emac_rx_rd_i : std_logic;
signal emac_rx_rd_data_i : std_logic_vector(0 to 5);
signal emac_rx_rd_data_d1 : std_logic_vector(0 to 5); -- 03-26-04
signal rxAbortRst : std_logic;
signal rxChannelReset : std_logic;
signal rxBusFifoRdAck : std_logic;
signal rxComboCrcRst : std_logic;
signal rxComboCrcEn : std_logic;
signal crcOk_i : std_logic;
signal rxCrcRst : std_logic;
signal rxCrcEn : std_logic;
signal rxCrcEn_d1 : std_logic; -- 03-26-04
signal receive_enable : std_logic; -- 03-26-04
signal fifo_reset : std_logic; -- 03-26-04
begin
----------------------------------------------------------------------------
-- rx control state machine
----------------------------------------------------------------------------
INST_RX_STATE: entity axi_ethernetlite_v3_0_9.rx_statemachine
generic map (
C_DUPLEX => C_DUPLEX
)
port map (
Clk => Clk,
Rst => rxChannelReset,
Emac_rx_rd_data_d1 => emac_rx_rd_data_d1, -- 03-26-04
Receive_enable => receive_enable, -- 03-26-04
RxBusFifoRdAck => rxBusFifoRdAck,
BusFifoEmpty => fifo_empty_i,
Collision => Phy_rx_col,
DataValid => emac_rx_rd_data_i(4),
RxError => emac_rx_rd_data_i(5),
BusFifoData => emac_rx_rd_data_i(0 to 3),
CrcOk => crcOk_i,
BusFifoRd => emac_rx_rd_i,
RxAbortRst => rxAbortRst,
RxCrcRst => rxCrcRst,
RxCrcEn => rxCrcEn,
Rx_addr_en => Rx_addr_en,
Rx_start => Rx_start,
Rx_done => Rx_done,
Rx_pong_ping_l => Rx_pong_ping_l,
Rx_DPM_ce => Rx_DPM_ce,
Rx_DPM_wr_data => Rx_DPM_wr_data,
Rx_DPM_rd_data => Rx_DPM_rd_data,
Rx_DPM_wr_rd_n => Rx_DPM_wr_rd_n,
Rx_idle => Rx_idle,
Mac_addr_ram_addr_rd => Mac_addr_ram_addr_rd,
Mac_addr_ram_data => Mac_addr_ram_data,
Rx_buffer_ready => Rx_buffer_ready
);
rxChannelReset <= Rst;
----------------------------------------------------------------------------
-- rx interface contains the ethernet rx fifo
----------------------------------------------------------------------------
INST_RX_INTRFCE: entity axi_ethernetlite_v3_0_9.rx_intrfce
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Rst => fifo_reset,
Phy_rx_clk => Phy_rx_clk,
InternalWrapEn => '0',
Phy_rx_er => Phy_rx_er,
Phy_dv => Phy_dv,
Phy_rx_data => Phy_rx_data,
Rcv_en => receive_enable,
Fifo_empty => fifo_empty_i,
Fifo_full => fifo_full_i,
Emac_rx_rd => emac_rx_rd_i,
Emac_rx_rd_data => emac_rx_rd_data_i,
RdAck => rxBusFifoRdAck
);
--fifo_reset <= Rst or not(receive_enable); -- 03-26-04
fifo_reset <= Rst; -- removing cross clock passing of signal(receive_enable is genrated in lite_clock domain and going to fifo working in rx_clk domain)
----------------------------------------------------------------------------
-- crc checker
----------------------------------------------------------------------------
INST_CRCGENRX: entity axi_ethernetlite_v3_0_9.crcgenrx
port map(
Clk => Clk,
Rst => rxComboCrcRst,
Data => emac_rx_rd_data_i(0 to 3),
DataEn => rxComboCrcEn,
CrcOk => crcOk_i);
rxComboCrcRst <= Rst or rxCrcRst or rxAbortRst;
rxComboCrcEn <= rxCrcEn_d1;
----------------------------------------------------------------------------
-- REG_PROCESS
----------------------------------------------------------------------------
-- This process registers the received read data and receive CRC enable.
----------------------------------------------------------------------------
REG_PROCESS : process (Clk)
begin --
if (Clk'event and Clk = '1') then -- rising clock edge
if (Rst = '1') then
emac_rx_rd_data_d1 <= "000000";
rxCrcEn_d1 <= '0';
else
emac_rx_rd_data_d1 <= emac_rx_rd_data_i;
rxCrcEn_d1 <= rxCrcEn;
end if;
end if;
end process REG_PROCESS;
end imp;
-------------------------------------------------------------------------------
-- MacAddrRAM - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : macaddram.vhd
-- Version : v2.0
-- Description : Design file for the Ethernet Lite MAC.
-- There is a rom used in the MII to store the MAC address
--
-- Note that the two nibbles in each word of the MAC address
-- are transposed in order to transmit to the network in the
-- proper order.However, the generic value (MACAddr)of this
-- ROM keeps the normal order.
--
-- Representation of each word in this ROM (list with address order)
--
-- Addr (3 downto 0) : netOrder(MACAddr(47 downto 32)) e.g.: 0xafec
-- Addr (7 downto 4) : netOrder(MACAddr(31 downto 16)) e.g.: 0xedfa
-- Addr (11 downto 8) : netOrder(MACAddr(15 downto 0)) e.g.: 0xacef
-- Addr (15 downto 12) : netOrder(Filler) e.g.: 0x0000
--
-- Uses 4 LUTs (4 rom16x1), 0 register
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0_9 library is used for axi_ethernetlite_v3_0_9
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0_9;
use axi_ethernetlite_v3_0_9.mac_pkg.all;
-------------------------------------------------------------------------------
-- synopsys translate_off
-- Library XilinxCoreLib;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
--
-- MACAddr -- MAC Address
-- Filler -- Filler
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Addr -- Address
-- Dout -- Data output
-- Din -- Data input
-- We -- Write Enable
-- Clk -- Clock
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity MacAddrRAM is
generic
(MACAddr : bit_vector(47 downto 0) := x"ffffffffffaa";
-- use the normal order
Filler : bit_vector(15 downto 0) := x"0000");
port(
Addr : in std_logic_vector (3 downto 0);
Dout : out std_logic_vector (3 downto 0);
Din : in std_logic_vector (3 downto 0);
We : in std_logic;
Clk : in std_logic
);
end MacAddrRAM;
architecture imp of MacAddrRAM is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Constants used in this design are found in mac_pkg.vhd
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- The following components are the building blocks of the EMAC
--component ram16x4
-- generic(
-- INIT_00 : bit_vector(15 downto 0) :=x"0000";-- for Addr(3 downto 0)
-- INIT_01 : bit_vector(15 downto 0) :=x"0000";-- for Addr(7 downto 4)
-- INIT_02 : bit_vector(15 downto 0) :=x"0000";-- for Addr(11 downto 8)
-- INIT_03 : bit_vector(15 downto 0) :=x"0000" -- for Addr(15 downto 12)
-- );
-- port(
-- Addr : in std_logic_vector(3 downto 0);
-- D : in std_logic_vector(3 downto 0);
-- We : in std_logic;
-- Clk : in std_logic;
-- Q : out std_logic_vector(3 downto 0));
--end component;
begin
ram16x4i: entity axi_ethernetlite_v3_0_9.ram16x4
generic map
(INIT_00 => netOrder(MACAddr(47 downto 32)),
INIT_01 => netOrder(MACAddr(31 downto 16)),
INIT_02 => netOrder(MACAddr(15 downto 0)),
INIT_03 => netOrder(Filler)
)
port map
(Addr => Addr,
D => Din,
Q => Dout,
We => We,
Clk => Clk
);
end imp;
-------------------------------------------------------------------------------
-- mdio_if.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : mdio_if.vhd
-- Version : v2.0
-- Description : This entity provides the interface between the physical layer
-- management control, and the host interface through the MAC.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
library axi_ethernetlite_v3_0_9;
use axi_ethernetlite_v3_0_9.all;
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- MDIO_Clk -- 2.5Mhz clock
-- MDIO_en -- MDIO enable
-- MDIO_OP -- MDIO OP code
-- MDIO_Req -- MDIO transmission request
-- MDIO_PHY_AD -- The physical layer address
-- MDIO_REG_AD -- The individual register address
-- MDIO_WR_DATA -- The data to be written on MDIO
-- MDIO_RD_DATA -- The data read from MDIO
-- PHY_MDIO_I -- MDIO Tri-state input from PHY
-- PHY_MDIO_O -- MDIO Tri-state output to PHY
-- PHY_MDIO_T -- MDIO Tri-state control
-- PHY_MDC -- 2.5Mhz communication clock to PHY
-- MDIO_done -- RX FIFO read ack
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity mdio_if is
port (
Clk : in std_logic; -- System Clock
Rst : in std_logic; -- System Reset
MDIO_Clk : in std_logic; -- 2.5Mhz clock
MDIO_en : in std_logic; -- MDIO enable
MDIO_OP : in std_logic; -- MDIO OP code
MDIO_Req : in std_logic; -- MDIO transmission request
MDIO_PHY_AD : in std_logic_vector(4 downto 0);
-- The physical layer address
MDIO_REG_AD : in std_logic_vector(4 downto 0);
-- The individual register address
MDIO_WR_DATA : in std_logic_vector(15 downto 0);
-- The data to be written on MDIO
MDIO_RD_DATA : out std_logic_vector(15 downto 0);
-- The data read from MDIO
PHY_MDIO_I : in std_logic; -- MDIO Tri-state input from PHY
PHY_MDIO_O : out std_logic; -- MDIO Tri-state output to PHY
PHY_MDIO_T : out std_logic; -- MDIO Tri-state control
PHY_MDC : out std_logic; -- 2.5Mhz communication clock
MDIO_done : out std_logic -- MDIO tranfer done indicator
);
end mdio_if;
architecture imp of mdio_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
type mdio_state_type is (IDLE, PREAMBLE, ST1, ST2, OP1, OP2, TA1, TA2,
PHY_ADDR, REG_ADDR, WRITE, READ, DONE);
signal mdio_state, next_state : mdio_state_type;
signal mdio_xfer_done : std_logic; -- pulse to inidcate end of activity
signal mdio_idle : std_logic; -- internal READY signal
signal rd_data_en : std_logic_vector(15 downto 0); -- decoded write
-- MDIO_en for RD_DATA
signal mdio_en_reg : std_logic; -- MDIO_en signal latched at start of
-- transmission
signal mdio_o_cmb : std_logic; -- rising edge version of MDIO_OUT
signal mdio_t_comb : std_logic; -- combinatorial term to produce
-- MDIO_TRISTATE
signal mdio_clk_reg : std_logic; -- registering MDIO_Clk to use it as a
-- clock MDIO_en
signal mdio_in_reg1 : std_logic; -- compensate in pipeline delay caused
-- by using MDC as a clock MDIO_en
signal mdio_in_reg2 : std_logic; -- compensate in pipeline delay caused by
-- using MDC as a clock MDIO_en
signal clk_cnt : integer range 0 to 32; -- Clk counter
signal ld_cnt_data_cmb : integer range 0 to 32; -- Counter load comb
signal ld_cnt_data_reg : integer range 0 to 32; -- Counter load reg
signal ld_cnt_en_cmb : std_logic; -- Counter load enable
signal clk_cnt_en : std_logic; -- Counter enable
signal mdc_falling : std_logic; -- MDC falling edge
signal mdc_rising : std_logic; -- MDC rising edge
signal ld_cnt_en_reg : std_logic; -- Counter load enable reg
begin
----------------------------------------------------------------------------
-- PROCESS : INPUT_REG_CLK
----------------------------------------------------------------------------
-- Registering PHY_MDIO_I and MDC signals w.r.t SAXI clock.
----------------------------------------------------------------------------
INPUT_REG_CLK: process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_clk_reg <= '0';
mdio_in_reg1 <= '0';
mdio_in_reg2 <= '0';
else
mdio_clk_reg <= MDIO_Clk;
mdio_in_reg1 <= PHY_MDIO_I;
mdio_in_reg2 <= mdio_in_reg1;
end if;
end if;
end process INPUT_REG_CLK;
-- Falling edge and rising edge generation of MDC clock
mdc_falling <= not MDIO_Clk and mdio_clk_reg;
mdc_rising <= MDIO_Clk and not mdio_clk_reg;
-- Enable MDC only when MDIO interface is enabled.
PHY_MDC <= MDIO_Clk; -- making the MDC clk contineous
--PHY_MDC <= MDIO_Clk and mdio_en_reg;
-- Informs MDIO interface about the MDIO transfer complete.
MDIO_done <= mdio_xfer_done;
----------------------------------------------------------------------------
-- PROCESS : REG_MDIO_en
----------------------------------------------------------------------------
-- Latch MDIO_en bit on falling edge of MDC and when MDIO master is IDLE.
-- MDIO Master will complete the existing transfer even if MDIO interface
-- is disable in middle of the transaction.
----------------------------------------------------------------------------
REG_MDIO_en : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_en_reg <= '0';
elsif mdc_falling='1' then
if mdio_idle = '1' then
mdio_en_reg <= MDIO_en;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : PHY_MDIO_T_REG
----------------------------------------------------------------------------
-- The mdio_t_comb signal is driven high only for read operation starting
-- from the Turn arround state.
-- It is driven on falling clock edge to match up with PHY_MDIO_O
----------------------------------------------------------------------------
PHY_MDIO_T_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
PHY_MDIO_T <= '1';
elsif (mdc_falling='1') then -- falling edge of MDC
PHY_MDIO_T <= mdio_t_comb;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : PHY_MDIO_O_REG
----------------------------------------------------------------------------
-- Generating PHY_MDIO_O output singnal on falling edge of MDC
----------------------------------------------------------------------------
PHY_MDIO_O_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
PHY_MDIO_O <= '0';
elsif (mdc_falling='1') then -- falling edge of MDC
PHY_MDIO_O <= mdio_o_cmb;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : MDIO_IDLE_REG
----------------------------------------------------------------------------
-- The mdio_idle signal is used to indicate no activity on the MDIO.
-- Set at reset amd at the end of transmission.
-- Rst at start of transmission as long as device is MDIO_end
----------------------------------------------------------------------------
MDIO_IDLE_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_idle <= '1';
elsif (mdc_rising='1') then -- rising edge of MDC
if (mdio_xfer_done = '1') then
mdio_idle <= '1';
elsif (MDIO_Req = '1' and mdio_en_reg = '1') then
mdio_idle <= '0';
end if;
end if;
end if;
end process ;
----------------------------------------------------------------------------
-- PROCESS : MDIO_CAPTURE_DATA
----------------------------------------------------------------------------
-- This process captures registered PHY_MDIO_i input on rising edge of the
-- MDC clock. The rd_data_en signal is generated in MDIO State machine for
-- respective captured bit.
----------------------------------------------------------------------------
MDIO_CAPTURE_DATA : for i in 15 downto 0 generate
MDIO_DATA_IN : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1') then
MDIO_RD_DATA(i) <= '0';
elsif (mdc_rising='1') then -- rising edge of MDC
if(rd_data_en(i) = '1') then
MDIO_RD_DATA(i) <= mdio_in_reg2;
end if;
end if;
end if;
end process MDIO_DATA_IN;
end generate;
----------------------------------------------------------------------------
-- PROCESS : MDIO_DOWN_COUNTER
----------------------------------------------------------------------------
-- This counter is used in Preamble and PHY_ADDR and REG_ADDR state.
-- This counter is loaded for the required values for each above states.
----------------------------------------------------------------------------
MDIO_DOWN_COUNTER : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1' ) then
clk_cnt <= 0;
elsif (mdc_rising='1') then -- falling edge of MDC
if (ld_cnt_en_reg = '1') then -- Load counter with load data
clk_cnt <= ld_cnt_data_reg;
elsif (clk_cnt_en='1') then -- Enable Down Counter
clk_cnt <= clk_cnt - 1;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : MDIO_NEXT_STATE_GEN
----------------------------------------------------------------------------
-- MDIO next state register process
----------------------------------------------------------------------------
MDIO_NEXT_STATE_GEN : process (Clk)
begin
if Clk'event and Clk = '1' then
if (Rst = '1') then
mdio_state <= IDLE;
elsif (mdc_rising='1') then
mdio_state <= next_state;
end if;
end if;
end process MDIO_NEXT_STATE_GEN;
----------------------------------------------------------------------------
-- PROCESS : MDIO_COMB_REG_GEN
----------------------------------------------------------------------------
-- Combinational signal register process
----------------------------------------------------------------------------
MDIO_COMB_REG_GEN : process (Clk)
begin
if Clk'event and Clk = '1' then
if (Rst = '1') then
ld_cnt_data_reg <= 0;
ld_cnt_en_reg <= '0';
else
ld_cnt_data_reg <= ld_cnt_data_cmb;
ld_cnt_en_reg <= ld_cnt_en_cmb;
end if;
end if;
end process MDIO_COMB_REG_GEN;
----------------------------------------------------------------------------
-- PROCESS : MDIO_STATE_COMB
----------------------------------------------------------------------------
-- This process generates mdio_o_cmb signal in command and Write phase as
-- per the required MDIO protocol. This process also generate mdio_t_comb
-- tristate signal and rd_data_en to capture the respective bit in Read
-- operation.
----------------------------------------------------------------------------
MDIO_STATE_COMB : process (mdio_state, mdio_idle, clk_cnt, MDIO_OP,
MDIO_PHY_AD, MDIO_REG_AD, MDIO_WR_DATA)
begin
-- state machine defaults
mdio_o_cmb <= '1';
rd_data_en <= "0000000000000000";
mdio_xfer_done <= '0';
ld_cnt_en_cmb <= '0';
clk_cnt_en <= '0';
mdio_t_comb <= '0';
next_state <= mdio_state;
ld_cnt_data_cmb <= 0;
case mdio_state is
when IDLE =>
mdio_o_cmb <= '1';
mdio_t_comb <= '1';
ld_cnt_en_cmb <= '1';
-- leave IDLE state when new mdio request is received.
if mdio_idle = '0' then
-- Load counter for 32-bit preamble
ld_cnt_data_cmb <= 31;
next_state <= PREAMBLE;
end if;
when PREAMBLE =>
clk_cnt_en <= '1';
-- Move to ST1 after 32-bit preamble.
if clk_cnt = 0 then
next_state <= ST1;
clk_cnt_en <= '0';
end if;
when ST1 => -- Start Code-1
mdio_o_cmb <= '0';
next_state <= ST2;
when ST2 => -- Start Code-2
mdio_o_cmb <= '1';
next_state <= OP1;
when OP1 => -- Opcode-1
next_state <= OP2;
if MDIO_OP='1' then
mdio_o_cmb <= '1';
else
mdio_o_cmb <= '0';
end if;
when OP2 => -- Opcode-2
next_state <= PHY_ADDR;
-- Load counter for 5-bit PHYaddress transfer
ld_cnt_data_cmb <= 4;
ld_cnt_en_cmb <= '1';
if MDIO_OP='1' then
mdio_o_cmb <= '0';
else
mdio_o_cmb <= '1';
end if;
when PHY_ADDR => -- PHY Device Address
clk_cnt_en <= '1';
mdio_o_cmb <= MDIO_PHY_AD(clk_cnt);
-- Send 5-bit PHY device address
if clk_cnt=0 then
next_state <= REG_ADDR;
-- Load counter for 5-bit REG address transfer
ld_cnt_data_cmb <= 4;
ld_cnt_en_cmb <= '1';
end if;
when REG_ADDR => -- PHY Device Address
clk_cnt_en <= '1';
mdio_o_cmb <= MDIO_REG_AD(clk_cnt);
-- Send 5-bit PHY Register address
if clk_cnt=0 then
next_state <= TA1;
clk_cnt_en <= '0';
end if;
when TA1 => -- Turn Around Time-1
mdio_o_cmb <= '1';
next_state <= TA2;
-- For Read operation generate high impedence on
-- MDIO bus
if MDIO_OP='1' then
mdio_t_comb <= '1';
else
mdio_t_comb <= '0';
end if;
when TA2 => -- Turn Around Time-2
mdio_o_cmb <= '0';
-- Load the down counter for 16 bit data transfer
ld_cnt_data_cmb <= 15;
ld_cnt_en_cmb <= '1';
-- Move to Write state if opcode is '0'
if MDIO_OP='0' then
next_state <= WRITE;
mdio_t_comb <= '0';
else
next_state <= READ;
mdio_t_comb <= '1';
end if;
when WRITE => -- MDIO DATA Write
clk_cnt_en <= '1';
-- Send 16-bit Write Data on the MDIO data line
mdio_o_cmb <= MDIO_WR_DATA(clk_cnt);
-- Wait for 16 bit transfer
if clk_cnt=0 then
next_state <= DONE;
clk_cnt_en <= '0';
end if;
when READ => -- MDIO DATA Read
clk_cnt_en <= '1';
mdio_t_comb <= '1';
-- Generate read data enable for respective bit
rd_data_en(clk_cnt) <= '1';
-- Wait for 16 bit transfer
if clk_cnt=0 then
next_state <= DONE;
clk_cnt_en <= '0';
end if;
when DONE => -- MDIO Transfer Done
mdio_o_cmb <= '1';
mdio_t_comb <= '1';
next_state <= IDLE;
-- Mdio trasnfer complete
mdio_xfer_done <= '1';
-- coverage off
when others =>
next_state <= IDLE;
-- coverage on
end case;
end process MDIO_STATE_COMB;
end imp;
-------------------------------------------------------------------------------
-- emac_dpram.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : emac_dpram.vhd
-- Version : v2.0
-- Description : Realization of dprams
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0_9 library is used for axi_ethernetlite_v3_0_9
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0_9;
use axi_ethernetlite_v3_0_9.mac_pkg.all;
-------------------------------------------------------------------------------
library lib_bmg_v1_0_7;
use lib_bmg_v1_0_7.all;
library xpm;
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all; -- uses BRAM primitives
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_FAMILY -- Target device family
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Ce_a -- Port A enable
-- Wr_rd_n_a -- Port A write/read enable
-- Adr_a -- Port A address
-- Data_in_a -- Port A data in
-- Data_out_a -- Port A data out
-- Ce_b -- Port B enable
-- Wr_rd_n_b -- Port B write/read enable
-- Adr_b -- Port B address
-- Data_in_b -- Port B data in
-- Data_out_b -- Port B data out
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity emac_dpram is
generic
(
C_FAMILY : string := "virtex6";
C_SELECT_XPM : integer := 1
);
port
(
Clk : in std_logic;
Rst : in std_logic;
-- a Port signals
Ce_a : in std_logic;
Wr_rd_n_a : in std_logic;
Adr_a : in std_logic_vector(11 downto 0);
Data_in_a : in std_logic_vector(3 downto 0);
Data_out_a : out std_logic_vector(3 downto 0);
-- b Port Signals
Ce_b : in std_logic;
Wr_rd_n_b : in std_logic;
Adr_b : in std_logic_vector(8 downto 0);
Data_in_b : in std_logic_vector(31 downto 0);
Data_out_b : out std_logic_vector(31 downto 0)
);
end entity emac_dpram;
architecture imp of emac_dpram is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- component RAMB16_S4_S36
---- pragma translate_off
-- generic
-- (
-- WRITE_MODE_A : string := "READ_FIRST";
-- --WRITE_FIRST(default)/ READ_FIRST/ NO_CHANGE
-- WRITE_MODE_B : string := "READ_FIRST"
-- --WRITE_FIRST(default)/ READ_FIRST/ NO_CHANGE
-- );
---- pragma translate_on
-- port (
-- DOA : out std_logic_vector (3 downto 0);
-- DOB : out std_logic_vector (31 downto 0);
-- DOPB : out std_logic_vector (3 downto 0);
-- ADDRA : in std_logic_vector (11 downto 0);
-- CLKA : in std_logic;
-- DIA : in std_logic_vector (3 downto 0);
-- ENA : in std_logic;
-- SSRA : in std_logic;
-- WEA : in std_logic;
-- ADDRB : in std_logic_vector (8 downto 0);
-- CLKB : in std_logic;
-- DIB : in std_logic_vector (31 downto 0);
-- DIPB : in std_logic_vector (3 downto 0);
-- ENB : in std_logic;
-- SSRB : in std_logic;
-- WEB : in std_logic
-- );
-- end component;
--constant create_v2_mem : boolean := supported(C_FAMILY, u_RAMB16_S4_S36);
component xpm_memory_tdpram
generic (
MEMORY_SIZE : integer := 4096*32;
MEMORY_PRIMITIVE : string := "blockram";
CLOCKING_MODE : string := "common_clock";
ECC_MODE : string := "no_ecc";
MEMORY_INIT_FILE : string := "none";
WAKEUP_TIME : string := "disable_sleep";
MESSAGE_CONTROL : integer := 0;
WRITE_DATA_WIDTH_A : integer := 32;
READ_DATA_WIDTH_A : integer := 32;
BYTE_WRITE_WIDTH_A : integer := 8;
ADDR_WIDTH_A : integer := 12;
READ_RESET_VALUE_A : string := "0";
READ_LATENCY_A : integer := 1;
WRITE_MODE_A : string := "read_first";
WRITE_DATA_WIDTH_B : integer := 32;
READ_DATA_WIDTH_B : integer := 32;
BYTE_WRITE_WIDTH_B : integer := 8;
ADDR_WIDTH_B : integer := 12;
READ_RESET_VALUE_B : string := "0";
READ_LATENCY_B : integer := 1;
WRITE_MODE_B : string := "read_first"
);
port (
-- Common module ports
sleep : in std_logic;
-- Port A module ports
clka : in std_logic;
rsta : in std_logic;
ena : in std_logic;
regcea : in std_logic;
wea : in std_logic_vector (0 downto 0); -- (WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A)-1:0]
addra : in std_logic_vector (11 downto 0); -- [ADDR_WIDTH_A-1:0]
dina : in std_logic_vector (3 downto 0); -- [WRITE_DATA_WIDTH_A-1:0]
injectsbiterra : in std_logic;
injectdbiterra : in std_logic;
douta : out std_logic_vector; -- [READ_DATA_WIDTH_A-1:0]
sbiterra : out std_logic;
dbiterra : out std_logic;
-- Port B module ports
clkb : in std_logic;
rstb : in std_logic;
enb : in std_logic;
regceb : in std_logic;
web : in std_logic_vector (0 downto 0); -- (WRITE_DATA_WIDTH_B/BYTE_WRITE_WIDTH_B)-1:0]
addrb : in std_logic_vector (8 downto 0); -- [ADDR_WIDTH_B-1:0]
dinb : in std_logic_vector (31 downto 0); -- [WRITE_DATA_WIDTH_B-1:0]
injectsbiterrb : in std_logic;
injectdbiterrb : in std_logic;
doutb : out std_logic_vector; -- [READ_DATA_WIDTH_B-1:0]
sbiterrb : out std_logic;
dbiterrb : out std_logic
);
end component;
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal ce_a_i : std_logic;
signal ce_b_i : std_logic;
--signal wr_rd_n_a_i : std_logic;
signal wr_rd_n_a_i : std_logic_vector(0 downto 0);
--signal wr_rd_n_b_i : std_logic;
signal wr_rd_n_b_i : std_logic_vector(0 downto 0);
signal port_b_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal port_b_data_out : STD_LOGIC_VECTOR (31 downto 0);
--attribute WRITE_MODE_A : string;
--attribute WRITE_MODE_A of I_DPB16_4_9: label is "READ_FIRST";
--attribute WRITE_MODE_B : string;
--attribute WRITE_MODE_B of I_DPB16_4_9: label is "READ_FIRST";
begin -- architecture
ce_a_i <= Ce_a or Rst;
ce_b_i <= Ce_b or Rst;
wr_rd_n_a_i(0) <= Wr_rd_n_a and not(Rst);
wr_rd_n_b_i(0) <= Wr_rd_n_b and not(Rst);
-------------------------------------------------------------------------------
-- Using VII 4096 x 4 : 2048 x 8 Dual Port Primitive
-------------------------------------------------------------------------------
-- port_b_data_in(31) <= Data_in_b(0);
-- port_b_data_in(30) <= Data_in_b(1);
-- port_b_data_in(29) <= Data_in_b(2);
-- port_b_data_in(28) <= Data_in_b(3);
-- port_b_data_in(27) <= Data_in_b(4);
-- port_b_data_in(26) <= Data_in_b(5);
-- port_b_data_in(25) <= Data_in_b(6);
-- port_b_data_in(24) <= Data_in_b(7);
-- port_b_data_in(23) <= Data_in_b(8);
-- port_b_data_in(22) <= Data_in_b(9);
-- port_b_data_in(21) <= Data_in_b(10);
-- port_b_data_in(20) <= Data_in_b(11);
-- port_b_data_in(19) <= Data_in_b(12);
-- port_b_data_in(18) <= Data_in_b(13);
-- port_b_data_in(17) <= Data_in_b(14);
-- port_b_data_in(16) <= Data_in_b(15);
-- port_b_data_in(15) <= Data_in_b(16);
-- port_b_data_in(14) <= Data_in_b(17);
-- port_b_data_in(13) <= Data_in_b(18);
-- port_b_data_in(12) <= Data_in_b(19);
-- port_b_data_in(11) <= Data_in_b(20);
-- port_b_data_in(10) <= Data_in_b(21);
-- port_b_data_in(9) <= Data_in_b(22);
-- port_b_data_in(8) <= Data_in_b(23);
-- port_b_data_in(7) <= Data_in_b(24);
-- port_b_data_in(6) <= Data_in_b(25);
-- port_b_data_in(5) <= Data_in_b(26);
-- port_b_data_in(4) <= Data_in_b(27);
-- port_b_data_in(3) <= Data_in_b(28);
-- port_b_data_in(2) <= Data_in_b(29);
-- port_b_data_in(1) <= Data_in_b(30);
-- port_b_data_in(0) <= Data_in_b(31);
--
-- Data_out_b(31) <= port_b_data_out(0);
-- Data_out_b(30) <= port_b_data_out(1);
-- Data_out_b(29) <= port_b_data_out(2);
-- Data_out_b(28) <= port_b_data_out(3);
-- Data_out_b(27) <= port_b_data_out(4);
-- Data_out_b(26) <= port_b_data_out(5);
-- Data_out_b(25) <= port_b_data_out(6);
-- Data_out_b(24) <= port_b_data_out(7);
-- Data_out_b(23) <= port_b_data_out(8);
-- Data_out_b(22) <= port_b_data_out(9);
-- Data_out_b(21) <= port_b_data_out(10);
-- Data_out_b(20) <= port_b_data_out(11);
-- Data_out_b(19) <= port_b_data_out(12);
-- Data_out_b(18) <= port_b_data_out(13);
-- Data_out_b(17) <= port_b_data_out(14);
-- Data_out_b(16) <= port_b_data_out(15);
-- Data_out_b(15) <= port_b_data_out(16);
-- Data_out_b(14) <= port_b_data_out(17);
-- Data_out_b(13) <= port_b_data_out(18);
-- Data_out_b(12) <= port_b_data_out(19);
-- Data_out_b(11) <= port_b_data_out(20);
-- Data_out_b(10) <= port_b_data_out(21);
-- Data_out_b(9) <= port_b_data_out(22);
-- Data_out_b(8) <= port_b_data_out(23);
-- Data_out_b(7) <= port_b_data_out(24);
-- Data_out_b(6) <= port_b_data_out(25);
-- Data_out_b(5) <= port_b_data_out(26);
-- Data_out_b(4) <= port_b_data_out(27);
-- Data_out_b(3) <= port_b_data_out(28);
-- Data_out_b(2) <= port_b_data_out(29);
-- Data_out_b(1) <= port_b_data_out(30);
-- Data_out_b(0) <= port_b_data_out(31);
--
--
-- I_DPB16_4_9: RAMB16_S4_S36
-- port map (
-- DOA => Data_out_a, --[out]
-- DOB => port_b_data_out, --[out]
-- DOPB => open, --[out]
-- ADDRA => Adr_a, --[in]
-- CLKA => Clk, --[in]
-- DIA => Data_in_a, --[in]
-- ENA => ce_a_i, --[in]
-- SSRA => Rst, --[in]
-- WEA => wr_rd_n_a_i, --[in]
-- ADDRB => Adr_b, --[in]
-- CLKB => Clk, --[in]
-- DIB => port_b_data_in, --[in]
-- DIPB => (others => '0'), --[in]
-- ENB => ce_b_i, --[in]
-- SSRB => Rst, --[in]
-- WEB => wr_rd_n_b_i --[in]
-- );
--
-- I_DPB16_4_9: RAMB16_S4_S36
-- port map (
-- DOA => Data_out_a, --[out]
-- DOB => Data_out_b, --[out]
-- DOPB => open, --[out]
-- ADDRA => Adr_a, --[in]
-- CLKA => Clk, --[in]
-- DIA => Data_in_a, --[in]
-- ENA => ce_a_i, --[in]
-- SSRA => Rst, --[in]
-- WEA => wr_rd_n_a_i, --[in]
-- ADDRB => Adr_b, --[in]
-- CLKB => Clk, --[in]
-- DIB => Data_in_b, --[in]
-- DIPB => (others => '0'), --[in]
-- ENB => ce_b_i, --[in]
-- SSRB => Rst, --[in]
-- WEB => wr_rd_n_b_i --[in]
-- );
xpm_mem_gen : if (C_SELECT_XPM = 1) generate
xpm_memory_inst: xpm_memory_tdpram
generic map (
MEMORY_SIZE => 4096*4,
MEMORY_PRIMITIVE => "blockram",
CLOCKING_MODE => "common_clock",
ECC_MODE => "no_ecc",
MEMORY_INIT_FILE => "none",
WAKEUP_TIME => "disable_sleep",
MESSAGE_CONTROL => 0,
WRITE_DATA_WIDTH_A => 4,
READ_DATA_WIDTH_A => 4,
BYTE_WRITE_WIDTH_A => 4,
ADDR_WIDTH_A => 12,
READ_RESET_VALUE_A => "0",
READ_LATENCY_A => 1,
WRITE_MODE_A => "read_first",
WRITE_DATA_WIDTH_B => 32,
READ_DATA_WIDTH_B => 32,
BYTE_WRITE_WIDTH_B => 32,
ADDR_WIDTH_B => 9,
READ_RESET_VALUE_B => "0",
READ_LATENCY_B => 1,
WRITE_MODE_B => "read_first"
)
port map (
-- Common module ports
sleep => '0',
-- Port A module ports
clka => Clk,
rsta => '0',
ena => ce_a_i,
regcea => '1',
wea => wr_rd_n_a_i,
addra => Adr_a,
dina => Data_in_a,
injectsbiterra => '0',
injectdbiterra => '0',
douta => Data_out_a,
sbiterra => open,
dbiterra => open,
-- Port B module ports
clkb => Clk,
rstb => '0',
enb => ce_b_i,
regceb => '1',
web => wr_rd_n_b_i,
addrb => Adr_b,
dinb => Data_in_b,
injectsbiterrb => '0',
injectdbiterrb => '0',
doutb => Data_out_b,
sbiterrb => open,
dbiterrb => open
);
end generate;
blk_mem_gen : if (C_SELECT_XPM = 0) generate
dpram_blkmem: entity lib_bmg_v1_0_7.blk_mem_gen_wrapper
generic map (
c_family => C_FAMILY,
c_xdevicefamily => C_FAMILY,
c_mem_type => 2,
c_algorithm => 1,
c_prim_type => 1,
c_byte_size => 8, -- 8 or 9
c_sim_collision_check => "NONE",
c_common_clk => 1, -- 0, 1
c_disable_warn_bhv_coll => 1, -- 0, 1
c_disable_warn_bhv_range => 1, -- 0, 1
c_load_init_file => 0,
c_init_file_name => "no_coe_file_loaded",
c_use_default_data => 0, -- 0, 1
c_default_data => "0", -- "..."
-- Port A Specific Configurations
c_has_mem_output_regs_a => 0, -- 0, 1
c_has_mux_output_regs_a => 0, -- 0, 1
c_write_width_a => 4, -- 1 to 1152
c_read_width_a => 4, -- 1 to 1152
c_write_depth_a => 4096, -- 2 to 9011200
c_read_depth_a => 4096, -- 2 to 9011200
c_addra_width => 12, -- 1 to 24
c_write_mode_a => "READ_FIRST",
c_has_ena => 1, -- 0, 1
c_has_regcea => 1, -- 0, 1
c_has_ssra => 0, -- 0, 1
c_sinita_val => "0", --"..."
c_use_byte_wea => 0, -- 0, 1
c_wea_width => 1, -- 1 to 128
-- Port B Specific Configurations
c_has_mem_output_regs_b => 0, -- 0, 1
c_has_mux_output_regs_b => 0, -- 0, 1
c_write_width_b => 32, -- 1 to 1152
c_read_width_b => 32, -- 1 to 1152
c_write_depth_b => 512, -- 2 to 9011200
c_read_depth_b => 512, -- 2 to 9011200
c_addrb_width => 9, -- 1 to 24
c_write_mode_b => "READ_FIRST",
c_has_enb => 1, -- 0, 1
c_has_regceb => 1, -- 0, 1
c_has_ssrb => 0, -- 0, 1
c_sinitb_val => "0", -- "..."
c_use_byte_web => 0, -- 0, 1
c_web_width => 1, -- 1 to 128
-- Other Miscellaneous Configurations
c_mux_pipeline_stages => 0, -- 0, 1, 2, 3
c_use_ecc => 0,
c_use_ramb16bwer_rst_bhv => 0--, --0, 1
)
port map (
clka => Clk,
ssra => '0',
dina => Data_in_a,
addra => Adr_a,
ena => ce_a_i,
regcea => '1',
wea => wr_rd_n_a_i,
douta => Data_out_a,
clkb => Clk,
ssrb => '0',
dinb => Data_in_b,
addrb => Adr_b,
enb => ce_b_i,
regceb => '1',
web => wr_rd_n_b_i,
doutb => Data_out_b,
dbiterr => open,
sbiterr => open );
end generate;
--assert (create_v2_mem)
--report "The primitive RAMB16_S4_S36 is not Supported by the Target device"
--severity FAILURE;
end architecture imp;
-------------------------------------------------------------------------------
-- emac - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : emac.vhd
-- Version : v2.0
-- Description : Design file for the Ethernet Lite MAC.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0_9 library is used for axi_ethernetlite_v3_0_9
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0_9;
use axi_ethernetlite_v3_0_9.mac_pkg.all;
use axi_ethernetlite_v3_0_9.all;
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
library lib_cdc_v1_0_2;
use lib_cdc_v1_0_2.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-- NODE_MAC -- EMACLite MAC address
-- C_FAMILY -- Target device family
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- PHY_tx_clk -- Ethernet tranmit clock
-- PHY_rx_clk -- Ethernet receive clock
-- PHY_crs -- Ethernet carrier sense
-- PHY_dv -- Ethernet receive data valid
-- PHY_rx_data -- Ethernet receive data
-- PHY_col -- Ethernet collision indicator
-- PHY_rx_er -- Ethernet receive error
-- PHY_rst_n -- Ethernet PHY Reset
-- PHY_tx_en -- Ethernet transmit enable
-- PHY_tx_data -- Ethernet transmit data
-- Tx_DPM_ce -- TX buffer chip enable
-- Tx_DPM_adr -- Tx buffer address
-- Tx_DPM_wr_data -- TX buffer write data
-- Tx_DPM_rd_data -- TX buffer read data
-- Tx_DPM_wr_rd_n -- TX buffer write/read enable
-- Tx_done -- Transmit done
-- Tx_pong_ping_l -- TX Ping/Pong buffer enable
-- Tx_idle -- Transmit idle
-- Rx_idle -- Receive idle
-- Rx_DPM_ce -- RX buffer chip enable
-- Rx_DPM_adr -- RX buffer address
-- Rx_DPM_wr_data -- RX buffer write data
-- Rx_DPM_rd_data -- RX buffer read data
-- Rx_DPM_wr_rd_n -- RX buffer write/read enable
-- Rx_done -- Receive done
-- Rx_pong_ping_l -- RX Ping/Pong buffer enable
-- Tx_packet_length -- Transmit packet length
-- Transmit_start -- Transmit Start
-- Mac_program_start -- MAC Program start
-- Rx_buffer_ready -- RX Buffer ready indicator
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity emac is
generic (
C_DUPLEX : integer := 1;
-- 1 = full duplex, 0 = half duplex
NODE_MAC : bit_vector := x"00005e00FACE";
C_FAMILY : string := "virtex6"
);
port (
Clk : in std_logic;
Rst : in std_logic;
Phy_tx_clk : in std_logic;
Phy_rx_clk : in std_logic;
Phy_crs : in std_logic;
Phy_dv : in std_logic;
Phy_rx_data : in std_logic_vector (0 to 3);
Phy_col : in std_logic;
Phy_rx_er : in std_logic;
Phy_tx_en : out std_logic;
Phy_tx_data : out std_logic_vector (0 to 3);
Tx_DPM_ce : out std_logic;
Tx_DPM_adr : out std_logic_vector (0 to 11);
Tx_DPM_wr_data : out std_logic_vector (0 to 3);
Tx_DPM_rd_data : in std_logic_vector (0 to 3);
Tx_DPM_wr_rd_n : out std_logic;
Tx_done : out std_logic;
Tx_pong_ping_l : in std_logic;
Tx_idle : out std_logic;
Rx_idle : out std_logic;
Rx_DPM_ce : out std_logic;
Rx_DPM_adr : out std_logic_vector (0 to 11);
Rx_DPM_wr_data : out std_logic_vector (0 to 3);
Rx_DPM_rd_data : in std_logic_vector (0 to 3);
Rx_DPM_wr_rd_n : out std_logic;
Rx_done : out std_logic;
Rx_pong_ping_l : in std_logic;
Tx_packet_length : in std_logic_vector(0 to 15);
Transmit_start : in std_logic;
Mac_program_start : in std_logic;
Rx_buffer_ready : in std_logic
);
end emac;
architecture imp of emac is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
signal phy_col_d1 : std_logic; -- added 3-03-05 MSH
signal phy_crs_d1 : std_logic; -- added 3-03-05 MSH
signal phy_col_d2 : std_logic; -- added 27-jul-2011
signal phy_crs_d2 : std_logic; -- added 27-jul-2011
signal rxbuffer_addr : std_logic_vector(0 to 11);
signal rx_addr_en : std_logic;
signal rx_start : std_logic;
signal txbuffer_addr : std_logic_vector(0 to 11);
signal tx_addr_en : std_logic;
signal tx_start : std_logic;
signal mac_addr_ram_addr : std_logic_vector(0 to 3);
signal mac_addr_ram_addr_rd : std_logic_vector(0 to 3);
signal mac_addr_ram_we : std_logic;
signal mac_addr_ram_addr_wr : std_logic_vector(0 to 3);
signal mac_addr_ram_data : std_logic_vector(0 to 3);
signal txClkEn : std_logic;
signal tx_clk_reg_d1 : std_logic;
signal tx_clk_reg_d2 : std_logic;
signal tx_clk_reg_d3 : std_logic;
signal mac_tx_frame_length : std_logic_vector(0 to 15);
signal nibbleLength : std_logic_vector(0 to 11);
signal nibbleLength_orig : std_logic_vector(0 to 11);
signal en_pad : std_logic;
signal Phy_tx_clk_axi_d : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- The following components are the building blocks of the EMAC
component FDR
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
begin
----------------------------------------------------------------------------
-- Receive Interface
----------------------------------------------------------------------------
RX: entity axi_ethernetlite_v3_0_9.receive
generic map
(
C_DUPLEX => C_DUPLEX,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Rst => Rst,
Phy_rx_clk => Phy_rx_clk,
Phy_dv => Phy_dv,
Phy_rx_data => Phy_rx_data,
Phy_rx_col => phy_col_d2,
Phy_rx_er => Phy_rx_er,
Rx_addr_en => rx_addr_en,
Rx_start => rx_start,
Rx_done => Rx_done,
Rx_pong_ping_l => Rx_pong_ping_l,
Rx_DPM_ce => Rx_DPM_ce,
Rx_DPM_wr_data => Rx_DPM_wr_data,
Rx_DPM_rd_data => Rx_DPM_rd_data,
Rx_DPM_wr_rd_n => Rx_DPM_wr_rd_n,
Rx_idle => Rx_idle,
Mac_addr_ram_addr_rd => mac_addr_ram_addr_rd,
Mac_addr_ram_data => mac_addr_ram_data,
Rx_buffer_ready => Rx_buffer_ready
);
----------------------------------------------------------------------------
-- Transmit Interface
----------------------------------------------------------------------------
TX: entity axi_ethernetlite_v3_0_9.transmit
generic map
(
C_DUPLEX => C_DUPLEX,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Rst => Rst,
NibbleLength => nibbleLength,
NibbleLength_orig => nibbleLength_orig,
En_pad => en_pad,
TxClkEn => txClkEn,
Phy_tx_clk => Phy_tx_clk,
Phy_crs => phy_crs_d2,
Phy_col => phy_col_d2,
Phy_tx_en => phy_tx_en,
Phy_tx_data => phy_tx_data,
Tx_addr_en => tx_addr_en,
Tx_start => tx_start,
Tx_done => Tx_done,
Tx_pong_ping_l => Tx_pong_ping_l,
Tx_idle => Tx_idle,
Tx_DPM_ce => Tx_DPM_ce,
Tx_DPM_wr_data => Tx_DPM_wr_data,
Tx_DPM_rd_data => Tx_DPM_rd_data,
Tx_DPM_wr_rd_n => Tx_DPM_wr_rd_n,
Transmit_start => Transmit_start,
Mac_program_start => Mac_program_start,
Mac_addr_ram_we => mac_addr_ram_we,
Mac_addr_ram_addr_wr => mac_addr_ram_addr_wr
);
----------------------------------------------------------------------------
-- Registerign PHY Col
----------------------------------------------------------------------------
COLLISION_SYNC_1: FDR
port map
(
Q => phy_col_d1, --[out]
C => Clk, --[in]
D => Phy_col, --[in]
R => Rst --[in]
);
COLLISION_SYNC_2: FDR
port map
(
Q => phy_col_d2, --[out]
C => Clk, --[in]
D => phy_col_d1, --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- Registerign PHY CRs
----------------------------------------------------------------------------
C_SENSE_SYNC_1: FDR
port map
(
Q => phy_crs_d1, --[out]
C => Clk, --[in]
D => Phy_crs, --[in]
R => Rst --[in]
);
C_SENSE_SYNC_2: FDR
port map
(
Q => phy_crs_d2, --[out]
C => Clk, --[in]
D => phy_crs_d1, --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- MAC Address RAM
----------------------------------------------------------------------------
NODEMACADDRRAMI: entity axi_ethernetlite_v3_0_9.MacAddrRAM
generic map
(
MACAddr => NODE_MAC
)
port map
(
addr => mac_addr_ram_addr,
dout => mac_addr_ram_data,
din => Tx_DPM_rd_data,
we => mac_addr_ram_we,
Clk => Clk
);
mac_addr_ram_addr <= mac_addr_ram_addr_rd when mac_addr_ram_we = '0' else
mac_addr_ram_addr_wr;
----------------------------------------------------------------------------
-- RX Address Counter for the RxBuffer
----------------------------------------------------------------------------
RXADDRCNT: process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
rxbuffer_addr <= (others => '0');
elsif rx_start = '1' then
rxbuffer_addr <= (others => '0');
elsif rx_addr_en = '1' then
rxbuffer_addr <= rxbuffer_addr + 1;
end if;
end if;
end process RXADDRCNT;
Rx_DPM_adr <= rxbuffer_addr;
----------------------------------------------------------------------------
-- TX Address Counter for the TxBuffer (To Read)
----------------------------------------------------------------------------
TXADDRCNT: process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
txbuffer_addr <= (others => '0');
elsif tx_start = '1' then
txbuffer_addr <= (others => '0');
elsif tx_addr_en = '1' then
txbuffer_addr <= txbuffer_addr + 1;
end if;
end if;
end process TXADDRCNT;
Tx_DPM_adr <= txbuffer_addr;
----------------------------------------------------------------------------
-- CDC module for syncing phy_tx_clk in PHY_tx_clk domain
----------------------------------------------------------------------------
CDC_TX_CLK: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => Phy_tx_clk,
prmry_ack => open,
scndry_out => Phy_tx_clk_axi_d,
scndry_aclk => Clk,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
----------------------------------------------------------------------------
-- INT_tx_clk_sync_PROCESS
----------------------------------------------------------------------------
-- This process syncronizes the tx Clk and generates an enable pulse
----------------------------------------------------------------------------
INT_TX_CLK_SYNC_PROCESS : process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
tx_clk_reg_d1 <= '0';
tx_clk_reg_d2 <= '0';
tx_clk_reg_d3 <= '0';
else
tx_clk_reg_d1 <= Phy_tx_clk_axi_d;
tx_clk_reg_d2 <= tx_clk_reg_d1;
tx_clk_reg_d3 <= tx_clk_reg_d2;
end if;
end if;
end process INT_TX_CLK_SYNC_PROCESS;
txClkEn <= '1' when tx_clk_reg_d2 = '1' and tx_clk_reg_d3 = '0' else
'0';
----------------------------------------------------------------------------
-- ADJP
----------------------------------------------------------------------------
-- Adjust the packet length is it is less than minimum
----------------------------------------------------------------------------
ADJP : process(mac_tx_frame_length)
begin
if mac_tx_frame_length > MinimumPacketLength then
nibbleLength <= mac_tx_frame_length(5 to 15) & '0';
en_pad <= '0';
else
nibbleLength <= MinimumPacketLength(5 to 15) & '0';
en_pad <= '1';
end if;
end process ADJP;
nibbleLength_orig <= mac_tx_frame_length(5 to 15) & '0';
mac_tx_frame_length <= Tx_packet_length;
----------------------------------------------------------------------------
end imp;
-------------------------------------------------------------------------------
-- xemac.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : xemac.vhd
-- Version : v2.0
-- Description : Design file for the Ethernet Lite MAC with
-- IPIF elements included.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-- PVK 07/21/2010
-- ^^^^^^
-- Updated local register decoding logic to fix the issue related with read.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0_9 library is used for axi_ethernetlite_v3_0_9
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0_9;
use axi_ethernetlite_v3_0_9.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_FAMILY -- Target device family (spartan3e, spartan3a,
-- spartan3an, spartan3af, virtex4 or virtex6)
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width - allowed value - 32 only
-- C_S_AXI_DATA_WIDTH -- AXI data bus width - allowed value - 32 only
-- C_S_AXI_ACLK_PERIOD_PS -- The period of the AXI clock in ps
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-- C_TX_PING_PONG -- 1 = ping-pong memory used for transmit buffer
-- C_RX_PING_PONG -- 1 = ping-pong memory used for receive buffer
-- C_INCLUDE_MDIO -- 1 = Include MDIO Innterface, 0 = No MDIO Interface
-- NODE_MAC -- = Default MAC address of the core
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- System signals
-- Clk -- System clock
-- Rst -- System Reset
-- IP2INTC_Irpt -- System Interrupt
-- IPIC signals
-- IP2Bus_Data -- IP to Bus data
-- IP2Bus_Error -- IP to Bus error
-- Bus2IP_Addr -- Bus to IP address
-- Bus2IP_Data -- Bus to IP data
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- Bus2IP_Burst -- Bus to IP burst
-- Ethernet
-- PHY_tx_clk -- Ethernet tranmit clock
-- PHY_rx_clk -- Ethernet receive clock
-- PHY_crs -- Ethernet carrier sense
-- PHY_dv -- Ethernet receive data valid
-- PHY_rx_data -- Ethernet receive data
-- PHY_col -- Ethernet collision indicator
-- PHY_rx_er -- Ethernet receive error
-- PHY_rst_n -- Ethernet PHY Reset
-- PHY_tx_en -- Ethernet transmit enable
-- PHY_tx_data -- Ethernet transmit data
-- Loopback -- Internal Loopback enable
-- PHY_MDIO_I -- Ethernet PHY MDIO data input
-- PHY_MDIO_O -- Ethernet PHY MDIO data output
-- PHY_MDIO_T -- Ethernet PHY MDIO data 3-state control
-- PHY_MDC -- Ethernet PHY management clock
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity xemac is
generic (
C_FAMILY : string := "virtex6";
C_SELECT_XPM : integer := 1;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ACLK_PERIOD_PS : integer := 10000;
C_DUPLEX : integer := 1; -- 1 = full duplex, 0 = half duplex
C_RX_PING_PONG : integer := 0; -- 1 = ping-pong memory used for
-- receive buffer
C_TX_PING_PONG : integer := 0; -- 1 = ping-pong memory used for
-- transmit buffer
C_INCLUDE_MDIO : integer := 1; -- 1 = Include MDIO interface
-- 0 = No MDIO interface
NODE_MAC : bit_vector := x"00005e00FACE"
-- power up defaul MAC address
);
port (
Clk : in std_logic;
Rst : in std_logic;
IP2INTC_Irpt : out std_logic;
-- Controls to the IP/IPIF modules
IP2Bus_Data : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0 );
IP2Bus_Error : out std_logic;
Bus2IP_Addr : in std_logic_vector(12 downto 0);
Bus2IP_Data : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
Bus2IP_BE : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1)downto 0);
Bus2IP_RdCE : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Burst : in std_logic;
-- Ethernet Interface
PHY_tx_clk : in std_logic;
PHY_rx_clk : in std_logic;
PHY_crs : in std_logic;
PHY_dv : in std_logic;
PHY_rx_data : in std_logic_vector (3 downto 0);
PHY_col : in std_logic;
PHY_rx_er : in std_logic;
PHY_tx_en : out std_logic;
PHY_tx_data : out std_logic_vector (3 downto 0);
Loopback : out std_logic;
-- MDIO Interface
PHY_MDIO_I : in std_logic;
PHY_MDIO_O : out std_logic;
PHY_MDIO_T : out std_logic;
PHY_MDC : out std_logic
);
end xemac;
architecture imp of xemac is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant MDIO_CNT : integer := ((200000/C_S_AXI_ACLK_PERIOD_PS)+1);
constant IP2BUS_DATA_ZERO : std_logic_vector(0 to 31) := X"00000000";
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal phy_rx_data_i : std_logic_vector (3 downto 0);
signal phy_tx_data_i : std_logic_vector (3 downto 0);
signal tx_DPM_ce : std_logic;
signal tx_DPM_ce_i : std_logic; -- added 03-03-05 MSH
signal tx_DPM_adr : std_logic_vector (11 downto 0);
signal tx_DPM_wr_data : std_logic_vector (3 downto 0);
signal tx_DPM_rd_data : std_logic_vector (3 downto 0);
signal tx_ping_rd_data : std_logic_vector (3 downto 0);
signal tx_pong_rd_data : std_logic_vector (3 downto 0) := (others => '0');
signal tx_DPM_wr_rd_n : std_logic;
signal rx_DPM_ce : std_logic;
signal rx_DPM_ce_i : std_logic; -- added 03-03-05 MSH
signal rx_DPM_adr : std_logic_vector (11 downto 0);
signal rx_DPM_wr_data : std_logic_vector (3 downto 0);
signal rx_DPM_rd_data : std_logic_vector (3 downto 0);
signal rx_ping_rd_data : std_logic_vector (3 downto 0);
signal rx_pong_rd_data : std_logic_vector (3 downto 0) := (others => '0');
signal rx_DPM_wr_rd_n : std_logic;
signal IPIF_tx_Ping_CE : std_logic;
signal IPIF_tx_Pong_CE : std_logic := '0';
signal IPIF_rx_Ping_CE : std_logic;
signal IPIF_rx_Pong_CE : std_logic := '0';
signal tx_ping_data_out : std_logic_vector (31 downto 0);
signal tx_pong_data_out : std_logic_vector (31 downto 0) := (others => '0');
signal rx_ping_data_out : std_logic_vector (31 downto 0);
signal rx_pong_data_out : std_logic_vector (31 downto 0) := (others => '0');
signal dpm_wr_ack : std_logic;
signal dpm_rd_ack : std_logic;
signal rx_done : std_logic;
signal rx_done_d1 : std_logic := '0';
signal tx_done : std_logic;
signal tx_done_d1 : std_logic := '0';
signal tx_done_d2 : std_logic := '0';
signal tx_ping_ce : std_logic;
signal tx_pong_ping_l : std_logic := '0';
signal tx_idle : std_logic;
signal rx_idle : std_logic;
signal rx_ping_ce : std_logic;
signal rx_pong_ping_l : std_logic := '0';
signal reg_access : std_logic;
signal reg_en : std_logic;
signal tx_ping_reg_en : std_logic;
signal tx_pong_reg_en : std_logic;
signal rx_ping_reg_en : std_logic;
signal rx_pong_reg_en : std_logic;
signal tx_ping_ctrl_reg_en : std_logic;
signal tx_ping_length_reg_en : std_logic;
signal tx_pong_ctrl_reg_en : std_logic;
signal tx_pong_length_reg_en : std_logic;
signal rx_ping_ctrl_reg_en : std_logic;
signal rx_pong_ctrl_reg_en : std_logic;
signal loopback_en : std_logic;
signal tx_intr_en : std_logic;
signal ping_mac_program : std_logic;
signal pong_mac_program : std_logic;
signal ping_tx_status : std_logic;
signal pong_tx_status : std_logic;
signal ping_pkt_lenth : std_logic_vector(15 downto 0);
signal pong_pkt_lenth : std_logic_vector(15 downto 0);
signal rx_intr_en : std_logic;
signal ping_rx_status : std_logic;
signal pong_rx_status : std_logic;
signal ping_tx_done : std_logic;
signal mdio_data_out : std_logic_vector(31 downto 0);
signal reg_data_out : std_logic_vector(31 downto 0);
signal mdio_reg_en : std_logic;
signal gie_reg : std_logic;
signal gie_reg_en : std_logic;
signal gie_enable : std_logic;
signal tx_packet_length : std_logic_vector(15 downto 0);
signal stat_reg_en : std_logic;
signal status_reg : std_logic_vector(5 downto 0);
signal ping_mac_prog_done : std_logic;
signal transmit_start : std_logic;
signal mac_program_start : std_logic;
signal rx_buffer_ready : std_logic;
signal dpm_addr_ack : std_logic;
signal control_reg : std_logic;
signal length_reg : std_logic;
signal word_access : std_logic;
signal reg_access_i : std_logic;
signal ip2intc_irpt_i : std_logic;
signal reg_access_d1 : std_logic;
signal ping_soft_status : std_logic;
signal pong_soft_status : std_logic;
signal rx_pong_ce_en : std_logic;
signal tx_pong_ce_en : std_logic;
-------------------------------------------------------------------------------
-- New ipif_ssp1 signal declaration --
-------------------------------------------------------------------------------
signal bus2ip_ce : std_logic;
signal tx_ping_ce_en : std_logic;
signal rx_ping_ce_en : std_logic;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component SRL16E
generic (
INIT : bit_vector := X"0000"
);
port (
Q : out std_logic; --[out]
A0 : in std_logic; --[in]
A1 : in std_logic; --[in]
A2 : in std_logic; --[in]
A3 : in std_logic; --[in]
CE : in std_logic; --[in]
CLK : in std_logic; --[in]
D : in std_logic --[in]
);
end component;
component FDR
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component FDRE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component LUT4
generic(INIT : bit_vector);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end component;
begin
IP2Bus_Error <= '0';
-- IP2INTC_Irpt generation if global interrupt is enable
ip2intc_irpt_i <= gie_enable and ((rx_done and rx_intr_en) or
(tx_done and tx_intr_en));
----------------------------------------------------------------------------
-- IP2INTC_IRPT register
----------------------------------------------------------------------------
IP2INTC_IRPT_REG_I: FDR
port map (
Q => IP2INTC_Irpt , --[out]
C => Clk , --[in]
D => ip2intc_irpt_i, --[in]
R => Rst --[in]
);
-- ----------------------------------------------------------------------------
-- -- IPIF interface
-- ----------------------------------------------------------------------------
-- PHY_tx_data conversion
PHY_tx_data(0) <= phy_tx_data_i(0);
PHY_tx_data(1) <= phy_tx_data_i(1);
PHY_tx_data(2) <= phy_tx_data_i(2);
PHY_tx_data(3) <= phy_tx_data_i(3);
-- PHY_rx_data conversion
phy_rx_data_i(0) <= PHY_rx_data(0);
phy_rx_data_i(1) <= PHY_rx_data(1);
phy_rx_data_i(2) <= PHY_rx_data(2);
phy_rx_data_i(3) <= PHY_rx_data(3);
----------------------------------------------------------------------------
-- EMAC
----------------------------------------------------------------------------
EMAC_I: entity axi_ethernetlite_v3_0_9.emac
generic map (
C_DUPLEX => C_DUPLEX,
NODE_MAC => NODE_MAC,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Rst => Rst,
Phy_tx_clk => PHY_tx_clk,
Phy_rx_clk => PHY_rx_clk,
Phy_crs => phy_crs,
Phy_dv => Phy_dv,
Phy_rx_data => Phy_rx_data_i,
Phy_col => Phy_col,
Phy_rx_er => Phy_rx_er,
Phy_tx_en => Phy_tx_en,
Phy_tx_data => Phy_tx_data_i,
Tx_DPM_ce => tx_DPM_ce_i,
Tx_DPM_adr => tx_DPM_adr,
Tx_DPM_wr_data => tx_DPM_wr_data,
Tx_DPM_rd_data => tx_DPM_rd_data,
Tx_DPM_wr_rd_n => tx_DPM_wr_rd_n,
Tx_done => tx_done,
Tx_pong_ping_l => tx_pong_ping_l,
Tx_idle => tx_idle,
Rx_idle => rx_idle,
Rx_DPM_ce => rx_DPM_ce_i,
Rx_DPM_adr => rx_DPM_adr,
Rx_DPM_wr_data => rx_DPM_wr_data,
Rx_DPM_rd_data => rx_DPM_rd_data,
Rx_DPM_wr_rd_n => rx_DPM_wr_rd_n ,
Rx_done => rx_done,
Rx_pong_ping_l => rx_pong_ping_l,
Tx_packet_length => tx_packet_length,
Transmit_start => transmit_start,
Mac_program_start => mac_program_start,
Rx_buffer_ready => rx_buffer_ready
);
----------------------------------------------------------------------------
-- This core only supports word access
word_access <= '1' when bus2ip_be="1111" else '0';
-- DPRAM buffer chip enable generation
bus2ip_ce <= (Bus2IP_RdCE or (Bus2IP_WrCE and word_access));
tx_ping_ce_en <= not Bus2IP_Addr(12) and not Bus2IP_Addr(11);
rx_ping_ce_en <= Bus2IP_Addr(12) and not Bus2IP_Addr(11);
IPIF_tx_Ping_CE <= bus2ip_ce and tx_ping_ce_en;
IPIF_rx_Ping_CE <= bus2ip_ce and rx_ping_ce_en;
-- IP2Bus_Data generation
IP2BUS_DATA_GENERATE: for i in 31 downto 0 generate
IP2Bus_Data(i) <= ((
(tx_ping_data_out(i) and tx_ping_ce_en) or
(tx_pong_data_out(i) and tx_pong_ce_en) or
(rx_ping_data_out(i) and rx_ping_ce_en) or
(rx_pong_data_out(i) and rx_pong_ce_en)
) and not reg_access)
or
((
(reg_data_out(i) and not mdio_reg_en) or
(mdio_data_out(i) and mdio_reg_en)
) and reg_access) ;
end generate IP2BUS_DATA_GENERATE;
----------------------------------------------------------------------------
-- DPM_TX_RD_DATA_GENERATE
----------------------------------------------------------------------------
-- This logic generates tx_DPM_rd_data for transmit section from
-- tx_ping_buffer and tx_pong_buffer.
----------------------------------------------------------------------------
DPM_TX_RD_DATA_GENERATE: for i in 0 to 3 generate
tx_DPM_rd_data(i) <= (tx_ping_rd_data(i) and not tx_pong_ping_l
and (not tx_idle)) or
(tx_pong_rd_data(i) and tx_pong_ping_l
and (not tx_idle));
end generate DPM_TX_RD_DATA_GENERATE;
----------------------------------------------------------------------------
-- DPM_RX_RD_DATA_GENERATE
----------------------------------------------------------------------------
-- This logic generates rx_DPM_rd_data for receive section from
-- rx_ping_buffer and rx_pong_buffer.
----------------------------------------------------------------------------
DPM_RX_RD_DATA_GENERATE: for i in 0 to 3 generate
rx_DPM_rd_data(i) <= (rx_ping_rd_data(i) and not rx_pong_ping_l) or
(rx_pong_rd_data(i) and rx_pong_ping_l);
end generate DPM_RX_RD_DATA_GENERATE;
-- Chip enable generation
tx_ping_ce <= tx_DPM_ce and not tx_pong_ping_l;
tx_DPM_ce <= tx_DPM_ce_i;
rx_DPM_ce <= rx_DPM_ce_i;
rx_ping_ce <= rx_DPM_ce and not rx_pong_ping_l;
----------------------------------------------------------------------------
-- TX_PING Buffer
----------------------------------------------------------------------------
TX_PING: entity axi_ethernetlite_v3_0_9.emac_dpram
generic map (
C_FAMILY => C_FAMILY,
C_SELECT_XPM => C_SELECT_XPM
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => tx_ping_ce ,
Wr_rd_n_a => tx_DPM_wr_rd_n ,
Adr_a => tx_DPM_adr ,
Data_in_a => tx_DPM_wr_data ,
Data_out_a => tx_ping_rd_data ,
Ce_b => IPIF_tx_Ping_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => tx_ping_data_out
);
----------------------------------------------------------------------------
-- RX_PING Buffer
----------------------------------------------------------------------------
RX_PING: entity axi_ethernetlite_v3_0_9.emac_dpram
generic map (
C_FAMILY => C_FAMILY,
C_SELECT_XPM => C_SELECT_XPM
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => rx_ping_ce ,
Wr_rd_n_a => rx_DPM_wr_rd_n ,
Adr_a => rx_DPM_adr ,
Data_in_a => rx_DPM_wr_data ,
Data_out_a => rx_ping_rd_data ,
Ce_b => IPIF_rx_Ping_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => rx_ping_data_out
);
----------------------------------------------------------------------------
-- TX Done register
----------------------------------------------------------------------------
TX_DONE_D1_I: FDR
port map (
Q => tx_done_d1 , --[out]
C => Clk , --[in]
D => tx_done , --[in]
R => Rst --[in]
);
TX_DONE_D2_I: FDR
port map (
Q => tx_done_d2 , --[out]
C => Clk , --[in]
D => tx_done_d1 , --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- Transmit Pong memory generate
----------------------------------------------------------------------------
TX_PONG_GEN: if C_TX_PING_PONG = 1 generate
signal tx_pong_ce : std_logic;
signal pp_tog_ce : std_logic;
attribute INIT : string;
-- attribute INIT of PP_TOG_LUT_I: label is "1111";
Begin
TX_PONG_I: entity axi_ethernetlite_v3_0_9.emac_dpram
generic map (
C_FAMILY => C_FAMILY,
C_SELECT_XPM => C_SELECT_XPM
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => tx_pong_ce ,
Wr_rd_n_a => tx_DPM_wr_rd_n ,
Adr_a => tx_DPM_adr ,
Data_in_a => tx_DPM_wr_data ,
Data_out_a => tx_pong_rd_data ,
Ce_b => IPIF_tx_Pong_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => tx_pong_data_out
);
-- TX Pong Buffer Chip enable
tx_pong_ce <= tx_DPM_ce and tx_pong_ping_l;
--IPIF_tx_Pong_CE <= bus2ip_ce and not Bus2IP_Addr(12) Bus2IP_Addr(11);
IPIF_tx_Pong_CE <= bus2ip_ce and tx_pong_ce_en;
tx_pong_ce_en <= not Bus2IP_Addr(12) and Bus2IP_Addr(11);
-------------------------------------------------------------------------
-- TX_PONG_PING_L_PROCESS
-------------------------------------------------------------------------
-- This process generate tx_pong_ping_l for TX PING/PONG buffer access
-------------------------------------------------------------------------
TX_PONG_PING_L_PROCESS:process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
tx_pong_ping_l <= '0';
elsif (tx_done_d1 = '1' ) then
tx_pong_ping_l <= not tx_pong_ping_l;
elsif (pong_tx_status = '1' and ping_tx_status = '0' ) then
tx_pong_ping_l <= '1';
elsif (pong_tx_status = '0' and ping_tx_status = '1' ) then
tx_pong_ping_l <= '0';
else
tx_pong_ping_l <= tx_pong_ping_l;
end if;
end if;
end process;
end generate TX_PONG_GEN;
----------------------------------------------------------------------------
-- RX Done register
----------------------------------------------------------------------------
RX_DONE_D1_I: FDR
port map (
Q => rx_done_d1 , --[out]
C => Clk , --[in]
D => rx_done , --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- Receive Pong memory generate
----------------------------------------------------------------------------
RX_PONG_GEN: if C_RX_PING_PONG = 1 generate
signal rx_pong_ce : std_logic;
Begin
RX_PONG_I: entity axi_ethernetlite_v3_0_9.emac_dpram
generic map (
C_FAMILY => C_FAMILY,
C_SELECT_XPM => C_SELECT_XPM
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => rx_pong_ce ,
Wr_rd_n_a => rx_DPM_wr_rd_n ,
Adr_a => rx_DPM_adr ,
Data_in_a => rx_DPM_wr_data ,
Data_out_a => rx_pong_rd_data ,
Ce_b => IPIF_rx_Pong_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => rx_pong_data_out
);
-- RX Pong Buffer enable
rx_pong_ce <= rx_DPM_ce and rx_pong_ping_l;
--IPIF_rx_Pong_CE <= bus2ip_ce and Bus2IP_Addr(12) and Bus2IP_Addr(11);
IPIF_rx_Pong_CE <= bus2ip_ce and rx_pong_ce_en;
rx_pong_ce_en <= Bus2IP_Addr(12) and Bus2IP_Addr(11);
-------------------------------------------------------------------------
-- RX_PONG_PING_L_PROCESS
-------------------------------------------------------------------------
-- This process generate rx_pong_ping_l for RX PING/PONG buffer access
-------------------------------------------------------------------------
RX_PONG_PING_L_PROCESS:process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
rx_pong_ping_l <= '0';
elsif (rx_done_d1 = '1') then
if rx_pong_ping_l = '0' then
rx_pong_ping_l <= '1';
else
rx_pong_ping_l <= '0';
end if;
else
rx_pong_ping_l <= rx_pong_ping_l;
end if;
end if;
end process;
end generate RX_PONG_GEN;
----------------------------------------------------------------------------
-- Regiter Address Decoding
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
-- Register Address Space
-----------------------------------------
-- **** MDIO Registers offset ****
-- Address Register => 0x07E4
-- Write Data Register => 0x07E8
-- Read Data Register => 0x07Ec
-- Control Register => 0x07F0
-----------------------------------------
-- **** Transmit Registers offset ****
-- Ping Length Register => 0x07F4
-- Ping Control Register => 0x07FC
-- Pong Length Register => 0x0FF4
-- Pong Control Register => 0x0FFC
-----------------------------------------
-- **** Receive Registers offset ****
-- Ping Control Register => 0x17FC
-- Pong Control Register => 0x1FFC
------------------------------------------
-- bus2ip_addr(12 downto 0)= axi_addr (12 downto 0)
----------------------------------------------------------------------------
reg_access_i <= '1' when bus2ip_addr(10 downto 5) = "111111"
else '0';
-- Register access enable
reg_en <= reg_access_i and (not Bus2IP_Burst);
-- TX/RX PING/PONG address decode
tx_ping_reg_en <= reg_en and (not bus2ip_addr(12)) and (not bus2ip_addr(11));
rx_ping_reg_en <= reg_en and ( bus2ip_addr(12)) and (not bus2ip_addr(11));
-- Status/Control/Length address decode
stat_reg_en <= not (bus2ip_addr(4) and bus2ip_addr(3) and bus2ip_addr(2));
control_reg <= bus2ip_addr(4) and bus2ip_addr(3) and bus2ip_addr(2);
length_reg <= bus2ip_addr(4) and (not bus2ip_addr(3)) and bus2ip_addr(2);
gie_reg <= bus2ip_addr(4) and bus2ip_addr(3) and (not bus2ip_addr(2));
---- TX/RX Ping/Pong Control/Length reg enable
tx_ping_ctrl_reg_en <= tx_ping_reg_en and control_reg;
tx_ping_length_reg_en <= tx_ping_reg_en and length_reg;
rx_ping_ctrl_reg_en <= rx_ping_reg_en and control_reg;
gie_reg_en <= tx_ping_reg_en and gie_reg;
----------------------------------------------------------------------------
-- REG_ACCESS_PROCESS
----------------------------------------------------------------------------
-- Registering the reg_access to break long timing path
----------------------------------------------------------------------------
REG_ACCESS_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
reg_access <= '0';
reg_access_d1 <= '0';
elsif Bus2IP_RdCE='1' then
-- TX/RX Ping/Pong Control/Length reg enable
reg_access <= reg_access_i;
reg_access_d1 <= reg_access;
end if;
end if;
end process REG_ACCESS_PROCESS;
----------------------------------------------------------------------------
-- TX_PONG_REG_GEN : Receive Pong Register generate
----------------------------------------------------------------------------
-- This Logic is included only if both the buffers are enabled.
----------------------------------------------------------------------------
TX_PONG_REG_GEN: if C_TX_PING_PONG = 1 generate
tx_pong_reg_en <= reg_en and (not bus2ip_addr(12))
and (bus2ip_addr(11));
tx_pong_ctrl_reg_en <= '1' when (tx_pong_reg_en='1') and
(control_reg='1') else
'0';
tx_pong_length_reg_en <= '1' when (tx_pong_reg_en='1') and
(length_reg='1') else
'0';
-------------------------------------------------------------------------
-- TX_PONG_CTRL_REG_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
-------------------------------------------------------------------------
TX_PONG_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
pong_mac_program <= '0';
pong_tx_status <= '0';
pong_soft_status <= '0';
elsif (Bus2IP_WrCE = '1' and tx_pong_ctrl_reg_en = '1') then
-- Load Pong Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
pong_soft_status <= Bus2IP_Data(31);
pong_mac_program <= Bus2IP_Data(1);
pong_tx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif (tx_done_d1 = '1' and tx_pong_ping_l = '1') then
pong_tx_status <= '0';
pong_mac_program <= '0';
end if;
end if;
end process TX_PONG_CTRL_REG_PROCESS;
-------------------------------------------------------------------------
-- TX_PONG_LENGTH_REG_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the length register is enabled.
-------------------------------------------------------------------------
TX_PONG_LENGTH_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
pong_pkt_lenth <= (others=>'0');
elsif (Bus2IP_WrCE = '1' and tx_pong_length_reg_en = '1') then
-- Load Packet length Register with AXI
-- data if there is a write request
-- and the length register is enabled
pong_pkt_lenth <= Bus2IP_Data(15 downto 0);
end if;
end if;
end process TX_PONG_LENGTH_REG_PROCESS;
end generate TX_PONG_REG_GEN;
----------------------------------------------------------------------------
-- NO_TX_PING_SIG :No Pong registers
----------------------------------------------------------------------------
NO_TX_PING_SIG: if C_TX_PING_PONG = 0 generate
tx_pong_ping_l <= '0';
tx_pong_length_reg_en <= '0';
tx_pong_ctrl_reg_en <= '0';
pong_pkt_lenth <= (others=>'0');
pong_mac_program <= '0';
pong_tx_status <= '0';
IPIF_tx_Pong_CE <= '0';
tx_pong_data_out <= (others=>'0');
tx_pong_rd_data <= (others=>'0');
end generate NO_TX_PING_SIG;
----------------------------------------------------------------------------
-- RX_PONG_REG_GEN: Receive Pong Register generate
----------------------------------------------------------------------------
-- This Logic is included only if both the buffers are enabled.
----------------------------------------------------------------------------
RX_PONG_REG_GEN: if C_RX_PING_PONG = 1 generate
rx_pong_reg_en <= reg_en and (bus2ip_addr(12)) and (bus2ip_addr(11));
rx_pong_ctrl_reg_en <= '1' when (rx_pong_reg_en='1') and
(control_reg='1') else
'0';
-- Receive frame indicator
rx_buffer_ready <= not (ping_rx_status and pong_rx_status);
-------------------------------------------------------------------------
-- RX_PONG_CTRL_REG_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the Pong control register is enabled.
-------------------------------------------------------------------------
RX_PONG_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
pong_rx_status <= '0';
elsif (Bus2IP_WrCE = '1' and rx_pong_ctrl_reg_en = '1') then
-- Load Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
pong_rx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
--elsif (rx_done_d1 = '1' and rx_pong_ping_l = '1') then
elsif (rx_done = '1' and rx_pong_ping_l = '1') then
pong_rx_status <= '1';
end if;
end if;
end process RX_PONG_CTRL_REG_PROCESS;
end generate RX_PONG_REG_GEN;
----------------------------------------------------------------------------
-- No Pong registers
----------------------------------------------------------------------------
NO_RX_PING_SIG: if C_RX_PING_PONG = 0 generate
rx_pong_ping_l <= '0';
rx_pong_reg_en <= '0';
rx_pong_ctrl_reg_en <= '0';
pong_rx_status <= '0';
IPIF_rx_Pong_CE <= '0';
rx_pong_rd_data <= (others=>'0');
rx_pong_data_out <= (others=>'0');
-- Receive frame indicator
rx_buffer_ready <= not ping_rx_status ;
end generate NO_RX_PING_SIG;
----------------------------------------------------------------------------
-- TX_PING_CTRL_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
TX_PING_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
tx_intr_en <= '0';
ping_mac_program <= '0';
ping_tx_status <= '0';
ping_soft_status <= '0';
elsif (Bus2IP_WrCE = '1' and tx_ping_ctrl_reg_en = '1') then
-- Load Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
ping_soft_status <= Bus2IP_Data(31);
tx_intr_en <= Bus2IP_Data(3);
ping_mac_program <= Bus2IP_Data(1);
ping_tx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif (tx_done_d1 = '1' and tx_pong_ping_l = '0') then
ping_tx_status <= '0';
ping_mac_program <= '0';
end if;
end if;
end process TX_PING_CTRL_REG_PROCESS;
----------------------------------------------------------------------------
-- TX_LOOPBACK_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
TX_LOOPBACK_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
loopback_en <= '0';
elsif (Bus2IP_WrCE = '1' and tx_ping_ctrl_reg_en = '1'
and tx_idle='1' ) then
-- Load loopback Register with AXI
-- data if there is a write request
-- and the Loopback register is enabled
loopback_en <= Bus2IP_Data(4);
-- Clear the status bit when trnasmit complete
end if;
end if;
end process TX_LOOPBACK_REG_PROCESS;
----------------------------------------------------------------------------
-- CDC module for syncing tx_en_i in fifo_empty domain
----------------------------------------------------------------------------
-- CDC_LOOPBACK: entity proc_common_v4_0_2.cdc_sync
-- generic map (
-- C_CDC_TYPE => 1,
-- C_RESET_STATE => 0,
-- C_SINGLE_BIT => 1,
-- C_FLOP_INPUT => 0,
-- C_VECTOR_WIDTH => 1,
-- C_MTBF_STAGES => 4
-- )
-- port map(
-- prmry_aclk => '1',
-- prmry_resetn => '1',
-- prmry_in => loopback_en,
-- prmry_ack => open,
-- scndry_out => Loopback,
-- scndry_aclk => PHY_rx_clk,
-- scndry_resetn => '1',
-- prmry_vect_in => (OTHERS => '0'),
-- scndry_vect_out => open
-- );
Loopback <= loopback_en; --added the cdc block to drive the output directly
----------------------------------------------------------------------------
-- TX_PING_LENGTH_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the Length register is enabled.
----------------------------------------------------------------------------
TX_PING_LENGTH_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
ping_pkt_lenth <= (others=>'0');
elsif (Bus2IP_WrCE = '1' and tx_ping_length_reg_en = '1') then
-- Load Packet length Register with AXI
-- data if there is a write request
-- and the length register is enabled
ping_pkt_lenth <= Bus2IP_Data(15 downto 0);
end if;
end if;
end process TX_PING_LENGTH_REG_PROCESS;
----------------------------------------------------------------------------
-- GIE_EN_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the GIE register is enabled.
----------------------------------------------------------------------------
GIE_EN_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
gie_enable <= '0';
elsif (Bus2IP_WrCE = '1' and gie_reg_en = '1') then
-- Load Global Interrupt Enable Register with AXI
-- data if there is a write request
-- and the length register is enabled
gie_enable <= Bus2IP_Data(31);
end if;
end if;
end process GIE_EN_REG_PROCESS;
----------------------------------------------------------------------------
-- RX_PING_CTRL_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the Ping control register is enabled.
----------------------------------------------------------------------------
RX_PING_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
rx_intr_en <= '0';
ping_rx_status <= '0';
elsif (Bus2IP_WrCE = '1' and rx_ping_ctrl_reg_en = '1') then
-- Load Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
rx_intr_en <= Bus2IP_Data(3);
ping_rx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif (rx_done = '1' and rx_pong_ping_l = '0') then
ping_rx_status <= '1';
end if;
end if;
end process RX_PING_CTRL_REG_PROCESS;
----------------------------------------------------------------------------
-- REGISTER_READ_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
REGISTER_READ_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
reg_data_out <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and tx_ping_ctrl_reg_en = '1') then
-- TX PING Control Register Read through AXI
reg_data_out(0) <= ping_tx_status;
reg_data_out(1) <= ping_mac_program;
reg_data_out(2) <= '0';
reg_data_out(3) <= tx_intr_en;
reg_data_out(4) <= loopback_en;
reg_data_out(31) <= ping_soft_status;
reg_data_out(30 downto 5) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and tx_pong_ctrl_reg_en = '1') then
-- TX PONG Control Register Read through AXI
reg_data_out(0) <= pong_tx_status;
reg_data_out(1) <= pong_mac_program;
reg_data_out(30 downto 2) <= (others=>'0');
reg_data_out(31) <= pong_soft_status;
elsif (Bus2IP_RdCE = '1' and tx_ping_length_reg_en = '1') then
-- TX PING Length Register Read through AXI
reg_data_out(31 downto 16) <= (others=>'0');
reg_data_out(15 downto 0) <= ping_pkt_lenth;
elsif (Bus2IP_RdCE = '1' and tx_pong_length_reg_en = '1') then
-- TX PONG Length Register Read through AXI
reg_data_out(31 downto 16) <= (others=>'0');
reg_data_out(15 downto 0) <= pong_pkt_lenth;
elsif (Bus2IP_RdCE = '1' and rx_ping_ctrl_reg_en = '1') then
-- RX PING Control Register Read through AXI
reg_data_out(0) <= ping_rx_status;
reg_data_out(1) <= '0';
reg_data_out(2) <= '0';
reg_data_out(3) <= rx_intr_en;
reg_data_out(31 downto 4) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and rx_pong_ctrl_reg_en = '1') then
-- RX PONG Control Register Read through AXI
reg_data_out(0) <= pong_rx_status;
reg_data_out(31 downto 1) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and gie_reg_en = '1') then
-- GIE Register Read through AXI
reg_data_out(31) <= gie_enable;
reg_data_out(30 downto 0) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and stat_reg_en = '1') then
-- Common Status Register Read through AXI
reg_data_out(0) <= status_reg(0);
reg_data_out(1) <= status_reg(1);
reg_data_out(2) <= status_reg(2);
reg_data_out(3) <= status_reg(3);
reg_data_out(4) <= status_reg(4);
reg_data_out(5) <= status_reg(5);
reg_data_out(31 downto 6) <= (others=>'0');
--else
-- reg_data_out <= (others=>'0');
end if;
end if;
end process REGISTER_READ_PROCESS;
----------------------------------------------------------------------------
-- COMMON_STATUS_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
-- status_reg : std_logic_vector(0 to 5);
-- status reg address = 0x07E0
-- status_reg(5) : Ping TX complete
-- status_reg(4) : Pong TX complete
-- status_reg(3) : Ping RX complete
-- status_reg(2) : Pong RX complete
-- status_reg(1) : Ping MAC program complete
-- status_reg(0) : Pong MAC program complete
-- All Status bit will be cleared after reading this register
----------------------------------------------------------------------------
COMMON_STATUS_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
status_reg <= (others=>'0');
elsif (tx_done = '1') then
if (tx_pong_ping_l = '0' and ping_mac_program='0' ) then
status_reg <= (others=>'0');
status_reg(5) <= '1';
elsif (tx_pong_ping_l = '0' and ping_mac_program='1' ) then
status_reg <= (others=>'0');
status_reg(1) <= '1';
elsif (tx_pong_ping_l = '1' and pong_mac_program='0' ) then
status_reg <= (others=>'0');
status_reg(4) <= '1';
elsif (tx_pong_ping_l = '1' and pong_mac_program='1' ) then
status_reg <= (others=>'0');
status_reg(0) <= '1';
end if;
elsif (rx_done_d1 = '1') then
if (rx_pong_ping_l = '0') then
status_reg <= (others=>'0');
status_reg(3) <= '1';
else
status_reg <= (others=>'0');
status_reg(2) <= '1';
end if;
end if;
end if;
end process COMMON_STATUS_REG_PROCESS;
----------------------------------------------------------------------------
-- TX_LENGTH_MUX_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
TX_LENGTH_MUX_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
tx_packet_length <= (others=>'0');
elsif (tx_pong_ping_l = '1') then
-- Load Control Register with AXI
tx_packet_length <= pong_pkt_lenth;
-- Clear the status bit when trnasmit complete
else
tx_packet_length <= ping_pkt_lenth;
end if;
end if;
end process TX_LENGTH_MUX_PROCESS;
-- Tx Start indicator
transmit_start <= ((ping_tx_status and not ping_mac_program) or
(pong_tx_status and not pong_mac_program)) and
not tx_done_d2;
-- MAC program start indicator
mac_program_start <= (ping_tx_status and ping_mac_program) or
(pong_tx_status and pong_mac_program);
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- MDIO_GEN :- Include MDIO interface if the parameter C_INCLUDE_MDIO = 1
----------------------------------------------------------------------------
MDIO_GEN: if C_INCLUDE_MDIO = 1 generate
signal mdio_addr_en : std_logic;
signal mdio_wr_data_en : std_logic;
signal mdio_rd_data_en : std_logic;
signal mdio_ctrl_en : std_logic;
signal mdio_op_i : std_logic;
signal mdio_en_i : std_logic;
signal mdio_req_i : std_logic;
signal mdio_done_i : std_logic;
signal mdio_wr_data_reg : std_logic_vector(15 downto 0);
signal mdio_rd_data_reg : std_logic_vector(15 downto 0);
signal mdio_phy_addr : std_logic_vector(4 downto 0);
signal mdio_reg_addr : std_logic_vector(4 downto 0);
signal mdio_clk_i : std_logic;
-- signal mdio_ctrl_en_reg : std_logic;
signal clk_cnt : integer range 0 to 63;
begin
-- MDIO reg enable
mdio_reg_en <= --not stat_reg_en_reg and
(mdio_addr_en or
mdio_wr_data_en or
mdio_rd_data_en or
mdio_ctrl_en ) and (not Bus2IP_Burst);
--mdio_ctrl_en or mdio_ctrl_en_reg ) and (not Bus2IP_Burst);
-- MDIO address reg enable
mdio_addr_en <= reg_en and (not bus2ip_addr(4))
and (not bus2ip_addr(3))
and ( bus2ip_addr(2));
-- MDIO write data reg enable
mdio_wr_data_en <= reg_en and (not bus2ip_addr(4))
and ( bus2ip_addr(3))
and (not bus2ip_addr(2));
-- MDIO read data reg enable
mdio_rd_data_en <= reg_en and (not bus2ip_addr(4))
and ( bus2ip_addr(3))
and ( bus2ip_addr(2));
-- MDIO controlreg enable
mdio_ctrl_en <= reg_en and ( bus2ip_addr(4))
and (not bus2ip_addr(3))
and (not bus2ip_addr(2));
-------------------------------------------------------------------------
-- MDIO_CTRL_REG_WR_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the MDIO control register is enabled.
-------------------------------------------------------------------------
MDIO_CTRL_REG_WR_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_en_i <= '0';
mdio_req_i <= '0';
elsif (Bus2IP_WrCE = '1' and mdio_ctrl_en= '1') then
-- Load MDIO Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
mdio_en_i <= Bus2IP_Data(3);
mdio_req_i <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif mdio_done_i = '1' then
mdio_req_i <= '0';
end if;
end if;
end process MDIO_CTRL_REG_WR_PROCESS;
-------------------------------------------------------------------------
-- MDIO_ADDR_REG_WR_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the MDIO Address register is enabled.
-------------------------------------------------------------------------
MDIO_ADDR_REG_WR_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_phy_addr <= (others =>'0');
mdio_reg_addr <= (others =>'0');
mdio_op_i <= '0';
elsif (Bus2IP_WrCE = '1' and mdio_addr_en= '1') then
-- Load MDIO ADDR Register with AXI
-- data if there is a write request
-- and the Address register is enabled
mdio_phy_addr <= Bus2IP_Data(9 downto 5);
mdio_reg_addr <= Bus2IP_Data(4 downto 0);
mdio_op_i <= Bus2IP_Data(10);
end if;
end if;
end process MDIO_ADDR_REG_WR_PROCESS;
-------------------------------------------------------------------------
-- MDIO_WRITE_REG_WR_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request
-- and the MDIO Write register is enabled.
-------------------------------------------------------------------------
MDIO_WRITE_REG_WR_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_wr_data_reg <= (others =>'0');
elsif (Bus2IP_WrCE = '1' and mdio_wr_data_en= '1') then
-- Load MDIO Write Data Register with AXI
-- data if there is a write request
-- and the Write Data register is enabled
mdio_wr_data_reg <= Bus2IP_Data(15 downto 0);
end if;
end if;
end process MDIO_WRITE_REG_WR_PROCESS;
-------------------------------------------------------------------------
-- MDIO_REG_RD_PROCESS
-------------------------------------------------------------------------
-- This process allows MDIO register read from the AXI when there is a
-- read request and the MDIO registers are enabled.
-------------------------------------------------------------------------
MDIO_REG_RD_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_data_out <= (others =>'0');
elsif (Bus2IP_RdCE = '1' and mdio_addr_en= '1') then
-- MDIO Address Register Read through AXI
mdio_data_out(4 downto 0) <= mdio_reg_addr;
mdio_data_out(9 downto 5) <= mdio_phy_addr;
mdio_data_out(10) <= mdio_op_i;
mdio_data_out(31 downto 11) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and mdio_wr_data_en= '1') then
-- MDIO Write Data Register Read through AXI
mdio_data_out(15 downto 0) <= mdio_wr_data_reg;
mdio_data_out(31 downto 16) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and mdio_rd_data_en= '1') then
-- MDIO Read Data Register Read through AXI
mdio_data_out(15 downto 0) <= mdio_rd_data_reg;
mdio_data_out(31 downto 16) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and mdio_ctrl_en= '1') then
-- MDIO Control Register Read through AXI
mdio_data_out(0) <= mdio_req_i;
mdio_data_out(1) <= '0';
mdio_data_out(2) <= '0';
mdio_data_out(3) <= mdio_en_i;
mdio_data_out(31 downto 4) <= (others=>'0');
--else
-- mdio_data_out <= (others =>'0');
end if;
end if;
end process MDIO_REG_RD_PROCESS;
-------------------------------------------------------------------------
-- PROCESS : MDIO_CLK_COUNTER
-------------------------------------------------------------------------
-- Generating MDIO clock. The minimum period for MDC clock is 400 ns.
-------------------------------------------------------------------------
MDIO_CLK_COUNTER : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1' ) then
clk_cnt <= MDIO_CNT;
mdio_clk_i <= '0';
elsif (clk_cnt = 0) then
clk_cnt <= MDIO_CNT;
mdio_clk_i <= not mdio_clk_i;
else
clk_cnt <= clk_cnt - 1;
end if;
end if;
end process;
-------------------------------------------------------------------------
-- MDIO master interface module
-------------------------------------------------------------------------
MDIO_IF_I: entity axi_ethernetlite_v3_0_9.mdio_if
port map (
Clk => Clk ,
Rst => Rst ,
MDIO_CLK => mdio_clk_i ,
MDIO_en => mdio_en_i ,
MDIO_OP => mdio_op_i ,
MDIO_Req => mdio_req_i ,
MDIO_PHY_AD => mdio_phy_addr ,
MDIO_REG_AD => mdio_reg_addr ,
MDIO_WR_DATA => mdio_wr_data_reg ,
MDIO_RD_DATA => mdio_rd_data_reg ,
PHY_MDIO_I => PHY_MDIO_I ,
PHY_MDIO_O => PHY_MDIO_O ,
PHY_MDIO_T => PHY_MDIO_T ,
PHY_MDC => PHY_MDC ,
MDIO_done => mdio_done_i
);
end generate MDIO_GEN;
----------------------------------------------------------------------------
-- NO_MDIO_GEN :- Include MDIO interface if the parameter C_INCLUDE_MDIO = 0
----------------------------------------------------------------------------
NO_MDIO_GEN: if C_INCLUDE_MDIO = 0 generate
begin
mdio_data_out <= (others=>'0');
mdio_reg_en <= '0';
PHY_MDIO_O <= '0';
PHY_MDIO_T <= '1';
end generate NO_MDIO_GEN;
end imp;
-------------------------------------------------------------------------------
-- axi_interface - entity / architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: axi_interface.vhd
-- Version: v1.00a
-- Description: This module takes care of AXI protocol interface for AXI4
-- AXI4-Lite interfaces. This supports word access and INCR
-- burst only.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
--
-- AXI generics
-- C_S_AXI_PROTOCOL -- AXI protocol type
-- C_S_AXI_CTRL_BASEADDR -- Base address of the core
-- C_S_AXI_HIGHADDR -- Permits alias of address space
-- by making greater than xFFF
-- C_S_AXI_CTRL_ADDR_WIDTH -- Width of AXI Address Bus (in bits)
-- C_S_AXI_CTRL_DATA_WIDTH -- Width of the AXI Data Bus (in bits)
--
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System signals
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- IP2INTC_Irpt -- Device interrupt output to microprocessor
-- interrupt input or system interrupt controller.
-- AXI signals
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
--
-- IPIC signals
-- IP2Bus_Data -- IP to Bus data
-- IP2Bus_Error -- IP to Bus error
-- Bus2IP_Addr -- Bus to IP address
-- Bus2IP_Data -- Bus to IP data
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_Burst -- Bus to IP burst indicator
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity axi_interface is
generic (
-- -- System Parameter
C_FAMILY : string := "virtex6";
-- -- AXI Parameters
C_S_AXI_PROTOCOL : string := "AXI4";
C_S_AXI_ID_WIDTH : integer range 1 to 16 := 4;
C_S_AXI_ADDR_WIDTH : integer := 13;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32
);
port (
-- -- AXI Global System Signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
-- -- AXI Write Address Channel Signals
S_AXI_AWID : in std_logic_vector((C_S_AXI_ID_WIDTH-1) downto 0);
S_AXI_AWADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
-- -- AXI Write Channel Signals
S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_WSTRB : in std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
S_AXI_WLAST : in std_logic;
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
-- -- AXI Write Response Channel Signals
S_AXI_BID : out std_logic_vector((C_S_AXI_ID_WIDTH-1) downto 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
-- -- AXI Read Address Channel Signals
S_AXI_ARID : in std_logic_vector((C_S_AXI_ID_WIDTH-1) downto 0);
S_AXI_ARADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
-- -- AXI Read Data Channel Signals
S_AXI_RID : out std_logic_vector((C_S_AXI_ID_WIDTH-1) downto 0);
S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic;
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
IP2Bus_Data : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0 );
IP2Bus_Error : in std_logic;
Bus2IP_Addr : out std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
Bus2IP_Data : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
Bus2IP_BE : out std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1)downto 0);
Bus2IP_Burst : out std_logic;
Bus2IP_RdCE : out std_logic;
Bus2IP_WrCE : out std_logic
);
end entity axi_interface;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture rtl of axi_interface is
-----------------------------------------------------------------------------
-- Constant Declarations
-----------------------------------------------------------------------------
constant ZEROES : std_logic_vector := X"00000000";
constant RST_ACTIVE : std_logic := '0';
-----------------------------------------------------------------------------
-- Signal and Type Declarations
-----------------------------------------------------------------------------
signal bus2ip_addr_i : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal wid : std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
signal rid : std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
signal read_burst_cntr : std_logic_vector(7 downto 0);
signal bvalid : std_logic;
signal rvalid : std_logic;
signal read_req : std_logic;
signal write_req : std_logic;
signal awready_i : std_logic;
signal arready_i : std_logic;
signal arready_i1 : std_logic;
signal arready_i2 : std_logic;
signal s_axi_rlast_i : std_logic;
signal read_burst_length : std_logic_vector(7 downto 0);
signal rd_burst : std_logic;
signal rd_last : std_logic;
signal read_req_d1 : std_logic;
signal read_req_re : std_logic;
signal bus2ip_rdce_i : std_logic;
signal bus2ip_rdce_i_d1 : std_logic;
signal IP2Bus_Data_sampled: std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0 );
signal read_in_prog, write_in_prog : std_logic;
signal read_complete, write_complete : std_logic;
-----------------------------------------------------------------------------
-- Begin Architecture
-----------------------------------------------------------------------------
begin
-- AXI signal assignment
S_AXI_BRESP <= "00";
S_AXI_BVALID <= bvalid;
-- S_AXI_RDATA <= IP2Bus_Data;
--S_AXI_RVALID <= rvalid;
S_AXI_RRESP <= "00";
-- IPIC signal assignment
Bus2IP_Addr <= bus2ip_addr_i;
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_RdCE <= bus2ip_rdce_i;
Bus2IP_BE <= S_AXI_WSTRB;
Bus2IP_Burst <= '0';
AXI4_RDATA_GEN : if (C_S_AXI_PROTOCOL = "AXI4") generate
AXI_READ_OUTPUT_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
S_AXI_RDATA <= (others =>'0');
elsif S_AXI_RREADY = '1' then
S_AXI_RDATA <= IP2Bus_Data;
end if;
end if;
end process AXI_READ_OUTPUT_P;
end generate AXI4_RDATA_GEN;
AXI4LITE_RDATA_GEN : if (C_S_AXI_PROTOCOL = "AXI4LITE") generate
S_AXI_RDATA <= IP2Bus_Data_sampled;
end generate AXI4LITE_RDATA_GEN;
-- AWREADY is enabled only if valid write request and no read request
--awready_i <= (not write_req) and not (S_AXI_ARVALID or read_req or rvalid);
-- ARREADY is enabled only if valid read request and no current write request
--arready_i <= (not read_req) and not (write_req);
-----------------------------------------------------------------------------
-- Generate AXI4-MM interface if (C_S_AXI_PROTOCOL="AXI4")
-----------------------------------------------------------------------------
AXI4_MM_IF_GEN : if (C_S_AXI_PROTOCOL = "AXI4") generate
S_AXI_AWREADY <= awready_i;
S_AXI_WREADY <= write_req;
S_AXI_ARREADY <= arready_i;
Bus2IP_WrCE <= S_AXI_WVALID and write_req;
-- -----------------------------------------------------------------------
-- Process AXI_AWREADY_P to generate Write request on the IPIC
-- -----------------------------------------------------------------------
AXI_AWREADY_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
awready_i <='0';
elsif (S_AXI_AWVALID = '1' and awready_i = '1') then
awready_i <= '0';
else
awready_i <= (not write_req) and not (S_AXI_ARVALID or read_req or rvalid);
end if;
end if;
end process AXI_AWREADY_P;
-- -----------------------------------------------------------------------
-- Process AXI_ARREADY_P to generate Write request on the IPIC
-- -----------------------------------------------------------------------
AXI_ARREADY_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
arready_i <='0';
elsif (S_AXI_ARVALID = '1' and arready_i = '1') then
arready_i <= '0';
else
arready_i <= (not read_req) and not (S_AXI_AWVALID or write_req);
end if;
end if;
end process AXI_ARREADY_P;
-- -----------------------------------------------------------------------
-- Process AXI_READ_OUTPUT_P to generate Write request on the IPIC
-- -----------------------------------------------------------------------
--AXI_READ_OUTPUT_P: process (S_AXI_ACLK) is
--begin
-- if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
-- if (S_AXI_ARESETN=RST_ACTIVE) then
-- S_AXI_RDATA <= (others =>'0');
-- S_AXI_RVALID <='0';
-- elsif S_AXI_RREADY = '1' then
-- S_AXI_RDATA <= IP2Bus_Data;
-- S_AXI_RVALID <= rvalid;
-- end if;
-- end if;
--end process AXI_READ_OUTPUT_P;
AXI_READ_VALID_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
S_AXI_RVALID <='0';
elsif S_AXI_RREADY = '1' then
S_AXI_RVALID <= rvalid;
end if;
end if;
end process AXI_READ_VALID_P;
AXI_READ_CE_DELAY_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
bus2ip_rdce_i_d1 <= '0';
else
bus2ip_rdce_i_d1 <= bus2ip_rdce_i;
end if;
end if;
end process AXI_READ_CE_DELAY_P;
AXI_READ_OUTPUT_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
IP2Bus_Data_sampled <= (others =>'0');
elsif bus2ip_rdce_i_d1 = '1' then
IP2Bus_Data_sampled <= IP2Bus_Data;
end if;
end if;
end process AXI_READ_OUTPUT_P;
-- AXI4 outputs
S_AXI_BID <= wid;
S_AXI_RID <= rid;
--S_AXI_RLAST <= s_axi_rlast_i and rvalid;
-- Read burst
rd_burst <= or_reduce(read_burst_length);
rd_last <= (s_axi_rlast_i and rd_burst) or (s_axi_rlast_i and S_AXI_RREADY);
s_axi_rlast_i <= '1' when read_burst_cntr = "00000000" else '0';
-- Read request on IPIC
bus2ip_rdce_i <= read_req_re or (read_req and S_AXI_RREADY);
-- AXI/IPIC Read request signal generation
read_req_re <= read_req and not read_req_d1;
-- -----------------------------------------------------------------------
-- Process AXI_READ_OUTPUT_P to generate Write request on the IPIC
-- -----------------------------------------------------------------------
AXI_READ_LAST_OUTPUT_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
S_AXI_RLAST <= '0';
elsif S_AXI_RREADY = '1' then
S_AXI_RLAST <= s_axi_rlast_i and rvalid;
end if;
end if;
end process AXI_READ_LAST_OUTPUT_P;
-- -----------------------------------------------------------------------
-- Process WRITE_REQUEST_P to generate Write request on the IPIC
-- -----------------------------------------------------------------------
WRITE_REQUEST_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
write_req <= '0';
elsif (S_AXI_AWVALID = '1' and awready_i = '1') then
write_req <= '1';
elsif (S_AXI_WVALID = '1' and S_AXI_WLAST = '1') then
write_req <= '0';
else
write_req <= write_req;
end if;
end if;
end process WRITE_REQUEST_P;
-- -----------------------------------------------------------------------
-- Process READ_REQUEST_P to generate read request
-- -----------------------------------------------------------------------
READ_REQUEST_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
read_req <= '0';
elsif (S_AXI_ARVALID = '1' and arready_i = '1') then
read_req <= '1';
elsif (s_axi_rlast_i = '1') then
read_req <= '0';
end if;
end if;
end process READ_REQUEST_P;
-- -----------------------------------------------------------------------
-- Process ADDR_GEN_P to generate bus2ip_addr for read/write
-- -----------------------------------------------------------------------
ADDR_GEN_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
bus2ip_addr_i <= (others=>'0');
elsif (S_AXI_ARVALID = '1' and arready_i = '1') then
bus2ip_addr_i <= S_AXI_ARADDR;
elsif (bus2ip_rdce_i='1' and rd_burst='1') then
bus2ip_addr_i <= bus2ip_addr_i + 4;
elsif (S_AXI_AWVALID = '1' and awready_i = '1') then
bus2ip_addr_i <= S_AXI_AWADDR;
elsif (S_AXI_WVALID = '1' and write_req='1') then
bus2ip_addr_i <= bus2ip_addr_i + 4;
end if;
end if;
end process ADDR_GEN_P;
-- -----------------------------------------------------------------------
-- Process WRITE_ID_P to generate Write response ID on AXI
-- -----------------------------------------------------------------------
WRITE_ID_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
wid <= (others=>'0');
elsif (S_AXI_AWVALID = '1' and awready_i = '1') then
wid <= S_AXI_AWID;
end if;
end if;
end process WRITE_ID_P;
-- -----------------------------------------------------------------------
-- Process WRITE_BVALID_P to generate Write Response valid
-- -----------------------------------------------------------------------
WRITE_BVALID_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
bvalid <= '0';
elsif (S_AXI_WLAST = '1' and write_req = '1' and S_AXI_WVALID = '1') then
bvalid <= '1';
elsif (S_AXI_BREADY = '1') then
bvalid <= '0';
end if;
end if;
end process WRITE_BVALID_P;
-- -----------------------------------------------------------------------
-- Process READ_ID_P to generate read ID
-- -----------------------------------------------------------------------
READ_ID_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
rid <= (others=>'0');
elsif (S_AXI_ARVALID = '1' and arready_i = '1') then
rid <= S_AXI_ARID;
end if;
end if;
end process READ_ID_P;
-- -----------------------------------------------------------------------
-- Process READ_BURST_CNTR_P to generate rdlast signal after completion
-- of burst
-- -----------------------------------------------------------------------
READ_BURST_CNTR_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
read_burst_cntr <= (others=>'0');
elsif (S_AXI_ARVALID = '1' and arready_i = '1') then
read_burst_cntr <= S_AXI_ARLEN;
elsif (rvalid = '1' and S_AXI_RREADY='1') then
read_burst_cntr <= read_burst_cntr-'1';
end if;
end if;
end process READ_BURST_CNTR_P;
-- -----------------------------------------------------------------------
-- Process READ_BURST_LENGTH_P to latch the burst length for read xfer
-- -----------------------------------------------------------------------
READ_BURST_LENGTH_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
read_burst_length <= (others=>'0');
elsif (S_AXI_ARVALID = '1' and arready_i = '1') then
read_burst_length <= S_AXI_ARLEN;
end if;
end if;
end process READ_BURST_LENGTH_P;
-- -----------------------------------------------------------------------
-- Process READ_RVALID_P to generate Read valid
-- -----------------------------------------------------------------------
READ_RVALID_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
rvalid <= '0';
elsif (s_axi_rlast_i = '1' and S_AXI_RREADY='1' and rd_burst='1') then
rvalid <= '0';
elsif (read_req = '1') then
rvalid <= '1';
elsif (s_axi_rlast_i = '1' and S_AXI_RREADY='1') then
rvalid <= '0';
end if;
end if;
end process READ_RVALID_P;
-- -----------------------------------------------------------------------
-- Process READ_REQUEST_REG_P to generate Read request on IPIC
-- -----------------------------------------------------------------------
READ_REQUEST_REG_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
read_req_d1 <= '0';
else
read_req_d1 <= read_req;
end if;
end if;
end process READ_REQUEST_REG_P;
--------------------------
end generate AXI4_MM_IF_GEN;
---------------------------
-----------------------------------------------------------------------------
-- Generate AXI4-Lite interface if (C_S_AXI_PROTOCOL="AXI4LITE")
-----------------------------------------------------------------------------
AXI4_LITE_IF_GEN : if (C_S_AXI_PROTOCOL = "AXI4LITE") generate
S_AXI_AWREADY <= awready_i;
S_AXI_WREADY <= awready_i;
S_AXI_ARREADY <= arready_i;
Bus2IP_WrCE <= S_AXI_WVALID and write_in_prog; --and write_req;
-- -----------------------------------------------------------------------
-- Process AXI_AWREADY_P to generate Write request on the IPIC
-- -----------------------------------------------------------------------
AXI_AWREADY_P1: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
write_in_prog <='0';
read_in_prog <='0';
elsif ((rvalid = '1' and S_AXI_RREADY = '1') or (bvalid = '1' and S_AXI_BREADY = '1')) then -- and write_complete = '1') then
-- elsif (read_complete = '1' or (bvalid = '1' and S_AXI_BREADY = '1')) then -- and write_complete = '1') then
write_in_prog <='0';
read_in_prog <='0';
elsif (S_AXI_ARVALID = '1' and write_in_prog = '0') then
read_in_prog <='1';
elsif ((S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') and read_in_prog = '0') then
write_in_prog <='1';
end if;
end if;
end process AXI_AWREADY_P1;
-- -----------------------------------------------------------------------
-- Process AXI_AWREADY_P to generate Write request on the IPIC
-- -----------------------------------------------------------------------
AXI_AWREADY_P2: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
awready_i <='0';
elsif (S_AXI_WVALID = '1' and write_in_prog = '1' and awready_i = '0') then
awready_i <= '1';
else
awready_i <= '0'; --(not write_req) and not (S_AXI_ARVALID or read_req or rvalid);
end if;
end if;
end process AXI_AWREADY_P2;
-- -----------------------------------------------------------------------
-- Process WRITE_BVALID_P to generate Write Response valid
-- -----------------------------------------------------------------------
WRITE_BVALID_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
bvalid <= '0';
elsif (awready_i = '1') then
bvalid <= '1';
elsif (S_AXI_BREADY = '1') then
bvalid <= '0';
end if;
end if;
end process WRITE_BVALID_P;
WRITE_BVALID_P2: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
write_complete <= '0';
elsif (bvalid = '1' and S_AXI_BREADY = '1' and write_complete = '0') then
write_complete <= '1';
else
write_complete <= '0';
end if;
end if;
end process WRITE_BVALID_P2;
-- -----------------------------------------------------------------------
-- Process AXI_ARREADY_P to generate Write request on the IPIC
-- -----------------------------------------------------------------------
AXI_ARREADY_P1: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
arready_i1 <='0';
elsif (read_in_prog = '1') then -- and rvalid = '1') then --S_AXI_ARVALID = '1' and read_complete = '1' and arready_i = '0') then
arready_i1 <= '1';
else
arready_i1 <= '0';
end if;
end if;
end process AXI_ARREADY_P1;
AXI_ARREADY_P2: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
arready_i2 <='0';
else
arready_i2 <= arready_i1;
end if;
end if;
end process AXI_ARREADY_P2;
arready_i <= arready_i1 and (not arready_i2);
-- AXI_READ_VALID_P1: process (S_AXI_ACLK) is
-- begin
-- if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
-- if (S_AXI_ARESETN=RST_ACTIVE) then
-- S_AXI_RVALID <='0';
-- elsif S_AXI_RREADY = '1' then
S_AXI_RVALID <= rvalid;
-- end if;
-- end if;
-- end process AXI_READ_VALID_P1;
AXI_READ_CE_DELAY_P1: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
bus2ip_rdce_i_d1 <= '0';
else
bus2ip_rdce_i_d1 <= bus2ip_rdce_i;
end if;
end if;
end process AXI_READ_CE_DELAY_P1;
AXI_READ_OUTPUT_P1: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
IP2Bus_Data_sampled <= (others =>'0');
elsif bus2ip_rdce_i_d1 = '1' then
IP2Bus_Data_sampled <= IP2Bus_Data;
end if;
end if;
end process AXI_READ_OUTPUT_P1;
-- AXI4 outputs
--S_AXI_BID <= (others => '0');
--S_AXI_RID <= (others => '0');
S_AXI_RLAST <= rvalid;
S_AXI_BID <= wid;
S_AXI_RID <= rid;
wid <= (others => '0');
rid <= (others => '0');
-- -----------------------------------------------------------------------
-- Process WRITE_REQUEST_P to generate Write request on the IPIC
-- -----------------------------------------------------------------------
-- WRITE_REQUEST_P: process (S_AXI_ACLK) is
-- begin
-- if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
-- if (S_AXI_ARESETN=RST_ACTIVE) then
-- write_req <= '0';
-- elsif (S_AXI_AWVALID = '1' and awready_i = '1') then
-- write_req <= '1';
-- elsif (write_req = '1' and S_AXI_WVALID = '1') then
-- write_req <= '0';
-- else
-- write_req <= write_req;
-- end if;
-- end if;
-- end process WRITE_REQUEST_P;
-- -----------------------------------------------------------------------
-- Process READ_REQUEST_P to generate read request
-- -----------------------------------------------------------------------
READ_REQUEST_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then -- or read_in_prog = '0') then
read_req <= '0';
elsif (S_AXI_ARVALID = '1' and bus2ip_rdce_i_d1 = '0') then
read_req <= '1';
elsif (S_AXI_RREADY = '1') then
read_req <= '0';
end if;
end if;
end process READ_REQUEST_P;
-- -----------------------------------------------------------------------
-- Process ADDR_GEN_P to generate bus2ip_addr for read/write
-- -----------------------------------------------------------------------
ADDR_GEN_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
bus2ip_addr_i <= (others=>'0');
elsif (S_AXI_ARVALID = '1' and write_in_prog = '0') then --read_in_prog = '1') then
bus2ip_addr_i <= S_AXI_ARADDR;
elsif (S_AXI_AWVALID = '1' and read_in_prog = '0') then --write_in_prog = '1') then
bus2ip_addr_i <= S_AXI_AWADDR;
end if;
end if;
end process ADDR_GEN_P;
-- -----------------------------------------------------------------------
-- Process READ_RVALID_P to generate Read valid
-- -----------------------------------------------------------------------
READ_RVALID_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
rvalid <= '0';
elsif (S_AXI_RREADY='1' and rvalid = '1') then
rvalid <= '0';
elsif (read_req = '1' and bus2ip_rdce_i_d1 = '1') then
rvalid <= '1';
end if;
end if;
end process READ_RVALID_P;
READ_RVALID_P1: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN=RST_ACTIVE) then
read_complete <= '0';
elsif ((rvalid = '1' and S_AXI_RREADY = '1')) then --(arready_i = '1') then
read_complete <= '1';
else
read_complete <= '0';
end if;
end if;
end process READ_RVALID_P1;
-- -- -----------------------------------------------------------------------
-- -- Process WRITE_ID_P to generate Write response ID on AXI
-- -- -----------------------------------------------------------------------
-- WRITE_ID_P: process (S_AXI_ACLK) is
-- begin
-- if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
-- if (S_AXI_ARESETN=RST_ACTIVE) then
-- wid <= (others=>'0');
-- elsif (S_AXI_AWVALID = '1' and awready_i = '1') then
-- wid <= S_AXI_AWID;
-- end if;
-- end if;
-- end process WRITE_ID_P;
--
-- -- Process READ_ID_P to generate read ID
-- -- -----------------------------------------------------------------------
-- READ_ID_P: process (S_AXI_ACLK) is
-- begin
-- if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
-- if (S_AXI_ARESETN=RST_ACTIVE) then
-- rid <= (others=>'0');
-- elsif (S_AXI_ARVALID = '1' and arready_i = '1') then
-- rid <= S_AXI_ARID;
-- end if;
-- end if;
-- end process READ_ID_P;
-- Read request on IPIC
bus2ip_rdce_i <= read_in_prog; --read_req;
--------------------------
end generate AXI4_LITE_IF_GEN;
---------------------------
end architecture rtl;
--
-------------------------------------------------------------------------------
-- axi_ethernetlite - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename : axi_ethernetlite.vhd
-- Version : v2.0
-- Description : This is the top level wrapper file for the Ethernet
-- Lite function It provides a 10 or 100 Mbs full or half
-- duplex Ethernet bus with an interface to an AXI Interface.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-- PVK 07/29/2010 First Version
-- ^^^^^^
-- Removed ARLOCK and AWLOCK, AWPROT, ARPROT signals from the list.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0_9 library is used for axi_ethernetlite_v3_0_9
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0_9;
use axi_ethernetlite_v3_0_9.mac_pkg.all;
use axi_ethernetlite_v3_0_9.axi_interface;
use axi_ethernetlite_v3_0_9.all;
-------------------------------------------------------------------------------
library lib_cdc_v1_0_2;
use lib_cdc_v1_0_2.all;
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
--
-- C_FAMILY -- Target device family
-- C_SELECT_XPM -- Selects XPM if set to 1 else selects BMG
-- C_S_AXI_ACLK_PERIOD_PS -- The period of the AXI clock in ps
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width - allowed value - 32 only
-- C_S_AXI_DATA_WIDTH -- AXI data bus width - allowed value - 32 or 64 only
-- C_S_AXI_ID_WIDTH -- AXI Identification TAG width - 1 to 16
-- C_S_AXI_PROTOCOL -- AXI protocol type
--
-- C_DUPLEX -- 1 = Full duplex, 0 = Half duplex
-- C_TX_PING_PONG -- 1 = Ping-pong memory used for transmit buffer
-- 0 = Pong memory not used for transmit buffer
-- C_RX_PING_PONG -- 1 = Ping-pong memory used for receive buffer
-- 0 = Pong memory not used for receive buffer
-- C_INCLUDE_MDIO -- 1 = Include MDIO Innterface,
-- 0 = No MDIO Interface
-- C_INCLUDE_INTERNAL_LOOPBACK -- 1 = Include Internal Loopback logic,
-- 0 = Internal Loopback logic disabled
-- C_INCLUDE_GLOBAL_BUFFERS -- 1 = Include global buffers for PHY clocks
-- 0 = Use normal input buffers for PHY clocks
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset - active low
-- -- interrupts
-- ip2intc_irpt -- Interrupt to processor
--==================================
-- axi write address Channel Signals
--==================================
-- s_axi_awid -- AXI Write Address ID
-- s_axi_awaddr -- AXI Write address - 32 bit
-- s_axi_awlen -- AXI Write Data Length
-- s_axi_awsize -- AXI Burst Size - allowed values
-- -- 000 - byte burst
-- -- 001 - half word
-- -- 010 - word
-- -- 011 - double word
-- -- NA for all remaining values
-- s_axi_awburst -- AXI Burst Type
-- -- 00 - Fixed
-- -- 01 - Incr
-- -- 10 - Wrap
-- -- 11 - Reserved
-- s_axi_awcache -- AXI Cache Type
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
--===============================
-- axi write data channel Signals
--===============================
-- s_axi_wdata -- AXI Write data width
-- s_axi_wstrb -- AXI Write strobes
-- s_axi_wlast -- AXI Last write indicator signal
-- s_axi_wvalid -- AXI Write valid
-- s_axi_wready -- AXI Write ready
--================================
-- axi write data response Signals
--================================
-- s_axi_bid -- AXI Write Response channel number
-- s_axi_bresp -- AXI Write response
-- -- 00 - Okay
-- -- 01 - ExOkay
-- -- 10 - Slave Error
-- -- 11 - Decode Error
-- s_axi_bvalid -- AXI Write response valid
-- s_axi_bready -- AXI Response ready
--=================================
-- axi read address Channel Signals
--=================================
-- s_axi_arid -- AXI Read ID
-- s_axi_araddr -- AXI Read address
-- s_axi_arlen -- AXI Read Data length
-- s_axi_arsize -- AXI Read Size
-- s_axi_arburst -- AXI Read Burst length
-- s_axi_arcache -- AXI Read Cache
-- s_axi_arprot -- AXI Read Protection
-- s_axi_rvalid -- AXI Read valid
-- s_axi_rready -- AXI Read ready
--==============================
-- axi read data channel Signals
--==============================
-- s_axi_rid -- AXI Read Channel ID
-- s_axi_rdata -- AXI Read data
-- s_axi_rresp -- AXI Read response
-- s_axi_rlast -- AXI Read Data Last signal
-- s_axi_rvalid -- AXI Read address valid
-- s_axi_rready -- AXI Read address ready
--
-- -- ethernet
-- phy_tx_clk -- Ethernet tranmit clock
-- phy_rx_clk -- Ethernet receive clock
-- phy_crs -- Ethernet carrier sense
-- phy_dv -- Ethernet receive data valid
-- phy_rx_data -- Ethernet receive data
-- phy_col -- Ethernet collision indicator
-- phy_rx_er -- Ethernet receive error
-- phy_rst_n -- Ethernet PHY Reset
-- phy_tx_en -- Ethernet transmit enable
-- phy_tx_data -- Ethernet transmit data
-- phy_mdio_i -- Ethernet PHY MDIO data input
-- phy_mdio_o -- Ethernet PHY MDIO data output
-- phy_mdio_t -- Ethernet PHY MDIO data 3-state control
-- phy_mdc -- Ethernet PHY management clock
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity axi_ethernetlite is
generic
(
C_FAMILY : string := "virtex6";
C_SELECT_XPM : integer := 1;
C_INSTANCE : string := "axi_ethernetlite_inst";
C_S_AXI_ACLK_PERIOD_PS : integer := 10000;
C_S_AXI_ADDR_WIDTH : integer := 13;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ID_WIDTH : integer := 4;
C_S_AXI_PROTOCOL : string := "AXI4";
C_INCLUDE_MDIO : integer := 1;
C_INCLUDE_INTERNAL_LOOPBACK : integer := 0;
C_INCLUDE_GLOBAL_BUFFERS : integer := 1;
C_DUPLEX : integer range 0 to 1:= 1;
C_TX_PING_PONG : integer range 0 to 1:= 0;
C_RX_PING_PONG : integer range 0 to 1:= 0
);
port
(
-- -- AXI Slave signals ------------------------------------------------------
-- -- AXI Global System Signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
ip2intc_irpt : out std_logic;
-- -- axi slave burst Interface
-- -- axi write address Channel Signals
s_axi_awid : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_awaddr : in std_logic_vector(12 downto 0); -- (C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awlen : in std_logic_vector(7 downto 0);
s_axi_awsize : in std_logic_vector(2 downto 0);
s_axi_awburst : in std_logic_vector(1 downto 0);
s_axi_awcache : in std_logic_vector(3 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
-- -- axi write data Channel Signals
s_axi_wdata : in std_logic_vector(31 downto 0); -- (C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
--(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
s_axi_wlast : in std_logic;
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
-- -- axi write response Channel Signals
s_axi_bid : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
-- -- axi read address Channel Signals
s_axi_arid : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_araddr : in std_logic_vector(12 downto 0); -- (C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arlen : in std_logic_vector(7 downto 0);
s_axi_arsize : in std_logic_vector(2 downto 0);
s_axi_arburst : in std_logic_vector(1 downto 0);
s_axi_arcache : in std_logic_vector(3 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
-- -- axi read data Channel Signals
s_axi_rid : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_rdata : out std_logic_vector(31 downto 0); -- (C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- -- Ethernet Interface
phy_tx_clk : in std_logic;
phy_rx_clk : in std_logic;
phy_crs : in std_logic;
phy_dv : in std_logic;
phy_rx_data : in std_logic_vector (3 downto 0);
phy_col : in std_logic;
phy_rx_er : in std_logic;
phy_rst_n : out std_logic;
phy_tx_en : out std_logic;
phy_tx_data : out std_logic_vector (3 downto 0);
phy_mdio_i : in std_logic;
phy_mdio_o : out std_logic;
phy_mdio_t : out std_logic;
phy_mdc : out std_logic
);
-- XST attributes
-- Fan-out attributes for XST
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of s_axi_aclk : signal is "10000";
attribute MAX_FANOUT of s_axi_aresetn : signal is "10000";
--Psfutil attributes
attribute ASSIGNMENT : string;
attribute ADDRESS : string;
attribute PAIR : string;
end axi_ethernetlite;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_ethernetlite is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
--Parameters captured for webtalk
-- C_FAMILY
-- C_S_AXI_ACLK_PERIOD_PS
-- C_S_AXI_DATA_WIDTH
-- C_S_AXI_PROTOCOL
-- C_INCLUDE_MDIO
-- C_INCLUDE_INTERNAL_LOOPBACK
-- C_INCLUDE_GLOBAL_BUFFERS
-- C_DUPLEX
-- C_TX_PING_PONG
-- C_RX_PING_PONG
-- constant C_CORE_GENERATION_INFO : string := C_INSTANCE & ",axi_ethernetlite,{"
-- & "c_family=" & C_FAMILY
-- & ",C_INSTANCE = " & C_INSTANCE
-- & ",c_s_axi_protocol=" & C_S_AXI_PROTOCOL
-- & ",c_s_axi_aclk_period_ps=" & integer'image(C_S_AXI_ACLK_PERIOD_PS)
-- & ",c_s_axi_data_width=" & integer'image(C_S_AXI_DATA_WIDTH)
-- & ",c_include_mdio=" & integer'image(C_INCLUDE_MDIO)
-- & ",c_include_internal_loopback=" & integer'image(C_INCLUDE_INTERNAL_LOOPBACK)
-- & ",c_include_global_buffers=" & integer'image(C_INCLUDE_GLOBAL_BUFFERS)
-- & ",c_duplex=" & integer'image(C_DUPLEX)
-- & ",c_tx_ping_pong=" & integer'image(C_TX_PING_PONG)
-- & ",c_rx_ping_pong=" & integer'image(C_RX_PING_PONG)
-- & "}";
--
-- attribute CORE_GENERATION_INFO : string;
-- attribute CORE_GENERATION_INFO of imp : architecture is C_CORE_GENERATION_INFO;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant NODE_MAC : bit_vector := x"00005e00FACE";
-------------------------------------------------------------------------------
-- Signal declaration Section
-------------------------------------------------------------------------------
signal phy_rx_clk_i : std_logic;
signal phy_tx_clk_i : std_logic;
signal phy_rx_clk_ib : std_logic;
signal phy_tx_clk_ib : std_logic;
signal phy_rx_data_i : std_logic_vector(3 downto 0);
signal phy_tx_data_i : std_logic_vector(3 downto 0);
signal phy_tx_data_i_cdc : std_logic_vector(3 downto 0);
signal phy_dv_i : std_logic;
signal phy_rx_er_i : std_logic;
signal phy_tx_en_i : std_logic;
signal phy_tx_en_i_cdc : std_logic;
signal Loopback : std_logic;
signal phy_rx_data_in : std_logic_vector (3 downto 0);
signal phy_rx_data_in_cdc : std_logic_vector (3 downto 0);
signal phy_dv_in : std_logic;
signal phy_dv_in_cdc : std_logic;
signal phy_rx_data_reg : std_logic_vector(3 downto 0);
signal phy_rx_er_reg : std_logic;
signal phy_dv_reg : std_logic;
signal phy_tx_clk_core : std_logic;
signal phy_rx_clk_core : std_logic;
-- IPIC Signals
signal temp_Bus2IP_Addr: std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal bus2ip_addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal Bus2IP_Data : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal bus2ip_rdce : std_logic;
signal bus2ip_wrce : std_logic;
signal ip2bus_data : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal bus2ip_burst : std_logic;
signal bus2ip_be : std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
signal bus_rst_tx_sync_core : std_logic;
--signal bus_rst_rx_sync : std_logic;
signal bus_rst_rx_sync_core : std_logic;
signal bus_rst : std_logic;
signal ip2bus_errack : std_logic;
component FDRE
port
(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component BUFG
port (
O : out std_ulogic;
I : in std_ulogic := '0'
);
end component;
component BUFGMUX
port (
O : out std_ulogic;
I0 : in std_ulogic := '0';
I1 : in std_ulogic := '0';
S : in std_ulogic
);
end component;
component BUF
port(
O : out std_ulogic;
I : in std_ulogic
);
end component;
COMPONENT IBUF
PORT(i : IN std_logic;
o : OUT std_logic);
END COMPONENT;
-- attribute IOB : string;
begin -- this is the begin between declarations and architecture body
-- PHY Reset
PHY_rst_n <= S_AXI_ARESETN ;
-- Bus Reset
bus_rst <= not S_AXI_ARESETN ;
BUS_RST_RX_SYNC_CORE_I: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => bus_rst,
prmry_ack => open,
scndry_out => bus_rst_rx_sync_core,
scndry_aclk => phy_rx_clk_core,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
BUS_RST_TX_SYNC_CORE_I: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => bus_rst,
prmry_ack => open,
scndry_out => bus_rst_tx_sync_core,
scndry_aclk => phy_tx_clk_core,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
----------------------------------------------------------------------------
-- LOOPBACK_GEN :- Include MDIO interface if the parameter
-- C_INCLUDE_INTERNAL_LOOPBACK = 1
----------------------------------------------------------------------------
LOOPBACK_GEN: if C_INCLUDE_INTERNAL_LOOPBACK = 1 generate
begin
-------------------------------------------------------------------------
-- INCLUDE_BUFG_GEN :- Include Global Buffer for PHY clocks
-- C_INCLUDE_GLOBAL_BUFFERS = 1
-------------------------------------------------------------------------
INCLUDE_BUFG_GEN: if C_INCLUDE_GLOBAL_BUFFERS = 1 generate
begin
-------------------------------------------------------------------------
-- IBUF for TX/RX clocks
-------------------------------------------------------------------------
TX_IBUF_INST: IBUF
port map (
O => phy_tx_clk_ib,
I => PHY_tx_clk
);
RX_IBUF_INST: IBUF
port map (
O => phy_rx_clk_ib,
I => PHY_rx_clk
);
-------------------------------------------------------------------------
-- BUFG for TX clock
-------------------------------------------------------------------------
CLOCK_BUFG_TX: BUFG
port map (
O => phy_tx_clk_core, --[out]
I => PHY_tx_clk_ib --[in]
);
-------------------------------------------------------------------------
-- BUFGMUX for clock muxing in Loopback mode
-------------------------------------------------------------------------
CLOCK_MUX: BUFGMUX
port map (
O => phy_rx_clk_core, --[out]
I0 => PHY_rx_clk_ib, --[in]
I1 => phy_tx_clk_ib, --[in]
S => Loopback --[in]
);
end generate INCLUDE_BUFG_GEN;
-------------------------------------------------------------------------
-- NO_BUFG_GEN :- Dont include Global Buffer for PHY clocks
-- C_INCLUDE_GLOBAL_BUFFERS = 0
-------------------------------------------------------------------------
NO_BUFG_GEN: if C_INCLUDE_GLOBAL_BUFFERS = 0 generate
begin
phy_tx_clk_core <= PHY_tx_clk;
-------------------------------------------------------------------------
-- BUFGMUX for clock muxing in Loopback mode
-------------------------------------------------------------------------
CLOCK_MUX: BUFGMUX
port map (
O => phy_rx_clk_core, --[out]
I0 => PHY_rx_clk, --[in]
I1 => phy_tx_clk_core, --[in]
S => Loopback --[in]
);
end generate NO_BUFG_GEN;
-------------------------------------------------------------------------
-- Internal Loopback generation logic
-------------------------------------------------------------------------
phy_rx_data_in <= phy_tx_data_i when Loopback = '1' else
phy_rx_data_reg;
phy_dv_in <= phy_tx_en_i when Loopback = '1' else
phy_dv_reg;
-- No receive error is generated in internal loopback
phy_rx_er_i <= '0' when Loopback = '1' else
phy_rx_er_reg;
-- Transmit and Receive clocks
phy_tx_clk_i <= phy_tx_clk_core;--not(phy_tx_clk_core);
phy_rx_clk_i <= phy_rx_clk_core;--not(phy_rx_clk_core);
----------------------------------------------------------------------------
-- CDC module for syncing phy_dv_in in rx_clk domain
----------------------------------------------------------------------------
CDC_PHY_DV_IN: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 2
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => phy_dv_in,
prmry_ack => open,
scndry_out => phy_dv_in_cdc,
scndry_aclk => phy_rx_clk_i,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
--BUS_RST_RX_SYNC_I: entity lib_cdc_v1_0_2.cdc_sync
-- generic map (
-- C_CDC_TYPE => 1,
-- C_RESET_STATE => 0,
-- C_SINGLE_BIT => 1,
-- C_FLOP_INPUT => 0,
-- C_VECTOR_WIDTH => 1,
-- C_MTBF_STAGES => 4
-- )
-- port map(
-- prmry_aclk => '1',
-- prmry_resetn => '1',
-- prmry_in => bus_rst,
-- prmry_ack => open,
-- scndry_out => bus_rst_rx_sync,
-- scndry_aclk => phy_rx_clk_i,
-- scndry_resetn => '1',
-- prmry_vect_in => (OTHERS => '0'),
-- scndry_vect_out => open
-- );
-------------------------------------------------------------------------
-- Registering RX signal
-------------------------------------------------------------------------
DV_FF: FDR
port map (
Q => phy_dv_i, --[out]
C => phy_rx_clk_i, --[in]
D => phy_dv_in_cdc, --[in]
R => bus_rst_rx_sync_core); --[in]
----------------------------------------------------------------------------
-- CDC module for syncing phy_rx_data_in in rx_clk domain
----------------------------------------------------------------------------
CDC_PHY_RX_DATA_IN: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 4,
C_MTBF_STAGES => 2
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => '1',
prmry_ack => open,
scndry_out => open,
scndry_aclk => phy_rx_clk_i,
scndry_resetn => '1',
prmry_vect_in => phy_rx_data_in,
scndry_vect_out => phy_rx_data_in_cdc
);
-------------------------------------------------------------------------
-- Registering RX data input with clock mux output
-------------------------------------------------------------------------
RX_REG_GEN: for i in 3 downto 0 generate
begin
RX_FF_LOOP: FDRE
port map (
Q => phy_rx_data_i(i), --[out]
C => phy_rx_clk_i, --[in]
CE => '1', --[in]
D => phy_rx_data_in_cdc(i), --[in]
R => bus_rst_rx_sync_core); --[in]
end generate RX_REG_GEN;
end generate LOOPBACK_GEN;
----------------------------------------------------------------------------
-- NO_LOOPBACK_GEN :- Include MDIO interface if the parameter
-- C_INCLUDE_INTERNAL_LOOPBACK = 0
----------------------------------------------------------------------------
NO_LOOPBACK_GEN: if C_INCLUDE_INTERNAL_LOOPBACK = 0 generate
begin
-------------------------------------------------------------------------
-- INCLUDE_BUFG_GEN :- Include Global Buffer for PHY clocks
-- C_INCLUDE_GLOBAL_BUFFERS = 1
-------------------------------------------------------------------------
INCLUDE_BUFG_GEN: if C_INCLUDE_GLOBAL_BUFFERS = 1 generate
begin
-------------------------------------------------------------------------
-- IBUF for TX/RX clocks
-------------------------------------------------------------------------
TX_IBUF_INST: IBUF
port map (
O => phy_tx_clk_ib,
I => PHY_tx_clk
);
RX_IBUF_INST: IBUF
port map (
O => phy_rx_clk_ib,
I => PHY_rx_clk
);
-------------------------------------------------------------------------
-- BUFG for clock muxing
-------------------------------------------------------------------------
CLOCK_BUFG_TX: BUFG
port map (
O => phy_tx_clk_core, --[out]
I => PHY_tx_clk_ib --[in]
);
-------------------------------------------------------------------------
-- BUFG for clock muxing
-------------------------------------------------------------------------
CLOCK_BUFG_RX: BUFG
port map (
O => phy_rx_clk_core, --[out]
I => PHY_rx_clk_ib --[in]
);
end generate INCLUDE_BUFG_GEN;
-------------------------------------------------------------------------
-- NO_BUFG_GEN :- Dont include Global Buffer for PHY clocks
-- C_INCLUDE_GLOBAL_BUFFERS = 0
-------------------------------------------------------------------------
NO_BUFG_GEN: if C_INCLUDE_GLOBAL_BUFFERS = 0 generate
begin
phy_tx_clk_core <= PHY_tx_clk;
phy_rx_clk_core <= PHY_rx_clk;
end generate NO_BUFG_GEN;
-- Transmit and Receive clocks for core
phy_tx_clk_i <= phy_tx_clk_core;--not(phy_tx_clk_core);
phy_rx_clk_i <= phy_rx_clk_core;--not(phy_rx_clk_core);
-- TX/RX internal signals
phy_rx_data_i <= phy_rx_data_reg;
phy_rx_er_i <= phy_rx_er_reg;
phy_dv_i <= phy_dv_reg;
end generate NO_LOOPBACK_GEN;
----------------------------------------------------------------------------
-- CDC module for syncing phy_tx_en in tx_clk domain
----------------------------------------------------------------------------
CDC_PHY_TX_EN_O: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 2
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => PHY_tx_en_i,
prmry_ack => open,
scndry_out => PHY_tx_en_i_cdc,
scndry_aclk => phy_tx_clk_core,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
----------------------------------------------------------------------------
-- CDC module for syncing phy_tx_data_out in tx_clk domain
----------------------------------------------------------------------------
CDC_PHY_TX_DATA_OUT: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 4,
C_MTBF_STAGES => 2
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => '1',
prmry_ack => open,
scndry_out => open,
scndry_aclk => phy_tx_clk_core,
scndry_resetn => '1',
prmry_vect_in => phy_tx_data_i,
scndry_vect_out => phy_tx_data_i_cdc
);
----------------------------------------------------------------------------
-- Registering the Ethernet data signals
----------------------------------------------------------------------------
IOFFS_GEN: for i in 3 downto 0 generate
-- attribute IOB of RX_FF_I : label is "true";
-- attribute IOB of TX_FF_I : label is "true";
begin
RX_FF_I: FDRE
port map (
Q => phy_rx_data_reg(i), --[out]
C => phy_rx_clk_core, --[in]
CE => '1', --[in]
D => PHY_rx_data(i), --[in]
R => bus_rst_rx_sync_core); --[in]
TX_FF_I: FDRE
port map (
Q => PHY_tx_data(i), --[out]
C => phy_tx_clk_core, --[in]
CE => '1', --[in]
D => phy_tx_data_i_cdc(i), --[in]
R => bus_rst_tx_sync_core); --[in]
end generate IOFFS_GEN;
----------------------------------------------------------------------------
-- Registering the Ethernet control signals
----------------------------------------------------------------------------
IOFFS_GEN2: if(true) generate
-- attribute IOB of DVD_FF : label is "true";
-- attribute IOB of RER_FF : label is "true";
-- attribute IOB of TEN_FF : label is "true";
begin
DVD_FF: FDRE
port map (
Q => phy_dv_reg, --[out]
C => phy_rx_clk_core, --[in]
CE => '1', --[in]
D => PHY_dv, --[in]
R => bus_rst_rx_sync_core); --[in]
RER_FF: FDRE
port map (
Q => phy_rx_er_reg, --[out]
C => phy_rx_clk_core, --[in]
CE => '1', --[in]
D => PHY_rx_er, --[in]
R => bus_rst_rx_sync_core); --[in]
TEN_FF: FDRE
port map (
Q => PHY_tx_en, --[out]
C => phy_tx_clk_core, --[in]
CE => '1', --[in]
D => PHY_tx_en_i_cdc, --[in]
R => bus_rst_tx_sync_core); --[in]
end generate IOFFS_GEN2;
----------------------------------------------------------------------------
-- XEMAC Module
----------------------------------------------------------------------------
XEMAC_I : entity axi_ethernetlite_v3_0_9.xemac
generic map
(
C_FAMILY => C_FAMILY,
C_SELECT_XPM => C_SELECT_XPM,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ACLK_PERIOD_PS => C_S_AXI_ACLK_PERIOD_PS,
C_DUPLEX => C_DUPLEX,
C_RX_PING_PONG => C_RX_PING_PONG,
C_TX_PING_PONG => C_TX_PING_PONG,
C_INCLUDE_MDIO => C_INCLUDE_MDIO,
NODE_MAC => NODE_MAC
)
port map
(
Clk => S_AXI_ACLK,
Rst => bus_rst,
IP2INTC_Irpt => IP2INTC_Irpt,
-- Bus2IP Signals
Bus2IP_Addr => bus2ip_addr,
Bus2IP_Data => bus2ip_data,
Bus2IP_BE => bus2ip_be,
Bus2IP_Burst => bus2ip_burst,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce,
-- IP2Bus Signals
IP2Bus_Data => ip2bus_data,
IP2Bus_Error => ip2bus_errack,
-- EMAC Signals
PHY_tx_clk => phy_tx_clk_i,
PHY_rx_clk => phy_rx_clk_i,
PHY_crs => PHY_crs,
PHY_dv => phy_dv_i,
PHY_rx_data => phy_rx_data_i,
PHY_col => PHY_col,
PHY_rx_er => phy_rx_er_i,
PHY_tx_en => PHY_tx_en_i,
PHY_tx_data => PHY_tx_data_i,
PHY_MDIO_I => phy_mdio_i,
PHY_MDIO_O => phy_mdio_o,
PHY_MDIO_T => phy_mdio_t,
PHY_MDC => phy_mdc,
Loopback => Loopback
);
I_AXI_NATIVE_IPIF: entity axi_ethernetlite_v3_0_9.axi_interface
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH,
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL,
C_FAMILY => C_FAMILY
)
port map (
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWID => s_axi_awid,
S_AXI_AWLEN => s_axi_awlen,
S_AXI_AWSIZE => s_axi_awsize,
S_AXI_AWBURST => s_axi_awburst,
S_AXI_AWCACHE => s_axi_awcache,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WLAST => s_axi_wlast,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BID => s_axi_bid,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARID => s_axi_arid,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARLEN => s_axi_arlen,
S_AXI_ARSIZE => s_axi_arsize,
S_AXI_ARBURST => s_axi_arburst,
S_AXI_ARCACHE => s_axi_arcache,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RID => s_axi_rid,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RLAST => s_axi_rlast,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IP Interconnect (IPIC) port signals ------------------------------------
-- Controls to the IP/IPIF modules
-- IP Interconnect (IPIC) port signals
IP2Bus_Data => ip2bus_data,
IP2Bus_Error => ip2bus_errack,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_Data => bus2ip_data,
Bus2IP_BE => bus2ip_be,
Bus2IP_Burst => bus2ip_burst,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
------------------------------------------------------------------------------------------
end imp;
|
apache-2.0
|
ca9de246e6d8fcc6c0662954ebf051fd
| 0.408035 | 4.573252 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_wiz_0_0_family.vhd
| 1 | 23,033 |
-------------------------------------------------------------------------------
-- system_xadc_wiz_0_0_family.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: system_xadc_wiz_0_0_family.vhd
--
-- Description:
-- This HDL file provides various functions for determining features (such
-- as BRAM types) in the various device families in Xilinx products.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- system_xadc_wiz_0_0_family.vhd
--
-------------------------------------------------------------------------------
-- Revision history
--
-- ??? ?????????? Initial version
-- jam 03/31/2003 added spartan3 to constants and derived function. Added
-- comments to try and explain how the function is used
-- jam 04/01/2003 removed VIRTEX from the derived list for BYZANTIUM,
-- VIRTEX2P, and SPARTAN3. This changes VIRTEX2 to be a
-- base family type, similar to X4K and VIRTEX
-- jam 04/02/2003 add VIRTEX back into the hierarchy of VIRTEX2P, BYZANTIUM
-- and SPARTAN3; add additional comments showing use in
-- VHDL
-- lss 03/24/2004 Added QVIRTEX2, QRVIRTEX2, VIRTEX4
-- flo 03/22/2005 Added SPARTAN3E
-- als 02/23/2006 Added VIRTEX5
-- flo 09/13/2006 Added SPARTAN3A and SPARTAN3A. This may allow
-- legacy designs to support spartan3a and spartan3an in
-- terms of BRAMs. For new work (and maintenence where
-- possible) this package, family, should be dropped in favor
-- of the package, family_support.
--
-- DET 1/17/2008 v3_30_a
-- ~~~~~~
-- - Changed proc_common library version to v3_30_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_H_SP1
-- Added spartan3e
-- @END_CHANGELOG
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
package system_xadc_wiz_0_0_family is
-- constant declarations
constant ANY : string := "any";
constant X4K : string := "x4k";
constant X4KE : string := "x4ke";
constant X4KL : string := "x4kl";
constant X4KEX : string := "x4kex";
constant X4KXL : string := "x4kxl";
constant X4KXV : string := "x4kxv";
constant X4KXLA : string := "x4kxla";
constant SPARTAN : string := "spartan";
constant SPARTANXL : string := "spartanxl";
constant SPARTAN2 : string := "spartan2";
constant SPARTAN2E : string := "spartan2e";
constant VIRTEX : string := "virtex";
constant VIRTEXE : string := "virtexe";
constant VIRTEX2 : string := "virtex2";
constant VIRTEX2P : string := "virtex2p";
constant BYZANTIUM : string := "byzantium";
constant SPARTAN3 : string := "spartan3";
constant QRVIRTEX2 : string := "qrvirtex2";
constant QVIRTEX2 : string := "qvirtex2";
constant VIRTEX4 : string := "virtex4";
constant VIRTEX5 : string := "virtex5";
constant SPARTAN3E : string := "spartan3e";
constant SPARTAN3A : string := "spartan3a";
constant SPARTAN3AN: string := "spartan3an";
-- function declarations
-- derived - provides a means to determine if a family specified in child is
-- the same as, or is a super set of, the family specified in
-- ancestor.
--
-- Typically, child is set to the generic specifying the family type
-- the user wishes to implement the design into (C_FAMILY), and the
-- designer hard codes ancestor to the family type supported by the
-- design. If the design supports multiple family types, then each
-- of those family types would need to be tested against C_FAMILY
-- using this function. An example for the VIRTEX2P hierarchy
-- is shown below:
--
-- VIRTEX2P_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX2P)
-- generate
-- -- logic specific to Virtex2P family
-- end generate VIRTEX2P_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX2P_SPECIFIC_LOGIC_GEN:
-- if not derived(C_FAMILY,VIRTEX2P)
-- generate
--
-- VIRTEX2_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX2)
-- generate
-- -- logic specific to Virtex2 family
-- end generate VIRTEX2_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX2_SPECIFIC_LOGIC_GEN
-- if not derived(C_FAMILY,VIRTEX2)
-- generate
--
-- VIRTEX_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX)
-- generate
-- -- logic specific to Virtex family
-- end generate VIRTEX_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX_SPECIFIC_LOGIC_GEN;
-- if not derived(C_FAMILY,VIRTEX)
-- generate
--
-- ANY_FAMILY_TYPE_LOGIC_GEN:
-- if derived(C_FAMILY,ANY)
-- generate
-- -- logic not specific to any family
-- end generate ANY_FAMILY_TYPE_LOGIC_GEN;
--
-- end generate NON_VIRTEX_SPECIFIC_LOGIC_GEN;
--
-- end generate NON_VIRTEX2_SPECIFIC_LOGIC_GEN;
--
-- end generate NON_VIRTEX2P_SPECIFIC_LOGIC_GEN;
--
-- This function will return TRUE if the family type specified in
-- child is equal to, or a super set of, the family type specified in
-- ancestor, otherwise it returns FALSE.
--
-- The current super sets are defined by the following list, where
-- all family types listed to the right of an item are contained in
-- the super set of that item, for all lines containing that item.
--
-- ANY, X4K, SPARTAN, SPARTANXL
-- ANY, X4K, X4KE, X4KL
-- ANY, X4K, X4KEX, X4KXL, X4KXV, X4KXLA
-- ANY, VIRTEX, SPARTAN2, SPARTAN2E
-- ANY, VIRTEX, VIRTEXE
-- ANY, VIRTEX, VIRTEX2, BYZANTIUM
-- ANY, VIRTEX, VIRTEX2, VIRTEX2P
-- ANY, VIRTEX, VIRTEX2, SPARTAN3
--
-- For exampel, all other family types are contained in the super set
-- for ANY. Stated another way, if the designer specifies ANY
-- for the family type the design supports, then the function will
-- return TRUE for any family type the user wishes to implement the
-- design into.
--
-- if derived(C_FAMILY,ANY) generate ... end generate;
--
-- If the designer specifies VIRTEX2 as the family type supported by
-- the design, then the function will only return TRUE if the user
-- intends to implement the design in VIRTEX2, VIRTEX2P, BYZANTIUM,
-- or SPARTAN3.
--
-- if derived(C_FAMILY,VIRTEX2) generate
-- -- logic that uses VIRTEX2 BRAMs
-- end generate;
--
-- if not derived(C_FAMILY,VIRTEX2) generate
-- -- logic that uses non VIRTEX2 BRAMs
-- end generate;
--
-- Note:
-- The last three lines of the list above were modified from the
-- original to remove VIRTEX from those lines because, from our point
-- of view, VIRTEX2 is different enough from VIRTEX to conclude that
-- it should be its own base family type.
--
-- **************************************************************************
-- WARNING
-- **************************************************************************
-- DO NOT RELY ON THE DERIVED FUNCTION TO PROVIDE DIFFERENTIATION BETWEEN
-- FAMILY TYPES FOR ANYTHING OTHER THAN BRAMS
--
-- Use of the derived function assumes that the designer is not using
-- RLOCs (RLOC'd FIFO's from Coregen, etc.) and that the BRAMs in the
-- derived families are similar. If the designer is using specific
-- elements of a family type, they are responsible for ensuring that
-- those same elements are available in all family types supported by
-- their design, and that the elements function exactly the same in all
-- "similar" families.
--
-- **************************************************************************
--
function derived ( child, ancestor : string ) return boolean;
-- equalIgnoreCase - Returns TRUE if case insensitive string comparison
-- determines that str1 and str2 are equal, otherwise FALSE
function equalIgnoreCase( str1, str2 : string ) return boolean;
-- toLowerCaseChar - Returns the lower case form of char if char is an upper
-- case letter. Otherwise char is returned.
function toLowerCaseChar( char : character ) return character;
end system_xadc_wiz_0_0_family;
package body system_xadc_wiz_0_0_family is
-- True if architecture "child" is derived from, or equal to,
-- the architecture "ancestor".
-- ANY, X4K, SPARTAN, SPARTANXL
-- ANY, X4K, X4KE, X4KL
-- ANY, X4K, X4KEX, X4KXL, X4KXV, X4KXLA
-- ANY, VIRTEX, SPARTAN2, SPARTAN2E
-- ANY, VIRTEX, VIRTEXE
-- ANY, VIRTEX, VIRTEX2, BYZANTIUM
-- ANY, VIRTEX, VIRTEX2, VIRTEX2P
-- ANY, VIRTEX, VIRTEX2, SPARTAN3
function derived ( child, ancestor : string ) return boolean is
variable is_derived : boolean := FALSE;
begin
if equalIgnoreCase( child, VIRTEX ) then -- base family type
if ( equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX2 ) then
if ( equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, QRVIRTEX2 ) then
if ( equalIgnoreCase(ancestor,QRVIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, QVIRTEX2 ) then
if ( equalIgnoreCase(ancestor,QVIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX5 ) then
if ( equalIgnoreCase(ancestor,VIRTEX5) OR
equalIgnoreCase(ancestor,VIRTEX4) OR
equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX4 ) then
if ( equalIgnoreCase(ancestor,VIRTEX4) OR
equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX2P ) then
if ( equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, BYZANTIUM ) then
if ( equalIgnoreCase(ancestor,BYZANTIUM) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEXE ) then
if ( equalIgnoreCase(ancestor,VIRTEXE) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN2 ) then
if ( equalIgnoreCase(ancestor,SPARTAN2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN2E ) then
if ( equalIgnoreCase(ancestor,SPARTAN2E) OR
equalIgnoreCase(ancestor,SPARTAN2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3 ) then
if ( equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3E ) then
if ( equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3A ) then
if ( equalIgnoreCase(ancestor,SPARTAN3A) OR
equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3AN ) then
if ( equalIgnoreCase(ancestor,SPARTAN3AN) OR
equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4K ) then -- base family type
if ( equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KEX ) then
if ( equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXL ) then
if ( equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXV ) then
if ( equalIgnoreCase(ancestor,X4KXV) OR
equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXLA ) then
if ( equalIgnoreCase(ancestor,X4KXLA) OR
equalIgnoreCase(ancestor,X4KXV) OR
equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KE ) then
if ( equalIgnoreCase(ancestor,X4KE) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KL ) then
if ( equalIgnoreCase(ancestor,X4KL) OR
equalIgnoreCase(ancestor,X4KE) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN ) then
if ( equalIgnoreCase(ancestor,SPARTAN) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTANXL ) then
if ( equalIgnoreCase(ancestor,SPARTANXL) OR
equalIgnoreCase(ancestor,SPARTAN) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, ANY ) then
if equalIgnoreCase( ancestor, any ) then is_derived := TRUE;
end if;
end if;
return is_derived;
end derived;
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
function toLowerCaseChar( char : character ) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' OR char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a';
when 'B' => return 'b';
when 'C' => return 'c';
when 'D' => return 'd';
when 'E' => return 'e';
when 'F' => return 'f';
when 'G' => return 'g';
when 'H' => return 'h';
when 'I' => return 'i';
when 'J' => return 'j';
when 'K' => return 'k';
when 'L' => return 'l';
when 'M' => return 'm';
when 'N' => return 'n';
when 'O' => return 'o';
when 'P' => return 'p';
when 'Q' => return 'q';
when 'R' => return 'r';
when 'S' => return 's';
when 'T' => return 't';
when 'U' => return 'u';
when 'V' => return 'v';
when 'W' => return 'w';
when 'X' => return 'x';
when 'Y' => return 'y';
when 'Z' => return 'z';
when others => return char;
end case;
end toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function equalIgnoreCase( str1, str2 : string ) return boolean is
constant LEN1 : integer := str1'length;
constant LEN2 : integer := str2'length;
variable equal : boolean := TRUE;
begin
if not (LEN1 = LEN2) then
equal := FALSE;
else
for i in str1'range loop
if not (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) then
equal := FALSE;
end if;
end loop;
end if;
return equal;
end equalIgnoreCase;
end system_xadc_wiz_0_0_family;
|
apache-2.0
|
ebc944bfd41269801a4091a4126cb685
| 0.548517 | 4.68436 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ipshared/2e37/xlconcat.vhd
| 9 | 11,196 |
------------------------------------------------------------------------
--
-- Filename : xlconcat.vhd
--
-- Date : 03/14/2014
--
-- Description : VHDL description of a concat block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconcat
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of bus concatenater
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconcat is
generic (
NUM_PORTS : integer := 2; -- Number of input ports to concat
IN0_WIDTH : integer := 1; -- Width of a In0 input
IN1_WIDTH : integer := 1; -- Width of a In1 input
IN2_WIDTH : integer := 1; -- Width of a In2 input
IN3_WIDTH : integer := 1; -- Width of a In3 input
IN4_WIDTH : integer := 1; -- Width of a In4 input
IN5_WIDTH : integer := 1; -- Width of a In5 input
IN6_WIDTH : integer := 1; -- Width of a In6 input
IN7_WIDTH : integer := 1; -- Width of a In7 input
IN8_WIDTH : integer := 1; -- Width of a In8 input
IN9_WIDTH : integer := 1; -- Width of a In9 input
IN10_WIDTH : integer := 1; -- Width of a In10 input
IN11_WIDTH : integer := 1; -- Width of a In10 input
IN12_WIDTH : integer := 1; -- Width of a In10 input
IN13_WIDTH : integer := 1; -- Width of a In10 input
IN14_WIDTH : integer := 1; -- Width of a In10 input
IN15_WIDTH : integer := 1; -- Width of a In15 input
IN16_WIDTH : integer := 1; -- Width of a In16 input
IN17_WIDTH : integer := 1; -- Width of a In17 input
IN18_WIDTH : integer := 1; -- Width of a In18 input
IN19_WIDTH : integer := 1; -- Width of a In19 input
IN20_WIDTH : integer := 1; -- Width of a In20 input
IN21_WIDTH : integer := 1; -- Width of a In21 input
IN22_WIDTH : integer := 1; -- Width of a In22 input
IN23_WIDTH : integer := 1; -- Width of a In23 input
IN24_WIDTH : integer := 1; -- Width of a In24 input
IN25_WIDTH : integer := 1; -- Width of a In25 input
IN26_WIDTH : integer := 1; -- Width of a In26 input
IN27_WIDTH : integer := 1; -- Width of a In27 input
IN28_WIDTH : integer := 1; -- Width of a In28 input
IN29_WIDTH : integer := 1; -- Width of a In29 input
IN30_WIDTH : integer := 1; -- Width of a In30 input
IN31_WIDTH : integer := 1; -- Width of a In31 input
dout_width : integer := 2); -- Width of output
port (
In0 : in std_logic_vector (IN0_WIDTH-1 downto 0);
In1 : in std_logic_vector (IN1_WIDTH-1 downto 0);
In2 : in std_logic_vector (IN2_WIDTH-1 downto 0);
In3 : in std_logic_vector (IN3_WIDTH-1 downto 0);
In4 : in std_logic_vector (IN4_WIDTH-1 downto 0);
In5 : in std_logic_vector (IN5_WIDTH-1 downto 0);
In6 : in std_logic_vector (IN6_WIDTH-1 downto 0);
In7 : in std_logic_vector (IN7_WIDTH-1 downto 0);
In8 : in std_logic_vector (IN8_WIDTH-1 downto 0);
In9 : in std_logic_vector (IN9_WIDTH-1 downto 0);
In10 : in std_logic_vector (IN10_WIDTH-1 downto 0);
In11 : in std_logic_vector (IN11_WIDTH-1 downto 0);
In12 : in std_logic_vector (IN12_WIDTH-1 downto 0);
In13 : in std_logic_vector (IN13_WIDTH-1 downto 0);
In14 : in std_logic_vector (IN14_WIDTH-1 downto 0);
In15 : in std_logic_vector (IN15_WIDTH-1 downto 0);
In16 : in std_logic_vector (IN16_WIDTH-1 downto 0);
In17 : in std_logic_vector (IN17_WIDTH-1 downto 0);
In18 : in std_logic_vector (IN18_WIDTH-1 downto 0);
In19 : in std_logic_vector (IN19_WIDTH-1 downto 0);
In20 : in std_logic_vector (IN20_WIDTH-1 downto 0);
In21 : in std_logic_vector (IN21_WIDTH-1 downto 0);
In22 : in std_logic_vector (IN22_WIDTH-1 downto 0);
In23 : in std_logic_vector (IN23_WIDTH-1 downto 0);
In24 : in std_logic_vector (IN24_WIDTH-1 downto 0);
In25 : in std_logic_vector (IN25_WIDTH-1 downto 0);
In26 : in std_logic_vector (IN26_WIDTH-1 downto 0);
In27 : in std_logic_vector (IN27_WIDTH-1 downto 0);
In28 : in std_logic_vector (IN28_WIDTH-1 downto 0);
In29 : in std_logic_vector (IN29_WIDTH-1 downto 0);
In30 : in std_logic_vector (IN30_WIDTH-1 downto 0);
In31 : in std_logic_vector (IN31_WIDTH-1 downto 0);
dout : out std_logic_vector (dout_width-1 downto 0)
);
end xlconcat;
architecture behavioral of xlconcat is
begin
NUM_1_INST : if NUM_PORTS = 1 generate
begin
dout <= In0;
end generate NUM_1_INST;
NUM_2_INST : if NUM_PORTS = 2 generate
begin
dout <= In1 & In0;
end generate NUM_2_INST;
NUM_3_INST : if NUM_PORTS = 3 generate
begin
dout <= In2 & In1 & In0;
end generate NUM_3_INST;
NUM_4_INST : if NUM_PORTS = 4 generate
begin
dout <= In3 & In2 & In1 & In0;
end generate NUM_4_INST;
NUM_5_INST : if NUM_PORTS = 5 generate
begin
dout <= In4 & In3 & In2 & In1 & In0;
end generate NUM_5_INST;
NUM_6_INST : if NUM_PORTS = 6 generate
begin
dout <= In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_6_INST;
NUM_7_INST : if NUM_PORTS = 7 generate
begin
dout <= In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_7_INST;
NUM_8_INST : if NUM_PORTS = 8 generate
begin
dout <= In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_8_INST;
NUM_9_INST : if NUM_PORTS = 9 generate
begin
dout <= In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_9_INST;
NUM_10_INST : if NUM_PORTS = 10 generate
begin
dout <= In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_10_INST;
NUM_11_INST : if NUM_PORTS = 11 generate
begin
dout <= In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_11_INST;
NUM_12_INST : if NUM_PORTS = 12 generate
begin
dout <= In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_12_INST;
NUM_13_INST : if NUM_PORTS = 13 generate
begin
dout <= In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_13_INST;
NUM_14_INST : if NUM_PORTS = 14 generate
begin
dout <= In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_14_INST;
NUM_15_INST : if NUM_PORTS = 15 generate
begin
dout <= In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_15_INST;
NUM_16_INST : if NUM_PORTS = 16 generate
begin
dout <= In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_16_INST;
NUM_17_INST : if NUM_PORTS = 17 generate
begin
dout <= In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_17_INST;
NUM_18_INST : if NUM_PORTS = 18 generate
begin
dout <= In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_18_INST;
NUM_19_INST : if NUM_PORTS = 19 generate
begin
dout <= In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_19_INST;
NUM_20_INST : if NUM_PORTS = 20 generate
begin
dout <= In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_20_INST;
NUM_21_INST : if NUM_PORTS = 21 generate
begin
dout <= In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_21_INST;
NUM_22_INST : if NUM_PORTS = 22 generate
begin
dout <= In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_22_INST;
NUM_23_INST : if NUM_PORTS = 23 generate
begin
dout <= In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_23_INST;
NUM_24_INST : if NUM_PORTS = 24 generate
begin
dout <= In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_24_INST;
NUM_25_INST : if NUM_PORTS = 25 generate
begin
dout <= In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_25_INST;
NUM_26_INST : if NUM_PORTS = 26 generate
begin
dout <= In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_26_INST;
NUM_27_INST : if NUM_PORTS = 27 generate
begin
dout <= In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_27_INST;
NUM_28_INST : if NUM_PORTS = 28 generate
begin
dout <= In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_28_INST;
NUM_29_INST : if NUM_PORTS = 29 generate
begin
dout <= In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_29_INST;
NUM_30_INST : if NUM_PORTS = 30 generate
begin
dout <= In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_30_INST;
NUM_31_INST : if NUM_PORTS = 31 generate
begin
dout <= In30 & In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_31_INST;
NUM_32_INST : if NUM_PORTS = 32 generate
begin
dout <= In31 & In30 & In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_32_INST;
end behavioral;
|
apache-2.0
|
9c3d4064dd3c05db383195338cc08332
| 0.56547 | 2.822284 | false | false | false | false |
kaott/16-bit-risc
|
vhdl/ins_mem.vhd
| 4 | 947 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.lib.all;
entity ins_mem is
port (DIN : in std_logic_vector(15 downto 0);
DOUT : out std_logic_vector(15 downto 0)
);
end ins_mem;
architecture Logic of ins_mem is
type input is array (32 downto 0) of std_logic_vector(15 downto 0);
signal inputstruct : input;
begin
inputstruct(0) <= "1011111010000000"; -- lw r2, 0x100
inputstruct(1) <= "1011111011000010"; -- lw r3, 0x102
inputstruct(2) <= "0000010011001010"; -- add r1, r2, r3
inputstruct(3) <= "1111111001000100"; -- sw r1, 0x104
inputstruct(4) <= "1011111001000100"; -- print r1
inputstruct(5) <= "0000010011100110"; -- sub r4, r2, r3
inputstruct(6) <= "0100001100000001"; -- beq r1, r4, 8
inputstruct(7) <= "0000001100001110"; -- sub r1, r1, r4
inputstruct(8) <= "1111111001000110"; -- sw r1, 0x106
DOUT <= inputstruct(to_integer(unsigned(DIN)));
end Logic;
|
mit
|
d3c4590ea019861dfc56cdc31b238c81
| 0.663147 | 2.869697 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_rst_mig_7series_0_83M_0/system_rst_mig_7series_0_83M_0_sim_netlist.vhdl
| 1 | 32,593 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:44:09 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_rst_mig_7series_0_83M_0/system_rst_mig_7series_0_83M_0_sim_netlist.vhdl
-- Design : system_rst_mig_7series_0_83M_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_mig_7series_0_83M_0_cdc_sync is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
ext_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_mig_7series_0_83M_0_cdc_sync : entity is "cdc_sync";
end system_rst_mig_7series_0_83M_0_cdc_sync;
architecture STRUCTURE of system_rst_mig_7series_0_83M_0_cdc_sync is
signal exr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => exr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => ext_reset_in,
I1 => mb_debug_sys_rst,
O => exr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(0),
I2 => \^scndry_out\,
I3 => p_3_out(1),
I4 => p_3_out(2),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_mig_7series_0_83M_0_cdc_sync_0 is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
aux_reset_in : in STD_LOGIC;
lpf_asr : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_mig_7series_0_83M_0_cdc_sync_0 : entity is "cdc_sync";
end system_rst_mig_7series_0_83M_0_cdc_sync_0;
architecture STRUCTURE of system_rst_mig_7series_0_83M_0_cdc_sync_0 is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => asr_lpf(0),
I2 => \^scndry_out\,
I3 => p_1_in,
I4 => p_2_in,
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_mig_7series_0_83M_0_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_mig_7series_0_83M_0_upcnt_n : entity is "upcnt_n";
end system_rst_mig_7series_0_83M_0_upcnt_n;
architecture STRUCTURE of system_rst_mig_7series_0_83M_0_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_mig_7series_0_83M_0_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
aux_reset_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_mig_7series_0_83M_0_lpf : entity is "lpf";
end system_rst_mig_7series_0_83M_0_lpf;
architecture STRUCTURE of system_rst_mig_7series_0_83M_0_lpf is
signal \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of POR_SRL_I : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_HIGH_EXT.ACT_HI_EXT\: entity work.system_rst_mig_7series_0_83M_0_cdc_sync
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.system_rst_mig_7series_0_83M_0_cdc_sync_0
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => Q,
I1 => lpf_asr,
I2 => dcm_locked,
I3 => lpf_exr,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_mig_7series_0_83M_0_sequence_psr is
port (
Core : out STD_LOGIC;
bsr : out STD_LOGIC;
pr : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_mig_7series_0_83M_0_sequence_psr : entity is "sequence_psr";
end system_rst_mig_7series_0_83M_0_sequence_psr;
architecture STRUCTURE of system_rst_mig_7series_0_83M_0_sequence_psr is
signal \^core\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^bsr\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^pr\ : STD_LOGIC;
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Core <= \^core\;
bsr <= \^bsr\;
pr <= \^pr\;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^core\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^core\,
S => lpf_int
);
SEQ_COUNTER: entity work.system_rst_mig_7series_0_83M_0_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0804"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8040"
)
port map (
I0 => seq_cnt(4),
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt_en,
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^core\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0210"
)
port map (
I0 => seq_cnt(0),
I1 => seq_cnt(1),
I2 => seq_cnt(2),
I3 => seq_cnt_en,
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1080"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(5),
I2 => seq_cnt(3),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_mig_7series_0_83M_0_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of system_rst_mig_7series_0_83M_0_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of system_rst_mig_7series_0_83M_0_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of system_rst_mig_7series_0_83M_0_proc_sys_reset : entity is "1'b1";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of system_rst_mig_7series_0_83M_0_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of system_rst_mig_7series_0_83M_0_proc_sys_reset : entity is "artix7";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of system_rst_mig_7series_0_83M_0_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of system_rst_mig_7series_0_83M_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of system_rst_mig_7series_0_83M_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of system_rst_mig_7series_0_83M_0_proc_sys_reset : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_mig_7series_0_83M_0_proc_sys_reset : entity is "proc_sys_reset";
end system_rst_mig_7series_0_83M_0_proc_sys_reset;
architecture STRUCTURE of system_rst_mig_7series_0_83M_0_proc_sys_reset is
signal Core : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal bsr : STD_LOGIC;
signal lpf_int : STD_LOGIC;
signal pr : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \BSR_OUT_DFF[0].bus_struct_reset_reg[0]\ : label is "no";
attribute equivalent_register_removal of \PR_OUT_DFF[0].peripheral_reset_reg[0]\ : label is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].bus_struct_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.system_rst_mig_7series_0_83M_0_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
\PR_OUT_DFF[0].peripheral_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.system_rst_mig_7series_0_83M_0_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ => SEQ_n_4,
Core => Core,
bsr => bsr,
lpf_int => lpf_int,
pr => pr,
slowest_sync_clk => slowest_sync_clk
);
mb_reset_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core,
Q => mb_reset,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_mig_7series_0_83M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_rst_mig_7series_0_83M_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_rst_mig_7series_0_83M_0 : entity is "system_rst_mig_7series_0_83M_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_rst_mig_7series_0_83M_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_rst_mig_7series_0_83M_0 : entity is "proc_sys_reset,Vivado 2016.4";
end system_rst_mig_7series_0_83M_0;
architecture STRUCTURE of system_rst_mig_7series_0_83M_0 is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b1";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
begin
U0: entity work.system_rst_mig_7series_0_83M_0_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
|
apache-2.0
|
a87e9318961ea9d61d58aa1a29691b74
| 0.574847 | 2.845556 | false | false | false | false |
jeffmagina/ECE368
|
Project1/EXECUTE/ALU/alu_logic_unit.vhd
| 1 | 1,459 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Logic_Unit
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Logic Unit
-- Operations - AND, OR, CMP, ANDI
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Logic_Unit is
Port ( A : in STD_LOGIC_VECTOR (15 downto 0);
B : in STD_LOGIC_VECTOR (15 downto 0);
OP : in STD_LOGIC_VECTOR (2 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
RESULT : out STD_LOGIC_VECTOR (15 downto 0));
end Logic_Unit;
architecture Combinational of Logic_Unit is
signal cmp: STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
with OP select
RESULT <=
A and B when "010", -- AND REG A, REG B
A or B when "011", -- OR REG A, REG B
A and B when OTHERS;-- ANDI REG A, IMMED
--Compare Operation
cmp(3) <= '1' when a<b else '0'; -- N when s<r
cmp(2) <= '1' when a=b else '0'; -- Z when s=r
-- Choose CCR output
with OP select
ccr <=
cmp when "100",
"0000" when OTHERS;
end Combinational;
|
mit
|
354171f76a53de8fdfc0be75b26aa04f
| 0.549006 | 3.731458 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_gpio_pullup_0/sim/system_axi_gpio_pullup_0.vhd
| 1 | 9,135 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_13;
USE axi_gpio_v2_0_13.axi_gpio;
ENTITY system_axi_gpio_pullup_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END system_axi_gpio_pullup_0;
ARCHITECTURE system_axi_gpio_pullup_0_arch OF system_axi_gpio_pullup_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_gpio_pullup_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 2,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END system_axi_gpio_pullup_0_arch;
|
apache-2.0
|
678c8eae944047b4d9399dc09426e6d6
| 0.68046 | 3.237066 | false | false | false | false |
daniw/add
|
edk/IVK_HW/t01_hello/hdl/mb_plb_wrapper.vhd
| 1 | 14,613 |
-------------------------------------------------------------------------------
-- mb_plb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_v46_v1_05_a;
use plb_v46_v1_05_a.all;
entity mb_plb_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 4);
MPLB_Rst : out std_logic_vector(0 to 1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 63);
M_UABus : in std_logic_vector(0 to 63);
M_BE : in std_logic_vector(0 to 7);
M_RNW : in std_logic_vector(0 to 1);
M_abort : in std_logic_vector(0 to 1);
M_busLock : in std_logic_vector(0 to 1);
M_TAttribute : in std_logic_vector(0 to 31);
M_lockErr : in std_logic_vector(0 to 1);
M_MSize : in std_logic_vector(0 to 3);
M_priority : in std_logic_vector(0 to 3);
M_rdBurst : in std_logic_vector(0 to 1);
M_request : in std_logic_vector(0 to 1);
M_size : in std_logic_vector(0 to 7);
M_type : in std_logic_vector(0 to 5);
M_wrBurst : in std_logic_vector(0 to 1);
M_wrDBus : in std_logic_vector(0 to 63);
Sl_addrAck : in std_logic_vector(0 to 4);
Sl_MRdErr : in std_logic_vector(0 to 9);
Sl_MWrErr : in std_logic_vector(0 to 9);
Sl_MBusy : in std_logic_vector(0 to 9);
Sl_rdBTerm : in std_logic_vector(0 to 4);
Sl_rdComp : in std_logic_vector(0 to 4);
Sl_rdDAck : in std_logic_vector(0 to 4);
Sl_rdDBus : in std_logic_vector(0 to 159);
Sl_rdWdAddr : in std_logic_vector(0 to 19);
Sl_rearbitrate : in std_logic_vector(0 to 4);
Sl_SSize : in std_logic_vector(0 to 9);
Sl_wait : in std_logic_vector(0 to 4);
Sl_wrBTerm : in std_logic_vector(0 to 4);
Sl_wrComp : in std_logic_vector(0 to 4);
Sl_wrDAck : in std_logic_vector(0 to 4);
Sl_MIRQ : in std_logic_vector(0 to 9);
PLB_MIRQ : out std_logic_vector(0 to 1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 3);
PLB_MAddrAck : out std_logic_vector(0 to 1);
PLB_MTimeout : out std_logic_vector(0 to 1);
PLB_MBusy : out std_logic_vector(0 to 1);
PLB_MRdErr : out std_logic_vector(0 to 1);
PLB_MWrErr : out std_logic_vector(0 to 1);
PLB_MRdBTerm : out std_logic_vector(0 to 1);
PLB_MRdDAck : out std_logic_vector(0 to 1);
PLB_MRdDBus : out std_logic_vector(0 to 63);
PLB_MRdWdAddr : out std_logic_vector(0 to 7);
PLB_MRearbitrate : out std_logic_vector(0 to 1);
PLB_MWrBTerm : out std_logic_vector(0 to 1);
PLB_MWrDAck : out std_logic_vector(0 to 1);
PLB_MSSize : out std_logic_vector(0 to 3);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 0);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 4);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 31);
PLB_wrPrim : out std_logic_vector(0 to 4);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 1);
PLB_SMWrErr : out std_logic_vector(0 to 1);
PLB_SMBusy : out std_logic_vector(0 to 1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 31);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of mb_plb_wrapper : entity is "plb_v46_v1_05_a";
end mb_plb_wrapper;
architecture STRUCTURE of mb_plb_wrapper is
component plb_v46 is
generic (
C_PLBV46_NUM_MASTERS : integer;
C_PLBV46_NUM_SLAVES : integer;
C_PLBV46_MID_WIDTH : integer;
C_PLBV46_AWIDTH : integer;
C_PLBV46_DWIDTH : integer;
C_DCR_INTFCE : integer;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_DCR_AWIDTH : integer;
C_DCR_DWIDTH : integer;
C_EXT_RESET_HIGH : integer;
C_IRQ_ACTIVE : std_logic;
C_ADDR_PIPELINING_TYPE : integer;
C_FAMILY : string;
C_P2P : integer;
C_ARB_TYPE : integer
);
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
MPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_ABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
DCR_DBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_UABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_BE : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1);
M_RNW : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_busLock : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_TAttribute : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*16)-1);
M_lockErr : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_MSize : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_priority : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_rdBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_request : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_size : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
M_type : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*3)-1);
M_wrBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_wrDBus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
Sl_addrAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MRdErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MWrErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MBusy : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 );
Sl_rdBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1);
Sl_rdWdAddr : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*4-1);
Sl_rearbitrate : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_SSize : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*2-1);
Sl_wait : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MIRQ : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1);
PLB_MIRQ : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to (C_PLBV46_DWIDTH/8)-1);
PLB_MAddrAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MTimeout : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDBus : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
PLB_MRdWdAddr : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
PLB_MRearbitrate : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MSSize : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to C_PLBV46_MID_WIDTH-1);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_wrPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
end component;
begin
mb_plb : plb_v46
generic map (
C_PLBV46_NUM_MASTERS => 2,
C_PLBV46_NUM_SLAVES => 5,
C_PLBV46_MID_WIDTH => 1,
C_PLBV46_AWIDTH => 32,
C_PLBV46_DWIDTH => 32,
C_DCR_INTFCE => 0,
C_BASEADDR => B"1111111111",
C_HIGHADDR => B"0000000000",
C_DCR_AWIDTH => 10,
C_DCR_DWIDTH => 32,
C_EXT_RESET_HIGH => 1,
C_IRQ_ACTIVE => '1',
C_ADDR_PIPELINING_TYPE => 1,
C_FAMILY => "spartan6",
C_P2P => 0,
C_ARB_TYPE => 0
)
port map (
PLB_Clk => PLB_Clk,
SYS_Rst => SYS_Rst,
PLB_Rst => PLB_Rst,
SPLB_Rst => SPLB_Rst,
MPLB_Rst => MPLB_Rst,
PLB_dcrAck => PLB_dcrAck,
PLB_dcrDBus => PLB_dcrDBus,
DCR_ABus => DCR_ABus,
DCR_DBus => DCR_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
M_ABus => M_ABus,
M_UABus => M_UABus,
M_BE => M_BE,
M_RNW => M_RNW,
M_abort => M_abort,
M_busLock => M_busLock,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
Sl_addrAck => Sl_addrAck,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MBusy => Sl_MBusy,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
Sl_MIRQ => Sl_MIRQ,
PLB_MIRQ => PLB_MIRQ,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_BE => PLB_BE,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MSSize => PLB_MSSize,
PLB_PAValid => PLB_PAValid,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_rdPendPri => PLB_rdPendPri,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
PLB_SaddrAck => PLB_SaddrAck,
PLB_SMRdErr => PLB_SMRdErr,
PLB_SMWrErr => PLB_SMWrErr,
PLB_SMBusy => PLB_SMBusy,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_Sssize => PLB_Sssize,
PLB_Swait => PLB_Swait,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrDAck => PLB_SwrDAck,
Bus_Error_Det => Bus_Error_Det
);
end architecture STRUCTURE;
|
gpl-2.0
|
23aaf11a9594753a9dd66efd24efe11b
| 0.610142 | 3.033001 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_wiz_0_0_axi_lite_ipif.vhd
| 1 | 14,907 |
-------------------------------------------------------------------------------
-- AXI Lite IP Interface (IPIF) - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: system_xadc_wiz_0_0_axi_lite_ipif.vhd
-- Version: v1.01.a
-- Description: This is the top level design file for the axi_lite_ipif
-- function. It provides a standardized slave interface
-- between the IP and the AXI. This version supports
-- single read/write transfers only. It does not provide
-- address pipelining or simultaneous read and write
-- operations.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- v1.01.a
-- 1. updated to reduce the utilization
-- Closed CR #574507
-- 2. Optimized the state machine code
-- 3. Optimized the address decoder logic to generate the CE's with common logic
-- 4. Address GAP decoding logic is removed and timeout counter is made active
-- for all transactions.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library work;
use work.system_xadc_wiz_0_0_proc_common_pkg.all;
use work.system_xadc_wiz_0_0_proc_common_pkg.clog2;
use work.system_xadc_wiz_0_0_proc_common_pkg.max2;
use work.system_xadc_wiz_0_0_family_support.all;
use work.system_xadc_wiz_0_0_ipif_pkg.all;
--library axi_lite_ipif_v1_01_a;
-- use axi_lite_ipif_v1_01_a.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity system_xadc_wiz_0_0_axi_lite_ipif is
generic (
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 8;
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := -- not used
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := -- not used
(
4, -- User0 CE Number
12 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
--System signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
((C_S_AXI_ADDR_WIDTH-1) downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end system_xadc_wiz_0_0_axi_lite_ipif;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of system_xadc_wiz_0_0_axi_lite_ipif is
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Slave Attachment
-------------------------------------------------------------------------------
I_SLAVE_ATTACHMENT: entity work.system_xadc_wiz_0_0_slave_attachment
generic map(
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_IPIF_ABUS_WIDTH => C_S_AXI_ADDR_WIDTH,
C_IPIF_DBUS_WIDTH => C_S_AXI_DATA_WIDTH,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_FAMILY => C_FAMILY
)
port map(
-- AXI signals
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
-- IPIC signals
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Resetn => Bus2IP_Resetn,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_CS => Bus2IP_CS,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
Bus2IP_Data => Bus2IP_Data,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_Error => IP2Bus_Error
);
end imp;
|
apache-2.0
|
17a841f1987ed54146f9cec6422802b6
| 0.452942 | 4.255495 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ipshared/0ba0/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd
| 7 | 126,490 |
-- IPIF Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_pkg.vhd
-- Version: Intital
-- Description: This file contains the constants and functions used in the
-- ipif common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 02/21/02 -- Created from proc_common_pkg.vhd
--
-- DET 03/13/02 -- PLB IPIF development updates
-- ^^^^^^
-- - Commented out string types and string functions due to an XST
-- problem with string arrays and functions. THe string array
-- processing functions were replaced with comperable functions
-- operating on integer arrays.
-- ~~~~~~
--
--
-- DET 4/30/2002 Initial
-- ~~~~~~
-- - Added three functions: rebuild_slv32_array, rebuild_slv64_array, and
-- rebuild_int_array to support removal of unused elements from the
-- ARD arrays.
-- ^^^^^^ --
--
-- FLO 8/12/2002
-- ~~~~~~
-- - Added three functions: bits_needed_for_vac, bits_needed_for_occ,
-- and get_id_index_iboe.
-- (Removed provisional functions bits_needed_for_vacancy,
-- bits needed_for_occupancy, and bits_needed_for.)
-- ^^^^^^
--
-- FLO 3/24/2003
-- ~~~~~~
-- - Added dependent property paramters for channelized DMA.
-- - Added common property parameter array type.
-- - Definded the KEYHOLD_BURST common-property parameter.
-- ^^^^^^
--
-- FLO 10/22/2003
-- ~~~~~~
-- - Some adjustment to CHDMA parameterization.
-- - Cleanup of obsolete code and comments. (The former "XST workaround"
-- has become the officially deployed method.)
-- ^^^^^^
--
-- LSS 03/24/2004
-- ~~~~~~
-- - Added 5 functions
-- ^^^^^^
--
-- ALS 09/03/04
-- ^^^^^^
-- -- Added constants to describe the channel protocols used in MCH_OPB_IPIF
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package ipif_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type SLV32_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 31);
subtype SLV64_TYPE is std_logic_vector(0 to 63);
type SLV64_ARRAY_TYPE is array (natural range <>) of SLV64_TYPE;
type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean;
function equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN;
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer;
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer;
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function S32 (in_string : string) return string;
--------------------------------------------------------------------------------
-- ARD support functions.
-- These function can be useful when operating with the ARD parameterization.
--------------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean;
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default_i : integer)
return integer;
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE) return integer;
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer ;
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE;
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE;
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE;
-- 5 Functions Added 3/24/04
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE ;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function log2(x : natural) return integer;
function clog2(x : positive) return natural;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Channel Protocols
-- The constant declarations below give symbolic-name aliases for values that
-- can be used in the C_MCH_PROTOCOL_ARRAY generic of the MCH_OPB_IPIF.
-------------------------------------------------------------------------------
constant XCL : integer := 0;
constant DAG : integer := 1;
--------------------------------------------------------------------------------
-- Address range types.
-- The constant declarations, below, give symbolic-name aliases for values
-- that can be used in the C_ARD_ID_ARRAY generic of IPIFs. The first set
-- gives aliases that are used to include IPIF services.
--------------------------------------------------------------------------------
-- IPIF module aliases
Constant IPIF_INTR : integer := 1;
Constant IPIF_RST : integer := 2;
Constant IPIF_SESR_SEAR : integer := 3;
Constant IPIF_DMA_SG : integer := 4;
Constant IPIF_WRFIFO_REG : integer := 5;
Constant IPIF_WRFIFO_DATA : integer := 6;
Constant IPIF_RDFIFO_REG : integer := 7;
Constant IPIF_RDFIFO_DATA : integer := 8;
Constant IPIF_CHDMA_CHANNELS : integer := 9;
Constant IPIF_CHDMA_GLOBAL_REGS : integer := 10;
Constant CHDMA_STATUS_FIFO : integer := 90;
-- Some predefined user module aliases
Constant USER_00 : integer := 100;
Constant USER_01 : integer := 101;
Constant USER_02 : integer := 102;
Constant USER_03 : integer := 103;
Constant USER_04 : integer := 104;
Constant USER_05 : integer := 105;
Constant USER_06 : integer := 106;
Constant USER_07 : integer := 107;
Constant USER_08 : integer := 108;
Constant USER_09 : integer := 109;
Constant USER_10 : integer := 110;
Constant USER_11 : integer := 111;
Constant USER_12 : integer := 112;
Constant USER_13 : integer := 113;
Constant USER_14 : integer := 114;
Constant USER_15 : integer := 115;
Constant USER_16 : integer := 116;
---( Start of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Dependent Properties (properties that depend on the type of
-- the address range, or in other words, address-range-specific parameters).
-- There is one property, i.e. one parameter, encoded as an integer at
-- each index of the properties array. There is one properties array for
-- each address range.
--
-- The C_ARD_DEPENDENT_PROPS_ARRAY generic parameter in (most) IPIFs is such
-- a properties array and it is usually giving its (static) value using a
-- VHDL aggregate construct. (--ToDo, give an example of this.)
--
-- The the "assigned" default value of a dependent property is zero. This value
-- is usually specified the aggregate by leaving its (index) name out so that
-- it is covered by an "others => 0" choice in the aggregate. Some parameters,
-- as noted in the definitions, below, have an "effective" default value that is
-- different from the assigned default value of zero. In such cases, the
-- function, eff_dp, given below, can be used to get the effective value of
-- the dependent property.
--------------------------------------------------------------------------------
constant DEPENDENT_PROPS_SIZE : integer := 32;
subtype DEPENDENT_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to DEPENDENT_PROPS_SIZE-1);
type DEPENDENT_PROPS_ARRAY_TYPE
is array (natural range <>) of DEPENDENT_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of dependent properties for the different types of
-- address ranges.
--
-- Example: Let C_ARD_DEPENDENT_PROPS_ARRAY hold the dependent properites
-- for a set of address ranges. Then, e.g.,
--
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(FIFO_CAPACITY_BITS)
--
-- gives the fifo capacity in bits, provided that the i'th address range
-- is of type IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals. (The right to change numerical index assignments
-- is reserved; applications using the names will not be affected by such
-- reassignments.)
--------------------------------------------------------------------------------
--
--ToDo, if the interrupt controller parameterization is ever moved to
-- C_ARD_DEPENDENT_PROPS_ARRAY, then the following declarations
-- could be uncommented and used.
---- IPIF_INTR IDX
---------------------------------------------------------------------------- ---
constant EXCLUDE_DEV_ISC : integer := 0;
-- 1 specifies that only the global interrupt
-- enable is present in the device interrupt source
-- controller and that the only source of interrupts
-- in the device is the IP interrupt source controller.
-- 0 specifies that the full device interrupt
-- source controller structure will be included.
constant INCLUDE_DEV_PENCODER : integer := 1;
-- 1 will include the Device IID in the device interrupt
-- source controller, 0 will exclude it.
--
-- IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA IDX
---------------------------------------------------------------------------- ---
constant FIFO_CAPACITY_BITS : integer := 0;
constant WR_WIDTH_BITS : integer := 1;
constant RD_WIDTH_BITS : integer := 2;
constant EXCLUDE_PACKET_MODE : integer := 3;
-- 1 Don't include packet mode features
-- 0 Include packet mode features
constant EXCLUDE_VACANCY : integer := 4;
-- 1 Don't include vacancy calculation
-- 0 Include vacancy calculation
-- See also the functions
-- bits_needed_for_vac and
-- bits_needed_for_occ that are declared below.
constant INCLUDE_DRE : integer := 5;
constant INCLUDE_AUTOPUSH_POP : integer := 6;
constant AUTOPUSH_POP_CE : integer := 7;
constant INCLUDE_CSUM : integer := 8;
--------------------------------------------------------------------------------
--
-- DMA_SG IDX
---------------------------------------------------------------------------- ---
--------------------------------------------------------------------------------
-- IPIF_CHDMA_CHANNELS IDX
---------------------------------------------------------------------------- ---
constant NUM_SUBS_FOR_PHYS_0 : integer :=0;
constant NUM_SUBS_FOR_PHYS_1 : integer :=1;
constant NUM_SUBS_FOR_PHYS_2 : integer :=2;
constant NUM_SUBS_FOR_PHYS_3 : integer :=3;
constant NUM_SUBS_FOR_PHYS_4 : integer :=4;
constant NUM_SUBS_FOR_PHYS_5 : integer :=5;
constant NUM_SUBS_FOR_PHYS_6 : integer :=6;
constant NUM_SUBS_FOR_PHYS_7 : integer :=7;
constant NUM_SUBS_FOR_PHYS_8 : integer :=8;
constant NUM_SUBS_FOR_PHYS_9 : integer :=9;
constant NUM_SUBS_FOR_PHYS_10 : integer :=10;
constant NUM_SUBS_FOR_PHYS_11 : integer :=11;
constant NUM_SUBS_FOR_PHYS_12 : integer :=12;
constant NUM_SUBS_FOR_PHYS_13 : integer :=13;
constant NUM_SUBS_FOR_PHYS_14 : integer :=14;
constant NUM_SUBS_FOR_PHYS_15 : integer :=15;
-- Gives the number of sub-channels for physical channel i.
--
-- These constants, which will be MAX_NUM_PHYS_CHANNELS in number (see
-- below), have consecutive values starting with 0 for
-- NUM_SUBS_FOR_PHYS_0. (The constants serve the purpose of giving symbolic
-- names for use in the dependent-properties aggregates that parameterize
-- an IPIF_CHDMA_CHANNELS address range.)
--
-- [Users can ignore this note for developers
-- If the number of physical channels changes, both the
-- IPIF_CHDMA_CHANNELS constants and MAX_NUM_PHYS_CHANNELS,
-- below, must be adjusted.
-- (Use of an array constant or a function of the form
-- NUM_SUBS_FOR_PHYS(i) to define the indices
-- runs afoul of LRM restrictions on non-locally static aggregate
-- choices. (Further, the LRM imposes perhaps unnecessarily
-- strict limits on what qualifies as a locally static primary.)
-- Note: This information is supplied for the benefit of anyone seeking
-- to improve the way that these NUM_SUBS_FOR_PHYS parameter
-- indices are defined.)
-- End of note for developers ]
--
-- The value associated with any index NUM_SUBS_FOR_PHYS_i in the
-- dependent-properties array must be even since TX and RX channels
-- come in pairs with the TX followed immediately by
-- the corresponding RX.
--
constant NUM_SIMPLE_DMA_CHANS : integer :=16;
-- The number of simple DMA channels.
constant NUM_SIMPLE_SG_CHANS : integer :=17;
-- The number of simple SG channels.
constant INTR_COALESCE : integer :=18;
-- 0 Interrupt coalescing is disabled
-- 1 Interrupt coalescing is enabled
constant CLK_PERIOD_PS : integer :=19;
-- The period of the OPB Bus clock in ps.
-- The default value of 0 is a special value that
-- is synonymous with 10000 ps (10 ns).
-- The value for CLK_PERIOD_PS is relevant only if (INTR_COALESCE = 1).
constant PACKET_WAIT_UNIT_NS : integer :=20;
-- Gives the unit for used for timing of pack-wait bounds.
-- The default value of 0 is a special value that
-- is synonymous with 1,000,000 ns (1 ms) and a non-default
-- value is typically only used for testing.
-- Relevant only if (INTR_COALESCE = 1).
constant BURST_SIZE : integer :=21;
-- 1, 2, 4, 8 or 16
-- The default value of 0 is a special value that
-- is synonymous with a burst size of 16.
-- Setting the BURST_SIZE to 1 effectively disables
-- bursts.
constant REMAINDER_AS_SINGLES : integer :=22;
-- 0 Remainder handled as a short burst
-- 1 Remainder handled as a series of singles
--------------------------------------------------------------------------------
-- The constant below is not the index of a dependent-properties
-- parameter (and, as such, would never appear as a choice in a
-- dependent-properties aggregate). Rather, it is fixed to the maximum
-- number of physical channels that an Address Range of type
-- IPIF_CHDMA_CHANNELS supports. It must be maintained in conjuction with
-- the constants named, e.g., NUM_SUBS_FOR_PHYS_15, above.
--------------------------------------------------------------------------------
constant MAX_NUM_PHYS_CHANNELS : natural := 16;
--------------------------------------------------------------------------
-- EXAMPLE: Here is an example dependent-properties aggregate for an
-- address range of type IPIF_CHDMA_CHANNELS.
-- To have a compact list of all of the CHDMA parameters, all are
-- shown, however three are commented out and the unneeded
-- MUM_SUBS_FOR_PHYS_x are excluded. The "OTHERS => 0" association
-- gives these parameters their default values, such that, for the example
--
-- - All physical channels above 2 have zero subchannels (effectively,
-- these physical channels are not used)
-- - There are no simple SG channels
-- - The packet-wait time unit is 1 ms
-- - Burst size is 16
--------------------------------------------------------------------------
-- (
-- NUM_SUBS_FOR_PHYS_0 => 8,
-- NUM_SUBS_FOR_PHYS_1 => 4,
-- NUM_SUBS_FOR_PHYS_2 => 14,
-- NUM_SIMPLE_DMA_CHANS => 1,
-- --NUM_SIMPLE_SG_CHANS => 5,
-- INTR_COALESCE => 1,
-- CLK_PERIOD_PS => 20000,
-- --PACKET_WAIT_UNIT_NS => 50000,
-- --BURST_SIZE => 1,
-- REMAINDER_AS_SINGLES => 1,
-- OTHERS => 0
-- )
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the vacancy (emptiness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the occupancy (fullness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Function eff_dp.
--
-- For some of the dependent properties, the default value of zero is meant
-- to imply an effective default value of other than zero (see e.g.
-- PKT_WAIT_UNIT_NS for the IPIF_CHDMA_CHANNELS address-range type). The
-- following function is used to get the (possibly default-adjusted)
-- value for a dependent property.
--
-- Example call:
--
-- eff_value_of_param :=
-- eff_dp(
-- C_IPIF_CHDMA_CHANNELS,
-- PACKET_WAIT_UNIT_NS,
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(PACKET_WAIT_UNIT_NS)
-- );
--
-- where C_ARD_DEPENDENT_PROPS_ARRAY(i) is an object of type
-- DEPENDENT_PROPS_ARRAY_TYPE, that was parameterized for an address range of
-- type C_IPIF_CHDMA_CHANNELS.
--------------------------------------------------------------------------------
function eff_dp(id : integer; -- The type of address range.
dep_prop : integer; -- The index of the dependent prop.
value : integer -- The value at that index.
) return integer; -- The effective value, possibly adjusted
-- if value has the default value of 0.
---) End of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Common Properties (properties that apply regardless of the
-- type of the address range). Structurally, these work the same as
-- the dependent properties.
--------------------------------------------------------------------------------
constant COMMON_PROPS_SIZE : integer := 2;
subtype COMMON_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to COMMON_PROPS_SIZE-1);
type COMMON_PROPS_ARRAY_TYPE
is array (natural range <>) of COMMON_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of the common properties.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals.
-- IDX
---------------------------------------------------------------------------- ---
constant KEYHOLE_BURST : integer := 0;
-- 1 All addresses of a burst are forced to the initial
-- address of the burst.
-- 0 Burst addresses follow the bus protocol.
-- IP interrupt mode array constants
Constant INTR_PASS_THRU : integer := 1;
Constant INTR_PASS_THRU_INV : integer := 2;
Constant INTR_REG_EVENT : integer := 3;
Constant INTR_REG_EVENT_INV : integer := 4;
Constant INTR_POS_EDGE_DETECT : integer := 5;
Constant INTR_NEG_EDGE_DETECT : integer := 6;
end ipif_pkg;
package body ipif_pkg is
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function "="
--
-- This function can be used to overload the "=" operator when comparing
-- strings.
-----------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean is
constant tc: character := ' '; -- string termination character
variable i: integer := 1;
variable v1 : string(1 to s1'length) := s1;
variable v2 : string(1 to s2'length) := s2;
begin
while (i <= v1'length) and (v1(i) /= tc) and
(i <= v2'length) and (v2(i) /= tc) and
(v1(i) = v2(i))
loop
i := i+1;
end loop;
return ((i > v1'length) or (v1(i) = tc)) and
((i > v2'length) or (v2(i) = tc));
end;
----------------------------------------------------------------------------
-- Function equaluseCase
--
-- This function returns true if case sensitive string comparison determines
-- that str1 and str2 are the same.
-----------------------------------------------------------------------------
FUNCTION equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str1'range LOOP
IF NOT (str1(i) = str2(i)) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equaluseCase;
-----------------------------------------------------------------------------
-- Function calc_num_ce
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The array is input to
-- the function and an integer is returned reflecting the total number of
-- Chip Enables required for the CE, RdCE, and WrCE Buses
-----------------------------------------------------------------------------
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer is
Variable ce_num_sum : integer := 0;
begin
for i in 0 to (ce_num_array'length)-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
return(ce_num_sum);
end function calc_num_ce;
-----------------------------------------------------------------------------
-- Function calc_start_ce_index
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The CE Size array is
-- input to the function and an integer index representing the index of the
-- target module in the ce_num_array. An integer is returned reflecting the
-- starting index of the assigned Chip Enables within the CE, RdCE, and
-- WrCE Buses.
-----------------------------------------------------------------------------
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer is
Variable ce_num_sum : integer := 0;
begin
If (index = 0) Then
ce_num_sum := 0;
else
for i in 0 to index-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
End if;
return(ce_num_sum);
end function calc_start_ce_index;
-----------------------------------------------------------------------------
-- Function get_min_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the smallest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_min : Integer := 1024;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) < temp_min) Then
temp_min := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_min);
end function get_min_dwidth;
-----------------------------------------------------------------------------
-- Function get_max_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the largest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_max : Integer := 0;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) > temp_max) Then
temp_max := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_max);
end function get_max_dwidth;
-----------------------------------------------------------------------------
-- Function S32
--
-- This function is used to expand an input string to 32 characters by
-- padding with spaces. If the input string is larger than 32 characters,
-- it will truncate to 32 characters.
-----------------------------------------------------------------------------
function S32 (in_string : string) return string is
constant OUTPUT_STRING_LENGTH : integer := 32;
Constant space : character := ' ';
variable new_string : string(1 to 32);
Variable start_index : Integer := in_string'length+1;
begin
If (in_string'length < OUTPUT_STRING_LENGTH) Then
for i in 1 to in_string'length loop
new_string(i) := in_string(i);
End loop;
for j in start_index to OUTPUT_STRING_LENGTH loop
new_string(j) := space;
End loop;
else -- use first 32 chars of in_string (truncate the rest)
for k in 1 to OUTPUT_STRING_LENGTH loop
new_string(k) := in_string(k);
End loop;
End if;
return(new_string);
end function S32;
-----------------------------------------------------------------------------
-- Function get_id_index
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- id number is input to the function. A integer is returned reflecting the
-- array index of the id matching the id input number. This function
-- should only be called if the id number is known to exist in the
-- name_array input. This can be detirmined by using the find_ard_id
-- function.
-----------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := 10000; -- a really big number!
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then
match_index := array_index;
else
null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index;
--------------------------------------------------------------------------------
-- get_id_index but return a value in bounds on error (iboe).
--
-- This function is the same as get_id_index, except that when id does
-- not exist in id_array, the value returned is any index that is
-- within the index range of id_array.
--
-- This function would normally only be used where function find_ard_id
-- is used to establish the existence of id but, even when non-existent,
-- an element of one of the ARD arrays will be computed from the
-- returned get_id_index_iboe value. See, e.g., function bits_needed_for_vac
-- and the example call, below
--
-- bits_needed_for_vac(
-- find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA),
-- C_ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe(C_ARD_ID_ARRAY,
-- IPIF_RDFIFO_DATA))
-- )
--------------------------------------------------------------------------------
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := id_array'left; -- any valid array index
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then match_index := array_index;
else null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index_iboe;
-----------------------------------------------------------------------------
-- Function find_ard_id
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- integer id is input to the function. A boolean is returned reflecting the
-- presence (or not) of a number in the array matching the id input number.
-----------------------------------------------------------------------------
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean is
Variable match : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
End if;
End loop;
return(match);
end function find_ard_id;
-----------------------------------------------------------------------------
-- Function find_id_dwidth
--
-- This function is used to find the data width of a target module. If the
-- target module exists, the data width is extracted from the input dwidth
-- array. If the module is not in the ID array, the default input is
-- returned. This function is needed to assign data port size constraints on
-- unconstrained port widths.
-----------------------------------------------------------------------------
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default_i : integer) return integer is
Variable id_present : Boolean := false;
Variable array_index : Integer := 0;
Variable dwidth : Integer := default_i;
begin
id_present := find_ard_id(id_array, id);
If (id_present) Then
array_index := get_id_index (id_array, id);
dwidth := dwidth_array(array_index);
else
null; -- use default input
End if;
Return (dwidth);
end function find_id_dwidth;
-----------------------------------------------------------------------------
-- Function cnt_ipif_id_blks
--
-- This function is used to detirmine the number of IPIF components specified
-- in the ARD ID Array. An integer is returned representing the number
-- of elements counted. User IDs are ignored in the counting process.
-----------------------------------------------------------------------------
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE)
return integer is
Variable blk_count : integer := 0;
Variable temp_id : integer;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_count := blk_count+1;
else -- go to next loop iteration
null;
End if;
End loop;
return(blk_count);
end function cnt_ipif_id_blks;
-----------------------------------------------------------------------------
-- Function get_ipif_id_dbus_index
--
-- This function is used to detirmine the IPIF relative index of a given
-- ID value. User IDs are ignored in the index detirmination.
-----------------------------------------------------------------------------
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer is
Variable blk_index : integer := 0;
Variable temp_id : integer;
Variable id_found : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (id_found) then
null;
elsif (temp_id = id) then
id_found := true;
elsif (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_index := blk_index+1;
else -- user block so do nothing
null;
End if;
End loop;
return(blk_index);
end function get_ipif_id_dbus_index;
------------------------------------------------------------------------------
-- Function: rebuild_slv32_array
--
-- Description:
-- This function takes an input slv32 array and rebuilds an output slv32
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr32_array : SLV32_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr32_array(array_index) := slv32_array(array_index);
end loop;
return(temp_baseaddr32_array);
end function rebuild_slv32_array;
------------------------------------------------------------------------------
-- Function: rebuild_slv64_array
--
-- Description:
-- This function takes an input slv64 array and rebuilds an output slv64
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr64_array : SLV64_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr64_array(array_index) := slv64_array(array_index);
end loop;
return(temp_baseaddr64_array);
end function rebuild_slv64_array;
------------------------------------------------------------------------------
-- Function: rebuild_int_array
--
-- Description:
-- This function takes an input integer array and rebuilds an output integer
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE is
-- Variables
variable temp_int_array : INTEGER_ARRAY_TYPE( 0 to num_valid_entry-1);
begin
for array_index in 0 to num_valid_entry-1 loop
temp_int_array(array_index) := int_array(array_index);
end loop;
return(temp_int_array);
end function rebuild_int_array;
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(RD_WIDTH_BITS)
);
end if;
end function bits_needed_for_vac;
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(WR_WIDTH_BITS)
);
end if;
end function bits_needed_for_occ;
function eff_dp(id : integer;
dep_prop : integer;
value : integer) return integer is
variable dp : integer := dep_prop;
type bo2na_type is array (boolean) of natural;
constant bo2na : bo2na_type := (0, 1);
begin
if value /= 0 then return value; end if; -- Not default
case id is
when IPIF_CHDMA_CHANNELS =>
-------------------
return( bo2na(dp = CLK_PERIOD_PS ) * 10000
+ bo2na(dp = PACKET_WAIT_UNIT_NS ) * 1000000
+ bo2na(dp = BURST_SIZE ) * 16
);
when others => return 0;
end case;
end eff_dp;
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE is
variable intr_mode_array : INTEGER_ARRAY_TYPE(0 to num_user_intr-1);
begin
for i in 0 to num_user_intr-1 loop
intr_mode_array(i) := intr_capture_mode;
end loop;
return intr_mode_array;
end function populate_intr_mode_array;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_id_array : INTEGER_ARRAY_TYPE(0 to ard_id_array'length);
begin
intr_ard_id_array(0 to ard_id_array'length-1) := ard_id_array;
if include_intr then
intr_ard_id_array(ard_id_array'length) := IPIF_INTR;
return intr_ard_id_array;
else
return ard_id_array;
end if;
end function add_intr_ard_id_array;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE is
variable intr_ard_addr_range_array : SLV64_ARRAY_TYPE(0 to ard_addr_range_array'length+1);
begin
intr_ard_addr_range_array(0 to ard_addr_range_array'length-1) := ard_addr_range_array;
if include_intr then
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR))
:= ZERO_ADDR_PAD & intr_baseaddr;
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR)+1)
:= ZERO_ADDR_PAD & intr_highaddr;
return intr_ard_addr_range_array;
else
return ard_addr_range_array;
end if;
end function add_intr_ard_addr_range_array;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_dwidth_array : INTEGER_ARRAY_TYPE(0 to ard_dwidth_array'length);
begin
intr_ard_dwidth_array(0 to ard_dwidth_array'length-1) := ard_dwidth_array;
if include_intr then
intr_ard_dwidth_array(get_id_index(ard_id_array, IPIF_INTR)) := intr_dwidth;
return intr_ard_dwidth_array;
else
return ard_dwidth_array;
end if;
end function add_intr_ard_dwidth_array;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_num_ce_array : INTEGER_ARRAY_TYPE(0 to ard_num_ce_array'length);
begin
intr_ard_num_ce_array(0 to ard_num_ce_array'length-1) := ard_num_ce_array;
if include_intr then
intr_ard_num_ce_array(get_id_index(ard_id_array, IPIF_INTR)) := 16;
return intr_ard_num_ce_array;
else
return ard_num_ce_array;
end if;
end function add_intr_ard_num_ce_array;
end package body ipif_pkg;
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
-- type bo2sl_type is array (boolean) of std_logic;
-- constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end imp;
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: address_decoder.vhd
-- Version: v2.0
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 08/09/2010 --
-- - updated the core with optimziation. Closed CR 574507
-- - combined the CE generation logic to further optimize the code.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.pselect_f;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of address_decoder is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity axi_lite_ipif_v3_0_4.pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in natural range 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity axi_lite_ipif_v3_0_4.pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture IMP;
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v2.0
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
signal start2 : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rd_done1,wr_done1 : std_logic;
--signal rd_done2,wr_done2 : std_logic;
signal wrack_1,rdack_1 : std_logic;
--signal wrack_2,rdack_2 : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
signal is_read, is_write : std_logic;
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
--bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
-- else
-- '0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
--bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
-- when (S_AXI_ARVALID='1')
-- else
-- ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
--start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
-- when (state = SM_IDLE)
-- else
-- '0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or (timeout and is_read);
wr_done <= IP2Bus_WrAck or (timeout and is_write);
--wr_done1 <= (not (wrack_1) and IP2Bus_WrAck) or timeout;
--rd_done1 <= (not (rdack_1) and IP2Bus_RdAck) or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v3_0_4.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start2,
Bus_RNW => bus2ip_rnw_i, --S_AXI_ARVALID,
Bus_RNW_Erly => bus2ip_rnw_i, --S_AXI_ARVALID,
CS_CE_ld_enable => start2,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start2,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
REGISTERING_RESET_P2 : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
-- wrack_1 <= '0';
-- rdack_1 <= '0';
-- wrack_2 <= '0';
-- rdack_2 <= '0';
-- wr_done2 <= '0';
-- rd_done2 <= '0';
bus2ip_rnw_i <= '0';
bus2ip_addr_i <= (others => '0');
start2 <= '0';
else
-- wrack_1 <= IP2Bus_WrAck;
-- rdack_1 <= IP2Bus_RdAck;
-- wrack_2 <= wrack_1;
-- rdack_2 <= rdack_1;
-- wr_done2 <= wr_done1;
-- rd_done2 <= rd_done1;
if (state = SM_IDLE and S_AXI_ARVALID='1') then
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '1';
start2 <= '1';
elsif (state = SM_IDLE and (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1')) then
bus2ip_addr_i <= ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '0';
start2 <= '1';
else
bus2ip_rnw_i <= bus2ip_rnw_i;
bus2ip_addr_i <= bus2ip_addr_i;
start2 <= '0';
end if;
end if;
end if;
end process REGISTERING_RESET_P2;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
is_read <= '0';
is_write <= '0';
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
is_read <='1';
is_write <= '0';
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
is_read <='0';
is_write <= '1';
else
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= '1' when (dpto_cnt = C_DPHASE_TIMEOUT) else '0';
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_lite_ipif.vhd
-- Version: v2.0
-- Description: This is the top level design file for the axi_lite_ipif
-- function. It provides a standardized slave interface
-- between the IP and the AXI. This version supports
-- single read/write transfers only. It does not provide
-- address pipelining or simultaneous read and write
-- operations.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- v1.01.a
-- 1. updated to reduce the utilization
-- Closed CR #574507
-- 2. Optimized the state machine code
-- 3. Optimized the address decoder logic to generate the CE's with common logic
-- 4. Address GAP decoding logic is removed and timeout counter is made active
-- for all transactions.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity axi_lite_ipif is
generic (
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 8;
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := -- not used
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := -- not used
(
4, -- User0 CE Number
12 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
--System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
((C_S_AXI_ADDR_WIDTH-1) downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end axi_lite_ipif;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_lite_ipif is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Slave Attachment
-------------------------------------------------------------------------------
I_SLAVE_ATTACHMENT: entity axi_lite_ipif_v3_0_4.slave_attachment
generic map(
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_IPIF_ABUS_WIDTH => C_S_AXI_ADDR_WIDTH,
C_IPIF_DBUS_WIDTH => C_S_AXI_DATA_WIDTH,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_FAMILY => C_FAMILY
)
port map(
-- AXI signals
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IPIC signals
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Resetn => Bus2IP_Resetn,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_CS => Bus2IP_CS,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
Bus2IP_Data => Bus2IP_Data,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_Error => IP2Bus_Error
);
end imp;
|
apache-2.0
|
af822f8d69ff35555003adfedc4ff81f
| 0.480773 | 4.528498 | false | false | false | false |
qynvi/rtl-regmux
|
regmux.vhd
| 1 | 549 |
-- William Fan
-- 02/14/2011
-- Mux RTL
library ieee;
use ieee.std_logic_1164.all;
entity reg_mux is
port (a, b, c, d: in std_logic_vector(3 downto 0);
sel: in std_logic_vector(1 downto 0);
clk: in std_logic;
y: out std_logic_vector(3 downto 0));
end entity;
architecture reg_mux of reg_mux is
signal x: std_logic_vector(3 downto 0);
begin
x <= a when sel = "00" else
b when sel = "01" else
c when sel = "10" else
d;
process (clk)
begin
if (clk'event and clk = '1') then
y <= x;
end if;
end process;
end architecture;
|
mit
|
57617d247e49fc43b1cc4e18502cd178
| 0.641166 | 2.626794 | false | false | false | false |
aggroskater/ee4321-vhdl-digital-design
|
Project-4-4bit-ALU/alu_testBench.vhd
| 1 | 17,597 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY alu_testBench IS
--thanks to: https://groups.google.com/forum/#!topic/comp.lang.vhdl/Ap0d7bl5ExU
function to_std_logic_vector(L: BOOLEAN) return std_logic_vector is
begin
if L then
return("0001");
else
return("0000");
end if;
end function to_std_logic_vector;
END alu_testBench;
ARCHITECTURE behavior OF alu_testBench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT alu_4_bit
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
op : IN std_logic_vector(5 downto 0);
R : OUT std_logic_vector(3 downto 0);
Cout : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal op : std_logic_vector(5 downto 0) := (others => '0');
--Outputs
signal R : std_logic_vector(3 downto 0);
signal Cout : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
--constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: alu_4_bit PORT MAP (
A => A,
B => B,
op => op,
R => R,
Cout => Cout
);
-- Clock process definitions
--<clock>_process :process
--begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
--end process;
-- Stimulus process
stim_proc: process
variable count_add_sub : integer :=0;
variable count_comp : integer :=0;
variable count_logic : integer :=0;
variable count_shift_rot : integer :=0;
begin
---------------------------
-- Adder Subtractor
---------------------------
-- TEST ADDER FUNCTIONALITY
A <= "0000";
B <= "0000";
op <= "000XXX";
wait for 1 ns;
for i in 0 to 15 loop
for j in 0 to 15 loop
wait for 1 ns;
if NOT(R = (A+B)) then
assert R = (A + B) report "R should have been " &
integer'image(to_integer(unsigned((A+B)))) & " with A=" &
integer'image(to_integer(unsigned(A))) & " and B=" &
integer'image(to_integer(unsigned(B))) & " but instead R was " &
integer'image(to_integer(unsigned(R))) severity ERROR;
count_add_sub := count_add_sub + 1;
else
--nada
end if;
B <= B + "0001";
end loop;
A <= A + "0001";
end loop;
-- TEST SUBTRACTOR FUNCTIONALITY
A <= "0000";
B <= "0000";
op <= "001XXX";
wait for 1 ns;
for i in 0 to 15 loop
for j in 0 to 15 loop
wait for 1 ns;
if NOT(R = (A-B)) then
assert R = (A - B) report "R should have been " &
integer'image(to_integer(unsigned((A-B)))) & " with A=" &
integer'image(to_integer(unsigned(A))) & " and B=" &
integer'image(to_integer(unsigned(B))) & " but instead R was " &
integer'image(to_integer(unsigned(R))) severity ERROR;
count_add_sub := count_add_sub + 1;
else
--nada
end if;
B <= B + "0001";
end loop;
A <= A + "0001";
end loop;
---------------------------
-- Comparison
---------------------------
--the comparison testing makes use of a user-defined function for converting
--a boolean back into a std_logic_vector. it is at the top of this file where
--the alu_testBench entity is declared.
-- Test A >= B (signed)
A <= "0000";
B <= "0000";
op <= "011001";
wait for 1 ns;
for i in 0 to 15 loop
for j in 0 to 15 loop
wait for 1 ns;
if NOT( R = to_std_logic_vector(to_integer(signed(A)) >= to_integer(signed(B)) ) )
then
assert R = to_std_logic_vector( to_integer(signed(A)) >= to_integer(signed(B)) )
report "R = A >= B signed should have been " &
boolean'image(to_integer(signed(A)) >= to_integer(signed(B)) ) &
" with A=" & integer'image(to_integer(signed(A))) &
" and B=" & integer'image(to_integer(signed(B))) &
" but instead R was " & integer'image(to_integer(unsigned(R)))
severity ERROR;
count_comp := count_comp + 1;
else
--nada
end if;
B <= B + "0001";
end loop;
A <= A + "0001";
end loop;
-- Test A < B (signed)
A <= "0000";
B <= "0000";
op <= "011010";
wait for 1 ns;
for i in 0 to 15 loop
for j in 0 to 15 loop
wait for 1 ns;
if NOT( R = to_std_logic_vector( to_integer(signed(A)) < to_integer(signed(B)) ) )
then
assert R = to_std_logic_vector( to_integer(signed(A)) < to_integer(signed(B)) )
report "R = A < B signed should have been " &
boolean'image( to_integer(signed(A)) < to_integer(signed(B)) ) &
" with A=" & integer'image(to_integer(signed(A))) &
" and B=" & integer'image(to_integer(signed(B))) &
" but instead R was " & integer'image(to_integer(unsigned(R)))
severity ERROR;
count_comp := count_comp + 1;
else
--nada
end if;
B <= B + "0001";
end loop;
A <= A + "0001";
end loop;
-- Test A != B
A <= "0000";
B <= "0000";
op <= "011011";
wait for 1 ns;
for i in 0 to 15 loop
for j in 0 to 15 loop
wait for 1 ns;
if NOT( R = to_std_logic_vector( to_integer(unsigned(A)) /= to_integer(unsigned(B)) ) )
then
assert R = to_std_logic_vector( to_integer(unsigned(A)) /= to_integer(unsigned(B)) )
report "R = A != B should have been " &
boolean'image( to_integer(unsigned(A)) /= to_integer(unsigned(B)) ) &
" with A=" & integer'image(to_integer(unsigned(A))) &
" and B=" & integer'image(to_integer(unsigned(B))) &
" but instead R was " & integer'image(to_integer(unsigned(R)))
severity ERROR;
count_comp := count_comp + 1;
else
--nada
end if;
B <= B + "0001";
end loop;
A <= A + "0001";
end loop;
-- Test A = B
A <= "0000";
B <= "0000";
op <= "011100";
wait for 1 ns;
for i in 0 to 15 loop
for j in 0 to 15 loop
wait for 1 ns;
if NOT( R = to_std_logic_vector( to_integer(unsigned(A)) = to_integer(unsigned(B)) ) )
then
assert R = to_std_logic_vector( to_integer(unsigned(A)) = to_integer(unsigned(B)) )
report "R = A = B should have been " &
boolean'image( to_integer(unsigned(A)) = to_integer(unsigned(B)) ) &
" with A=" & integer'image(to_integer(unsigned(A))) &
" and B=" & integer'image(to_integer(unsigned(B))) &
" but instead R was " & integer'image(to_integer(unsigned(R)))
severity ERROR;
count_comp := count_comp + 1;
else
--nada
end if;
B <= B + "0001";
end loop;
A <= A + "0001";
end loop;
-- Test A >= B (unsigned)
A <= "0000";
B <= "0000";
op <= "011101";
wait for 1 ns;
for i in 0 to 15 loop
for j in 0 to 15 loop
wait for 1 ns;
if NOT( R = to_std_logic_vector( to_integer(unsigned(A)) >= to_integer(unsigned(B)) ) )
then
assert R = to_std_logic_vector( to_integer(unsigned(A)) >= to_integer(unsigned(B)) )
report "R = A >= B unsigned should have been " &
boolean'image( to_integer(unsigned(A)) >= to_integer(unsigned(B)) ) &
" with A=" & integer'image(to_integer(unsigned(A))) &
" and B=" & integer'image(to_integer(unsigned(B))) &
" but instead R was " & integer'image(to_integer(unsigned(R)))
severity ERROR;
count_comp := count_comp + 1;
else
--nada
end if;
B <= B + "0001";
end loop;
A <= A + "0001";
end loop;
-- Test A < B (unsigned)
A <= "0000";
B <= "0000";
op <= "011110";
wait for 1 ns;
for i in 0 to 15 loop
for j in 0 to 15 loop
wait for 1 ns;
if NOT( R = to_std_logic_vector( to_integer(unsigned(A)) < to_integer(unsigned(B)) ) )
then
assert R = to_std_logic_vector( to_integer(unsigned(A)) < to_integer(unsigned(B)) )
report "R = A < B unsigned should have been " &
boolean'image( to_integer(unsigned(A)) < to_integer(unsigned(B)) ) &
" with A=" & integer'image(to_integer(unsigned(A))) &
" and B=" & integer'image(to_integer(unsigned(B))) &
" but instead R was " & integer'image(to_integer(unsigned(R)))
severity ERROR;
count_comp := count_comp + 1;
else
--nada
end if;
B <= B + "0001";
end loop;
A <= A + "0001";
end loop;
---------------------------
-- Logical
---------------------------
-- Test A NOR B
A <= "0000";
B <= "0000";
op <= "10XX00";
wait for 1 ns;
for i in 0 to 15 loop
for j in 0 to 15 loop
wait for 1 ns;
if NOT( R = std_logic_vector( A NOR B) )
then
assert R = std_logic_vector(A NOR B )
report "R = A NOR B should have been " &
integer'image(to_integer(unsigned(A NOR B))) &
" with A=" & integer'image(to_integer(unsigned(A))) &
" and B=" & integer'image(to_integer(unsigned(B))) &
" but instead R was " & integer'image(to_integer(unsigned(R)))
severity ERROR;
count_logic := count_logic + 1;
else
--nada
end if;
B <= B + "0001";
end loop;
A <= A + "0001";
end loop;
-- Test A AND B
A <= "0000";
B <= "0000";
op <= "10XX01";
wait for 1 ns;
for i in 0 to 15 loop
for j in 0 to 15 loop
wait for 1 ns;
if NOT( R = std_logic_vector( A AND B) )
then
assert R = std_logic_vector(A AND B )
report "R = A AND B should have been " &
integer'image(to_integer(unsigned(A AND B))) &
" with A=" & integer'image(to_integer(unsigned(A))) &
" and B=" & integer'image(to_integer(unsigned(B))) &
" but instead R was " & integer'image(to_integer(unsigned(R)))
severity ERROR;
count_logic := count_logic + 1;
else
--nada
end if;
B <= B + "0001";
end loop;
A <= A + "0001";
end loop;
-- Test A OR B
A <= "0000";
B <= "0000";
op <= "10XX10";
wait for 1 ns;
for i in 0 to 15 loop
for j in 0 to 15 loop
wait for 1 ns;
if NOT( R = std_logic_vector( A OR B) )
then
assert R = std_logic_vector(A OR B )
report "R = A OR B should have been " &
integer'image(to_integer(unsigned(A OR B))) &
" with A=" & integer'image(to_integer(unsigned(A))) &
" and B=" & integer'image(to_integer(unsigned(B))) &
" but instead R was " & integer'image(to_integer(unsigned(R)))
severity ERROR;
count_logic := count_logic + 1;
else
--nada
end if;
B <= B + "0001";
end loop;
A <= A + "0001";
end loop;
-- Test A XOR B
A <= "0000";
B <= "0000";
op <= "10XX11";
wait for 1 ns;
for i in 0 to 15 loop
for j in 0 to 15 loop
wait for 1 ns;
if NOT( R = std_logic_vector( A XOR B) )
then
assert R = std_logic_vector(A XOR B )
report "R = A XOR B should have been " &
integer'image(to_integer(unsigned(A XOR B))) &
" with A=" & integer'image(to_integer(unsigned(A))) &
" and B=" & integer'image(to_integer(unsigned(B))) &
" but instead R was " & integer'image(to_integer(unsigned(R)))
severity ERROR;
count_logic := count_logic + 1;
else
--nada
end if;
B <= B + "0001";
end loop;
A <= A + "0001";
end loop;
---------------------------
-- Shift Rotate
---------------------------
-- TEST Rotate Left
A <= "0000";
B <= "0000";
op <= "11X000";
wait for 1 ns;
for i in 0 to 15 loop
for j in 0 to 15 loop
wait for 1 ns;
if NOT(R = std_logic_vector(rotate_left(unsigned(A),to_integer(unsigned(B)))))
then
assert R = std_logic_vector(rotate_left(unsigned(A),to_integer(unsigned(B))))
report "R = A rol B should have been " &
integer'image(to_integer(rotate_left(unsigned(A),to_integer(unsigned(B))))) &
" with A=" & integer'image(to_integer(unsigned(A))) &
" and B=" & integer'image(to_integer(unsigned(B))) &
" but instead R was " & integer'image(to_integer(unsigned(R)))
severity ERROR;
count_shift_rot := count_shift_rot + 1;
else
--nada
end if;
B <= B + "0001";
end loop;
A <= A + "0001";
end loop;
-- TEST Rotate Right
A <= "0000";
B <= "0000";
op <= "11X001";
wait for 1 ns;
for i in 0 to 15 loop
for j in 0 to 15 loop
wait for 1 ns;
if NOT(R = std_logic_vector(rotate_right(unsigned(A),to_integer(unsigned(B)))))
then
assert R = std_logic_vector(rotate_right(unsigned(A),to_integer(unsigned(B))))
report "R = A rol B should have been " &
integer'image(to_integer(rotate_right(unsigned(A),to_integer(unsigned(B))))) &
" with A=" & integer'image(to_integer(unsigned(A))) &
" and B=" & integer'image(to_integer(unsigned(B))) &
" but instead R was " & integer'image(to_integer(unsigned(R)))
severity ERROR;
count_shift_rot := count_shift_rot + 1;
else
--nada
end if;
B <= B + "0001";
end loop;
A <= A + "0001";
end loop;
-- TEST Shift Left Logical
A <= "0000";
B <= "0000";
op <= "11X010";
wait for 1 ns;
for i in 0 to 15 loop
for j in 0 to 15 loop
wait for 1 ns;
if NOT(R = std_logic_vector(shift_left(unsigned(A),to_integer(unsigned(B)))))
then
assert R = std_logic_vector(shift_left(unsigned(A),to_integer(unsigned(B))))
report "R = A sll B should have been " &
integer'image(to_integer(shift_left(unsigned(A),to_integer(unsigned(B))))) &
" with A=" & integer'image(to_integer(unsigned(A))) &
" and B=" & integer'image(to_integer(unsigned(B))) &
" but instead R was " & integer'image(to_integer(unsigned(R)))
severity ERROR;
count_shift_rot := count_shift_rot + 1;
else
--nada
end if;
B <= B + "0001";
end loop;
A <= A + "0001";
end loop;
-- TEST Shift Right Logical
A <= "0000";
B <= "0000";
op <= "11X011";
wait for 1 ns;
for i in 0 to 15 loop
for j in 0 to 15 loop
wait for 1 ns;
if NOT(R = std_logic_vector(shift_right(unsigned(A),to_integer(unsigned(B)))))
then
assert R = std_logic_vector(shift_right(unsigned(A),to_integer(unsigned(B))))
report "R = A srl B should have been " &
integer'image(to_integer(shift_right(unsigned(A),to_integer(unsigned(B))))) &
" with A=" & integer'image(to_integer(unsigned(A))) &
" and B=" & integer'image(to_integer(unsigned(B))) &
" but instead R was " & integer'image(to_integer(unsigned(R)))
severity ERROR;
count_shift_rot := count_shift_rot + 1;
else
--nada
end if;
B <= B + "0001";
end loop;
A <= A + "0001";
end loop;
-- TEST Shift Right Arithmetic
A <= "0000";
B <= "0000";
op <= "11X111";
wait for 1 ns;
for i in 0 to 15 loop
for j in 0 to 15 loop
wait for 1 ns;
if NOT(R = std_logic_vector(shift_right(signed(A),to_integer(unsigned(B)))))
then
assert R = std_logic_vector(shift_right(signed(A),to_integer(unsigned(B))))
report "R = A sra B should have been " &
integer'image(to_integer(shift_right(signed(A),to_integer(unsigned(B))))) &
" with A=" & integer'image(to_integer(unsigned(A))) &
" and B=" & integer'image(to_integer(unsigned(B))) &
" but instead R was " & integer'image(to_integer(signed(R)))
severity ERROR;
count_shift_rot := count_shift_rot + 1;
else
--nada
end if;
B <= B + "0001";
end loop;
A <= A + "0001";
end loop;
---------------------------
-- Testing Complete.
---------------------------
-- Spit out error reports
report "TEST FINISHED.";
report "ERROR COUNT add_sub: " & integer'image(count_add_sub);
report "ERROR COUNT comparator: " & integer'image(count_comp);
report "ERROR COUNT logical/bitwise: " & integer'image(count_logic);
report "ERROR COUNT shift_rotate: " & integer'image(count_shift_rot);
wait;
end process;
END;
|
agpl-3.0
|
b5c1000f53063d005d643bfd12499acc
| 0.512303 | 3.570095 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 3/ALU_tb.vhd
| 1 | 7,200 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ALU_tb IS
END ALU_tb;
ARCHITECTURE behavior OF ALU_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU
PORT(
Oper1 : IN std_logic_vector(31 downto 0);
Oper2 : IN std_logic_vector(31 downto 0);
ALUOP : IN std_logic_vector(5 downto 0);
C: IN std_logic;
ALURESULT : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Oper1 : std_logic_vector(31 downto 0) := (others => '0');
signal Oper2 : std_logic_vector(31 downto 0) := (others => '0');
signal ALUOP : std_logic_vector(5 downto 0) := (others => '0');
signal C : std_logic:='0';
--Outputs
signal ALURESULT : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU PORT MAP (
Oper1 => Oper1,
Oper2 => Oper2,
ALUOP => ALUOP,
C => C,
ALURESULT => ALURESULT
);
-- Stimulus process
stim_proc: process
begin
C<='1';
------------------SUB-------------------------------
ALUOP<="000111";
-- 5 - 28
Oper1<="00000000000000000000000000000101"; -- +5
Oper2<="00000000000000000000000000011100"; -- +28
wait for 20 ns;
-- 32 - 20
Oper1<="00000000000000000000000000100000";-- +32
Oper2<="00000000000000000000000000010100";-- +20
wait for 20 ns;
-- -45 - (+33)
Oper1<="11111111111111111111111111010011";-- -45
Oper2<="00000000000000000000000000100001";-- +33
wait for 20 ns;
-- -45 - (+63)
Oper1<="11111111111111111111111111010011";-- -45
Oper2<="00000000000000000000000000111111";-- +63
wait for 20 ns;
-- -45 - (-33)
Oper1<="11111111111111111111111111010011";-- -45
Oper2<="11111111111111111111111111011111";-- -33
wait for 20 ns;
-- -45 - (-63)
Oper1<="11111111111111111111111111010011";-- -45
Oper2<="11111111111111111111111111000001";-- -63
wait for 20 ns;
-- 45 - (-63)
Oper1<="00000000000000000000000000101101";-- 45
Oper2<="11111111111111111111111111000001";-- -63
wait for 20 ns;
-- 45 - (-33)
Oper1<="00000000000000000000000000101101";-- 45
Oper2<="11111111111111111111111111011111";-- -33
wait for 20 ns;
----------------SUMA----------------
ALUOP<="000110";-- 75 + 25
Oper1<="00000000000000000000000001001011";-- 75
Oper2<="00000000000000000000000000011001";-- 25
wait for 20 ns;
-- 75 + (-25)
Oper1<="00000000000000000000000001001011";-- 75
Oper2<="11111111111111111111111111100111";-- -25
wait for 20 ns;
-- 75 + (-100)
Oper1<="00000000000000000000000001001011";-- 75
Oper2<="11111111111111111111111110011100";-- -100
wait for 20 ns;
-- -75 + 25
Oper1<="11111111111111111111111110110101";-- -75
Oper2<="00000000000000000000000000011001";-- 25
wait for 20 ns;
-- -75 + 100
Oper1<="11111111111111111111111110110101";-- -75
Oper2<="00000000000000000000000001100100";-- +100
wait for 20 ns;
-- -75 + (-25)
Oper1<="11111111111111111111111110110101";-- -75
Oper2<="11111111111111111111111111100111";-- -25
wait for 20 ns;
-- -75 + (-100)
Oper1<="11111111111111111111111110110101";-- -75
Oper2<="11111111111111111111111110011100";-- -100
wait for 20 ns;
-------------------OR--------------------
ALUOP<="000010";
Oper1<="11111111111111111100011110110101";
Oper2<="00000011101010001001010000001100";
wait for 20 ns;
-----------------orn---------------------
ALUOP<="000011";
wait for 20 ns;
-----------------xor-------------------
ALUOP<="000100";
wait for 20 ns;
-----------------xnor-------------------
ALUOP<="000101";
wait for 20 ns;
-----------------and-------------------
ALUOP<="000000";
wait for 20 ns;
-----------------andn-------------------
ALUOP<="000001";
wait for 20 ns;
------------------------Instrucciones aritmetico logicas no definidas-----------------------
-----------------SLL------------------
ALUOP<="001000";
Oper1<="00000000000000011110001110011011";
Oper2<="00000000000000000000000000000011";
wait for 20 ns;
-----------------SRL-------------------
ALUOP<="001001";
Oper1<="11111000000000011110001110011011";
Oper2<="00000000000000000000000000000011";
wait for 20 ns;
-----------------SRA----------------------
ALUOP<="001010";
Oper1<="11111000000000011110001110011011";
Oper2<="00000000000000000000000000000011";
wait for 20 ns;
-----------------ANDcc---------------------
ALUOP<="001011";
Oper1<="00000111111000000010010000000111";
Oper2<="00000111111111000000000000000011";
wait for 20 ns;
-----------------ANDNcc--------------------
ALUOP<="001100";
Oper1<="00000000111111111000000010100000";
Oper2<="00001111111100000000000000000011";
wait for 20 ns;
-----------------ORcc----------------------
ALUOP<="001101";
Oper1<="00000001111111111100000000000000";
Oper2<="11111000000000111111110000000000";
wait for 20 ns;
-----------------ORNcc---------------------
ALUOP<="001110";
Oper1<="00000011111111100000011111000000";
Oper2<="00000000001111111111111100000000";
wait for 20 ns;
-----------------XORcc---------------------
ALUOP<="001111";
Oper1<="00001000100000000111111111100000";
Oper2<="00000001111110000110000011000000";
wait for 20 ns;
-----------------XNORcc--------------------
ALUOP<="010000";
Oper1<="00000001111111111100000000000111";
Oper2<="11110000001111100000110001000000";
wait for 20 ns;
-----------------ADDcc---------------------
ALUOP<="010001";
Oper1<="00000000000000000000000001101000";
Oper2<="00000000000000000000000000000101";
wait for 20 ns;
-----------------ADDX----------------------
ALUOP<="010010";
Oper1<="00000000000000100101010000000000";
Oper2<="00000000000000000000000100000011";
wait for 20 ns;
-----------------ADDXcc--------------------
ALUOP<="010011";
Oper1<="00000000000000000000000000101010";
Oper2<="00000000000000000000000000001101";
wait for 20 ns;
-----------------SUBcc---------------------
ALUOP<="010100";
Oper1<="00000000000000000000000100000000";
Oper2<="00000000000000000000000000010000";
wait for 20 ns;
-----------------SUBX----------------------
ALUOP<="010101";
Oper1<="00000000000000000000000000001111";
Oper2<="00000000000000000000000000001011";
wait for 20 ns;
-----------------SUBXcc--------------------
ALUOP<="010110";
Oper1<="00000000000000000000000100011011";
Oper2<="00000000000000000000000000000011";
wait for 20 ns;
-----------------SAVE----------------------
ALUOP<="010111";
Oper1<="00000000000000000000000000011011";
Oper2<="00000000000000000000000000001100";
wait for 20 ns;
-----------------RESTORE-------------------
ALUOP<="011000";
Oper1<="00000000000000000000000000010000";
Oper2<="00000000000000000000000000000111";
wait for 20 ns;
---------------Instrucciones no definidas--------------------------
ALUOP<="111111";
Oper1<="00000000000000011110001110011011";
Oper2<="00000000000000000000000011111111";
wait;
end process;
END;
|
mit
|
3552b027a5fb2f770ab8f65cfccfac23
| 0.575694 | 4.55408 | false | false | false | false |
KPU-RISC/KPU
|
VHDL/SHL8Bit.vhd
| 1 | 1,348 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/20/2015 05:54:19 PM
-- Design Name:
-- Module Name: SHL8Bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SHL8Bit is
Port
(
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
Cout : out BIT -- Carry-out flag
);
end SHL8Bit;
architecture Behavioral of SHL8Bit is
begin
Cout <= Input(7);
Output(0) <= '0';
Output(1) <= Input(0);
Output(2) <= Input(1);
Output(3) <= Input(2);
Output(4) <= Input(3);
Output(5) <= Input(4);
Output(6) <= Input(5);
Output(7) <= Input(6);
end Behavioral;
|
mit
|
b14c70d840a2711d4450c607c4ef3dbe
| 0.546736 | 3.765363 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_gpio_1_0/synth/system_axi_gpio_1_0.vhd
| 1 | 10,187 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_13;
USE axi_gpio_v2_0_13.axi_gpio;
ENTITY system_axi_gpio_1_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END system_axi_gpio_1_0;
ARCHITECTURE system_axi_gpio_1_0_arch OF system_axi_gpio_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_gpio_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_axi_gpio_1_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_axi_gpio_1_0_arch : ARCHITECTURE IS "system_axi_gpio_1_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_axi_gpio_1_0_arch: ARCHITECTURE IS "system_axi_gpio_1_0,axi_gpio,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=13,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=16,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=1,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 16,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 1,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
ip2intc_irpt => ip2intc_irpt,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END system_axi_gpio_1_0_arch;
|
apache-2.0
|
85daa891937c494b1f06517bda88e1ee
| 0.688132 | 3.166615 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 3/MUX_PCSOURCE.vhd
| 1 | 733 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX_PCSOURCE is
Port ( PCdisp30 : in STD_LOGIC_VECTOR (31 downto 0);
PCSEUdisp22 : in STD_LOGIC_VECTOR (31 downto 0);
ALURESULT : in STD_LOGIC_VECTOR (31 downto 0);
PC : in STD_LOGIC_VECTOR(31 downto 0);
PCSOURCE : in STD_LOGIC_VECTOR (1 downto 0);
nPC : out STD_LOGIC_VECTOR (31 downto 0));
end MUX_PCSOURCE;
architecture Behavioral of MUX_PCSOURCE is
begin
process(PC,PCdisp30,PCSEUdisp22,ALURESULT,PCSOURCE)
begin
case PCSOURCE is
when "00"=>nPC<=PCdisp30;
when "01"=>nPC<=PCSEUdisp22;
when "10"=>nPC<=PC;
when others=>nPC<=ALURESULT;--11
end case;
end process;
end Behavioral;
|
mit
|
acf9caf03861cc940f68dc4d79cc95e2
| 0.639836 | 3.331818 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_xadc_wiz_0_0/system_xadc_wiz_0_0.vhd
| 1 | 15,371 |
-- file: system_xadc_wiz_0_0.vhd
-- (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xadc_wiz_0_0 is
port
(
-- System interface
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
-- AXI Write address channel signals
s_axi_awaddr : in std_logic_vector(10 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
-- AXI Write data channel signals
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
-- AXI Write response channel signals
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
-- AXI Read address channel signals
s_axi_araddr : in std_logic_vector(10 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
-- AXI Read address channel signals
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Input to the system from the axi_xadc core
ip2intc_irpt : out std_logic;
vauxp0 : in STD_LOGIC; -- Auxiliary Channel 0
vauxn0 : in STD_LOGIC;
vauxp1 : in STD_LOGIC; -- Auxiliary Channel 1
vauxn1 : in STD_LOGIC;
vauxp2 : in STD_LOGIC; -- Auxiliary Channel 2
vauxn2 : in STD_LOGIC;
vauxp4 : in STD_LOGIC; -- Auxiliary Channel 4
vauxn4 : in STD_LOGIC;
vauxp5 : in STD_LOGIC; -- Auxiliary Channel 5
vauxn5 : in STD_LOGIC;
vauxp6 : in STD_LOGIC; -- Auxiliary Channel 6
vauxn6 : in STD_LOGIC;
vauxp7 : in STD_LOGIC; -- Auxiliary Channel 7
vauxn7 : in STD_LOGIC;
vauxp9 : in STD_LOGIC; -- Auxiliary Channel 9
vauxn9 : in STD_LOGIC;
vauxp10 : in STD_LOGIC; -- Auxiliary Channel 10
vauxn10 : in STD_LOGIC;
vauxp12 : in STD_LOGIC; -- Auxiliary Channel 12
vauxn12 : in STD_LOGIC;
vauxp13 : in STD_LOGIC; -- Auxiliary Channel 13
vauxn13 : in STD_LOGIC;
vauxp14 : in STD_LOGIC; -- Auxiliary Channel 14
vauxn14 : in STD_LOGIC;
vauxp15 : in STD_LOGIC; -- Auxiliary Channel 15
vauxn15 : in STD_LOGIC;
busy_out : out STD_LOGIC; -- ADC Busy signal
channel_out : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs
eoc_out : out STD_LOGIC; -- End of Conversion Signal
eos_out : out STD_LOGIC; -- End of Sequence Signal
vccaux_alarm_out : out STD_LOGIC; -- VCCAUX-sensor alarm output
vccint_alarm_out : out STD_LOGIC; -- VCCINT-sensor alarm output
user_temp_alarm_out : out STD_LOGIC; -- Temperature-sensor alarm output
alarm_out : out STD_LOGIC; -- OR'ed output of all the Alarms
temp_out : out std_logic_vector(11 downto 0);
vp_in : in STD_LOGIC; -- Dedicated Analog Input Pair
vn_in : in STD_LOGIC
);
end system_xadc_wiz_0_0;
architecture xilinx of system_xadc_wiz_0_0 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "system_xadc_wiz_0_0,xadc_wiz_v3_3_2,{component_name=system_xadc_wiz_0_0,enable_axi=true,enable_axi4stream=false,dclk_frequency=100,enable_busy=true,enable_convst=false,enable_convstclk=false,enable_dclk=true,enable_drp=false,enable_eoc=true,enable_eos=true,enable_vbram_alaram=false,enable_vccddro_alaram=false,enable_Vccint_Alaram=true,enable_Vccaux_alaram=trueenable_vccpaux_alaram=false,enable_vccpint_alaram=false,ot_alaram=false,user_temp_alaram=true,timing_mode=continuous,channel_averaging=None,sequencer_mode=on,startup_channel_selection=contineous_sequence}";
component system_xadc_wiz_0_0_axi_xadc
generic
(
-----------------------------------------
-- C_BASEADDR : std_logic_vector := X"FFFF_FFFF";
-- C_HIGHADDR : std_logic_vector := X"0000_0000";
-----------------------------------------
-- AXI slave single block generics
C_INSTANCE : string := "system_xadc_wiz_0_0_axi_xadc";
C_FAMILY : string := "virtex7";
C_S_AXI_ADDR_WIDTH : integer range 2 to 32 := 11;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
-----------------------------------------
-- SYSMON Generics
C_INCLUDE_INTR : integer range 0 to 1 := 1;
C_SIM_MONITOR_FILE : string := "design.txt"
);
port
(
-- System interface
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
-- AXI Write address channel signals
s_axi_awaddr : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
-- AXI Write data channel signals
s_axi_wdata : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_wstrb : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
-- AXI Write response channel signals
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
-- AXI Read address channel signals
s_axi_araddr : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
-- AXI Read address channel signals
s_axi_rdata : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Input to the system from the axi_xadc core
ip2intc_irpt : out std_logic;
-- XADC External interface signals
-- Conversion start control signal for Event driven mode
vauxp0 : in STD_LOGIC; -- Auxiliary Channel 0
vauxn0 : in STD_LOGIC;
vauxp1 : in STD_LOGIC; -- Auxiliary Channel 1
vauxn1 : in STD_LOGIC;
vauxp2 : in STD_LOGIC; -- Auxiliary Channel 2
vauxn2 : in STD_LOGIC;
vauxp4 : in STD_LOGIC; -- Auxiliary Channel 4
vauxn4 : in STD_LOGIC;
vauxp5 : in STD_LOGIC; -- Auxiliary Channel 5
vauxn5 : in STD_LOGIC;
vauxp6 : in STD_LOGIC; -- Auxiliary Channel 6
vauxn6 : in STD_LOGIC;
vauxp7 : in STD_LOGIC; -- Auxiliary Channel 7
vauxn7 : in STD_LOGIC;
vauxp9 : in STD_LOGIC; -- Auxiliary Channel 9
vauxn9 : in STD_LOGIC;
vauxp10 : in STD_LOGIC; -- Auxiliary Channel 10
vauxn10 : in STD_LOGIC;
vauxp12 : in STD_LOGIC; -- Auxiliary Channel 12
vauxn12 : in STD_LOGIC;
vauxp13 : in STD_LOGIC; -- Auxiliary Channel 13
vauxn13 : in STD_LOGIC;
vauxp14 : in STD_LOGIC; -- Auxiliary Channel 14
vauxn14 : in STD_LOGIC;
vauxp15 : in STD_LOGIC; -- Auxiliary Channel 15
vauxn15 : in STD_LOGIC;
busy_out : out STD_LOGIC; -- ADC Busy signal
channel_out : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs
eoc_out : out STD_LOGIC; -- End of Conversion Signal
eos_out : out STD_LOGIC; -- End of Sequence Signal
alarm_out : out STD_LOGIC_VECTOR(7 downto 0);
temp_out : out std_logic_vector(11 downto 0);
vp_in : in STD_LOGIC; -- Dedicated Analog Input Pair
vn_in : in STD_LOGIC
);
end component;
signal alm_int : std_logic_vector (7 downto 0);
begin
alarm_out <= alm_int(7);
vccaux_alarm_out <= alm_int(2);
vccint_alarm_out <= alm_int(1);
user_temp_alarm_out <= alm_int(0);
U0 : system_xadc_wiz_0_0_axi_xadc
generic map
(
C_INSTANCE => "system_xadc_wiz_0_0_axi_xadc",
C_FAMILY => "virtex7",
C_S_AXI_ADDR_WIDTH => 11,
C_S_AXI_DATA_WIDTH => 32,
C_INCLUDE_INTR => 1,
C_SIM_MONITOR_FILE => "design.txt"
)
port map
(
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
ip2intc_irpt => ip2intc_irpt,
vauxp0 => vauxp0,
vauxn0 => vauxn0,
vauxp1 => vauxp1,
vauxn1 => vauxn1,
vauxp2 => vauxp2,
vauxn2 => vauxn2,
vauxp4 => vauxp4,
vauxn4 => vauxn4,
vauxp5 => vauxp5,
vauxn5 => vauxn5,
vauxp6 => vauxp6,
vauxn6 => vauxn6,
vauxp7 => vauxp7,
vauxn7 => vauxn7,
vauxp9 => vauxp9,
vauxn9 => vauxn9,
vauxp10 => vauxp10,
vauxn10 => vauxn10,
vauxp12 => vauxp12,
vauxn12 => vauxn12,
vauxp13 => vauxp13,
vauxn13 => vauxn13,
vauxp14 => vauxp14,
vauxn14 => vauxn14,
vauxp15 => vauxp15,
vauxn15 => vauxn15,
busy_out => busy_out,
channel_out => channel_out,
eoc_out => eoc_out,
eos_out => eos_out,
alarm_out => alm_int,
temp_out => temp_out,
vp_in => vp_in,
vn_in => vn_in
);
end xilinx;
|
apache-2.0
|
f487476b1d82ac39b9d6599e29a2e9f8
| 0.485785 | 4.275661 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 1/ALU.vhd
| 1 | 988 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ALU is
Port ( Oper1 : in STD_LOGIC_VECTOR (31 downto 0);
Oper2 : in STD_LOGIC_VECTOR (31 downto 0);
ALUOP : in STD_LOGIC_VECTOR (5 downto 0);
ALURESULT : out STD_LOGIC_VECTOR (31 downto 0));
end ALU;
architecture Behavioral of ALU is
begin
process(Oper1,Oper2,ALUOP)
begin
case ALUOP is
when "000000"=>
ALURESULT<=Oper1 and Oper2;
when "000001"=>
ALURESULT<=Oper1 and not Oper2;
when "000010"=>
ALURESULT<=Oper1 or Oper2;
when "000011"=>
ALURESULT<=Oper1 or not Oper2;
when "000100"=>
ALURESULT<=Oper1 xor Oper2;
when "000101"=>
ALURESULT<=Oper1 xnor Oper2;
when "000110"=>
ALURESULT<=Oper1+Oper2;
when "000111"=>
ALURESULT<=Oper1-Oper2;
when others=>--"111111" Instrucciones no definidas
ALURESULT<=(others=>'0');
end case;
end process;
end Behavioral;
|
mit
|
37e5a28877684f2ef227ff0a87339048
| 0.644737 | 3.187097 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_quad_spi_shield_0/sim/system_axi_quad_spi_shield_0.vhd
| 1 | 15,796 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_quad_spi:3.2
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_quad_spi_v3_2_10;
USE axi_quad_spi_v3_2_10.axi_quad_spi;
ENTITY system_axi_quad_spi_shield_0 IS
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END system_axi_quad_spi_shield_0;
ARCHITECTURE system_axi_quad_spi_shield_0_arch OF system_axi_quad_spi_shield_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_quad_spi_shield_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_quad_spi IS
GENERIC (
Async_Clk : INTEGER;
C_FAMILY : STRING;
C_SELECT_XPM : INTEGER;
C_SUB_FAMILY : STRING;
C_INSTANCE : STRING;
C_SPI_MEM_ADDR_BITS : INTEGER;
C_TYPE_OF_AXI4_INTERFACE : INTEGER;
C_XIP_MODE : INTEGER;
C_UC_FAMILY : INTEGER;
C_FIFO_DEPTH : INTEGER;
C_SCK_RATIO : INTEGER;
C_DUAL_QUAD_MODE : INTEGER;
C_NUM_SS_BITS : INTEGER;
C_NUM_TRANSFER_BITS : INTEGER;
C_SPI_MODE : INTEGER;
C_USE_STARTUP : INTEGER;
C_USE_STARTUP_EXT : INTEGER;
C_SPI_MEMORY : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI4_ADDR_WIDTH : INTEGER;
C_S_AXI4_DATA_WIDTH : INTEGER;
C_S_AXI4_ID_WIDTH : INTEGER;
C_SHARED_STARTUP : INTEGER;
C_S_AXI4_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI4_HIGHADDR : STD_LOGIC_VECTOR;
C_LSB_STUP : INTEGER
);
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi4_aclk : IN STD_LOGIC;
s_axi4_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi4_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_awaddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_awlock : IN STD_LOGIC;
s_axi4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awvalid : IN STD_LOGIC;
s_axi4_awready : OUT STD_LOGIC;
s_axi4_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_wlast : IN STD_LOGIC;
s_axi4_wvalid : IN STD_LOGIC;
s_axi4_wready : OUT STD_LOGIC;
s_axi4_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_bvalid : OUT STD_LOGIC;
s_axi4_bready : IN STD_LOGIC;
s_axi4_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_araddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_arlock : IN STD_LOGIC;
s_axi4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arvalid : IN STD_LOGIC;
s_axi4_arready : OUT STD_LOGIC;
s_axi4_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_rlast : OUT STD_LOGIC;
s_axi4_rvalid : OUT STD_LOGIC;
s_axi4_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
io2_i : IN STD_LOGIC;
io2_o : OUT STD_LOGIC;
io2_t : OUT STD_LOGIC;
io3_i : IN STD_LOGIC;
io3_o : OUT STD_LOGIC;
io3_t : OUT STD_LOGIC;
io0_1_i : IN STD_LOGIC;
io0_1_o : OUT STD_LOGIC;
io0_1_t : OUT STD_LOGIC;
io1_1_i : IN STD_LOGIC;
io1_1_o : OUT STD_LOGIC;
io1_1_t : OUT STD_LOGIC;
io2_1_i : IN STD_LOGIC;
io2_1_o : OUT STD_LOGIC;
io2_1_t : OUT STD_LOGIC;
io3_1_i : IN STD_LOGIC;
io3_1_o : OUT STD_LOGIC;
io3_1_t : OUT STD_LOGIC;
spisel : IN STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
ss_1_i : IN STD_LOGIC;
ss_1_o : OUT STD_LOGIC;
ss_1_t : OUT STD_LOGIC;
cfgclk : OUT STD_LOGIC;
cfgmclk : OUT STD_LOGIC;
eos : OUT STD_LOGIC;
preq : OUT STD_LOGIC;
clk : IN STD_LOGIC;
gsr : IN STD_LOGIC;
gts : IN STD_LOGIC;
keyclearb : IN STD_LOGIC;
usrcclkts : IN STD_LOGIC;
usrdoneo : IN STD_LOGIC;
usrdonets : IN STD_LOGIC;
pack : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END COMPONENT axi_quad_spi;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ext_spi_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 spi_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 lite_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 lite_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF io0_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_I";
ATTRIBUTE X_INTERFACE_INFO OF io0_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_O";
ATTRIBUTE X_INTERFACE_INFO OF io0_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_T";
ATTRIBUTE X_INTERFACE_INFO OF io1_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_I";
ATTRIBUTE X_INTERFACE_INFO OF io1_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_O";
ATTRIBUTE X_INTERFACE_INFO OF io1_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_T";
ATTRIBUTE X_INTERFACE_INFO OF sck_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_I";
ATTRIBUTE X_INTERFACE_INFO OF sck_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_O";
ATTRIBUTE X_INTERFACE_INFO OF sck_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_T";
ATTRIBUTE X_INTERFACE_INFO OF ss_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_I";
ATTRIBUTE X_INTERFACE_INFO OF ss_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_O";
ATTRIBUTE X_INTERFACE_INFO OF ss_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_T";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
BEGIN
U0 : axi_quad_spi
GENERIC MAP (
Async_Clk => 0,
C_FAMILY => "artix7",
C_SELECT_XPM => 0,
C_SUB_FAMILY => "artix7",
C_INSTANCE => "axi_quad_spi_inst",
C_SPI_MEM_ADDR_BITS => 24,
C_TYPE_OF_AXI4_INTERFACE => 0,
C_XIP_MODE => 0,
C_UC_FAMILY => 0,
C_FIFO_DEPTH => 16,
C_SCK_RATIO => 16,
C_DUAL_QUAD_MODE => 0,
C_NUM_SS_BITS => 1,
C_NUM_TRANSFER_BITS => 8,
C_SPI_MODE => 0,
C_USE_STARTUP => 0,
C_USE_STARTUP_EXT => 0,
C_SPI_MEMORY => 1,
C_S_AXI_ADDR_WIDTH => 7,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI4_ADDR_WIDTH => 24,
C_S_AXI4_DATA_WIDTH => 32,
C_S_AXI4_ID_WIDTH => 1,
C_SHARED_STARTUP => 0,
C_S_AXI4_BASEADDR => X"FFFFFFFF",
C_S_AXI4_HIGHADDR => X"00000000",
C_LSB_STUP => 0
)
PORT MAP (
ext_spi_clk => ext_spi_clk,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi4_aclk => '0',
s_axi4_aresetn => '0',
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi4_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_awlock => '0',
s_axi4_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awvalid => '0',
s_axi4_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi4_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_wlast => '0',
s_axi4_wvalid => '0',
s_axi4_bready => '0',
s_axi4_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_arlock => '0',
s_axi4_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arvalid => '0',
s_axi4_rready => '0',
io0_i => io0_i,
io0_o => io0_o,
io0_t => io0_t,
io1_i => io1_i,
io1_o => io1_o,
io1_t => io1_t,
io2_i => '0',
io3_i => '0',
io0_1_i => '0',
io1_1_i => '0',
io2_1_i => '0',
io3_1_i => '0',
spisel => '1',
sck_i => sck_i,
sck_o => sck_o,
sck_t => sck_t,
ss_i => ss_i,
ss_o => ss_o,
ss_t => ss_t,
ss_1_i => '0',
clk => '0',
gsr => '0',
gts => '0',
keyclearb => '0',
usrcclkts => '0',
usrdoneo => '1',
usrdonets => '0',
pack => '0',
ip2intc_irpt => ip2intc_irpt
);
END system_axi_quad_spi_shield_0_arch;
|
apache-2.0
|
6dd685658fecf5a7c29329d860661960
| 0.635541 | 3.009909 | false | false | false | false |
daniw/add
|
edk/IVK_HW/t01_hello/hdl/leds_8bit_wrapper.vhd
| 1 | 7,771 |
-------------------------------------------------------------------------------
-- leds_8bit_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_gpio_v2_00_a;
use xps_gpio_v2_00_a.all;
entity leds_8bit_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 3);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 31);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 31);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MWrErr : out std_logic_vector(0 to 1);
Sl_MRdErr : out std_logic_vector(0 to 1);
Sl_MIRQ : out std_logic_vector(0 to 1);
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(0 to 7);
GPIO_IO_O : out std_logic_vector(0 to 7);
GPIO_IO_T : out std_logic_vector(0 to 7);
GPIO2_IO_I : in std_logic_vector(0 to 31);
GPIO2_IO_O : out std_logic_vector(0 to 31);
GPIO2_IO_T : out std_logic_vector(0 to 31)
);
attribute x_core_info : STRING;
attribute x_core_info of leds_8bit_wrapper : entity is "xps_gpio_v2_00_a";
end leds_8bit_wrapper;
architecture STRUCTURE of leds_8bit_wrapper is
component xps_gpio is
generic (
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_SPLB_AWIDTH : INTEGER;
C_SPLB_DWIDTH : INTEGER;
C_SPLB_P2P : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_NATIVE_DWIDTH : INTEGER;
C_SPLB_SUPPORT_BURSTS : INTEGER;
C_FAMILY : STRING;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : std_logic_vector;
C_TRI_DEFAULT : std_logic_vector;
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : std_logic_vector;
C_TRI_DEFAULT_2 : std_logic_vector
);
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(0 to (C_GPIO_WIDTH-1));
GPIO_IO_O : out std_logic_vector(0 to (C_GPIO_WIDTH-1));
GPIO_IO_T : out std_logic_vector(0 to (C_GPIO_WIDTH-1));
GPIO2_IO_I : in std_logic_vector(0 to (C_GPIO2_WIDTH-1));
GPIO2_IO_O : out std_logic_vector(0 to (C_GPIO2_WIDTH-1));
GPIO2_IO_T : out std_logic_vector(0 to (C_GPIO2_WIDTH-1))
);
end component;
begin
LEDs_8Bit : xps_gpio
generic map (
C_BASEADDR => X"81420000",
C_HIGHADDR => X"8142ffff",
C_SPLB_AWIDTH => 32,
C_SPLB_DWIDTH => 32,
C_SPLB_P2P => 0,
C_SPLB_MID_WIDTH => 1,
C_SPLB_NUM_MASTERS => 2,
C_SPLB_NATIVE_DWIDTH => 32,
C_SPLB_SUPPORT_BURSTS => 0,
C_FAMILY => "spartan6",
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 32,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"ffffffff",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"ffffffff"
)
port map (
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
IP2INTC_Irpt => IP2INTC_Irpt,
GPIO_IO_I => GPIO_IO_I,
GPIO_IO_O => GPIO_IO_O,
GPIO_IO_T => GPIO_IO_T,
GPIO2_IO_I => GPIO2_IO_I,
GPIO2_IO_O => GPIO2_IO_O,
GPIO2_IO_T => GPIO2_IO_T
);
end architecture STRUCTURE;
|
gpl-2.0
|
2675d7e1464d7525be1b4e538d1c0a6a
| 0.583065 | 3.073972 | false | false | false | false |
daniw/add
|
edk/IVK_HW/t01_hello/hdl/push_buttons_3bit_wrapper.vhd
| 1 | 7,819 |
-------------------------------------------------------------------------------
-- push_buttons_3bit_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_gpio_v2_00_a;
use xps_gpio_v2_00_a.all;
entity push_buttons_3bit_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 3);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 31);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 31);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MWrErr : out std_logic_vector(0 to 1);
Sl_MRdErr : out std_logic_vector(0 to 1);
Sl_MIRQ : out std_logic_vector(0 to 1);
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(0 to 2);
GPIO_IO_O : out std_logic_vector(0 to 2);
GPIO_IO_T : out std_logic_vector(0 to 2);
GPIO2_IO_I : in std_logic_vector(0 to 31);
GPIO2_IO_O : out std_logic_vector(0 to 31);
GPIO2_IO_T : out std_logic_vector(0 to 31)
);
attribute x_core_info : STRING;
attribute x_core_info of push_buttons_3bit_wrapper : entity is "xps_gpio_v2_00_a";
end push_buttons_3bit_wrapper;
architecture STRUCTURE of push_buttons_3bit_wrapper is
component xps_gpio is
generic (
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_SPLB_AWIDTH : INTEGER;
C_SPLB_DWIDTH : INTEGER;
C_SPLB_P2P : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_NATIVE_DWIDTH : INTEGER;
C_SPLB_SUPPORT_BURSTS : INTEGER;
C_FAMILY : STRING;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : std_logic_vector;
C_TRI_DEFAULT : std_logic_vector;
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : std_logic_vector;
C_TRI_DEFAULT_2 : std_logic_vector
);
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(0 to (C_GPIO_WIDTH-1));
GPIO_IO_O : out std_logic_vector(0 to (C_GPIO_WIDTH-1));
GPIO_IO_T : out std_logic_vector(0 to (C_GPIO_WIDTH-1));
GPIO2_IO_I : in std_logic_vector(0 to (C_GPIO2_WIDTH-1));
GPIO2_IO_O : out std_logic_vector(0 to (C_GPIO2_WIDTH-1));
GPIO2_IO_T : out std_logic_vector(0 to (C_GPIO2_WIDTH-1))
);
end component;
begin
Push_Buttons_3Bit : xps_gpio
generic map (
C_BASEADDR => X"81400000",
C_HIGHADDR => X"8140ffff",
C_SPLB_AWIDTH => 32,
C_SPLB_DWIDTH => 32,
C_SPLB_P2P => 0,
C_SPLB_MID_WIDTH => 1,
C_SPLB_NUM_MASTERS => 2,
C_SPLB_NATIVE_DWIDTH => 32,
C_SPLB_SUPPORT_BURSTS => 0,
C_FAMILY => "spartan6",
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 0,
C_GPIO_WIDTH => 3,
C_GPIO2_WIDTH => 32,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"ffffffff",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"ffffffff"
)
port map (
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
IP2INTC_Irpt => IP2INTC_Irpt,
GPIO_IO_I => GPIO_IO_I,
GPIO_IO_O => GPIO_IO_O,
GPIO_IO_T => GPIO_IO_T,
GPIO2_IO_I => GPIO2_IO_I,
GPIO2_IO_O => GPIO2_IO_O,
GPIO2_IO_T => GPIO2_IO_T
);
end architecture STRUCTURE;
|
gpl-2.0
|
4275bad5183749ab5fa0e680bbe07b00
| 0.584857 | 3.078346 | false | false | false | false |
jeffmagina/ECE368
|
Project1/DECODE/decode_tbd.vhd
| 1 | 2,845 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:45:55 03/24/2015
-- Design Name:
-- Module Name: C:/Users/Jeff Magina/Documents/GitHub/ECE368/Project1/DECODE/decode_tbd.vhd
-- Project Name: decode
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: decode
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY decode_tbd IS
END decode_tbd;
ARCHITECTURE behavior OF decode_tbd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT decode
PORT(
CLK : IN std_logic;
INST_IN : IN std_logic_vector(15 downto 0);
OPCODE : OUT std_logic_vector(3 downto 0);
REG_A : OUT std_logic_vector(3 downto 0);
REG_B : OUT std_logic_vector(3 downto 0);
IMMEDIATE : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal INST_IN : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal OPCODE : std_logic_vector(3 downto 0);
signal REG_A : std_logic_vector(3 downto 0);
signal REG_B : std_logic_vector(3 downto 0);
signal IMMEDIATE : std_logic_vector(3 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: decode PORT MAP (
CLK => CLK,
INST_IN => INST_IN,
OPCODE => OPCODE,
REG_A => REG_A,
REG_B => REG_B,
IMMEDIATE => IMMEDIATE
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
tb: process
begin
-- hold reset state for 100 ns.
wait for 20 ns;
report "Start Debug Test Bench!" severity Note;
INST_IN <= x"0FC0";
wait for CLK_period;
INST_IN <= x"1671";
wait for CLK_period;
INST_IN <= x"467A";
wait for CLK_period;
INST_IN <= x"0682";
wait for CLK_period;
wait for 100 ns;
wait;
end process;
END;
|
mit
|
693195f267e545e62a3afca13608226d
| 0.594025 | 3.743421 | false | true | false | false |
KPU-RISC/KPU
|
VHDL/Decoder4To16.vhd
| 1 | 2,407 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07/14/2015 04:50:10 PM
-- Design Name:
-- Module Name: Decoder4To16 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Decoder4To16 is
Port
(
F : in BIT_VECTOR(3 downto 0); -- 4-Bit Function Code (Input)
X : out BIT_VECTOR(15 downto 0) -- 16-Bit State (Output)
);
end Decoder4To16;
architecture Behavioral of Decoder4To16 is
begin
-- 0000
X(0) <= not(F(0)) and not(F(1)) and not (F(2)) and not(F(3)) after 1 ns;
-- 0001
X(1) <= F(0) and not (F(1)) and not (F(2)) and not(F(3)) after 1 ns;
-- 0010
X(2) <= not(F(0)) and F(1) and not (F(2)) and not(F(3)) after 1 ns;
-- 0011
X(3) <= F(0) and F(1) and not (F(2)) and not(F(3)) after 1 ns;
-- 0100
X(4) <= not(F(0)) and not(F(1)) and F(2) and not(F(3)) after 1 ns;
-- 0101
X(5) <= F(0) and not(F(1)) and F(2) and not(F(3)) after 1 ns;
-- 0110
X(6) <= not(F(0)) and F(1) and F(2) and not(F(3)) after 1 ns;
-- 0111
X(7) <= F(0) and F(1) and F(2) and not(F(3)) after 1 ns;
-- 1000
X(8) <= not(F(0)) and not(F(1)) and not(F(2)) and F(3) after 1 ns;
-- 1001
X(9) <= F(0) and not(F(1)) and not(F(2)) and F(3) after 1 ns;
-- 1010
X(10) <= not(F(0)) and F(1) and not(F(2)) and F(3) after 1 ns;
-- 1011
X(11) <= F(0) and F(1) and not(F(2)) and F(3) after 1 ns;
-- 1100
X(12) <= not(F(0)) and not(F(1)) and F(2) and F(3) after 1 ns;
-- 1101
X(13) <= F(0) and not(F(1)) and F(2) and F(3) after 1 ns;
-- 1110
X(14) <= not(F(0)) and F(1) and F(2) and F(3) after 1 ns;
-- 1111
X(15) <= F(0) and F(1) and F(2) and F(3) after 1 ns;
end Behavioral;
|
mit
|
330d21c46175ffc83062dac93633abae
| 0.508517 | 2.855279 | false | false | false | false |
daniw/add
|
edk/IVK_HW/t01_hello/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl/lmb_bram_elaborate.vhd
| 1 | 35,169 |
-------------------------------------------------------------------------------
-- lmb_bram_elaborate.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity lmb_bram_elaborate is
generic (
C_MEMSIZE : integer;
C_PORT_DWIDTH : integer;
C_PORT_AWIDTH : integer;
C_NUM_WE : integer;
C_FAMILY : string
);
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_A : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_A : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_A : in std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_B : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_B : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_B : in std_logic_vector(0 to C_PORT_DWIDTH-1)
);
attribute keep_hierarchy : STRING;
attribute keep_hierarchy of lmb_bram_elaborate : entity is "yes";
end lmb_bram_elaborate;
architecture STRUCTURE of lmb_bram_elaborate is
component RAMB16BWER is
generic (
INIT_FILE : string;
DATA_WIDTH_A : integer;
DATA_WIDTH_B : integer
);
port (
ADDRA : in std_logic_vector(13 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector(31 downto 0);
DIPA : in std_logic_vector(3 downto 0);
DOA : out std_logic_vector(31 downto 0);
DOPA : out std_logic_vector(3 downto 0);
ENA : in std_logic;
REGCEA : in std_logic;
RSTA : in std_logic;
WEA : in std_logic_vector(3 downto 0);
ADDRB : in std_logic_vector(13 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector(31 downto 0);
DIPB : in std_logic_vector(3 downto 0);
DOB : out std_logic_vector(31 downto 0);
DOPB : out std_logic_vector(3 downto 0);
ENB : in std_logic;
REGCEB : in std_logic;
RSTB : in std_logic;
WEB : in std_logic_vector(3 downto 0)
);
end component;
attribute BMM_INFO : STRING;
attribute BMM_INFO of ramb16bwer_0: label is " ";
attribute BMM_INFO of ramb16bwer_1: label is " ";
attribute BMM_INFO of ramb16bwer_2: label is " ";
attribute BMM_INFO of ramb16bwer_3: label is " ";
attribute BMM_INFO of ramb16bwer_4: label is " ";
attribute BMM_INFO of ramb16bwer_5: label is " ";
attribute BMM_INFO of ramb16bwer_6: label is " ";
attribute BMM_INFO of ramb16bwer_7: label is " ";
attribute BMM_INFO of ramb16bwer_8: label is " ";
attribute BMM_INFO of ramb16bwer_9: label is " ";
attribute BMM_INFO of ramb16bwer_10: label is " ";
attribute BMM_INFO of ramb16bwer_11: label is " ";
attribute BMM_INFO of ramb16bwer_12: label is " ";
attribute BMM_INFO of ramb16bwer_13: label is " ";
attribute BMM_INFO of ramb16bwer_14: label is " ";
attribute BMM_INFO of ramb16bwer_15: label is " ";
-- Internal signals
signal net_gnd0 : std_logic;
signal net_gnd4 : std_logic_vector(3 downto 0);
signal pgassign1 : std_logic_vector(0 to 0);
signal pgassign2 : std_logic_vector(0 to 29);
signal pgassign3 : std_logic_vector(13 downto 0);
signal pgassign4 : std_logic_vector(31 downto 0);
signal pgassign5 : std_logic_vector(31 downto 0);
signal pgassign6 : std_logic_vector(3 downto 0);
signal pgassign7 : std_logic_vector(13 downto 0);
signal pgassign8 : std_logic_vector(31 downto 0);
signal pgassign9 : std_logic_vector(31 downto 0);
signal pgassign10 : std_logic_vector(3 downto 0);
signal pgassign11 : std_logic_vector(13 downto 0);
signal pgassign12 : std_logic_vector(31 downto 0);
signal pgassign13 : std_logic_vector(31 downto 0);
signal pgassign14 : std_logic_vector(3 downto 0);
signal pgassign15 : std_logic_vector(13 downto 0);
signal pgassign16 : std_logic_vector(31 downto 0);
signal pgassign17 : std_logic_vector(31 downto 0);
signal pgassign18 : std_logic_vector(3 downto 0);
signal pgassign19 : std_logic_vector(13 downto 0);
signal pgassign20 : std_logic_vector(31 downto 0);
signal pgassign21 : std_logic_vector(31 downto 0);
signal pgassign22 : std_logic_vector(3 downto 0);
signal pgassign23 : std_logic_vector(13 downto 0);
signal pgassign24 : std_logic_vector(31 downto 0);
signal pgassign25 : std_logic_vector(31 downto 0);
signal pgassign26 : std_logic_vector(3 downto 0);
signal pgassign27 : std_logic_vector(13 downto 0);
signal pgassign28 : std_logic_vector(31 downto 0);
signal pgassign29 : std_logic_vector(31 downto 0);
signal pgassign30 : std_logic_vector(3 downto 0);
signal pgassign31 : std_logic_vector(13 downto 0);
signal pgassign32 : std_logic_vector(31 downto 0);
signal pgassign33 : std_logic_vector(31 downto 0);
signal pgassign34 : std_logic_vector(3 downto 0);
signal pgassign35 : std_logic_vector(13 downto 0);
signal pgassign36 : std_logic_vector(31 downto 0);
signal pgassign37 : std_logic_vector(31 downto 0);
signal pgassign38 : std_logic_vector(3 downto 0);
signal pgassign39 : std_logic_vector(13 downto 0);
signal pgassign40 : std_logic_vector(31 downto 0);
signal pgassign41 : std_logic_vector(31 downto 0);
signal pgassign42 : std_logic_vector(3 downto 0);
signal pgassign43 : std_logic_vector(13 downto 0);
signal pgassign44 : std_logic_vector(31 downto 0);
signal pgassign45 : std_logic_vector(31 downto 0);
signal pgassign46 : std_logic_vector(3 downto 0);
signal pgassign47 : std_logic_vector(13 downto 0);
signal pgassign48 : std_logic_vector(31 downto 0);
signal pgassign49 : std_logic_vector(31 downto 0);
signal pgassign50 : std_logic_vector(3 downto 0);
signal pgassign51 : std_logic_vector(13 downto 0);
signal pgassign52 : std_logic_vector(31 downto 0);
signal pgassign53 : std_logic_vector(31 downto 0);
signal pgassign54 : std_logic_vector(3 downto 0);
signal pgassign55 : std_logic_vector(13 downto 0);
signal pgassign56 : std_logic_vector(31 downto 0);
signal pgassign57 : std_logic_vector(31 downto 0);
signal pgassign58 : std_logic_vector(3 downto 0);
signal pgassign59 : std_logic_vector(13 downto 0);
signal pgassign60 : std_logic_vector(31 downto 0);
signal pgassign61 : std_logic_vector(31 downto 0);
signal pgassign62 : std_logic_vector(3 downto 0);
signal pgassign63 : std_logic_vector(13 downto 0);
signal pgassign64 : std_logic_vector(31 downto 0);
signal pgassign65 : std_logic_vector(31 downto 0);
signal pgassign66 : std_logic_vector(3 downto 0);
signal pgassign67 : std_logic_vector(13 downto 0);
signal pgassign68 : std_logic_vector(31 downto 0);
signal pgassign69 : std_logic_vector(31 downto 0);
signal pgassign70 : std_logic_vector(3 downto 0);
signal pgassign71 : std_logic_vector(13 downto 0);
signal pgassign72 : std_logic_vector(31 downto 0);
signal pgassign73 : std_logic_vector(31 downto 0);
signal pgassign74 : std_logic_vector(3 downto 0);
signal pgassign75 : std_logic_vector(13 downto 0);
signal pgassign76 : std_logic_vector(31 downto 0);
signal pgassign77 : std_logic_vector(31 downto 0);
signal pgassign78 : std_logic_vector(3 downto 0);
signal pgassign79 : std_logic_vector(13 downto 0);
signal pgassign80 : std_logic_vector(31 downto 0);
signal pgassign81 : std_logic_vector(31 downto 0);
signal pgassign82 : std_logic_vector(3 downto 0);
signal pgassign83 : std_logic_vector(13 downto 0);
signal pgassign84 : std_logic_vector(31 downto 0);
signal pgassign85 : std_logic_vector(31 downto 0);
signal pgassign86 : std_logic_vector(3 downto 0);
signal pgassign87 : std_logic_vector(13 downto 0);
signal pgassign88 : std_logic_vector(31 downto 0);
signal pgassign89 : std_logic_vector(31 downto 0);
signal pgassign90 : std_logic_vector(3 downto 0);
signal pgassign91 : std_logic_vector(13 downto 0);
signal pgassign92 : std_logic_vector(31 downto 0);
signal pgassign93 : std_logic_vector(31 downto 0);
signal pgassign94 : std_logic_vector(3 downto 0);
signal pgassign95 : std_logic_vector(13 downto 0);
signal pgassign96 : std_logic_vector(31 downto 0);
signal pgassign97 : std_logic_vector(31 downto 0);
signal pgassign98 : std_logic_vector(3 downto 0);
signal pgassign99 : std_logic_vector(13 downto 0);
signal pgassign100 : std_logic_vector(31 downto 0);
signal pgassign101 : std_logic_vector(31 downto 0);
signal pgassign102 : std_logic_vector(3 downto 0);
signal pgassign103 : std_logic_vector(13 downto 0);
signal pgassign104 : std_logic_vector(31 downto 0);
signal pgassign105 : std_logic_vector(31 downto 0);
signal pgassign106 : std_logic_vector(3 downto 0);
signal pgassign107 : std_logic_vector(13 downto 0);
signal pgassign108 : std_logic_vector(31 downto 0);
signal pgassign109 : std_logic_vector(31 downto 0);
signal pgassign110 : std_logic_vector(3 downto 0);
signal pgassign111 : std_logic_vector(13 downto 0);
signal pgassign112 : std_logic_vector(31 downto 0);
signal pgassign113 : std_logic_vector(31 downto 0);
signal pgassign114 : std_logic_vector(3 downto 0);
signal pgassign115 : std_logic_vector(13 downto 0);
signal pgassign116 : std_logic_vector(31 downto 0);
signal pgassign117 : std_logic_vector(31 downto 0);
signal pgassign118 : std_logic_vector(3 downto 0);
signal pgassign119 : std_logic_vector(13 downto 0);
signal pgassign120 : std_logic_vector(31 downto 0);
signal pgassign121 : std_logic_vector(31 downto 0);
signal pgassign122 : std_logic_vector(3 downto 0);
signal pgassign123 : std_logic_vector(13 downto 0);
signal pgassign124 : std_logic_vector(31 downto 0);
signal pgassign125 : std_logic_vector(31 downto 0);
signal pgassign126 : std_logic_vector(3 downto 0);
signal pgassign127 : std_logic_vector(13 downto 0);
signal pgassign128 : std_logic_vector(31 downto 0);
signal pgassign129 : std_logic_vector(31 downto 0);
signal pgassign130 : std_logic_vector(3 downto 0);
begin
-- Internal assignments
pgassign1(0 to 0) <= B"0";
pgassign2(0 to 29) <= B"000000000000000000000000000000";
pgassign3(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign3(0 downto 0) <= B"0";
pgassign4(31 downto 2) <= B"000000000000000000000000000000";
pgassign4(1 downto 0) <= BRAM_Dout_A(0 to 1);
BRAM_Din_A(0 to 1) <= pgassign5(1 downto 0);
pgassign6(3 downto 3) <= BRAM_WEN_A(0 to 0);
pgassign6(2 downto 2) <= BRAM_WEN_A(0 to 0);
pgassign6(1 downto 1) <= BRAM_WEN_A(0 to 0);
pgassign6(0 downto 0) <= BRAM_WEN_A(0 to 0);
pgassign7(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign7(0 downto 0) <= B"0";
pgassign8(31 downto 2) <= B"000000000000000000000000000000";
pgassign8(1 downto 0) <= BRAM_Dout_B(0 to 1);
BRAM_Din_B(0 to 1) <= pgassign9(1 downto 0);
pgassign10(3 downto 3) <= BRAM_WEN_B(0 to 0);
pgassign10(2 downto 2) <= BRAM_WEN_B(0 to 0);
pgassign10(1 downto 1) <= BRAM_WEN_B(0 to 0);
pgassign10(0 downto 0) <= BRAM_WEN_B(0 to 0);
pgassign11(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign11(0 downto 0) <= B"0";
pgassign12(31 downto 2) <= B"000000000000000000000000000000";
pgassign12(1 downto 0) <= BRAM_Dout_A(2 to 3);
BRAM_Din_A(2 to 3) <= pgassign13(1 downto 0);
pgassign14(3 downto 3) <= BRAM_WEN_A(0 to 0);
pgassign14(2 downto 2) <= BRAM_WEN_A(0 to 0);
pgassign14(1 downto 1) <= BRAM_WEN_A(0 to 0);
pgassign14(0 downto 0) <= BRAM_WEN_A(0 to 0);
pgassign15(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign15(0 downto 0) <= B"0";
pgassign16(31 downto 2) <= B"000000000000000000000000000000";
pgassign16(1 downto 0) <= BRAM_Dout_B(2 to 3);
BRAM_Din_B(2 to 3) <= pgassign17(1 downto 0);
pgassign18(3 downto 3) <= BRAM_WEN_B(0 to 0);
pgassign18(2 downto 2) <= BRAM_WEN_B(0 to 0);
pgassign18(1 downto 1) <= BRAM_WEN_B(0 to 0);
pgassign18(0 downto 0) <= BRAM_WEN_B(0 to 0);
pgassign19(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign19(0 downto 0) <= B"0";
pgassign20(31 downto 2) <= B"000000000000000000000000000000";
pgassign20(1 downto 0) <= BRAM_Dout_A(4 to 5);
BRAM_Din_A(4 to 5) <= pgassign21(1 downto 0);
pgassign22(3 downto 3) <= BRAM_WEN_A(0 to 0);
pgassign22(2 downto 2) <= BRAM_WEN_A(0 to 0);
pgassign22(1 downto 1) <= BRAM_WEN_A(0 to 0);
pgassign22(0 downto 0) <= BRAM_WEN_A(0 to 0);
pgassign23(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign23(0 downto 0) <= B"0";
pgassign24(31 downto 2) <= B"000000000000000000000000000000";
pgassign24(1 downto 0) <= BRAM_Dout_B(4 to 5);
BRAM_Din_B(4 to 5) <= pgassign25(1 downto 0);
pgassign26(3 downto 3) <= BRAM_WEN_B(0 to 0);
pgassign26(2 downto 2) <= BRAM_WEN_B(0 to 0);
pgassign26(1 downto 1) <= BRAM_WEN_B(0 to 0);
pgassign26(0 downto 0) <= BRAM_WEN_B(0 to 0);
pgassign27(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign27(0 downto 0) <= B"0";
pgassign28(31 downto 2) <= B"000000000000000000000000000000";
pgassign28(1 downto 0) <= BRAM_Dout_A(6 to 7);
BRAM_Din_A(6 to 7) <= pgassign29(1 downto 0);
pgassign30(3 downto 3) <= BRAM_WEN_A(0 to 0);
pgassign30(2 downto 2) <= BRAM_WEN_A(0 to 0);
pgassign30(1 downto 1) <= BRAM_WEN_A(0 to 0);
pgassign30(0 downto 0) <= BRAM_WEN_A(0 to 0);
pgassign31(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign31(0 downto 0) <= B"0";
pgassign32(31 downto 2) <= B"000000000000000000000000000000";
pgassign32(1 downto 0) <= BRAM_Dout_B(6 to 7);
BRAM_Din_B(6 to 7) <= pgassign33(1 downto 0);
pgassign34(3 downto 3) <= BRAM_WEN_B(0 to 0);
pgassign34(2 downto 2) <= BRAM_WEN_B(0 to 0);
pgassign34(1 downto 1) <= BRAM_WEN_B(0 to 0);
pgassign34(0 downto 0) <= BRAM_WEN_B(0 to 0);
pgassign35(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign35(0 downto 0) <= B"0";
pgassign36(31 downto 2) <= B"000000000000000000000000000000";
pgassign36(1 downto 0) <= BRAM_Dout_A(8 to 9);
BRAM_Din_A(8 to 9) <= pgassign37(1 downto 0);
pgassign38(3 downto 3) <= BRAM_WEN_A(1 to 1);
pgassign38(2 downto 2) <= BRAM_WEN_A(1 to 1);
pgassign38(1 downto 1) <= BRAM_WEN_A(1 to 1);
pgassign38(0 downto 0) <= BRAM_WEN_A(1 to 1);
pgassign39(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign39(0 downto 0) <= B"0";
pgassign40(31 downto 2) <= B"000000000000000000000000000000";
pgassign40(1 downto 0) <= BRAM_Dout_B(8 to 9);
BRAM_Din_B(8 to 9) <= pgassign41(1 downto 0);
pgassign42(3 downto 3) <= BRAM_WEN_B(1 to 1);
pgassign42(2 downto 2) <= BRAM_WEN_B(1 to 1);
pgassign42(1 downto 1) <= BRAM_WEN_B(1 to 1);
pgassign42(0 downto 0) <= BRAM_WEN_B(1 to 1);
pgassign43(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign43(0 downto 0) <= B"0";
pgassign44(31 downto 2) <= B"000000000000000000000000000000";
pgassign44(1 downto 0) <= BRAM_Dout_A(10 to 11);
BRAM_Din_A(10 to 11) <= pgassign45(1 downto 0);
pgassign46(3 downto 3) <= BRAM_WEN_A(1 to 1);
pgassign46(2 downto 2) <= BRAM_WEN_A(1 to 1);
pgassign46(1 downto 1) <= BRAM_WEN_A(1 to 1);
pgassign46(0 downto 0) <= BRAM_WEN_A(1 to 1);
pgassign47(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign47(0 downto 0) <= B"0";
pgassign48(31 downto 2) <= B"000000000000000000000000000000";
pgassign48(1 downto 0) <= BRAM_Dout_B(10 to 11);
BRAM_Din_B(10 to 11) <= pgassign49(1 downto 0);
pgassign50(3 downto 3) <= BRAM_WEN_B(1 to 1);
pgassign50(2 downto 2) <= BRAM_WEN_B(1 to 1);
pgassign50(1 downto 1) <= BRAM_WEN_B(1 to 1);
pgassign50(0 downto 0) <= BRAM_WEN_B(1 to 1);
pgassign51(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign51(0 downto 0) <= B"0";
pgassign52(31 downto 2) <= B"000000000000000000000000000000";
pgassign52(1 downto 0) <= BRAM_Dout_A(12 to 13);
BRAM_Din_A(12 to 13) <= pgassign53(1 downto 0);
pgassign54(3 downto 3) <= BRAM_WEN_A(1 to 1);
pgassign54(2 downto 2) <= BRAM_WEN_A(1 to 1);
pgassign54(1 downto 1) <= BRAM_WEN_A(1 to 1);
pgassign54(0 downto 0) <= BRAM_WEN_A(1 to 1);
pgassign55(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign55(0 downto 0) <= B"0";
pgassign56(31 downto 2) <= B"000000000000000000000000000000";
pgassign56(1 downto 0) <= BRAM_Dout_B(12 to 13);
BRAM_Din_B(12 to 13) <= pgassign57(1 downto 0);
pgassign58(3 downto 3) <= BRAM_WEN_B(1 to 1);
pgassign58(2 downto 2) <= BRAM_WEN_B(1 to 1);
pgassign58(1 downto 1) <= BRAM_WEN_B(1 to 1);
pgassign58(0 downto 0) <= BRAM_WEN_B(1 to 1);
pgassign59(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign59(0 downto 0) <= B"0";
pgassign60(31 downto 2) <= B"000000000000000000000000000000";
pgassign60(1 downto 0) <= BRAM_Dout_A(14 to 15);
BRAM_Din_A(14 to 15) <= pgassign61(1 downto 0);
pgassign62(3 downto 3) <= BRAM_WEN_A(1 to 1);
pgassign62(2 downto 2) <= BRAM_WEN_A(1 to 1);
pgassign62(1 downto 1) <= BRAM_WEN_A(1 to 1);
pgassign62(0 downto 0) <= BRAM_WEN_A(1 to 1);
pgassign63(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign63(0 downto 0) <= B"0";
pgassign64(31 downto 2) <= B"000000000000000000000000000000";
pgassign64(1 downto 0) <= BRAM_Dout_B(14 to 15);
BRAM_Din_B(14 to 15) <= pgassign65(1 downto 0);
pgassign66(3 downto 3) <= BRAM_WEN_B(1 to 1);
pgassign66(2 downto 2) <= BRAM_WEN_B(1 to 1);
pgassign66(1 downto 1) <= BRAM_WEN_B(1 to 1);
pgassign66(0 downto 0) <= BRAM_WEN_B(1 to 1);
pgassign67(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign67(0 downto 0) <= B"0";
pgassign68(31 downto 2) <= B"000000000000000000000000000000";
pgassign68(1 downto 0) <= BRAM_Dout_A(16 to 17);
BRAM_Din_A(16 to 17) <= pgassign69(1 downto 0);
pgassign70(3 downto 3) <= BRAM_WEN_A(2 to 2);
pgassign70(2 downto 2) <= BRAM_WEN_A(2 to 2);
pgassign70(1 downto 1) <= BRAM_WEN_A(2 to 2);
pgassign70(0 downto 0) <= BRAM_WEN_A(2 to 2);
pgassign71(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign71(0 downto 0) <= B"0";
pgassign72(31 downto 2) <= B"000000000000000000000000000000";
pgassign72(1 downto 0) <= BRAM_Dout_B(16 to 17);
BRAM_Din_B(16 to 17) <= pgassign73(1 downto 0);
pgassign74(3 downto 3) <= BRAM_WEN_B(2 to 2);
pgassign74(2 downto 2) <= BRAM_WEN_B(2 to 2);
pgassign74(1 downto 1) <= BRAM_WEN_B(2 to 2);
pgassign74(0 downto 0) <= BRAM_WEN_B(2 to 2);
pgassign75(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign75(0 downto 0) <= B"0";
pgassign76(31 downto 2) <= B"000000000000000000000000000000";
pgassign76(1 downto 0) <= BRAM_Dout_A(18 to 19);
BRAM_Din_A(18 to 19) <= pgassign77(1 downto 0);
pgassign78(3 downto 3) <= BRAM_WEN_A(2 to 2);
pgassign78(2 downto 2) <= BRAM_WEN_A(2 to 2);
pgassign78(1 downto 1) <= BRAM_WEN_A(2 to 2);
pgassign78(0 downto 0) <= BRAM_WEN_A(2 to 2);
pgassign79(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign79(0 downto 0) <= B"0";
pgassign80(31 downto 2) <= B"000000000000000000000000000000";
pgassign80(1 downto 0) <= BRAM_Dout_B(18 to 19);
BRAM_Din_B(18 to 19) <= pgassign81(1 downto 0);
pgassign82(3 downto 3) <= BRAM_WEN_B(2 to 2);
pgassign82(2 downto 2) <= BRAM_WEN_B(2 to 2);
pgassign82(1 downto 1) <= BRAM_WEN_B(2 to 2);
pgassign82(0 downto 0) <= BRAM_WEN_B(2 to 2);
pgassign83(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign83(0 downto 0) <= B"0";
pgassign84(31 downto 2) <= B"000000000000000000000000000000";
pgassign84(1 downto 0) <= BRAM_Dout_A(20 to 21);
BRAM_Din_A(20 to 21) <= pgassign85(1 downto 0);
pgassign86(3 downto 3) <= BRAM_WEN_A(2 to 2);
pgassign86(2 downto 2) <= BRAM_WEN_A(2 to 2);
pgassign86(1 downto 1) <= BRAM_WEN_A(2 to 2);
pgassign86(0 downto 0) <= BRAM_WEN_A(2 to 2);
pgassign87(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign87(0 downto 0) <= B"0";
pgassign88(31 downto 2) <= B"000000000000000000000000000000";
pgassign88(1 downto 0) <= BRAM_Dout_B(20 to 21);
BRAM_Din_B(20 to 21) <= pgassign89(1 downto 0);
pgassign90(3 downto 3) <= BRAM_WEN_B(2 to 2);
pgassign90(2 downto 2) <= BRAM_WEN_B(2 to 2);
pgassign90(1 downto 1) <= BRAM_WEN_B(2 to 2);
pgassign90(0 downto 0) <= BRAM_WEN_B(2 to 2);
pgassign91(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign91(0 downto 0) <= B"0";
pgassign92(31 downto 2) <= B"000000000000000000000000000000";
pgassign92(1 downto 0) <= BRAM_Dout_A(22 to 23);
BRAM_Din_A(22 to 23) <= pgassign93(1 downto 0);
pgassign94(3 downto 3) <= BRAM_WEN_A(2 to 2);
pgassign94(2 downto 2) <= BRAM_WEN_A(2 to 2);
pgassign94(1 downto 1) <= BRAM_WEN_A(2 to 2);
pgassign94(0 downto 0) <= BRAM_WEN_A(2 to 2);
pgassign95(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign95(0 downto 0) <= B"0";
pgassign96(31 downto 2) <= B"000000000000000000000000000000";
pgassign96(1 downto 0) <= BRAM_Dout_B(22 to 23);
BRAM_Din_B(22 to 23) <= pgassign97(1 downto 0);
pgassign98(3 downto 3) <= BRAM_WEN_B(2 to 2);
pgassign98(2 downto 2) <= BRAM_WEN_B(2 to 2);
pgassign98(1 downto 1) <= BRAM_WEN_B(2 to 2);
pgassign98(0 downto 0) <= BRAM_WEN_B(2 to 2);
pgassign99(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign99(0 downto 0) <= B"0";
pgassign100(31 downto 2) <= B"000000000000000000000000000000";
pgassign100(1 downto 0) <= BRAM_Dout_A(24 to 25);
BRAM_Din_A(24 to 25) <= pgassign101(1 downto 0);
pgassign102(3 downto 3) <= BRAM_WEN_A(3 to 3);
pgassign102(2 downto 2) <= BRAM_WEN_A(3 to 3);
pgassign102(1 downto 1) <= BRAM_WEN_A(3 to 3);
pgassign102(0 downto 0) <= BRAM_WEN_A(3 to 3);
pgassign103(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign103(0 downto 0) <= B"0";
pgassign104(31 downto 2) <= B"000000000000000000000000000000";
pgassign104(1 downto 0) <= BRAM_Dout_B(24 to 25);
BRAM_Din_B(24 to 25) <= pgassign105(1 downto 0);
pgassign106(3 downto 3) <= BRAM_WEN_B(3 to 3);
pgassign106(2 downto 2) <= BRAM_WEN_B(3 to 3);
pgassign106(1 downto 1) <= BRAM_WEN_B(3 to 3);
pgassign106(0 downto 0) <= BRAM_WEN_B(3 to 3);
pgassign107(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign107(0 downto 0) <= B"0";
pgassign108(31 downto 2) <= B"000000000000000000000000000000";
pgassign108(1 downto 0) <= BRAM_Dout_A(26 to 27);
BRAM_Din_A(26 to 27) <= pgassign109(1 downto 0);
pgassign110(3 downto 3) <= BRAM_WEN_A(3 to 3);
pgassign110(2 downto 2) <= BRAM_WEN_A(3 to 3);
pgassign110(1 downto 1) <= BRAM_WEN_A(3 to 3);
pgassign110(0 downto 0) <= BRAM_WEN_A(3 to 3);
pgassign111(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign111(0 downto 0) <= B"0";
pgassign112(31 downto 2) <= B"000000000000000000000000000000";
pgassign112(1 downto 0) <= BRAM_Dout_B(26 to 27);
BRAM_Din_B(26 to 27) <= pgassign113(1 downto 0);
pgassign114(3 downto 3) <= BRAM_WEN_B(3 to 3);
pgassign114(2 downto 2) <= BRAM_WEN_B(3 to 3);
pgassign114(1 downto 1) <= BRAM_WEN_B(3 to 3);
pgassign114(0 downto 0) <= BRAM_WEN_B(3 to 3);
pgassign115(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign115(0 downto 0) <= B"0";
pgassign116(31 downto 2) <= B"000000000000000000000000000000";
pgassign116(1 downto 0) <= BRAM_Dout_A(28 to 29);
BRAM_Din_A(28 to 29) <= pgassign117(1 downto 0);
pgassign118(3 downto 3) <= BRAM_WEN_A(3 to 3);
pgassign118(2 downto 2) <= BRAM_WEN_A(3 to 3);
pgassign118(1 downto 1) <= BRAM_WEN_A(3 to 3);
pgassign118(0 downto 0) <= BRAM_WEN_A(3 to 3);
pgassign119(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign119(0 downto 0) <= B"0";
pgassign120(31 downto 2) <= B"000000000000000000000000000000";
pgassign120(1 downto 0) <= BRAM_Dout_B(28 to 29);
BRAM_Din_B(28 to 29) <= pgassign121(1 downto 0);
pgassign122(3 downto 3) <= BRAM_WEN_B(3 to 3);
pgassign122(2 downto 2) <= BRAM_WEN_B(3 to 3);
pgassign122(1 downto 1) <= BRAM_WEN_B(3 to 3);
pgassign122(0 downto 0) <= BRAM_WEN_B(3 to 3);
pgassign123(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign123(0 downto 0) <= B"0";
pgassign124(31 downto 2) <= B"000000000000000000000000000000";
pgassign124(1 downto 0) <= BRAM_Dout_A(30 to 31);
BRAM_Din_A(30 to 31) <= pgassign125(1 downto 0);
pgassign126(3 downto 3) <= BRAM_WEN_A(3 to 3);
pgassign126(2 downto 2) <= BRAM_WEN_A(3 to 3);
pgassign126(1 downto 1) <= BRAM_WEN_A(3 to 3);
pgassign126(0 downto 0) <= BRAM_WEN_A(3 to 3);
pgassign127(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign127(0 downto 0) <= B"0";
pgassign128(31 downto 2) <= B"000000000000000000000000000000";
pgassign128(1 downto 0) <= BRAM_Dout_B(30 to 31);
BRAM_Din_B(30 to 31) <= pgassign129(1 downto 0);
pgassign130(3 downto 3) <= BRAM_WEN_B(3 to 3);
pgassign130(2 downto 2) <= BRAM_WEN_B(3 to 3);
pgassign130(1 downto 1) <= BRAM_WEN_B(3 to 3);
pgassign130(0 downto 0) <= BRAM_WEN_B(3 to 3);
net_gnd0 <= '0';
net_gnd4(3 downto 0) <= B"0000";
ramb16bwer_0 : RAMB16BWER
generic map (
INIT_FILE => "lmb_bram_combined_0.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign3,
CLKA => BRAM_Clk_A,
DIA => pgassign4,
DIPA => net_gnd4,
DOA => pgassign5,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign6,
ADDRB => pgassign7,
CLKB => BRAM_Clk_B,
DIB => pgassign8,
DIPB => net_gnd4,
DOB => pgassign9,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign10
);
ramb16bwer_1 : RAMB16BWER
generic map (
INIT_FILE => "lmb_bram_combined_1.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign11,
CLKA => BRAM_Clk_A,
DIA => pgassign12,
DIPA => net_gnd4,
DOA => pgassign13,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign14,
ADDRB => pgassign15,
CLKB => BRAM_Clk_B,
DIB => pgassign16,
DIPB => net_gnd4,
DOB => pgassign17,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign18
);
ramb16bwer_2 : RAMB16BWER
generic map (
INIT_FILE => "lmb_bram_combined_2.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign19,
CLKA => BRAM_Clk_A,
DIA => pgassign20,
DIPA => net_gnd4,
DOA => pgassign21,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign22,
ADDRB => pgassign23,
CLKB => BRAM_Clk_B,
DIB => pgassign24,
DIPB => net_gnd4,
DOB => pgassign25,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign26
);
ramb16bwer_3 : RAMB16BWER
generic map (
INIT_FILE => "lmb_bram_combined_3.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign27,
CLKA => BRAM_Clk_A,
DIA => pgassign28,
DIPA => net_gnd4,
DOA => pgassign29,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign30,
ADDRB => pgassign31,
CLKB => BRAM_Clk_B,
DIB => pgassign32,
DIPB => net_gnd4,
DOB => pgassign33,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign34
);
ramb16bwer_4 : RAMB16BWER
generic map (
INIT_FILE => "lmb_bram_combined_4.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign35,
CLKA => BRAM_Clk_A,
DIA => pgassign36,
DIPA => net_gnd4,
DOA => pgassign37,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign38,
ADDRB => pgassign39,
CLKB => BRAM_Clk_B,
DIB => pgassign40,
DIPB => net_gnd4,
DOB => pgassign41,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign42
);
ramb16bwer_5 : RAMB16BWER
generic map (
INIT_FILE => "lmb_bram_combined_5.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign43,
CLKA => BRAM_Clk_A,
DIA => pgassign44,
DIPA => net_gnd4,
DOA => pgassign45,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign46,
ADDRB => pgassign47,
CLKB => BRAM_Clk_B,
DIB => pgassign48,
DIPB => net_gnd4,
DOB => pgassign49,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign50
);
ramb16bwer_6 : RAMB16BWER
generic map (
INIT_FILE => "lmb_bram_combined_6.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign51,
CLKA => BRAM_Clk_A,
DIA => pgassign52,
DIPA => net_gnd4,
DOA => pgassign53,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign54,
ADDRB => pgassign55,
CLKB => BRAM_Clk_B,
DIB => pgassign56,
DIPB => net_gnd4,
DOB => pgassign57,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign58
);
ramb16bwer_7 : RAMB16BWER
generic map (
INIT_FILE => "lmb_bram_combined_7.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign59,
CLKA => BRAM_Clk_A,
DIA => pgassign60,
DIPA => net_gnd4,
DOA => pgassign61,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign62,
ADDRB => pgassign63,
CLKB => BRAM_Clk_B,
DIB => pgassign64,
DIPB => net_gnd4,
DOB => pgassign65,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign66
);
ramb16bwer_8 : RAMB16BWER
generic map (
INIT_FILE => "lmb_bram_combined_8.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign67,
CLKA => BRAM_Clk_A,
DIA => pgassign68,
DIPA => net_gnd4,
DOA => pgassign69,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign70,
ADDRB => pgassign71,
CLKB => BRAM_Clk_B,
DIB => pgassign72,
DIPB => net_gnd4,
DOB => pgassign73,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign74
);
ramb16bwer_9 : RAMB16BWER
generic map (
INIT_FILE => "lmb_bram_combined_9.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign75,
CLKA => BRAM_Clk_A,
DIA => pgassign76,
DIPA => net_gnd4,
DOA => pgassign77,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign78,
ADDRB => pgassign79,
CLKB => BRAM_Clk_B,
DIB => pgassign80,
DIPB => net_gnd4,
DOB => pgassign81,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign82
);
ramb16bwer_10 : RAMB16BWER
generic map (
INIT_FILE => "lmb_bram_combined_10.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign83,
CLKA => BRAM_Clk_A,
DIA => pgassign84,
DIPA => net_gnd4,
DOA => pgassign85,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign86,
ADDRB => pgassign87,
CLKB => BRAM_Clk_B,
DIB => pgassign88,
DIPB => net_gnd4,
DOB => pgassign89,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign90
);
ramb16bwer_11 : RAMB16BWER
generic map (
INIT_FILE => "lmb_bram_combined_11.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign91,
CLKA => BRAM_Clk_A,
DIA => pgassign92,
DIPA => net_gnd4,
DOA => pgassign93,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign94,
ADDRB => pgassign95,
CLKB => BRAM_Clk_B,
DIB => pgassign96,
DIPB => net_gnd4,
DOB => pgassign97,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign98
);
ramb16bwer_12 : RAMB16BWER
generic map (
INIT_FILE => "lmb_bram_combined_12.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign99,
CLKA => BRAM_Clk_A,
DIA => pgassign100,
DIPA => net_gnd4,
DOA => pgassign101,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign102,
ADDRB => pgassign103,
CLKB => BRAM_Clk_B,
DIB => pgassign104,
DIPB => net_gnd4,
DOB => pgassign105,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign106
);
ramb16bwer_13 : RAMB16BWER
generic map (
INIT_FILE => "lmb_bram_combined_13.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign107,
CLKA => BRAM_Clk_A,
DIA => pgassign108,
DIPA => net_gnd4,
DOA => pgassign109,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign110,
ADDRB => pgassign111,
CLKB => BRAM_Clk_B,
DIB => pgassign112,
DIPB => net_gnd4,
DOB => pgassign113,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign114
);
ramb16bwer_14 : RAMB16BWER
generic map (
INIT_FILE => "lmb_bram_combined_14.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign115,
CLKA => BRAM_Clk_A,
DIA => pgassign116,
DIPA => net_gnd4,
DOA => pgassign117,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign118,
ADDRB => pgassign119,
CLKB => BRAM_Clk_B,
DIB => pgassign120,
DIPB => net_gnd4,
DOB => pgassign121,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign122
);
ramb16bwer_15 : RAMB16BWER
generic map (
INIT_FILE => "lmb_bram_combined_15.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign123,
CLKA => BRAM_Clk_A,
DIA => pgassign124,
DIPA => net_gnd4,
DOA => pgassign125,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign126,
ADDRB => pgassign127,
CLKB => BRAM_Clk_B,
DIB => pgassign128,
DIPB => net_gnd4,
DOB => pgassign129,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign130
);
end architecture STRUCTURE;
|
gpl-2.0
|
7268a42c7d217d61cb1b8e9a1198e4fc
| 0.616879 | 3.125855 | false | false | false | false |
berickson1/DE2-Ethernet
|
Quartus/EthernetExample.vhd
| 1 | 9,670 |
-- EthernetExample
-- Brent Erickson
-- Top level system file
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.vital_primitives.all;
use work.DE2_CONSTANTS.all;
entity EthernetExample is
port (
-- Reset and Clock
KEY : in std_logic_vector (0 downto 0);
CLOCK_50 : in std_logic;
CLOCK_27 : in std_logic;
-- SDRAM On Board
DRAM_ADDR : out DE2_SDRAM_ADDR_BUS;
DRAM_BA_0 : out std_logic;
DRAM_BA_1 : out std_logic;
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
DRAM_DQ : inout DE2_SDRAM_DATA_BUS;
DRAM_LDQM : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_WE_N : out std_logic;
-- Ethernet
ENET_CLK : out std_logic;
ENET_CMD : out std_logic;
ENET_CS_N : out std_logic;
ENET_INT : in std_logic;
ENET_RD_N : out std_logic;
ENET_WR_N : out std_logic;
ENET_RST_N : out std_logic;
ENET_DATA : inout std_logic_vector(15 downto 0);
-- Flash memory
FL_ADDR : out std_logic_vector (21 downto 0);
FL_CE_N : out std_logic_vector (0 downto 0);
FL_OE_N : out std_logic_vector (0 downto 0);
FL_DQ : inout std_logic_vector (7 downto 0);
FL_RST_N : out std_logic_vector (0 downto 0);
FL_WE_N : out std_logic_vector (0 downto 0)
);
end EthernetExample;
architecture structure of EthernetExample is
component nios_system is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n -- export
altpll_0_c0_clk : out std_logic; -- clk
altpll_0_c2_clk : out std_logic; -- clk
sdram_0_wire_addr : out std_logic_vector(11 downto 0); -- addr
sdram_0_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_0_wire_cas_n : out std_logic; -- cas_n
sdram_0_wire_cke : out std_logic; -- cke
sdram_0_wire_cs_n : out std_logic; -- cs_n
sdram_0_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
sdram_0_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_0_wire_ras_n : out std_logic; -- ras_n
sdram_0_wire_we_n : out std_logic; -- we_n
dm9000a_if_0_s1_export_DATA : inout std_logic_vector(15 downto 0) := (others => 'X'); -- DATA
dm9000a_if_0_s1_export_CMD : out std_logic; -- CMD
dm9000a_if_0_s1_export_RD_N : out std_logic; -- RD_N
dm9000a_if_0_s1_export_WR_N : out std_logic; -- WR_N
dm9000a_if_0_s1_export_CS_N : out std_logic; -- CS_N
dm9000a_if_0_s1_export_RST_N : out std_logic; -- RST_N
dm9000a_if_0_s1_export_INT : in std_logic := 'X'; -- INT
dm9000a_if_0_s1_export_CLK : out std_logic;
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_read_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_read_n_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_data_out : inout std_logic_vector(7 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_data_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_chipselect_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_chipselect_n_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_write_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_write_n_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_address_out : out std_logic_vector(21 downto 0) -- generic_tristate_controller_0_tcm_address_out
);
end component nios_system;
-- signals to match provided IP core to specific SDRAM chip of our system
signal BA : std_logic_vector (1 downto 0);
signal DQM : std_logic_vector (1 downto 0);
begin
DRAM_BA_1 <= BA(1);
DRAM_BA_0 <= BA(0);
DRAM_UDQM <= DQM(1);
DRAM_LDQM <= DQM(0);
FL_RST_N <= "1";
u0 : component nios_system
port map (
reset_reset_n => KEY(0), -- reset.reset_n
altpll_0_c0_clk => DRAM_CLK, -- altpll_0_c0.clk
altpll_0_c2_clk => ENET_CLK, -- altpll_0_c2.clk
sdram_0_wire_addr => DRAM_ADDR, -- sdram_0_wire.addr
sdram_0_wire_ba => BA, -- .ba
sdram_0_wire_cas_n => DRAM_CAS_N, -- .cas_n
sdram_0_wire_cke => DRAM_CKE, -- .cke
sdram_0_wire_cs_n => DRAM_CS_N, -- .cs_n
sdram_0_wire_dq => DRAM_DQ, -- .dq
sdram_0_wire_dqm => DQM, -- .dqm
sdram_0_wire_ras_n => DRAM_RAS_N, -- .ras_n
sdram_0_wire_we_n => DRAM_WE_N, -- .we_n
clk_clk => CLOCK_50, -- clk.clk
dm9000a_if_0_s1_export_DATA => ENET_DATA, -- dm9000a_if_0_s1_export.DATA
dm9000a_if_0_s1_export_CMD => ENET_CMD, -- .CMD
dm9000a_if_0_s1_export_RD_N => ENET_RD_N, -- .RD_N
dm9000a_if_0_s1_export_WR_N => ENET_WR_N, -- .WR_N
dm9000a_if_0_s1_export_CS_N => ENET_CS_N, -- .CS_N
dm9000a_if_0_s1_export_RST_N => ENET_RST_N, -- .RST_N
dm9000a_if_0_s1_export_INT => ENET_INT, -- .INT
--dm9000a_if_0_s1_export_CLK => ENET_CLK, -- .CLK
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_read_n_out => FL_OE_N, -- tristate_conduit_bridge_0_out.generic_tristate_controller_0_tcm_read_n_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_data_out => FL_DQ, -- .generic_tristate_controller_0_tcm_data_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_chipselect_n_out => FL_CE_N, -- .generic_tristate_controller_0_tcm_chipselect_n_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_write_n_out => FL_WE_N, -- .generic_tristate_controller_0_tcm_write_n_out
tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_address_out => FL_ADDR -- .generic_tristate_controller_0_tcm_address_out
);
end structure;
library ieee;
--DE2 Constants
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.vital_primitives.all;
package DE2_CONSTANTS is
subtype DE2_LCD_DATA_BUS is std_logic_vector(7 downto 0);
subtype DE2_LED_GREEN is std_logic_vector(7 downto 0);
subtype DE2_SRAM_ADDR_BUS is std_logic_vector(17 downto 0);
subtype DE2_SRAM_DATA_BUS is std_logic_vector(15 downto 0);
subtype DE2_SDRAM_ADDR_BUS is std_logic_vector(11 downto 0);
subtype DE2_SDRAM_DATA_BUS is std_logic_vector(15 downto 0);
end DE2_CONSTANTS;
|
gpl-2.0
|
d98efcd4bf8262c41089f6c8d5ccedcb
| 0.423888 | 3.799607 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 2/PSRModifier.vhd
| 1 | 1,710 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PSRModifier is
Port ( ALUOP : in STD_LOGIC_VECTOR (5 downto 0);
Oper2 : in STD_LOGIC_VECTOR (31 downto 0);
Oper1 : in STD_LOGIC_VECTOR (31 downto 0);
ALURESULT : in STD_LOGIC_VECTOR (31 downto 0);
NZVC : out STD_LOGIC_VECTOR (3 downto 0));
end PSRModifier;
architecture Behavioral of PSRModifier is
begin
process(ALUOP,Oper2,Oper1,ALURESULT)
begin
if(ALUOP="001011" or ALUOP="001100" or ALUOP="001101" or ALUOP="001110" or ALUOP="001111" or ALUOP="010000" or ALUOP="010001" or ALUOP="010011" or ALUOP="010100" or ALUOP="010110") then
--ANDcc,ANDNcc,ORcc,ORNcc,XORcc,XNORcc,ADDcc,ADDXcc,SUBcc,SUBXcc
if(ALURESULT="00000000000000000000000000000000") then
NZVC(2)<='1';
else
NZVC(2)<='0';
end if;
NZVC(3)<=ALURESULT(31);
if(ALUOP="001011" or ALUOP="001100" or ALUOP="001101" or ALUOP="001110" or ALUOP="001111" or ALUOP="010000") then
--ANDcc,ANDNcc,ORcc,ORNcc,XORcc,XNORcc
NZVC(1 downto 0)<="00";
elsif(ALUOP="010001" or ALUOP="010011") then --ADDcc, ADDXcc
NZVC(1)<=((Oper1(31) and Oper2(31) and (not ALURESULT(31))) or ((not Oper1(31)) and (not Oper2(31)) and ALURESULT(31)));
NZVC(0)<=(Oper1(31) and Oper2(31)) or ((not ALURESULT(31)) and (Oper1(31) or Oper2(31)));
else--(ALUOP="010100" or ALUOP="010110") SUBcc, SUBXcc
NZVC(1)<=(Oper1(31) and (not Oper2(31)) and (not ALURESULT(31))) or ((not Oper1(31)) and Oper2(31) and ALURESULT(31));
NZVC(0)<=((not Oper1(31)) and Oper2(31)) or (ALURESULT(31) and ((not Oper1(31)) or Oper2(31)));
end if;
else
NZVC<="1111";
end if;
end process;
end Behavioral;
|
mit
|
2fe1a96d032b215c368e7610986f8ab1
| 0.64269 | 3.172542 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 1/RF.vhd
| 1 | 1,050 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity RF is
Port ( rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
DWR : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
Crs1 : out STD_LOGIC_VECTOR (31 downto 0):=(others=>'0');
Crs2 : out STD_LOGIC_VECTOR (31 downto 0):=(others=>'0'));
end RF;
architecture Behavioral of RF is
type ram_type is array (31 downto 0) of std_logic_vector (31 downto 0);
signal RAM: ram_type:=(others => "00000000000000000000000000000000");
--registro g0 siempre es cero
begin
process (rs1,rs2,rd,DWR,rst,RAM)
begin
if rst='0' then
if rd >"00000" then
RAM(conv_integer(rd)) <= DWR;
end if;
Crs1<=RAM(conv_integer(rs1));
Crs2<=RAM(conv_integer(rs2));
else
RAM<=(others => "00000000000000000000000000000000");
Crs1<=(others=>'0');
Crs2<=(others=>'0');
end if;
end process;
end Behavioral;
|
mit
|
eb340928a1b827a35a80d1e028fc1a2f
| 0.617143 | 3.097345 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_wiz_0_0_address_decoder.vhd
| 1 | 23,202 |
-------------------------------------------------------------------------------
-- Address Decoder - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: address_decoder.vhd
-- Version: v1.01.a
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 08/09/2010 --
-- - updated the core with optimziation. Closed CR 574507
-- - combined the CE generation logic to further optimize the code.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.system_xadc_wiz_0_0_proc_common_pkg.all;
use work.system_xadc_wiz_0_0_pselect_f;
use work.system_xadc_wiz_0_0_ipif_pkg.all;
use work.system_xadc_wiz_0_0_family_support.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity system_xadc_wiz_0_0_address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity system_xadc_wiz_0_0_address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of system_xadc_wiz_0_0_address_decoder is
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity work.system_xadc_wiz_0_0_pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity work.system_xadc_wiz_0_0_pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture IMP;
|
apache-2.0
|
e6e803f5c1a4ae3e179b9d59552be0c0
| 0.428196 | 4.692012 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 3/ALU.vhd
| 1 | 2,164 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ALU is
Port ( Oper1 : in STD_LOGIC_VECTOR (31 downto 0);
Oper2 : in STD_LOGIC_VECTOR (31 downto 0);
ALUOP : in STD_LOGIC_VECTOR (5 downto 0);
C: in STD_LOGIC;
ALURESULT : out STD_LOGIC_VECTOR (31 downto 0));
end ALU;
architecture Behavioral of ALU is
begin
process(Oper1,Oper2,ALUOP,C)
begin
case ALUOP is
when "000000"=>
ALURESULT<=Oper1 and Oper2;--AND
when "000001"=>
ALURESULT<=Oper1 and not Oper2;--ANDN
when "000010"=>
ALURESULT<=Oper1 or Oper2;--OR
when "000011"=>
ALURESULT<=Oper1 or not Oper2;--ORN
when "000100"=>
ALURESULT<=Oper1 xor Oper2;--XOR
when "000101"=>
ALURESULT<=Oper1 xnor Oper2;--XNOR
when "000110"=>
ALURESULT<=Oper1+Oper2;--ADD
when "000111"=>
ALURESULT<=Oper1-Oper2;--SUB
when "001000"=> --SLL
ALURESULT<=std_logic_vector(unsigned(Oper1) sll conv_integer(oper2(4 downto 0)));
when "001001"=> --SRL
ALURESULT<=std_logic_vector(unsigned(Oper1) srl conv_integer(oper2(4 downto 0)));
when "001010"=> --SRA
ALURESULT<=To_StdLogicVector(to_bitvector(Oper1) sra conv_integer(oper2(4 downto 0)));
when "001011"=>
ALURESULT<=Oper1 and Oper2;--ANDcc
when "001100"=>
ALURESULT<=Oper1 and not Oper2;--ANDNcc
when "001101"=>
ALURESULT<=Oper1 or Oper2;--ORcc
when "001110"=>
ALURESULT<=Oper1 or not Oper2;--ORNcc
when "001111"=>
ALURESULT<=Oper1 xor Oper2;--XORcc
when "010000"=>
ALURESULT<=Oper1 xnor Oper2;--XNORcc
when "010001"=>
ALURESULT<=Oper1+Oper2;--ADDcc
when "010010"=> --ADDX
ALURESULT<=Oper1+Oper2+C;
when "010011"=> --ADDXcc
ALURESULT<=Oper1+Oper2+C;
when "010100"=>
ALURESULT<=Oper1-Oper2;--SUBcc
when "010101"=> --SUBX
ALURESULT<=Oper1-Oper2-C;
when "010110"=> --SUBXcc
ALURESULT<=Oper1-Oper2-C;
when "010111"=> --SAVE
ALURESULT<=Oper1+Oper2;
when "011000"=> --RESTORE
ALURESULT<=Oper1+Oper2;
when others=>--"111111" Instrucciones no definidas
ALURESULT<=(others=>'0');
end case;
end process;
end Behavioral;
|
mit
|
7f72401e95b874ad65599a6afcb87890
| 0.652495 | 3.145349 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_uartlite_0_0/sim/system_axi_uartlite_0_0.vhd
| 1 | 8,178 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_uartlite:2.0
-- IP Revision: 15
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_uartlite_v2_0_15;
USE axi_uartlite_v2_0_15.axi_uartlite;
ENTITY system_axi_uartlite_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
rx : IN STD_LOGIC;
tx : OUT STD_LOGIC
);
END system_axi_uartlite_0_0;
ARCHITECTURE system_axi_uartlite_0_0_arch OF system_axi_uartlite_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_uartlite_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_uartlite IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_BAUDRATE : INTEGER;
C_DATA_BITS : INTEGER;
C_USE_PARITY : INTEGER;
C_ODD_PARITY : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
rx : IN STD_LOGIC;
tx : OUT STD_LOGIC
);
END COMPONENT axi_uartlite;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF rx: SIGNAL IS "xilinx.com:interface:uart:1.0 UART RxD";
ATTRIBUTE X_INTERFACE_INFO OF tx: SIGNAL IS "xilinx.com:interface:uart:1.0 UART TxD";
BEGIN
U0 : axi_uartlite
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ACLK_FREQ_HZ => 100000000,
C_S_AXI_ADDR_WIDTH => 4,
C_S_AXI_DATA_WIDTH => 32,
C_BAUDRATE => 9600,
C_DATA_BITS => 8,
C_USE_PARITY => 0,
C_ODD_PARITY => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
interrupt => interrupt,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
rx => rx,
tx => tx
);
END system_axi_uartlite_0_0_arch;
|
apache-2.0
|
98a70440798eb63354f942e1b82b3cfb
| 0.690633 | 3.351639 | false | false | false | false |
jeffmagina/ECE368
|
Lab1/ALU/alu_shift_unit.vhd
| 1 | 1,190 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Shift_Unit
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Shift Unit
-- Operations - Shift Left, Shift Right
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_Shift_Unit is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
COUNT : in STD_LOGIC_VECTOR (2 downto 0);
OP : in STD_LOGIC;
RESULT : out STD_LOGIC_VECTOR (7 downto 0));
end ALU_Shift_Unit;
architecture Combinational of ALU_Shift_Unit is
signal shift_left, shift_right : std_logic_vector (7 downto 0) := (OTHERS => '0');
begin
shift_left <= to_stdlogicvector(to_bitvector(A) sll conv_integer(COUNT));
shift_right <= to_stdlogicvector(to_bitvector(A) srl conv_integer(COUNT));
RESULT <= shift_left when OP='0' else shift_right;
end Combinational;
|
mit
|
08a0982825ba08479fbc8bc466aa7834
| 0.617647 | 3.777778 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_ilmb_bram_if_cntlr_0/synth/system_ilmb_bram_if_cntlr_0.vhd
| 1 | 13,435 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:lmb_bram_if_cntlr:4.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY lmb_bram_if_cntlr_v4_0_10;
USE lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_cntlr;
ENTITY system_ilmb_bram_if_cntlr_0 IS
PORT (
LMB_Clk : IN STD_LOGIC;
LMB_Rst : IN STD_LOGIC;
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_AddrStrobe : IN STD_LOGIC;
LMB_ReadStrobe : IN STD_LOGIC;
LMB_WriteStrobe : IN STD_LOGIC;
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : OUT STD_LOGIC;
Sl_Wait : OUT STD_LOGIC;
Sl_UE : OUT STD_LOGIC;
Sl_CE : OUT STD_LOGIC;
BRAM_Rst_A : OUT STD_LOGIC;
BRAM_Clk_A : OUT STD_LOGIC;
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_EN_A : OUT STD_LOGIC;
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31)
);
END system_ilmb_bram_if_cntlr_0;
ARCHITECTURE system_ilmb_bram_if_cntlr_0_arch OF system_ilmb_bram_if_cntlr_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "yes";
COMPONENT lmb_bram_if_cntlr IS
GENERIC (
C_FAMILY : STRING;
C_HIGHADDR : STD_LOGIC_VECTOR;
C_BASEADDR : STD_LOGIC_VECTOR;
C_NUM_LMB : INTEGER;
C_MASK : STD_LOGIC_VECTOR;
C_MASK1 : STD_LOGIC_VECTOR;
C_MASK2 : STD_LOGIC_VECTOR;
C_MASK3 : STD_LOGIC_VECTOR;
C_LMB_AWIDTH : INTEGER;
C_LMB_DWIDTH : INTEGER;
C_ECC : INTEGER;
C_INTERCONNECT : INTEGER;
C_FAULT_INJECT : INTEGER;
C_CE_FAILING_REGISTERS : INTEGER;
C_UE_FAILING_REGISTERS : INTEGER;
C_ECC_STATUS_REGISTERS : INTEGER;
C_ECC_ONOFF_REGISTER : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER;
C_CE_COUNTER_WIDTH : INTEGER;
C_WRITE_ACCESS : INTEGER;
C_BRAM_AWIDTH : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
PORT (
LMB_Clk : IN STD_LOGIC;
LMB_Rst : IN STD_LOGIC;
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_AddrStrobe : IN STD_LOGIC;
LMB_ReadStrobe : IN STD_LOGIC;
LMB_WriteStrobe : IN STD_LOGIC;
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : OUT STD_LOGIC;
Sl_Wait : OUT STD_LOGIC;
Sl_UE : OUT STD_LOGIC;
Sl_CE : OUT STD_LOGIC;
LMB1_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB1_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB1_AddrStrobe : IN STD_LOGIC;
LMB1_ReadStrobe : IN STD_LOGIC;
LMB1_WriteStrobe : IN STD_LOGIC;
LMB1_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl1_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl1_Ready : OUT STD_LOGIC;
Sl1_Wait : OUT STD_LOGIC;
Sl1_UE : OUT STD_LOGIC;
Sl1_CE : OUT STD_LOGIC;
LMB2_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB2_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB2_AddrStrobe : IN STD_LOGIC;
LMB2_ReadStrobe : IN STD_LOGIC;
LMB2_WriteStrobe : IN STD_LOGIC;
LMB2_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl2_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl2_Ready : OUT STD_LOGIC;
Sl2_Wait : OUT STD_LOGIC;
Sl2_UE : OUT STD_LOGIC;
Sl2_CE : OUT STD_LOGIC;
LMB3_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB3_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB3_AddrStrobe : IN STD_LOGIC;
LMB3_ReadStrobe : IN STD_LOGIC;
LMB3_WriteStrobe : IN STD_LOGIC;
LMB3_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl3_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl3_Ready : OUT STD_LOGIC;
Sl3_Wait : OUT STD_LOGIC;
Sl3_UE : OUT STD_LOGIC;
Sl3_CE : OUT STD_LOGIC;
BRAM_Rst_A : OUT STD_LOGIC;
BRAM_Clk_A : OUT STD_LOGIC;
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_EN_A : OUT STD_LOGIC;
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31);
S_AXI_CTRL_ACLK : IN STD_LOGIC;
S_AXI_CTRL_ARESETN : IN STD_LOGIC;
S_AXI_CTRL_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_AWVALID : IN STD_LOGIC;
S_AXI_CTRL_AWREADY : OUT STD_LOGIC;
S_AXI_CTRL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_CTRL_WVALID : IN STD_LOGIC;
S_AXI_CTRL_WREADY : OUT STD_LOGIC;
S_AXI_CTRL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_CTRL_BVALID : OUT STD_LOGIC;
S_AXI_CTRL_BREADY : IN STD_LOGIC;
S_AXI_CTRL_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_ARVALID : IN STD_LOGIC;
S_AXI_CTRL_ARREADY : OUT STD_LOGIC;
S_AXI_CTRL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_CTRL_RVALID : OUT STD_LOGIC;
S_AXI_CTRL_RREADY : IN STD_LOGIC;
UE : OUT STD_LOGIC;
CE : OUT STD_LOGIC;
Interrupt : OUT STD_LOGIC
);
END COMPONENT lmb_bram_if_cntlr;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "lmb_bram_if_cntlr,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_ilmb_bram_if_cntlr_0_arch : ARCHITECTURE IS "system_ilmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "system_ilmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_bram_if_cntlr,x_ipVersion=4.0,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_HIGHADDR=0x0000000000007FFF,C_BASEADDR=0x0000000000000000,C_NUM_LMB=1,C_MASK=0x0000000080000000,C_MASK1=0x0000000000800000,C_MASK2=0x0000000000800000,C_MASK3=0x0000000000800000,C_LMB_AWIDTH=32,C_LMB_DWIDTH=32,C_ECC=0,C_INTERCONNECT=0,C_FAULT_INJECT=0,C_CE_FAILING_REGIS" &
"TERS=0,C_UE_FAILING_REGISTERS=0,C_ECC_STATUS_REGISTERS=0,C_ECC_ONOFF_REGISTER=0,C_ECC_ONOFF_RESET_VALUE=1,C_CE_COUNTER_WIDTH=0,C_WRITE_ACCESS=2,C_BRAM_AWIDTH=32,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB BE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READY";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB CE";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Rst_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT RST";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Clk_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT CLK";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Addr_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_EN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT EN";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_WEN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT WE";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Dout_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DIN";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Din_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT";
BEGIN
U0 : lmb_bram_if_cntlr
GENERIC MAP (
C_FAMILY => "artix7",
C_HIGHADDR => X"0000000000007FFF",
C_BASEADDR => X"0000000000000000",
C_NUM_LMB => 1,
C_MASK => X"0000000080000000",
C_MASK1 => X"0000000000800000",
C_MASK2 => X"0000000000800000",
C_MASK3 => X"0000000000800000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_BRAM_AWIDTH => 32,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
PORT MAP (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB1_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB1_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB1_AddrStrobe => '0',
LMB1_ReadStrobe => '0',
LMB1_WriteStrobe => '0',
LMB1_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
LMB2_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB2_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB2_AddrStrobe => '0',
LMB2_ReadStrobe => '0',
LMB2_WriteStrobe => '0',
LMB2_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
LMB3_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB3_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB3_AddrStrobe => '0',
LMB3_ReadStrobe => '0',
LMB3_WriteStrobe => '0',
LMB3_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Dout_A => BRAM_Dout_A,
BRAM_Din_A => BRAM_Din_A,
S_AXI_CTRL_ACLK => '0',
S_AXI_CTRL_ARESETN => '0',
S_AXI_CTRL_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_AWVALID => '0',
S_AXI_CTRL_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_CTRL_WVALID => '0',
S_AXI_CTRL_BREADY => '0',
S_AXI_CTRL_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_ARVALID => '0',
S_AXI_CTRL_RREADY => '0'
);
END system_ilmb_bram_if_cntlr_0_arch;
|
apache-2.0
|
13e373fa7375ec8d9f743823ac1c350e
| 0.664012 | 3.179882 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 3/MUX_RFSOURCE.vhd
| 1 | 689 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX_RFSOURCE is
Port ( RFSOURCE : in STD_LOGIC_VECTOR (1 downto 0);
DATATOMEM : in STD_LOGIC_VECTOR (31 downto 0);
ALURESULT : in STD_LOGIC_VECTOR (31 downto 0);
PC : in STD_LOGIC_VECTOR (31 downto 0);
DATATOREG : out STD_LOGIC_VECTOR (31 downto 0));
end MUX_RFSOURCE;
architecture Behavioral of MUX_RFSOURCE is
begin
process(RFSOURCE,DATATOMEM,ALURESULT)
begin
case RFSOURCE is
when "00"=>DATATOREG<=DATATOMEM;
when "01"=>DATATOREG<=ALURESULT;
when "10"=>DATATOREG<=PC;
when others=>DATATOREG<=(others=>'0');
end case;
end process;
end Behavioral;
|
mit
|
f7de846187b24c20eb01e42b0efe528b
| 0.648766 | 3.551546 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_wiz_0_0_family_support.vhd
| 1 | 404,661 |
--------------------------------------------------------------------------------
-- system_xadc_wiz_0_0_family_support.vhd - package
--------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
--------------------------------------------------------------------------------
-- Filename: system_xadc_wiz_0_0_family_support.vhd
--
-- Description:
--
-- FAMILIES, PRIMITIVES and PRIMITIVE AVAILABILITY GUARDS
--
-- This package allows to determine whether a given primitive
-- or set of primitives is available in an FPGA family of interest.
--
-- The key element is the function, 'supported', which is
-- available in four variants (overloads). Here are examples
-- of each:
--
-- supported(virtex2, u_RAMB16_S2)
--
-- supported("Virtex2", u_RAMB16_S2)
--
-- supported(spartan3, (u_MUXCY, u_XORCY, u_FD))
--
-- supported("spartan3", (u_MUXCY, u_XORCY, u_FD))
--
-- The 'supported' function returns true if and only
-- if all of the primitives being tested, as given in the
-- second argument, are available in the FPGA family that
-- is given in the first argument.
--
-- The first argument can be either one of the FPGA family
-- names from the enumeration type, 'families_type', or a
-- (case insensitive) string giving the same information.
-- The family name 'nofamily' is special and supports
-- none of the primitives.
--
-- The second argument is either a primitive or a list of
-- primitives. The set of primitive names that can be
-- tested is defined by the declaration of the
-- enumeration type, 'primitives_type'. The names are
-- the UNISIM-library names for the primitives, prefixed
-- by "u_". (The prefix avoids introducing a name that
-- conflicts with the component declaration for the primitive.)
--
-- The array type, 'primitive_array_type' is the basis for
-- forming lists of primitives. Typically, a fixed list
-- of primitves is expressed as a VHDL aggregate, a
-- comma separated list of primitives enclosed in
-- parentheses. (See the last two examples, above.)
--
-- The 'supported' function can be used as a guard
-- condition for a piece of code that depends on primitives
-- (primitive availability guard). Here is an example:
--
--
-- GEN : if supported(C_FAMILY, (u_MUXCY, u_XORCY)) generate
-- begin
-- ... Here, an implementation that depends on
-- ... MUXCY and XORCY.
-- end generate;
--
--
-- It can also be used in an assertion statement
-- to give warnings about problems that can arise from
-- attempting to implement into a family that does not
-- support all of the required primitives:
--
--
-- assert supported(C_FAMILY, <primtive list>)
-- report "This module cannot be implemnted " &
-- "into family, " & C_FAMILY &
-- ", because one or more of the primitives, " &
-- "<primitive_list>" & ", is not supported."
-- severity error;
--
--
-- A NOTE ON USAGE
--
-- It is probably best to take an exception to the coding
-- guidelines and make the names that are needed
-- from this package visible to a VHDL compilation unit by
--
-- library <libname>;
-- use <libname>.system_xadc_wiz_0_0_family_support.all;
--
-- rather than by calling out individual names in use clauses.
-- (VHDL tools do not have a common interpretation at present
-- on whether
--
-- use <libname>.system_xadc_wiz_0_0_family_support.primitives_type"
--
-- makes the enumeration literals visible.)
--
-- ADDITIONAL FEATURES
--
-- - A function, native_lut_size, is available to allow
-- the caller to query the largest sized LUT available in a given
-- FPGA family.
--
-- - A function, equalIgnoringCase, is available to compare strings
-- with case insensitivity. While this can be used to establish
-- whether the target family is some particular family, such
-- usage is discouraged and should be limited to legacy
-- situations or the rare situations where primitive
-- availability guards will not suffice.
--
--------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 2005Mar24 - First Version
--
-- FLO 11/30/05
-- ^^^^^^
-- Virtex5 added.
-- ~~~~~~
-- TK 03/17/06 Corrected a Spartan3e issue in myimage
-- ~~~~~~
-- FLO 04/26/06
-- ^^^^^^
-- Added the native_lut_size function.
-- ~~~~~~
-- FLO 08/10/06
-- ^^^^^^
-- Added support for families virtex, spartan2 and spartan2e.
-- ~~~~~~
-- FLO 08/25/06
-- ^^^^^^
-- Enhanced the warning in function str2fam. Now when a string that is
-- passed in the call as a parameter does not correspond to a supported fpga
-- family, the string value of the passed string is mentioned in the warning
-- and it is explicitly stated that the returned value is 'nofamily'.
-- ~~~~~~
-- FLO 08/26/06
-- ^^^^^^
-- - Updated the virtex5 primitive set to a more recent list and
-- removed primitives (TEMAC, PCIE, etc.) that are not present
-- in all virtex5 family members.
-- - Added function equalIgnoringCase and an admonition to use it
-- as little as possible.
-- - Made some improvements to descriptions inside comments.
-- ~~~~~~
-- FLO 08/28/06
-- ^^^^^^
-- Added support for families spartan3a and spartan3an. These are initially
-- taken to have the same primitives as spartan3e.
-- ~~~~~~
-- FLO 10/28/06
-- ^^^^^^
-- Changed function str2fam so that it no longer depends on the VHDL
-- attribute, 'VAL. This is an XST workaround.
-- ~~~~~~
-- FLO 03/08/07
-- ^^^^^^
-- Updated spartan3a and sparan3an.
-- Added spartan3adsp.
-- ~~~~~~
-- FLO 08/31/07
-- ^^^^^^
-- A performance XST workaround was implemented to address slowness
-- associated with primitive availability guards. The workaround changes
-- the way that the fam_has_prim constant is initialized (aggregate
-- rather than a system of function and procedure calls).
-- ~~~~~~
-- FLO 04/11/08
-- ^^^^^^
-- Added these families: aspartan3e, aspartan3a, aspartan3an, aspartan3adsp
-- ~~~~~~
-- FLO 04/14/08
-- ^^^^^^
-- Removed family: aspartan3an
-- ~~~~~~
-- FLO 06/25/08
-- ^^^^^^
-- Added these families: qvirtex4, qrvirtex4
-- ~~~~~~
-- FLO 07/26/08
-- ^^^^^^
-- The BSCAN primitive for spartan3e is now BSCAN_SPARTAN3 instead
-- of BSCAN_SPARTAN3E.
-- ~~~~~~
-- FLO 09/02/06
-- ^^^^^^
-- Added an initial approximation of primitives for spartan6 and virtex6.
-- ~~~~~~
-- FLO 09/04/28
-- ^^^^^^
-- -Removed primitive u_BSCAN_SPARTAN3A from spartan6.
-- -Added the 5 and 6 LUTs to spartan6.
-- ~~~~~~
-- FLO 02/09/10 (back to MM/DD/YY)
-- ^^^^^^
-- -Removed primitive u_BSCAN_VIRTEX5 from virtex6.
-- -Added families spartan6l, qspartan6, aspartan6 and virtex6l.
-- ~~~~~~
-- FLO 04/26/10 (MM/DD/YY)
-- ^^^^^^
-- -Added families qspartan6l, qvirtex5 and qvirtex6.
-- ~~~~~~
-- FLO 06/21/10 (MM/DD/YY)
-- ^^^^^^
-- -Added family qrvirtex5.
-- ~~~~~~
--
-- DET 9/7/2010 For 12.4
-- ~~~~~~
-- -- Per CR573867
-- - Added the function get_root_family() as part of the derivative part
-- support improvements.
-- - Added the Virtex7 and Kintex7 device families
-- ^^^^^^
-- ~~~~~~
-- FLO 10/28/10 (MM/DD/YY)
-- ^^^^^^
-- -Added u_SRLC32E as supported for spartan6 (and its derivatives). (CR 575828)
-- ~~~~~~
-- FLO 12/15/10 (MM/DD/YY)
-- ^^^^^^
-- -Changed virtex6cx to be equal to virtex6 (instead of virtex5)
-- -Move kintex7 and virtex7 to the primitives in the Rodin unisim.btl file
-- -Added artix7 from the primitives in the Rodin unisim.btl file
-- ~~~~~~
--
-- DET 3/2/2011 EDk 13.2
-- ~~~~~~
-- -- Per CR595477
-- - Added zynq support in the get_root_family function.
-- ^^^^^^
--
-- DET 03/18/2011
-- ^^^^^^
-- Per CR602290
-- - Added u_RAMB16_S4_S36 for kintex7, virtex7, artix7 to grandfather axi_ethernetlite_v1_00_a.
-- - This change was lost from 13.1 O.40d to 13.2 branch.
-- - Copied the Virtex7 primitive info to zynq primitive entry (instead of the artix7 info)
-- ~~~~~~
--
-- DET 4/4/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR604652
-- - Added kintex7l and virtex7l
-- ^^^^^^
--
--------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinational signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports:- Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
package system_xadc_wiz_0_0_family_support is
type families_type is
(
nofamily
, virtex
, spartan2
, spartan2e
, virtexe
, virtex2
, qvirtex2 -- Taken to be identical to the virtex2 primitive set.
, qrvirtex2 -- Taken to be identical to the virtex2 primitive set.
, virtex2p
, spartan3
, aspartan3
, virtex4
, virtex4lx
, virtex4fx
, virtex4sx
, spartan3e
, virtex5
, spartan3a
, spartan3an
, spartan3adsp
, aspartan3e
, aspartan3a
, aspartan3adsp
, qvirtex4
, qrvirtex4
, spartan6
, virtex6
, spartan6l
, qspartan6
, aspartan6
, virtex6l
, qspartan6l
, qvirtex5
, qvirtex6
, qrvirtex5
, virtex5tx
, virtex5fx
, virtex6cx
, kintex7
, kintex7l
, qkintex7
, qkintex7l
, virtex7
, virtex7l
, qvirtex7
, qvirtex7l
, artix7
, aartix7
, artix7l
, qartix7
, zynq
, azynq
, qzynq
);
type primitives_type is range 0 to 798;
constant u_AND2: primitives_type := 0;
constant u_AND2B1L: primitives_type := u_AND2 + 1;
constant u_AND3: primitives_type := u_AND2B1L + 1;
constant u_AND4: primitives_type := u_AND3 + 1;
constant u_AUTOBUF: primitives_type := u_AND4 + 1;
constant u_BSCAN_SPARTAN2: primitives_type := u_AUTOBUF + 1;
constant u_BSCAN_SPARTAN3: primitives_type := u_BSCAN_SPARTAN2 + 1;
constant u_BSCAN_SPARTAN3A: primitives_type := u_BSCAN_SPARTAN3 + 1;
constant u_BSCAN_SPARTAN3E: primitives_type := u_BSCAN_SPARTAN3A + 1;
constant u_BSCAN_SPARTAN6: primitives_type := u_BSCAN_SPARTAN3E + 1;
constant u_BSCAN_VIRTEX: primitives_type := u_BSCAN_SPARTAN6 + 1;
constant u_BSCAN_VIRTEX2: primitives_type := u_BSCAN_VIRTEX + 1;
constant u_BSCAN_VIRTEX4: primitives_type := u_BSCAN_VIRTEX2 + 1;
constant u_BSCAN_VIRTEX5: primitives_type := u_BSCAN_VIRTEX4 + 1;
constant u_BSCAN_VIRTEX6: primitives_type := u_BSCAN_VIRTEX5 + 1;
constant u_BUF: primitives_type := u_BSCAN_VIRTEX6 + 1;
constant u_BUFCF: primitives_type := u_BUF + 1;
constant u_BUFE: primitives_type := u_BUFCF + 1;
constant u_BUFG: primitives_type := u_BUFE + 1;
constant u_BUFGCE: primitives_type := u_BUFG + 1;
constant u_BUFGCE_1: primitives_type := u_BUFGCE + 1;
constant u_BUFGCTRL: primitives_type := u_BUFGCE_1 + 1;
constant u_BUFGDLL: primitives_type := u_BUFGCTRL + 1;
constant u_BUFGMUX: primitives_type := u_BUFGDLL + 1;
constant u_BUFGMUX_1: primitives_type := u_BUFGMUX + 1;
constant u_BUFGMUX_CTRL: primitives_type := u_BUFGMUX_1 + 1;
constant u_BUFGMUX_VIRTEX4: primitives_type := u_BUFGMUX_CTRL + 1;
constant u_BUFGP: primitives_type := u_BUFGMUX_VIRTEX4 + 1;
constant u_BUFH: primitives_type := u_BUFGP + 1;
constant u_BUFHCE: primitives_type := u_BUFH + 1;
constant u_BUFIO: primitives_type := u_BUFHCE + 1;
constant u_BUFIO2: primitives_type := u_BUFIO + 1;
constant u_BUFIO2_2CLK: primitives_type := u_BUFIO2 + 1;
constant u_BUFIO2FB: primitives_type := u_BUFIO2_2CLK + 1;
constant u_BUFIO2FB_2CLK: primitives_type := u_BUFIO2FB + 1;
constant u_BUFIODQS: primitives_type := u_BUFIO2FB_2CLK + 1;
constant u_BUFPLL: primitives_type := u_BUFIODQS + 1;
constant u_BUFPLL_MCB: primitives_type := u_BUFPLL + 1;
constant u_BUFR: primitives_type := u_BUFPLL_MCB + 1;
constant u_BUFT: primitives_type := u_BUFR + 1;
constant u_CAPTURE_SPARTAN2: primitives_type := u_BUFT + 1;
constant u_CAPTURE_SPARTAN3: primitives_type := u_CAPTURE_SPARTAN2 + 1;
constant u_CAPTURE_SPARTAN3A: primitives_type := u_CAPTURE_SPARTAN3 + 1;
constant u_CAPTURE_SPARTAN3E: primitives_type := u_CAPTURE_SPARTAN3A + 1;
constant u_CAPTURE_VIRTEX: primitives_type := u_CAPTURE_SPARTAN3E + 1;
constant u_CAPTURE_VIRTEX2: primitives_type := u_CAPTURE_VIRTEX + 1;
constant u_CAPTURE_VIRTEX4: primitives_type := u_CAPTURE_VIRTEX2 + 1;
constant u_CAPTURE_VIRTEX5: primitives_type := u_CAPTURE_VIRTEX4 + 1;
constant u_CAPTURE_VIRTEX6: primitives_type := u_CAPTURE_VIRTEX5 + 1;
constant u_CARRY4: primitives_type := u_CAPTURE_VIRTEX6 + 1;
constant u_CFGLUT5: primitives_type := u_CARRY4 + 1;
constant u_CLKDLL: primitives_type := u_CFGLUT5 + 1;
constant u_CLKDLLE: primitives_type := u_CLKDLL + 1;
constant u_CLKDLLHF: primitives_type := u_CLKDLLE + 1;
constant u_CRC32: primitives_type := u_CLKDLLHF + 1;
constant u_CRC64: primitives_type := u_CRC32 + 1;
constant u_DCIRESET: primitives_type := u_CRC64 + 1;
constant u_DCM: primitives_type := u_DCIRESET + 1;
constant u_DCM_ADV: primitives_type := u_DCM + 1;
constant u_DCM_BASE: primitives_type := u_DCM_ADV + 1;
constant u_DCM_CLKGEN: primitives_type := u_DCM_BASE + 1;
constant u_DCM_PS: primitives_type := u_DCM_CLKGEN + 1;
constant u_DNA_PORT: primitives_type := u_DCM_PS + 1;
constant u_DSP48: primitives_type := u_DNA_PORT + 1;
constant u_DSP48A: primitives_type := u_DSP48 + 1;
constant u_DSP48A1: primitives_type := u_DSP48A + 1;
constant u_DSP48E: primitives_type := u_DSP48A1 + 1;
constant u_DSP48E1: primitives_type := u_DSP48E + 1;
constant u_DUMMY_INV: primitives_type := u_DSP48E1 + 1;
constant u_DUMMY_NOR2: primitives_type := u_DUMMY_INV + 1;
constant u_EFUSE_USR: primitives_type := u_DUMMY_NOR2 + 1;
constant u_EMAC: primitives_type := u_EFUSE_USR + 1;
constant u_FD: primitives_type := u_EMAC + 1;
constant u_FD_1: primitives_type := u_FD + 1;
constant u_FDC: primitives_type := u_FD_1 + 1;
constant u_FDC_1: primitives_type := u_FDC + 1;
constant u_FDCE: primitives_type := u_FDC_1 + 1;
constant u_FDCE_1: primitives_type := u_FDCE + 1;
constant u_FDCP: primitives_type := u_FDCE_1 + 1;
constant u_FDCP_1: primitives_type := u_FDCP + 1;
constant u_FDCPE: primitives_type := u_FDCP_1 + 1;
constant u_FDCPE_1: primitives_type := u_FDCPE + 1;
constant u_FDDRCPE: primitives_type := u_FDCPE_1 + 1;
constant u_FDDRRSE: primitives_type := u_FDDRCPE + 1;
constant u_FDE: primitives_type := u_FDDRRSE + 1;
constant u_FDE_1: primitives_type := u_FDE + 1;
constant u_FDP: primitives_type := u_FDE_1 + 1;
constant u_FDP_1: primitives_type := u_FDP + 1;
constant u_FDPE: primitives_type := u_FDP_1 + 1;
constant u_FDPE_1: primitives_type := u_FDPE + 1;
constant u_FDR: primitives_type := u_FDPE_1 + 1;
constant u_FDR_1: primitives_type := u_FDR + 1;
constant u_FDRE: primitives_type := u_FDR_1 + 1;
constant u_FDRE_1: primitives_type := u_FDRE + 1;
constant u_FDRS: primitives_type := u_FDRE_1 + 1;
constant u_FDRS_1: primitives_type := u_FDRS + 1;
constant u_FDRSE: primitives_type := u_FDRS_1 + 1;
constant u_FDRSE_1: primitives_type := u_FDRSE + 1;
constant u_FDS: primitives_type := u_FDRSE_1 + 1;
constant u_FDS_1: primitives_type := u_FDS + 1;
constant u_FDSE: primitives_type := u_FDS_1 + 1;
constant u_FDSE_1: primitives_type := u_FDSE + 1;
constant u_FIFO16: primitives_type := u_FDSE_1 + 1;
constant u_FIFO18: primitives_type := u_FIFO16 + 1;
constant u_FIFO18_36: primitives_type := u_FIFO18 + 1;
constant u_FIFO18E1: primitives_type := u_FIFO18_36 + 1;
constant u_FIFO36: primitives_type := u_FIFO18E1 + 1;
constant u_FIFO36_72: primitives_type := u_FIFO36 + 1;
constant u_FIFO36E1: primitives_type := u_FIFO36_72 + 1;
constant u_FMAP: primitives_type := u_FIFO36E1 + 1;
constant u_FRAME_ECC_VIRTEX4: primitives_type := u_FMAP + 1;
constant u_FRAME_ECC_VIRTEX5: primitives_type := u_FRAME_ECC_VIRTEX4 + 1;
constant u_FRAME_ECC_VIRTEX6: primitives_type := u_FRAME_ECC_VIRTEX5 + 1;
constant u_GND: primitives_type := u_FRAME_ECC_VIRTEX6 + 1;
constant u_GT10_10GE_4: primitives_type := u_GND + 1;
constant u_GT10_10GE_8: primitives_type := u_GT10_10GE_4 + 1;
constant u_GT10_10GFC_4: primitives_type := u_GT10_10GE_8 + 1;
constant u_GT10_10GFC_8: primitives_type := u_GT10_10GFC_4 + 1;
constant u_GT10_AURORA_1: primitives_type := u_GT10_10GFC_8 + 1;
constant u_GT10_AURORA_2: primitives_type := u_GT10_AURORA_1 + 1;
constant u_GT10_AURORA_4: primitives_type := u_GT10_AURORA_2 + 1;
constant u_GT10_AURORAX_4: primitives_type := u_GT10_AURORA_4 + 1;
constant u_GT10_AURORAX_8: primitives_type := u_GT10_AURORAX_4 + 1;
constant u_GT10_CUSTOM: primitives_type := u_GT10_AURORAX_8 + 1;
constant u_GT10_INFINIBAND_1: primitives_type := u_GT10_CUSTOM + 1;
constant u_GT10_INFINIBAND_2: primitives_type := u_GT10_INFINIBAND_1 + 1;
constant u_GT10_INFINIBAND_4: primitives_type := u_GT10_INFINIBAND_2 + 1;
constant u_GT10_OC192_4: primitives_type := u_GT10_INFINIBAND_4 + 1;
constant u_GT10_OC192_8: primitives_type := u_GT10_OC192_4 + 1;
constant u_GT10_OC48_1: primitives_type := u_GT10_OC192_8 + 1;
constant u_GT10_OC48_2: primitives_type := u_GT10_OC48_1 + 1;
constant u_GT10_OC48_4: primitives_type := u_GT10_OC48_2 + 1;
constant u_GT10_PCI_EXPRESS_1: primitives_type := u_GT10_OC48_4 + 1;
constant u_GT10_PCI_EXPRESS_2: primitives_type := u_GT10_PCI_EXPRESS_1 + 1;
constant u_GT10_PCI_EXPRESS_4: primitives_type := u_GT10_PCI_EXPRESS_2 + 1;
constant u_GT10_XAUI_1: primitives_type := u_GT10_PCI_EXPRESS_4 + 1;
constant u_GT10_XAUI_2: primitives_type := u_GT10_XAUI_1 + 1;
constant u_GT10_XAUI_4: primitives_type := u_GT10_XAUI_2 + 1;
constant u_GT11CLK: primitives_type := u_GT10_XAUI_4 + 1;
constant u_GT11CLK_MGT: primitives_type := u_GT11CLK + 1;
constant u_GT11_CUSTOM: primitives_type := u_GT11CLK_MGT + 1;
constant u_GT_AURORA_1: primitives_type := u_GT11_CUSTOM + 1;
constant u_GT_AURORA_2: primitives_type := u_GT_AURORA_1 + 1;
constant u_GT_AURORA_4: primitives_type := u_GT_AURORA_2 + 1;
constant u_GT_CUSTOM: primitives_type := u_GT_AURORA_4 + 1;
constant u_GT_ETHERNET_1: primitives_type := u_GT_CUSTOM + 1;
constant u_GT_ETHERNET_2: primitives_type := u_GT_ETHERNET_1 + 1;
constant u_GT_ETHERNET_4: primitives_type := u_GT_ETHERNET_2 + 1;
constant u_GT_FIBRE_CHAN_1: primitives_type := u_GT_ETHERNET_4 + 1;
constant u_GT_FIBRE_CHAN_2: primitives_type := u_GT_FIBRE_CHAN_1 + 1;
constant u_GT_FIBRE_CHAN_4: primitives_type := u_GT_FIBRE_CHAN_2 + 1;
constant u_GT_INFINIBAND_1: primitives_type := u_GT_FIBRE_CHAN_4 + 1;
constant u_GT_INFINIBAND_2: primitives_type := u_GT_INFINIBAND_1 + 1;
constant u_GT_INFINIBAND_4: primitives_type := u_GT_INFINIBAND_2 + 1;
constant u_GTPA1_DUAL: primitives_type := u_GT_INFINIBAND_4 + 1;
constant u_GT_XAUI_1: primitives_type := u_GTPA1_DUAL + 1;
constant u_GT_XAUI_2: primitives_type := u_GT_XAUI_1 + 1;
constant u_GT_XAUI_4: primitives_type := u_GT_XAUI_2 + 1;
constant u_GTXE1: primitives_type := u_GT_XAUI_4 + 1;
constant u_IBUF: primitives_type := u_GTXE1 + 1;
constant u_IBUF_AGP: primitives_type := u_IBUF + 1;
constant u_IBUF_CTT: primitives_type := u_IBUF_AGP + 1;
constant u_IBUF_DLY_ADJ: primitives_type := u_IBUF_CTT + 1;
constant u_IBUFDS: primitives_type := u_IBUF_DLY_ADJ + 1;
constant u_IBUFDS_DIFF_OUT: primitives_type := u_IBUFDS + 1;
constant u_IBUFDS_DLY_ADJ: primitives_type := u_IBUFDS_DIFF_OUT + 1;
constant u_IBUFDS_GTXE1: primitives_type := u_IBUFDS_DLY_ADJ + 1;
constant u_IBUFG: primitives_type := u_IBUFDS_GTXE1 + 1;
constant u_IBUFG_AGP: primitives_type := u_IBUFG + 1;
constant u_IBUFG_CTT: primitives_type := u_IBUFG_AGP + 1;
constant u_IBUFGDS: primitives_type := u_IBUFG_CTT + 1;
constant u_IBUFGDS_DIFF_OUT: primitives_type := u_IBUFGDS + 1;
constant u_IBUFG_GTL: primitives_type := u_IBUFGDS_DIFF_OUT + 1;
constant u_IBUFG_GTLP: primitives_type := u_IBUFG_GTL + 1;
constant u_IBUFG_HSTL_I: primitives_type := u_IBUFG_GTLP + 1;
constant u_IBUFG_HSTL_III: primitives_type := u_IBUFG_HSTL_I + 1;
constant u_IBUFG_HSTL_IV: primitives_type := u_IBUFG_HSTL_III + 1;
constant u_IBUFG_LVCMOS18: primitives_type := u_IBUFG_HSTL_IV + 1;
constant u_IBUFG_LVCMOS2: primitives_type := u_IBUFG_LVCMOS18 + 1;
constant u_IBUFG_LVDS: primitives_type := u_IBUFG_LVCMOS2 + 1;
constant u_IBUFG_LVPECL: primitives_type := u_IBUFG_LVDS + 1;
constant u_IBUFG_PCI33_3: primitives_type := u_IBUFG_LVPECL + 1;
constant u_IBUFG_PCI33_5: primitives_type := u_IBUFG_PCI33_3 + 1;
constant u_IBUFG_PCI66_3: primitives_type := u_IBUFG_PCI33_5 + 1;
constant u_IBUFG_PCIX66_3: primitives_type := u_IBUFG_PCI66_3 + 1;
constant u_IBUFG_SSTL2_I: primitives_type := u_IBUFG_PCIX66_3 + 1;
constant u_IBUFG_SSTL2_II: primitives_type := u_IBUFG_SSTL2_I + 1;
constant u_IBUFG_SSTL3_I: primitives_type := u_IBUFG_SSTL2_II + 1;
constant u_IBUFG_SSTL3_II: primitives_type := u_IBUFG_SSTL3_I + 1;
constant u_IBUF_GTL: primitives_type := u_IBUFG_SSTL3_II + 1;
constant u_IBUF_GTLP: primitives_type := u_IBUF_GTL + 1;
constant u_IBUF_HSTL_I: primitives_type := u_IBUF_GTLP + 1;
constant u_IBUF_HSTL_III: primitives_type := u_IBUF_HSTL_I + 1;
constant u_IBUF_HSTL_IV: primitives_type := u_IBUF_HSTL_III + 1;
constant u_IBUF_LVCMOS18: primitives_type := u_IBUF_HSTL_IV + 1;
constant u_IBUF_LVCMOS2: primitives_type := u_IBUF_LVCMOS18 + 1;
constant u_IBUF_LVDS: primitives_type := u_IBUF_LVCMOS2 + 1;
constant u_IBUF_LVPECL: primitives_type := u_IBUF_LVDS + 1;
constant u_IBUF_PCI33_3: primitives_type := u_IBUF_LVPECL + 1;
constant u_IBUF_PCI33_5: primitives_type := u_IBUF_PCI33_3 + 1;
constant u_IBUF_PCI66_3: primitives_type := u_IBUF_PCI33_5 + 1;
constant u_IBUF_PCIX66_3: primitives_type := u_IBUF_PCI66_3 + 1;
constant u_IBUF_SSTL2_I: primitives_type := u_IBUF_PCIX66_3 + 1;
constant u_IBUF_SSTL2_II: primitives_type := u_IBUF_SSTL2_I + 1;
constant u_IBUF_SSTL3_I: primitives_type := u_IBUF_SSTL2_II + 1;
constant u_IBUF_SSTL3_II: primitives_type := u_IBUF_SSTL3_I + 1;
constant u_ICAP_SPARTAN3A: primitives_type := u_IBUF_SSTL3_II + 1;
constant u_ICAP_SPARTAN6: primitives_type := u_ICAP_SPARTAN3A + 1;
constant u_ICAP_VIRTEX2: primitives_type := u_ICAP_SPARTAN6 + 1;
constant u_ICAP_VIRTEX4: primitives_type := u_ICAP_VIRTEX2 + 1;
constant u_ICAP_VIRTEX5: primitives_type := u_ICAP_VIRTEX4 + 1;
constant u_ICAP_VIRTEX6: primitives_type := u_ICAP_VIRTEX5 + 1;
constant u_IDDR: primitives_type := u_ICAP_VIRTEX6 + 1;
constant u_IDDR2: primitives_type := u_IDDR + 1;
constant u_IDDR_2CLK: primitives_type := u_IDDR2 + 1;
constant u_IDELAY: primitives_type := u_IDDR_2CLK + 1;
constant u_IDELAYCTRL: primitives_type := u_IDELAY + 1;
constant u_IFDDRCPE: primitives_type := u_IDELAYCTRL + 1;
constant u_IFDDRRSE: primitives_type := u_IFDDRCPE + 1;
constant u_INV: primitives_type := u_IFDDRRSE + 1;
constant u_IOBUF: primitives_type := u_INV + 1;
constant u_IOBUF_AGP: primitives_type := u_IOBUF + 1;
constant u_IOBUF_CTT: primitives_type := u_IOBUF_AGP + 1;
constant u_IOBUFDS: primitives_type := u_IOBUF_CTT + 1;
constant u_IOBUFDS_DIFF_OUT: primitives_type := u_IOBUFDS + 1;
constant u_IOBUF_F_12: primitives_type := u_IOBUFDS_DIFF_OUT + 1;
constant u_IOBUF_F_16: primitives_type := u_IOBUF_F_12 + 1;
constant u_IOBUF_F_2: primitives_type := u_IOBUF_F_16 + 1;
constant u_IOBUF_F_24: primitives_type := u_IOBUF_F_2 + 1;
constant u_IOBUF_F_4: primitives_type := u_IOBUF_F_24 + 1;
constant u_IOBUF_F_6: primitives_type := u_IOBUF_F_4 + 1;
constant u_IOBUF_F_8: primitives_type := u_IOBUF_F_6 + 1;
constant u_IOBUF_GTL: primitives_type := u_IOBUF_F_8 + 1;
constant u_IOBUF_GTLP: primitives_type := u_IOBUF_GTL + 1;
constant u_IOBUF_HSTL_I: primitives_type := u_IOBUF_GTLP + 1;
constant u_IOBUF_HSTL_III: primitives_type := u_IOBUF_HSTL_I + 1;
constant u_IOBUF_HSTL_IV: primitives_type := u_IOBUF_HSTL_III + 1;
constant u_IOBUF_LVCMOS18: primitives_type := u_IOBUF_HSTL_IV + 1;
constant u_IOBUF_LVCMOS2: primitives_type := u_IOBUF_LVCMOS18 + 1;
constant u_IOBUF_LVDS: primitives_type := u_IOBUF_LVCMOS2 + 1;
constant u_IOBUF_LVPECL: primitives_type := u_IOBUF_LVDS + 1;
constant u_IOBUF_PCI33_3: primitives_type := u_IOBUF_LVPECL + 1;
constant u_IOBUF_PCI33_5: primitives_type := u_IOBUF_PCI33_3 + 1;
constant u_IOBUF_PCI66_3: primitives_type := u_IOBUF_PCI33_5 + 1;
constant u_IOBUF_PCIX66_3: primitives_type := u_IOBUF_PCI66_3 + 1;
constant u_IOBUF_S_12: primitives_type := u_IOBUF_PCIX66_3 + 1;
constant u_IOBUF_S_16: primitives_type := u_IOBUF_S_12 + 1;
constant u_IOBUF_S_2: primitives_type := u_IOBUF_S_16 + 1;
constant u_IOBUF_S_24: primitives_type := u_IOBUF_S_2 + 1;
constant u_IOBUF_S_4: primitives_type := u_IOBUF_S_24 + 1;
constant u_IOBUF_S_6: primitives_type := u_IOBUF_S_4 + 1;
constant u_IOBUF_S_8: primitives_type := u_IOBUF_S_6 + 1;
constant u_IOBUF_SSTL2_I: primitives_type := u_IOBUF_S_8 + 1;
constant u_IOBUF_SSTL2_II: primitives_type := u_IOBUF_SSTL2_I + 1;
constant u_IOBUF_SSTL3_I: primitives_type := u_IOBUF_SSTL2_II + 1;
constant u_IOBUF_SSTL3_II: primitives_type := u_IOBUF_SSTL3_I + 1;
constant u_IODELAY: primitives_type := u_IOBUF_SSTL3_II + 1;
constant u_IODELAY2: primitives_type := u_IODELAY + 1;
constant u_IODELAYE1: primitives_type := u_IODELAY2 + 1;
constant u_IODRP2: primitives_type := u_IODELAYE1 + 1;
constant u_IODRP2_MCB: primitives_type := u_IODRP2 + 1;
constant u_ISERDES: primitives_type := u_IODRP2_MCB + 1;
constant u_ISERDES2: primitives_type := u_ISERDES + 1;
constant u_ISERDESE1: primitives_type := u_ISERDES2 + 1;
constant u_ISERDES_NODELAY: primitives_type := u_ISERDESE1 + 1;
constant u_JTAGPPC: primitives_type := u_ISERDES_NODELAY + 1;
constant u_JTAG_SIM_SPARTAN6: primitives_type := u_JTAGPPC + 1;
constant u_JTAG_SIM_VIRTEX6: primitives_type := u_JTAG_SIM_SPARTAN6 + 1;
constant u_KEEPER: primitives_type := u_JTAG_SIM_VIRTEX6 + 1;
constant u_KEY_CLEAR: primitives_type := u_KEEPER + 1;
constant u_LD: primitives_type := u_KEY_CLEAR + 1;
constant u_LD_1: primitives_type := u_LD + 1;
constant u_LDC: primitives_type := u_LD_1 + 1;
constant u_LDC_1: primitives_type := u_LDC + 1;
constant u_LDCE: primitives_type := u_LDC_1 + 1;
constant u_LDCE_1: primitives_type := u_LDCE + 1;
constant u_LDCP: primitives_type := u_LDCE_1 + 1;
constant u_LDCP_1: primitives_type := u_LDCP + 1;
constant u_LDCPE: primitives_type := u_LDCP_1 + 1;
constant u_LDCPE_1: primitives_type := u_LDCPE + 1;
constant u_LDE: primitives_type := u_LDCPE_1 + 1;
constant u_LDE_1: primitives_type := u_LDE + 1;
constant u_LDP: primitives_type := u_LDE_1 + 1;
constant u_LDP_1: primitives_type := u_LDP + 1;
constant u_LDPE: primitives_type := u_LDP_1 + 1;
constant u_LDPE_1: primitives_type := u_LDPE + 1;
constant u_LUT1: primitives_type := u_LDPE_1 + 1;
constant u_LUT1_D: primitives_type := u_LUT1 + 1;
constant u_LUT1_L: primitives_type := u_LUT1_D + 1;
constant u_LUT2: primitives_type := u_LUT1_L + 1;
constant u_LUT2_D: primitives_type := u_LUT2 + 1;
constant u_LUT2_L: primitives_type := u_LUT2_D + 1;
constant u_LUT3: primitives_type := u_LUT2_L + 1;
constant u_LUT3_D: primitives_type := u_LUT3 + 1;
constant u_LUT3_L: primitives_type := u_LUT3_D + 1;
constant u_LUT4: primitives_type := u_LUT3_L + 1;
constant u_LUT4_D: primitives_type := u_LUT4 + 1;
constant u_LUT4_L: primitives_type := u_LUT4_D + 1;
constant u_LUT5: primitives_type := u_LUT4_L + 1;
constant u_LUT5_D: primitives_type := u_LUT5 + 1;
constant u_LUT5_L: primitives_type := u_LUT5_D + 1;
constant u_LUT6: primitives_type := u_LUT5_L + 1;
constant u_LUT6_D: primitives_type := u_LUT6 + 1;
constant u_LUT6_L: primitives_type := u_LUT6_D + 1;
constant u_MCB: primitives_type := u_LUT6_L + 1;
constant u_MMCM_ADV: primitives_type := u_MCB + 1;
constant u_MMCM_BASE: primitives_type := u_MMCM_ADV + 1;
constant u_MULT18X18: primitives_type := u_MMCM_BASE + 1;
constant u_MULT18X18S: primitives_type := u_MULT18X18 + 1;
constant u_MULT18X18SIO: primitives_type := u_MULT18X18S + 1;
constant u_MULT_AND: primitives_type := u_MULT18X18SIO + 1;
constant u_MUXCY: primitives_type := u_MULT_AND + 1;
constant u_MUXCY_D: primitives_type := u_MUXCY + 1;
constant u_MUXCY_L: primitives_type := u_MUXCY_D + 1;
constant u_MUXF5: primitives_type := u_MUXCY_L + 1;
constant u_MUXF5_D: primitives_type := u_MUXF5 + 1;
constant u_MUXF5_L: primitives_type := u_MUXF5_D + 1;
constant u_MUXF6: primitives_type := u_MUXF5_L + 1;
constant u_MUXF6_D: primitives_type := u_MUXF6 + 1;
constant u_MUXF6_L: primitives_type := u_MUXF6_D + 1;
constant u_MUXF7: primitives_type := u_MUXF6_L + 1;
constant u_MUXF7_D: primitives_type := u_MUXF7 + 1;
constant u_MUXF7_L: primitives_type := u_MUXF7_D + 1;
constant u_MUXF8: primitives_type := u_MUXF7_L + 1;
constant u_MUXF8_D: primitives_type := u_MUXF8 + 1;
constant u_MUXF8_L: primitives_type := u_MUXF8_D + 1;
constant u_NAND2: primitives_type := u_MUXF8_L + 1;
constant u_NAND3: primitives_type := u_NAND2 + 1;
constant u_NAND4: primitives_type := u_NAND3 + 1;
constant u_NOR2: primitives_type := u_NAND4 + 1;
constant u_NOR3: primitives_type := u_NOR2 + 1;
constant u_NOR4: primitives_type := u_NOR3 + 1;
constant u_OBUF: primitives_type := u_NOR4 + 1;
constant u_OBUF_AGP: primitives_type := u_OBUF + 1;
constant u_OBUF_CTT: primitives_type := u_OBUF_AGP + 1;
constant u_OBUFDS: primitives_type := u_OBUF_CTT + 1;
constant u_OBUF_F_12: primitives_type := u_OBUFDS + 1;
constant u_OBUF_F_16: primitives_type := u_OBUF_F_12 + 1;
constant u_OBUF_F_2: primitives_type := u_OBUF_F_16 + 1;
constant u_OBUF_F_24: primitives_type := u_OBUF_F_2 + 1;
constant u_OBUF_F_4: primitives_type := u_OBUF_F_24 + 1;
constant u_OBUF_F_6: primitives_type := u_OBUF_F_4 + 1;
constant u_OBUF_F_8: primitives_type := u_OBUF_F_6 + 1;
constant u_OBUF_GTL: primitives_type := u_OBUF_F_8 + 1;
constant u_OBUF_GTLP: primitives_type := u_OBUF_GTL + 1;
constant u_OBUF_HSTL_I: primitives_type := u_OBUF_GTLP + 1;
constant u_OBUF_HSTL_III: primitives_type := u_OBUF_HSTL_I + 1;
constant u_OBUF_HSTL_IV: primitives_type := u_OBUF_HSTL_III + 1;
constant u_OBUF_LVCMOS18: primitives_type := u_OBUF_HSTL_IV + 1;
constant u_OBUF_LVCMOS2: primitives_type := u_OBUF_LVCMOS18 + 1;
constant u_OBUF_LVDS: primitives_type := u_OBUF_LVCMOS2 + 1;
constant u_OBUF_LVPECL: primitives_type := u_OBUF_LVDS + 1;
constant u_OBUF_PCI33_3: primitives_type := u_OBUF_LVPECL + 1;
constant u_OBUF_PCI33_5: primitives_type := u_OBUF_PCI33_3 + 1;
constant u_OBUF_PCI66_3: primitives_type := u_OBUF_PCI33_5 + 1;
constant u_OBUF_PCIX66_3: primitives_type := u_OBUF_PCI66_3 + 1;
constant u_OBUF_S_12: primitives_type := u_OBUF_PCIX66_3 + 1;
constant u_OBUF_S_16: primitives_type := u_OBUF_S_12 + 1;
constant u_OBUF_S_2: primitives_type := u_OBUF_S_16 + 1;
constant u_OBUF_S_24: primitives_type := u_OBUF_S_2 + 1;
constant u_OBUF_S_4: primitives_type := u_OBUF_S_24 + 1;
constant u_OBUF_S_6: primitives_type := u_OBUF_S_4 + 1;
constant u_OBUF_S_8: primitives_type := u_OBUF_S_6 + 1;
constant u_OBUF_SSTL2_I: primitives_type := u_OBUF_S_8 + 1;
constant u_OBUF_SSTL2_II: primitives_type := u_OBUF_SSTL2_I + 1;
constant u_OBUF_SSTL3_I: primitives_type := u_OBUF_SSTL2_II + 1;
constant u_OBUF_SSTL3_II: primitives_type := u_OBUF_SSTL3_I + 1;
constant u_OBUFT: primitives_type := u_OBUF_SSTL3_II + 1;
constant u_OBUFT_AGP: primitives_type := u_OBUFT + 1;
constant u_OBUFT_CTT: primitives_type := u_OBUFT_AGP + 1;
constant u_OBUFTDS: primitives_type := u_OBUFT_CTT + 1;
constant u_OBUFT_F_12: primitives_type := u_OBUFTDS + 1;
constant u_OBUFT_F_16: primitives_type := u_OBUFT_F_12 + 1;
constant u_OBUFT_F_2: primitives_type := u_OBUFT_F_16 + 1;
constant u_OBUFT_F_24: primitives_type := u_OBUFT_F_2 + 1;
constant u_OBUFT_F_4: primitives_type := u_OBUFT_F_24 + 1;
constant u_OBUFT_F_6: primitives_type := u_OBUFT_F_4 + 1;
constant u_OBUFT_F_8: primitives_type := u_OBUFT_F_6 + 1;
constant u_OBUFT_GTL: primitives_type := u_OBUFT_F_8 + 1;
constant u_OBUFT_GTLP: primitives_type := u_OBUFT_GTL + 1;
constant u_OBUFT_HSTL_I: primitives_type := u_OBUFT_GTLP + 1;
constant u_OBUFT_HSTL_III: primitives_type := u_OBUFT_HSTL_I + 1;
constant u_OBUFT_HSTL_IV: primitives_type := u_OBUFT_HSTL_III + 1;
constant u_OBUFT_LVCMOS18: primitives_type := u_OBUFT_HSTL_IV + 1;
constant u_OBUFT_LVCMOS2: primitives_type := u_OBUFT_LVCMOS18 + 1;
constant u_OBUFT_LVDS: primitives_type := u_OBUFT_LVCMOS2 + 1;
constant u_OBUFT_LVPECL: primitives_type := u_OBUFT_LVDS + 1;
constant u_OBUFT_PCI33_3: primitives_type := u_OBUFT_LVPECL + 1;
constant u_OBUFT_PCI33_5: primitives_type := u_OBUFT_PCI33_3 + 1;
constant u_OBUFT_PCI66_3: primitives_type := u_OBUFT_PCI33_5 + 1;
constant u_OBUFT_PCIX66_3: primitives_type := u_OBUFT_PCI66_3 + 1;
constant u_OBUFT_S_12: primitives_type := u_OBUFT_PCIX66_3 + 1;
constant u_OBUFT_S_16: primitives_type := u_OBUFT_S_12 + 1;
constant u_OBUFT_S_2: primitives_type := u_OBUFT_S_16 + 1;
constant u_OBUFT_S_24: primitives_type := u_OBUFT_S_2 + 1;
constant u_OBUFT_S_4: primitives_type := u_OBUFT_S_24 + 1;
constant u_OBUFT_S_6: primitives_type := u_OBUFT_S_4 + 1;
constant u_OBUFT_S_8: primitives_type := u_OBUFT_S_6 + 1;
constant u_OBUFT_SSTL2_I: primitives_type := u_OBUFT_S_8 + 1;
constant u_OBUFT_SSTL2_II: primitives_type := u_OBUFT_SSTL2_I + 1;
constant u_OBUFT_SSTL3_I: primitives_type := u_OBUFT_SSTL2_II + 1;
constant u_OBUFT_SSTL3_II: primitives_type := u_OBUFT_SSTL3_I + 1;
constant u_OCT_CALIBRATE: primitives_type := u_OBUFT_SSTL3_II + 1;
constant u_ODDR: primitives_type := u_OCT_CALIBRATE + 1;
constant u_ODDR2: primitives_type := u_ODDR + 1;
constant u_OFDDRCPE: primitives_type := u_ODDR2 + 1;
constant u_OFDDRRSE: primitives_type := u_OFDDRCPE + 1;
constant u_OFDDRTCPE: primitives_type := u_OFDDRRSE + 1;
constant u_OFDDRTRSE: primitives_type := u_OFDDRTCPE + 1;
constant u_OR2: primitives_type := u_OFDDRTRSE + 1;
constant u_OR2L: primitives_type := u_OR2 + 1;
constant u_OR3: primitives_type := u_OR2L + 1;
constant u_OR4: primitives_type := u_OR3 + 1;
constant u_ORCY: primitives_type := u_OR4 + 1;
constant u_OSERDES: primitives_type := u_ORCY + 1;
constant u_OSERDES2: primitives_type := u_OSERDES + 1;
constant u_OSERDESE1: primitives_type := u_OSERDES2 + 1;
constant u_PCIE_2_0: primitives_type := u_OSERDESE1 + 1;
constant u_PCIE_A1: primitives_type := u_PCIE_2_0 + 1;
constant u_PLL_ADV: primitives_type := u_PCIE_A1 + 1;
constant u_PLL_BASE: primitives_type := u_PLL_ADV + 1;
constant u_PMCD: primitives_type := u_PLL_BASE + 1;
constant u_POST_CRC_INTERNAL: primitives_type := u_PMCD + 1;
constant u_PPC405: primitives_type := u_POST_CRC_INTERNAL + 1;
constant u_PPC405_ADV: primitives_type := u_PPC405 + 1;
constant u_PPR_FRAME: primitives_type := u_PPC405_ADV + 1;
constant u_PULLDOWN: primitives_type := u_PPR_FRAME + 1;
constant u_PULLUP: primitives_type := u_PULLDOWN + 1;
constant u_RAM128X1D: primitives_type := u_PULLUP + 1;
constant u_RAM128X1S: primitives_type := u_RAM128X1D + 1;
constant u_RAM128X1S_1: primitives_type := u_RAM128X1S + 1;
constant u_RAM16X1D: primitives_type := u_RAM128X1S_1 + 1;
constant u_RAM16X1D_1: primitives_type := u_RAM16X1D + 1;
constant u_RAM16X1S: primitives_type := u_RAM16X1D_1 + 1;
constant u_RAM16X1S_1: primitives_type := u_RAM16X1S + 1;
constant u_RAM16X2S: primitives_type := u_RAM16X1S_1 + 1;
constant u_RAM16X4S: primitives_type := u_RAM16X2S + 1;
constant u_RAM16X8S: primitives_type := u_RAM16X4S + 1;
constant u_RAM256X1S: primitives_type := u_RAM16X8S + 1;
constant u_RAM32M: primitives_type := u_RAM256X1S + 1;
constant u_RAM32X1D: primitives_type := u_RAM32M + 1;
constant u_RAM32X1D_1: primitives_type := u_RAM32X1D + 1;
constant u_RAM32X1S: primitives_type := u_RAM32X1D_1 + 1;
constant u_RAM32X1S_1: primitives_type := u_RAM32X1S + 1;
constant u_RAM32X2S: primitives_type := u_RAM32X1S_1 + 1;
constant u_RAM32X4S: primitives_type := u_RAM32X2S + 1;
constant u_RAM32X8S: primitives_type := u_RAM32X4S + 1;
constant u_RAM64M: primitives_type := u_RAM32X8S + 1;
constant u_RAM64X1D: primitives_type := u_RAM64M + 1;
constant u_RAM64X1D_1: primitives_type := u_RAM64X1D + 1;
constant u_RAM64X1S: primitives_type := u_RAM64X1D_1 + 1;
constant u_RAM64X1S_1: primitives_type := u_RAM64X1S + 1;
constant u_RAM64X2S: primitives_type := u_RAM64X1S_1 + 1;
constant u_RAMB16: primitives_type := u_RAM64X2S + 1;
constant u_RAMB16BWE: primitives_type := u_RAMB16 + 1;
constant u_RAMB16BWER: primitives_type := u_RAMB16BWE + 1;
constant u_RAMB16BWE_S18: primitives_type := u_RAMB16BWER + 1;
constant u_RAMB16BWE_S18_S18: primitives_type := u_RAMB16BWE_S18 + 1;
constant u_RAMB16BWE_S18_S9: primitives_type := u_RAMB16BWE_S18_S18 + 1;
constant u_RAMB16BWE_S36: primitives_type := u_RAMB16BWE_S18_S9 + 1;
constant u_RAMB16BWE_S36_S18: primitives_type := u_RAMB16BWE_S36 + 1;
constant u_RAMB16BWE_S36_S36: primitives_type := u_RAMB16BWE_S36_S18 + 1;
constant u_RAMB16BWE_S36_S9: primitives_type := u_RAMB16BWE_S36_S36 + 1;
constant u_RAMB16_S1: primitives_type := u_RAMB16BWE_S36_S9 + 1;
constant u_RAMB16_S18: primitives_type := u_RAMB16_S1 + 1;
constant u_RAMB16_S18_S18: primitives_type := u_RAMB16_S18 + 1;
constant u_RAMB16_S18_S36: primitives_type := u_RAMB16_S18_S18 + 1;
constant u_RAMB16_S1_S1: primitives_type := u_RAMB16_S18_S36 + 1;
constant u_RAMB16_S1_S18: primitives_type := u_RAMB16_S1_S1 + 1;
constant u_RAMB16_S1_S2: primitives_type := u_RAMB16_S1_S18 + 1;
constant u_RAMB16_S1_S36: primitives_type := u_RAMB16_S1_S2 + 1;
constant u_RAMB16_S1_S4: primitives_type := u_RAMB16_S1_S36 + 1;
constant u_RAMB16_S1_S9: primitives_type := u_RAMB16_S1_S4 + 1;
constant u_RAMB16_S2: primitives_type := u_RAMB16_S1_S9 + 1;
constant u_RAMB16_S2_S18: primitives_type := u_RAMB16_S2 + 1;
constant u_RAMB16_S2_S2: primitives_type := u_RAMB16_S2_S18 + 1;
constant u_RAMB16_S2_S36: primitives_type := u_RAMB16_S2_S2 + 1;
constant u_RAMB16_S2_S4: primitives_type := u_RAMB16_S2_S36 + 1;
constant u_RAMB16_S2_S9: primitives_type := u_RAMB16_S2_S4 + 1;
constant u_RAMB16_S36: primitives_type := u_RAMB16_S2_S9 + 1;
constant u_RAMB16_S36_S36: primitives_type := u_RAMB16_S36 + 1;
constant u_RAMB16_S4: primitives_type := u_RAMB16_S36_S36 + 1;
constant u_RAMB16_S4_S18: primitives_type := u_RAMB16_S4 + 1;
constant u_RAMB16_S4_S36: primitives_type := u_RAMB16_S4_S18 + 1;
constant u_RAMB16_S4_S4: primitives_type := u_RAMB16_S4_S36 + 1;
constant u_RAMB16_S4_S9: primitives_type := u_RAMB16_S4_S4 + 1;
constant u_RAMB16_S9: primitives_type := u_RAMB16_S4_S9 + 1;
constant u_RAMB16_S9_S18: primitives_type := u_RAMB16_S9 + 1;
constant u_RAMB16_S9_S36: primitives_type := u_RAMB16_S9_S18 + 1;
constant u_RAMB16_S9_S9: primitives_type := u_RAMB16_S9_S36 + 1;
constant u_RAMB18: primitives_type := u_RAMB16_S9_S9 + 1;
constant u_RAMB18E1: primitives_type := u_RAMB18 + 1;
constant u_RAMB18SDP: primitives_type := u_RAMB18E1 + 1;
constant u_RAMB32_S64_ECC: primitives_type := u_RAMB18SDP + 1;
constant u_RAMB36: primitives_type := u_RAMB32_S64_ECC + 1;
constant u_RAMB36E1: primitives_type := u_RAMB36 + 1;
constant u_RAMB36_EXP: primitives_type := u_RAMB36E1 + 1;
constant u_RAMB36SDP: primitives_type := u_RAMB36_EXP + 1;
constant u_RAMB36SDP_EXP: primitives_type := u_RAMB36SDP + 1;
constant u_RAMB4_S1: primitives_type := u_RAMB36SDP_EXP + 1;
constant u_RAMB4_S16: primitives_type := u_RAMB4_S1 + 1;
constant u_RAMB4_S16_S16: primitives_type := u_RAMB4_S16 + 1;
constant u_RAMB4_S1_S1: primitives_type := u_RAMB4_S16_S16 + 1;
constant u_RAMB4_S1_S16: primitives_type := u_RAMB4_S1_S1 + 1;
constant u_RAMB4_S1_S2: primitives_type := u_RAMB4_S1_S16 + 1;
constant u_RAMB4_S1_S4: primitives_type := u_RAMB4_S1_S2 + 1;
constant u_RAMB4_S1_S8: primitives_type := u_RAMB4_S1_S4 + 1;
constant u_RAMB4_S2: primitives_type := u_RAMB4_S1_S8 + 1;
constant u_RAMB4_S2_S16: primitives_type := u_RAMB4_S2 + 1;
constant u_RAMB4_S2_S2: primitives_type := u_RAMB4_S2_S16 + 1;
constant u_RAMB4_S2_S4: primitives_type := u_RAMB4_S2_S2 + 1;
constant u_RAMB4_S2_S8: primitives_type := u_RAMB4_S2_S4 + 1;
constant u_RAMB4_S4: primitives_type := u_RAMB4_S2_S8 + 1;
constant u_RAMB4_S4_S16: primitives_type := u_RAMB4_S4 + 1;
constant u_RAMB4_S4_S4: primitives_type := u_RAMB4_S4_S16 + 1;
constant u_RAMB4_S4_S8: primitives_type := u_RAMB4_S4_S4 + 1;
constant u_RAMB4_S8: primitives_type := u_RAMB4_S4_S8 + 1;
constant u_RAMB4_S8_S16: primitives_type := u_RAMB4_S8 + 1;
constant u_RAMB4_S8_S8: primitives_type := u_RAMB4_S8_S16 + 1;
constant u_RAMB8BWER: primitives_type := u_RAMB4_S8_S8 + 1;
constant u_ROM128X1: primitives_type := u_RAMB8BWER + 1;
constant u_ROM16X1: primitives_type := u_ROM128X1 + 1;
constant u_ROM256X1: primitives_type := u_ROM16X1 + 1;
constant u_ROM32X1: primitives_type := u_ROM256X1 + 1;
constant u_ROM64X1: primitives_type := u_ROM32X1 + 1;
constant u_SLAVE_SPI: primitives_type := u_ROM64X1 + 1;
constant u_SPI_ACCESS: primitives_type := u_SLAVE_SPI + 1;
constant u_SRL16: primitives_type := u_SPI_ACCESS + 1;
constant u_SRL16_1: primitives_type := u_SRL16 + 1;
constant u_SRL16E: primitives_type := u_SRL16_1 + 1;
constant u_SRL16E_1: primitives_type := u_SRL16E + 1;
constant u_SRLC16: primitives_type := u_SRL16E_1 + 1;
constant u_SRLC16_1: primitives_type := u_SRLC16 + 1;
constant u_SRLC16E: primitives_type := u_SRLC16_1 + 1;
constant u_SRLC16E_1: primitives_type := u_SRLC16E + 1;
constant u_SRLC32E: primitives_type := u_SRLC16E_1 + 1;
constant u_STARTBUF_SPARTAN2: primitives_type := u_SRLC32E + 1;
constant u_STARTBUF_SPARTAN3: primitives_type := u_STARTBUF_SPARTAN2 + 1;
constant u_STARTBUF_SPARTAN3E: primitives_type := u_STARTBUF_SPARTAN3 + 1;
constant u_STARTBUF_VIRTEX: primitives_type := u_STARTBUF_SPARTAN3E + 1;
constant u_STARTBUF_VIRTEX2: primitives_type := u_STARTBUF_VIRTEX + 1;
constant u_STARTBUF_VIRTEX4: primitives_type := u_STARTBUF_VIRTEX2 + 1;
constant u_STARTUP_SPARTAN2: primitives_type := u_STARTBUF_VIRTEX4 + 1;
constant u_STARTUP_SPARTAN3: primitives_type := u_STARTUP_SPARTAN2 + 1;
constant u_STARTUP_SPARTAN3A: primitives_type := u_STARTUP_SPARTAN3 + 1;
constant u_STARTUP_SPARTAN3E: primitives_type := u_STARTUP_SPARTAN3A + 1;
constant u_STARTUP_SPARTAN6: primitives_type := u_STARTUP_SPARTAN3E + 1;
constant u_STARTUP_VIRTEX: primitives_type := u_STARTUP_SPARTAN6 + 1;
constant u_STARTUP_VIRTEX2: primitives_type := u_STARTUP_VIRTEX + 1;
constant u_STARTUP_VIRTEX4: primitives_type := u_STARTUP_VIRTEX2 + 1;
constant u_STARTUP_VIRTEX5: primitives_type := u_STARTUP_VIRTEX4 + 1;
constant u_STARTUP_VIRTEX6: primitives_type := u_STARTUP_VIRTEX5 + 1;
constant u_SUSPEND_SYNC: primitives_type := u_STARTUP_VIRTEX6 + 1;
constant u_SYSMON: primitives_type := u_SUSPEND_SYNC + 1;
constant u_TEMAC_SINGLE: primitives_type := u_SYSMON + 1;
constant u_TOC: primitives_type := u_TEMAC_SINGLE + 1;
constant u_TOCBUF: primitives_type := u_TOC + 1;
constant u_USR_ACCESS_VIRTEX4: primitives_type := u_TOCBUF + 1;
constant u_USR_ACCESS_VIRTEX5: primitives_type := u_USR_ACCESS_VIRTEX4 + 1;
constant u_USR_ACCESS_VIRTEX6: primitives_type := u_USR_ACCESS_VIRTEX5 + 1;
constant u_VCC: primitives_type := u_USR_ACCESS_VIRTEX6 + 1;
constant u_XNOR2: primitives_type := u_VCC + 1;
constant u_XNOR3: primitives_type := u_XNOR2 + 1;
constant u_XNOR4: primitives_type := u_XNOR3 + 1;
constant u_XOR2: primitives_type := u_XNOR4 + 1;
constant u_XOR3: primitives_type := u_XOR2 + 1;
constant u_XOR4: primitives_type := u_XOR3 + 1;
constant u_XORCY: primitives_type := u_XOR4 + 1;
constant u_XORCY_D: primitives_type := u_XORCY + 1;
constant u_XORCY_L: primitives_type := u_XORCY_D + 1;
-- Primitives added for artix7, kintex6, virtex7, and zynq
constant u_AND2B1: primitives_type := u_XORCY_L + 1;
constant u_AND2B2: primitives_type := u_AND2B1 + 1;
constant u_AND3B1: primitives_type := u_AND2B2 + 1;
constant u_AND3B2: primitives_type := u_AND3B1 + 1;
constant u_AND3B3: primitives_type := u_AND3B2 + 1;
constant u_AND4B1: primitives_type := u_AND3B3 + 1;
constant u_AND4B2: primitives_type := u_AND4B1 + 1;
constant u_AND4B3: primitives_type := u_AND4B2 + 1;
constant u_AND4B4: primitives_type := u_AND4B3 + 1;
constant u_AND5: primitives_type := u_AND4B4 + 1;
constant u_AND5B1: primitives_type := u_AND5 + 1;
constant u_AND5B2: primitives_type := u_AND5B1 + 1;
constant u_AND5B3: primitives_type := u_AND5B2 + 1;
constant u_AND5B4: primitives_type := u_AND5B3 + 1;
constant u_AND5B5: primitives_type := u_AND5B4 + 1;
constant u_BSCANE2: primitives_type := u_AND5B5 + 1;
constant u_BUFMR: primitives_type := u_BSCANE2 + 1;
constant u_BUFMRCE: primitives_type := u_BUFMR + 1;
constant u_CAPTUREE2: primitives_type := u_BUFMRCE + 1;
constant u_CFG_IO_ACCESS: primitives_type := u_CAPTUREE2 + 1;
constant u_FRAME_ECCE2: primitives_type := u_CFG_IO_ACCESS + 1;
constant u_GTXE2_CHANNEL: primitives_type := u_FRAME_ECCE2 + 1;
constant u_GTXE2_COMMON: primitives_type := u_GTXE2_CHANNEL + 1;
constant u_IBUF_DCIEN: primitives_type := u_GTXE2_COMMON + 1;
constant u_IBUFDS_BLVDS_25: primitives_type := u_IBUF_DCIEN + 1;
constant u_IBUFDS_DCIEN: primitives_type := u_IBUFDS_BLVDS_25 + 1;
constant u_IBUFDS_DIFF_OUT_DCIEN: primitives_type := u_IBUFDS_DCIEN + 1;
constant u_IBUFDS_GTE2: primitives_type := u_IBUFDS_DIFF_OUT_DCIEN + 1;
constant u_IBUFDS_LVDS_25: primitives_type := u_IBUFDS_GTE2 + 1;
constant u_IBUFGDS_BLVDS_25: primitives_type := u_IBUFDS_LVDS_25 + 1;
constant u_IBUFGDS_LVDS_25: primitives_type := u_IBUFGDS_BLVDS_25 + 1;
constant u_IBUFG_HSTL_I_18: primitives_type := u_IBUFGDS_LVDS_25 + 1;
constant u_IBUFG_HSTL_I_DCI: primitives_type := u_IBUFG_HSTL_I_18 + 1;
constant u_IBUFG_HSTL_I_DCI_18: primitives_type := u_IBUFG_HSTL_I_DCI + 1;
constant u_IBUFG_HSTL_II: primitives_type := u_IBUFG_HSTL_I_DCI_18 + 1;
constant u_IBUFG_HSTL_II_18: primitives_type := u_IBUFG_HSTL_II + 1;
constant u_IBUFG_HSTL_II_DCI: primitives_type := u_IBUFG_HSTL_II_18 + 1;
constant u_IBUFG_HSTL_II_DCI_18: primitives_type := u_IBUFG_HSTL_II_DCI + 1;
constant u_IBUFG_HSTL_III_18: primitives_type := u_IBUFG_HSTL_II_DCI_18 + 1;
constant u_IBUFG_HSTL_III_DCI: primitives_type := u_IBUFG_HSTL_III_18 + 1;
constant u_IBUFG_HSTL_III_DCI_18: primitives_type := u_IBUFG_HSTL_III_DCI + 1;
constant u_IBUFG_LVCMOS12: primitives_type := u_IBUFG_HSTL_III_DCI_18 + 1;
constant u_IBUFG_LVCMOS15: primitives_type := u_IBUFG_LVCMOS12 + 1;
constant u_IBUFG_LVCMOS25: primitives_type := u_IBUFG_LVCMOS15 + 1;
constant u_IBUFG_LVCMOS33: primitives_type := u_IBUFG_LVCMOS25 + 1;
constant u_IBUFG_LVDCI_15: primitives_type := u_IBUFG_LVCMOS33 + 1;
constant u_IBUFG_LVDCI_18: primitives_type := u_IBUFG_LVDCI_15 + 1;
constant u_IBUFG_LVDCI_DV2_15: primitives_type := u_IBUFG_LVDCI_18 + 1;
constant u_IBUFG_LVDCI_DV2_18: primitives_type := u_IBUFG_LVDCI_DV2_15 + 1;
constant u_IBUFG_LVTTL: primitives_type := u_IBUFG_LVDCI_DV2_18 + 1;
constant u_IBUFG_SSTL18_I: primitives_type := u_IBUFG_LVTTL + 1;
constant u_IBUFG_SSTL18_I_DCI: primitives_type := u_IBUFG_SSTL18_I + 1;
constant u_IBUFG_SSTL18_II: primitives_type := u_IBUFG_SSTL18_I_DCI + 1;
constant u_IBUFG_SSTL18_II_DCI: primitives_type := u_IBUFG_SSTL18_II + 1;
constant u_IBUF_HSTL_I_18: primitives_type := u_IBUFG_SSTL18_II_DCI + 1;
constant u_IBUF_HSTL_I_DCI: primitives_type := u_IBUF_HSTL_I_18 + 1;
constant u_IBUF_HSTL_I_DCI_18: primitives_type := u_IBUF_HSTL_I_DCI + 1;
constant u_IBUF_HSTL_II: primitives_type := u_IBUF_HSTL_I_DCI_18 + 1;
constant u_IBUF_HSTL_II_18: primitives_type := u_IBUF_HSTL_II + 1;
constant u_IBUF_HSTL_II_DCI: primitives_type := u_IBUF_HSTL_II_18 + 1;
constant u_IBUF_HSTL_II_DCI_18: primitives_type := u_IBUF_HSTL_II_DCI + 1;
constant u_IBUF_HSTL_III_18: primitives_type := u_IBUF_HSTL_II_DCI_18 + 1;
constant u_IBUF_HSTL_III_DCI: primitives_type := u_IBUF_HSTL_III_18 + 1;
constant u_IBUF_HSTL_III_DCI_18: primitives_type := u_IBUF_HSTL_III_DCI + 1;
constant u_IBUF_LVCMOS12: primitives_type := u_IBUF_HSTL_III_DCI_18 + 1;
constant u_IBUF_LVCMOS15: primitives_type := u_IBUF_LVCMOS12 + 1;
constant u_IBUF_LVCMOS25: primitives_type := u_IBUF_LVCMOS15 + 1;
constant u_IBUF_LVCMOS33: primitives_type := u_IBUF_LVCMOS25 + 1;
constant u_IBUF_LVDCI_15: primitives_type := u_IBUF_LVCMOS33 + 1;
constant u_IBUF_LVDCI_18: primitives_type := u_IBUF_LVDCI_15 + 1;
constant u_IBUF_LVDCI_DV2_15: primitives_type := u_IBUF_LVDCI_18 + 1;
constant u_IBUF_LVDCI_DV2_18: primitives_type := u_IBUF_LVDCI_DV2_15 + 1;
constant u_IBUF_LVTTL: primitives_type := u_IBUF_LVDCI_DV2_18 + 1;
constant u_IBUF_SSTL18_I: primitives_type := u_IBUF_LVTTL + 1;
constant u_IBUF_SSTL18_I_DCI: primitives_type := u_IBUF_SSTL18_I + 1;
constant u_IBUF_SSTL18_II: primitives_type := u_IBUF_SSTL18_I_DCI + 1;
constant u_IBUF_SSTL18_II_DCI: primitives_type := u_IBUF_SSTL18_II + 1;
constant u_ICAPE2: primitives_type := u_IBUF_SSTL18_II_DCI + 1;
constant u_IDELAYE2: primitives_type := u_ICAPE2 + 1;
constant u_IN_FIFO: primitives_type := u_IDELAYE2 + 1;
constant u_IOBUFDS_BLVDS_25: primitives_type := u_IN_FIFO + 1;
constant u_IOBUFDS_DIFF_OUT_DCIEN: primitives_type := u_IOBUFDS_BLVDS_25 + 1;
constant u_IOBUF_HSTL_I_18: primitives_type := u_IOBUFDS_DIFF_OUT_DCIEN + 1;
constant u_IOBUF_HSTL_II: primitives_type := u_IOBUF_HSTL_I_18 + 1;
constant u_IOBUF_HSTL_II_18: primitives_type := u_IOBUF_HSTL_II + 1;
constant u_IOBUF_HSTL_II_DCI: primitives_type := u_IOBUF_HSTL_II_18 + 1;
constant u_IOBUF_HSTL_II_DCI_18: primitives_type := u_IOBUF_HSTL_II_DCI + 1;
constant u_IOBUF_HSTL_III_18: primitives_type := u_IOBUF_HSTL_II_DCI_18 + 1;
constant u_IOBUF_LVCMOS12: primitives_type := u_IOBUF_HSTL_III_18 + 1;
constant u_IOBUF_LVCMOS15: primitives_type := u_IOBUF_LVCMOS12 + 1;
constant u_IOBUF_LVCMOS25: primitives_type := u_IOBUF_LVCMOS15 + 1;
constant u_IOBUF_LVCMOS33: primitives_type := u_IOBUF_LVCMOS25 + 1;
constant u_IOBUF_LVDCI_15: primitives_type := u_IOBUF_LVCMOS33 + 1;
constant u_IOBUF_LVDCI_18: primitives_type := u_IOBUF_LVDCI_15 + 1;
constant u_IOBUF_LVDCI_DV2_15: primitives_type := u_IOBUF_LVDCI_18 + 1;
constant u_IOBUF_LVDCI_DV2_18: primitives_type := u_IOBUF_LVDCI_DV2_15 + 1;
constant u_IOBUF_LVTTL: primitives_type := u_IOBUF_LVDCI_DV2_18 + 1;
constant u_IOBUF_SSTL18_I: primitives_type := u_IOBUF_LVTTL + 1;
constant u_IOBUF_SSTL18_II: primitives_type := u_IOBUF_SSTL18_I + 1;
constant u_IOBUF_SSTL18_II_DCI: primitives_type := u_IOBUF_SSTL18_II + 1;
constant u_ISERDESE2: primitives_type := u_IOBUF_SSTL18_II_DCI + 1;
constant u_JTAG_SIME2: primitives_type := u_ISERDESE2 + 1;
constant u_LUT6_2: primitives_type := u_JTAG_SIME2 + 1;
constant u_MMCME2_ADV: primitives_type := u_LUT6_2 + 1;
constant u_MMCME2_BASE: primitives_type := u_MMCME2_ADV + 1;
constant u_NAND2B1: primitives_type := u_MMCME2_BASE + 1;
constant u_NAND2B2: primitives_type := u_NAND2B1 + 1;
constant u_NAND3B1: primitives_type := u_NAND2B2 + 1;
constant u_NAND3B2: primitives_type := u_NAND3B1 + 1;
constant u_NAND3B3: primitives_type := u_NAND3B2 + 1;
constant u_NAND4B1: primitives_type := u_NAND3B3 + 1;
constant u_NAND4B2: primitives_type := u_NAND4B1 + 1;
constant u_NAND4B3: primitives_type := u_NAND4B2 + 1;
constant u_NAND4B4: primitives_type := u_NAND4B3 + 1;
constant u_NAND5: primitives_type := u_NAND4B4 + 1;
constant u_NAND5B1: primitives_type := u_NAND5 + 1;
constant u_NAND5B2: primitives_type := u_NAND5B1 + 1;
constant u_NAND5B3: primitives_type := u_NAND5B2 + 1;
constant u_NAND5B4: primitives_type := u_NAND5B3 + 1;
constant u_NAND5B5: primitives_type := u_NAND5B4 + 1;
constant u_NOR2B1: primitives_type := u_NAND5B5 + 1;
constant u_NOR2B2: primitives_type := u_NOR2B1 + 1;
constant u_NOR3B1: primitives_type := u_NOR2B2 + 1;
constant u_NOR3B2: primitives_type := u_NOR3B1 + 1;
constant u_NOR3B3: primitives_type := u_NOR3B2 + 1;
constant u_NOR4B1: primitives_type := u_NOR3B3 + 1;
constant u_NOR4B2: primitives_type := u_NOR4B1 + 1;
constant u_NOR4B3: primitives_type := u_NOR4B2 + 1;
constant u_NOR4B4: primitives_type := u_NOR4B3 + 1;
constant u_NOR5: primitives_type := u_NOR4B4 + 1;
constant u_NOR5B1: primitives_type := u_NOR5 + 1;
constant u_NOR5B2: primitives_type := u_NOR5B1 + 1;
constant u_NOR5B3: primitives_type := u_NOR5B2 + 1;
constant u_NOR5B4: primitives_type := u_NOR5B3 + 1;
constant u_NOR5B5: primitives_type := u_NOR5B4 + 1;
constant u_OBUFDS_BLVDS_25: primitives_type := u_NOR5B5 + 1;
constant u_OBUFDS_DUAL_BUF: primitives_type := u_OBUFDS_BLVDS_25 + 1;
constant u_OBUFDS_LVDS_25: primitives_type := u_OBUFDS_DUAL_BUF + 1;
constant u_OBUF_HSTL_I_18: primitives_type := u_OBUFDS_LVDS_25 + 1;
constant u_OBUF_HSTL_I_DCI: primitives_type := u_OBUF_HSTL_I_18 + 1;
constant u_OBUF_HSTL_I_DCI_18: primitives_type := u_OBUF_HSTL_I_DCI + 1;
constant u_OBUF_HSTL_II: primitives_type := u_OBUF_HSTL_I_DCI_18 + 1;
constant u_OBUF_HSTL_II_18: primitives_type := u_OBUF_HSTL_II + 1;
constant u_OBUF_HSTL_II_DCI: primitives_type := u_OBUF_HSTL_II_18 + 1;
constant u_OBUF_HSTL_II_DCI_18: primitives_type := u_OBUF_HSTL_II_DCI + 1;
constant u_OBUF_HSTL_III_18: primitives_type := u_OBUF_HSTL_II_DCI_18 + 1;
constant u_OBUF_HSTL_III_DCI: primitives_type := u_OBUF_HSTL_III_18 + 1;
constant u_OBUF_HSTL_III_DCI_18: primitives_type := u_OBUF_HSTL_III_DCI + 1;
constant u_OBUF_LVCMOS12: primitives_type := u_OBUF_HSTL_III_DCI_18 + 1;
constant u_OBUF_LVCMOS15: primitives_type := u_OBUF_LVCMOS12 + 1;
constant u_OBUF_LVCMOS25: primitives_type := u_OBUF_LVCMOS15 + 1;
constant u_OBUF_LVCMOS33: primitives_type := u_OBUF_LVCMOS25 + 1;
constant u_OBUF_LVDCI_15: primitives_type := u_OBUF_LVCMOS33 + 1;
constant u_OBUF_LVDCI_18: primitives_type := u_OBUF_LVDCI_15 + 1;
constant u_OBUF_LVDCI_DV2_15: primitives_type := u_OBUF_LVDCI_18 + 1;
constant u_OBUF_LVDCI_DV2_18: primitives_type := u_OBUF_LVDCI_DV2_15 + 1;
constant u_OBUF_LVTTL: primitives_type := u_OBUF_LVDCI_DV2_18 + 1;
constant u_OBUF_SSTL18_I: primitives_type := u_OBUF_LVTTL + 1;
constant u_OBUF_SSTL18_I_DCI: primitives_type := u_OBUF_SSTL18_I + 1;
constant u_OBUF_SSTL18_II: primitives_type := u_OBUF_SSTL18_I_DCI + 1;
constant u_OBUF_SSTL18_II_DCI: primitives_type := u_OBUF_SSTL18_II + 1;
constant u_OBUFT_DCIEN: primitives_type := u_OBUF_SSTL18_II_DCI + 1;
constant u_OBUFTDS_BLVDS_25: primitives_type := u_OBUFT_DCIEN + 1;
constant u_OBUFTDS_DCIEN: primitives_type := u_OBUFTDS_BLVDS_25 + 1;
constant u_OBUFTDS_DCIEN_DUAL_BUF: primitives_type := u_OBUFTDS_DCIEN + 1;
constant u_OBUFTDS_DUAL_BUF: primitives_type := u_OBUFTDS_DCIEN_DUAL_BUF + 1;
constant u_OBUFTDS_LVDS_25: primitives_type := u_OBUFTDS_DUAL_BUF + 1;
constant u_OBUFT_HSTL_I_18: primitives_type := u_OBUFTDS_LVDS_25 + 1;
constant u_OBUFT_HSTL_I_DCI: primitives_type := u_OBUFT_HSTL_I_18 + 1;
constant u_OBUFT_HSTL_I_DCI_18: primitives_type := u_OBUFT_HSTL_I_DCI + 1;
constant u_OBUFT_HSTL_II: primitives_type := u_OBUFT_HSTL_I_DCI_18 + 1;
constant u_OBUFT_HSTL_II_18: primitives_type := u_OBUFT_HSTL_II + 1;
constant u_OBUFT_HSTL_II_DCI: primitives_type := u_OBUFT_HSTL_II_18 + 1;
constant u_OBUFT_HSTL_II_DCI_18: primitives_type := u_OBUFT_HSTL_II_DCI + 1;
constant u_OBUFT_HSTL_III_18: primitives_type := u_OBUFT_HSTL_II_DCI_18 + 1;
constant u_OBUFT_HSTL_III_DCI: primitives_type := u_OBUFT_HSTL_III_18 + 1;
constant u_OBUFT_HSTL_III_DCI_18: primitives_type := u_OBUFT_HSTL_III_DCI + 1;
constant u_OBUFT_LVCMOS12: primitives_type := u_OBUFT_HSTL_III_DCI_18 + 1;
constant u_OBUFT_LVCMOS15: primitives_type := u_OBUFT_LVCMOS12 + 1;
constant u_OBUFT_LVCMOS25: primitives_type := u_OBUFT_LVCMOS15 + 1;
constant u_OBUFT_LVCMOS33: primitives_type := u_OBUFT_LVCMOS25 + 1;
constant u_OBUFT_LVDCI_15: primitives_type := u_OBUFT_LVCMOS33 + 1;
constant u_OBUFT_LVDCI_18: primitives_type := u_OBUFT_LVDCI_15 + 1;
constant u_OBUFT_LVDCI_DV2_15: primitives_type := u_OBUFT_LVDCI_18 + 1;
constant u_OBUFT_LVDCI_DV2_18: primitives_type := u_OBUFT_LVDCI_DV2_15 + 1;
constant u_OBUFT_LVTTL: primitives_type := u_OBUFT_LVDCI_DV2_18 + 1;
constant u_OBUFT_SSTL18_I: primitives_type := u_OBUFT_LVTTL + 1;
constant u_OBUFT_SSTL18_I_DCI: primitives_type := u_OBUFT_SSTL18_I + 1;
constant u_OBUFT_SSTL18_II: primitives_type := u_OBUFT_SSTL18_I_DCI + 1;
constant u_OBUFT_SSTL18_II_DCI: primitives_type := u_OBUFT_SSTL18_II + 1;
constant u_ODELAYE2: primitives_type := u_OBUFT_SSTL18_II_DCI + 1;
constant u_OR2B1: primitives_type := u_ODELAYE2 + 1;
constant u_OR2B2: primitives_type := u_OR2B1 + 1;
constant u_OR3B1: primitives_type := u_OR2B2 + 1;
constant u_OR3B2: primitives_type := u_OR3B1 + 1;
constant u_OR3B3: primitives_type := u_OR3B2 + 1;
constant u_OR4B1: primitives_type := u_OR3B3 + 1;
constant u_OR4B2: primitives_type := u_OR4B1 + 1;
constant u_OR4B3: primitives_type := u_OR4B2 + 1;
constant u_OR4B4: primitives_type := u_OR4B3 + 1;
constant u_OR5: primitives_type := u_OR4B4 + 1;
constant u_OR5B1: primitives_type := u_OR5 + 1;
constant u_OR5B2: primitives_type := u_OR5B1 + 1;
constant u_OR5B3: primitives_type := u_OR5B2 + 1;
constant u_OR5B4: primitives_type := u_OR5B3 + 1;
constant u_OR5B5: primitives_type := u_OR5B4 + 1;
constant u_OSERDESE2: primitives_type := u_OR5B5 + 1;
constant u_OUT_FIFO: primitives_type := u_OSERDESE2 + 1;
constant u_PCIE_2_1: primitives_type := u_OUT_FIFO + 1;
constant u_PHASER_IN: primitives_type := u_PCIE_2_1 + 1;
constant u_PHASER_IN_PHY: primitives_type := u_PHASER_IN + 1;
constant u_PHASER_OUT: primitives_type := u_PHASER_IN_PHY + 1;
constant u_PHASER_OUT_PHY: primitives_type := u_PHASER_OUT + 1;
constant u_PHASER_REF: primitives_type := u_PHASER_OUT_PHY + 1;
constant u_PHY_CONTROL: primitives_type := u_PHASER_REF + 1;
constant u_PLLE2_ADV: primitives_type := u_PHY_CONTROL + 1;
constant u_PLLE2_BASE: primitives_type := u_PLLE2_ADV + 1;
constant u_PSS: primitives_type := u_PLLE2_BASE + 1;
constant u_RAMD32: primitives_type := u_PSS + 1;
constant u_RAMD64E: primitives_type := u_RAMD32 + 1;
constant u_RAMS32: primitives_type := u_RAMD64E + 1;
constant u_RAMS64E: primitives_type := u_RAMS32 + 1;
constant u_SIM_CONFIGE2: primitives_type := u_RAMS64E + 1;
constant u_STARTUPE2: primitives_type := u_SIM_CONFIGE2 + 1;
constant u_USR_ACCESSE2: primitives_type := u_STARTUPE2 + 1;
constant u_XADC: primitives_type := u_USR_ACCESSE2 + 1;
constant u_XNOR5: primitives_type := u_XADC + 1;
constant u_XOR5: primitives_type := u_XNOR5 + 1;
constant u_ZHOLD_DELAY: primitives_type := u_XOR5 + 1;
type primitive_array_type is array (natural range <>) of primitives_type;
----------------------------------------------------------------------------
-- Returns true if primitive is available in family.
--
-- Examples:
--
-- supported(virtex2, u_RAMB16_S2) returns true because the RAMB16_S2
-- primitive is available in the
-- virtex2 family.
--
-- supported(spartan3, u_RAM4B_S4) returns false because the RAMB4_S4
-- primitive is not available in the
-- spartan3 family.
----------------------------------------------------------------------------
function supported( family : families_type;
primitive : primitives_type
) return boolean;
----------------------------------------------------------------------------
-- This is an overload of function 'supported' (see above). It allows a list
-- of primitives to be tested.
--
-- Returns true if all of primitives in the list are available in family.
--
-- Example: supported(spartan3, (u_MUXCY, u_XORCY, u_FD))
-- is
-- equivalent to: supported(spartan3, u_MUXCY) and
-- supported(spartan3, u_XORCY) and
-- supported(spartan3, u_FD);
----------------------------------------------------------------------------
function supported( family : families_type;
primitives : primitive_array_type
) return boolean;
----------------------------------------------------------------------------
-- Below, are overloads of function 'supported' that allow the family
-- parameter to be passed as a string. These correspond to the above two
-- functions otherwise.
----------------------------------------------------------------------------
function supported( fam_as_str : string;
primitive : primitives_type
) return boolean;
function supported( fam_as_str : string;
primitives : primitive_array_type
) return boolean;
----------------------------------------------------------------------------
-- Conversions from/to STRING to/from families_type.
-- These are convenience functions that are not normally needed when
-- using the 'supported' functions.
----------------------------------------------------------------------------
function str2fam( fam_as_string : string ) return families_type;
function fam2str( fam : families_type ) return string;
----------------------------------------------------------------------------
-- Function: native_lut_size
--
-- Returns the largest LUT size available in FPGA family, fam.
-- If no LUT is available in fam, then returns zero by default, unless
-- the call specifies a no_lut_return_val, in which case this value
-- is returned.
--
-- The function is available in two overload versions, one for each
-- way of passing the fam argument.
----------------------------------------------------------------------------
function native_lut_size( fam : families_type;
no_lut_return_val : natural := 0
) return natural;
function native_lut_size( fam_as_string : string;
no_lut_return_val : natural := 0
) return natural;
----------------------------------------------------------------------------
-- Function: equalIgnoringCase
--
-- Compare one string against another for equality with case insensitivity.
-- Can be used to test see if a family, C_FAMILY, is equal to some
-- family. However such usage is discouraged. Use instead availability
-- primitive guards based on the function, 'supported', wherever possible.
----------------------------------------------------------------------------
function equalIgnoringCase( str1, str2 : string ) return boolean;
----------------------------------------------------------------------------
-- Function: get_root_family
--
-- This function takes in the string for the desired FPGA family type and
-- returns the root FPGA family type. This is used for derivative part
-- aliasing to the root family.
----------------------------------------------------------------------------
function get_root_family( family_in : string ) return string;
end package system_xadc_wiz_0_0_family_support;
package body system_xadc_wiz_0_0_family_support is
type prim_status_type is (
n -- no
, y -- yes
, u -- unknown, not used. However, we use
-- an enumeration to allow for
-- possible future enhancement.
);
type fam_prim_status is array (primitives_type) of prim_status_type;
type fam_has_prim_type is array (families_type) of fam_prim_status;
-- Performance workaround (XST procedure and function handling).
-- The fam_has_prim constant is initialized by an aggregate rather than by the
-- following function. A version of this file with this function not
-- commented was employed in building the aggregate. So, what is below still
-- defines the family-primitive matirix.
--# ----------------------------------------------------------------------------
--# -- This function is used to populate the matrix of family/primitive values.
--# ----------------------------------------------------------------------------
--# ---(
--# function prim_population return fam_has_prim_type is
--# variable pp : fam_has_prim_type := (others => (others => n));
--#
--# procedure set_to( stat : prim_status_type
--# ; fam : families_type
--# ; prim_list : primitive_array_type
--# ) is
--# begin
--# for i in prim_list'range loop
--# pp(fam)(prim_list(i)) := stat;
--# end loop;
--# end set_to;
--#
--# begin
--# set_to(y, virtex, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX
--# , u_CLKDLL
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_IBUFG_AGP
--# , u_IBUFG_CTT
--# , u_IBUFG_GTL
--# , u_IBUFG_GTLP
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_IV
--# , u_IBUFG_LVCMOS2
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI33_5
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_SSTL2_I
--# , u_IBUFG_SSTL2_II
--# , u_IBUFG_SSTL3_I
--# , u_IBUFG_SSTL3_II
--# , u_IBUF_AGP
--# , u_IBUF_CTT
--# , u_IBUF_GTL
--# , u_IBUF_GTLP
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_IV
--# , u_IBUF_LVCMOS2
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI33_5
--# , u_IBUF_PCI66_3
--# , u_IBUF_SSTL2_I
--# , u_IBUF_SSTL2_II
--# , u_IBUF_SSTL3_I
--# , u_IBUF_SSTL3_II
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF_AGP
--# , u_IOBUF_CTT
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_GTL
--# , u_IOBUF_GTLP
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_IV
--# , u_IOBUF_LVCMOS2
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI33_5
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_SSTL2_I
--# , u_IOBUF_SSTL2_II
--# , u_IOBUF_SSTL3_I
--# , u_IOBUF_SSTL3_II
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OBUFT_AGP
--# , u_OBUFT_CTT
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_GTL
--# , u_OBUFT_GTLP
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_IV
--# , u_OBUFT_LVCMOS2
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI33_5
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_SSTL2_I
--# , u_OBUFT_SSTL2_II
--# , u_OBUFT_SSTL3_I
--# , u_OBUFT_SSTL3_II
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUF_AGP
--# , u_OBUF_CTT
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_GTL
--# , u_OBUF_GTLP
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_IV
--# , u_OBUF_LVCMOS2
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI33_5
--# , u_OBUF_PCI66_3
--# , u_OBUF_SSTL2_I
--# , u_OBUF_SSTL2_II
--# , u_OBUF_SSTL3_I
--# , u_OBUF_SSTL3_II
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_VIRTEX
--# , u_STARTUP_VIRTEX
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# set_to(y, spartan2, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_SPARTAN2
--# , u_CLKDLL
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_IBUFG_AGP
--# , u_IBUFG_CTT
--# , u_IBUFG_GTL
--# , u_IBUFG_GTLP
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_IV
--# , u_IBUFG_LVCMOS2
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI33_5
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_SSTL2_I
--# , u_IBUFG_SSTL2_II
--# , u_IBUFG_SSTL3_I
--# , u_IBUFG_SSTL3_II
--# , u_IBUF_AGP
--# , u_IBUF_CTT
--# , u_IBUF_GTL
--# , u_IBUF_GTLP
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_IV
--# , u_IBUF_LVCMOS2
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI33_5
--# , u_IBUF_PCI66_3
--# , u_IBUF_SSTL2_I
--# , u_IBUF_SSTL2_II
--# , u_IBUF_SSTL3_I
--# , u_IBUF_SSTL3_II
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF_AGP
--# , u_IOBUF_CTT
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_GTL
--# , u_IOBUF_GTLP
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_IV
--# , u_IOBUF_LVCMOS2
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI33_5
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_SSTL2_I
--# , u_IOBUF_SSTL2_II
--# , u_IOBUF_SSTL3_I
--# , u_IOBUF_SSTL3_II
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OBUFT_AGP
--# , u_OBUFT_CTT
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_GTL
--# , u_OBUFT_GTLP
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_IV
--# , u_OBUFT_LVCMOS2
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI33_5
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_SSTL2_I
--# , u_OBUFT_SSTL2_II
--# , u_OBUFT_SSTL3_I
--# , u_OBUFT_SSTL3_II
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUF_AGP
--# , u_OBUF_CTT
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_GTL
--# , u_OBUF_GTLP
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_IV
--# , u_OBUF_LVCMOS2
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI33_5
--# , u_OBUF_PCI66_3
--# , u_OBUF_SSTL2_I
--# , u_OBUF_SSTL2_II
--# , u_OBUF_SSTL3_I
--# , u_OBUF_SSTL3_II
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_SPARTAN2
--# , u_STARTUP_SPARTAN2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# set_to(y, spartan2e, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_SPARTAN2
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_IBUFG_AGP
--# , u_IBUFG_CTT
--# , u_IBUFG_GTL
--# , u_IBUFG_GTLP
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_IV
--# , u_IBUFG_LVCMOS18
--# , u_IBUFG_LVCMOS2
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_PCIX66_3
--# , u_IBUFG_SSTL2_I
--# , u_IBUFG_SSTL2_II
--# , u_IBUFG_SSTL3_I
--# , u_IBUFG_SSTL3_II
--# , u_IBUF_AGP
--# , u_IBUF_CTT
--# , u_IBUF_GTL
--# , u_IBUF_GTLP
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_IV
--# , u_IBUF_LVCMOS18
--# , u_IBUF_LVCMOS2
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI66_3
--# , u_IBUF_PCIX66_3
--# , u_IBUF_SSTL2_I
--# , u_IBUF_SSTL2_II
--# , u_IBUF_SSTL3_I
--# , u_IBUF_SSTL3_II
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF_AGP
--# , u_IOBUF_CTT
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_GTL
--# , u_IOBUF_GTLP
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_IV
--# , u_IOBUF_LVCMOS18
--# , u_IOBUF_LVCMOS2
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_SSTL2_I
--# , u_IOBUF_SSTL2_II
--# , u_IOBUF_SSTL3_I
--# , u_IOBUF_SSTL3_II
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OBUFT_AGP
--# , u_OBUFT_CTT
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_GTL
--# , u_OBUFT_GTLP
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_IV
--# , u_OBUFT_LVCMOS18
--# , u_OBUFT_LVCMOS2
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_SSTL2_I
--# , u_OBUFT_SSTL2_II
--# , u_OBUFT_SSTL3_I
--# , u_OBUFT_SSTL3_II
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUF_AGP
--# , u_OBUF_CTT
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_GTL
--# , u_OBUF_GTLP
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_IV
--# , u_OBUF_LVCMOS18
--# , u_OBUF_LVCMOS2
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI66_3
--# , u_OBUF_PCIX66_3
--# , u_OBUF_SSTL2_I
--# , u_OBUF_SSTL2_II
--# , u_OBUF_SSTL3_I
--# , u_OBUF_SSTL3_II
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_SPARTAN2
--# , u_STARTUP_SPARTAN2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# set_to(y, virtexe, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_INV
--# , u_IOBUF
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_VIRTEX
--# , u_STARTUP_VIRTEX
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# set_to(y, virtex2, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX2
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_VIRTEX2
--# , u_STARTUP_VIRTEX2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(qvirtex2) := pp(virtex2);
--# --
--# pp(qrvirtex2) := pp(virtex2);
--# --
--# set_to(y, virtex2p,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX2
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_GT10_10GE_4
--# , u_GT10_10GE_8
--# , u_GT10_10GFC_4
--# , u_GT10_10GFC_8
--# , u_GT10_AURORAX_4
--# , u_GT10_AURORAX_8
--# , u_GT10_AURORA_1
--# , u_GT10_AURORA_2
--# , u_GT10_AURORA_4
--# , u_GT10_CUSTOM
--# , u_GT10_INFINIBAND_1
--# , u_GT10_INFINIBAND_2
--# , u_GT10_INFINIBAND_4
--# , u_GT10_OC192_4
--# , u_GT10_OC192_8
--# , u_GT10_OC48_1
--# , u_GT10_OC48_2
--# , u_GT10_OC48_4
--# , u_GT10_PCI_EXPRESS_1
--# , u_GT10_PCI_EXPRESS_2
--# , u_GT10_PCI_EXPRESS_4
--# , u_GT10_XAUI_1
--# , u_GT10_XAUI_2
--# , u_GT10_XAUI_4
--# , u_GT_AURORA_1
--# , u_GT_AURORA_2
--# , u_GT_AURORA_4
--# , u_GT_CUSTOM
--# , u_GT_ETHERNET_1
--# , u_GT_ETHERNET_2
--# , u_GT_ETHERNET_4
--# , u_GT_FIBRE_CHAN_1
--# , u_GT_FIBRE_CHAN_2
--# , u_GT_FIBRE_CHAN_4
--# , u_GT_INFINIBAND_1
--# , u_GT_INFINIBAND_2
--# , u_GT_INFINIBAND_4
--# , u_GT_XAUI_1
--# , u_GT_XAUI_2
--# , u_GT_XAUI_4
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_JTAGPPC
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PPC405
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_VIRTEX2
--# , u_STARTUP_VIRTEX2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# set_to(y, spartan3,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN3
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_CAPTURE_SPARTAN3
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_SPARTAN3
--# , u_STARTUP_SPARTAN3
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(aspartan3) := pp(spartan3);
--# --
--# set_to(y, spartan3e,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN3
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_CAPTURE_SPARTAN3E
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_IDDR2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT18X18SIO
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR2
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_SPARTAN3E
--# , u_STARTUP_SPARTAN3E
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(aspartan3e) := pp(spartan3e);
--# --
--# set_to(y, virtex4fx,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX4
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_VIRTEX4
--# , u_BUFGP
--# , u_BUFGP
--# , u_BUFIO
--# , u_BUFR
--# , u_CAPTURE_VIRTEX4
--# , u_DCIRESET
--# , u_DCM
--# , u_DCM_ADV
--# , u_DCM_BASE
--# , u_DCM_PS
--# , u_DSP48
--# , u_EMAC
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FIFO16
--# , u_FMAP
--# , u_FRAME_ECC_VIRTEX4
--# , u_GND
--# , u_GT11CLK
--# , u_GT11CLK_MGT
--# , u_GT11_CUSTOM
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX4
--# , u_IDDR
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_ISERDES
--# , u_JTAGPPC
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_OSERDES
--# , u_PMCD
--# , u_PPC405
--# , u_PPC405_ADV
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB32_S64_ECC
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_VIRTEX4
--# , u_STARTUP_VIRTEX4
--# , u_TOC
--# , u_TOCBUF
--# , u_USR_ACCESS_VIRTEX4
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(virtex4sx) := pp(virtex4fx);
--# --
--# pp(virtex4lx) := pp(virtex4fx);
--# set_to(n, virtex4lx, (u_EMAC,
--# u_GT11CLK, u_GT11CLK_MGT, u_GT11_CUSTOM,
--# u_JTAGPPC, u_PPC405, u_PPC405_ADV
--# ) );
--# --
--# pp(virtex4) := pp(virtex4lx); -- virtex4 is defined as the largest set
--# -- of primitives that EVERY virtex4
--# -- device supports, i.e.. a design that uses
--# -- the virtex4 subset of primitives
--# -- is compatible with any variant of
--# -- the virtex4 family.
--# --
--# pp(qvirtex4) := pp(virtex4);
--# --
--# pp(qrvirtex4) := pp(virtex4);
--# --
--# set_to(y, virtex5,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX5
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_CTRL
--# , u_BUFGP
--# , u_BUFIO
--# , u_BUFR
--# , u_CAPTURE_VIRTEX5
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_CRC32
--# , u_CRC64
--# , u_DCIRESET
--# , u_DCM
--# , u_DCM_ADV
--# , u_DCM_BASE
--# , u_DCM_PS
--# , u_DSP48
--# , u_DSP48E
--# , u_EMAC
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FIFO16
--# , u_FIFO18
--# , u_FIFO18_36
--# , u_FIFO36
--# , u_FIFO36_72
--# , u_FMAP
--# , u_FRAME_ECC_VIRTEX5
--# , u_GND
--# , u_GT11CLK
--# , u_GT11CLK_MGT
--# , u_GT11_CUSTOM
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX5
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IODELAY
--# , u_ISERDES
--# , u_ISERDES_NODELAY
--# , u_KEEPER
--# , u_KEY_CLEAR
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_OSERDES
--# , u_PLL_ADV
--# , u_PLL_BASE
--# , u_PMCD
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB18
--# , u_RAMB18SDP
--# , u_RAMB32_S64_ECC
--# , u_RAMB36
--# , u_RAMB36SDP
--# , u_RAMB36SDP_EXP
--# , u_RAMB36_EXP
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_SRLC32E
--# , u_STARTUP_VIRTEX5
--# , u_SYSMON
--# , u_TOC
--# , u_TOCBUF
--# , u_USR_ACCESS_VIRTEX5
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(spartan3a) := pp(spartan3e); -- Populate spartan3a by taking
--# -- differences from spartan3e.
--# set_to(n, spartan3a, (
--# u_BSCAN_SPARTAN3
--# , u_CAPTURE_SPARTAN3E
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_STARTBUF_SPARTAN3E
--# , u_STARTUP_SPARTAN3E
--# ) );
--# set_to(y, spartan3a, (
--# u_BSCAN_SPARTAN3A
--# , u_CAPTURE_SPARTAN3A
--# , u_DCM_PS
--# , u_DNA_PORT
--# , u_IBUF_DLY_ADJ
--# , u_IBUFDS_DLY_ADJ
--# , u_ICAP_SPARTAN3A
--# , u_RAMB16BWE
--# , u_RAMB16BWE_S18
--# , u_RAMB16BWE_S18_S18
--# , u_RAMB16BWE_S18_S9
--# , u_RAMB16BWE_S36
--# , u_RAMB16BWE_S36_S18
--# , u_RAMB16BWE_S36_S36
--# , u_RAMB16BWE_S36_S9
--# , u_SPI_ACCESS
--# , u_STARTUP_SPARTAN3A
--# ) );
--#
--# --
--# pp(aspartan3a) := pp(spartan3a);
--# --
--# pp(spartan3an) := pp(spartan3a);
--# --
--# pp(spartan3adsp) := pp(spartan3a);
--# set_to(y, spartan3adsp, (
--# u_DSP48A
--# , u_RAMB16BWER
--# ) );
--# --
--# pp(aspartan3adsp) := pp(spartan3adsp);
--# --
--# set_to(y, spartan6, (
--# u_AND2
--# , u_AND2B1L
--# , u_AND3
--# , u_AND4
--# , u_AUTOBUF
--# , u_BSCAN_SPARTAN6
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFIO2
--# , u_BUFIO2_2CLK
--# , u_BUFIO2FB
--# , u_BUFIO2FB_2CLK
--# , u_BUFPLL
--# , u_BUFPLL_MCB
--# , u_CAPTURE_SPARTAN3A
--# , u_DCM
--# , u_DCM_CLKGEN
--# , u_DCM_PS
--# , u_DNA_PORT
--# , u_DSP48A1
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FMAP
--# , u_GND
--# , u_GTPA1_DUAL
--# , u_IBUF
--# , u_IBUF_DLY_ADJ
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DLY_ADJ
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_SPARTAN3A
--# , u_ICAP_SPARTAN6
--# , u_IDDR2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IODELAY2
--# , u_IODRP2
--# , u_IODRP2_MCB
--# , u_ISERDES2
--# , u_JTAG_SIM_SPARTAN6
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MCB
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT18X18SIO
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OCT_CALIBRATE
--# , u_ODDR2
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR2L
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_OSERDES2
--# , u_PCIE_A1
--# , u_PLL_ADV
--# , u_POST_CRC_INTERNAL
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAMB16BWE
--# , u_RAMB16BWE_S18
--# , u_RAMB16BWE_S18_S18
--# , u_RAMB16BWE_S18_S9
--# , u_RAMB16BWE_S36
--# , u_RAMB16BWE_S36_S18
--# , u_RAMB16BWE_S36_S36
--# , u_RAMB16BWE_S36_S9
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB8BWER
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SLAVE_SPI
--# , u_SPI_ACCESS
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUP_SPARTAN3A
--# , u_STARTUP_SPARTAN6
--# , u_SUSPEND_SYNC
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# ) );
--# --
--# --
--# set_to(y, virtex6, (
--# u_AND2
--# , u_AND2B1L
--# , u_AND3
--# , u_AND4
--# , u_AUTOBUF
--# , u_BSCAN_VIRTEX6
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_CTRL
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFIODQS
--# , u_BUFR
--# , u_CAPTURE_VIRTEX5
--# , u_CAPTURE_VIRTEX6
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_CRC32
--# , u_CRC64
--# , u_DCIRESET
--# , u_DCIRESET
--# , u_DCM
--# , u_DCM_ADV
--# , u_DCM_BASE
--# , u_DCM_PS
--# , u_DSP48
--# , u_DSP48E
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_EMAC
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO16
--# , u_FIFO18
--# , u_FIFO18_36
--# , u_FIFO18E1
--# , u_FIFO36
--# , u_FIFO36_72
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECC_VIRTEX5
--# , u_FRAME_ECC_VIRTEX6
--# , u_GND
--# , u_GT11CLK
--# , u_GT11CLK_MGT
--# , u_GT11_CUSTOM
--# , u_GTXE1
--# , u_IBUF
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_GTXE1
--# , u_IBUFG
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX5
--# , u_ICAP_VIRTEX6
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS
--# , u_IOBUFDS_DIFF_OUT
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDES
--# , u_ISERDESE1
--# , u_ISERDES_NODELAY
--# , u_JTAG_SIM_VIRTEX6
--# , u_KEEPER
--# , u_KEY_CLEAR
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCM_ADV
--# , u_MMCM_BASE
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR2L
--# , u_OR3
--# , u_OR4
--# , u_OSERDES
--# , u_OSERDESE1
--# , u_PCIE_2_0
--# , u_PLL_ADV
--# , u_PLL_BASE
--# , u_PMCD
--# , u_PPR_FRAME
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB18
--# , u_RAMB18E1
--# , u_RAMB18SDP
--# , u_RAMB32_S64_ECC
--# , u_RAMB36
--# , u_RAMB36E1
--# , u_RAMB36_EXP
--# , u_RAMB36SDP
--# , u_RAMB36SDP_EXP
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUP_VIRTEX5
--# , u_STARTUP_VIRTEX6
--# , u_SYSMON
--# , u_SYSMON
--# , u_TEMAC_SINGLE
--# , u_TOC
--# , u_TOCBUF
--# , u_USR_ACCESS_VIRTEX5
--# , u_USR_ACCESS_VIRTEX6
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# ) );
--# --
--# pp(spartan6l) := pp(spartan6);
--# --
--# pp(qspartan6) := pp(spartan6);
--# --
--# pp(aspartan6) := pp(spartan6);
--# --
--# pp(virtex6l) := pp(virtex6);
--# --
--# pp(qspartan6l) := pp(spartan6);
--# --
--# pp(qvirtex5) := pp(virtex5);
--# --
--# pp(qvirtex6) := pp(virtex6);
--# --
--# pp(qrvirtex5) := pp(virtex5);
--# --
--# pp(virtex5tx) := pp(virtex5);
--# --
--# pp(virtex5fx) := pp(virtex5);
--# --
--# pp(virtex6cx) := pp(virtex6);
--# --
--# set_to(y, kintex7, (
--# u_AND2
--# , u_AND2B1
--# , u_AND2B1L
--# , u_AND2B2
--# , u_AND3
--# , u_AND3B1
--# , u_AND3B2
--# , u_AND3B3
--# , u_AND4
--# , u_AND4B1
--# , u_AND4B2
--# , u_AND4B3
--# , u_AND4B4
--# , u_AND5
--# , u_AND5B1
--# , u_AND5B2
--# , u_AND5B3
--# , u_AND5B4
--# , u_AND5B5
--# , u_AUTOBUF
--# , u_BSCANE2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFMR
--# , u_BUFMRCE
--# , u_BUFR
--# , u_BUFT
--# , u_CAPTUREE2
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_DCIRESET
--# , u_DNA_PORT
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO18E1
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECCE2
--# , u_GND
--# , u_GTXE2_CHANNEL
--# , u_GTXE2_COMMON
--# , u_IBUF
--# , u_IBUF_DCIEN
--# , u_IBUFDS
--# , u_IBUFDS_BLVDS_25
--# , u_IBUFDS_DCIEN
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DIFF_OUT_DCIEN
--# , u_IBUFDS_GTE2
--# , u_IBUFDS_LVDS_25
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_BLVDS_25
--# , u_IBUFGDS_DIFF_OUT
--# , u_IBUFGDS_LVDS_25
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_I_18
--# , u_IBUFG_HSTL_I_DCI
--# , u_IBUFG_HSTL_I_DCI_18
--# , u_IBUFG_HSTL_II
--# , u_IBUFG_HSTL_II_18
--# , u_IBUFG_HSTL_II_DCI
--# , u_IBUFG_HSTL_II_DCI_18
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_III_18
--# , u_IBUFG_HSTL_III_DCI
--# , u_IBUFG_HSTL_III_DCI_18
--# , u_IBUFG_LVCMOS12
--# , u_IBUFG_LVCMOS15
--# , u_IBUFG_LVCMOS18
--# , u_IBUFG_LVCMOS25
--# , u_IBUFG_LVCMOS33
--# , u_IBUFG_LVDCI_15
--# , u_IBUFG_LVDCI_18
--# , u_IBUFG_LVDCI_DV2_15
--# , u_IBUFG_LVDCI_DV2_18
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_LVTTL
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_PCIX66_3
--# , u_IBUFG_SSTL18_I
--# , u_IBUFG_SSTL18_I_DCI
--# , u_IBUFG_SSTL18_II
--# , u_IBUFG_SSTL18_II_DCI
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_I_18
--# , u_IBUF_HSTL_I_DCI
--# , u_IBUF_HSTL_I_DCI_18
--# , u_IBUF_HSTL_II
--# , u_IBUF_HSTL_II_18
--# , u_IBUF_HSTL_II_DCI
--# , u_IBUF_HSTL_II_DCI_18
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_III_18
--# , u_IBUF_HSTL_III_DCI
--# , u_IBUF_HSTL_III_DCI_18
--# , u_IBUF_LVCMOS12
--# , u_IBUF_LVCMOS15
--# , u_IBUF_LVCMOS18
--# , u_IBUF_LVCMOS25
--# , u_IBUF_LVCMOS33
--# , u_IBUF_LVDCI_15
--# , u_IBUF_LVDCI_18
--# , u_IBUF_LVDCI_DV2_15
--# , u_IBUF_LVDCI_DV2_18
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_LVTTL
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI66_3
--# , u_IBUF_PCIX66_3
--# , u_IBUF_SSTL18_I
--# , u_IBUF_SSTL18_I_DCI
--# , u_IBUF_SSTL18_II
--# , u_IBUF_SSTL18_II_DCI
--# , u_ICAPE2
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IDELAYE2
--# , u_IN_FIFO
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS_BLVDS_25
--# , u_IOBUFDS_DIFF_OUT
--# , u_IOBUFDS_DIFF_OUT_DCIEN
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_I_18
--# , u_IOBUF_HSTL_II
--# , u_IOBUF_HSTL_II_18
--# , u_IOBUF_HSTL_II_DCI
--# , u_IOBUF_HSTL_II_DCI_18
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_III_18
--# , u_IOBUF_LVCMOS12
--# , u_IOBUF_LVCMOS15
--# , u_IOBUF_LVCMOS18
--# , u_IOBUF_LVCMOS25
--# , u_IOBUF_LVCMOS33
--# , u_IOBUF_LVDCI_15
--# , u_IOBUF_LVDCI_18
--# , u_IOBUF_LVDCI_DV2_15
--# , u_IOBUF_LVDCI_DV2_18
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_LVTTL
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_IOBUF_SSTL18_I
--# , u_IOBUF_SSTL18_II
--# , u_IOBUF_SSTL18_II_DCI
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDESE2
--# , u_JTAG_SIME2
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_2
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCME2_ADV
--# , u_MMCME2_BASE
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND2B1
--# , u_NAND2B2
--# , u_NAND3
--# , u_NAND3B1
--# , u_NAND3B2
--# , u_NAND3B3
--# , u_NAND4
--# , u_NAND4B1
--# , u_NAND4B2
--# , u_NAND4B3
--# , u_NAND4B4
--# , u_NAND5
--# , u_NAND5B1
--# , u_NAND5B2
--# , u_NAND5B3
--# , u_NAND5B4
--# , u_NAND5B5
--# , u_NOR2
--# , u_NOR2B1
--# , u_NOR2B2
--# , u_NOR3
--# , u_NOR3B1
--# , u_NOR3B2
--# , u_NOR3B3
--# , u_NOR4
--# , u_NOR4B1
--# , u_NOR4B2
--# , u_NOR4B3
--# , u_NOR4B4
--# , u_NOR5
--# , u_NOR5B1
--# , u_NOR5B2
--# , u_NOR5B3
--# , u_NOR5B4
--# , u_NOR5B5
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFDS_BLVDS_25
--# , u_OBUFDS_DUAL_BUF
--# , u_OBUFDS_LVDS_25
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_I_18
--# , u_OBUF_HSTL_I_DCI
--# , u_OBUF_HSTL_I_DCI_18
--# , u_OBUF_HSTL_II
--# , u_OBUF_HSTL_II_18
--# , u_OBUF_HSTL_II_DCI
--# , u_OBUF_HSTL_II_DCI_18
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_III_18
--# , u_OBUF_HSTL_III_DCI
--# , u_OBUF_HSTL_III_DCI_18
--# , u_OBUF_LVCMOS12
--# , u_OBUF_LVCMOS15
--# , u_OBUF_LVCMOS18
--# , u_OBUF_LVCMOS25
--# , u_OBUF_LVCMOS33
--# , u_OBUF_LVDCI_15
--# , u_OBUF_LVDCI_18
--# , u_OBUF_LVDCI_DV2_15
--# , u_OBUF_LVDCI_DV2_18
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_LVTTL
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI66_3
--# , u_OBUF_PCIX66_3
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OBUF_SSTL18_I
--# , u_OBUF_SSTL18_I_DCI
--# , u_OBUF_SSTL18_II
--# , u_OBUF_SSTL18_II_DCI
--# , u_OBUFT
--# , u_OBUFT_DCIEN
--# , u_OBUFTDS
--# , u_OBUFTDS_BLVDS_25
--# , u_OBUFTDS_DCIEN
--# , u_OBUFTDS_DCIEN_DUAL_BUF
--# , u_OBUFTDS_DUAL_BUF
--# , u_OBUFTDS_LVDS_25
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_I_18
--# , u_OBUFT_HSTL_I_DCI
--# , u_OBUFT_HSTL_I_DCI_18
--# , u_OBUFT_HSTL_II
--# , u_OBUFT_HSTL_II_18
--# , u_OBUFT_HSTL_II_DCI
--# , u_OBUFT_HSTL_II_DCI_18
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_III_18
--# , u_OBUFT_HSTL_III_DCI
--# , u_OBUFT_HSTL_III_DCI_18
--# , u_OBUFT_LVCMOS12
--# , u_OBUFT_LVCMOS15
--# , u_OBUFT_LVCMOS18
--# , u_OBUFT_LVCMOS25
--# , u_OBUFT_LVCMOS33
--# , u_OBUFT_LVDCI_15
--# , u_OBUFT_LVDCI_18
--# , u_OBUFT_LVDCI_DV2_15
--# , u_OBUFT_LVDCI_DV2_18
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_LVTTL
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUFT_SSTL18_I
--# , u_OBUFT_SSTL18_I_DCI
--# , u_OBUFT_SSTL18_II
--# , u_OBUFT_SSTL18_II_DCI
--# , u_ODDR
--# , u_ODELAYE2
--# , u_OR2
--# , u_OR2B1
--# , u_OR2B2
--# , u_OR2L
--# , u_OR3
--# , u_OR3B1
--# , u_OR3B2
--# , u_OR3B3
--# , u_OR4
--# , u_OR4B1
--# , u_OR4B2
--# , u_OR4B3
--# , u_OR4B4
--# , u_OR5
--# , u_OR5B1
--# , u_OR5B2
--# , u_OR5B3
--# , u_OR5B4
--# , u_OR5B5
--# , u_OSERDESE2
--# , u_OUT_FIFO
--# , u_PCIE_2_1
--# , u_PHASER_IN
--# , u_PHASER_IN_PHY
--# , u_PHASER_OUT
--# , u_PHASER_OUT_PHY
--# , u_PHASER_REF
--# , u_PHY_CONTROL
--# , u_PLLE2_ADV
--# , u_PLLE2_BASE
--# , u_PSS
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S4_S36
--# , u_RAMB18E1
--# , u_RAMB36E1
--# , u_RAMD32
--# , u_RAMD64E
--# , u_RAMS32
--# , u_RAMS64E
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SIM_CONFIGE2
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUPE2
--# , u_USR_ACCESSE2
--# , u_VCC
--# , u_XADC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XNOR5
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XOR5
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# , u_ZHOLD_DELAY
--# ) );
--# --
--# set_to(y, virtex7, (
--# u_AND2
--# , u_AND2B1
--# , u_AND2B1L
--# , u_AND2B2
--# , u_AND3
--# , u_AND3B1
--# , u_AND3B2
--# , u_AND3B3
--# , u_AND4
--# , u_AND4B1
--# , u_AND4B2
--# , u_AND4B3
--# , u_AND4B4
--# , u_AND5
--# , u_AND5B1
--# , u_AND5B2
--# , u_AND5B3
--# , u_AND5B4
--# , u_AND5B5
--# , u_AUTOBUF
--# , u_BSCANE2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFMR
--# , u_BUFMRCE
--# , u_BUFR
--# , u_BUFT
--# , u_CAPTUREE2
--# , u_CARRY4
--# , u_CFG_IO_ACCESS
--# , u_CFGLUT5
--# , u_DCIRESET
--# , u_DNA_PORT
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO18E1
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECCE2
--# , u_GND
--# , u_GTXE2_CHANNEL
--# , u_GTXE2_COMMON
--# , u_IBUF
--# , u_IBUF_DCIEN
--# , u_IBUFDS
--# , u_IBUFDS_BLVDS_25
--# , u_IBUFDS_DCIEN
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DIFF_OUT_DCIEN
--# , u_IBUFDS_GTE2
--# , u_IBUFDS_LVDS_25
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_BLVDS_25
--# , u_IBUFGDS_DIFF_OUT
--# , u_IBUFGDS_LVDS_25
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_I_18
--# , u_IBUFG_HSTL_I_DCI
--# , u_IBUFG_HSTL_I_DCI_18
--# , u_IBUFG_HSTL_II
--# , u_IBUFG_HSTL_II_18
--# , u_IBUFG_HSTL_II_DCI
--# , u_IBUFG_HSTL_II_DCI_18
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_III_18
--# , u_IBUFG_HSTL_III_DCI
--# , u_IBUFG_HSTL_III_DCI_18
--# , u_IBUFG_LVCMOS12
--# , u_IBUFG_LVCMOS15
--# , u_IBUFG_LVCMOS18
--# , u_IBUFG_LVCMOS25
--# , u_IBUFG_LVCMOS33
--# , u_IBUFG_LVDCI_15
--# , u_IBUFG_LVDCI_18
--# , u_IBUFG_LVDCI_DV2_15
--# , u_IBUFG_LVDCI_DV2_18
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_LVTTL
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_PCIX66_3
--# , u_IBUFG_SSTL18_I
--# , u_IBUFG_SSTL18_I_DCI
--# , u_IBUFG_SSTL18_II
--# , u_IBUFG_SSTL18_II_DCI
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_I_18
--# , u_IBUF_HSTL_I_DCI
--# , u_IBUF_HSTL_I_DCI_18
--# , u_IBUF_HSTL_II
--# , u_IBUF_HSTL_II_18
--# , u_IBUF_HSTL_II_DCI
--# , u_IBUF_HSTL_II_DCI_18
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_III_18
--# , u_IBUF_HSTL_III_DCI
--# , u_IBUF_HSTL_III_DCI_18
--# , u_IBUF_LVCMOS12
--# , u_IBUF_LVCMOS15
--# , u_IBUF_LVCMOS18
--# , u_IBUF_LVCMOS25
--# , u_IBUF_LVCMOS33
--# , u_IBUF_LVDCI_15
--# , u_IBUF_LVDCI_18
--# , u_IBUF_LVDCI_DV2_15
--# , u_IBUF_LVDCI_DV2_18
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_LVTTL
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI66_3
--# , u_IBUF_PCIX66_3
--# , u_IBUF_SSTL18_I
--# , u_IBUF_SSTL18_I_DCI
--# , u_IBUF_SSTL18_II
--# , u_IBUF_SSTL18_II_DCI
--# , u_ICAPE2
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IDELAYE2
--# , u_IN_FIFO
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS_BLVDS_25
--# , u_IOBUFDS_DIFF_OUT
--# , u_IOBUFDS_DIFF_OUT_DCIEN
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_I_18
--# , u_IOBUF_HSTL_II
--# , u_IOBUF_HSTL_II_18
--# , u_IOBUF_HSTL_II_DCI
--# , u_IOBUF_HSTL_II_DCI_18
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_III_18
--# , u_IOBUF_LVCMOS12
--# , u_IOBUF_LVCMOS15
--# , u_IOBUF_LVCMOS18
--# , u_IOBUF_LVCMOS25
--# , u_IOBUF_LVCMOS33
--# , u_IOBUF_LVDCI_15
--# , u_IOBUF_LVDCI_18
--# , u_IOBUF_LVDCI_DV2_15
--# , u_IOBUF_LVDCI_DV2_18
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_LVTTL
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_IOBUF_SSTL18_I
--# , u_IOBUF_SSTL18_II
--# , u_IOBUF_SSTL18_II_DCI
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDESE2
--# , u_JTAG_SIME2
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_2
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCME2_ADV
--# , u_MMCME2_BASE
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND2B1
--# , u_NAND2B2
--# , u_NAND3
--# , u_NAND3B1
--# , u_NAND3B2
--# , u_NAND3B3
--# , u_NAND4
--# , u_NAND4B1
--# , u_NAND4B2
--# , u_NAND4B3
--# , u_NAND4B4
--# , u_NAND5
--# , u_NAND5B1
--# , u_NAND5B2
--# , u_NAND5B3
--# , u_NAND5B4
--# , u_NAND5B5
--# , u_NOR2
--# , u_NOR2B1
--# , u_NOR2B2
--# , u_NOR3
--# , u_NOR3B1
--# , u_NOR3B2
--# , u_NOR3B3
--# , u_NOR4
--# , u_NOR4B1
--# , u_NOR4B2
--# , u_NOR4B3
--# , u_NOR4B4
--# , u_NOR5
--# , u_NOR5B1
--# , u_NOR5B2
--# , u_NOR5B3
--# , u_NOR5B4
--# , u_NOR5B5
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFDS_BLVDS_25
--# , u_OBUFDS_DUAL_BUF
--# , u_OBUFDS_LVDS_25
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_I_18
--# , u_OBUF_HSTL_I_DCI
--# , u_OBUF_HSTL_I_DCI_18
--# , u_OBUF_HSTL_II
--# , u_OBUF_HSTL_II_18
--# , u_OBUF_HSTL_II_DCI
--# , u_OBUF_HSTL_II_DCI_18
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_III_18
--# , u_OBUF_HSTL_III_DCI
--# , u_OBUF_HSTL_III_DCI_18
--# , u_OBUF_LVCMOS12
--# , u_OBUF_LVCMOS15
--# , u_OBUF_LVCMOS18
--# , u_OBUF_LVCMOS25
--# , u_OBUF_LVCMOS33
--# , u_OBUF_LVDCI_15
--# , u_OBUF_LVDCI_18
--# , u_OBUF_LVDCI_DV2_15
--# , u_OBUF_LVDCI_DV2_18
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_LVTTL
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI66_3
--# , u_OBUF_PCIX66_3
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OBUF_SSTL18_I
--# , u_OBUF_SSTL18_I_DCI
--# , u_OBUF_SSTL18_II
--# , u_OBUF_SSTL18_II_DCI
--# , u_OBUFT
--# , u_OBUFT_DCIEN
--# , u_OBUFTDS
--# , u_OBUFTDS_BLVDS_25
--# , u_OBUFTDS_DCIEN
--# , u_OBUFTDS_DCIEN_DUAL_BUF
--# , u_OBUFTDS_DUAL_BUF
--# , u_OBUFTDS_LVDS_25
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_I_18
--# , u_OBUFT_HSTL_I_DCI
--# , u_OBUFT_HSTL_I_DCI_18
--# , u_OBUFT_HSTL_II
--# , u_OBUFT_HSTL_II_18
--# , u_OBUFT_HSTL_II_DCI
--# , u_OBUFT_HSTL_II_DCI_18
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_III_18
--# , u_OBUFT_HSTL_III_DCI
--# , u_OBUFT_HSTL_III_DCI_18
--# , u_OBUFT_LVCMOS12
--# , u_OBUFT_LVCMOS15
--# , u_OBUFT_LVCMOS18
--# , u_OBUFT_LVCMOS25
--# , u_OBUFT_LVCMOS33
--# , u_OBUFT_LVDCI_15
--# , u_OBUFT_LVDCI_18
--# , u_OBUFT_LVDCI_DV2_15
--# , u_OBUFT_LVDCI_DV2_18
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_LVTTL
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUFT_SSTL18_I
--# , u_OBUFT_SSTL18_I_DCI
--# , u_OBUFT_SSTL18_II
--# , u_OBUFT_SSTL18_II_DCI
--# , u_ODDR
--# , u_ODELAYE2
--# , u_OR2
--# , u_OR2B1
--# , u_OR2B2
--# , u_OR2L
--# , u_OR3
--# , u_OR3B1
--# , u_OR3B2
--# , u_OR3B3
--# , u_OR4
--# , u_OR4B1
--# , u_OR4B2
--# , u_OR4B3
--# , u_OR4B4
--# , u_OR5
--# , u_OR5B1
--# , u_OR5B2
--# , u_OR5B3
--# , u_OR5B4
--# , u_OR5B5
--# , u_OSERDESE2
--# , u_OUT_FIFO
--# , u_PCIE_2_1
--# , u_PHASER_IN
--# , u_PHASER_IN_PHY
--# , u_PHASER_OUT
--# , u_PHASER_OUT_PHY
--# , u_PHASER_REF
--# , u_PHY_CONTROL
--# , u_PLLE2_ADV
--# , u_PLLE2_BASE
--# , u_PSS
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S4_S36
--# , u_RAMB36E1
--# , u_RAMB36E1
--# , u_RAMD32
--# , u_RAMD64E
--# , u_RAMS32
--# , u_RAMS64E
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SIM_CONFIGE2
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUPE2
--# , u_USR_ACCESSE2
--# , u_VCC
--# , u_XADC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XNOR5
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XOR5
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# , u_ZHOLD_DELAY
--# ) );
--# --
--# set_to(y, artix7, (
--# u_AND2
--# , u_AND2B1
--# , u_AND2B1L
--# , u_AND2B2
--# , u_AND3
--# , u_AND3B1
--# , u_AND3B2
--# , u_AND3B3
--# , u_AND4
--# , u_AND4B1
--# , u_AND4B2
--# , u_AND4B3
--# , u_AND4B4
--# , u_AND5
--# , u_AND5B1
--# , u_AND5B2
--# , u_AND5B3
--# , u_AND5B4
--# , u_AND5B5
--# , u_AUTOBUF
--# , u_BSCANE2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFMR
--# , u_BUFMRCE
--# , u_BUFR
--# , u_BUFT
--# , u_CAPTUREE2
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_DCIRESET
--# , u_DNA_PORT
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO18E1
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECCE2
--# , u_GND
--# , u_IBUF
--# , u_IBUF_DCIEN
--# , u_IBUFDS
--# , u_IBUFDS_DCIEN
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DIFF_OUT_DCIEN
--# , u_IBUFDS_GTE2
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_PCIX66_3
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_PCIX66_3
--# , u_ICAPE2
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IDELAYE2
--# , u_IN_FIFO
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS_DIFF_OUT
--# , u_IOBUFDS_DIFF_OUT_DCIEN
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDESE2
--# , u_JTAG_SIME2
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_2
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCME2_ADV
--# , u_MMCME2_BASE
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND2B1
--# , u_NAND2B2
--# , u_NAND3
--# , u_NAND3B1
--# , u_NAND3B2
--# , u_NAND3B3
--# , u_NAND4
--# , u_NAND4B1
--# , u_NAND4B2
--# , u_NAND4B3
--# , u_NAND4B4
--# , u_NAND5
--# , u_NAND5B1
--# , u_NAND5B2
--# , u_NAND5B3
--# , u_NAND5B4
--# , u_NAND5B5
--# , u_NOR2
--# , u_NOR2B1
--# , u_NOR2B2
--# , u_NOR3
--# , u_NOR3B1
--# , u_NOR3B2
--# , u_NOR3B3
--# , u_NOR4
--# , u_NOR4B1
--# , u_NOR4B2
--# , u_NOR4B3
--# , u_NOR4B4
--# , u_NOR5
--# , u_NOR5B1
--# , u_NOR5B2
--# , u_NOR5B3
--# , u_NOR5B4
--# , u_NOR5B5
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFDS_DUAL_BUF
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_PCIX66_3
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OBUFT
--# , u_OBUFT_DCIEN
--# , u_OBUFTDS
--# , u_OBUFTDS_DCIEN
--# , u_OBUFTDS_DCIEN_DUAL_BUF
--# , u_OBUFTDS_DUAL_BUF
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_ODDR
--# , u_ODELAYE2
--# , u_OR2
--# , u_OR2B1
--# , u_OR2B2
--# , u_OR2L
--# , u_OR3
--# , u_OR3B1
--# , u_OR3B2
--# , u_OR3B3
--# , u_OR4
--# , u_OR4B1
--# , u_OR4B2
--# , u_OR4B3
--# , u_OR4B4
--# , u_OR5
--# , u_OR5B1
--# , u_OR5B2
--# , u_OR5B3
--# , u_OR5B4
--# , u_OR5B5
--# , u_OSERDESE2
--# , u_OUT_FIFO
--# , u_PCIE_2_1
--# , u_PHASER_IN
--# , u_PHASER_IN_PHY
--# , u_PHASER_OUT
--# , u_PHASER_OUT_PHY
--# , u_PHASER_REF
--# , u_PHY_CONTROL
--# , u_PLLE2_ADV
--# , u_PLLE2_BASE
--# , u_PSS
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S4_S36
--# , u_RAMB18E1
--# , u_RAMB36E1
--# , u_RAMD32
--# , u_RAMD64E
--# , u_RAMS32
--# , u_RAMS64E
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SIM_CONFIGE2
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUPE2
--# , u_USR_ACCESSE2
--# , u_VCC
--# , u_XADC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XNOR5
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XOR5
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# , u_ZHOLD_DELAY
--# ) );
--# --
--# return pp;
--# end prim_population;
--# ---)
--#
--#constant fam_has_prim : fam_has_prim_type := prim_population;
constant fam_has_prim : fam_has_prim_type :=
(
nofamily => (
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex => (
y, n, y, y, n, n, n, n, n, n, y, n, n, n, n, y, y, y, y, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan2 => (
y, n, y, y, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, y, n, n, n, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan2e => (
y, n, y, y, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, y, n, n, n, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtexe => (
y, n, y, y, n, n, n, n, n, n, y, n, n, n, n, y, y, y, y, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex2 => (
y, n, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex2 => (
y, n, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qrvirtex2 => (
y, n, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex2p => (
y, n, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3 => (
y, n, y, y, n, n, y, n, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan3 => (
y, n, y, y, n, n, y, n, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex4 => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex4lx => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex4fx => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, y, y, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex4sx => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, y, y, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3e => (
y, n, y, y, n, n, y, n, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex5 => (
y, n, y, y, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, y, y, y, n, y, y, y, n, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, y, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, n, y, y, n, y, n, n, n, n, y, y, y, n, n, n, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3a => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3an => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3adsp => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, y, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan3e => (
y, n, y, y, n, n, y, n, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan3a => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan3adsp => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, y, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex4 => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qrvirtex4 => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan6 => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex6 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, n, y, y, y, n, y, y, y, y, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, n, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, y, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, n, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, n, y, n, y, y, n, y, y, y, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan6l => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qspartan6 => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan6 => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex6l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, n, y, y, y, n, y, y, y, y, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, n, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, y, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, n, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, n, y, n, y, y, n, y, y, y, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qspartan6l => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex5 => (
y, n, y, y, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, y, y, y, n, y, y, y, n, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, y, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, n, y, y, n, y, n, n, n, n, y, y, y, n, n, n, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex6 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, n, y, y, y, n, y, y, y, y, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, n, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, y, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, n, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, n, y, n, y, y, n, y, y, y, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qrvirtex5 => (
y, n, y, y, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, y, y, y, n, y, y, y, n, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, y, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, n, y, y, n, y, n, n, n, n, y, y, y, n, n, n, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex5tx => (
y, n, y, y, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, y, y, y, n, y, y, y, n, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, y, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, n, y, y, n, y, n, n, n, n, y, y, y, n, n, n, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex5fx => (
y, n, y, y, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, y, y, y, n, y, y, y, n, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, y, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, n, y, y, n, y, n, n, n, n, y, y, y, n, n, n, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
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virtex6cx => (
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n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
kintex7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
kintex7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
qkintex7 => (
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y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
qkintex7l => (
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artix7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
aartix7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
artix7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
qartix7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
zynq => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
azynq => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
qzynq => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y)
);
function supported( family : families_type;
primitive : primitives_type
) return boolean is
begin
return fam_has_prim(family)(primitive) = y;
end supported;
function supported( family : families_type;
primitives : primitive_array_type
) return boolean is
begin
for i in primitives'range loop
if fam_has_prim(family)(primitives(i)) /= y then
return false;
end if;
end loop;
return true;
end supported;
----------------------------------------------------------------------------
-- This function is used as alternative to the 'IMAGE attribute, which
-- is not correctly interpretted by some vhdl tools.
----------------------------------------------------------------------------
function myimage (fam_type : families_type) return string is
variable temp : families_type :=fam_type;
begin
case temp is
when nofamily => return "nofamily" ;
when virtex => return "virtex" ;
when spartan2 => return "spartan2" ;
when spartan2e => return "spartan2e" ;
when virtexe => return "virtexe" ;
when virtex2 => return "virtex2" ;
when qvirtex2 => return "qvirtex2" ;
when qrvirtex2 => return "qrvirtex2" ;
when virtex2p => return "virtex2p" ;
when spartan3 => return "spartan3" ;
when aspartan3 => return "aspartan3" ;
when spartan3e => return "spartan3e" ;
when virtex4 => return "virtex4" ;
when virtex4lx => return "virtex4lx" ;
when virtex4fx => return "virtex4fx" ;
when virtex4sx => return "virtex4sx" ;
when virtex5 => return "virtex5" ;
when spartan3a => return "spartan3a" ;
when spartan3an => return "spartan3an" ;
when spartan3adsp => return "spartan3adsp" ;
when aspartan3e => return "aspartan3e" ;
when aspartan3a => return "aspartan3a" ;
when aspartan3adsp => return "aspartan3adsp";
when qvirtex4 => return "qvirtex4" ;
when qrvirtex4 => return "qrvirtex4" ;
when spartan6 => return "spartan6" ;
when virtex6 => return "virtex6" ;
when spartan6l => return "spartan6l" ;
when qspartan6 => return "qspartan6" ;
when aspartan6 => return "aspartan6" ;
when virtex6l => return "virtex6l" ;
when qspartan6l => return "qspartan6l" ;
when qvirtex5 => return "qvirtex5" ;
when qvirtex6 => return "qvirtex6" ;
when qrvirtex5 => return "qrvirtex5" ;
when virtex5tx => return "virtex5tx" ;
when virtex5fx => return "virtex5fx" ;
when virtex6cx => return "virtex6cx" ;
when virtex7 => return "virtex7" ;
when virtex7l => return "virtex7l" ;
when qvirtex7 => return "qvirtex7" ;
when qvirtex7l => return "qvirtex7l" ;
when kintex7 => return "kintex7" ;
when kintex7l => return "kintex7l" ;
when qkintex7 => return "qkintex7" ;
when qkintex7l => return "qkintex7l" ;
when artix7 => return "artix7" ;
when aartix7 => return "aartix7" ;
when artix7l => return "artix7l" ;
when qartix7 => return "qartix7" ;
when zynq => return "zynq" ;
when azynq => return "azynq" ;
when qzynq => return "qzynq" ;
end case;
end myimage;
----------------------------------------------------------------------------
-- Function: get_root_family
--
-- This function takes in the string for the desired FPGA family type and
-- returns the root FPGA family type string. This is used for derivative part
-- aliasing to the root family. This is primarily for fifo_generator and
-- blk_mem_gen calls that need the root family passed to the call.
----------------------------------------------------------------------------
function get_root_family(family_in : string) return string is
begin
-- spartan3 Root family
if (equalIgnoringCase(family_in, "spartan3" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "spartan3a" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "spartan3an" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "spartan3adsp" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "aspartan3" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "aspartan3a" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "aspartan3adsp" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "spartan3e" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "aspartan3e" )) Then return "spartan3" ;
-- virtex4 Root family
Elsif (equalIgnoringCase(family_in, "virtex4" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "virtex4lx" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "virtex4fx" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "virtex4sx" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "qvirtex4" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "qrvirtex4" )) Then return "virtex4" ;
-- virtex5 Root family
Elsif (equalIgnoringCase(family_in, "virtex5" )) Then return "virtex5" ;
Elsif (equalIgnoringCase(family_in, "qvirtex5" )) Then return "virtex5" ;
Elsif (equalIgnoringCase(family_in, "qrvirtex5" )) Then return "virtex5" ;
Elsif (equalIgnoringCase(family_in, "virtex5tx" )) Then return "virtex5" ;
Elsif (equalIgnoringCase(family_in, "virtex5fx" )) Then return "virtex5" ;
-- virtex6 Root family
Elsif (equalIgnoringCase(family_in, "virtex6" )) Then return "virtex6" ;
Elsif (equalIgnoringCase(family_in, "virtex6l" )) Then return "virtex6" ;
Elsif (equalIgnoringCase(family_in, "qvirtex6" )) Then return "virtex6" ;
Elsif (equalIgnoringCase(family_in, "virtex6cx" )) Then return "virtex6" ;
-- spartan6 Root family
Elsif (equalIgnoringCase(family_in, "spartan6" )) Then return "spartan6" ;
Elsif (equalIgnoringCase(family_in, "spartan6l" )) Then return "spartan6" ;
Elsif (equalIgnoringCase(family_in, "qspartan6" )) Then return "spartan6" ;
Elsif (equalIgnoringCase(family_in, "aspartan6" )) Then return "spartan6" ;
Elsif (equalIgnoringCase(family_in, "qspartan6l" )) Then return "spartan6" ;
-- Virtex7 Root family
Elsif (equalIgnoringCase(family_in, "virtex7" )) Then return "virtex7" ;
Elsif (equalIgnoringCase(family_in, "virtex7l" )) Then return "virtex7" ;
Elsif (equalIgnoringCase(family_in, "qvirtex7" )) Then return "virtex7" ;
Elsif (equalIgnoringCase(family_in, "qvirtex7l" )) Then return "virtex7" ;
-- Kintex7 Root family
Elsif (equalIgnoringCase(family_in, "kintex7" )) Then return "kintex7" ;
Elsif (equalIgnoringCase(family_in, "kintex7l" )) Then return "kintex7" ;
Elsif (equalIgnoringCase(family_in, "qkintex7" )) Then return "kintex7" ;
Elsif (equalIgnoringCase(family_in, "qkintex7l" )) Then return "kintex7" ;
-- artix7 Root family
Elsif (equalIgnoringCase(family_in, "artix7" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "aartix7" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "artix7l" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "qartix7" )) Then return "artix7" ;
-- zynq Root family
Elsif (equalIgnoringCase(family_in, "zynq" )) Then return "zynq" ;
Elsif (equalIgnoringCase(family_in, "azynq" )) Then return "zynq" ;
Elsif (equalIgnoringCase(family_in, "qzynq" )) Then return "zynq" ;
-- No Match to supported families and derivatives
Else return "nofamily";
End if;
end get_root_family;
function toLowerCaseChar( char : character ) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' OR char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a';
when 'B' => return 'b';
when 'C' => return 'c';
when 'D' => return 'd';
when 'E' => return 'e';
when 'F' => return 'f';
when 'G' => return 'g';
when 'H' => return 'h';
when 'I' => return 'i';
when 'J' => return 'j';
when 'K' => return 'k';
when 'L' => return 'l';
when 'M' => return 'm';
when 'N' => return 'n';
when 'O' => return 'o';
when 'P' => return 'p';
when 'Q' => return 'q';
when 'R' => return 'r';
when 'S' => return 's';
when 'T' => return 't';
when 'U' => return 'u';
when 'V' => return 'v';
when 'W' => return 'w';
when 'X' => return 'x';
when 'Y' => return 'y';
when 'Z' => return 'z';
when others => return char;
end case;
end toLowerCaseChar;
----------------------------------------------------------------------------
-- Function: equalIgnoringCase
--
-- Compare one string against another for equality with case insensitivity.
-- Can be used to test see if a family, C_FAMILY, is equal to some
-- family. However such usage is discouraged. Use instead availability
-- primitive guards based on the function, 'supported', wherever possible.
----------------------------------------------------------------------------
function equalIgnoringCase( str1, str2 : string ) return boolean is
constant LEN1 : integer := str1'length;
constant LEN2 : integer := str2'length;
variable equal : boolean := TRUE;
begin
if not (LEN1 = LEN2) then
equal := FALSE;
else
for i in str1'range loop
if not (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) then
equal := FALSE;
end if;
end loop;
end if;
return equal;
end equalIgnoringCase;
----------------------------------------------------------------------------
-- Conversions from/to STRING to/from families_type.
-- These are convenience functions that are not normally needed when
-- using the 'supported' functions.
----------------------------------------------------------------------------
function str2fam( fam_as_string : string ) return families_type is
--
variable fas : string(1 to fam_as_string'length) := fam_as_string;
variable fam : families_type;
--
begin
-- Search for and return the corresponding family.
for fam in families_type'low to families_type'high loop
if equalIgnoringCase(fas, myimage(fam)) then return fam; end if;
end loop;
-- If there is no matching family, report a warning and return nofamily.
assert false
report "Package system_xadc_wiz_0_0_family_support: Function str2fam called" &
" with string parameter, " & fam_as_string &
", that does not correspond" &
" to a supported family. Returning nofamily."
severity warning;
return nofamily;
end str2fam;
function fam2str( fam : families_type) return string is
begin
--return families_type'IMAGE(fam);
return myimage(fam);
end fam2str;
function supported( fam_as_str : string;
primitive : primitives_type
) return boolean is
begin
return supported(str2fam(fam_as_str), primitive);
end supported;
function supported( fam_as_str : string;
primitives : primitive_array_type
) return boolean is
begin
return supported(str2fam(fam_as_str), primitives);
end supported;
----------------------------------------------------------------------------
-- Function: native_lut_size, two overloads.
----------------------------------------------------------------------------
function native_lut_size( fam : families_type;
no_lut_return_val : natural := 0
) return natural is
begin
if supported(fam, u_LUT6) then return 6;
elsif supported(fam, u_LUT5) then return 5;
elsif supported(fam, u_LUT4) then return 4;
elsif supported(fam, u_LUT3) then return 3;
elsif supported(fam, u_LUT2) then return 2;
elsif supported(fam, u_LUT1) then return 1;
else return no_lut_return_val;
end if;
end;
function native_lut_size( fam_as_string : string;
no_lut_return_val : natural := 0
) return natural is
begin
return native_lut_size( fam => str2fam(fam_as_string),
no_lut_return_val => no_lut_return_val
);
end;
end package body system_xadc_wiz_0_0_family_support;
|
apache-2.0
|
c66c2f971a70f6488a61ec93b4d9543f
| 0.322725 | 2.593293 | false | false | false | false |
jeffmagina/ECE368
|
Lab1/CounterTest/counter.vhd
| 1 | 1,344 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2014
-- Module Name: counter
-- Project Name: CLOCK COUNTER
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Counter
-- Will increase the counter(output) ever time
-- the clock does a rising action
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
Port ( CLK : in STD_LOGIC;
DIRECTION : in STD_LOGIC;
RST : in STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (7 downto 0));
end counter;
architecture Behavioral of counter is
signal count : std_logic_vector(0 to 7) := "00000000";
begin
process (CLK, RST)
begin
if (RST = '1') then
count <= "00000000";
elsif (CLK'event and CLK = '1') then
if DIRECTION = '1' then
count <= count + 1;
else
count <= count - 1;
end if;
end if;
end process;
COUNT_OUT <= count;
end Behavioral;
|
mit
|
ad2bd7665eb408cb48dcae9fd21e21aa
| 0.523065 | 4.392157 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_gpio_1_0/sim/system_axi_gpio_1_0.vhd
| 1 | 9,295 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_13;
USE axi_gpio_v2_0_13.axi_gpio;
ENTITY system_axi_gpio_1_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END system_axi_gpio_1_0;
ARCHITECTURE system_axi_gpio_1_0_arch OF system_axi_gpio_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_gpio_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 16,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 1,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
ip2intc_irpt => ip2intc_irpt,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END system_axi_gpio_1_0_arch;
|
apache-2.0
|
32e490e4df02b3da5577720eeadf0b58
| 0.680581 | 3.225191 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_quad_spi_shield_0/synth/system_axi_quad_spi_shield_0.vhd
| 1 | 16,977 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_quad_spi:3.2
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_quad_spi_v3_2_10;
USE axi_quad_spi_v3_2_10.axi_quad_spi;
ENTITY system_axi_quad_spi_shield_0 IS
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END system_axi_quad_spi_shield_0;
ARCHITECTURE system_axi_quad_spi_shield_0_arch OF system_axi_quad_spi_shield_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_quad_spi_shield_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_quad_spi IS
GENERIC (
Async_Clk : INTEGER;
C_FAMILY : STRING;
C_SELECT_XPM : INTEGER;
C_SUB_FAMILY : STRING;
C_INSTANCE : STRING;
C_SPI_MEM_ADDR_BITS : INTEGER;
C_TYPE_OF_AXI4_INTERFACE : INTEGER;
C_XIP_MODE : INTEGER;
C_UC_FAMILY : INTEGER;
C_FIFO_DEPTH : INTEGER;
C_SCK_RATIO : INTEGER;
C_DUAL_QUAD_MODE : INTEGER;
C_NUM_SS_BITS : INTEGER;
C_NUM_TRANSFER_BITS : INTEGER;
C_SPI_MODE : INTEGER;
C_USE_STARTUP : INTEGER;
C_USE_STARTUP_EXT : INTEGER;
C_SPI_MEMORY : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI4_ADDR_WIDTH : INTEGER;
C_S_AXI4_DATA_WIDTH : INTEGER;
C_S_AXI4_ID_WIDTH : INTEGER;
C_SHARED_STARTUP : INTEGER;
C_S_AXI4_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI4_HIGHADDR : STD_LOGIC_VECTOR;
C_LSB_STUP : INTEGER
);
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi4_aclk : IN STD_LOGIC;
s_axi4_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi4_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_awaddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_awlock : IN STD_LOGIC;
s_axi4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awvalid : IN STD_LOGIC;
s_axi4_awready : OUT STD_LOGIC;
s_axi4_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_wlast : IN STD_LOGIC;
s_axi4_wvalid : IN STD_LOGIC;
s_axi4_wready : OUT STD_LOGIC;
s_axi4_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_bvalid : OUT STD_LOGIC;
s_axi4_bready : IN STD_LOGIC;
s_axi4_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_araddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_arlock : IN STD_LOGIC;
s_axi4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arvalid : IN STD_LOGIC;
s_axi4_arready : OUT STD_LOGIC;
s_axi4_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_rlast : OUT STD_LOGIC;
s_axi4_rvalid : OUT STD_LOGIC;
s_axi4_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
io2_i : IN STD_LOGIC;
io2_o : OUT STD_LOGIC;
io2_t : OUT STD_LOGIC;
io3_i : IN STD_LOGIC;
io3_o : OUT STD_LOGIC;
io3_t : OUT STD_LOGIC;
io0_1_i : IN STD_LOGIC;
io0_1_o : OUT STD_LOGIC;
io0_1_t : OUT STD_LOGIC;
io1_1_i : IN STD_LOGIC;
io1_1_o : OUT STD_LOGIC;
io1_1_t : OUT STD_LOGIC;
io2_1_i : IN STD_LOGIC;
io2_1_o : OUT STD_LOGIC;
io2_1_t : OUT STD_LOGIC;
io3_1_i : IN STD_LOGIC;
io3_1_o : OUT STD_LOGIC;
io3_1_t : OUT STD_LOGIC;
spisel : IN STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
ss_1_i : IN STD_LOGIC;
ss_1_o : OUT STD_LOGIC;
ss_1_t : OUT STD_LOGIC;
cfgclk : OUT STD_LOGIC;
cfgmclk : OUT STD_LOGIC;
eos : OUT STD_LOGIC;
preq : OUT STD_LOGIC;
clk : IN STD_LOGIC;
gsr : IN STD_LOGIC;
gts : IN STD_LOGIC;
keyclearb : IN STD_LOGIC;
usrcclkts : IN STD_LOGIC;
usrdoneo : IN STD_LOGIC;
usrdonets : IN STD_LOGIC;
pack : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END COMPONENT axi_quad_spi;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_axi_quad_spi_shield_0_arch: ARCHITECTURE IS "axi_quad_spi,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_axi_quad_spi_shield_0_arch : ARCHITECTURE IS "system_axi_quad_spi_shield_0,axi_quad_spi,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_axi_quad_spi_shield_0_arch: ARCHITECTURE IS "system_axi_quad_spi_shield_0,axi_quad_spi,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_quad_spi,x_ipVersion=3.2,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,Async_Clk=0,C_FAMILY=artix7,C_SELECT_XPM=0,C_SUB_FAMILY=artix7,C_INSTANCE=axi_quad_spi_inst,C_SPI_MEM_ADDR_BITS=24,C_TYPE_OF_AXI4_INTERFACE=0,C_XIP_MODE=0,C_UC_FAMILY=0,C_FIFO_DEPTH=16,C_SCK_RATIO=16,C_DUAL_QUAD_MODE=0,C_NUM_SS_BITS=1,C_NUM_TRANSFER_BITS=8,C_SPI_MODE=0,C_USE_STARTUP=0,C_USE_STAR" &
"TUP_EXT=0,C_SPI_MEMORY=1,C_S_AXI_ADDR_WIDTH=7,C_S_AXI_DATA_WIDTH=32,C_S_AXI4_ADDR_WIDTH=24,C_S_AXI4_DATA_WIDTH=32,C_S_AXI4_ID_WIDTH=1,C_SHARED_STARTUP=0,C_S_AXI4_BASEADDR=0xFFFFFFFF,C_S_AXI4_HIGHADDR=0x00000000,C_LSB_STUP=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ext_spi_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 spi_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 lite_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 lite_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF io0_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_I";
ATTRIBUTE X_INTERFACE_INFO OF io0_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_O";
ATTRIBUTE X_INTERFACE_INFO OF io0_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_T";
ATTRIBUTE X_INTERFACE_INFO OF io1_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_I";
ATTRIBUTE X_INTERFACE_INFO OF io1_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_O";
ATTRIBUTE X_INTERFACE_INFO OF io1_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_T";
ATTRIBUTE X_INTERFACE_INFO OF sck_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_I";
ATTRIBUTE X_INTERFACE_INFO OF sck_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_O";
ATTRIBUTE X_INTERFACE_INFO OF sck_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_T";
ATTRIBUTE X_INTERFACE_INFO OF ss_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_I";
ATTRIBUTE X_INTERFACE_INFO OF ss_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_O";
ATTRIBUTE X_INTERFACE_INFO OF ss_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_T";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
BEGIN
U0 : axi_quad_spi
GENERIC MAP (
Async_Clk => 0,
C_FAMILY => "artix7",
C_SELECT_XPM => 0,
C_SUB_FAMILY => "artix7",
C_INSTANCE => "axi_quad_spi_inst",
C_SPI_MEM_ADDR_BITS => 24,
C_TYPE_OF_AXI4_INTERFACE => 0,
C_XIP_MODE => 0,
C_UC_FAMILY => 0,
C_FIFO_DEPTH => 16,
C_SCK_RATIO => 16,
C_DUAL_QUAD_MODE => 0,
C_NUM_SS_BITS => 1,
C_NUM_TRANSFER_BITS => 8,
C_SPI_MODE => 0,
C_USE_STARTUP => 0,
C_USE_STARTUP_EXT => 0,
C_SPI_MEMORY => 1,
C_S_AXI_ADDR_WIDTH => 7,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI4_ADDR_WIDTH => 24,
C_S_AXI4_DATA_WIDTH => 32,
C_S_AXI4_ID_WIDTH => 1,
C_SHARED_STARTUP => 0,
C_S_AXI4_BASEADDR => X"FFFFFFFF",
C_S_AXI4_HIGHADDR => X"00000000",
C_LSB_STUP => 0
)
PORT MAP (
ext_spi_clk => ext_spi_clk,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi4_aclk => '0',
s_axi4_aresetn => '0',
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi4_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_awlock => '0',
s_axi4_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awvalid => '0',
s_axi4_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi4_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_wlast => '0',
s_axi4_wvalid => '0',
s_axi4_bready => '0',
s_axi4_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_arlock => '0',
s_axi4_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arvalid => '0',
s_axi4_rready => '0',
io0_i => io0_i,
io0_o => io0_o,
io0_t => io0_t,
io1_i => io1_i,
io1_o => io1_o,
io1_t => io1_t,
io2_i => '0',
io3_i => '0',
io0_1_i => '0',
io1_1_i => '0',
io2_1_i => '0',
io3_1_i => '0',
spisel => '1',
sck_i => sck_i,
sck_o => sck_o,
sck_t => sck_t,
ss_i => ss_i,
ss_o => ss_o,
ss_t => ss_t,
ss_1_i => '0',
clk => '0',
gsr => '0',
gts => '0',
keyclearb => '0',
usrcclkts => '0',
usrdoneo => '1',
usrdonets => '0',
pack => '0',
ip2intc_irpt => ip2intc_irpt
);
END system_axi_quad_spi_shield_0_arch;
|
apache-2.0
|
6e3992ea2175cb78550d224bb7529143
| 0.644166 | 2.961793 | false | false | false | false |
xcthulhu/lambda-geda
|
top_mod.vhdl
| 1 | 5,690 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use work.common_decs.all;
use work.clocksim_decs.all;
library unisim;
use unisim.Vcomponents.all;
entity top_mod is
port
(
-- External Clock
clk : in std_logic;
-- Interupt
irq : out std_logic;
-- Armadeus handshaking
imx_data : inout imx_chan;
imx_address : in std_logic_vector(11 downto 0); -- LSB not used
imx_cs_n : in std_logic;
imx_oe_n : in std_logic;
imx_eb3_n : in std_logic;
-- External pins
---- Inputs
a_in, a_inb,
b_in, b_inb : in std_logic;
SCLK_in, SCLK_inb : in std_logic;
STROBE_in, STROBE_inb : in std_logic;
---- Outputs
a_out, a_outb,
b_out, b_outb : out std_logic;
SCLK_out, SCLK_outb : out std_logic;
STROBE_out, STROBE_outb : out std_logic
);
end entity;
architecture RTL of top_mod is
-- Components
component rstgen_syscon
generic (invert_reset : std_logic := '0');
port (
clk : in std_logic;
sysc : out syscon
);
end component;
component wishbone_wrapper
port (
sysc : in syscon;
imx_data : inout imx_chan;
imx : in imx_in;
wbr : in wbrs;
wbw : out wbws
);
end component;
component irq_mngr
generic(
id : device_id := x"1009";
irq_level : std_logic := '1'
);
port (
sysc : in syscon;
wbw : in wbws;
wbr : out wbrs;
irqport : in write_chan;
irq : out std_logic
);
end component;
component intercon
port (
sysc : in syscon;
irq_wbr, fifo_wbr : in wbrs;
irq_wbw, fifo_wbw : out wbws;
irq_sysc, fifo_sysc,
wsysc : out syscon;
wwbr : out wbrs;
wwbw : in wbws
);
end component;
component wb_fifo_chain is
generic (id : device_id := x"0523";
addrdepth : integer := 9
);
port
(
sysc : in syscon;
a_in, b_in,
SCLK, STROBE : in std_logic;
irqport : out write_chan;
wbw : in wbws;
wbr : out wbrs
);
end component;
component clocksim is
generic (div : natural := 100);
port (sysc : in syscon;
SCLK, STROBE, A, B : out std_logic);
end component;
-- External Pins
signal xa_in, xb_in, xSCLK_in, xSTROBE_in : std_logic;
signal xa_out, xb_out, xSCLK_out, xSTROBE_out : std_logic;
-- IRQ communication
signal irqport : write_chan;
---- Intercon
signal sysc, irq_sysc, fifo_sysc, wsysc : syscon;
signal wwbr, irq_wbr, fifo_wbr : wbrs;
signal wwbw, irq_wbw, fifo_wbw : wbws;
signal imx : imx_in;
begin
imx.address <= imx_address;
imx.cs_n <= imx_cs_n;
imx.oe_n <= imx_oe_n;
imx.eb3_n <= imx_eb3_n;
IO_L01X_0 : IBUFDS
port map ( I => a_in,
IB => a_inb,
O => xa_in);
IO_L03X_0 : IBUFDS
port map ( I => b_in,
IB => b_inb,
O => xb_in);
IO_L07X_0 : IBUFDS
port map ( I => SCLK_in,
IB => SCLK_inb,
O => xSCLK_in);
IO_L15X_0 : IBUFDS
port map ( I => STROBE_in,
IB => STROBE_inb,
O => xSTROBE_in);
rstgen00 : rstgen_syscon
generic map (invert_reset => '0')
port map ( clk => clk,
sysc => sysc);
intercon00 : intercon
port map ( sysc => sysc,
irq_wbr => irq_wbr,
irq_wbw => irq_wbw,
irq_sysc => irq_sysc,
fifo_wbr => fifo_wbr,
fifo_wbw => fifo_wbw,
fifo_sysc => fifo_sysc,
wwbr => wwbr,
wwbw => wwbw,
wsysc => wsysc);
wrapper : wishbone_wrapper
port map ( sysc => wsysc,
imx_data => imx_data,
imx => imx,
wbw => wwbw,
wbr => wwbr);
irq_mngr00 : irq_mngr
generic map ( id => x"1009",
irq_level => '1')
port map ( sysc => irq_sysc,
wbr => irq_wbr,
wbw => irq_wbw,
irqport => irqport,
irq => irq);
wb_fifo_chain00 : wb_fifo_chain
generic map (
id => x"0523",
addrdepth => 9
)
port map (
sysc => fifo_sysc,
a_in => xa_in,
b_in => xb_in,
STROBE => xSTROBE_in,
SCLK => xSCLK_in,
irqport => irqport,
wbw => fifo_wbw,
wbr => fifo_wbr
);
-- Output System
SCLK_LVDS_OUT : OBUFDS
port map (I => xSCLK_out,
O => SCLK_out,
OB => SCLK_outb);
STROBE_LVDS_OUT : OBUFDS
port map (I => xSTROBE_out,
O => STROBE_out,
OB => STROBE_outb);
A_LVDS_OUT : OBUFDS
port map (I => xa_out,
O => a_out,
OB => a_outb);
B_LVDS_OUT : OBUFDS
port map (I => xb_out,
O => b_out,
OB => b_outb);
CLOCKSIMULATOR : clocksim
generic map (div => 100000000)
port map (sysc => sysc,
SCLK => xSCLK_out,
STROBE => xSTROBE_out,
A => xa_out,
B => xb_out);
end architecture;
|
gpl-3.0
|
8146434be77ee3df7c3c10a95d4f0633
| 0.449736 | 3.538557 | false | false | false | false |
daniw/add
|
rot_enc/tb_mcu.vhd
| 1 | 1,285 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity tb_mcu is
end tb_mcu;
architecture TB of tb_mcu is
signal rst : std_logic;
signal clk : std_logic := '0';
signal Switch : std_logic_vector(3 downto 0);
signal LED : std_logic_vector(7 downto 0);
signal ROT_A : std_logic;
signal ROT_B : std_logic;
signal ROT_CENTER : std_logic;
begin
-- instantiate MUT
MUT : entity work.mcu
port map(
rst => rst,
clk => clk,
LED => LED,
Switch => Switch,
ROT_A => ROT_A,
ROT_B => ROT_B,
ROT_CENTER => ROT_CENTER
);
-- generate reset
rst <= '1', '0' after 5us;
-- clock generation
p_clk: process
begin
wait for 1 sec / CF/2;
clk <= not clk;
end process;
-- encoder signal generation
p_encoder: process
begin
ROT_A <= '0';
ROT_B <= '0';
wait for 1 sec / CF/2 * 5;
ROT_A <= '0';
ROT_B <= '1';
wait for 1 sec / CF/2 * 5;
ROT_A <= '1';
ROT_B <= '1';
wait for 1 sec / CF/2 * 5;
ROT_A <= '1';
ROT_B <= '0';
wait for 1 sec / CF/2 * 5;
end process;
end TB;
|
gpl-2.0
|
add00d7c1e75d84a403dbba915749973
| 0.48716 | 3.196517 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 3/DataMemory_tb.vhd
| 1 | 1,772 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY DataMemory_tb IS
END DataMemory_tb;
ARCHITECTURE behavior OF DataMemory_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT DataMemory
PORT(
Crd : IN std_logic_vector(31 downto 0);
Address : IN std_logic_vector(31 downto 0);
WRENMEM : IN std_logic;
DATATOMEM : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Crd : std_logic_vector(31 downto 0) := (others => '0');
signal Address : std_logic_vector(31 downto 0) := (others => '0');
signal WRENMEM : std_logic := '0';
--Outputs
signal DATATOMEM : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: DataMemory PORT MAP (
Crd => Crd,
Address => Address,
WRENMEM => WRENMEM,
DATATOMEM => DATATOMEM
);
-- Stimulus process
stim_proc: process
begin
Crd<="00000000000000000000001000001011";
Address<="00000000000000000000000000001110";
wait for 20 ns;
Crd<="00000000000000000000001000101011";
Address<="00000000000000000000000000001111";
WRENMEM<='1';
wait for 20 ns;
Crd<="00000000000000000000000000001011";
Address<="00000000000000000000000000001111";
WRENMEM<='0';
wait for 20 ns;
Crd<="00000000000000000001001000001011";
Address<="00000000000000000000000000001111";
WRENMEM<='1';
wait for 20 ns;
Crd<="00000000000000000000000000001011";
Address<="00000000000000000000000000010000";
wait for 20 ns;
Crd<="00000000000000000000000000000011";
Address<="00000000000000000000000000010000";
WRENMEM<='0';
wait;
end process;
END;
|
mit
|
6bc4fe19ee3c8aa84a2e722df7e993d5
| 0.642212 | 4.486076 | false | false | false | false |
kaott/16-bit-risc
|
vhdl/control.vhd
| 4 | 3,052 |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity control is
port( op : in std_logic_vector(3 downto 0);
funct : in std_logic_vector(2 downto 0);
RegDst, Jump, Branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite : out std_logic;
ALUOp : out std_logic_vector(2 downto 0)
);
end control;
architecture logic of control is
begin
process(op, funct)
begin
if op = "0000" then
RegDst <= '1';
case funct is
when "010" => Jump <= '0';
Branch <= '0';
MemRead <= '0';
MemtoReg <= '1';
ALUOp <= "010"; --add
MemWrite <= '0';
ALUSrc <= '0';
RegWrite <= '1';
when "110" => Jump <= '0';
Branch <= '0';
MemRead <= '0';
MemtoReg <= '1';
ALUOp <= "110"; --sub
MemWrite <= '0';
ALUSrc <= '0';
RegWrite <= '1';
when "000" => Jump <= '0';
Branch <= '0';
MemRead <= '0';
MemtoReg <= '1';
ALUOp <= "000"; --and
MemWrite <= '0';
ALUSrc <= '0';
RegWrite <= '1';
when "001" => Jump <= '0';
Branch <= '0';
MemRead <= '0';
MemtoReg <= '1';
ALUOp <= "001"; --or
MemWrite <= '0';
ALUSrc <= '0';
RegWrite <= '1';
when "111" => Jump <= '0';
Branch <= '0';
MemRead <= '0';
MemtoReg <= '1';
ALUOp <= "111"; --slt
MemWrite <= '0';
ALUSrc <= '0';
RegWrite <= '1';
when others => RegDst <= 'X';
Jump <= 'X';
Branch <= 'X';
MemRead <= 'X';
MemtoReg <= 'X';
ALUOp <= "XXX"; --others
MemWrite <= 'X';
ALUSrc <= 'X';
RegWrite <= 'X';
end case;
else
case op is
when "1011" => RegDst <= '1';
Jump <= '0';
Branch <= '0';
MemRead <= '1';
MemtoReg <= '0';
ALUOp <= "010"; --lw
MemWrite <= '0';
ALUSrc <= '1';
RegWrite <= '1';
when "1111" => RegDst <= '0';
Jump <= '0';
Branch <= '0';
MemRead <= '0';
MemtoReg <= '0';
ALUOp <= "010"; --sw
MemWrite <= '1';
ALUSrc <= '1';
RegWrite <= '0';
when "0100" => RegDst <= '0';
Jump <= '0';
Branch <= '1';
MemRead <= '0';
MemtoReg <= '0';
ALUOp <= "110"; --beq
MemWrite <= '0';
ALUSrc <= '0';
RegWrite <= '0';
when "0010" => RegDst <= '0';
Jump <= '1';
Branch <= '0';
MemRead <= '0';
MemtoReg <= '0';
ALUOp <= "000"; --j
MemWrite <= '0';
ALUSrc <= '0';
RegWrite <= '0';
when others => RegDst <= 'X';
Jump <= 'X';
Branch <= 'X';
MemRead <= 'X';
MemtoReg <= 'X';
ALUOp <= "XXX"; --others
MemWrite <= 'X';
ALUSrc <= 'X';
RegWrite <= 'X';
end case;
end if;
end process;
end logic;
|
mit
|
19aee035afc2ea6c1063a02f9a31c344
| 0.393185 | 3.260684 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_dlmb_bram_if_cntlr_0/system_dlmb_bram_if_cntlr_0_sim_netlist.vhdl
| 1 | 25,599 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:42:41 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_dlmb_bram_if_cntlr_0/system_dlmb_bram_if_cntlr_0_sim_netlist.vhdl
-- Design : system_dlmb_bram_if_cntlr_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr is
port (
LMB_Clk : in STD_LOGIC;
LMB_Rst : in STD_LOGIC;
LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_AddrStrobe : in STD_LOGIC;
LMB_ReadStrobe : in STD_LOGIC;
LMB_WriteStrobe : in STD_LOGIC;
LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : out STD_LOGIC;
Sl_Wait : out STD_LOGIC;
Sl_UE : out STD_LOGIC;
Sl_CE : out STD_LOGIC;
LMB1_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB1_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB1_AddrStrobe : in STD_LOGIC;
LMB1_ReadStrobe : in STD_LOGIC;
LMB1_WriteStrobe : in STD_LOGIC;
LMB1_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl1_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl1_Ready : out STD_LOGIC;
Sl1_Wait : out STD_LOGIC;
Sl1_UE : out STD_LOGIC;
Sl1_CE : out STD_LOGIC;
LMB2_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB2_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB2_AddrStrobe : in STD_LOGIC;
LMB2_ReadStrobe : in STD_LOGIC;
LMB2_WriteStrobe : in STD_LOGIC;
LMB2_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl2_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl2_Ready : out STD_LOGIC;
Sl2_Wait : out STD_LOGIC;
Sl2_UE : out STD_LOGIC;
Sl2_CE : out STD_LOGIC;
LMB3_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB3_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB3_AddrStrobe : in STD_LOGIC;
LMB3_ReadStrobe : in STD_LOGIC;
LMB3_WriteStrobe : in STD_LOGIC;
LMB3_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl3_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl3_Ready : out STD_LOGIC;
Sl3_Wait : out STD_LOGIC;
Sl3_UE : out STD_LOGIC;
Sl3_CE : out STD_LOGIC;
BRAM_Rst_A : out STD_LOGIC;
BRAM_Clk_A : out STD_LOGIC;
BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_EN_A : out STD_LOGIC;
BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 );
S_AXI_CTRL_ACLK : in STD_LOGIC;
S_AXI_CTRL_ARESETN : in STD_LOGIC;
S_AXI_CTRL_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_CTRL_AWVALID : in STD_LOGIC;
S_AXI_CTRL_AWREADY : out STD_LOGIC;
S_AXI_CTRL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_CTRL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_CTRL_WVALID : in STD_LOGIC;
S_AXI_CTRL_WREADY : out STD_LOGIC;
S_AXI_CTRL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_CTRL_BVALID : out STD_LOGIC;
S_AXI_CTRL_BREADY : in STD_LOGIC;
S_AXI_CTRL_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_CTRL_ARVALID : in STD_LOGIC;
S_AXI_CTRL_ARREADY : out STD_LOGIC;
S_AXI_CTRL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_CTRL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_CTRL_RVALID : out STD_LOGIC;
S_AXI_CTRL_RREADY : in STD_LOGIC;
UE : out STD_LOGIC;
CE : out STD_LOGIC;
Interrupt : out STD_LOGIC
);
attribute C_BASEADDR : string;
attribute C_BASEADDR of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute C_BRAM_AWIDTH : integer;
attribute C_BRAM_AWIDTH of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 32;
attribute C_CE_COUNTER_WIDTH : integer;
attribute C_CE_COUNTER_WIDTH of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
attribute C_CE_FAILING_REGISTERS : integer;
attribute C_CE_FAILING_REGISTERS of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
attribute C_ECC : integer;
attribute C_ECC of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
attribute C_ECC_ONOFF_REGISTER : integer;
attribute C_ECC_ONOFF_REGISTER of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 1;
attribute C_ECC_STATUS_REGISTERS : integer;
attribute C_ECC_STATUS_REGISTERS of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "artix7";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
attribute C_HIGHADDR : string;
attribute C_HIGHADDR of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "64'b0000000000000000000000000000000000000000000000000111111111111111";
attribute C_INTERCONNECT : integer;
attribute C_INTERCONNECT of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
attribute C_LMB_AWIDTH : integer;
attribute C_LMB_AWIDTH of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 32;
attribute C_LMB_DWIDTH : integer;
attribute C_LMB_DWIDTH of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 32;
attribute C_MASK : string;
attribute C_MASK of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "64'b0000000000000000000000000000000011000000000000000000000000000000";
attribute C_MASK1 : string;
attribute C_MASK1 of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "64'b0000000000000000000000000000000000000000100000000000000000000000";
attribute C_MASK2 : string;
attribute C_MASK2 of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "64'b0000000000000000000000000000000000000000100000000000000000000000";
attribute C_MASK3 : string;
attribute C_MASK3 of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "64'b0000000000000000000000000000000000000000100000000000000000000000";
attribute C_NUM_LMB : integer;
attribute C_NUM_LMB of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 1;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 32;
attribute C_S_AXI_CTRL_BASEADDR : string;
attribute C_S_AXI_CTRL_BASEADDR of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "32'b11111111111111111111111111111111";
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 32;
attribute C_S_AXI_CTRL_HIGHADDR : string;
attribute C_S_AXI_CTRL_HIGHADDR of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "32'b00000000000000000000000000000000";
attribute C_UE_FAILING_REGISTERS : integer;
attribute C_UE_FAILING_REGISTERS of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
attribute C_WRITE_ACCESS : integer;
attribute C_WRITE_ACCESS of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 2;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "lmb_bram_if_cntlr";
end system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr;
architecture STRUCTURE of system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr is
signal \<const0>\ : STD_LOGIC;
signal \^bram_din_a\ : STD_LOGIC_VECTOR ( 0 to 31 );
signal \^lmb_abus\ : STD_LOGIC_VECTOR ( 0 to 31 );
signal \^lmb_addrstrobe\ : STD_LOGIC;
signal \^lmb_clk\ : STD_LOGIC;
signal \^lmb_writedbus\ : STD_LOGIC_VECTOR ( 0 to 31 );
signal \No_ECC.Sl_Rdy_i_1_n_0\ : STD_LOGIC;
signal \No_ECC.lmb_as_i_1_n_0\ : STD_LOGIC;
signal Sl_Rdy : STD_LOGIC;
signal lmb_as : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \BRAM_WEN_A[0]_INST_0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \BRAM_WEN_A[1]_INST_0\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \BRAM_WEN_A[2]_INST_0\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \BRAM_WEN_A[3]_INST_0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \No_ECC.Sl_Rdy_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \No_ECC.lmb_as_i_1\ : label is "soft_lutpair2";
begin
BRAM_Addr_A(0 to 31) <= \^lmb_abus\(0 to 31);
BRAM_Clk_A <= \^lmb_clk\;
BRAM_Dout_A(0 to 31) <= \^lmb_writedbus\(0 to 31);
BRAM_EN_A <= \^lmb_addrstrobe\;
BRAM_Rst_A <= \<const0>\;
CE <= \<const0>\;
Interrupt <= \<const0>\;
S_AXI_CTRL_ARREADY <= \<const0>\;
S_AXI_CTRL_AWREADY <= \<const0>\;
S_AXI_CTRL_BRESP(1) <= \<const0>\;
S_AXI_CTRL_BRESP(0) <= \<const0>\;
S_AXI_CTRL_BVALID <= \<const0>\;
S_AXI_CTRL_RDATA(31) <= \<const0>\;
S_AXI_CTRL_RDATA(30) <= \<const0>\;
S_AXI_CTRL_RDATA(29) <= \<const0>\;
S_AXI_CTRL_RDATA(28) <= \<const0>\;
S_AXI_CTRL_RDATA(27) <= \<const0>\;
S_AXI_CTRL_RDATA(26) <= \<const0>\;
S_AXI_CTRL_RDATA(25) <= \<const0>\;
S_AXI_CTRL_RDATA(24) <= \<const0>\;
S_AXI_CTRL_RDATA(23) <= \<const0>\;
S_AXI_CTRL_RDATA(22) <= \<const0>\;
S_AXI_CTRL_RDATA(21) <= \<const0>\;
S_AXI_CTRL_RDATA(20) <= \<const0>\;
S_AXI_CTRL_RDATA(19) <= \<const0>\;
S_AXI_CTRL_RDATA(18) <= \<const0>\;
S_AXI_CTRL_RDATA(17) <= \<const0>\;
S_AXI_CTRL_RDATA(16) <= \<const0>\;
S_AXI_CTRL_RDATA(15) <= \<const0>\;
S_AXI_CTRL_RDATA(14) <= \<const0>\;
S_AXI_CTRL_RDATA(13) <= \<const0>\;
S_AXI_CTRL_RDATA(12) <= \<const0>\;
S_AXI_CTRL_RDATA(11) <= \<const0>\;
S_AXI_CTRL_RDATA(10) <= \<const0>\;
S_AXI_CTRL_RDATA(9) <= \<const0>\;
S_AXI_CTRL_RDATA(8) <= \<const0>\;
S_AXI_CTRL_RDATA(7) <= \<const0>\;
S_AXI_CTRL_RDATA(6) <= \<const0>\;
S_AXI_CTRL_RDATA(5) <= \<const0>\;
S_AXI_CTRL_RDATA(4) <= \<const0>\;
S_AXI_CTRL_RDATA(3) <= \<const0>\;
S_AXI_CTRL_RDATA(2) <= \<const0>\;
S_AXI_CTRL_RDATA(1) <= \<const0>\;
S_AXI_CTRL_RDATA(0) <= \<const0>\;
S_AXI_CTRL_RRESP(1) <= \<const0>\;
S_AXI_CTRL_RRESP(0) <= \<const0>\;
S_AXI_CTRL_RVALID <= \<const0>\;
S_AXI_CTRL_WREADY <= \<const0>\;
Sl1_CE <= \<const0>\;
Sl1_DBus(0) <= \<const0>\;
Sl1_DBus(1) <= \<const0>\;
Sl1_DBus(2) <= \<const0>\;
Sl1_DBus(3) <= \<const0>\;
Sl1_DBus(4) <= \<const0>\;
Sl1_DBus(5) <= \<const0>\;
Sl1_DBus(6) <= \<const0>\;
Sl1_DBus(7) <= \<const0>\;
Sl1_DBus(8) <= \<const0>\;
Sl1_DBus(9) <= \<const0>\;
Sl1_DBus(10) <= \<const0>\;
Sl1_DBus(11) <= \<const0>\;
Sl1_DBus(12) <= \<const0>\;
Sl1_DBus(13) <= \<const0>\;
Sl1_DBus(14) <= \<const0>\;
Sl1_DBus(15) <= \<const0>\;
Sl1_DBus(16) <= \<const0>\;
Sl1_DBus(17) <= \<const0>\;
Sl1_DBus(18) <= \<const0>\;
Sl1_DBus(19) <= \<const0>\;
Sl1_DBus(20) <= \<const0>\;
Sl1_DBus(21) <= \<const0>\;
Sl1_DBus(22) <= \<const0>\;
Sl1_DBus(23) <= \<const0>\;
Sl1_DBus(24) <= \<const0>\;
Sl1_DBus(25) <= \<const0>\;
Sl1_DBus(26) <= \<const0>\;
Sl1_DBus(27) <= \<const0>\;
Sl1_DBus(28) <= \<const0>\;
Sl1_DBus(29) <= \<const0>\;
Sl1_DBus(30) <= \<const0>\;
Sl1_DBus(31) <= \<const0>\;
Sl1_Ready <= \<const0>\;
Sl1_UE <= \<const0>\;
Sl1_Wait <= \<const0>\;
Sl2_CE <= \<const0>\;
Sl2_DBus(0) <= \<const0>\;
Sl2_DBus(1) <= \<const0>\;
Sl2_DBus(2) <= \<const0>\;
Sl2_DBus(3) <= \<const0>\;
Sl2_DBus(4) <= \<const0>\;
Sl2_DBus(5) <= \<const0>\;
Sl2_DBus(6) <= \<const0>\;
Sl2_DBus(7) <= \<const0>\;
Sl2_DBus(8) <= \<const0>\;
Sl2_DBus(9) <= \<const0>\;
Sl2_DBus(10) <= \<const0>\;
Sl2_DBus(11) <= \<const0>\;
Sl2_DBus(12) <= \<const0>\;
Sl2_DBus(13) <= \<const0>\;
Sl2_DBus(14) <= \<const0>\;
Sl2_DBus(15) <= \<const0>\;
Sl2_DBus(16) <= \<const0>\;
Sl2_DBus(17) <= \<const0>\;
Sl2_DBus(18) <= \<const0>\;
Sl2_DBus(19) <= \<const0>\;
Sl2_DBus(20) <= \<const0>\;
Sl2_DBus(21) <= \<const0>\;
Sl2_DBus(22) <= \<const0>\;
Sl2_DBus(23) <= \<const0>\;
Sl2_DBus(24) <= \<const0>\;
Sl2_DBus(25) <= \<const0>\;
Sl2_DBus(26) <= \<const0>\;
Sl2_DBus(27) <= \<const0>\;
Sl2_DBus(28) <= \<const0>\;
Sl2_DBus(29) <= \<const0>\;
Sl2_DBus(30) <= \<const0>\;
Sl2_DBus(31) <= \<const0>\;
Sl2_Ready <= \<const0>\;
Sl2_UE <= \<const0>\;
Sl2_Wait <= \<const0>\;
Sl3_CE <= \<const0>\;
Sl3_DBus(0) <= \<const0>\;
Sl3_DBus(1) <= \<const0>\;
Sl3_DBus(2) <= \<const0>\;
Sl3_DBus(3) <= \<const0>\;
Sl3_DBus(4) <= \<const0>\;
Sl3_DBus(5) <= \<const0>\;
Sl3_DBus(6) <= \<const0>\;
Sl3_DBus(7) <= \<const0>\;
Sl3_DBus(8) <= \<const0>\;
Sl3_DBus(9) <= \<const0>\;
Sl3_DBus(10) <= \<const0>\;
Sl3_DBus(11) <= \<const0>\;
Sl3_DBus(12) <= \<const0>\;
Sl3_DBus(13) <= \<const0>\;
Sl3_DBus(14) <= \<const0>\;
Sl3_DBus(15) <= \<const0>\;
Sl3_DBus(16) <= \<const0>\;
Sl3_DBus(17) <= \<const0>\;
Sl3_DBus(18) <= \<const0>\;
Sl3_DBus(19) <= \<const0>\;
Sl3_DBus(20) <= \<const0>\;
Sl3_DBus(21) <= \<const0>\;
Sl3_DBus(22) <= \<const0>\;
Sl3_DBus(23) <= \<const0>\;
Sl3_DBus(24) <= \<const0>\;
Sl3_DBus(25) <= \<const0>\;
Sl3_DBus(26) <= \<const0>\;
Sl3_DBus(27) <= \<const0>\;
Sl3_DBus(28) <= \<const0>\;
Sl3_DBus(29) <= \<const0>\;
Sl3_DBus(30) <= \<const0>\;
Sl3_DBus(31) <= \<const0>\;
Sl3_Ready <= \<const0>\;
Sl3_UE <= \<const0>\;
Sl3_Wait <= \<const0>\;
Sl_CE <= \<const0>\;
Sl_DBus(0 to 31) <= \^bram_din_a\(0 to 31);
Sl_UE <= \<const0>\;
Sl_Wait <= \<const0>\;
UE <= \<const0>\;
\^bram_din_a\(0 to 31) <= BRAM_Din_A(0 to 31);
\^lmb_abus\(0 to 31) <= LMB_ABus(0 to 31);
\^lmb_addrstrobe\ <= LMB_AddrStrobe;
\^lmb_clk\ <= LMB_Clk;
\^lmb_writedbus\(0 to 31) <= LMB_WriteDBus(0 to 31);
\BRAM_WEN_A[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => LMB_WriteStrobe,
I1 => LMB_BE(0),
I2 => \^lmb_abus\(1),
I3 => \^lmb_abus\(0),
O => BRAM_WEN_A(0)
);
\BRAM_WEN_A[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \^lmb_abus\(1),
I1 => \^lmb_abus\(0),
I2 => LMB_WriteStrobe,
I3 => LMB_BE(1),
O => BRAM_WEN_A(1)
);
\BRAM_WEN_A[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \^lmb_abus\(1),
I1 => \^lmb_abus\(0),
I2 => LMB_WriteStrobe,
I3 => LMB_BE(2),
O => BRAM_WEN_A(2)
);
\BRAM_WEN_A[3]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \^lmb_abus\(1),
I1 => \^lmb_abus\(0),
I2 => LMB_WriteStrobe,
I3 => LMB_BE(3),
O => BRAM_WEN_A(3)
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\No_ECC.Sl_Rdy_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^lmb_abus\(0),
I1 => \^lmb_abus\(1),
I2 => LMB_Rst,
O => \No_ECC.Sl_Rdy_i_1_n_0\
);
\No_ECC.Sl_Rdy_reg\: unisim.vcomponents.FDRE
port map (
C => \^lmb_clk\,
CE => '1',
D => \No_ECC.Sl_Rdy_i_1_n_0\,
Q => Sl_Rdy,
R => '0'
);
\No_ECC.lmb_as_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^lmb_addrstrobe\,
I1 => LMB_Rst,
O => \No_ECC.lmb_as_i_1_n_0\
);
\No_ECC.lmb_as_reg\: unisim.vcomponents.FDRE
port map (
C => \^lmb_clk\,
CE => '1',
D => \No_ECC.lmb_as_i_1_n_0\,
Q => lmb_as,
R => '0'
);
Sl_Ready_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => Sl_Rdy,
I1 => lmb_as,
O => Sl_Ready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_dlmb_bram_if_cntlr_0 is
port (
LMB_Clk : in STD_LOGIC;
LMB_Rst : in STD_LOGIC;
LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_AddrStrobe : in STD_LOGIC;
LMB_ReadStrobe : in STD_LOGIC;
LMB_WriteStrobe : in STD_LOGIC;
LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : out STD_LOGIC;
Sl_Wait : out STD_LOGIC;
Sl_UE : out STD_LOGIC;
Sl_CE : out STD_LOGIC;
BRAM_Rst_A : out STD_LOGIC;
BRAM_Clk_A : out STD_LOGIC;
BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_EN_A : out STD_LOGIC;
BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_dlmb_bram_if_cntlr_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_dlmb_bram_if_cntlr_0 : entity is "system_dlmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_dlmb_bram_if_cntlr_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_dlmb_bram_if_cntlr_0 : entity is "lmb_bram_if_cntlr,Vivado 2016.4";
end system_dlmb_bram_if_cntlr_0;
architecture STRUCTURE of system_dlmb_bram_if_cntlr_0 is
signal NLW_U0_CE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl1_CE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl1_Ready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl1_UE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl1_Wait_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl2_CE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl2_Ready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl2_UE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl2_Wait_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl3_CE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl3_Ready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl3_UE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl3_Wait_UNCONNECTED : STD_LOGIC;
signal NLW_U0_UE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_Sl1_DBus_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_Sl2_DBus_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_Sl3_DBus_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
attribute C_BASEADDR : string;
attribute C_BASEADDR of U0 : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute C_BRAM_AWIDTH : integer;
attribute C_BRAM_AWIDTH of U0 : label is 32;
attribute C_CE_COUNTER_WIDTH : integer;
attribute C_CE_COUNTER_WIDTH of U0 : label is 0;
attribute C_CE_FAILING_REGISTERS : integer;
attribute C_CE_FAILING_REGISTERS of U0 : label is 0;
attribute C_ECC : integer;
attribute C_ECC of U0 : label is 0;
attribute C_ECC_ONOFF_REGISTER : integer;
attribute C_ECC_ONOFF_REGISTER of U0 : label is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of U0 : label is 1;
attribute C_ECC_STATUS_REGISTERS : integer;
attribute C_ECC_STATUS_REGISTERS of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of U0 : label is 0;
attribute C_HIGHADDR : string;
attribute C_HIGHADDR of U0 : label is "64'b0000000000000000000000000000000000000000000000000111111111111111";
attribute C_INTERCONNECT : integer;
attribute C_INTERCONNECT of U0 : label is 0;
attribute C_LMB_AWIDTH : integer;
attribute C_LMB_AWIDTH of U0 : label is 32;
attribute C_LMB_DWIDTH : integer;
attribute C_LMB_DWIDTH of U0 : label is 32;
attribute C_MASK : string;
attribute C_MASK of U0 : label is "64'b0000000000000000000000000000000011000000000000000000000000000000";
attribute C_MASK1 : string;
attribute C_MASK1 of U0 : label is "64'b0000000000000000000000000000000000000000100000000000000000000000";
attribute C_MASK2 : string;
attribute C_MASK2 of U0 : label is "64'b0000000000000000000000000000000000000000100000000000000000000000";
attribute C_MASK3 : string;
attribute C_MASK3 of U0 : label is "64'b0000000000000000000000000000000000000000100000000000000000000000";
attribute C_NUM_LMB : integer;
attribute C_NUM_LMB of U0 : label is 1;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of U0 : label is 32;
attribute C_S_AXI_CTRL_BASEADDR : string;
attribute C_S_AXI_CTRL_BASEADDR of U0 : label is "32'b11111111111111111111111111111111";
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_CTRL_HIGHADDR : string;
attribute C_S_AXI_CTRL_HIGHADDR of U0 : label is "32'b00000000000000000000000000000000";
attribute C_UE_FAILING_REGISTERS : integer;
attribute C_UE_FAILING_REGISTERS of U0 : label is 0;
attribute C_WRITE_ACCESS : integer;
attribute C_WRITE_ACCESS of U0 : label is 2;
begin
U0: entity work.system_dlmb_bram_if_cntlr_0_lmb_bram_if_cntlr
port map (
BRAM_Addr_A(0 to 31) => BRAM_Addr_A(0 to 31),
BRAM_Clk_A => BRAM_Clk_A,
BRAM_Din_A(0 to 31) => BRAM_Din_A(0 to 31),
BRAM_Dout_A(0 to 31) => BRAM_Dout_A(0 to 31),
BRAM_EN_A => BRAM_EN_A,
BRAM_Rst_A => BRAM_Rst_A,
BRAM_WEN_A(0 to 3) => BRAM_WEN_A(0 to 3),
CE => NLW_U0_CE_UNCONNECTED,
Interrupt => NLW_U0_Interrupt_UNCONNECTED,
LMB1_ABus(0 to 31) => B"00000000000000000000000000000000",
LMB1_AddrStrobe => '0',
LMB1_BE(0 to 3) => B"0000",
LMB1_ReadStrobe => '0',
LMB1_WriteDBus(0 to 31) => B"00000000000000000000000000000000",
LMB1_WriteStrobe => '0',
LMB2_ABus(0 to 31) => B"00000000000000000000000000000000",
LMB2_AddrStrobe => '0',
LMB2_BE(0 to 3) => B"0000",
LMB2_ReadStrobe => '0',
LMB2_WriteDBus(0 to 31) => B"00000000000000000000000000000000",
LMB2_WriteStrobe => '0',
LMB3_ABus(0 to 31) => B"00000000000000000000000000000000",
LMB3_AddrStrobe => '0',
LMB3_BE(0 to 3) => B"0000",
LMB3_ReadStrobe => '0',
LMB3_WriteDBus(0 to 31) => B"00000000000000000000000000000000",
LMB3_WriteStrobe => '0',
LMB_ABus(0 to 31) => LMB_ABus(0 to 31),
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_BE(0 to 3) => LMB_BE(0 to 3),
LMB_Clk => LMB_Clk,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_Rst => LMB_Rst,
LMB_WriteDBus(0 to 31) => LMB_WriteDBus(0 to 31),
LMB_WriteStrobe => LMB_WriteStrobe,
S_AXI_CTRL_ACLK => '0',
S_AXI_CTRL_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_CTRL_ARESETN => '0',
S_AXI_CTRL_ARREADY => NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED,
S_AXI_CTRL_ARVALID => '0',
S_AXI_CTRL_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_CTRL_AWREADY => NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED,
S_AXI_CTRL_AWVALID => '0',
S_AXI_CTRL_BREADY => '0',
S_AXI_CTRL_BRESP(1 downto 0) => NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED(1 downto 0),
S_AXI_CTRL_BVALID => NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED,
S_AXI_CTRL_RDATA(31 downto 0) => NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED(31 downto 0),
S_AXI_CTRL_RREADY => '0',
S_AXI_CTRL_RRESP(1 downto 0) => NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED(1 downto 0),
S_AXI_CTRL_RVALID => NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED,
S_AXI_CTRL_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_CTRL_WREADY => NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED,
S_AXI_CTRL_WSTRB(3 downto 0) => B"0000",
S_AXI_CTRL_WVALID => '0',
Sl1_CE => NLW_U0_Sl1_CE_UNCONNECTED,
Sl1_DBus(0 to 31) => NLW_U0_Sl1_DBus_UNCONNECTED(0 to 31),
Sl1_Ready => NLW_U0_Sl1_Ready_UNCONNECTED,
Sl1_UE => NLW_U0_Sl1_UE_UNCONNECTED,
Sl1_Wait => NLW_U0_Sl1_Wait_UNCONNECTED,
Sl2_CE => NLW_U0_Sl2_CE_UNCONNECTED,
Sl2_DBus(0 to 31) => NLW_U0_Sl2_DBus_UNCONNECTED(0 to 31),
Sl2_Ready => NLW_U0_Sl2_Ready_UNCONNECTED,
Sl2_UE => NLW_U0_Sl2_UE_UNCONNECTED,
Sl2_Wait => NLW_U0_Sl2_Wait_UNCONNECTED,
Sl3_CE => NLW_U0_Sl3_CE_UNCONNECTED,
Sl3_DBus(0 to 31) => NLW_U0_Sl3_DBus_UNCONNECTED(0 to 31),
Sl3_Ready => NLW_U0_Sl3_Ready_UNCONNECTED,
Sl3_UE => NLW_U0_Sl3_UE_UNCONNECTED,
Sl3_Wait => NLW_U0_Sl3_Wait_UNCONNECTED,
Sl_CE => Sl_CE,
Sl_DBus(0 to 31) => Sl_DBus(0 to 31),
Sl_Ready => Sl_Ready,
Sl_UE => Sl_UE,
Sl_Wait => Sl_Wait,
UE => NLW_U0_UE_UNCONNECTED
);
end STRUCTURE;
|
apache-2.0
|
87632212134041f24b5216723b845c31
| 0.630259 | 2.912949 | false | false | false | false |
jeffmagina/ECE368
|
Project1/WRITE_BACK/write_back_tbd.vhd
| 1 | 3,907 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:13:53 04/06/2015
-- Design Name:
-- Module Name: C:/Users/Jeff Magina/Documents/GitHub/ECE368/Project1/WRITE_BACK/write_back_tbd.vhd
-- Project Name: Write_Back
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: write_back
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY write_back_tbd IS
END write_back_tbd;
ARCHITECTURE behavior OF write_back_tbd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT write_back
PORT(
CLK : IN STD_LOGIC;
DATA_WE : IN STD_LOGIC;
FPU_IN : IN STD_LOGIC_VECTOR (15 downto 0);
REG_A : IN STD_LOGIC_VECTOR (15 downto 0);
D_OUT_SEL : IN STD_LOGIC;
WB_OUT : OUT STD_LOGIC_VECTOR (15 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal DATA_WE : std_logic := '0';
signal FPU_IN : std_logic_vector(15 downto 0) := (others => '0');
signal REG_A : std_logic_vector(15 downto 0) := (others => '0');
signal D_OUT_SEL : std_logic := '0';
--Outputs
signal WB_OUT : std_logic_vector(15 downto 0):= (others => '0');
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: write_back PORT MAP (
CLK => CLK,
DATA_WE => DATA_WE,
FPU_IN => FPU_IN,
REG_A => REG_A,
D_OUT_SEL => D_OUT_SEL,
WB_OUT => WB_OUT
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
tb: process
begin
wait for 100 ns;
FPU_IN <= x"0003";
REG_A <= x"1234";
wait for CLK_PERIOD;
-- Don't care what WB_OUT because WE is low
DATA_WE <= '1';
wait for CLK_PERIOD;
-- Simulating a Load
FPU_IN <= x"0002";
wait for CLK_PERIOD;
DATA_WE <= '0';
D_OUT_SEL <= '0';
wait for CLK_PERIOD;
-- Storing FFFF into DATA MEM
FPU_IN <= x"0001";
REG_A <= x"FFFF";
wait for CLK_PERIOD;
DATA_WE <= '1';
wait for CLK_PERIOD;
FPU_IN <= x"0000";
REG_A <= x"0001";
wait for CLK_PERIOD;
DATA_WE <= '1';
wait for CLK_PERIOD;
-- Simulating Load from data memory
FPU_IN <= x"0001";
wait for CLK_PERIOD;
DATA_WE <= '0';
D_OUT_SEL <= '0';
wait for CLK_PERIOD;
FPU_IN <= x"0000";
wait for CLK_PERIOD;
DATA_WE <= '0';
D_OUT_SEL <= '0';
wait for CLK_PERIOD;
-- Simulating FPU Data to Register
FPU_IN <= x"00FF";
wait for CLK_PERIOD;
DATA_WE <= '0';
D_OUT_SEL <= '1';
wait for CLK_PERIOD;
FPU_IN <= x"00CC";
wait for CLK_PERIOD;
DATA_WE <= '0';
D_OUT_SEL <= '1';
wait for CLK_PERIOD;
wait;
end process;
END;
|
mit
|
988f258fd657bdcdf933901809d866de
| 0.530842 | 3.590993 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_wiz_0_0_soft_reset.vhd
| 1 | 13,846 |
-------------------------------------------------------------------------------
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v3_30_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity system_xadc_wiz_0_0_soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end system_xadc_wiz_0_0_soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of system_xadc_wiz_0_0_soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
|
apache-2.0
|
f9190c407d2c772f0782e21ec67ea482
| 0.403943 | 4.856542 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ipshared/38e8/hdl/lib_bmg_v1_0_rfs.vhd
| 1 | 30,885 |
-- blk_mem_gen_wrapper.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008, 2009. 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: blk_mem_gen_wrapper.vhd
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
library blk_mem_gen_v8_3_5;
use blk_mem_gen_v8_3_5.all;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
entity blk_mem_gen_wrapper is
generic
(
-- Device Family
c_family : string := "virtex7";
c_xdevicefamily : string := "virtex7";
c_elaboration_dir : string := "";
-- Memory Specific Configurations
c_mem_type : integer := 2;
-- This wrapper only supports the True Dual Port RAM
-- 0: Single Port RAM
-- 1: Simple Dual Port RAM
-- 2: True Dual Port RAM
-- 3: Single Port Rom
-- 4: Dual Port RAM
c_algorithm : integer := 1;
-- 0: Selectable Primative
-- 1: Minimum Area
c_prim_type : integer := 1;
-- 0: ( 1-bit wide)
-- 1: ( 2-bit wide)
-- 2: ( 4-bit wide)
-- 3: ( 9-bit wide)
-- 4: (18-bit wide)
-- 5: (36-bit wide)
-- 6: (72-bit wide, single port only)
c_byte_size : integer := 9; -- 8 or 9
-- Simulation Behavior Options
c_sim_collision_check : string := "NONE";
-- "None"
-- "Generate_X"
-- "All"
-- "Warnings_only"
c_common_clk : integer := 1; -- 0, 1
c_disable_warn_bhv_coll : integer := 0; -- 0, 1
c_disable_warn_bhv_range : integer := 0; -- 0, 1
-- Initialization Configuration Options
c_load_init_file : integer := 0;
c_init_file_name : string := "no_coe_file_loaded";
c_use_default_data : integer := 0; -- 0, 1
c_default_data : string := "0"; -- "..."
-- Port A Specific Configurations
c_has_mem_output_regs_a : integer := 0; -- 0, 1
c_has_mux_output_regs_a : integer := 0; -- 0, 1
c_write_width_a : integer := 32; -- 1 to 1152
c_read_width_a : integer := 32; -- 1 to 1152
c_write_depth_a : integer := 64; -- 2 to 9011200
c_read_depth_a : integer := 64; -- 2 to 9011200
c_addra_width : integer := 6; -- 1 to 24
c_write_mode_a : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_ena : integer := 1; -- 0, 1
c_has_regcea : integer := 0; -- 0, 1
c_has_ssra : integer := 0; -- 0, 1
c_sinita_val : string := "0"; --"..."
c_use_byte_wea : integer := 0; -- 0, 1
c_wea_width : integer := 1; -- 1 to 128
-- Port B Specific Configurations
c_has_mem_output_regs_b : integer := 0; -- 0, 1
c_has_mux_output_regs_b : integer := 0; -- 0, 1
c_write_width_b : integer := 32; -- 1 to 1152
c_read_width_b : integer := 32; -- 1 to 1152
c_write_depth_b : integer := 64; -- 2 to 9011200
c_read_depth_b : integer := 64; -- 2 to 9011200
c_addrb_width : integer := 6; -- 1 to 24
c_write_mode_b : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_enb : integer := 1; -- 0, 1
c_has_regceb : integer := 0; -- 0, 1
c_has_ssrb : integer := 0; -- 0, 1
c_sinitb_val : string := "0"; -- "..."
c_use_byte_web : integer := 0; -- 0, 1
c_web_width : integer := 1; -- 1 to 128
-- Other Miscellaneous Configurations
c_mux_pipeline_stages : integer := 0; -- 0, 1, 2, 3
-- The number of pipeline stages within the MUX
-- for both Port A and Port B
c_use_ecc : integer := 0;
-- See DS512 for the limited core option selections for ECC support
c_use_ramb16bwer_rst_bhv : integer := 0--; --0, 1
-- c_corename : string := "blk_mem_gen_v2_7"
--Uncommenting the above parameter (C_CORENAME) will cause
--the a failure in NGCBuild!!!
);
port
(
clka : in std_logic;
ssra : in std_logic := '0';
dina : in std_logic_vector(c_write_width_a-1 downto 0) := (OTHERS => '0');
addra : in std_logic_vector(c_addra_width-1 downto 0);
ena : in std_logic := '1';
regcea : in std_logic := '1';
wea : in std_logic_vector(c_wea_width-1 downto 0) := (OTHERS => '0');
douta : out std_logic_vector(c_read_width_a-1 downto 0);
clkb : in std_logic := '0';
ssrb : in std_logic := '0';
dinb : in std_logic_vector(c_write_width_b-1 downto 0) := (OTHERS => '0');
addrb : in std_logic_vector(c_addrb_width-1 downto 0) := (OTHERS => '0');
enb : in std_logic := '1';
regceb : in std_logic := '1';
web : in std_logic_vector(c_web_width-1 downto 0) := (OTHERS => '0');
doutb : out std_logic_vector(c_read_width_b-1 downto 0);
dbiterr : out std_logic;
-- Double bit error that that cannot be auto corrected by ECC
sbiterr : out std_logic
-- Single Bit Error that has been auto corrected on the output bus
);
end entity blk_mem_gen_wrapper;
architecture implementation of blk_mem_gen_wrapper is
-- directly passing C_FAMILY
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
Constant FAMILY_IS_SUPPORTED : boolean := true;
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal RDADDRECC : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal S_AXI_AWREADY : STD_LOGIC;
signal S_AXI_WREADY : STD_LOGIC;
signal S_AXI_BID : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal S_AXI_BRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal S_AXI_BVALID : STD_LOGIC;
signal S_AXI_ARREADY : STD_LOGIC;
signal S_AXI_RID : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal S_AXI_RDATA : STD_LOGIC_VECTOR(c_write_width_b-1 DOWNTO 0);
signal S_AXI_RRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal S_AXI_RLAST : STD_LOGIC;
signal S_AXI_RVALID : STD_LOGIC;
signal S_AXI_SBITERR : STD_LOGIC;
signal S_AXI_DBITERR : STD_LOGIC;
signal S_AXI_RDADDRECC : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal S_AXI_WSTRB : STD_LOGIC_VECTOR(c_wea_width-1 downto 0);
signal S_AXI_WDATA : STD_LOGIC_VECTOR(c_write_width_a-1 downto 0);
signal RSTA_BUSY : STD_LOGIC;
signal RSTB_BUSY : STD_LOGIC;
begin
S_AXI_WSTRB <= (others => '0');
S_AXI_WDATA <= (others => '0');
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising clock edge to issue assertion
-- Wait until clka = '1';
-- wait until clka = '0';
-- Wait until clka = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait; -- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low
-- douta <= (others => '0'); -- : out std_logic_vector(c_read_width_a-1 downto 0);
-- doutb <= (others => '0'); -- : out std_logic_vector(c_read_width_b-1 downto 0);
-- dbiterr <= '0' ; -- : out std_logic;
-- sbiterr <= '0' ; -- : out std_logic
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the Block Memeory using blk_mem_gen 5.2.
-- This is for new cores designed and tested with FPGA
-- Families of Virtex-6, Spartan-6 and later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen Block Memory Generator Call module
-- for new IP BRAM implementations.
--
-------------------------------------------------------------------------------
I_TRUE_DUAL_PORT_BLK_MEM_GEN : entity blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5
generic map
(
--C_CORENAME => c_corename ,
-- Device Family
C_FAMILY => FAMILY_TO_USE ,
C_XDEVICEFAMILY => c_xdevicefamily ,
C_ELABORATION_DIR => c_elaboration_dir ,
------------------
C_INTERFACE_TYPE => 0 ,
C_USE_BRAM_BLOCK => 0 ,
C_AXI_TYPE => 0 ,
C_AXI_SLAVE_TYPE => 0 ,
C_HAS_AXI_ID => 0 ,
C_AXI_ID_WIDTH => 4 ,
------------------
-- Memory Specific Configurations
C_MEM_TYPE => c_mem_type ,
C_BYTE_SIZE => c_byte_size ,
C_ALGORITHM => c_algorithm ,
C_PRIM_TYPE => c_prim_type ,
C_LOAD_INIT_FILE => c_load_init_file ,
C_INIT_FILE_NAME => c_init_file_name ,
C_INIT_FILE => "" ,
C_USE_DEFAULT_DATA => c_use_default_data ,
C_DEFAULT_DATA => c_default_data ,
-- Port A Specific Configurations
--C_RST_TYPE => "SYNC" , --Removed in version v8_2
C_HAS_RSTA => c_has_ssra ,
C_RST_PRIORITY_A => "CE" ,
C_RSTRAM_A => 0 ,
C_INITA_VAL => c_sinita_val ,
C_HAS_ENA => c_has_ena ,
C_HAS_REGCEA => c_has_regcea ,
C_USE_BYTE_WEA => c_use_byte_wea ,
C_WEA_WIDTH => c_wea_width ,
C_WRITE_MODE_A => c_write_mode_a ,
C_WRITE_WIDTH_A => c_write_width_a ,
C_READ_WIDTH_A => c_read_width_a ,
C_WRITE_DEPTH_A => c_write_depth_a ,
C_READ_DEPTH_A => c_read_depth_a ,
C_ADDRA_WIDTH => c_addra_width ,
-- Port B Specific Configurations
C_HAS_RSTB => c_has_ssrb ,
C_RST_PRIORITY_B => "CE" ,
C_RSTRAM_B => 0 ,
C_INITB_VAL => c_sinitb_val ,
C_HAS_ENB => c_has_enb ,
C_HAS_REGCEB => c_has_regceb ,
C_USE_BYTE_WEB => c_use_byte_web ,
C_WEB_WIDTH => c_web_width ,
C_WRITE_MODE_B => c_write_mode_b ,
C_WRITE_WIDTH_B => c_write_width_b ,
C_READ_WIDTH_B => c_read_width_b ,
C_WRITE_DEPTH_B => c_write_depth_b ,
C_READ_DEPTH_B => c_read_depth_b ,
C_ADDRB_WIDTH => c_addrb_width ,
C_HAS_MEM_OUTPUT_REGS_A => c_has_mem_output_regs_a ,
C_HAS_MEM_OUTPUT_REGS_B => c_has_mem_output_regs_b ,
C_HAS_MUX_OUTPUT_REGS_A => c_has_mux_output_regs_a ,
C_HAS_MUX_OUTPUT_REGS_B => c_has_mux_output_regs_b ,
C_HAS_SOFTECC_INPUT_REGS_A => 0 ,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0 ,
-- Other Miscellaneous Configurations
C_MUX_PIPELINE_STAGES => c_mux_pipeline_stages ,
C_USE_SOFTECC => 0 ,
C_USE_ECC => c_use_ecc ,
C_EN_ECC_PIPE => 0 ,
-- New features in 2015.1
C_EN_DEEPSLEEP_PIN => 0 ,
C_EN_SHUTDOWN_PIN => 0 ,
C_EN_SAFETY_CKT => 0 ,
C_USE_URAM => 0 ,
C_EN_RDADDRA_CHG => 0 ,
C_EN_RDADDRB_CHG => 0 ,
-- Simulation Behavior Options
C_HAS_INJECTERR => 0 ,
C_SIM_COLLISION_CHECK => c_sim_collision_check ,
C_COMMON_CLK => c_common_clk ,
C_DISABLE_WARN_BHV_COLL => c_disable_warn_bhv_coll ,
C_EN_SLEEP_PIN => 0 ,
C_DISABLE_WARN_BHV_RANGE => c_disable_warn_bhv_range
)
port map
(
CLKA => clka ,
RSTA => ssra ,
ENA => ena ,
REGCEA => regcea ,
WEA => wea ,
ADDRA => addra ,
DINA => dina ,
DOUTA => douta ,
CLKB => clkb ,
RSTB => ssrb ,
ENB => enb ,
REGCEB => regceb ,
WEB => web ,
ADDRB => addrb ,
DINB => dinb ,
DOUTB => doutb ,
INJECTSBITERR => '0' , -- input
INJECTDBITERR => '0' , -- input
SBITERR => sbiterr ,
DBITERR => dbiterr ,
RDADDRECC => RDADDRECC , -- output
ECCPIPECE => '0' ,
SLEEP => '0' ,
SHUTDOWN => '0' ,
DEEPSLEEP => '0' ,
RSTA_BUSY => RSTA_BUSY ,
RSTB_BUSY => RSTB_BUSY ,
-- AXI BMG Input and Output Port Declarations -- new for v6.2
-- new for v6.2
-- AXI Global Signals -- new for v6.2
S_AClk => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_ARESETN => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Write (write side) -- new for v6.2
S_AXI_AWID => "0000" , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWADDR => "00000000000000000000000000000000" , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWLEN => "00000000" , -- : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWSIZE => "000" , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWBURST => "00" , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_AWREADY => S_AXI_AWREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_WDATA => S_AXI_WDATA , -- : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WSTRB => S_AXI_WSTRB , -- : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WLAST => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WREADY => S_AXI_WREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_BID => S_AXI_BID , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_BRESP => S_AXI_BRESP , -- : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- new for v6.2
S_AXI_BVALID => S_AXI_BVALID , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_BREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Read (Write side) -- new for v6.2
S_AXI_ARID => "0000" , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARADDR => "00000000000000000000000000000000" , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARLEN => "00000000" , -- : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARSIZE => "000" , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARBURST => "00" , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_ARREADY => S_AXI_ARREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RID => S_AXI_RID , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_RDATA => S_AXI_RDATA , -- : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0); -- new for v6.2
S_AXI_RRESP => S_AXI_RRESP , -- : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0); -- new for v6.2
S_AXI_RLAST => S_AXI_RLAST , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RVALID => S_AXI_RVALID , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Sideband Signals -- new for v6.2
S_AXI_INJECTSBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_INJECTDBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_SBITERR => S_AXI_SBITERR , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_DBITERR => S_AXI_DBITERR , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RDADDRECC => S_AXI_RDADDRECC -- : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) -- new for v6.2
);
end generate FAMILY_SUPPORTED;
end implementation;
|
apache-2.0
|
bc2439171fdb1ddd36f8c09309dc53a3
| 0.347644 | 4.858424 | false | false | false | false |
aggroskater/ee4321-vhdl-digital-design
|
Project-4-4bit-ALU/lib/comparator/comparator.vhd
| 1 | 3,008 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--NOTE: the "diff" input comes from the output of the add_sub module.
--the way the opcodes are defined, the output is always the difference
--of A and B if the user is requesting a comparison operation. Otherwise,
--the output of this module will technically be undefined/wrong, but it
--doesn't matter because we won't be selecting it for the final output.
entity comparator is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
op : in STD_LOGIC_VECTOR (2 downto 0);
zero : in STD_LOGIC;
cout : in STD_LOGIC;
overflow : in STD_LOGIC;
diff : in STD_LOGIC_VECTOR (3 downto 0);
R : out STD_LOGIC
);
end comparator;
architecture Behavioral of comparator is
--signals
signal a_GEQ_b_SIGNED_R : std_logic:='0';
signal a_LE_b_SIGNED_R : std_logic:='0';
signal a_NEQ_b_UNSIGNED_R : std_logic:='0';
signal a_EQ_b_UNSIGNED_R : std_logic:='0';
signal a_GEQ_b_UNSIGNED_R : std_logic:='0';
signal a_LE_b_UNSIGNED_R : std_logic:='0';
signal s : std_logic_vector(3 downto 0);
begin
-------------------------------------------
--SIGNED PORTIONS
-------------------------------------------
--SIGNED is a bit more tricky. However, we can take
--advantage of the overflow flag and arrive at the
--following conclusions:
--(thanks to: http://teahlab.com/4-Bit_Signed_Comparator/)
-- X = Y <--> zero
-- X < Y <--> diff(3) XOR overflow
-- X > Y <--> !( zero OR ( diff(3) XOR overflow) )
--GEQ SIGNED
a_GEQ_b_SIGNED_R <= NOT(zero OR (diff(3) XOR overflow) ) OR zero;
--LE SIGNED
a_LE_b_SIGNED_R <= diff(3) XOR overflow;
-------------------------------------------
--UNSIGNED PORTIONS
-------------------------------------------
--EQ/NEQ
--well, *that* was easy :D
a_NEQ_b_UNSIGNED_R <= NOT(zero);
a_EQ_b_UNSIGNED_R <= zero;
--GEQ UNSIGNED
--Well, it turns out unsigned is harder. I'm way behind and
--so close to being done, so I'm borrowing some code from here
--to make sure the tests all work:
--http://sid-vlsiarena.blogspot.com/2013/03/4-bit-magnitude-comparator-vhdl-code.html
--I'll have to explain the karnaugh map theory behind it later in the report.
s(0)<= a(0) xnor b(0);
s(1)<= a(1) xnor b(1);
s(2)<= a(2) xnor b(2);
s(3)<= a(3) xnor b(3);
a_GEQ_b_UNSIGNED_R <= (a(3) and (not b(3)))
or (s(3) and a(2) and (not b(2)))
or (s(3) and s(2) and a(1)and (not b(1)))
or (s(3) and s(2) and s(1) and a(0) and (not b(0)))
or zero;
--LE UNSIGNED
a_LE_b_UNSIGNED_R <= (b(3) and (not a(3)))
or (s(3) and b(2) and (not a(2)))
or (s(3) and s(2) and b(1)and (not a(1)))
or (s(3) and s(2) and s(1) and b(0) and (not a(0)));
-------------------------------------------
--select output based on opcode
-------------------------------------------
output: entity work.mux8_bit port map (open, a_GEQ_b_SIGNED_R, a_LE_B_SIGNED_R,
a_NEQ_b_UNSIGNED_R, a_EQ_b_UNSIGNED_R, a_GEQ_b_UNSIGNED_R, a_LE_b_UNSIGNED_R,
open, op, R);
end Behavioral;
|
agpl-3.0
|
ce011a84f9ae3dadfee6809361a6a9d6
| 0.585106 | 2.923226 | false | false | false | false |
KPU-RISC/KPU
|
VHDL/RAM_Wrapper.vhd
| 1 | 2,660 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/12/2015 08:52:54 PM
-- Design Name:
-- Module Name: RAM_Wrapper - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RAM_Wrapper is
port
(
Clock: IN BIT;
Load: IN BIT;
Sel: IN BIT; -- Requests the data from the RAM
Ret: IN BIT; -- Returns the data from the RAM and places it onto the data bus
Address: IN BIT_VECTOR(15 DOWNTO 0);
Input: IN BIT_VECTOR(7 DOWNTO 0);
Output: OUT BIT_VECTOR(7 DOWNTO 0)
);
end RAM_Wrapper;
architecture Behavioral of RAM_Wrapper is
component RAM64K is
port (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end component RAM64K;
signal Load_Vector: STD_LOGIC_VECTOR(0 downto 0);
signal Output_Temp: STD_LOGIC_VECTOR(7 DOWNTO 0);
signal Output_Local: BIT_VECTOR(7 DOWNTO 0);
function TO_STD_LOGIC(L: BIT) return STD_LOGIC is
begin
if L = '1' then
return('1');
else
return('0');
end if;
end function To_Std_Logic;
begin
Load_Vector(0) <= TO_STD_LOGIC(Load);
Output_Local <= TO_BITVECTOR(Output_Temp);
-- We only return the output if the Select-Line is high
Output(0) <= Output_Local(0) and Sel and Ret;
Output(1) <= Output_Local(1) and Sel and Ret;
Output(2) <= Output_Local(2) and Sel and Ret;
Output(3) <= Output_Local(3) and Sel and Ret;
Output(4) <= Output_Local(4) and Sel and Ret;
Output(5) <= Output_Local(5) and Sel and Ret;
Output(6) <= Output_Local(6) and Sel and Ret;
Output(7) <= Output_Local(7) and Sel and Ret;
ram: RAM64K port map (
TO_STD_LOGIC(Clock),
TO_STD_LOGIC(Load or Sel),
Load_Vector,
To_StdLogicVector(Address),
To_StdLogicVector(Input),
Output_Temp);
end Behavioral;
|
mit
|
8cb612ba86bc00602c25283160792640
| 0.590977 | 3.619048 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_contrast_stretch_1_0/hdl/vhdl/AXIvideo2Mat.vhd
| 1 | 69,169 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity AXIvideo2Mat is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
start_full_n : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
start_out : OUT STD_LOGIC;
start_write : OUT STD_LOGIC;
stream_in_TDATA : IN STD_LOGIC_VECTOR (23 downto 0);
stream_in_TVALID : IN STD_LOGIC;
stream_in_TREADY : OUT STD_LOGIC;
stream_in_TKEEP : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TSTRB : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TID : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
img_rows_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
img_rows_V_empty_n : IN STD_LOGIC;
img_rows_V_read : OUT STD_LOGIC;
img_cols_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
img_cols_V_empty_n : IN STD_LOGIC;
img_cols_V_read : OUT STD_LOGIC;
img_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_full_n : IN STD_LOGIC;
img_data_stream_0_V_write : OUT STD_LOGIC;
img_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_full_n : IN STD_LOGIC;
img_data_stream_1_V_write : OUT STD_LOGIC;
img_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_full_n : IN STD_LOGIC;
img_data_stream_2_V_write : OUT STD_LOGIC;
img_rows_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img_rows_V_out_full_n : IN STD_LOGIC;
img_rows_V_out_write : OUT STD_LOGIC;
img_cols_V_out_din : OUT STD_LOGIC_VECTOR (15 downto 0);
img_cols_V_out_full_n : IN STD_LOGIC;
img_cols_V_out_write : OUT STD_LOGIC );
end;
architecture behav of AXIvideo2Mat is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (7 downto 0) := "00001000";
constant ap_ST_fsm_pp1_stage0 : STD_LOGIC_VECTOR (7 downto 0) := "00010000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (7 downto 0) := "00100000";
constant ap_ST_fsm_pp2_stage0 : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
signal real_start : STD_LOGIC;
signal start_once_reg : STD_LOGIC := '0';
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal internal_ap_ready : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_data_out : STD_LOGIC_VECTOR (23 downto 0);
signal AXI_video_strm_V_data_V_0_vld_in : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_vld_out : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_ack_in : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_ack_out : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_payload_A : STD_LOGIC_VECTOR (23 downto 0);
signal AXI_video_strm_V_data_V_0_payload_B : STD_LOGIC_VECTOR (23 downto 0);
signal AXI_video_strm_V_data_V_0_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_data_V_0_sel_wr : STD_LOGIC := '0';
signal AXI_video_strm_V_data_V_0_sel : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_load_A : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_load_B : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal AXI_video_strm_V_data_V_0_state_cmp_full : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_data_out : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_user_V_0_vld_in : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_vld_out : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_ack_in : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_ack_out : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_payload_A : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_user_V_0_payload_B : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_user_V_0_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_user_V_0_sel_wr : STD_LOGIC := '0';
signal AXI_video_strm_V_user_V_0_sel : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_load_A : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_load_B : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal AXI_video_strm_V_user_V_0_state_cmp_full : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_data_out : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_last_V_0_vld_in : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_vld_out : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_ack_in : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_ack_out : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_payload_A : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_last_V_0_payload_B : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_last_V_0_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_last_V_0_sel_wr : STD_LOGIC := '0';
signal AXI_video_strm_V_last_V_0_sel : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_load_A : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_load_B : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal AXI_video_strm_V_last_V_0_state_cmp_full : STD_LOGIC;
signal AXI_video_strm_V_dest_V_0_vld_in : STD_LOGIC;
signal AXI_video_strm_V_dest_V_0_ack_out : STD_LOGIC;
signal AXI_video_strm_V_dest_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal stream_in_TDATA_blk_n : STD_LOGIC;
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal ap_CS_fsm_pp1_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp1_stage0 : signal is "none";
signal ap_enable_reg_pp1_iter1 : STD_LOGIC := '0';
signal ap_block_pp1_stage0 : BOOLEAN;
signal exitcond_i_reg_442 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_reg_451 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp2_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp2_stage0 : signal is "none";
signal ap_enable_reg_pp2_iter1 : STD_LOGIC := '0';
signal ap_block_pp2_stage0 : BOOLEAN;
signal eol_2_i_reg_270 : STD_LOGIC_VECTOR (0 downto 0);
signal img_rows_V_blk_n : STD_LOGIC;
signal img_cols_V_blk_n : STD_LOGIC;
signal img_data_stream_0_V_blk_n : STD_LOGIC;
signal img_data_stream_1_V_blk_n : STD_LOGIC;
signal img_data_stream_2_V_blk_n : STD_LOGIC;
signal img_rows_V_out_blk_n : STD_LOGIC;
signal img_cols_V_out_blk_n : STD_LOGIC;
signal t_V_2_reg_200 : STD_LOGIC_VECTOR (10 downto 0);
signal eol_i_reg_211 : STD_LOGIC_VECTOR (0 downto 0);
signal eol_reg_223 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_data_V_1_i_reg_234 : STD_LOGIC_VECTOR (23 downto 0);
signal axi_last_V_3_i_reg_281 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_data_V_3_i_reg_293 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_fu_315_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_reg_403 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_block_state1 : BOOLEAN;
signal tmp_43_fu_319_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_43_reg_408 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_data_V_reg_413 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_last_V_reg_421 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond2_i_fu_336_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal i_V_fu_341_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal i_V_reg_437 : STD_LOGIC_VECTOR (10 downto 0);
signal exitcond_i_fu_351_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_state5_pp1_stage0_iter0 : BOOLEAN;
signal ap_predicate_op75_read_state6 : BOOLEAN;
signal ap_block_state6_pp1_stage0_iter1 : BOOLEAN;
signal ap_block_pp1_stage0_11001 : BOOLEAN;
signal j_V_fu_356_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_enable_reg_pp1_iter0 : STD_LOGIC := '0';
signal brmerge_i_fu_365_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_state8_pp2_stage0_iter0 : BOOLEAN;
signal ap_block_state9_pp2_stage0_iter1 : BOOLEAN;
signal ap_block_pp2_stage0_11001 : BOOLEAN;
signal ap_block_pp1_stage0_subdone : BOOLEAN;
signal ap_enable_reg_pp2_iter0 : STD_LOGIC := '0';
signal ap_CS_fsm_state7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal ap_block_pp2_stage0_subdone : BOOLEAN;
signal ap_phi_mux_eol_2_i_phi_fu_273_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_last_V1_i_reg_169 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none";
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal axi_data_V1_i_reg_179 : STD_LOGIC_VECTOR (23 downto 0);
signal t_V_reg_189 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_phi_mux_eol_i_phi_fu_215_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_mux_p_Val2_s_phi_fu_262_p4 : STD_LOGIC_VECTOR (23 downto 0);
signal ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_245 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp1_iter1_p_Val2_s_reg_258 : STD_LOGIC_VECTOR (23 downto 0);
signal ap_block_pp1_stage0_01001 : BOOLEAN;
signal sof_1_i_fu_98 : STD_LOGIC_VECTOR (0 downto 0);
signal t_V_cast_i_fu_332_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal t_V_3_cast_i_fu_347_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_user_V_fu_323_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (7 downto 0);
signal ap_idle_pp1 : STD_LOGIC;
signal ap_enable_pp1 : STD_LOGIC;
signal ap_idle_pp2 : STD_LOGIC;
signal ap_enable_pp2 : STD_LOGIC;
signal ap_condition_529 : BOOLEAN;
begin
AXI_video_strm_V_data_V_0_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_data_V_0_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out))) then
AXI_video_strm_V_data_V_0_sel_rd <= not(AXI_video_strm_V_data_V_0_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_data_V_0_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_data_V_0_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_in) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_in))) then
AXI_video_strm_V_data_V_0_sel_wr <= not(AXI_video_strm_V_data_V_0_sel_wr);
end if;
end if;
end if;
end process;
AXI_video_strm_V_data_V_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_data_V_0_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_out)))) then
AXI_video_strm_V_data_V_0_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_in)))) then
AXI_video_strm_V_data_V_0_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_data_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_data_V_0_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_in)))) then
AXI_video_strm_V_data_V_0_state <= ap_const_lv2_3;
else
AXI_video_strm_V_data_V_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
AXI_video_strm_V_dest_V_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_0_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_ack_out)))) then
AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_0_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_vld_in)))) then
AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_dest_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_dest_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_dest_V_0_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_vld_in)))) then
AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_3;
else
AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
AXI_video_strm_V_last_V_0_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_last_V_0_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_out))) then
AXI_video_strm_V_last_V_0_sel_rd <= not(AXI_video_strm_V_last_V_0_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_last_V_0_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_last_V_0_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_in) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_in))) then
AXI_video_strm_V_last_V_0_sel_wr <= not(AXI_video_strm_V_last_V_0_sel_wr);
end if;
end if;
end if;
end process;
AXI_video_strm_V_last_V_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_last_V_0_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_0_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_out)))) then
AXI_video_strm_V_last_V_0_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_0_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_in)))) then
AXI_video_strm_V_last_V_0_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_last_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_last_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_last_V_0_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_in)))) then
AXI_video_strm_V_last_V_0_state <= ap_const_lv2_3;
else
AXI_video_strm_V_last_V_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
AXI_video_strm_V_user_V_0_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_user_V_0_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_out))) then
AXI_video_strm_V_user_V_0_sel_rd <= not(AXI_video_strm_V_user_V_0_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_user_V_0_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_user_V_0_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_in) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_in))) then
AXI_video_strm_V_user_V_0_sel_wr <= not(AXI_video_strm_V_user_V_0_sel_wr);
end if;
end if;
end if;
end process;
AXI_video_strm_V_user_V_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_user_V_0_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_0_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_out)))) then
AXI_video_strm_V_user_V_0_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_0_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_in)))) then
AXI_video_strm_V_user_V_0_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_user_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_user_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_user_V_0_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_in)))) then
AXI_video_strm_V_user_V_0_state <= ap_const_lv2_3;
else
AXI_video_strm_V_user_V_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_continue = ap_const_logic_1)) then
ap_done_reg <= ap_const_logic_0;
elsif (((exitcond2_i_fu_336_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp1_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
else
if (((exitcond_i_fu_351_p2 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
elsif (((exitcond2_i_fu_336_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_enable_reg_pp1_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp1_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp1_iter1 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp1_stage0_subdone)) then
ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0;
elsif (((exitcond2_i_fu_336_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_enable_reg_pp1_iter1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_enable_reg_pp2_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp2_iter0 <= ap_const_logic_0;
else
if (((ap_phi_mux_eol_2_i_phi_fu_273_p4 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp2_stage0_subdone) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
ap_enable_reg_pp2_iter0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
ap_enable_reg_pp2_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp2_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp2_iter1 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp2_stage0_subdone)) then
ap_enable_reg_pp2_iter1 <= ap_enable_reg_pp2_iter0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
ap_enable_reg_pp2_iter1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
start_once_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
start_once_reg <= ap_const_logic_0;
else
if (((internal_ap_ready = ap_const_logic_0) and (real_start = ap_const_logic_1))) then
start_once_reg <= ap_const_logic_1;
elsif ((internal_ap_ready = ap_const_logic_1)) then
start_once_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
axi_data_V1_i_reg_179_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
axi_data_V1_i_reg_179 <= tmp_data_V_reg_413;
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
axi_data_V1_i_reg_179 <= axi_data_V_3_i_reg_293;
end if;
end if;
end process;
axi_data_V_1_i_reg_234_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_i_reg_442 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
axi_data_V_1_i_reg_234 <= ap_phi_mux_p_Val2_s_phi_fu_262_p4;
elsif (((exitcond2_i_fu_336_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
axi_data_V_1_i_reg_234 <= axi_data_V1_i_reg_179;
end if;
end if;
end process;
axi_data_V_3_i_reg_293_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
axi_data_V_3_i_reg_293 <= axi_data_V_1_i_reg_234;
elsif (((eol_2_i_reg_270 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
axi_data_V_3_i_reg_293 <= AXI_video_strm_V_data_V_0_data_out;
end if;
end if;
end process;
axi_last_V1_i_reg_169_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
axi_last_V1_i_reg_169 <= tmp_last_V_reg_421;
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
axi_last_V1_i_reg_169 <= axi_last_V_3_i_reg_281;
end if;
end if;
end process;
axi_last_V_3_i_reg_281_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
axi_last_V_3_i_reg_281 <= eol_reg_223;
elsif (((eol_2_i_reg_270 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
axi_last_V_3_i_reg_281 <= AXI_video_strm_V_last_V_0_data_out;
end if;
end if;
end process;
eol_2_i_reg_270_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
eol_2_i_reg_270 <= eol_i_reg_211;
elsif (((eol_2_i_reg_270 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
eol_2_i_reg_270 <= AXI_video_strm_V_last_V_0_data_out;
end if;
end if;
end process;
eol_i_reg_211_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_i_reg_442 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
eol_i_reg_211 <= ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4;
elsif (((exitcond2_i_fu_336_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
eol_i_reg_211 <= ap_const_lv1_0;
end if;
end if;
end process;
eol_reg_223_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_i_reg_442 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
eol_reg_223 <= ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4;
elsif (((exitcond2_i_fu_336_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
eol_reg_223 <= axi_last_V1_i_reg_169;
end if;
end if;
end process;
sof_1_i_fu_98_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_i_fu_351_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
sof_1_i_fu_98 <= ap_const_lv1_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
sof_1_i_fu_98 <= ap_const_lv1_1;
end if;
end if;
end process;
t_V_2_reg_200_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_i_fu_351_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
t_V_2_reg_200 <= j_V_fu_356_p2;
elsif (((exitcond2_i_fu_336_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
t_V_2_reg_200 <= ap_const_lv11_0;
end if;
end if;
end process;
t_V_reg_189_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
t_V_reg_189 <= ap_const_lv11_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
t_V_reg_189 <= i_V_reg_437;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_load_A)) then
AXI_video_strm_V_data_V_0_payload_A <= stream_in_TDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_load_B)) then
AXI_video_strm_V_data_V_0_payload_B <= stream_in_TDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_last_V_0_load_A)) then
AXI_video_strm_V_last_V_0_payload_A <= stream_in_TLAST;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_last_V_0_load_B)) then
AXI_video_strm_V_last_V_0_payload_B <= stream_in_TLAST;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_user_V_0_load_A)) then
AXI_video_strm_V_user_V_0_payload_A <= stream_in_TUSER;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_user_V_0_load_B)) then
AXI_video_strm_V_user_V_0_payload_B <= stream_in_TUSER;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_i_fu_351_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
brmerge_i_reg_451 <= brmerge_i_fu_365_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
exitcond_i_reg_442 <= exitcond_i_fu_351_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
i_V_reg_437 <= i_V_fu_341_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
tmp_43_reg_408 <= tmp_43_fu_319_p1;
tmp_reg_403 <= tmp_fu_315_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
tmp_data_V_reg_413 <= AXI_video_strm_V_data_V_0_data_out;
tmp_last_V_reg_421 <= AXI_video_strm_V_last_V_0_data_out;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (real_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, AXI_video_strm_V_data_V_0_vld_out, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, exitcond2_i_fu_336_p2, ap_CS_fsm_state4, ap_enable_reg_pp1_iter0, ap_block_pp1_stage0_subdone, ap_enable_reg_pp2_iter0, ap_block_pp2_stage0_subdone, tmp_user_V_fu_323_p1)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if ((not(((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((tmp_user_V_fu_323_p1 = ap_const_lv1_0) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_NS_fsm <= ap_ST_fsm_state2;
elsif (((tmp_user_V_fu_323_p1 = ap_const_lv1_1) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_NS_fsm <= ap_ST_fsm_state3;
else
ap_NS_fsm <= ap_ST_fsm_state2;
end if;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
if (((exitcond2_i_fu_336_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
end if;
when ap_ST_fsm_pp1_stage0 =>
if (not(((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (ap_enable_reg_pp1_iter0 = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0)))) then
ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
elsif (((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (ap_enable_reg_pp1_iter0 = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
ap_NS_fsm <= ap_ST_fsm_state7;
else
ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
end if;
when ap_ST_fsm_state7 =>
ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
when ap_ST_fsm_pp2_stage0 =>
if (not(((ap_const_boolean_0 = ap_block_pp2_stage0_subdone) and (ap_enable_reg_pp2_iter0 = ap_const_logic_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)))) then
ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
elsif (((ap_const_boolean_0 = ap_block_pp2_stage0_subdone) and (ap_enable_reg_pp2_iter0 = ap_const_logic_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
ap_NS_fsm <= ap_ST_fsm_state10;
else
ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
end if;
when ap_ST_fsm_state10 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when others =>
ap_NS_fsm <= "XXXXXXXX";
end case;
end process;
AXI_video_strm_V_data_V_0_ack_in <= AXI_video_strm_V_data_V_0_state(1);
AXI_video_strm_V_data_V_0_ack_out_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_i_reg_270, ap_predicate_op75_read_state6, ap_block_pp1_stage0_11001, ap_block_pp2_stage0_11001)
begin
if ((((eol_2_i_reg_270 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_predicate_op75_read_state6 = ap_const_boolean_1)) or ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2)))) then
AXI_video_strm_V_data_V_0_ack_out <= ap_const_logic_1;
else
AXI_video_strm_V_data_V_0_ack_out <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_data_V_0_data_out_assign_proc : process(AXI_video_strm_V_data_V_0_payload_A, AXI_video_strm_V_data_V_0_payload_B, AXI_video_strm_V_data_V_0_sel)
begin
if ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_sel)) then
AXI_video_strm_V_data_V_0_data_out <= AXI_video_strm_V_data_V_0_payload_B;
else
AXI_video_strm_V_data_V_0_data_out <= AXI_video_strm_V_data_V_0_payload_A;
end if;
end process;
AXI_video_strm_V_data_V_0_load_A <= (not(AXI_video_strm_V_data_V_0_sel_wr) and AXI_video_strm_V_data_V_0_state_cmp_full);
AXI_video_strm_V_data_V_0_load_B <= (AXI_video_strm_V_data_V_0_state_cmp_full and AXI_video_strm_V_data_V_0_sel_wr);
AXI_video_strm_V_data_V_0_sel <= AXI_video_strm_V_data_V_0_sel_rd;
AXI_video_strm_V_data_V_0_state_cmp_full <= '0' when (AXI_video_strm_V_data_V_0_state = ap_const_lv2_1) else '1';
AXI_video_strm_V_data_V_0_vld_in <= stream_in_TVALID;
AXI_video_strm_V_data_V_0_vld_out <= AXI_video_strm_V_data_V_0_state(0);
AXI_video_strm_V_dest_V_0_ack_out_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_i_reg_270, ap_predicate_op75_read_state6, ap_block_pp1_stage0_11001, ap_block_pp2_stage0_11001)
begin
if ((((eol_2_i_reg_270 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_predicate_op75_read_state6 = ap_const_boolean_1)) or ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2)))) then
AXI_video_strm_V_dest_V_0_ack_out <= ap_const_logic_1;
else
AXI_video_strm_V_dest_V_0_ack_out <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_dest_V_0_vld_in <= stream_in_TVALID;
AXI_video_strm_V_last_V_0_ack_in <= AXI_video_strm_V_last_V_0_state(1);
AXI_video_strm_V_last_V_0_ack_out_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_i_reg_270, ap_predicate_op75_read_state6, ap_block_pp1_stage0_11001, ap_block_pp2_stage0_11001)
begin
if ((((eol_2_i_reg_270 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_predicate_op75_read_state6 = ap_const_boolean_1)) or ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2)))) then
AXI_video_strm_V_last_V_0_ack_out <= ap_const_logic_1;
else
AXI_video_strm_V_last_V_0_ack_out <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_last_V_0_data_out_assign_proc : process(AXI_video_strm_V_last_V_0_payload_A, AXI_video_strm_V_last_V_0_payload_B, AXI_video_strm_V_last_V_0_sel)
begin
if ((ap_const_logic_1 = AXI_video_strm_V_last_V_0_sel)) then
AXI_video_strm_V_last_V_0_data_out <= AXI_video_strm_V_last_V_0_payload_B;
else
AXI_video_strm_V_last_V_0_data_out <= AXI_video_strm_V_last_V_0_payload_A;
end if;
end process;
AXI_video_strm_V_last_V_0_load_A <= (not(AXI_video_strm_V_last_V_0_sel_wr) and AXI_video_strm_V_last_V_0_state_cmp_full);
AXI_video_strm_V_last_V_0_load_B <= (AXI_video_strm_V_last_V_0_state_cmp_full and AXI_video_strm_V_last_V_0_sel_wr);
AXI_video_strm_V_last_V_0_sel <= AXI_video_strm_V_last_V_0_sel_rd;
AXI_video_strm_V_last_V_0_state_cmp_full <= '0' when (AXI_video_strm_V_last_V_0_state = ap_const_lv2_1) else '1';
AXI_video_strm_V_last_V_0_vld_in <= stream_in_TVALID;
AXI_video_strm_V_last_V_0_vld_out <= AXI_video_strm_V_last_V_0_state(0);
AXI_video_strm_V_user_V_0_ack_in <= AXI_video_strm_V_user_V_0_state(1);
AXI_video_strm_V_user_V_0_ack_out_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_i_reg_270, ap_predicate_op75_read_state6, ap_block_pp1_stage0_11001, ap_block_pp2_stage0_11001)
begin
if ((((eol_2_i_reg_270 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_predicate_op75_read_state6 = ap_const_boolean_1)) or ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2)))) then
AXI_video_strm_V_user_V_0_ack_out <= ap_const_logic_1;
else
AXI_video_strm_V_user_V_0_ack_out <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_user_V_0_data_out_assign_proc : process(AXI_video_strm_V_user_V_0_payload_A, AXI_video_strm_V_user_V_0_payload_B, AXI_video_strm_V_user_V_0_sel)
begin
if ((ap_const_logic_1 = AXI_video_strm_V_user_V_0_sel)) then
AXI_video_strm_V_user_V_0_data_out <= AXI_video_strm_V_user_V_0_payload_B;
else
AXI_video_strm_V_user_V_0_data_out <= AXI_video_strm_V_user_V_0_payload_A;
end if;
end process;
AXI_video_strm_V_user_V_0_load_A <= (not(AXI_video_strm_V_user_V_0_sel_wr) and AXI_video_strm_V_user_V_0_state_cmp_full);
AXI_video_strm_V_user_V_0_load_B <= (AXI_video_strm_V_user_V_0_state_cmp_full and AXI_video_strm_V_user_V_0_sel_wr);
AXI_video_strm_V_user_V_0_sel <= AXI_video_strm_V_user_V_0_sel_rd;
AXI_video_strm_V_user_V_0_state_cmp_full <= '0' when (AXI_video_strm_V_user_V_0_state = ap_const_lv2_1) else '1';
AXI_video_strm_V_user_V_0_vld_in <= stream_in_TVALID;
AXI_video_strm_V_user_V_0_vld_out <= AXI_video_strm_V_user_V_0_state(0);
ap_CS_fsm_pp1_stage0 <= ap_CS_fsm(4);
ap_CS_fsm_pp2_stage0 <= ap_CS_fsm(6);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state10 <= ap_CS_fsm(7);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state7 <= ap_CS_fsm(5);
ap_block_pp1_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp1_stage0_01001_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, ap_enable_reg_pp1_iter1, exitcond_i_reg_442, ap_predicate_op75_read_state6)
begin
ap_block_pp1_stage0_01001 <= ((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_predicate_op75_read_state6 = ap_const_boolean_1)) or ((exitcond_i_reg_442 = ap_const_lv1_0) and (img_data_stream_2_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_442 = ap_const_lv1_0) and (img_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_442 = ap_const_lv1_0) and (img_data_stream_0_V_full_n = ap_const_logic_0))));
end process;
ap_block_pp1_stage0_11001_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, ap_enable_reg_pp1_iter1, exitcond_i_reg_442, ap_predicate_op75_read_state6)
begin
ap_block_pp1_stage0_11001 <= ((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_predicate_op75_read_state6 = ap_const_boolean_1)) or ((exitcond_i_reg_442 = ap_const_lv1_0) and (img_data_stream_2_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_442 = ap_const_lv1_0) and (img_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_442 = ap_const_lv1_0) and (img_data_stream_0_V_full_n = ap_const_logic_0))));
end process;
ap_block_pp1_stage0_subdone_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, ap_enable_reg_pp1_iter1, exitcond_i_reg_442, ap_predicate_op75_read_state6)
begin
ap_block_pp1_stage0_subdone <= ((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_predicate_op75_read_state6 = ap_const_boolean_1)) or ((exitcond_i_reg_442 = ap_const_lv1_0) and (img_data_stream_2_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_442 = ap_const_lv1_0) and (img_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_442 = ap_const_lv1_0) and (img_data_stream_0_V_full_n = ap_const_logic_0))));
end process;
ap_block_pp2_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp2_stage0_11001_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_enable_reg_pp2_iter1, eol_2_i_reg_270)
begin
ap_block_pp2_stage0_11001 <= ((eol_2_i_reg_270 = ap_const_lv1_0) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1));
end process;
ap_block_pp2_stage0_subdone_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_enable_reg_pp2_iter1, eol_2_i_reg_270)
begin
ap_block_pp2_stage0_subdone <= ((eol_2_i_reg_270 = ap_const_lv1_0) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1));
end process;
ap_block_state1_assign_proc : process(real_start, ap_done_reg, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n)
begin
ap_block_state1 <= ((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
ap_block_state5_pp1_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp1_stage0_iter1_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, exitcond_i_reg_442, ap_predicate_op75_read_state6)
begin
ap_block_state6_pp1_stage0_iter1 <= (((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_predicate_op75_read_state6 = ap_const_boolean_1)) or ((exitcond_i_reg_442 = ap_const_lv1_0) and (img_data_stream_2_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_442 = ap_const_lv1_0) and (img_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_442 = ap_const_lv1_0) and (img_data_stream_0_V_full_n = ap_const_logic_0)));
end process;
ap_block_state8_pp2_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp2_stage0_iter1_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, eol_2_i_reg_270)
begin
ap_block_state9_pp2_stage0_iter1 <= ((eol_2_i_reg_270 = ap_const_lv1_0) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out));
end process;
ap_condition_529_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_i_reg_442)
begin
ap_condition_529 <= ((exitcond_i_reg_442 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0));
end process;
ap_done_assign_proc : process(ap_done_reg, exitcond2_i_fu_336_p2, ap_CS_fsm_state4)
begin
if (((exitcond2_i_fu_336_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_enable_pp1 <= (ap_idle_pp1 xor ap_const_logic_1);
ap_enable_pp2 <= (ap_idle_pp2 xor ap_const_logic_1);
ap_idle_assign_proc : process(real_start, ap_CS_fsm_state1)
begin
if (((real_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp1_assign_proc : process(ap_enable_reg_pp1_iter1, ap_enable_reg_pp1_iter0)
begin
if (((ap_enable_reg_pp1_iter0 = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0))) then
ap_idle_pp1 <= ap_const_logic_1;
else
ap_idle_pp1 <= ap_const_logic_0;
end if;
end process;
ap_idle_pp2_assign_proc : process(ap_enable_reg_pp2_iter1, ap_enable_reg_pp2_iter0)
begin
if (((ap_enable_reg_pp2_iter0 = ap_const_logic_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_0))) then
ap_idle_pp2 <= ap_const_logic_1;
else
ap_idle_pp2 <= ap_const_logic_0;
end if;
end process;
ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4_assign_proc : process(AXI_video_strm_V_last_V_0_data_out, brmerge_i_reg_451, eol_reg_223, ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_245, ap_condition_529)
begin
if ((ap_const_boolean_1 = ap_condition_529)) then
if ((brmerge_i_reg_451 = ap_const_lv1_1)) then
ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4 <= eol_reg_223;
elsif ((brmerge_i_reg_451 = ap_const_lv1_0)) then
ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4 <= AXI_video_strm_V_last_V_0_data_out;
else
ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4 <= ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_245;
end if;
else
ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4 <= ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_245;
end if;
end process;
ap_phi_mux_eol_2_i_phi_fu_273_p4_assign_proc : process(AXI_video_strm_V_last_V_0_data_out, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, eol_2_i_reg_270)
begin
if (((eol_2_i_reg_270 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
ap_phi_mux_eol_2_i_phi_fu_273_p4 <= AXI_video_strm_V_last_V_0_data_out;
else
ap_phi_mux_eol_2_i_phi_fu_273_p4 <= eol_2_i_reg_270;
end if;
end process;
ap_phi_mux_eol_i_phi_fu_215_p4_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_i_reg_442, eol_i_reg_211, ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4)
begin
if (((exitcond_i_reg_442 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
ap_phi_mux_eol_i_phi_fu_215_p4 <= ap_phi_mux_axi_last_V_2_i_phi_fu_250_p4;
else
ap_phi_mux_eol_i_phi_fu_215_p4 <= eol_i_reg_211;
end if;
end process;
ap_phi_mux_p_Val2_s_phi_fu_262_p4_assign_proc : process(AXI_video_strm_V_data_V_0_data_out, brmerge_i_reg_451, axi_data_V_1_i_reg_234, ap_phi_reg_pp1_iter1_p_Val2_s_reg_258, ap_condition_529)
begin
if ((ap_const_boolean_1 = ap_condition_529)) then
if ((brmerge_i_reg_451 = ap_const_lv1_1)) then
ap_phi_mux_p_Val2_s_phi_fu_262_p4 <= axi_data_V_1_i_reg_234;
elsif ((brmerge_i_reg_451 = ap_const_lv1_0)) then
ap_phi_mux_p_Val2_s_phi_fu_262_p4 <= AXI_video_strm_V_data_V_0_data_out;
else
ap_phi_mux_p_Val2_s_phi_fu_262_p4 <= ap_phi_reg_pp1_iter1_p_Val2_s_reg_258;
end if;
else
ap_phi_mux_p_Val2_s_phi_fu_262_p4 <= ap_phi_reg_pp1_iter1_p_Val2_s_reg_258;
end if;
end process;
ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_245 <= "X";
ap_phi_reg_pp1_iter1_p_Val2_s_reg_258 <= "XXXXXXXXXXXXXXXXXXXXXXXX";
ap_predicate_op75_read_state6_assign_proc : process(exitcond_i_reg_442, brmerge_i_reg_451)
begin
ap_predicate_op75_read_state6 <= ((brmerge_i_reg_451 = ap_const_lv1_0) and (exitcond_i_reg_442 = ap_const_lv1_0));
end process;
ap_ready <= internal_ap_ready;
brmerge_i_fu_365_p2 <= (sof_1_i_fu_98 or ap_phi_mux_eol_i_phi_fu_215_p4);
exitcond2_i_fu_336_p2 <= "1" when (t_V_cast_i_fu_332_p1 = tmp_reg_403) else "0";
exitcond_i_fu_351_p2 <= "1" when (t_V_3_cast_i_fu_347_p1 = tmp_43_reg_408) else "0";
i_V_fu_341_p2 <= std_logic_vector(unsigned(t_V_reg_189) + unsigned(ap_const_lv11_1));
img_cols_V_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_cols_V_empty_n)
begin
if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_cols_V_blk_n <= img_cols_V_empty_n;
else
img_cols_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_cols_V_out_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_cols_V_out_full_n)
begin
if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_cols_V_out_blk_n <= img_cols_V_out_full_n;
else
img_cols_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img_cols_V_out_din <= img_cols_V_dout;
img_cols_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n)
begin
if ((not(((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_cols_V_out_write <= ap_const_logic_1;
else
img_cols_V_out_write <= ap_const_logic_0;
end if;
end process;
img_cols_V_read_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n)
begin
if ((not(((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_cols_V_read <= ap_const_logic_1;
else
img_cols_V_read <= ap_const_logic_0;
end if;
end process;
img_data_stream_0_V_blk_n_assign_proc : process(img_data_stream_0_V_full_n, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_i_reg_442)
begin
if (((exitcond_i_reg_442 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_0_V_blk_n <= img_data_stream_0_V_full_n;
else
img_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_data_stream_0_V_din <= ap_phi_mux_p_Val2_s_phi_fu_262_p4(8 - 1 downto 0);
img_data_stream_0_V_write_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, exitcond_i_reg_442, ap_block_pp1_stage0_11001)
begin
if (((exitcond_i_reg_442 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_0_V_write <= ap_const_logic_1;
else
img_data_stream_0_V_write <= ap_const_logic_0;
end if;
end process;
img_data_stream_1_V_blk_n_assign_proc : process(img_data_stream_1_V_full_n, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_i_reg_442)
begin
if (((exitcond_i_reg_442 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_1_V_blk_n <= img_data_stream_1_V_full_n;
else
img_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_data_stream_1_V_din <= ap_phi_mux_p_Val2_s_phi_fu_262_p4(15 downto 8);
img_data_stream_1_V_write_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, exitcond_i_reg_442, ap_block_pp1_stage0_11001)
begin
if (((exitcond_i_reg_442 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_1_V_write <= ap_const_logic_1;
else
img_data_stream_1_V_write <= ap_const_logic_0;
end if;
end process;
img_data_stream_2_V_blk_n_assign_proc : process(img_data_stream_2_V_full_n, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_i_reg_442)
begin
if (((exitcond_i_reg_442 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_2_V_blk_n <= img_data_stream_2_V_full_n;
else
img_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_data_stream_2_V_din <= ap_phi_mux_p_Val2_s_phi_fu_262_p4(23 downto 16);
img_data_stream_2_V_write_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, exitcond_i_reg_442, ap_block_pp1_stage0_11001)
begin
if (((exitcond_i_reg_442 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_2_V_write <= ap_const_logic_1;
else
img_data_stream_2_V_write <= ap_const_logic_0;
end if;
end process;
img_rows_V_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n)
begin
if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_rows_V_blk_n <= img_rows_V_empty_n;
else
img_rows_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_rows_V_out_blk_n_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_out_full_n)
begin
if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_rows_V_out_blk_n <= img_rows_V_out_full_n;
else
img_rows_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img_rows_V_out_din <= img_rows_V_dout;
img_rows_V_out_write_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n)
begin
if ((not(((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_rows_V_out_write <= ap_const_logic_1;
else
img_rows_V_out_write <= ap_const_logic_0;
end if;
end process;
img_rows_V_read_assign_proc : process(real_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n)
begin
if ((not(((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_rows_V_read <= ap_const_logic_1;
else
img_rows_V_read <= ap_const_logic_0;
end if;
end process;
internal_ap_ready_assign_proc : process(exitcond2_i_fu_336_p2, ap_CS_fsm_state4)
begin
if (((exitcond2_i_fu_336_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
internal_ap_ready <= ap_const_logic_1;
else
internal_ap_ready <= ap_const_logic_0;
end if;
end process;
j_V_fu_356_p2 <= std_logic_vector(unsigned(t_V_2_reg_200) + unsigned(ap_const_lv11_1));
real_start_assign_proc : process(ap_start, start_full_n, start_once_reg)
begin
if (((start_once_reg = ap_const_logic_0) and (start_full_n = ap_const_logic_0))) then
real_start <= ap_const_logic_0;
else
real_start <= ap_start;
end if;
end process;
start_out <= real_start;
start_write_assign_proc : process(real_start, start_once_reg)
begin
if (((start_once_reg = ap_const_logic_0) and (real_start = ap_const_logic_1))) then
start_write <= ap_const_logic_1;
else
start_write <= ap_const_logic_0;
end if;
end process;
stream_in_TDATA_blk_n_assign_proc : process(AXI_video_strm_V_data_V_0_state, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_i_reg_442, brmerge_i_reg_451, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, eol_2_i_reg_270)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) or ((eol_2_i_reg_270 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((brmerge_i_reg_451 = ap_const_lv1_0) and (exitcond_i_reg_442 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0)))) then
stream_in_TDATA_blk_n <= AXI_video_strm_V_data_V_0_state(0);
else
stream_in_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
stream_in_TREADY <= AXI_video_strm_V_dest_V_0_state(1);
t_V_3_cast_i_fu_347_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(t_V_2_reg_200),12));
t_V_cast_i_fu_332_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(t_V_reg_189),12));
tmp_43_fu_319_p1 <= img_cols_V_dout(12 - 1 downto 0);
tmp_fu_315_p1 <= img_rows_V_dout(12 - 1 downto 0);
tmp_user_V_fu_323_p1 <= AXI_video_strm_V_user_V_0_data_out;
end behav;
|
mit
|
8477b1fe805f31b5361251edc8584c4c
| 0.600558 | 2.607789 | false | false | false | false |
SLongofono/digital-design-final-project
|
driver.vhd
| 1 | 3,624 |
----------------------------------------------------------------------------------
-- Engineer: Longofono
-- Create Date: 04/28/2017 07:18:38 PM
-- Description: Mockup to stitch modules together for testing
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee. std_logic_unsigned.all;
entity driver is
port(
clk, rst: in std_logic;
hsync : out std_logic;
vsync : out std_logic;
red : out std_logic_vector (3 downto 0);
blue : out std_logic_vector (3 downto 0);
green : out std_logic_vector (3 downto 0);
new_color : in std_logic_vector(11 downto 0);
hw_in_up, hw_in_down, hw_in_left, hw_in_right, hw_in_cent : in std_logic;
SCLK : out std_logic;
MOSI : out std_logic;
MISO : in std_logic;
SS : out std_logic;
activity : out std_logic
);
end driver;
architecture Behavioral of driver is
component vga_ctrl is
port(
clk : in std_logic;
rst : in std_logic;
VGA_HS_O : out std_logic;
VGA_VS_O : out std_logic;
VGA_RED_O : out std_logic_vector (3 downto 0);
VGA_BLUE_O : out std_logic_vector (3 downto 0);
VGA_GREEN_O : out std_logic_vector (3 downto 0);
new_color : in std_logic_vector(11 downto 0);
address : in integer;
draw_enable : in std_logic
);
end component;
component accel is
generic( system_freq : integer := 100000000; -- System clock speed
serial_freq : integer := 1000000; -- SPI clock speed
average_window : integer := 16; -- Average this many samples
update_frequency : integer := 100); -- Update at this rate
port( clk, rst : in std_logic;
shaking : out std_logic; -- Output to upstream
SCLK : out std_logic; -- SPI clock
MOSI : out std_logic; -- SPI Master output
MISO : in std_logic; -- SPI Master input
SS : out std_logic); -- SPI Slave select
end component;
component controller is
PORT(
clk : in std_logic;
rst : in std_logic;
btn_up : in std_logic;
btn_down : in std_logic;
btn_left : in std_logic;
btn_right : in std_logic;
btn_mode_switch : in std_logic;
addr : out integer;
en_write : out std_logic);
end component;
constant FRAME_WIDTH : natural := 640;
constant FRAME_HEIGHT : natural := 480;
-- VGA interface
signal s_vsync, s_hsync : std_logic;
signal s_red, s_green, s_blue : std_logic_vector(3 downto 0);
signal s_x : integer := 320;
signal s_y : integer := 240;
signal s_color : std_logic_vector(11 downto 0);
-- Button controller interface
signal draw_enable : std_logic;
signal s_addr: integer := 153600;
-- Accelerometer interface
signal shaking : std_logic;
begin
activity <= draw_enable;
VGA_unit: VGA_ctrl port map(
clk => clk,
rst => shaking,
VGA_HS_O => hsync,
VGA_VS_O => vsync,
VGA_RED_O => red,
VGA_BLUE_O => blue,
VGA_GREEN_O => green,
new_color => new_color,
address => s_addr,
draw_enable => draw_enable
);
Ctrl: controller port map(
clk => clk,
rst => rst,
btn_up => hw_in_up,
btn_down => hw_in_down,
btn_left => hw_in_left,
btn_right => hw_in_right,
btn_mode_switch => hw_in_cent,
addr => s_addr,
en_write => draw_enable); -- draw enable
ACC : accel port map(
clk => clk,
rst => rst,
shaking => shaking,
SCLK => SCLK,
MOSI => MOSI,
MISO => MISO,
SS => SS
);
end Behavioral;
|
mit
|
1439281a29f79ad46071bce44fa7022b
| 0.560982 | 3.435071 | false | false | false | false |
grafi-tt/Maizul
|
src/Unit/FPU/FInv.vhd
| 1 | 3,090 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FInv is
port (
clk : in std_logic;
flt_in : in std_logic_vector(31 downto 0);
flt_out : out std_logic_vector(31 downto 0));
end FInv;
architecture twoproc_pipeline of FInv is
component FInvTable is
port (
clk : in std_logic;
k : in std_logic_vector(9 downto 0);
v : out std_logic_vector(35 downto 0) := (others => '0'));
end component;
signal k : std_logic_vector(9 downto 0) := (others => '0');
signal v : std_logic_vector(35 downto 0);
signal rest : unsigned(12 downto 0) := (others => '0');
signal sgn, sgn_p : std_logic := '0';
signal exp_in, exp_in_p : unsigned(7 downto 0) := (others => '0');
signal a0, a0_p : unsigned(22 downto 0) := (others => '0');
signal t1, t1_p : unsigned(22 downto 0) := (others => '0');
signal no_flow1, no_flow1_p, no_flow2, no_flow2_p, frc_any, frc_any_p : std_logic := '0';
begin
conbinatorial1 : process(flt_in)
begin
k <= flt_in(22 downto 13);
end process;
table_map : FInvTable port map (clk => clk, k => k, v => v);
sequential2 : process(clk)
begin
if rising_edge(clk) then
sgn <= flt_in(31);
exp_in <= unsigned(flt_in(30 downto 23));
rest <= unsigned(flt_in(12 downto 0));
if unsigned(flt_in(22 downto 0)) = 0 then
frc_any <= '0';
else
frc_any <= '1';
end if;
end if;
end process;
conbinatorial2 : process(v, exp_in, rest)
variable a1 : unsigned(12 downto 0);
variable tmp : unsigned(25 downto 0);
begin
a0 <= unsigned(v(35 downto 13));
a1 := unsigned(v(12 downto 0));
if exp_in = x"FD" then
no_flow1 <= '0';
else
no_flow1 <= '1';
end if;
if exp_in = x"FE" then
no_flow2 <= '0';
else
no_flow2 <= '1';
end if;
tmp := a1 * rest;
t1 <= "000000000" & tmp(25 downto 12);
end process;
sequential3 : process(clk)
begin
if rising_edge(clk) then
no_flow1_p <= no_flow1;
no_flow2_p <= no_flow2;
frc_any_p <= frc_any;
exp_in_p <= exp_in;
sgn_p <= sgn;
a0_p <= a0;
t1_p <= t1;
end if;
end process;
conbinatorial3 : process(no_flow1_p, no_flow2_p, frc_any_p, exp_in_p, sgn_p, a0_p, t1_p)
variable exp_out : unsigned(7 downto 0);
variable frc_out : unsigned(22 downto 0);
begin
if exp_in_p = x"00" then
exp_out := x"FF";
else
exp_out := x"FE" - exp_in_p - unsigned'(0 => (frc_any_p and no_flow2_p));
end if;
if (frc_any_p and no_flow1_p and no_flow2_p) = '1' then
frc_out := a0_p - t1_p;
else
frc_out := (others => '0');
end if;
flt_out <= std_logic_vector(sgn_p & exp_out & frc_out);
end process;
end twoproc_pipeline;
|
bsd-2-clause
|
7c4bde71e1048e2eec4ac29809689e8a
| 0.509709 | 3.179012 | false | false | false | false |
rickyzhangNYC/Pipelined_Multimedia_Cell_Lite_Unit
|
register_file_operations.vhd
| 1 | 3,552 |
-------------------------------------------------------------------------------
--
-- Title : register_file_operations
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\register_file_operations.vhd
-- Generated : Wed Dec 7 03:45:40 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {register_file_operations} architecture {behavioral}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
entity register_file_operations is
port (
clk : std_logic; --clk
rs1_addr, rs2_addr : in std_logic_vector(3 downto 0); --register addressing
rs1, rs2: out std_logic_vector(63 downto 0); --data registers
rd: in std_logic_vector(63 downto 0); --data registers
load_data : in std_logic_vector(11 downto 4); --8 bit immediate
load_addr, rd_address_writeback : in std_logic_vector(3 downto 0); --addressing for load and writeback
load_enable, writeback : in std_logic; --enables
reg_port0, reg_port1, reg_port2, reg_port3, reg_port4, reg_port5, reg_port6, reg_port7, reg_port8, reg_port9,
reg_port10, reg_port11, reg_port12, reg_port13, reg_port14, reg_port15: out std_logic_vector(63 downto 0)
);
end register_file_operations;
architecture behavioral of register_file_operations is
type registers is array (0 to 15) of std_logic_vector(63 downto 0);
begin
process(rs1, rs2, load_data, rd, load_addr, rd_address_writeback, load_enable, writeback, clk)
variable registers_updated : registers;
variable load_data_64bit: std_logic_vector(63 downto 0);
begin
load_data_64bit(63 downto 56) := load_data;
load_data_64bit(55 downto 48) := load_data;
load_data_64bit(47 downto 40) := load_data;
load_data_64bit(39 downto 32) := load_data;
load_data_64bit(31 downto 24) := load_data;
load_data_64bit(23 downto 16) := load_data;
load_data_64bit(15 downto 8) := load_data;
load_data_64bit(7 downto 0) := load_data;
rs1 <= registers_updated(to_integer(unsigned(rs1_addr)));
rs2 <= registers_updated(to_integer(unsigned(rs2_addr)));
if rising_edge(clk) then
if load_enable = '1' then
registers_updated(to_integer(unsigned(load_addr))) := load_data_64bit;
end if;
if writeback = '1' then
registers_updated(to_integer(unsigned(rd_address_writeback))) := rd;
end if;
end if;
reg_port0 <= registers_updated(0);
reg_port1 <= registers_updated(1);
reg_port2 <= registers_updated(2);
reg_port3 <= registers_updated(3);
reg_port4 <= registers_updated(4);
reg_port5 <= registers_updated(5);
reg_port6 <= registers_updated(6);
reg_port7 <= registers_updated(7);
reg_port8 <= registers_updated(8);
reg_port9 <= registers_updated(9);
reg_port10 <= registers_updated(10);
reg_port11 <= registers_updated(11);
reg_port12 <= registers_updated(12);
reg_port13 <= registers_updated(13);
reg_port14 <= registers_updated(14);
reg_port15 <= registers_updated(15);
end process;
end behavioral;
|
apache-2.0
|
427e1d99ba8a2f709b37e6c232348a34
| 0.596002 | 3.341486 | false | false | false | false |
Digilent/vivado-library
|
module/synchronizers/example/top.vhd
| 1 | 5,827 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/03/2022 05:43:57 PM
-- Design Name:
-- Module Name: top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library xpm;
use xpm.vcomponents.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top is
Port ( OneClk : in STD_LOGIC;
TwoClk : in STD_LOGIC;
aSignal : in STD_LOGIC;
atRstPos : out STD_LOGIC;
atRstNeg : out STD_LOGIC;
atRstXPMPos : out STD_LOGIC;
atRstXPMNeg : out STD_LOGIC;
tSignal : out STD_LOGIC;
tSignalHs : out STD_LOGIC;
oPush : in STD_LOGIC;
oRdy : out STD_LOGIC;
tValid : out STD_LOGIC);
end top;
architecture Behavioral of top is
signal aoRst, oSignal, oSignalXPM, aoRstPos, atRstPos_int : std_logic;
signal oSignalVect : std_logic_vector(0 downto 0);
signal tSignalVect : std_logic_vector(0 downto 0);
begin
oSignalVect(0) <= oSignal;
tSignalHs <= tSignalVect(0);
SyncAsync1: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 3) --use double FF synchronizer
port map (
aoReset => aoRstPos,
aIn => aSignal,
OutClk => OneClk,
oOut => oSignal);
SyncBase: entity work.SyncBase
generic map (
kResetTo => '0',
kStages => 3) --use double FF synchronizer
port map (
aiReset => '0',
InClk => OneClk,
iIn => oSignal,
aoReset => '0',
OutClk => TwoClk,
oOut => tSignal);
ResetBridgePos: entity work.ResetBridge
Generic map (
kPolarity => '1')
Port map (
aRst => oSignal,
OutClk => TwoClk,
aoRst => atRstPos_int
);
atRstPos <= atRstPos_int;
ResetBridgeBack: entity work.ResetBridge
Generic map (
kPolarity => '1')
Port map (
aRst => atRstPos_int,
OutClk => OneClk,
aoRst => aoRstPos
);
ResetBridgeNeg: entity work.ResetBridge
Generic map (
kPolarity => '0')
Port map (
aRst => oSignal,
OutClk => TwoClk,
aoRst => atRstNeg
);
HandshakeData: entity work.HandshakeData
Generic map(
kDataWidth => 1)
Port map(
InClk => OneClk,
OutClk => TwoClk,
iData => oSignalVect,
oData => tSignalVect,
iPush => oPush,
iRdy => oRdy,
oValid => tValid,
aiReset => '0',
aoReset => '0'
);
-- <-----Cut code below this line and paste into the architecture body---->
-- xpm_cdc_async_rst: Asynchronous Reset Synchronizer
-- Xilinx Parameterized Macro, version 2021.1
-- xpm_cdc_async_rst_pos : xpm_cdc_async_rst
-- generic map (
-- DEST_SYNC_FF => 2, -- DECIMAL; range: 2-10
-- INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
-- RST_ACTIVE_HIGH => 1 -- DECIMAL; 0=active low reset, 1=active high reset
-- )
-- port map (
-- dest_arst => atRstXPMPos, -- 1-bit output: src_arst asynchronous reset signal synchronized to destination
-- -- clock domain. This output is registered. NOTE: Signal asserts asynchronously
-- -- but deasserts synchronously to dest_clk. Width of the reset signal is at least
-- -- (DEST_SYNC_FF*dest_clk) period.
-- dest_clk => TwoClk, -- 1-bit input: Destination clock.
-- src_arst => oSignal -- 1-bit input: Source asynchronous reset signal.
-- );
-- xpm_cdc_async_rst_neg : xpm_cdc_async_rst
-- generic map (
-- DEST_SYNC_FF => 2, -- DECIMAL; range: 2-10
-- INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
-- RST_ACTIVE_HIGH => 0 -- DECIMAL; 0=active low reset, 1=active high reset
-- )
-- port map (
-- dest_arst => atRstXPMNeg, -- 1-bit output: src_arst asynchronous reset signal synchronized to destination
-- -- clock domain. This output is registered. NOTE: Signal asserts asynchronously
-- -- but deasserts synchronously to dest_clk. Width of the reset signal is at least
-- -- (DEST_SYNC_FF*dest_clk) period.
-- dest_clk => TwoClk, -- 1-bit input: Destination clock.
-- src_arst => oSignal -- 1-bit input: Source asynchronous reset signal.
-- );
-- xpm_cdc_single_inst : xpm_cdc_single
-- generic map (
-- DEST_SYNC_FF => 2, -- DECIMAL; range: 2-10
-- INIT_SYNC_FF => 0, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
-- SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
-- SRC_INPUT_REG => 0 -- DECIMAL; 0=do not register input, 1=register input
-- )
-- port map (
-- dest_out => oSignalXPM, -- 1-bit output: src_in synchronized to the destination clock domain. This output
-- -- is registered.
-- dest_clk => OneClk, -- 1-bit input: Clock signal for the destination clock domain.
-- src_clk => '1', -- 1-bit input: optional; required when SRC_INPUT_REG = 1
-- src_in => aSignal -- 1-bit input: Input signal to be synchronized to dest_clk domain.
-- );
end Behavioral;
|
mit
|
3753b652ae2196cce897e7b338dcc950
| 0.584005 | 3.871761 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/Mat2AXIvideo.vhd
| 3 | 67,208 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Mat2AXIvideo is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
img_rows_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
img_rows_V_empty_n : IN STD_LOGIC;
img_rows_V_read : OUT STD_LOGIC;
img_cols_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
img_cols_V_empty_n : IN STD_LOGIC;
img_cols_V_read : OUT STD_LOGIC;
img_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_empty_n : IN STD_LOGIC;
img_data_stream_0_V_read : OUT STD_LOGIC;
img_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_empty_n : IN STD_LOGIC;
img_data_stream_1_V_read : OUT STD_LOGIC;
img_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_empty_n : IN STD_LOGIC;
img_data_stream_2_V_read : OUT STD_LOGIC;
stream_out_TDATA : OUT STD_LOGIC_VECTOR (23 downto 0);
stream_out_TVALID : OUT STD_LOGIC;
stream_out_TREADY : IN STD_LOGIC;
stream_out_TKEEP : OUT STD_LOGIC_VECTOR (2 downto 0);
stream_out_TSTRB : OUT STD_LOGIC_VECTOR (2 downto 0);
stream_out_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0) );
end;
architecture behav of Mat2AXIvideo is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv3_7 : STD_LOGIC_VECTOR (2 downto 0) := "111";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv12_FFF : STD_LOGIC_VECTOR (11 downto 0) := "111111111111";
constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal AXI_video_strm_V_data_V_1_data_out : STD_LOGIC_VECTOR (23 downto 0);
signal AXI_video_strm_V_data_V_1_vld_in : STD_LOGIC;
signal AXI_video_strm_V_data_V_1_vld_out : STD_LOGIC;
signal AXI_video_strm_V_data_V_1_ack_in : STD_LOGIC;
signal AXI_video_strm_V_data_V_1_ack_out : STD_LOGIC;
signal AXI_video_strm_V_data_V_1_payload_A : STD_LOGIC_VECTOR (23 downto 0);
signal AXI_video_strm_V_data_V_1_payload_B : STD_LOGIC_VECTOR (23 downto 0);
signal AXI_video_strm_V_data_V_1_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_data_V_1_sel_wr : STD_LOGIC := '0';
signal AXI_video_strm_V_data_V_1_sel : STD_LOGIC;
signal AXI_video_strm_V_data_V_1_load_A : STD_LOGIC;
signal AXI_video_strm_V_data_V_1_load_B : STD_LOGIC;
signal AXI_video_strm_V_data_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal AXI_video_strm_V_data_V_1_state_cmp_full : STD_LOGIC;
signal AXI_video_strm_V_keep_V_1_data_out : STD_LOGIC_VECTOR (2 downto 0);
signal AXI_video_strm_V_keep_V_1_vld_in : STD_LOGIC;
signal AXI_video_strm_V_keep_V_1_vld_out : STD_LOGIC;
signal AXI_video_strm_V_keep_V_1_ack_in : STD_LOGIC;
signal AXI_video_strm_V_keep_V_1_ack_out : STD_LOGIC;
signal AXI_video_strm_V_keep_V_1_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_keep_V_1_sel : STD_LOGIC;
signal AXI_video_strm_V_keep_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal AXI_video_strm_V_strb_V_1_data_out : STD_LOGIC_VECTOR (2 downto 0);
signal AXI_video_strm_V_strb_V_1_vld_in : STD_LOGIC;
signal AXI_video_strm_V_strb_V_1_vld_out : STD_LOGIC;
signal AXI_video_strm_V_strb_V_1_ack_in : STD_LOGIC;
signal AXI_video_strm_V_strb_V_1_ack_out : STD_LOGIC;
signal AXI_video_strm_V_strb_V_1_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_strb_V_1_sel : STD_LOGIC;
signal AXI_video_strm_V_strb_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal AXI_video_strm_V_user_V_1_data_out : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_user_V_1_vld_in : STD_LOGIC;
signal AXI_video_strm_V_user_V_1_vld_out : STD_LOGIC;
signal AXI_video_strm_V_user_V_1_ack_in : STD_LOGIC;
signal AXI_video_strm_V_user_V_1_ack_out : STD_LOGIC;
signal AXI_video_strm_V_user_V_1_payload_A : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_user_V_1_payload_B : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_user_V_1_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_user_V_1_sel_wr : STD_LOGIC := '0';
signal AXI_video_strm_V_user_V_1_sel : STD_LOGIC;
signal AXI_video_strm_V_user_V_1_load_A : STD_LOGIC;
signal AXI_video_strm_V_user_V_1_load_B : STD_LOGIC;
signal AXI_video_strm_V_user_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal AXI_video_strm_V_user_V_1_state_cmp_full : STD_LOGIC;
signal AXI_video_strm_V_last_V_1_data_out : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_last_V_1_vld_in : STD_LOGIC;
signal AXI_video_strm_V_last_V_1_vld_out : STD_LOGIC;
signal AXI_video_strm_V_last_V_1_ack_in : STD_LOGIC;
signal AXI_video_strm_V_last_V_1_ack_out : STD_LOGIC;
signal AXI_video_strm_V_last_V_1_payload_A : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_last_V_1_payload_B : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_last_V_1_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_last_V_1_sel_wr : STD_LOGIC := '0';
signal AXI_video_strm_V_last_V_1_sel : STD_LOGIC;
signal AXI_video_strm_V_last_V_1_load_A : STD_LOGIC;
signal AXI_video_strm_V_last_V_1_load_B : STD_LOGIC;
signal AXI_video_strm_V_last_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal AXI_video_strm_V_last_V_1_state_cmp_full : STD_LOGIC;
signal AXI_video_strm_V_id_V_1_data_out : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_id_V_1_vld_in : STD_LOGIC;
signal AXI_video_strm_V_id_V_1_vld_out : STD_LOGIC;
signal AXI_video_strm_V_id_V_1_ack_in : STD_LOGIC;
signal AXI_video_strm_V_id_V_1_ack_out : STD_LOGIC;
signal AXI_video_strm_V_id_V_1_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_id_V_1_sel : STD_LOGIC;
signal AXI_video_strm_V_id_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal AXI_video_strm_V_dest_V_1_data_out : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_dest_V_1_vld_in : STD_LOGIC;
signal AXI_video_strm_V_dest_V_1_vld_out : STD_LOGIC;
signal AXI_video_strm_V_dest_V_1_ack_in : STD_LOGIC;
signal AXI_video_strm_V_dest_V_1_ack_out : STD_LOGIC;
signal AXI_video_strm_V_dest_V_1_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_dest_V_1_sel : STD_LOGIC;
signal AXI_video_strm_V_dest_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal img_rows_V_blk_n : STD_LOGIC;
signal img_cols_V_blk_n : STD_LOGIC;
signal img_data_stream_0_V_blk_n : STD_LOGIC;
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_block_pp0_stage0 : BOOLEAN;
signal exitcond_i_reg_280 : STD_LOGIC_VECTOR (0 downto 0);
signal img_data_stream_1_V_blk_n : STD_LOGIC;
signal img_data_stream_2_V_blk_n : STD_LOGIC;
signal stream_out_TDATA_blk_n : STD_LOGIC;
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal ap_reg_pp0_iter1_exitcond_i_reg_280 : STD_LOGIC_VECTOR (0 downto 0);
signal t_V_1_reg_164 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_fu_175_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_reg_256 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_block_state1 : BOOLEAN;
signal tmp_1_fu_179_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_1_reg_261 : STD_LOGIC_VECTOR (11 downto 0);
signal r_V_fu_183_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal r_V_reg_266 : STD_LOGIC_VECTOR (11 downto 0);
signal exitcond1_i_fu_198_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal ap_block_state2 : BOOLEAN;
signal i_V_fu_203_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal i_V_reg_275 : STD_LOGIC_VECTOR (10 downto 0);
signal exitcond_i_fu_213_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state4_io : BOOLEAN;
signal ap_block_state5_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_state5_io : BOOLEAN;
signal ap_block_pp0_stage0_11001 : BOOLEAN;
signal j_V_fu_218_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal axi_last_V_fu_224_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_last_V_reg_289 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_data_V_fu_233_p4 : STD_LOGIC_VECTOR (23 downto 0);
signal ap_block_pp0_stage0_subdone : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC;
signal t_V_reg_153 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal tmp_user_V_fu_90 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_pp0_stage0_01001 : BOOLEAN;
signal t_V_cast_i_fu_194_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal t_V_2_cast_i_fu_209_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
begin
AXI_video_strm_V_data_V_1_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_data_V_1_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_data_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_data_V_1_vld_out))) then
AXI_video_strm_V_data_V_1_sel_rd <= not(AXI_video_strm_V_data_V_1_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_data_V_1_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_data_V_1_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_data_V_1_ack_in) and (ap_const_logic_1 = AXI_video_strm_V_data_V_1_vld_in))) then
AXI_video_strm_V_data_V_1_sel_wr <= not(AXI_video_strm_V_data_V_1_sel_wr);
end if;
end if;
end if;
end process;
AXI_video_strm_V_data_V_1_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_data_V_1_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_data_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_1_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_data_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_data_V_1_ack_out)))) then
AXI_video_strm_V_data_V_1_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_data_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_data_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_data_V_1_vld_in)))) then
AXI_video_strm_V_data_V_1_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_data_V_1_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_data_V_1_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_data_V_1_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_data_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_data_V_1_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_data_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_data_V_1_vld_in)))) then
AXI_video_strm_V_data_V_1_state <= ap_const_lv2_3;
else
AXI_video_strm_V_data_V_1_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
AXI_video_strm_V_dest_V_1_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_dest_V_1_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_dest_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_1_vld_out))) then
AXI_video_strm_V_dest_V_1_sel_rd <= not(AXI_video_strm_V_dest_V_1_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_dest_V_1_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_dest_V_1_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_dest_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_dest_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_1_ack_out)))) then
AXI_video_strm_V_dest_V_1_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_dest_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_dest_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_1_vld_in)))) then
AXI_video_strm_V_dest_V_1_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_dest_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_1_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_1_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_dest_V_1_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_dest_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_1_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_dest_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_1_vld_in)))) then
AXI_video_strm_V_dest_V_1_state <= ap_const_lv2_3;
else
AXI_video_strm_V_dest_V_1_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
AXI_video_strm_V_id_V_1_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_id_V_1_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_id_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_id_V_1_vld_out))) then
AXI_video_strm_V_id_V_1_sel_rd <= not(AXI_video_strm_V_id_V_1_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_id_V_1_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_id_V_1_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_id_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_id_V_1_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_id_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_id_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_id_V_1_ack_out)))) then
AXI_video_strm_V_id_V_1_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_id_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_id_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_id_V_1_vld_in)))) then
AXI_video_strm_V_id_V_1_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_id_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_id_V_1_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_id_V_1_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_id_V_1_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_id_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_id_V_1_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_id_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_id_V_1_vld_in)))) then
AXI_video_strm_V_id_V_1_state <= ap_const_lv2_3;
else
AXI_video_strm_V_id_V_1_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
AXI_video_strm_V_keep_V_1_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_keep_V_1_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_keep_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_keep_V_1_vld_out))) then
AXI_video_strm_V_keep_V_1_sel_rd <= not(AXI_video_strm_V_keep_V_1_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_keep_V_1_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_keep_V_1_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_keep_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_keep_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_keep_V_1_ack_out)))) then
AXI_video_strm_V_keep_V_1_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_keep_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_keep_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_keep_V_1_vld_in)))) then
AXI_video_strm_V_keep_V_1_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_keep_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_keep_V_1_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_keep_V_1_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_keep_V_1_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_keep_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_keep_V_1_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_keep_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_keep_V_1_vld_in)))) then
AXI_video_strm_V_keep_V_1_state <= ap_const_lv2_3;
else
AXI_video_strm_V_keep_V_1_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
AXI_video_strm_V_last_V_1_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_last_V_1_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_last_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_last_V_1_vld_out))) then
AXI_video_strm_V_last_V_1_sel_rd <= not(AXI_video_strm_V_last_V_1_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_last_V_1_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_last_V_1_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_last_V_1_ack_in) and (ap_const_logic_1 = AXI_video_strm_V_last_V_1_vld_in))) then
AXI_video_strm_V_last_V_1_sel_wr <= not(AXI_video_strm_V_last_V_1_sel_wr);
end if;
end if;
end if;
end process;
AXI_video_strm_V_last_V_1_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_last_V_1_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_last_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_1_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_last_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_last_V_1_ack_out)))) then
AXI_video_strm_V_last_V_1_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_last_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_last_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_last_V_1_vld_in)))) then
AXI_video_strm_V_last_V_1_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_last_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_last_V_1_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_last_V_1_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_last_V_1_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_last_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_last_V_1_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_last_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_last_V_1_vld_in)))) then
AXI_video_strm_V_last_V_1_state <= ap_const_lv2_3;
else
AXI_video_strm_V_last_V_1_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
AXI_video_strm_V_strb_V_1_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_strb_V_1_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_strb_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_strb_V_1_vld_out))) then
AXI_video_strm_V_strb_V_1_sel_rd <= not(AXI_video_strm_V_strb_V_1_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_strb_V_1_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_strb_V_1_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_strb_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_strb_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_strb_V_1_ack_out)))) then
AXI_video_strm_V_strb_V_1_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_strb_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_strb_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_strb_V_1_vld_in)))) then
AXI_video_strm_V_strb_V_1_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_strb_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_strb_V_1_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_strb_V_1_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_strb_V_1_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_strb_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_strb_V_1_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_strb_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_strb_V_1_vld_in)))) then
AXI_video_strm_V_strb_V_1_state <= ap_const_lv2_3;
else
AXI_video_strm_V_strb_V_1_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
AXI_video_strm_V_user_V_1_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_user_V_1_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_user_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_user_V_1_vld_out))) then
AXI_video_strm_V_user_V_1_sel_rd <= not(AXI_video_strm_V_user_V_1_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_user_V_1_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_user_V_1_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_user_V_1_ack_in) and (ap_const_logic_1 = AXI_video_strm_V_user_V_1_vld_in))) then
AXI_video_strm_V_user_V_1_sel_wr <= not(AXI_video_strm_V_user_V_1_sel_wr);
end if;
end if;
end if;
end process;
AXI_video_strm_V_user_V_1_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_user_V_1_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_user_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_1_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_user_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_user_V_1_ack_out)))) then
AXI_video_strm_V_user_V_1_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_user_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_user_V_1_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_user_V_1_vld_in)))) then
AXI_video_strm_V_user_V_1_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_user_V_1_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_user_V_1_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_user_V_1_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_user_V_1_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_user_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_user_V_1_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_user_V_1_state) and (ap_const_logic_1 = AXI_video_strm_V_user_V_1_vld_in)))) then
AXI_video_strm_V_user_V_1_state <= ap_const_lv2_3;
else
AXI_video_strm_V_user_V_1_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_continue = ap_const_logic_1)) then
ap_done_reg <= ap_const_logic_0;
elsif ((not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in))) and (exitcond1_i_fu_198_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif ((not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in))) and (exitcond1_i_fu_198_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3)) then
ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state3);
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end if;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
elsif ((not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in))) and (exitcond1_i_fu_198_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
t_V_1_reg_164_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_i_fu_213_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
t_V_1_reg_164 <= j_V_fu_218_p2;
elsif ((not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in))) and (exitcond1_i_fu_198_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
t_V_1_reg_164 <= ap_const_lv11_0;
end if;
end if;
end process;
t_V_reg_153_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_start = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
t_V_reg_153 <= ap_const_lv11_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
t_V_reg_153 <= i_V_reg_275;
end if;
end if;
end process;
tmp_user_V_fu_90_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_i_reg_280 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
tmp_user_V_fu_90 <= ap_const_lv1_0;
elsif ((not(((ap_start = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
tmp_user_V_fu_90 <= ap_const_lv1_1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_data_V_1_load_A)) then
AXI_video_strm_V_data_V_1_payload_A <= tmp_data_V_fu_233_p4;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_data_V_1_load_B)) then
AXI_video_strm_V_data_V_1_payload_B <= tmp_data_V_fu_233_p4;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_last_V_1_load_A)) then
AXI_video_strm_V_last_V_1_payload_A <= axi_last_V_reg_289;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_last_V_1_load_B)) then
AXI_video_strm_V_last_V_1_payload_B <= axi_last_V_reg_289;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_user_V_1_load_A)) then
AXI_video_strm_V_user_V_1_payload_A <= tmp_user_V_fu_90;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_user_V_1_load_B)) then
AXI_video_strm_V_user_V_1_payload_B <= tmp_user_V_fu_90;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_reg_pp0_iter1_exitcond_i_reg_280 <= exitcond_i_reg_280;
exitcond_i_reg_280 <= exitcond_i_fu_213_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_i_fu_213_p2 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
axi_last_V_reg_289 <= axi_last_V_fu_224_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
i_V_reg_275 <= i_V_fu_203_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_start = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
r_V_reg_266 <= r_V_fu_183_p2;
tmp_1_reg_261 <= tmp_1_fu_179_p1;
tmp_reg_256 <= tmp_fu_175_p1;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, img_rows_V_empty_n, img_cols_V_empty_n, AXI_video_strm_V_data_V_1_ack_in, AXI_video_strm_V_keep_V_1_ack_in, AXI_video_strm_V_strb_V_1_ack_in, AXI_video_strm_V_user_V_1_ack_in, AXI_video_strm_V_last_V_1_ack_in, AXI_video_strm_V_id_V_1_ack_in, AXI_video_strm_V_dest_V_1_ack_in, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, exitcond1_i_fu_198_p2, ap_CS_fsm_state2, exitcond_i_fu_213_p2, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_subdone)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if ((not(((ap_start = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if ((not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in))) and (exitcond1_i_fu_198_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_NS_fsm <= ap_ST_fsm_state1;
elsif ((not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in))) and (exitcond1_i_fu_198_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_state2;
end if;
when ap_ST_fsm_pp0_stage0 =>
if ((not(((exitcond_i_fu_213_p2 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1))) and not(((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
elsif ((((exitcond_i_fu_213_p2 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1)) or ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)))) then
ap_NS_fsm <= ap_ST_fsm_state6;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_state6 =>
ap_NS_fsm <= ap_ST_fsm_state2;
when others =>
ap_NS_fsm <= "XXXX";
end case;
end process;
AXI_video_strm_V_data_V_1_ack_in <= AXI_video_strm_V_data_V_1_state(1);
AXI_video_strm_V_data_V_1_ack_out <= stream_out_TREADY;
AXI_video_strm_V_data_V_1_data_out_assign_proc : process(AXI_video_strm_V_data_V_1_payload_A, AXI_video_strm_V_data_V_1_payload_B, AXI_video_strm_V_data_V_1_sel)
begin
if ((ap_const_logic_1 = AXI_video_strm_V_data_V_1_sel)) then
AXI_video_strm_V_data_V_1_data_out <= AXI_video_strm_V_data_V_1_payload_B;
else
AXI_video_strm_V_data_V_1_data_out <= AXI_video_strm_V_data_V_1_payload_A;
end if;
end process;
AXI_video_strm_V_data_V_1_load_A <= (not(AXI_video_strm_V_data_V_1_sel_wr) and AXI_video_strm_V_data_V_1_state_cmp_full);
AXI_video_strm_V_data_V_1_load_B <= (AXI_video_strm_V_data_V_1_state_cmp_full and AXI_video_strm_V_data_V_1_sel_wr);
AXI_video_strm_V_data_V_1_sel <= AXI_video_strm_V_data_V_1_sel_rd;
AXI_video_strm_V_data_V_1_state_cmp_full <= '0' when (AXI_video_strm_V_data_V_1_state = ap_const_lv2_1) else '1';
AXI_video_strm_V_data_V_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_i_reg_280, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_reg_280 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
AXI_video_strm_V_data_V_1_vld_in <= ap_const_logic_1;
else
AXI_video_strm_V_data_V_1_vld_in <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_data_V_1_vld_out <= AXI_video_strm_V_data_V_1_state(0);
AXI_video_strm_V_dest_V_1_ack_in <= AXI_video_strm_V_dest_V_1_state(1);
AXI_video_strm_V_dest_V_1_ack_out <= stream_out_TREADY;
AXI_video_strm_V_dest_V_1_data_out <= ap_const_lv1_0;
AXI_video_strm_V_dest_V_1_sel <= AXI_video_strm_V_dest_V_1_sel_rd;
AXI_video_strm_V_dest_V_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_i_reg_280, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_reg_280 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
AXI_video_strm_V_dest_V_1_vld_in <= ap_const_logic_1;
else
AXI_video_strm_V_dest_V_1_vld_in <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_dest_V_1_vld_out <= AXI_video_strm_V_dest_V_1_state(0);
AXI_video_strm_V_id_V_1_ack_in <= AXI_video_strm_V_id_V_1_state(1);
AXI_video_strm_V_id_V_1_ack_out <= stream_out_TREADY;
AXI_video_strm_V_id_V_1_data_out <= ap_const_lv1_0;
AXI_video_strm_V_id_V_1_sel <= AXI_video_strm_V_id_V_1_sel_rd;
AXI_video_strm_V_id_V_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_i_reg_280, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_reg_280 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
AXI_video_strm_V_id_V_1_vld_in <= ap_const_logic_1;
else
AXI_video_strm_V_id_V_1_vld_in <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_id_V_1_vld_out <= AXI_video_strm_V_id_V_1_state(0);
AXI_video_strm_V_keep_V_1_ack_in <= AXI_video_strm_V_keep_V_1_state(1);
AXI_video_strm_V_keep_V_1_ack_out <= stream_out_TREADY;
AXI_video_strm_V_keep_V_1_data_out <= ap_const_lv3_7;
AXI_video_strm_V_keep_V_1_sel <= AXI_video_strm_V_keep_V_1_sel_rd;
AXI_video_strm_V_keep_V_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_i_reg_280, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_reg_280 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
AXI_video_strm_V_keep_V_1_vld_in <= ap_const_logic_1;
else
AXI_video_strm_V_keep_V_1_vld_in <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_keep_V_1_vld_out <= AXI_video_strm_V_keep_V_1_state(0);
AXI_video_strm_V_last_V_1_ack_in <= AXI_video_strm_V_last_V_1_state(1);
AXI_video_strm_V_last_V_1_ack_out <= stream_out_TREADY;
AXI_video_strm_V_last_V_1_data_out_assign_proc : process(AXI_video_strm_V_last_V_1_payload_A, AXI_video_strm_V_last_V_1_payload_B, AXI_video_strm_V_last_V_1_sel)
begin
if ((ap_const_logic_1 = AXI_video_strm_V_last_V_1_sel)) then
AXI_video_strm_V_last_V_1_data_out <= AXI_video_strm_V_last_V_1_payload_B;
else
AXI_video_strm_V_last_V_1_data_out <= AXI_video_strm_V_last_V_1_payload_A;
end if;
end process;
AXI_video_strm_V_last_V_1_load_A <= (not(AXI_video_strm_V_last_V_1_sel_wr) and AXI_video_strm_V_last_V_1_state_cmp_full);
AXI_video_strm_V_last_V_1_load_B <= (AXI_video_strm_V_last_V_1_state_cmp_full and AXI_video_strm_V_last_V_1_sel_wr);
AXI_video_strm_V_last_V_1_sel <= AXI_video_strm_V_last_V_1_sel_rd;
AXI_video_strm_V_last_V_1_state_cmp_full <= '0' when (AXI_video_strm_V_last_V_1_state = ap_const_lv2_1) else '1';
AXI_video_strm_V_last_V_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_i_reg_280, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_reg_280 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
AXI_video_strm_V_last_V_1_vld_in <= ap_const_logic_1;
else
AXI_video_strm_V_last_V_1_vld_in <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_last_V_1_vld_out <= AXI_video_strm_V_last_V_1_state(0);
AXI_video_strm_V_strb_V_1_ack_in <= AXI_video_strm_V_strb_V_1_state(1);
AXI_video_strm_V_strb_V_1_ack_out <= stream_out_TREADY;
AXI_video_strm_V_strb_V_1_data_out <= ap_const_lv3_0;
AXI_video_strm_V_strb_V_1_sel <= AXI_video_strm_V_strb_V_1_sel_rd;
AXI_video_strm_V_strb_V_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_i_reg_280, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_reg_280 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
AXI_video_strm_V_strb_V_1_vld_in <= ap_const_logic_1;
else
AXI_video_strm_V_strb_V_1_vld_in <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_strb_V_1_vld_out <= AXI_video_strm_V_strb_V_1_state(0);
AXI_video_strm_V_user_V_1_ack_in <= AXI_video_strm_V_user_V_1_state(1);
AXI_video_strm_V_user_V_1_ack_out <= stream_out_TREADY;
AXI_video_strm_V_user_V_1_data_out_assign_proc : process(AXI_video_strm_V_user_V_1_payload_A, AXI_video_strm_V_user_V_1_payload_B, AXI_video_strm_V_user_V_1_sel)
begin
if ((ap_const_logic_1 = AXI_video_strm_V_user_V_1_sel)) then
AXI_video_strm_V_user_V_1_data_out <= AXI_video_strm_V_user_V_1_payload_B;
else
AXI_video_strm_V_user_V_1_data_out <= AXI_video_strm_V_user_V_1_payload_A;
end if;
end process;
AXI_video_strm_V_user_V_1_load_A <= (not(AXI_video_strm_V_user_V_1_sel_wr) and AXI_video_strm_V_user_V_1_state_cmp_full);
AXI_video_strm_V_user_V_1_load_B <= (AXI_video_strm_V_user_V_1_state_cmp_full and AXI_video_strm_V_user_V_1_sel_wr);
AXI_video_strm_V_user_V_1_sel <= AXI_video_strm_V_user_V_1_sel_rd;
AXI_video_strm_V_user_V_1_state_cmp_full <= '0' when (AXI_video_strm_V_user_V_1_state = ap_const_lv2_1) else '1';
AXI_video_strm_V_user_V_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_i_reg_280, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_reg_280 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
AXI_video_strm_V_user_V_1_vld_in <= ap_const_logic_1;
else
AXI_video_strm_V_user_V_1_vld_in <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_user_V_1_vld_out <= AXI_video_strm_V_user_V_1_state(0);
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state6 <= ap_CS_fsm(3);
ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_01001_assign_proc : process(img_data_stream_0_V_empty_n, img_data_stream_1_V_empty_n, img_data_stream_2_V_empty_n, ap_enable_reg_pp0_iter1, exitcond_i_reg_280)
begin
ap_block_pp0_stage0_01001 <= ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((exitcond_i_reg_280 = ap_const_lv1_0) and (img_data_stream_2_V_empty_n = ap_const_logic_0)) or ((exitcond_i_reg_280 = ap_const_lv1_0) and (img_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond_i_reg_280 = ap_const_lv1_0) and (img_data_stream_0_V_empty_n = ap_const_logic_0))));
end process;
ap_block_pp0_stage0_11001_assign_proc : process(img_data_stream_0_V_empty_n, img_data_stream_1_V_empty_n, img_data_stream_2_V_empty_n, ap_enable_reg_pp0_iter1, exitcond_i_reg_280, ap_enable_reg_pp0_iter2, ap_block_state4_io, ap_block_state5_io)
begin
ap_block_pp0_stage0_11001 <= (((ap_const_boolean_1 = ap_block_state5_io) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and ((ap_const_boolean_1 = ap_block_state4_io) or ((exitcond_i_reg_280 = ap_const_lv1_0) and (img_data_stream_2_V_empty_n = ap_const_logic_0)) or ((exitcond_i_reg_280 = ap_const_lv1_0) and (img_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond_i_reg_280 = ap_const_lv1_0) and (img_data_stream_0_V_empty_n = ap_const_logic_0)))));
end process;
ap_block_pp0_stage0_subdone_assign_proc : process(img_data_stream_0_V_empty_n, img_data_stream_1_V_empty_n, img_data_stream_2_V_empty_n, ap_enable_reg_pp0_iter1, exitcond_i_reg_280, ap_enable_reg_pp0_iter2, ap_block_state4_io, ap_block_state5_io)
begin
ap_block_pp0_stage0_subdone <= (((ap_const_boolean_1 = ap_block_state5_io) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and ((ap_const_boolean_1 = ap_block_state4_io) or ((exitcond_i_reg_280 = ap_const_lv1_0) and (img_data_stream_2_V_empty_n = ap_const_logic_0)) or ((exitcond_i_reg_280 = ap_const_lv1_0) and (img_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond_i_reg_280 = ap_const_lv1_0) and (img_data_stream_0_V_empty_n = ap_const_logic_0)))));
end process;
ap_block_state1_assign_proc : process(ap_start, ap_done_reg, img_rows_V_empty_n, img_cols_V_empty_n)
begin
ap_block_state1 <= ((ap_start = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
ap_block_state2_assign_proc : process(AXI_video_strm_V_data_V_1_ack_in, AXI_video_strm_V_keep_V_1_ack_in, AXI_video_strm_V_strb_V_1_ack_in, AXI_video_strm_V_user_V_1_ack_in, AXI_video_strm_V_last_V_1_ack_in, AXI_video_strm_V_id_V_1_ack_in, AXI_video_strm_V_dest_V_1_ack_in)
begin
ap_block_state2 <= ((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in));
end process;
ap_block_state3_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_io_assign_proc : process(AXI_video_strm_V_data_V_1_ack_in, exitcond_i_reg_280)
begin
ap_block_state4_io <= ((exitcond_i_reg_280 = ap_const_lv1_0) and (ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in));
end process;
ap_block_state4_pp0_stage0_iter1_assign_proc : process(img_data_stream_0_V_empty_n, img_data_stream_1_V_empty_n, img_data_stream_2_V_empty_n, exitcond_i_reg_280)
begin
ap_block_state4_pp0_stage0_iter1 <= (((exitcond_i_reg_280 = ap_const_lv1_0) and (img_data_stream_2_V_empty_n = ap_const_logic_0)) or ((exitcond_i_reg_280 = ap_const_lv1_0) and (img_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond_i_reg_280 = ap_const_lv1_0) and (img_data_stream_0_V_empty_n = ap_const_logic_0)));
end process;
ap_block_state5_io_assign_proc : process(AXI_video_strm_V_data_V_1_ack_in, ap_reg_pp0_iter1_exitcond_i_reg_280)
begin
ap_block_state5_io <= ((ap_reg_pp0_iter1_exitcond_i_reg_280 = ap_const_lv1_0) and (ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in));
end process;
ap_block_state5_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_condition_pp0_exit_iter0_state3_assign_proc : process(exitcond_i_fu_213_p2)
begin
if ((exitcond_i_fu_213_p2 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_done_reg, AXI_video_strm_V_data_V_1_ack_in, AXI_video_strm_V_keep_V_1_ack_in, AXI_video_strm_V_strb_V_1_ack_in, AXI_video_strm_V_user_V_1_ack_in, AXI_video_strm_V_last_V_1_ack_in, AXI_video_strm_V_id_V_1_ack_in, AXI_video_strm_V_dest_V_1_ack_in, exitcond1_i_fu_198_p2, ap_CS_fsm_state2)
begin
if ((not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in))) and (exitcond1_i_fu_198_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter0)
begin
if (((ap_enable_reg_pp0_iter0 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(AXI_video_strm_V_data_V_1_ack_in, AXI_video_strm_V_keep_V_1_ack_in, AXI_video_strm_V_strb_V_1_ack_in, AXI_video_strm_V_user_V_1_ack_in, AXI_video_strm_V_last_V_1_ack_in, AXI_video_strm_V_id_V_1_ack_in, AXI_video_strm_V_dest_V_1_ack_in, exitcond1_i_fu_198_p2, ap_CS_fsm_state2)
begin
if ((not(((ap_const_logic_0 = AXI_video_strm_V_data_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_dest_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_id_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_last_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_user_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_strb_V_1_ack_in) or (ap_const_logic_0 = AXI_video_strm_V_keep_V_1_ack_in))) and (exitcond1_i_fu_198_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
axi_last_V_fu_224_p2 <= "1" when (t_V_2_cast_i_fu_209_p1 = r_V_reg_266) else "0";
exitcond1_i_fu_198_p2 <= "1" when (t_V_cast_i_fu_194_p1 = tmp_reg_256) else "0";
exitcond_i_fu_213_p2 <= "1" when (t_V_2_cast_i_fu_209_p1 = tmp_1_reg_261) else "0";
i_V_fu_203_p2 <= std_logic_vector(unsigned(t_V_reg_153) + unsigned(ap_const_lv11_1));
img_cols_V_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, img_cols_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_cols_V_blk_n <= img_cols_V_empty_n;
else
img_cols_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_cols_V_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n, img_cols_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_cols_V_read <= ap_const_logic_1;
else
img_cols_V_read <= ap_const_logic_0;
end if;
end process;
img_data_stream_0_V_blk_n_assign_proc : process(img_data_stream_0_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, exitcond_i_reg_280)
begin
if (((exitcond_i_reg_280 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
img_data_stream_0_V_blk_n <= img_data_stream_0_V_empty_n;
else
img_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_data_stream_0_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_i_reg_280, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_reg_280 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
img_data_stream_0_V_read <= ap_const_logic_1;
else
img_data_stream_0_V_read <= ap_const_logic_0;
end if;
end process;
img_data_stream_1_V_blk_n_assign_proc : process(img_data_stream_1_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, exitcond_i_reg_280)
begin
if (((exitcond_i_reg_280 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
img_data_stream_1_V_blk_n <= img_data_stream_1_V_empty_n;
else
img_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_data_stream_1_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_i_reg_280, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_reg_280 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
img_data_stream_1_V_read <= ap_const_logic_1;
else
img_data_stream_1_V_read <= ap_const_logic_0;
end if;
end process;
img_data_stream_2_V_blk_n_assign_proc : process(img_data_stream_2_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, exitcond_i_reg_280)
begin
if (((exitcond_i_reg_280 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
img_data_stream_2_V_blk_n <= img_data_stream_2_V_empty_n;
else
img_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_data_stream_2_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, exitcond_i_reg_280, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_reg_280 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
img_data_stream_2_V_read <= ap_const_logic_1;
else
img_data_stream_2_V_read <= ap_const_logic_0;
end if;
end process;
img_rows_V_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_rows_V_blk_n <= img_rows_V_empty_n;
else
img_rows_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_rows_V_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n, img_cols_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_rows_V_read <= ap_const_logic_1;
else
img_rows_V_read <= ap_const_logic_0;
end if;
end process;
j_V_fu_218_p2 <= std_logic_vector(unsigned(t_V_1_reg_164) + unsigned(ap_const_lv11_1));
r_V_fu_183_p2 <= std_logic_vector(signed(ap_const_lv12_FFF) + signed(tmp_1_fu_179_p1));
stream_out_TDATA <= AXI_video_strm_V_data_V_1_data_out;
stream_out_TDATA_blk_n_assign_proc : process(AXI_video_strm_V_data_V_1_state, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, exitcond_i_reg_280, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter1_exitcond_i_reg_280)
begin
if ((((ap_reg_pp0_iter1_exitcond_i_reg_280 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1)) or ((exitcond_i_reg_280 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
stream_out_TDATA_blk_n <= AXI_video_strm_V_data_V_1_state(1);
else
stream_out_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
stream_out_TDEST <= AXI_video_strm_V_dest_V_1_data_out;
stream_out_TID <= AXI_video_strm_V_id_V_1_data_out;
stream_out_TKEEP <= AXI_video_strm_V_keep_V_1_data_out;
stream_out_TLAST <= AXI_video_strm_V_last_V_1_data_out;
stream_out_TSTRB <= AXI_video_strm_V_strb_V_1_data_out;
stream_out_TUSER <= AXI_video_strm_V_user_V_1_data_out;
stream_out_TVALID <= AXI_video_strm_V_dest_V_1_state(0);
t_V_2_cast_i_fu_209_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(t_V_1_reg_164),12));
t_V_cast_i_fu_194_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(t_V_reg_153),12));
tmp_1_fu_179_p1 <= img_cols_V_dout(12 - 1 downto 0);
tmp_data_V_fu_233_p4 <= ((img_data_stream_2_V_dout & img_data_stream_1_V_dout) & img_data_stream_0_V_dout);
tmp_fu_175_p1 <= img_rows_V_dout(12 - 1 downto 0);
end behav;
|
mit
|
12b223ccbffcc442153fd7723c66b07b
| 0.60222 | 2.534334 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/hls_saturation_encud.vhd
| 1 | 7,269 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hls_saturation_encud_div_u is
generic (
in0_WIDTH : INTEGER :=32;
in1_WIDTH : INTEGER :=32;
out_WIDTH : INTEGER :=32);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
dividend : in STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
divisor : in STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
quot : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
remd : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0));
function max (left, right : INTEGER) return INTEGER is
begin
if left > right then return left;
else return right;
end if;
end max;
end entity;
architecture rtl of hls_saturation_encud_div_u is
constant cal_WIDTH : INTEGER := max(in0_WIDTH, in1_WIDTH);
type in0_vector is array(INTEGER range <>) of UNSIGNED(in0_WIDTH-1 downto 0);
type in1_vector is array(INTEGER range <>) of UNSIGNED(in1_WIDTH-1 downto 0);
type cal_vector is array(INTEGER range <>) of UNSIGNED(cal_WIDTH downto 0);
signal dividend_tmp : in0_vector(0 to in0_WIDTH);
signal divisor_tmp : in1_vector(0 to in0_WIDTH);
signal remd_tmp : in0_vector(0 to in0_WIDTH);
signal comb_tmp : in0_vector(0 to in0_WIDTH-1);
signal cal_tmp : cal_vector(0 to in0_WIDTH-1);
begin
quot <= STD_LOGIC_VECTOR(RESIZE(dividend_tmp(in0_WIDTH), out_WIDTH));
remd <= STD_LOGIC_VECTOR(RESIZE(remd_tmp(in0_WIDTH), out_WIDTH));
tran_tmp_proc : process (clk)
begin
if (clk'event and clk='1') then
if (ce = '1') then
dividend_tmp(0) <= UNSIGNED(dividend);
divisor_tmp(0) <= UNSIGNED(divisor);
remd_tmp(0) <= (others => '0');
end if;
end if;
end process tran_tmp_proc;
run_proc: for i in 0 to in0_WIDTH-1 generate
begin
comb_tmp(i) <= remd_tmp(i)(in0_WIDTH-2 downto 0) & dividend_tmp(i)(in0_WIDTH-1);
cal_tmp(i) <= ('0' & comb_tmp(i)) - ('0' & divisor_tmp(i));
process (clk)
begin
if (clk'event and clk='1') then
if (ce = '1') then
dividend_tmp(i+1) <= dividend_tmp(i)(in0_WIDTH-2 downto 0) & (not cal_tmp(i)(cal_WIDTH));
divisor_tmp(i+1) <= divisor_tmp(i);
if cal_tmp(i)(cal_WIDTH) = '1' then
remd_tmp(i+1) <= comb_tmp(i);
else
remd_tmp(i+1) <= cal_tmp(i)(in0_WIDTH-1 downto 0);
end if;
end if;
end if;
end process;
end generate run_proc;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hls_saturation_encud_div is
generic (
in0_WIDTH : INTEGER :=32;
in1_WIDTH : INTEGER :=32;
out_WIDTH : INTEGER :=32);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
dividend : in STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
divisor : in STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
quot : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
remd : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0));
end entity;
architecture rtl of hls_saturation_encud_div is
component hls_saturation_encud_div_u is
generic (
in0_WIDTH : INTEGER :=32;
in1_WIDTH : INTEGER :=32;
out_WIDTH : INTEGER :=32);
port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
dividend : in STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
divisor : in STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
quot : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
remd : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0));
end component;
signal dividend0 : STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
signal divisor0 : STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
signal dividend_u : STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
signal divisor_u : STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
signal quot_u : STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
signal remd_u : STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
begin
hls_saturation_encud_div_u_0 : hls_saturation_encud_div_u
generic map(
in0_WIDTH => in0_WIDTH,
in1_WIDTH => in1_WIDTH,
out_WIDTH => out_WIDTH)
port map(
clk => clk,
reset => reset,
ce => ce,
dividend => dividend_u,
divisor => divisor_u,
quot => quot_u,
remd => remd_u);
dividend_u <= dividend0;
divisor_u <= divisor0;
process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
dividend0 <= dividend;
divisor0 <= divisor;
end if;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
quot <= quot_u;
remd <= remd_u;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity hls_saturation_encud is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of hls_saturation_encud is
component hls_saturation_encud_div is
generic (
in0_WIDTH : INTEGER;
in1_WIDTH : INTEGER;
out_WIDTH : INTEGER);
port (
dividend : IN STD_LOGIC_VECTOR;
divisor : IN STD_LOGIC_VECTOR;
quot : OUT STD_LOGIC_VECTOR;
remd : OUT STD_LOGIC_VECTOR;
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
reset : IN STD_LOGIC);
end component;
signal sig_quot : STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0);
signal sig_remd : STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0);
begin
hls_saturation_encud_div_U : component hls_saturation_encud_div
generic map (
in0_WIDTH => din0_WIDTH,
in1_WIDTH => din1_WIDTH,
out_WIDTH => dout_WIDTH)
port map (
dividend => din0,
divisor => din1,
quot => dout,
remd => sig_remd,
clk => clk,
ce => ce,
reset => reset);
end architecture;
|
mit
|
287a68f3b0329579d2b757bcf77fabb8
| 0.529371 | 3.542398 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
Interpolation_not_complete/shift_count.vhd
| 1 | 1,251 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:36:22 07/13/05
-- Design Name:
-- Module Name: shifter_right - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity shift_count is
Port ( y : in std_logic_vector(2 downto 0);
shift_left : out std_logic_vector(2 downto 0));
end shift_count;
architecture Behavioral of shift_count is
signal y_bar: std_logic_vector(3 downto 0);
signal temp: std_logic_vector(3 downto 0);
begin
y_bar <= '0' & y;
temp <= "1000" + ((not y_bar) + '1');
-- shift_left(3) <= temp(3);
shift_left(2) <= temp(2);
shift_left(1) <= temp(1);
shift_left(0) <= temp(0);
end Behavioral;
|
mit
|
0406dd3e8a278d39d62e54ea808addde
| 0.543565 | 3.381081 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/hls_saturation_ensc4.vhd
| 1 | 1,686 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hls_saturation_ensc4_DSP48_3 is
port (
a: in std_logic_vector(16 - 1 downto 0);
b: in std_logic_vector(8 - 1 downto 0);
p: out std_logic_vector(24 - 1 downto 0));
end entity;
architecture behav of hls_saturation_ensc4_DSP48_3 is
signal a_cvt: unsigned(16 - 1 downto 0);
signal b_cvt: unsigned(8 - 1 downto 0);
signal p_cvt: unsigned(24 - 1 downto 0);
attribute keep : string;
attribute keep of a_cvt : signal is "true";
attribute keep of b_cvt : signal is "true";
attribute keep of p_cvt : signal is "true";
begin
a_cvt <= unsigned(a);
b_cvt <= unsigned(b);
p_cvt <= unsigned (resize(unsigned (unsigned (a_cvt) * unsigned (b_cvt)), 24));
p <= std_logic_vector(p_cvt);
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity hls_saturation_ensc4 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of hls_saturation_ensc4 is
component hls_saturation_ensc4_DSP48_3 is
port (
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
hls_saturation_ensc4_DSP48_3_U : component hls_saturation_ensc4_DSP48_3
port map (
a => din0,
b => din1,
p => dout);
end architecture;
|
mit
|
34dcc52dae593091fb97fd43edc92cab
| 0.616845 | 3.261122 | false | false | false | false |
Digilent/vivado-library
|
module/synchronizers/SyncAsync.vhd
| 2 | 4,635 |
-------------------------------------------------------------------------------
--
-- File: SyncAsync.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
-- Last modification date: 05 October 2022
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module synchronizes the asynchronous signal (aIn) with the OutClk clock
-- domain and provides it on oOut. The number of FFs in the synchronizer chain
-- can be configured with kStages. The reset value for oOut can be configured
-- with kResetTo. The asynchronous reset w/ synchronous de-assertion (aoReset)
-- is always active-high.
--
-- Constraints:
-- # Replace <InstSyncAsync> with path to SyncAsync instance, keep rest unchanged
-- # Begin scope to SyncAsync instance
-- current_instance [get_cells <InstSyncAsync>]
-- # Input to synchronizer ignored for timing analysis
-- set_false_path -through [get_ports -scoped_to_current_instance aIn]
-- # Constrain internal synchronizer paths to half-period, which is expected to be easily met with ASYNC_REG=true
-- set ClkPeriod [get_property PERIOD [get_clocks -of_objects [get_ports -scoped_to_current_instance OutClk]]]
-- set_max_delay -from [get_cells oSyncStages_reg[*]] -to [get_cells oSyncStages_reg[*]] [expr $ClkPeriod/2]
-- current_instance -quiet
-- # End scope to SyncAsync instance
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SyncAsync is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
Port (
aoReset : in STD_LOGIC; -- active-high asynchronous reset w/ sync de-assertion
aIn : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
attribute keep_hierarchy : string;
attribute keep_hierarchy of SyncAsync : entity is "yes";
end SyncAsync;
architecture Behavioral of SyncAsync is
signal oSyncStages : std_logic_vector(kStages-1 downto 0) := (others => kResetTo);
attribute ASYNC_REG : string;
attribute ASYNC_REG of oSyncStages: signal is "TRUE";
begin
Sync: process (OutClk, aoReset)
begin
if (aoReset = '1') then
oSyncStages <= (others => kResetTo);
elsif Rising_Edge(OutClk) then
oSyncStages <= oSyncStages(oSyncStages'high-1 downto 0) & aIn;
end if;
end process Sync;
oOut <= oSyncStages(oSyncStages'high);
end Behavioral;
|
mit
|
9840b34eb75673c2f135b73666646c3b
| 0.691046 | 4.557522 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/Loop_loop_height_ibs.vhd
| 1 | 7,137 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Loop_loop_height_ibs_rom is
generic(
dwidth : integer := 8;
awidth : integer := 8;
mem_size : integer := 256
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of Loop_loop_height_ibs_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem : mem_array := (
0 => "00000000", 1 => "00000001", 2 => "00000011", 3 => "00000100",
4 => "00000110", 5 => "00000111", 6 => "00001000", 7 => "00001010",
8 => "00001011", 9 => "00001100", 10 => "00001110", 11 => "00001111",
12 => "00010001", 13 => "00010010", 14 => "00010011", 15 => "00010101",
16 => "00010110", 17 => "00010111", 18 => "00011001", 19 => "00011010",
20 => "00011011", 21 => "00011101", 22 => "00011110", 23 => "00011111",
24 => "00100001", 25 => "00100010", 26 => "00100011", 27 => "00100101",
28 => "00100110", 29 => "00100111", 30 => "00101001", 31 => "00101010",
32 => "00101011", 33 => "00101100", 34 => "00101110", 35 => "00101111",
36 => "00110000", 37 => "00110010", 38 => "00110011", 39 => "00110100",
40 => "00110101", 41 => "00110111", 42 => "00111000", 43 => "00111001",
44 => "00111011", 45 => "00111100", 46 => "00111101", 47 => "00111110",
48 => "01000000", 49 => "01000001", 50 => "01000010", 51 => "01000011",
52 => "01000101", 53 => "01000110", 54 => "01000111", 55 => "01001000",
56 => "01001001", 57 => "01001011", 58 => "01001100", 59 => "01001101",
60 => "01001110", 61 => "01010000", 62 => "01010001", 63 => "01010010",
64 => "01010011", 65 => "01010100", 66 => "01010110", 67 => "01010111",
68 => "01011000", 69 => "01011001", 70 => "01011010", 71 => "01011011",
72 => "01011101", 73 => "01011110", 74 => "01011111", 75 => "01100000",
76 => "01100001", 77 => "01100010", 78 => "01100100", 79 => "01100101",
80 => "01100110", 81 => "01100111", 82 => "01101000", 83 => "01101001",
84 => "01101011", 85 => "01101100", 86 => "01101101", 87 => "01101110",
88 => "01101111", 89 => "01110000", 90 => "01110001", 91 => "01110010",
92 => "01110100", 93 => "01110101", 94 => "01110110", 95 => "01110111",
96 => "01111000", 97 => "01111001", 98 => "01111010", 99 => "01111011",
100 => "01111100", 101 => "01111101", 102 => "01111110", 103 => "10000000",
104 => "10000001", 105 => "10000010", 106 => "10000011", 107 => "10000100",
108 => "10000101", 109 => "10000110", 110 => "10000111", 111 => "10001000",
112 => "10001001", 113 => "10001010", 114 => "10001011", 115 => "10001100",
116 => "10001101", 117 => "10001110", 118 => "10001111", 119 => "10010000",
120 => "10010001", 121 => "10010010", 122 => "10010011", 123 => "10010100",
124 => "10010101", 125 => "10010110", 126 => "10010111", 127 => "10011000",
128 => "10011001", 129 => "10011010", 130 => "10011011", 131 => "10011100",
132 => "10011101", 133 => "10011110", 134 => "10011111", 135 => "10100000",
136 => "10100001", 137 => "10100010", 138 => "10100011", 139 => "10100100",
140 => "10100101", 141 => "10100110", 142 => "10100111", 143 => "10101000",
144 => "10101001", 145 => "10101010", 146 => "10101011", 147 => "10101100",
148 => "10101101", 149 => "10101110", 150 => "10101111", 151 => "10110000",
152 to 153=> "10110001", 154 => "10110010", 155 => "10110011", 156 => "10110100",
157 => "10110101", 158 => "10110110", 159 => "10110111", 160 => "10111000",
161 => "10111001", 162 => "10111010", 163 to 164=> "10111011", 165 => "10111100",
166 => "10111101", 167 => "10111110", 168 => "10111111", 169 => "11000000",
170 => "11000001", 171 to 172=> "11000010", 173 => "11000011", 174 => "11000100",
175 => "11000101", 176 => "11000110", 177 to 178=> "11000111", 179 => "11001000",
180 => "11001001", 181 => "11001010", 182 => "11001011", 183 to 184=> "11001100",
185 => "11001101", 186 => "11001110", 187 => "11001111", 188 => "11010000",
189 to 190=> "11010001", 191 => "11010010", 192 => "11010011", 193 => "11010100",
194 to 195=> "11010101", 196 => "11010110", 197 => "11010111", 198 to 199=> "11011000",
200 => "11011001", 201 => "11011010", 202 => "11011011", 203 to 204=> "11011100",
205 => "11011101", 206 => "11011110", 207 to 208=> "11011111", 209 => "11100000",
210 => "11100001", 211 to 212=> "11100010", 213 => "11100011", 214 to 215=> "11100100",
216 => "11100101", 217 => "11100110", 218 to 219=> "11100111", 220 => "11101000",
221 to 222=> "11101001", 223 => "11101010", 224 => "11101011", 225 to 226=> "11101100",
227 => "11101101", 228 to 229=> "11101110", 230 => "11101111", 231 to 232=> "11110000",
233 => "11110001", 234 to 235=> "11110010", 236 => "11110011", 237 to 238=> "11110100",
239 => "11110101", 240 to 241=> "11110110", 242 => "11110111", 243 to 244=> "11111000",
245 to 246=> "11111001", 247 => "11111010", 248 to 249=> "11111011", 250 => "11111100",
251 to 252=> "11111101", 253 to 254=> "11111110", 255 => "11111111" );
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity Loop_loop_height_ibs is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 256;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of Loop_loop_height_ibs is
component Loop_loop_height_ibs_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
Loop_loop_height_ibs_rom_U : component Loop_loop_height_ibs_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0);
end architecture;
|
mit
|
e4b861e40c60c24d9e657479bda33afb
| 0.541824 | 3.671296 | false | false | false | false |
igormacedo/vhdlstudy
|
srflipflop.vhdl
| 1 | 1,100 |
library ieee;
use ieee.std_logic_1164.all;
entity srflipflop is
port(
sr : in std_logic_vector (1 downto 0);
clk : in std_logic;
prs_clr : in std_logic_vector (1 downto 0);
q, qb : out std_ulogic
);
end entity;
architecture behavior of srflipflop is
signal aux : std_ulogic;
begin
process(clk, prs_clr)
variable q_temp : std_ulogic;
begin
if prs_clr = "11" then
-- Z is only used for detecting occurencies of this case during simulartion
-- this signal should be X (forced unknown)
q_temp := 'Z';
elsif prs_clr = "01" then
q_temp := '0';
elsif prs_clr = "10" then
q_temp := '1';
elsif rising_edge(clk) then
case sr is
when "00" => q_temp := q_temp;
when "10" => q_temp := '1';
when "01" => q_temp := '0';
-- Z is only used for detecting occurencies of this case during simulartion
-- this signal should be X (forced unknown)
when others => q_temp := 'Z';
end case;
end if;
q <= q_temp;
aux <= not(q_temp);
end process;
qb <= aux;
end architecture;
|
mit
|
02c66c5e0dabbb0bf0c59b1911523f3f
| 0.586364 | 3.374233 | false | false | false | false |
Digilent/vivado-library
|
ip/usb2device_v1_0/src/packet_decoder.vhd
| 2 | 58,683 |
-------------------------------------------------------------------------------
--
-- File: Packet_Decoder.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module implements chapter 8 of the USB protocol
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity Packet_Decoder is
Port ( Ulpi_Clk : in STD_LOGIC;
reset : in STD_LOGIC;
Axi_Resetn : IN STD_LOGIC;
Axi_Clk : IN STD_LOGIC;
-- Transmit FIFO interface
a_Arb_Endpt_Nr : in std_logic_vector(4 downto 0);
Tx_Fifo_S_Aresetn : IN STD_LOGIC;
a_Tx_Fifo_S_Aclk : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tvalid : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tready : OUT STD_LOGIC;
a_Tx_Fifo_S_Axis_Tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_Tx_Fifo_S_Axis_Tlast : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tkeep : IN std_logic_vector(3 downto 0);
a_Tx_Fifo_S_Axis_Tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
tx_fifo_axis_overflow : OUT STD_LOGIC;
tx_fifo_axis_underflow : OUT STD_LOGIC;
--Receive FIFO interface
u_Rx_Fifo_s_Aclk : OUT std_logic;
u_Rx_Fifo_s_Axis_Tready : IN std_logic;
u_Rx_Fifo_s_Axis_Tvalid : OUT std_logic;
u_Rx_Fifo_s_Axis_Tdata : OUT std_logic_vector(31 downto 0);
u_Rx_Fifo_s_Axis_Tkeep : OUT std_logic_vector (3 downto 0);
u_Rx_Fifo_s_Axis_Tlast : OUT std_logic;
u_Rx_Fifo_Axis_Overflow : IN std_logic;
u_Rx_Fifo_Axis_Underflow : IN std_logic;
--Command FIFO(used to keep track of OUT packets) interface
u_Command_Fifo_Rd_En : IN std_logic;
u_Command_Fifo_Dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
u_Command_Fifo_Empty : OUT std_logic;
u_Command_Fifo_Valid : OUT std_logic;
--Setup packets are stored in these registers before being copied into the dQH
u_Setup_Buffer_Bytes_3_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
u_Setup_Buffer_Bytes_7_4 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ULPI state machine interace
u_Send_PID_CMD : out STD_LOGIC;
u_Send_Last : out STD_LOGIC;
u_Tx_Data : out STD_LOGIC_VECTOR (7 downto 0);
u_Tx_Data_En : in STD_LOGIC;
u_Tx_Pid : out STD_LOGIC_VECTOR (3 downto 0);
u_Tx_Cmd_Done : in STD_LOGIC;
u_Tx_Pid_Phase_Done : in STD_LOGIC;
u_CRC16_En_Ulpi : in STD_LOGIC;
u_RxEvent : in STD_LOGIC_VECTOR(1 downto 0);
u_RxActive : in STD_LOGIC;
u_Rx_Packet_Received : in STD_LOGIC;
u_Ulpi_Dir_Out : in STD_LOGIC;
u_Rx_Data : in STD_LOGIC_VECTOR(7 downto 0);
u_USB_Mode : in STD_LOGIC;
--Status registers used by the DMA_Transfer_Manager block or by the Control_Register Block
u_Setup_Received : OUT std_logic;
u_Setup_Received_Rst : in std_logic;
u_In_Token_Received : OUT std_logic;
u_Send_Zero_Length_Packet_Ack_Set : OUT STD_LOGIC;
u_Send_Zero_Length_Packet_Clear : OUT STD_LOGIC;
u_Send_Zero_Length_Packet : in STD_LOGIC;
u_In_Packet_Complete : OUT std_logic;
u_In_Packet_Complete_Rst : IN std_logic;
u_Endp_Nr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
u_iPush_Endpt_Nr_PD : OUT STD_LOGIC;
u_NAK_Sent : out STD_LOGIC;
u_Frame_Index : out STD_LOGIC_VECTOR (10 downto 0);
u_SOF_Received : out STD_LOGIC;
u_Resend_Set : out STD_LOGIC;
u_Cnt_Bytes_Sent : out std_logic_vector(12 downto 0);
u_Cnt_Bytes_Sent_Latch : out STD_LOGIC;
--Input ontrol registers sourced by the Control_registers block
u_USBADRA : in STD_LOGIC_VECTOR (7 downto 0);
u_Endp_Type : in STD_LOGIC_VECTOR(1 downto 0);
u_Endp_Stall : IN STD_LOGIC;
axis_32_to_8_latency_comp_out_port : out STD_LOGIC;
ulpi_latency_comp_out : in STD_LOGIC;
state_ind_pd : out STD_LOGIC_VECTOR(6 downto 0);
packet_err : out STD_LOGIC
);
end Packet_Decoder;
architecture Behavioral of Packet_Decoder is
COMPONENT crc5
PORT (
data_in : in std_logic_vector (10 downto 0);
-- crc_en , rst, clk : in std_logic;
crc_out : out std_logic_vector (4 downto 0)
);
END COMPONENT;
COMPONENT crc16
PORT (
data_in : in std_logic_vector (7 downto 0);
crc_en , rst, clk : in std_logic;
crc_out_res : out std_logic_vector (15 downto 0);
crc_out : out std_logic_vector (15 downto 0)
);
END COMPONENT;
--receives data through the DMA controller; implements a 1KB buffer in BRAM for each endpoint
--provides data to the ULPI block on demand from the Packet_Decoder state machine
COMPONENT Transmit_Path
PORT (
Axi_Resetn : IN STD_LOGIC;
Axi_Clk : IN STD_LOGIC;
Ulpi_Clk : in STD_LOGIC;
u_Resetn : IN STD_LOGIC;
u_PE_Endpt_Nr: in std_logic_vector(4 downto 0);
a_Arb_Endpt_Nr : in std_logic_vector(4 downto 0);
Tx_Fifo_S_Aresetn : IN STD_LOGIC;
a_Tx_Fifo_S_Aclk : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tvalid : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tready : OUT STD_LOGIC;
a_Tx_Fifo_S_Axis_Tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_Tx_Fifo_S_Axis_Tlast : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tkeep : IN std_logic_vector(3 downto 0);
a_Tx_Fifo_S_Axis_Tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
u_Send_Packet : in STD_LOGIC;
u_Tx_Data_En : in STD_LOGIC;
u_Tx_Data : out STD_LOGIC_VECTOR(7 downto 0);
u_Send_Packet_Last : out STD_LOGIC;
u_Endpt_Ready : out STD_LOGIC;
latency_comp_in : in STD_LOGIC;
latency_comp_out : out STD_LOGIC;
tx_fifo_axis_overflow : OUT STD_LOGIC;
tx_fifo_axis_underflow : OUT STD_LOGIC
);
END COMPONENT;
--buffers data received over yhe ULPI bus. OUT packets are stored in a FIFO,
--SETUP data follows a different path. OUT transactions are not currently working
COMPONENT Receive_Path
PORT (
Ulpi_Clk : in STD_LOGIC;
Axi_Clk : IN std_logic;
reset : in STD_LOGIC;
--RX FIFO STREAM INTERFACE
u_Rx_Fifo_s_Aclk : OUT std_logic;
u_Rx_Fifo_s_Axis_Tready : IN std_logic;
u_Rx_Fifo_s_Axis_Tvalid : OUT std_logic;
u_Rx_Fifo_s_Axis_Tdata : OUT std_logic_vector(31 downto 0);
u_Rx_Fifo_s_Axis_Tkeep : OUT std_logic_vector (3 downto 0);
u_Rx_Fifo_s_Axis_Tlast : OUT std_logic;
u_Rx_Fifo_Axis_Overflow : IN std_logic;
u_Rx_Fifo_Axis_Underflow : IN std_logic;
u_Command_Fifo_Rd_En : IN std_logic;
u_Command_Fifo_Dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
u_Command_Fifo_Empty : OUT std_logic;
u_Command_Fifo_Valid : OUT std_logic;
u_Setup_Buffer_Bytes_3_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
u_Setup_Buffer_Bytes_7_4 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
u_Setup_Buffer_Bytes_3_0_Loc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
u_Device_Addr : IN STD_LOGIC_VECTOR (6 downto 0);
u_Fifo_Empty : OUT STD_LOGIC;
--inputs from ULPI
u_Rx_Data : in STD_LOGIC_VECTOR(7 downto 0);
u_Ulpi_Dir_Out : in STD_LOGIC;
--inputs from FSM
u_Store_Packet : in STD_LOGIC;
u_Store_Packet_State : in STD_LOGIC;
u_End_Packet_Set : in STD_LOGIC;
u_Fifo_Write_Toggle_Set : in STD_LOGIC;
u_Fifo_Write_Toggle_Rst : in STD_LOGIC;
u_Fifo_Rst_q : in STD_LOGIC;
u_Input_Buffer_Loaded_Rst : in STD_LOGIC;
u_Accept_Setup_Data_Set : in STD_LOGIC;
u_Accept_Data_Set : in STD_LOGIC;
u_Setup_Received_Set : OUT std_logic;
u_Input_CR16 : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
constant CONTROL : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant BULK : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ISOCHRONOUS : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant INTERRUPT : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant PID_OUT : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant PID_IN : STD_LOGIC_VECTOR (3 downto 0) := "1001";
constant PID_SOF : STD_LOGIC_VECTOR (3 downto 0) := "0101";
constant PID_SETUP : STD_LOGIC_VECTOR (3 downto 0) := "1101";
constant PID_DATA0 : STD_LOGIC_VECTOR (3 downto 0) := "0011";
constant PID_DATA1 : STD_LOGIC_VECTOR (3 downto 0) := "1011";
constant PID_DATA2 : STD_LOGIC_VECTOR (3 downto 0) := "0111";
constant PID_MDATA : STD_LOGIC_VECTOR (3 downto 0) := "1111";
constant PID_ACK : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant PID_NAK : STD_LOGIC_VECTOR (3 downto 0) := "1010";
constant PID_STALL : STD_LOGIC_VECTOR (3 downto 0) := "1110";
constant PID_NYET : STD_LOGIC_VECTOR (3 downto 0) := "0110";
constant PID_PRE : STD_LOGIC_VECTOR (3 downto 0) := "1100";
constant PID_ERR : STD_LOGIC_VECTOR (3 downto 0) := "1100";
constant PID_SPLIT : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant PID_PING : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant TIMEOUT : INTEGER := 100;
type state_type is (IDLE, IGNORE_PACKET, TOKEN, STORE_PACKET_STATE, CHECK_TOKEN_PID, DECODE_PID,WAIT_DATA_PID, PL_TOP, ERROR, DEV_DO_BCINTO_SOF, DEV_DO_ISCHO, DEV_DO_BCINTO, DEV_DO_BCO, DEV_DO_BCINTI, DEV_DO_ISOCHI, DEV_DO_HSPING, DCHPKT2, DOPKT, DSPACE, DDO_IODATA, D_DO_IINEXT, DEV_RESP, DEV_DO_BCINTI_PACKET, DEV_DO_BCINTI_ZERO_LENGTH, DEV_DO_BCINTI_NAK, DEV_DO_BCINTI_STALL, DEV_DO_BCINTO_CHECK_PID, SEND_CRC16_1, SEND_CRC16_2, SEND_CRC16_END);
signal state, next_state : state_type;
signal u_Token_Byte1 : STD_LOGIC_VECTOR(7 downto 0);
signal u_Token_Byte2 : STD_LOGIC_VECTOR(7 downto 0);
signal u_Token_Byte1_Latch : STD_LOGIC;
signal u_Token_Byte2_Latch : STD_LOGIC;
signal u_Endp_Field : STD_LOGIC_VECTOR(3 downto 0);
signal u_PID_Field : STD_LOGIC_VECTOR(3 downto 0);
signal u_PID_Field_Latch : STD_LOGIC;
signal u_Token_PID : STD_LOGIC_VECTOR(3 downto 0);
signal u_Token_PID_Latch : STD_LOGIC;
signal u_Device_Address : STD_LOGIC_VECTOR (6 downto 0);
signal u_DEVICEADDR : STD_LOGIC_VECTOR (6 downto 0);
signal u_Endp_Nr_Latch : STD_LOGIC;
signal u_Endp_Nr_Loc : STD_LOGIC_VECTOR(4 DOWNTO 0);
signal u_CRC16_Field : STD_LOGIC_VECTOR (15 downto 0);
signal u_CRC5_Field : STD_LOGIC_VECTOR(4 downto 0);
signal u_Tx_Data_En_q : STD_LOGIC;
--Buffer Control
signal u_Fifo_Write_Toggle_Set : STD_LOGIC;
signal u_Fifo_Write_Toggle_Rst : STD_LOGIC;
signal u_Fifo_Rst : STD_LOGIC;
signal u_Fifo_Rst_q : STD_LOGIC;
signal u_Buffer_Available : STD_LOGIC;
signal u_Buffer_Available_Latch : STD_LOGIC;
signal u_Buffer_Empty : STD_LOGIC;
--Buffer_Load_Proc control signals
signal u_Store_Packet, u_Store_Packet_State : STD_LOGIC;
signal u_Input_Buffer_Loaded_Rst : STD_LOGIC;
signal u_End_Packet_Set : STD_LOGIC;
--Input_Buffer_Read_Proc
signal u_Accept_Data_Set : STD_LOGIC;
signal u_Accept_Setup_Data_Set : STD_LOGIC;
--auxiliary signals
signal u_Tx_Data_Loc : STD_LOGIC_VECTOR(7 downto 0);
signal u_In_Token_Received_Fsm, u_In_Token_Received_Fsm_q, u_In_Token_Received_Fsm_qq : std_logic;
signal u_Data_Pid_Sync, u_Data_Pid_Sync_Tx : STD_LOGIC_VECTOR (3 downto 0);
signal u_Data_Sync_Toggle, u_Data_Sync_Toggle_Tx : STD_LOGIC;
signal u_Data_Sync_Toggle_Rst, u_Data_Sync_Toggle_Rst_Tx : STD_LOGIC;
signal u_Frame_Index_Latch : STD_LOGIC;
signal u_Cnt_Bytes_Sent_Loc : STD_LOGIC_VECTOR(12 downto 0);
signal u_Cnt_Bytes_Sent_Rst : STD_LOGIC;
signal u_Setup_Buffer_Bytes_3_0_Loc : STD_LOGIC_VECTOR(31 downto 0);
signal u_Setup_Buffer_Bytes_3_0_Inversed : STD_LOGIC_VECTOR(31 downto 0);
signal u_Setup_Buffer_Bytes_7_4_Inversed : STD_LOGIC_VECTOR(31 downto 0);
signal u_Setup_Received_Set : STD_LOGIC;
signal u_Resend_Set_Fsm : STD_LOGIC;
signal u_Cnt_Timeout_CE : STD_LOGIC;
signal u_Cnt_Timeout_Rst : STD_LOGIC;
signal u_Cnt_Timeout : integer range 0 to 500;
--Output Path
signal u_Send_Packet : STD_LOGIC;
signal Transmit_Path_rst : STD_LOGIC;
signal u_Send_Packet_Last, u_Endpt_Ready : STD_LOGIC;
signal u_In_Packet_Complete_Set : STD_LOGIC;
signal axis_32_to_8_latency_comp_out : STD_LOGIC;
signal u_BRAM_Read_Data : STD_LOGIC_VECTOR(7 downto 0);
--CRC
signal u_CRC16_Input_Mux : STD_LOGIC;
signal u_CRC5_Data_In : STD_LOGIC_VECTOR(10 downto 0);
signal u_CRC5_Output : STD_LOGIC_VECTOR(4 downto 0);
signal u_CRC16_Rst : STD_LOGIC;
signal u_CRC16_Rst_Fsm : STD_LOGIC;
signal u_CRC16_En : STD_LOGIC;
signal u_CRC16_Data_In : STD_LOGIC_VECTOR(7 downto 0);
signal u_CRC16_Data_In_Inversed : STD_LOGIC_VECTOR(7 downto 0);
signal u_CRC16_Output : STD_LOGIC_VECTOR(15 downto 0);
signal u_CRC16_Residual : std_logic_vector (15 downto 0);
--Device address change from software
signal u_Inhibit : std_logic;
signal u_New_Deviceaddr : std_logic_vector(6 downto 0);
signal u_In_ACK, u_In_ACK_q : std_logic;
signal u_Advance : std_logic;
attribute mark_debug : string;
attribute keep : string;
--attribute mark_debug of u_Endp_Field : signal is "true";
--attribute keep of u_Endp_Field : signal is "true";
--attribute mark_debug of u_Device_Address : signal is "true";
--attribute keep of u_Device_Address : signal is "true";
--attribute mark_debug of u_CRC5_Field : signal is "true";
--attribute keep of u_CRC5_Field : signal is "true";
--attribute mark_debug of u_DEVICEADDR : signal is "true";
--attribute keep of u_DEVICEADDR : signal is "true";
--attribute mark_debug of u_Setup_Buffer_Bytes_3_0_Inversed : signal is "true";
--attribute keep of u_Setup_Buffer_Bytes_3_0_Inversed : signal is "true";
--attribute mark_debug of u_Setup_Buffer_Bytes_7_4_Inversed : signal is "true";
--attribute keep of u_Setup_Buffer_Bytes_7_4_Inversed : signal is "true";
--attribute mark_debug of u_Setup_Received_Set : signal is "true";
--attribute keep of u_Setup_Received_Set : signal is "true";
--attribute mark_debug of u_Setup_Received : signal is "true";
--attribute keep of u_Setup_Received : signal is "true";
--attribute mark_debug of u_Setup_Received_Rst : signal is "true";
--attribute keep of u_Setup_Received_Rst : signal is "true";
--attribute mark_debug of u_Cnt_Bytes_Sent : signal is "true";
--attribute keep of u_Cnt_Bytes_Sent : signal is "true";
--attribute mark_debug of u_Endpt_Ready : signal is "true";
--attribute keep of u_Endpt_Ready : signal is "true";
--attribute mark_debug of u_Tx_Data_Loc : signal is "true";
--attribute keep of u_Tx_Data_Loc : signal is "true";
--attribute mark_debug of u_Tx_Data_En : signal is "true";
--attribute keep of u_Tx_Data_En : signal is "true";
--attribute mark_debug of u_Send_Last : signal is "true";
--attribute keep of u_Send_Last : signal is "true";
--attribute mark_debug of u_CRC16_Output : signal is "true";
--attribute keep of u_CRC16_Output : signal is "true";
--attribute mark_debug of u_In_Packet_Complete_Rst : signal is "true";
--attribute keep of u_In_Packet_Complete_Rst : signal is "true";
--attribute mark_debug of u_In_Packet_Complete : signal is "true";
--attribute keep of u_In_Packet_Complete : signal is "true";
--attribute mark_debug of u_In_Packet_Complete_Set : signal is "true";
--attribute keep of u_In_Packet_Complete_Set : signal is "true";
--attribute mark_debug of u_Resend_Set_Fsm : signal is "true";
--attribute keep of u_Resend_Set_Fsm : signal is "true";
--attribute mark_debug of u_Cnt_Timeout : signal is "true";
--attribute keep of u_Cnt_Timeout : signal is "true";
--attribute mark_debug of u_BRAM_Read_Data : signal is "true";
--attribute keep of u_BRAM_Read_Data : signal is "true";
--attribute mark_debug of u_Data_Pid_Sync : signal is "true";
--attribute keep of u_Data_Pid_Sync : signal is "true";
--attribute mark_debug of u_Data_Sync_Toggle : signal is "true";
--attribute keep of u_Data_Sync_Toggle : signal is "true";
--attribute mark_debug of u_Data_Sync_Toggle_Rst : signal is "true";
--attribute keep of u_Data_Sync_Toggle_Rst : signal is "true";
begin
axis_32_to_8_latency_comp_out_port <= axis_32_to_8_latency_comp_out;
u_Tx_Data <= u_Tx_Data_Loc;
u_Endp_Nr <= u_Endp_Nr_Loc;
u_CRC5_Data_In <= u_Token_Byte1(0) & u_Token_Byte1(1) & u_Token_Byte1(2) & u_Token_Byte1(3) & u_Token_Byte1(4) & u_Token_Byte1(5) & u_Token_Byte1(6) & u_Token_Byte1(7) & u_Token_Byte2(0) & u_Token_Byte2(1) & u_Token_Byte2(2);
u_CRC16_Data_In <= u_Rx_Data when u_CRC16_Input_Mux = '1' else u_Tx_Data_Loc;
u_CRC16_Rst <= reset and u_CRC16_Rst_Fsm;
u_Advance <= u_USBADRA(0);
TX_DATA_EN_DELAY_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Tx_Data_En_q <= '0';
else
u_Tx_Data_En_q <= u_Tx_Data_En;
end if;
end if;
end process;
u_Setup_Buffer_Bytes_3_0(7 downto 0) <= u_Setup_Buffer_Bytes_3_0_Inversed(31 downto 24);
u_Setup_Buffer_Bytes_3_0(15 downto 8) <= u_Setup_Buffer_Bytes_3_0_Inversed(23 downto 16);
u_Setup_Buffer_Bytes_3_0(23 downto 16) <= u_Setup_Buffer_Bytes_3_0_Inversed(15 downto 8);
u_Setup_Buffer_Bytes_3_0(31 downto 24) <= u_Setup_Buffer_Bytes_3_0_Inversed(7 downto 0);
u_Setup_Buffer_Bytes_7_4(7 downto 0) <= u_Setup_Buffer_Bytes_7_4_Inversed(31 downto 24);
u_Setup_Buffer_Bytes_7_4(15 downto 8) <= u_Setup_Buffer_Bytes_7_4_Inversed(23 downto 16);
u_Setup_Buffer_Bytes_7_4(23 downto 16) <= u_Setup_Buffer_Bytes_7_4_Inversed(15 downto 8);
u_Setup_Buffer_Bytes_7_4(31 downto 24) <= u_Setup_Buffer_Bytes_7_4_Inversed(7 downto 0);
u_CRC16_Data_In_Inversed(0) <= u_CRC16_Data_In(7);
u_CRC16_Data_In_Inversed(1) <= u_CRC16_Data_In(6);
u_CRC16_Data_In_Inversed(2) <= u_CRC16_Data_In(5);
u_CRC16_Data_In_Inversed(3) <= u_CRC16_Data_In(4);
u_CRC16_Data_In_Inversed(4) <= u_CRC16_Data_In(3);
u_CRC16_Data_In_Inversed(5) <= u_CRC16_Data_In(2);
u_CRC16_Data_In_Inversed(6) <= u_CRC16_Data_In(1);
u_CRC16_Data_In_Inversed(7) <= u_CRC16_Data_In(0);
crc5_1 : crc5
PORT MAP (
data_in => u_CRC5_Data_In,
crc_out => u_CRC5_Output
);
crc16_1 : crc16
PORT MAP (
clk => Ulpi_Clk,
rst => u_CRC16_Rst,
data_in => u_CRC16_Data_In_Inversed, -- data is registered once in ULPI block. data_in must correspond to tx_data_r in ULPI block
crc_en => u_CRC16_En,
crc_out_res => u_CRC16_Residual,
crc_out => u_CRC16_Output
);
Inst_Receive_Path : Receive_Path
PORT MAP (
Ulpi_Clk => Ulpi_Clk,
Axi_Clk => Axi_Clk,
reset => reset,
u_Rx_Fifo_s_Aclk => u_Rx_Fifo_s_Aclk,
u_Rx_Fifo_s_Axis_Tready => u_Rx_Fifo_s_Axis_Tready,
u_Rx_Fifo_s_Axis_Tvalid => u_Rx_Fifo_s_Axis_Tvalid,
u_Rx_Fifo_s_Axis_Tdata => u_Rx_Fifo_s_Axis_Tdata,
u_Rx_Fifo_s_Axis_Tkeep => u_Rx_Fifo_s_Axis_Tkeep,
u_Rx_Fifo_s_Axis_Tlast => u_Rx_Fifo_s_Axis_Tlast,
u_Rx_Fifo_Axis_Overflow => u_Rx_Fifo_Axis_Overflow,
u_Rx_Fifo_Axis_Underflow => u_Rx_Fifo_Axis_Underflow,
u_Command_Fifo_Rd_En => u_Command_Fifo_Rd_En,
u_Command_Fifo_Dout => u_Command_Fifo_Dout,
u_Command_Fifo_Empty => u_Command_Fifo_Empty,
u_Command_Fifo_Valid => u_Command_Fifo_Valid,
u_Setup_Buffer_Bytes_3_0 => u_Setup_Buffer_Bytes_3_0_Inversed,
u_Setup_Buffer_Bytes_7_4 => u_Setup_Buffer_Bytes_7_4_Inversed,
u_Setup_Buffer_Bytes_3_0_Loc => u_Setup_Buffer_Bytes_3_0_Loc,
u_Device_Addr => u_Device_Address,
u_Fifo_Empty => u_Buffer_Empty,
u_Rx_Data => u_Rx_Data,
u_Ulpi_Dir_Out => u_Ulpi_Dir_Out,
u_Store_Packet => u_Store_Packet,
u_Store_Packet_State => u_Store_Packet_State,
u_End_Packet_Set => u_End_Packet_Set,
u_Fifo_Write_Toggle_Set => u_Fifo_Write_Toggle_Set,
u_Fifo_Write_Toggle_Rst => u_Fifo_Write_Toggle_Rst,
u_Fifo_Rst_q => u_Fifo_Rst_q,
u_Input_Buffer_Loaded_Rst => u_Input_Buffer_Loaded_Rst,
u_Accept_Data_Set => u_Accept_Data_Set,
u_Accept_Setup_Data_Set => u_Accept_Setup_Data_Set,
u_Setup_Received_Set => u_Setup_Received_Set,
u_Input_CR16 => u_CRC16_Field
);
Transmit_Path_rst <= reset and u_Cnt_Bytes_Sent_Rst;
Inst_Transmit_Path: Transmit_Path PORT MAP(
Axi_Resetn => Axi_Resetn,
Axi_Clk => Axi_Clk,
Ulpi_Clk => Ulpi_Clk,
u_Resetn => reset,
u_PE_Endpt_Nr => u_Endp_Nr_Loc,
a_Arb_Endpt_Nr => a_Arb_Endpt_Nr,
Tx_Fifo_S_Aresetn => Tx_Fifo_S_Aresetn,
a_Tx_Fifo_S_Aclk => a_Tx_Fifo_S_Aclk,
a_Tx_Fifo_S_Axis_Tvalid => a_Tx_Fifo_S_Axis_Tvalid,
a_Tx_Fifo_S_Axis_Tready => a_Tx_Fifo_S_Axis_Tready,
a_Tx_Fifo_S_Axis_Tdata => a_Tx_Fifo_S_Axis_Tdata,
a_Tx_Fifo_S_Axis_Tlast => a_Tx_Fifo_S_Axis_Tlast,
a_Tx_Fifo_S_Axis_Tkeep => a_Tx_Fifo_S_Axis_Tkeep,
a_Tx_Fifo_S_Axis_Tuser => a_Tx_Fifo_S_Axis_Tuser,
u_Send_Packet => u_Send_Packet,
u_Tx_Data_En => u_Tx_Data_En,
u_Tx_Data => u_BRAM_Read_Data,
u_Send_Packet_Last => u_Send_Packet_Last,
u_Endpt_Ready => u_Endpt_Ready,
latency_comp_in => u_Send_Packet,
latency_comp_out => axis_32_to_8_latency_comp_out,
tx_fifo_axis_overflow => tx_fifo_axis_overflow,
tx_fifo_axis_underflow => tx_fifo_axis_underflow
);
--u_In_Token_Received is a pulse that signals to upper layers an IN token was detected
IN_TOKEN_SET_DELAY_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_In_Token_Received <= '0';
u_In_Token_Received_Fsm_q <= '0';
u_In_Token_Received_Fsm_qq <= '0';
else
u_In_Token_Received_Fsm_q <= u_In_Token_Received_Fsm;
u_In_Token_Received_Fsm_qq <= u_In_Token_Received_Fsm_q;
u_In_Token_Received <= u_In_Token_Received_Fsm_q and (not u_In_Token_Received_Fsm_qq);
end if;
end if;
end process;
-- u_Buffer_Available used to generate a NAK on response to OUT tokens in case the input buffer is full
SPACE_AVAIL_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Buffer_Available <= '0';
elsif (u_Buffer_Available_Latch = '1') then
u_Buffer_Available <= u_Buffer_Empty;
end if;
end if;
end process;
--u_Fifo_Rst_q used to reset the input buffer in case the data received has an invalid CRC
RESET_BUFFER_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Fifo_Rst_q <= '0';
else
if (u_Fifo_Rst = '1') then
u_Fifo_Rst_q <= '1';
else
u_Fifo_Rst_q <= '0';
end if;
end if;
end if;
end process;
--this process decodes token packets
TOCKEN_DECODE_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_PID_Field <= (others => '0');
u_Token_Byte1 <= (others => '0');
u_Token_Byte2 <= (others => '0');
else
--state_ind_pd_r <= state_ind_pd;
if (u_PID_Field_Latch = '1') then
u_PID_Field <= u_Rx_Data(3 downto 0);
elsif (u_Token_Byte1_Latch = '1') then
u_Token_Byte1 <= u_Rx_Data;
elsif (u_Token_Byte2_Latch = '1') then
u_Token_Byte2 <= u_Rx_Data;
end if;
end if;
end if;
end process;
--Frame index is obtained from SOF packets. Frame index is stored into a register
--in the Control_registers block
FRAME_INDEX_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Frame_Index <= (others => '0');
u_SOF_Received <= '0';
else
if (u_Frame_Index_Latch = '1') then
u_Frame_Index(7 downto 0) <= u_Rx_Data;
u_SOF_Received <= '0';
elsif (u_Token_Byte2_Latch = '1') then
u_Frame_Index(10 downto 8) <= u_Rx_Data(2 downto 0);
u_SOF_Received <= '1';
else
u_SOF_Received <= '0';
end if;
end if;
end if;
end process;
--register the incoming token PID
TOKEN_PID_Q_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Token_PID <= (others => '0');
elsif (u_Token_PID_Latch = '1') then
u_Token_PID <= u_PID_Field;
end if;
end if;
end process;
u_Device_Address <= u_Token_Byte1(6 downto 0);
u_Endp_Field <= u_Token_Byte2(2 downto 0) & u_Token_Byte1(7);
u_CRC5_Field(0) <= u_Token_Byte2(3);
u_CRC5_Field(1) <= u_Token_Byte2(4);
u_CRC5_Field(2) <= u_Token_Byte2(5);
u_CRC5_Field(3) <= u_Token_Byte2(6);
u_CRC5_Field(4) <= u_Token_Byte2(7);
--signal to upper layers on which endpoint to take action
PE_ENDPT_NR_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Endp_Nr_Loc <= (others => '0');
u_iPush_Endpt_Nr_PD <= '0';
elsif (u_Endp_Nr_Latch = '1') then
u_iPush_Endpt_Nr_PD <= '1';
if (u_PID_Field = PID_SETUP or u_PID_Field = PID_OUT) then
u_Endp_Nr_Loc <= u_Endp_Field & '0';
elsif (u_PID_Field = PID_IN) then
u_Endp_Nr_Loc <= u_Endp_Field & '1';
end if;
else
u_iPush_Endpt_Nr_PD <= '0';
end if;
end if;
end process;
--Data synchronization
DATA_SYNC_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if ((reset = '0') or (u_Data_Sync_Toggle_Rst = '0')) then
u_Data_Pid_Sync <= PID_DATA0;
elsif (u_Data_Sync_Toggle = '1') then
u_Data_Pid_Sync(3) <= not (u_Data_Pid_Sync(3));
end if;
end if;
end process;
--TX packets data synchronization
DATA_SYNC_TX_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if ((reset = '0') or (u_Data_Sync_Toggle_Rst_Tx = '0')) then
u_Data_Pid_Sync_Tx <= PID_DATA1;
elsif (u_Data_Sync_Toggle_Tx = '1') then
u_Data_Pid_Sync_Tx(3) <= not (u_Data_Pid_Sync_Tx(3));
end if;
end if;
end process;
--indicate a SETUP packet was received
SETUP_RECEIVED_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0' or u_Setup_Received_Rst = '0') then
u_Setup_Received <= '0';
elsif (u_Setup_Received_Set = '1') then
u_Setup_Received <= '1';
end if;
end if;
end process;
--indicate an input transaction was completed succesfully
PACKET_IN_COMPLETE_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0' or u_In_Packet_Complete_Rst = '0') then
u_In_Packet_Complete <= '0';
elsif (u_In_Packet_Complete_Set = '1') then
u_In_Packet_Complete <= '1';
end if;
end if;
end process;
--Counts packet bytes sent over the ULPI interface
IN_PACKET_COUNTER_TMP_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0' or u_Cnt_Bytes_Sent_Rst = '0') then
u_Cnt_Bytes_Sent_Loc <= (others => '0');
else
if (u_Tx_Data_En = '1' and u_Send_Packet = '1') then
u_Cnt_Bytes_Sent_Loc <= std_logic_vector(unsigned(u_Cnt_Bytes_Sent_Loc)+1);
end if;
end if;
end if;
end process;
U_IN_ACK_Q_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_In_ACK_q <= '0';
else
u_In_ACK_q <= u_In_ACK;
end if;
end if;
end process;
U_DEVICEADDR_UPDATE_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_DEVICEADDR <= (others => '0');
else
if (u_Advance = '1') then
if (u_In_ACK_q = '1') then
u_DEVICEADDR <= u_USBADRA(7 downto 1);
end if;
else
u_DEVICEADDR <= u_USBADRA(7 downto 1);
end if;
end if;
end if;
end process;
--monitors the host handshake response time for IN packets
U_TIMEOUT_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if ((reset = '0') or (u_Cnt_Timeout_Rst = '0'))then
u_Cnt_Timeout <= 0;
else
if (u_Cnt_Timeout_CE = '1') then
if (u_Cnt_Timeout = 500) then
u_Cnt_Timeout <= 0;
else
u_Cnt_Timeout <= u_Cnt_Timeout +1;
end if;
end if;
end if;
end if;
end process;
--signals to upper layers that a packet needs to be resent
U_RESEND_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0')then
u_Resend_Set <= '0';
else
u_Resend_Set <= u_Resend_Set_Fsm;
end if;
end if;
end process;
u_Cnt_Bytes_Sent <= u_Cnt_Bytes_Sent_Loc;
--Chapter8 State Machines
SYNC_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
state <= IDLE;
else
state <= next_state;
end if;
end if;
end process;
NEXT_STATE_DECODE: process (state, u_Rx_Data, u_Inhibit, u_CRC5_Field, u_CRC16_Residual, u_PID_Field, u_Send_Zero_Length_Packet, u_Tx_Pid_Phase_Done, u_CRC16_En_Ulpi, u_Device_Address, u_DEVICEADDR, u_Rx_Packet_Received, u_CRC5_Output, u_CRC16_Output, u_Send_Packet_Last, u_Tx_Data_En, u_BRAM_Read_Data, u_USB_Mode, u_Token_PID, u_Buffer_Available, u_Endp_Type, u_Data_Pid_Sync, u_Tx_Cmd_Done, u_Endp_Stall, u_RxActive, u_RxEvent)
begin
next_state <= state;
packet_err <= '0';
u_PID_Field_Latch <= '0';
u_Token_Byte1_Latch <= '0';
u_Token_Byte2_Latch <= '0';
u_Token_PID_Latch <= '0';
u_Store_Packet <= '0';
u_End_Packet_Set <= '0';
u_Fifo_Rst <= '0';
u_Accept_Data_Set <= '0';
u_Send_PID_CMD <= '0';
u_Send_Last <= '0';
u_Tx_Data_Loc <= (others => '0');
u_Tx_Pid <= (others => '0');
u_Buffer_Available_Latch <= '0';
u_In_Token_Received_Fsm <= '0';
u_Fifo_Write_Toggle_Set <= '0';
u_Fifo_Write_Toggle_Rst <= '1';
u_Data_Sync_Toggle_Rst <= '1';
u_Data_Sync_Toggle_Rst_Tx <= '1';
u_Data_Sync_Toggle_Tx <= '0';
u_Data_Sync_Toggle <= '0';
u_Accept_Setup_Data_Set <= '0';
u_Input_Buffer_Loaded_Rst <= '1';
state_ind_pd <= "0000000";
u_CRC16_En <= '0';
u_CRC16_Input_Mux <= '0';
u_Send_Packet <= '0';
u_CRC16_Rst_Fsm <= '1';
u_Cnt_Bytes_Sent_Rst <= '1';
u_In_Packet_Complete_Set <= '0';
u_NAK_Sent <= '0';
u_Frame_Index_Latch <= '0';
u_Endp_Nr_Latch <= '0';
u_Cnt_Bytes_Sent_Latch <= '0';
u_Send_Zero_Length_Packet_Ack_Set <= '0';
u_Send_Zero_Length_Packet_Clear <= '0';
u_Store_Packet_State <= '0';
u_In_ACK <= '0';
u_Cnt_Timeout_CE <= '0';
u_Cnt_Timeout_Rst <= '0';
u_Resend_Set_Fsm <= '0';
case (state) is
when IDLE =>
u_CRC16_Rst_Fsm <= '0';
state_ind_pd <= "0000001";
u_CRC16_Input_Mux <= '1';
if (u_Rx_Packet_Received = '1' and u_RxActive = '1' and u_RxEvent = "01") then --Packet data received over ULPI
if ((u_Rx_Data(3 downto 0) = PID_OUT) or (u_Rx_Data(3 downto 0) = PID_IN) or (u_Rx_Data(3 downto 0) = PID_SETUP) or (u_Rx_Data(3 downto 0) = PID_SOF))then --check for valid PID
u_PID_Field_Latch <= '1';
next_state <= DECODE_PID;
else
next_state <= IGNORE_PACKET;
end if;
end if;
when IGNORE_PACKET =>
if (u_RxEvent = "00") then
next_state <= IDLE;
end if;
when DECODE_PID =>
state_ind_pd <= "0000010";
if (((u_PID_Field = PID_OUT) or (u_PID_Field = PID_IN) or (u_PID_Field = pid_SETUP)) and (u_RxActive = '1' and u_RxEvent = "01"))then
if(u_Rx_Packet_Received = '1') then --if this is a token, store the first byte
u_Token_PID_Latch <= '1';
u_Token_Byte1_Latch <= '1';
u_CRC16_Input_Mux <= '1';
if (u_PID_Field = PID_SOF) then
u_Frame_Index_Latch <= '1';
end if;
next_state <= TOKEN;
end if;
elsif ((u_PID_Field = PID_ACK) and (u_RxActive = '1' and u_RxEvent = "01")) then
next_state <= IDLE;
elsif ((u_PID_Field = PID_NAK) and (u_RxActive = '1' and u_RxEvent = "01")) then
next_state <= IDLE;
else
packet_err <= '1';
if (u_RxActive = '0' or u_RxEvent /= "01") then
next_state <= IDLE;
end if;
end if;
when TOKEN =>
u_CRC16_Input_Mux <= '1';
u_Input_Buffer_Loaded_Rst <= '0';
u_Fifo_Write_Toggle_Rst <= '0';
state_ind_pd <= "0000110";
if (u_RxActive = '1' and u_RxEvent = "01") then
if(u_Rx_Packet_Received = '1') then --if packet data is valid, store the second byte of the token
u_Token_Byte2_Latch <= '1';
if (u_PID_Field = PID_SOF) then
next_state <= IDLE;
else
next_state <= CHECK_TOKEN_PID;
end if;
end if;
else
packet_err <= '1';
if (u_RxActive = '0' or u_RxEvent /= "01") then
next_state <= IDLE;
end if;
end if;
when CHECK_TOKEN_PID => --decide by which state machine the packet will be processed; if we are dealing with a SETUP/OUT packet, store it first
state_ind_pd <= "0000111";
if ((u_CRC5_Output = u_CRC5_Field) and (u_Device_Address = u_DEVICEADDR)) then --check CRC and device address
if ((u_PID_Field = PID_OUT) or (u_PID_Field = pid_SETUP)) then
u_Endp_Nr_Latch <= '1';
if (u_PID_Field = pid_SETUP) then
u_Data_Sync_Toggle_Rst <= '0';
u_Data_Sync_Toggle_Rst_Tx <= '0';
end if;
next_state <= WAIT_DATA_PID;
elsif (u_PID_Field = PID_IN) then
u_Endp_Nr_Latch <= '1';
next_state <= PL_TOP;
elsif (u_USB_Mode = '1' and u_Token_PID = PID_PING) then --Dev_HS-ping
next_state <= DEV_DO_HSPING;
elsif (u_Token_PID = PID_SOF) then
next_state <= IDLE;
else
next_state <= IDLE;
end if;
else
if (u_RxActive = '0') then
next_state <= IDLE;
end if;
end if;
when WAIT_DATA_PID => --wait for incoming packet
state_ind_pd <= "0001000";
u_CRC16_Input_Mux <= '1';
if (u_Rx_Packet_Received = '1' and u_RxActive = '1' and u_RxEvent = "01") then
u_PID_Field_Latch <= '1';
u_Buffer_Available_Latch <= '1';
next_state <= STORE_PACKET_STATE;
end if;
when STORE_PACKET_STATE =>
state_ind_pd <= "0001001";
u_CRC16_Input_Mux <= '1';
u_Store_Packet_State <= '1';
if ( (u_Token_PID = PID_OUT) or (u_Token_PID = PID_SETUP) ) then
if ((u_PID_Field = PID_DATA0) or (u_PID_Field = PID_DATA1) or (u_PID_Field = PID_DATA2) or (u_PID_Field = PID_MDATA) or (u_PID_Field = PID_SETUP)) then
if (u_Rx_Packet_Received = '1' and u_RxActive = '1' and u_RxEvent = "01") then --store data
u_CRC16_En <= '1';
if (u_Buffer_Available = '1') then --if PID valid and space is available in the input buffer, store the packet
u_Store_Packet <= '1';
end if;
elsif (u_RxActive /= '1' or u_RxEvent /= "01") then --advance to next state when the packet has ended
u_End_Packet_Set <= '1';
next_state <= PL_TOP;
end if;
else
next_state <= ERROR;
end if;
else
next_state <= PL_TOP;
end if;
when PL_TOP => --decide by which state machine the packet will be processed
state_ind_pd <= "0001010";
if (u_Token_PID = PID_OUT or u_Token_PID = PID_SETUP) then --Device_Do_OUT
u_Send_Zero_Length_Packet_Clear <= '1';
if ((u_Token_PID = PID_SETUP) and u_Endp_Type /= CONTROL) then
next_state <= IDLE; --ABORT PACKET, take no action
elsif ((u_Token_PID = PID_SETUP and u_Endp_Type = CONTROL) or u_Token_PID = PID_OUT) then
if (u_Endp_Type = ISOCHRONOUS) then --Dev_Do_IschO
next_state <= DEV_DO_ISCHO;
elsif ((u_USB_Mode = '0' and (u_Endp_Type = CONTROL or u_Endp_Type = BULK)) or u_Endp_Type = INTERRUPT) then --Dev_Do-BCINTO
next_state <= DEV_DO_BCINTO;
elsif (u_USB_Mode = '1' and (u_Endp_Type = CONTROL or u_Endp_Type = BULK)) then --Dev_Do_BCO
next_state <= DEV_DO_BCO;
else -- should not occur, undifined state
next_state <= IDLE;
end if;
else -- should not occur, undifined state
next_state <= IDLE;
end if;
elsif (u_Token_PID = PID_IN) then --Device_do_IN
u_CRC16_Rst_Fsm <= '0';
if (u_Endp_Type = CONTROL or u_Endp_Type = BULK or u_Endp_Type = INTERRUPT) then --Dev_Do_BCINTI
next_state <= DEV_DO_BCINTI;
elsif (u_Endp_Type = ISOCHRONOUS) then --Dev_Do_IsochI
next_state <= DEV_DO_ISOCHI;
end if;
else --ABORT/IGNORE data
next_state <= IDLE;
end if;
-------------------------------------------------------------------------------------------------
---------- Dev_Do_BCINTO Not tested-------------------------------------------------------------------------
when DEV_DO_BCINTO =>
state_ind_pd <= "0001011";
if (u_Token_PID = PID_OUT and ((u_PID_Field = PID_DATA0) or (u_PID_Field = PID_DATA1) or (u_PID_Field = PID_DATA2) or (u_PID_Field = PID_MDATA))) then
if (u_Data_Pid_Sync /= u_PID_Field and u_CRC16_Output = "0000000000000000") then --discard_data
u_Fifo_Write_Toggle_Set <= '0';
u_Fifo_Rst <= '1';
next_state <= DOPKT;
elsif (u_Data_Pid_Sync = u_PID_Field and u_CRC16_Output = "0000000000000000" and u_Buffer_Available = '1') then
u_Accept_Data_Set <= '1';--accept_data
u_Data_Sync_Toggle <= '1'; --toggle sequence bit
u_Fifo_Write_Toggle_Set <= '1';
next_state <= DOPKT;
elsif (u_Data_Pid_Sync = u_PID_Field and u_CRC16_Output = "0000000000000000" and u_Buffer_Available = '0') then
--issue NAK
u_Send_PID_CMD <= '1';
u_Tx_Pid <= PID_NAK;
u_Send_Last <= '1';
----------
if (u_Tx_Cmd_Done = '1') then
u_NAK_Sent <= '1';
next_state <= IDLE;
end if;
elsif (u_Endp_Stall = '1') then
--issue STALL
u_Send_PID_CMD <= '1';
u_Tx_Pid <= PID_STALL;
u_Send_Last <= '1';
---------------
u_Fifo_Rst <= '1';--reset FIFO
if (u_Tx_Cmd_Done = '1') then
next_state <= IDLE;
end if;
end if;
elsif (u_Token_PID = PID_SETUP and u_PID_Field = PID_DATA0) then
if (u_Buffer_Available = '0') then
next_state <= IDLE;
elsif (u_Buffer_Available = '1' and u_CRC16_Output = "0000000000000000") then
u_Accept_Setup_Data_Set <= '1';
u_Data_Sync_Toggle <= '1'; --toggle sequence bit
u_Fifo_Write_Toggle_Set <= '1';
next_state <= DOPKT;
else --invalid
u_Fifo_Rst <= '1';--reset FIFO
next_state <= IDLE;
end if;
else
u_Fifo_Rst <= '1';--reset FIFO
next_state <= IDLE;
end if;
when DOPKT =>
state_ind_pd <= "0001100";
--issue ACK
u_Send_PID_CMD <= '1';
u_Tx_Pid <= PID_ACK;
u_Send_Last <= '1';
----------
if (u_Tx_Cmd_Done = '1') then
next_state <= IDLE;
end if;
-------------------------------------------------------------------------------------------------------------
----------Dev_HS_BCO-----------------------------------------------------------------------------------------
when DEV_DO_BCO =>
--state_ind_pd <= "0001101";
if (u_Token_PID = PID_OUT and ((u_PID_Field = PID_DATA0) or (u_PID_Field = PID_DATA1) or (u_PID_Field = PID_DATA2) or (u_PID_Field = PID_MDATA))) then
state_ind_pd <= "0001101";
if (u_Data_Pid_Sync = u_PID_Field and u_CRC16_Residual = "1000000000001101" and u_Buffer_Available = '0') then
--issue NAK
u_Send_PID_CMD <= '1';
u_Tx_Pid <= PID_NAK;
u_Send_Last <= '1';
----------
u_Fifo_Rst <= '1';--reset FIFO
if (u_Tx_Cmd_Done = '1') then
u_NAK_Sent <= '1';
next_state <= IDLE;
end if;
elsif (u_Data_Pid_Sync /= u_PID_Field and u_CRC16_Residual = "1000000000001101") then
--issue ACK
u_Send_PID_CMD <= '1';
u_Tx_Pid <= PID_ACK;
u_Send_Last <= '1';
----------
u_Fifo_Rst <= '1';--reset FIFO
u_Fifo_Write_Toggle_Set <= '0';
if (u_Tx_Cmd_Done = '1') then
next_state <= IDLE;
end if;
elsif (u_Data_Pid_Sync = u_PID_Field and u_CRC16_Residual = "1000000000001101" and u_Buffer_Available = '1') then
u_Accept_Data_Set <= '1';--accept_data
u_Data_Sync_Toggle <= '1'; --toggle sequence bit
u_Fifo_Write_Toggle_Set <= '1';
next_state <= DSPACE;
elsif (u_Endp_Stall = '1') then
--issue STALL
u_Send_PID_CMD <= '1';
u_Tx_Pid <= PID_STALL;
u_Send_Last <= '1';
---------------
u_Fifo_Rst <= '1';--reset FIFO
if (u_Tx_Cmd_Done = '1') then
next_state <= IDLE;
end if;
else
u_Fifo_Rst <= '1';--reset FIFO
next_state <= IDLE;
end if;
elsif (u_Token_PID = PID_SETUP and u_PID_Field = PID_DATA0) then
state_ind_pd <= "1111111";
if (u_Buffer_Available = '0') then
--u_Fifo_Rst <= '1';--reset FIFO
next_state <= IDLE;
elsif (u_Buffer_Available = '1' and u_CRC16_Residual = "1000000000001101") then
u_Accept_Setup_Data_Set <= '1';
u_Data_Sync_Toggle <= '1'; --toggle sequence bit
u_Fifo_Write_Toggle_Set <= '1';
next_state <= DSPACE;
else --invalid
u_Fifo_Rst <= '1';--reset FIFO
next_state <= IDLE;
end if;
else --discard data
state_ind_pd <= "0000000";
u_Fifo_Rst <= '1';--reset FIFO
next_state <= IDLE;
end if;
when DSPACE =>
state_ind_pd <= "0001110";
--issue ACK
u_Send_PID_CMD <= '1';
u_Tx_Pid <= PID_ACK;
u_Send_Last <= '1';
----------
--u_Fifo_Rst <= '1';--reset FIFO
if (u_Tx_Cmd_Done = '1') then
next_state <= IDLE;
end if;
----------------------------------------------------------------------------------------------
--------Dev_Do_IsochO-------------------------------------------------------------------------
when DEV_DO_ISCHO =>
state_ind_pd <= "0001111";
if (((u_PID_Field = PID_DATA0) or (u_PID_Field = PID_DATA1) or (u_PID_Field = PID_DATA2) or (u_PID_Field = PID_MDATA)) and u_CRC16_Output = "0000000000000000") then
u_Accept_Data_Set <= '1';--accept_data
u_Fifo_Write_Toggle_Set <= '1';
next_state <= DDO_IODATA;
else
--Dev_Record_error
next_state <= DDO_IODATA;
end if;
when DDO_IODATA =>
state_ind_pd <= "0010000";
--Respond Dev Do next data??
u_Send_PID_CMD <= '1';
u_Tx_Pid <= PID_NAK;
u_Send_Last <= '1';
----------
if (u_Tx_Cmd_Done = '1') then
u_NAK_Sent <= '1';
next_state <= IDLE;
end if;
--------------------------------------------------------------------------------------------------
------------Dev_Do_IsochI-------------------------------------------------------------------------
when DEV_DO_ISOCHI =>
--issue packet
state_ind_pd <= "0010001";
next_state <= D_DO_IINEXT;
when D_DO_IINEXT =>
--RespondDev Do_next_data
u_Send_PID_CMD <= '1';
u_Tx_Pid <= PID_NAK;
u_Send_Last <= '1';
----------
if (u_Tx_Cmd_Done = '1') then
u_NAK_Sent <= '1';
next_state <= IDLE;
end if;
----------------------------------------------------------------------------------------------------
-------------Dev_DoBCINTI---------------------------------------------------------------------------
when DEV_DO_BCINTI =>
state_ind_pd <= "0010010";
if (u_Send_Zero_Length_Packet = '1') then --Zero Length packets use a different framework
next_state <= DEV_DO_BCINTI_ZERO_LENGTH;
elsif (u_Endpt_Ready = '1') then -- send packet data
next_state <= DEV_DO_BCINTI_PACKET;
elsif (u_Endpt_Ready = '0') then --issue a NAK handshake packet
next_state <= DEV_DO_BCINTI_NAK;
elsif (u_Endp_Stall = '1') then
next_state <= DEV_DO_BCINTI_STALL;
else
next_state <= IDLE;
end if;
when DEV_DO_BCINTI_PACKET =>
state_ind_pd <= "1000000";
if (u_Endpt_Ready = '1') then
u_In_Token_Received_Fsm <= '1';
u_Send_Packet <= '1';
if (axis_32_to_8_latency_comp_out = '1') then
u_Tx_Pid <= u_Data_Pid_Sync_Tx;
u_Send_PID_CMD <= '1';
u_Tx_Data_Loc <= u_BRAM_Read_Data;
if (u_Tx_Data_En = '1') then
u_CRC16_En <= u_CRC16_En_Ulpi;
if (u_Send_Packet_Last = '1') then
next_state <= SEND_CRC16_1;
end if;
end if;
end if;
else
next_state <= ERROR;
end if;
when DEV_DO_BCINTI_ZERO_LENGTH =>
state_ind_pd <= "1100000";
if (u_Send_Zero_Length_Packet = '1') then
u_In_ACK <= '1';
u_In_Token_Received_Fsm <= '1';
u_Send_PID_CMD <= '1';
u_Tx_Pid <= u_Data_Pid_Sync;
u_Tx_Data_Loc <= u_CRC16_Output(15 downto 8);
if (u_Tx_Pid_Phase_Done = '1') then
u_Cnt_Bytes_Sent_Latch <= '1';
next_state <= SEND_CRC16_2;
end if;
else
next_state <= ERROR;
end if;
when DEV_DO_BCINTI_NAK =>
state_ind_pd <= "1110000";
--issue NAK
u_Send_PID_CMD <= '1';
u_Tx_Pid <= PID_NAK;
u_Send_Last <= '1';
----------
if (u_Tx_Cmd_Done = '1') then
u_NAK_Sent <= '1';
next_state <= IDLE;
end if;
when DEV_DO_BCINTI_STALL =>
state_ind_pd <= "1111000";
--issue STALL
u_Send_PID_CMD <= '1';
u_Tx_Pid <= PID_STALL;
u_Send_Last <= '1';
---------------
if (u_Tx_Cmd_Done = '1') then
next_state <= IDLE;
end if;
when SEND_CRC16_1 => --send first CRC16 byte
u_Cnt_Bytes_Sent_Latch <= '1';
state_ind_pd <= "0010011";
if(u_Tx_Data_En = '1') then
u_Tx_Data_Loc <= u_CRC16_Output(15 downto 8);
next_state <= SEND_CRC16_2;
else
u_Tx_Data_Loc <= u_BRAM_Read_Data;
end if;
when SEND_CRC16_2 => --send second CRC16 byte
state_ind_pd <= "0010100";
u_Tx_Data_Loc <= u_CRC16_Output(7 downto 0);
u_Send_Last <= '1';
next_state <= SEND_CRC16_END;
when SEND_CRC16_END =>
u_Cnt_Bytes_Sent_Rst <= '0';
u_Send_Last <= '1';
if (u_Tx_Cmd_Done = '1') then
u_Tx_Data_Loc <= (others => '0');
next_state <= DEV_RESP;
else
if(u_Tx_Data_En = '0') then
u_Tx_Data_Loc <= u_CRC16_Output(7 downto 0);
else
u_Tx_Data_Loc <= (others => '0');
end if;
end if;
when DEV_RESP => --wait for host to respond with a hanshake packet
state_ind_pd <= "0010101";
u_Cnt_Timeout_CE <= '1';
u_Cnt_Timeout_Rst <= '1';
if (u_Rx_Packet_Received = '1' and u_RxActive = '1' and u_RxEvent = "01") then
u_PID_Field_Latch <= '1';
next_state <= DEV_DO_BCINTO_CHECK_PID;
elsif (u_Cnt_Timeout = TIMEOUT) then
u_Cnt_Timeout_Rst <= '0';
u_Resend_Set_Fsm <= '1';
next_state <= IDLE;
end if;
when DEV_DO_BCINTO_CHECK_PID => --check host response PID
state_ind_pd <= "0010110";
u_Cnt_Timeout_Rst <= '1';
if (u_PID_Field = PID_ACK) then
--Respond dev do next data
u_In_Packet_Complete_Set <= '1'; --IN Packet completed succesfully
u_Data_Sync_Toggle_Tx <= '1'; --Toggle data sync bit
u_Send_Zero_Length_Packet_Ack_Set <= '1';
u_Send_Zero_Length_Packet_Clear <= '1';
-------------------
next_state <= IDLE;
elsif (u_PID_Field = PID_SOF and (u_RxActive = '1' and u_RxEvent = "01")) then
u_Frame_Index_Latch <= '1';
next_state <= DEV_DO_BCINTO_SOF;
else
u_Resend_Set_Fsm <= '1';
next_state <= IDLE;
end if;
when DEV_DO_BCINTO_SOF => --new state
state_ind_pd <= "0010110";
u_Cnt_Timeout_Rst <= '1';
if (u_RxActive = '1' and u_RxEvent = "01") then
end if;
next_state <= DEV_RESP;
------------------------------------------------------------------------------------------------------
-----------Dev_HS_ping Not Tested--------------------------------------------------------------------------------
when DEV_DO_HSPING =>
state_ind_pd <= "0010111";
if (u_Buffer_Available = '0') then
--issue NAK
u_Send_PID_CMD <= '1';
u_Tx_Pid <= PID_NAK;
u_Send_Last <= '1';
----------
if (u_Tx_Cmd_Done = '1') then
u_NAK_Sent <= '1';
next_state <= IDLE;
end if;
elsif (u_Buffer_Available = '1') then
--issue ACK
u_Send_PID_CMD <= '1';
u_Tx_Pid <= PID_ACK;
u_Send_Last <= '1';
----------
if (u_Tx_Cmd_Done = '1') then
next_state <= IDLE;
end if;
elsif (u_Endp_Stall = '1') then
--issue STALL
u_Send_PID_CMD <= '1';
u_Tx_Pid <= PID_STALL;
u_Send_Last <= '1';
---------------
if (u_Tx_Cmd_Done = '1') then
next_state <= IDLE;
end if;
else
next_state <= IDLE;
end if;
when others =>
state_ind_pd <= "1111111";
next_state <= IDLE;
end case;
end process;
end Behavioral;
|
mit
|
25c26500185444e1f047bcf2caa75db3
| 0.503314 | 3.5169 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/CvtColor_1_sectormb6.vhd
| 1 | 2,653 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity CvtColor_1_sectormb6_rom is
generic(
dwidth : integer := 2;
awidth : integer := 3;
mem_size : integer := 6
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of CvtColor_1_sectormb6_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem : mem_array := (
0 => "00", 1 => "10", 2 to 3=> "01", 4 => "11", 5 => "00" );
attribute syn_rom_style : string;
attribute syn_rom_style of mem : signal is "select_rom";
attribute ROM_STYLE : string;
attribute ROM_STYLE of mem : signal is "distributed";
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity CvtColor_1_sectormb6 is
generic (
DataWidth : INTEGER := 2;
AddressRange : INTEGER := 6;
AddressWidth : INTEGER := 3);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of CvtColor_1_sectormb6 is
component CvtColor_1_sectormb6_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
CvtColor_1_sectormb6_rom_U : component CvtColor_1_sectormb6_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0);
end architecture;
|
mit
|
fa39b96507f198f878a1b166b9f41e58
| 0.551828 | 3.532623 | false | false | false | false |
Digilent/vivado-library
|
ip/axi_ps2_1.0/src/axi_ps2_v1_0.vhd
| 1 | 5,786 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_ps2_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S_AXI
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 5
);
port (
-- Users to add ports here
PS2_Data_I : in std_logic;
PS2_Data_O : out std_logic;
PS2_Data_T : out std_logic;
PS2_Clk_I : in std_logic;
PS2_Clk_O : out std_logic;
PS2_Clk_T : out std_logic;
PS2_interrupt : out std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S_AXI
S_AXI_aclk : in std_logic;
S_AXI_aresetn : in std_logic;
S_AXI_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_awprot : in std_logic_vector(2 downto 0);
S_AXI_awvalid : in std_logic;
S_AXI_awready : out std_logic;
S_AXI_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_wvalid : in std_logic;
S_AXI_wready : out std_logic;
S_AXI_bresp : out std_logic_vector(1 downto 0);
S_AXI_bvalid : out std_logic;
S_AXI_bready : in std_logic;
S_AXI_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_arprot : in std_logic_vector(2 downto 0);
S_AXI_arvalid : in std_logic;
S_AXI_arready : out std_logic;
S_AXI_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_rresp : out std_logic_vector(1 downto 0);
S_AXI_rvalid : out std_logic;
S_AXI_rready : in std_logic
);
end axi_ps2_v1_0;
architecture arch_imp of axi_ps2_v1_0 is
-- component declaration
component axi_ps2_v1_0_S_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 5
);
port (
lTxDataReg : out std_logic_vector (31 downto 0);
lRxDataReg : in std_logic_vector (31 downto 0);
lTxTrig : out std_logic;
lRxAck : out std_logic;
lStatusReg : in std_logic_vector (31 downto 0);
IsrBitTxNoack : in std_logic;
IsrBitTxAck : in std_logic;
IsrBitRxOvf : in std_logic;
IsrBitRxErr : in std_logic;
IsrBitRxFull : in std_logic;
SrstOut : out std_logic;
IntrOut : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component axi_ps2_v1_0_S_AXI;
signal lCtlTxDataReg : std_logic_vector (31 downto 0);
signal lCtlRxDataReg : std_logic_vector (31 downto 0);
signal lCtlTxTrig : std_logic;
signal lCtlRxAck : std_logic;
signal lCtlSrst : std_logic;
signal lCtlStatusReg : std_logic_vector (31 downto 0);
signal lCtlIsrBitTxNoAck : std_logic;
signal lCtlIsrBitTxAck : std_logic;
signal lCtlIsrBitRxOvf : std_logic;
signal lCtlIsrBitRxErr : std_logic;
signal lCtlIsrBitRxFull : std_logic;
begin
axi_ps2_v1_0_S_AXI_inst : axi_ps2_v1_0_S_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH
)
port map (
lTxDataReg => lCtlTxDataReg,
lRxDataReg => lCtlRxDataReg,
lTxTrig => lCtlTxTrig,
lRxAck => lCtlRxAck,
lStatusReg => lCtlStatusReg,
IsrBitTxNoAck => lCtlIsrBitTxNoack,
IsrBitTxAck => lCtlIsrBitTxAck,
IsrBitRxOvf => lCtlIsrBitRxOvf,
IsrBitRxErr => lCtlIsrBitRxErr,
IsrBitRxFull => lCtlIsrBitRxFull,
SrstOut => lCtlSrst,
IntrOut => PS2_interrupt,
S_AXI_ACLK => S_AXI_aclk,
S_AXI_ARESETN => S_AXI_aresetn,
S_AXI_AWADDR => S_AXI_awaddr,
S_AXI_AWPROT => S_AXI_awprot,
S_AXI_AWVALID => S_AXI_awvalid,
S_AXI_AWREADY => S_AXI_awready,
S_AXI_WDATA => S_AXI_wdata,
S_AXI_WSTRB => S_AXI_wstrb,
S_AXI_WVALID => S_AXI_wvalid,
S_AXI_WREADY => S_AXI_wready,
S_AXI_BRESP => S_AXI_bresp,
S_AXI_BVALID => S_AXI_bvalid,
S_AXI_BREADY => S_AXI_bready,
S_AXI_ARADDR => S_AXI_araddr,
S_AXI_ARPROT => S_AXI_arprot,
S_AXI_ARVALID => S_AXI_arvalid,
S_AXI_ARREADY => S_AXI_arready,
S_AXI_RDATA => S_AXI_rdata,
S_AXI_RRESP => S_AXI_rresp,
S_AXI_RVALID => S_AXI_rvalid,
S_AXI_RREADY => S_AXI_rready
);
-- Add user logic here
Wrapper: entity work.Ps2InterfaceWrapper
port map (
PS2_Data_I => PS2_Data_I,
PS2_Data_O => PS2_Data_O,
PS2_Data_T => PS2_Data_T,
PS2_Clk_I => PS2_Clk_I,
PS2_Clk_O => PS2_Clk_O,
PS2_Clk_T => PS2_Clk_T,
clk => S_AXI_aclk,
rst => S_AXI_aresetn,
lSrst => lCtlSrst,
lTxDataReg => lCtlTxDataReg,
lTxTrig => lCtlTxTrig,
lRxDataReg => lCtlRxDataReg,
lRxAck => lCtlRxAck,
IsrBitTxNoAck => lCtlIsrBitTxNoack,
IsrBitTxAck => lCtlIsrBitTxAck,
IsrBitRxOvf => lCtlIsrBitRxOvf,
IsrBitRxErr => lCtlIsrBitRxErr,
IsrBitRxFull => lCtlIsrBitRxFull,
lStatusReg => lCtlStatusReg
);
-- User logic ends
end arch_imp;
|
mit
|
6be6a1502f6c15e805f7eccfd580f41d
| 0.64898 | 2.686165 | false | false | false | false |
Digilent/vivado-library
|
ip/axi_ps2_1.0/src/Ps2InterfaceWrapper.vhd
| 1 | 7,161 |
------------------------------------------------------------------------------
--
-- File: Ps2InterfaceWrapper.vhd
-- Author: Sergiu Arpadi
-- Original Project: AXI PS2
-- Date: 10 October 2017
--
-------------------------------------------------------------------------------
--Copyright (c) 2017 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
-------------------------------------------------------------------------------
--
-- Purpose:
--This module is a wrapper for the PS/2 module used to faciliate the addition
--of the TX and RX FIFOs. It also contains some additional logic strictly related
--to these entities.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Ps2InterfaceWrapper is
Port (
PS2_Data_I : in std_logic;
PS2_Data_O : out std_logic;
PS2_Data_T : out std_logic;
PS2_Clk_I : in std_logic;
PS2_Clk_O : out std_logic;
PS2_Clk_T : out std_logic;
clk : in std_logic;
rst : in std_logic;
lSrst : in std_logic;
lTxDataReg : in std_logic_vector (31 downto 0);
lTxTrig : in std_logic;
lRxDataReg : out std_logic_vector (31 downto 0);
lRxAck : in std_logic;
-- ISR signals
IsrBitTxNoAck : out std_logic;
IsrBitTxAck : out std_logic;
IsrBitRxOvf : out std_logic;
IsrBitRxErr : out std_logic;
IsrBitRxFull : out std_logic;
-- Status register
lStatusReg : out std_logic_vector (31 downto 0)
);
end Ps2InterfaceWrapper;
architecture Behavioral of Ps2InterfaceWrapper is
------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------
signal lRxDataBuf : std_logic_vector(7 downto 0);
signal lTxBufFlag : std_logic := '0';
signal lBusy : std_logic;
signal lErrNack : std_logic;
signal lErrPar : std_logic;
signal lAck : std_logic;
signal lReset : std_logic := '0';
signal lWrite : std_logic := '0';
signal lRead : std_logic := '0';
--TX FIFO signals
signal TxDin : std_logic_vector (7 downto 0);
signal TxWrEn : std_logic := '0';
signal TxRdEn : std_logic := '0';
signal TxDout : std_logic_vector (7 downto 0);
signal TxFull : std_logic;
signal TxEmpty : std_logic;
--RX FIFO signals
signal RxDin : std_logic_vector (7 downto 0);
signal RxWrEn : std_logic := '0';
signal RxRdEn : std_logic := '0';
signal RxDout : std_logic_vector (7 downto 0);
signal RxFull : std_logic;
signal RxEmpty : std_logic;
COMPONENT fifo_generator_0
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
--------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------
-- AXI Lite Status register signal assignment
lStatusReg (0) <= TxFull;
lStatusReg (1) <= TxEmpty;
lStatusReg (2) <= RxFull;
lStatusReg (3) <= RxEmpty;
lStatusReg (31 downto 4) <= (others => '0'); -- bits that are not used are always 0
-- ISR interrupts constructed
IsrBitRxOvf <= lRead and RxFull;
IsrBitTxAck <= lAck;
IsrBitTxNoack <= lErrNack;
IsrBitRxErr <= lErrPar;
IsrBitRxFull <= not RxEmpty;
lReset <= (not rst) or lSrst; --not used
--------------------------------------------------------------------------------
--FIFOs
--------------------------------------------------------------------------------
-- AXI Lite data registers
TxDin <= lTxDataReg (7 downto 0);
lRxDataReg (7 downto 0) <= RxDout;
TxWrEn <= lTxTrig; --write enable connected to AXI Lite logic. Writes new TX data to TX FIFO
RxWrEn <= lRead; --write enable connected to AXI Lite logic. Writes new RX data to RX FIFO
RxRdEn <= lRxAck; --reads data out of RX FIFO and passes it to RX Data register
--------------------------------------------------------------------------------
Ps2Interface: entity work.Ps2Interface
port map (
PS2_Data_I => PS2_Data_I,
PS2_Data_O => PS2_Data_O,
PS2_Data_T => PS2_Data_T,
PS2_Clk_I => PS2_Clk_I,
PS2_Clk_O => PS2_Clk_O,
PS2_Clk_T => PS2_Clk_T,
clk => clk,
rst => lReset,
tx_data => TxDout,
write_data => lWrite,
rx_data => RxDin,
read_data => lRead,
ack => lAck,
busy => lBusy,
err_par => lErrPar,
err_nack => lErrNack
);
--------------------------------------------------------------------------------
TxFIFO: fifo_generator_0
PORT MAP (
clk => clk,
srst => lReset,
din => TxDin,
wr_en => TxWrEn,
rd_en => TxRdEn,
dout => TxDout,
full => TxFull,
empty => TxEmpty
);
--------------------------------------------------------------------------------
RxFIFO: fifo_generator_0
PORT MAP (
clk => clk,
srst => lReset,
din => RxDin,
wr_en => RxWrEn,
rd_en => RxRdEn,
dout => RxDout,
full => RxFull,
empty => RxEmpty
);
--------------------------------------------------------------------------------
--this process passes he next TX data byte from the TX FIFO to the PS/2 logic when
--data is available in the FIFO and the PS/2 core is not busy
OS_LWRITE_TXRDEN: process (clk)
variable count : integer range 0 to 1;
begin
if rising_edge (clk) then
if TxEmpty = '1' or lBusy = '1' then
count := 1;
lWrite <= '0';
TxRdEn <= '0';
elsif count = 1 then
lWrite <= '1';
TxRdEn <= '1';
else
count := 0;
lWrite <= '0';
TxRdEn <= '0';
end if;
end if;
end process;
end Behavioral;
|
mit
|
1b32e0421846704e8d4654b84f54808a
| 0.547968 | 4.002795 | false | false | false | false |
Digilent/vivado-library
|
ip/video_scaler/hdl/vhdl/AXIvideo2Mat.vhd
| 1 | 66,885 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity AXIvideo2Mat is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
stream_in_TDATA : IN STD_LOGIC_VECTOR (23 downto 0);
stream_in_TVALID : IN STD_LOGIC;
stream_in_TREADY : OUT STD_LOGIC;
stream_in_TKEEP : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TSTRB : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TID : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
img_rows_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
img_rows_V_empty_n : IN STD_LOGIC;
img_rows_V_read : OUT STD_LOGIC;
img_cols_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
img_cols_V_empty_n : IN STD_LOGIC;
img_cols_V_read : OUT STD_LOGIC;
img_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_full_n : IN STD_LOGIC;
img_data_stream_0_V_write : OUT STD_LOGIC;
img_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_full_n : IN STD_LOGIC;
img_data_stream_1_V_write : OUT STD_LOGIC;
img_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_full_n : IN STD_LOGIC;
img_data_stream_2_V_write : OUT STD_LOGIC;
img_rows_V_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
img_rows_V_out_full_n : IN STD_LOGIC;
img_rows_V_out_write : OUT STD_LOGIC;
img_cols_V_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
img_cols_V_out_full_n : IN STD_LOGIC;
img_cols_V_out_write : OUT STD_LOGIC );
end;
architecture behav of AXIvideo2Mat is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (7 downto 0) := "00001000";
constant ap_ST_fsm_pp1_stage0 : STD_LOGIC_VECTOR (7 downto 0) := "00010000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (7 downto 0) := "00100000";
constant ap_ST_fsm_pp2_stage0 : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal AXI_video_strm_V_data_V_0_data_out : STD_LOGIC_VECTOR (23 downto 0);
signal AXI_video_strm_V_data_V_0_vld_in : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_vld_out : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_ack_in : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_ack_out : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_payload_A : STD_LOGIC_VECTOR (23 downto 0);
signal AXI_video_strm_V_data_V_0_payload_B : STD_LOGIC_VECTOR (23 downto 0);
signal AXI_video_strm_V_data_V_0_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_data_V_0_sel_wr : STD_LOGIC := '0';
signal AXI_video_strm_V_data_V_0_sel : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_load_A : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_load_B : STD_LOGIC;
signal AXI_video_strm_V_data_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal AXI_video_strm_V_data_V_0_state_cmp_full : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_data_out : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_user_V_0_vld_in : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_vld_out : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_ack_in : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_ack_out : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_payload_A : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_user_V_0_payload_B : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_user_V_0_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_user_V_0_sel_wr : STD_LOGIC := '0';
signal AXI_video_strm_V_user_V_0_sel : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_load_A : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_load_B : STD_LOGIC;
signal AXI_video_strm_V_user_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal AXI_video_strm_V_user_V_0_state_cmp_full : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_data_out : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_last_V_0_vld_in : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_vld_out : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_ack_in : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_ack_out : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_payload_A : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_last_V_0_payload_B : STD_LOGIC_VECTOR (0 downto 0);
signal AXI_video_strm_V_last_V_0_sel_rd : STD_LOGIC := '0';
signal AXI_video_strm_V_last_V_0_sel_wr : STD_LOGIC := '0';
signal AXI_video_strm_V_last_V_0_sel : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_load_A : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_load_B : STD_LOGIC;
signal AXI_video_strm_V_last_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal AXI_video_strm_V_last_V_0_state_cmp_full : STD_LOGIC;
signal AXI_video_strm_V_dest_V_0_vld_in : STD_LOGIC;
signal AXI_video_strm_V_dest_V_0_ack_out : STD_LOGIC;
signal AXI_video_strm_V_dest_V_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal stream_in_TDATA_blk_n : STD_LOGIC;
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal ap_CS_fsm_pp1_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp1_stage0 : signal is "none";
signal ap_enable_reg_pp1_iter1 : STD_LOGIC := '0';
signal ap_block_pp1_stage0 : BOOLEAN;
signal exitcond_i_reg_504 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_reg_513 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp2_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp2_stage0 : signal is "none";
signal ap_enable_reg_pp2_iter1 : STD_LOGIC := '0';
signal ap_block_pp2_stage0 : BOOLEAN;
signal eol_2_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal img_rows_V_blk_n : STD_LOGIC;
signal img_cols_V_blk_n : STD_LOGIC;
signal img_data_stream_0_V_blk_n : STD_LOGIC;
signal img_data_stream_1_V_blk_n : STD_LOGIC;
signal img_data_stream_2_V_blk_n : STD_LOGIC;
signal img_rows_V_out_blk_n : STD_LOGIC;
signal img_cols_V_out_blk_n : STD_LOGIC;
signal t_V_2_reg_278 : STD_LOGIC_VECTOR (31 downto 0);
signal eol_i_reg_289 : STD_LOGIC_VECTOR (0 downto 0);
signal eol_reg_301 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_data_V_1_i_reg_312 : STD_LOGIC_VECTOR (23 downto 0);
signal axi_last_V_3_i_reg_359 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_data_V_3_i_reg_371 : STD_LOGIC_VECTOR (23 downto 0);
signal rows_V_reg_465 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_block_state1 : BOOLEAN;
signal cols_V_reg_470 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_data_V_reg_475 : STD_LOGIC_VECTOR (23 downto 0);
signal tmp_last_V_reg_483 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond4_i_fu_402_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal i_V_fu_407_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_V_reg_499 : STD_LOGIC_VECTOR (31 downto 0);
signal exitcond_i_fu_413_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_state5_pp1_stage0_iter0 : BOOLEAN;
signal ap_predicate_op71_read_state6 : BOOLEAN;
signal ap_block_state6_pp1_stage0_iter1 : BOOLEAN;
signal ap_block_pp1_stage0_11001 : BOOLEAN;
signal j_V_fu_418_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp1_iter0 : STD_LOGIC := '0';
signal brmerge_i_fu_427_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_state8_pp2_stage0_iter0 : BOOLEAN;
signal ap_block_state9_pp2_stage0_iter1 : BOOLEAN;
signal ap_block_pp2_stage0_11001 : BOOLEAN;
signal ap_block_pp1_stage0_subdone : BOOLEAN;
signal ap_enable_reg_pp2_iter0 : STD_LOGIC := '0';
signal ap_CS_fsm_state7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal ap_block_pp2_stage0_subdone : BOOLEAN;
signal ap_phi_mux_eol_2_i_phi_fu_351_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_last_V1_i_reg_247 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none";
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal axi_data_V1_i_reg_257 : STD_LOGIC_VECTOR (23 downto 0);
signal t_V_reg_267 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_phi_mux_eol_i_phi_fu_293_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_mux_axi_last_V_2_i_phi_fu_328_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_mux_p_Val2_s_phi_fu_340_p4 : STD_LOGIC_VECTOR (23 downto 0);
signal ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_323 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_reg_pp1_iter1_p_Val2_s_reg_336 : STD_LOGIC_VECTOR (23 downto 0);
signal ap_block_pp1_stage0_01001 : BOOLEAN;
signal sof_1_i_fu_176 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_user_V_fu_393_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (7 downto 0);
signal ap_idle_pp1 : STD_LOGIC;
signal ap_enable_pp1 : STD_LOGIC;
signal ap_idle_pp2 : STD_LOGIC;
signal ap_enable_pp2 : STD_LOGIC;
signal ap_condition_515 : BOOLEAN;
begin
AXI_video_strm_V_data_V_0_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_data_V_0_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out))) then
AXI_video_strm_V_data_V_0_sel_rd <= not(AXI_video_strm_V_data_V_0_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_data_V_0_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_data_V_0_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_in) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_in))) then
AXI_video_strm_V_data_V_0_sel_wr <= not(AXI_video_strm_V_data_V_0_sel_wr);
end if;
end if;
end if;
end process;
AXI_video_strm_V_data_V_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_data_V_0_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_out)))) then
AXI_video_strm_V_data_V_0_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_in)))) then
AXI_video_strm_V_data_V_0_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_data_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_data_V_0_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_data_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_in)))) then
AXI_video_strm_V_data_V_0_state <= ap_const_lv2_3;
else
AXI_video_strm_V_data_V_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
AXI_video_strm_V_dest_V_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_0_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_ack_out)))) then
AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_0_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_dest_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_vld_in)))) then
AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_dest_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_dest_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_dest_V_0_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_dest_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_dest_V_0_vld_in)))) then
AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_3;
else
AXI_video_strm_V_dest_V_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
AXI_video_strm_V_last_V_0_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_last_V_0_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_out))) then
AXI_video_strm_V_last_V_0_sel_rd <= not(AXI_video_strm_V_last_V_0_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_last_V_0_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_last_V_0_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_in) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_in))) then
AXI_video_strm_V_last_V_0_sel_wr <= not(AXI_video_strm_V_last_V_0_sel_wr);
end if;
end if;
end if;
end process;
AXI_video_strm_V_last_V_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_last_V_0_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_0_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_out)))) then
AXI_video_strm_V_last_V_0_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_0_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_last_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_in)))) then
AXI_video_strm_V_last_V_0_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_last_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_last_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_last_V_0_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_last_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_last_V_0_vld_in)))) then
AXI_video_strm_V_last_V_0_state <= ap_const_lv2_3;
else
AXI_video_strm_V_last_V_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
AXI_video_strm_V_user_V_0_sel_rd_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_user_V_0_sel_rd <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_out))) then
AXI_video_strm_V_user_V_0_sel_rd <= not(AXI_video_strm_V_user_V_0_sel_rd);
end if;
end if;
end if;
end process;
AXI_video_strm_V_user_V_0_sel_wr_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_user_V_0_sel_wr <= ap_const_logic_0;
else
if (((ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_in) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_in))) then
AXI_video_strm_V_user_V_0_sel_wr <= not(AXI_video_strm_V_user_V_0_sel_wr);
end if;
end if;
end if;
end process;
AXI_video_strm_V_user_V_0_state_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
AXI_video_strm_V_user_V_0_state <= ap_const_lv2_0;
else
if ((((ap_const_lv2_2 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_0_vld_in)) or ((ap_const_lv2_3 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_out)))) then
AXI_video_strm_V_user_V_0_state <= ap_const_lv2_2;
elsif ((((ap_const_lv2_1 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_0_ack_out)) or ((ap_const_lv2_3 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_0 = AXI_video_strm_V_user_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_in)))) then
AXI_video_strm_V_user_V_0_state <= ap_const_lv2_1;
elsif (((not(((ap_const_logic_0 = AXI_video_strm_V_user_V_0_vld_in) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_out))) and not(((ap_const_logic_0 = AXI_video_strm_V_user_V_0_ack_out) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_in))) and (ap_const_lv2_3 = AXI_video_strm_V_user_V_0_state)) or ((ap_const_lv2_1 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_ack_out)) or ((ap_const_lv2_2 = AXI_video_strm_V_user_V_0_state) and (ap_const_logic_1 = AXI_video_strm_V_user_V_0_vld_in)))) then
AXI_video_strm_V_user_V_0_state <= ap_const_lv2_3;
else
AXI_video_strm_V_user_V_0_state <= ap_const_lv2_2;
end if;
end if;
end if;
end process;
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_continue = ap_const_logic_1)) then
ap_done_reg <= ap_const_logic_0;
elsif (((exitcond4_i_fu_402_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp1_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
else
if (((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (exitcond_i_fu_413_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
elsif (((exitcond4_i_fu_402_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_enable_reg_pp1_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp1_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp1_iter1 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp1_stage0_subdone)) then
ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0;
elsif (((exitcond4_i_fu_402_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_enable_reg_pp1_iter1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_enable_reg_pp2_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp2_iter0 <= ap_const_logic_0;
else
if (((ap_const_boolean_0 = ap_block_pp2_stage0_subdone) and (ap_phi_mux_eol_2_i_phi_fu_351_p4 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
ap_enable_reg_pp2_iter0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
ap_enable_reg_pp2_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp2_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp2_iter1 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp2_stage0_subdone)) then
ap_enable_reg_pp2_iter1 <= ap_enable_reg_pp2_iter0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state7)) then
ap_enable_reg_pp2_iter1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
axi_data_V1_i_reg_257_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
axi_data_V1_i_reg_257 <= tmp_data_V_reg_475;
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
axi_data_V1_i_reg_257 <= axi_data_V_3_i_reg_371;
end if;
end if;
end process;
axi_data_V_1_i_reg_312_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (exitcond_i_reg_504 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
axi_data_V_1_i_reg_312 <= ap_phi_mux_p_Val2_s_phi_fu_340_p4;
elsif (((exitcond4_i_fu_402_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
axi_data_V_1_i_reg_312 <= axi_data_V1_i_reg_257;
end if;
end if;
end process;
axi_data_V_3_i_reg_371_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
axi_data_V_3_i_reg_371 <= axi_data_V_1_i_reg_312;
elsif (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (eol_2_i_reg_348 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
axi_data_V_3_i_reg_371 <= AXI_video_strm_V_data_V_0_data_out;
end if;
end if;
end process;
axi_last_V1_i_reg_247_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
axi_last_V1_i_reg_247 <= tmp_last_V_reg_483;
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
axi_last_V1_i_reg_247 <= axi_last_V_3_i_reg_359;
end if;
end if;
end process;
axi_last_V_3_i_reg_359_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
axi_last_V_3_i_reg_359 <= eol_reg_301;
elsif (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (eol_2_i_reg_348 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
axi_last_V_3_i_reg_359 <= AXI_video_strm_V_last_V_0_data_out;
end if;
end if;
end process;
eol_2_i_reg_348_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
eol_2_i_reg_348 <= eol_i_reg_289;
elsif (((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (eol_2_i_reg_348 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
eol_2_i_reg_348 <= AXI_video_strm_V_last_V_0_data_out;
end if;
end if;
end process;
eol_i_reg_289_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (exitcond_i_reg_504 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
eol_i_reg_289 <= ap_phi_mux_axi_last_V_2_i_phi_fu_328_p4;
elsif (((exitcond4_i_fu_402_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
eol_i_reg_289 <= ap_const_lv1_0;
end if;
end if;
end process;
eol_reg_301_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (exitcond_i_reg_504 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
eol_reg_301 <= ap_phi_mux_axi_last_V_2_i_phi_fu_328_p4;
elsif (((exitcond4_i_fu_402_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
eol_reg_301 <= axi_last_V1_i_reg_247;
end if;
end if;
end process;
sof_1_i_fu_176_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (exitcond_i_fu_413_p2 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
sof_1_i_fu_176 <= ap_const_lv1_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state3)) then
sof_1_i_fu_176 <= ap_const_lv1_1;
end if;
end if;
end process;
t_V_2_reg_278_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (exitcond_i_fu_413_p2 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter0 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
t_V_2_reg_278 <= j_V_fu_418_p2;
elsif (((exitcond4_i_fu_402_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
t_V_2_reg_278 <= ap_const_lv32_0;
end if;
end if;
end process;
t_V_reg_267_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
t_V_reg_267 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state10)) then
t_V_reg_267 <= i_V_reg_499;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_load_A)) then
AXI_video_strm_V_data_V_0_payload_A <= stream_in_TDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_load_B)) then
AXI_video_strm_V_data_V_0_payload_B <= stream_in_TDATA;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_last_V_0_load_A)) then
AXI_video_strm_V_last_V_0_payload_A <= stream_in_TLAST;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_last_V_0_load_B)) then
AXI_video_strm_V_last_V_0_payload_B <= stream_in_TLAST;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_user_V_0_load_A)) then
AXI_video_strm_V_user_V_0_payload_A <= stream_in_TUSER;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = AXI_video_strm_V_user_V_0_load_B)) then
AXI_video_strm_V_user_V_0_payload_B <= stream_in_TUSER;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (exitcond_i_fu_413_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
brmerge_i_reg_513 <= brmerge_i_fu_427_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
cols_V_reg_470 <= img_cols_V_dout;
rows_V_reg_465 <= img_rows_V_dout;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
exitcond_i_reg_504 <= exitcond_i_fu_413_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
i_V_reg_499 <= i_V_fu_407_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
tmp_data_V_reg_475 <= AXI_video_strm_V_data_V_0_data_out;
tmp_last_V_reg_483 <= AXI_video_strm_V_last_V_0_data_out;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, AXI_video_strm_V_data_V_0_vld_out, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, exitcond4_i_fu_402_p2, ap_CS_fsm_state4, ap_enable_reg_pp1_iter0, ap_block_pp1_stage0_subdone, ap_enable_reg_pp2_iter0, ap_block_pp2_stage0_subdone, tmp_user_V_fu_393_p1)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if ((not(((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((tmp_user_V_fu_393_p1 = ap_const_lv1_0) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_NS_fsm <= ap_ST_fsm_state2;
elsif (((tmp_user_V_fu_393_p1 = ap_const_lv1_1) and (ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_NS_fsm <= ap_ST_fsm_state3;
else
ap_NS_fsm <= ap_ST_fsm_state2;
end if;
when ap_ST_fsm_state3 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when ap_ST_fsm_state4 =>
if (((exitcond4_i_fu_402_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
end if;
when ap_ST_fsm_pp1_stage0 =>
if (not(((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (ap_enable_reg_pp1_iter0 = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0)))) then
ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
elsif (((ap_const_boolean_0 = ap_block_pp1_stage0_subdone) and (ap_enable_reg_pp1_iter0 = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
ap_NS_fsm <= ap_ST_fsm_state7;
else
ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
end if;
when ap_ST_fsm_state7 =>
ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
when ap_ST_fsm_pp2_stage0 =>
if (not(((ap_const_boolean_0 = ap_block_pp2_stage0_subdone) and (ap_enable_reg_pp2_iter0 = ap_const_logic_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)))) then
ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
elsif (((ap_const_boolean_0 = ap_block_pp2_stage0_subdone) and (ap_enable_reg_pp2_iter0 = ap_const_logic_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
ap_NS_fsm <= ap_ST_fsm_state10;
else
ap_NS_fsm <= ap_ST_fsm_pp2_stage0;
end if;
when ap_ST_fsm_state10 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when others =>
ap_NS_fsm <= "XXXXXXXX";
end case;
end process;
AXI_video_strm_V_data_V_0_ack_in <= AXI_video_strm_V_data_V_0_state(1);
AXI_video_strm_V_data_V_0_ack_out_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_i_reg_348, ap_predicate_op71_read_state6, ap_block_pp1_stage0_11001, ap_block_pp2_stage0_11001)
begin
if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (eol_2_i_reg_348 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_predicate_op71_read_state6 = ap_const_boolean_1) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0)) or ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2)))) then
AXI_video_strm_V_data_V_0_ack_out <= ap_const_logic_1;
else
AXI_video_strm_V_data_V_0_ack_out <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_data_V_0_data_out_assign_proc : process(AXI_video_strm_V_data_V_0_payload_A, AXI_video_strm_V_data_V_0_payload_B, AXI_video_strm_V_data_V_0_sel)
begin
if ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_sel)) then
AXI_video_strm_V_data_V_0_data_out <= AXI_video_strm_V_data_V_0_payload_B;
else
AXI_video_strm_V_data_V_0_data_out <= AXI_video_strm_V_data_V_0_payload_A;
end if;
end process;
AXI_video_strm_V_data_V_0_load_A <= (not(AXI_video_strm_V_data_V_0_sel_wr) and AXI_video_strm_V_data_V_0_state_cmp_full);
AXI_video_strm_V_data_V_0_load_B <= (AXI_video_strm_V_data_V_0_state_cmp_full and AXI_video_strm_V_data_V_0_sel_wr);
AXI_video_strm_V_data_V_0_sel <= AXI_video_strm_V_data_V_0_sel_rd;
AXI_video_strm_V_data_V_0_state_cmp_full <= '0' when (AXI_video_strm_V_data_V_0_state = ap_const_lv2_1) else '1';
AXI_video_strm_V_data_V_0_vld_in <= stream_in_TVALID;
AXI_video_strm_V_data_V_0_vld_out <= AXI_video_strm_V_data_V_0_state(0);
AXI_video_strm_V_dest_V_0_ack_out_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_i_reg_348, ap_predicate_op71_read_state6, ap_block_pp1_stage0_11001, ap_block_pp2_stage0_11001)
begin
if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (eol_2_i_reg_348 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_predicate_op71_read_state6 = ap_const_boolean_1) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0)) or ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2)))) then
AXI_video_strm_V_dest_V_0_ack_out <= ap_const_logic_1;
else
AXI_video_strm_V_dest_V_0_ack_out <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_dest_V_0_vld_in <= stream_in_TVALID;
AXI_video_strm_V_last_V_0_ack_in <= AXI_video_strm_V_last_V_0_state(1);
AXI_video_strm_V_last_V_0_ack_out_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_i_reg_348, ap_predicate_op71_read_state6, ap_block_pp1_stage0_11001, ap_block_pp2_stage0_11001)
begin
if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (eol_2_i_reg_348 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_predicate_op71_read_state6 = ap_const_boolean_1) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0)) or ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2)))) then
AXI_video_strm_V_last_V_0_ack_out <= ap_const_logic_1;
else
AXI_video_strm_V_last_V_0_ack_out <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_last_V_0_data_out_assign_proc : process(AXI_video_strm_V_last_V_0_payload_A, AXI_video_strm_V_last_V_0_payload_B, AXI_video_strm_V_last_V_0_sel)
begin
if ((ap_const_logic_1 = AXI_video_strm_V_last_V_0_sel)) then
AXI_video_strm_V_last_V_0_data_out <= AXI_video_strm_V_last_V_0_payload_B;
else
AXI_video_strm_V_last_V_0_data_out <= AXI_video_strm_V_last_V_0_payload_A;
end if;
end process;
AXI_video_strm_V_last_V_0_load_A <= (not(AXI_video_strm_V_last_V_0_sel_wr) and AXI_video_strm_V_last_V_0_state_cmp_full);
AXI_video_strm_V_last_V_0_load_B <= (AXI_video_strm_V_last_V_0_state_cmp_full and AXI_video_strm_V_last_V_0_sel_wr);
AXI_video_strm_V_last_V_0_sel <= AXI_video_strm_V_last_V_0_sel_rd;
AXI_video_strm_V_last_V_0_state_cmp_full <= '0' when (AXI_video_strm_V_last_V_0_state = ap_const_lv2_1) else '1';
AXI_video_strm_V_last_V_0_vld_in <= stream_in_TVALID;
AXI_video_strm_V_last_V_0_vld_out <= AXI_video_strm_V_last_V_0_state(0);
AXI_video_strm_V_user_V_0_ack_in <= AXI_video_strm_V_user_V_0_state(1);
AXI_video_strm_V_user_V_0_ack_out_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, eol_2_i_reg_348, ap_predicate_op71_read_state6, ap_block_pp1_stage0_11001, ap_block_pp2_stage0_11001)
begin
if ((((ap_const_boolean_0 = ap_block_pp2_stage0_11001) and (eol_2_i_reg_348 = ap_const_lv1_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (ap_predicate_op71_read_state6 = ap_const_boolean_1) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0)) or ((ap_const_logic_1 = AXI_video_strm_V_data_V_0_vld_out) and (ap_const_logic_1 = ap_CS_fsm_state2)))) then
AXI_video_strm_V_user_V_0_ack_out <= ap_const_logic_1;
else
AXI_video_strm_V_user_V_0_ack_out <= ap_const_logic_0;
end if;
end process;
AXI_video_strm_V_user_V_0_data_out_assign_proc : process(AXI_video_strm_V_user_V_0_payload_A, AXI_video_strm_V_user_V_0_payload_B, AXI_video_strm_V_user_V_0_sel)
begin
if ((ap_const_logic_1 = AXI_video_strm_V_user_V_0_sel)) then
AXI_video_strm_V_user_V_0_data_out <= AXI_video_strm_V_user_V_0_payload_B;
else
AXI_video_strm_V_user_V_0_data_out <= AXI_video_strm_V_user_V_0_payload_A;
end if;
end process;
AXI_video_strm_V_user_V_0_load_A <= (not(AXI_video_strm_V_user_V_0_sel_wr) and AXI_video_strm_V_user_V_0_state_cmp_full);
AXI_video_strm_V_user_V_0_load_B <= (AXI_video_strm_V_user_V_0_state_cmp_full and AXI_video_strm_V_user_V_0_sel_wr);
AXI_video_strm_V_user_V_0_sel <= AXI_video_strm_V_user_V_0_sel_rd;
AXI_video_strm_V_user_V_0_state_cmp_full <= '0' when (AXI_video_strm_V_user_V_0_state = ap_const_lv2_1) else '1';
AXI_video_strm_V_user_V_0_vld_in <= stream_in_TVALID;
AXI_video_strm_V_user_V_0_vld_out <= AXI_video_strm_V_user_V_0_state(0);
ap_CS_fsm_pp1_stage0 <= ap_CS_fsm(4);
ap_CS_fsm_pp2_stage0 <= ap_CS_fsm(6);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state10 <= ap_CS_fsm(7);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state7 <= ap_CS_fsm(5);
ap_block_pp1_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp1_stage0_01001_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, ap_enable_reg_pp1_iter1, exitcond_i_reg_504, ap_predicate_op71_read_state6)
begin
ap_block_pp1_stage0_01001 <= ((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_predicate_op71_read_state6 = ap_const_boolean_1)) or ((exitcond_i_reg_504 = ap_const_lv1_0) and (img_data_stream_2_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_504 = ap_const_lv1_0) and (img_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_504 = ap_const_lv1_0) and (img_data_stream_0_V_full_n = ap_const_logic_0))));
end process;
ap_block_pp1_stage0_11001_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, ap_enable_reg_pp1_iter1, exitcond_i_reg_504, ap_predicate_op71_read_state6)
begin
ap_block_pp1_stage0_11001 <= ((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_predicate_op71_read_state6 = ap_const_boolean_1)) or ((exitcond_i_reg_504 = ap_const_lv1_0) and (img_data_stream_2_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_504 = ap_const_lv1_0) and (img_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_504 = ap_const_lv1_0) and (img_data_stream_0_V_full_n = ap_const_logic_0))));
end process;
ap_block_pp1_stage0_subdone_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, ap_enable_reg_pp1_iter1, exitcond_i_reg_504, ap_predicate_op71_read_state6)
begin
ap_block_pp1_stage0_subdone <= ((ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_predicate_op71_read_state6 = ap_const_boolean_1)) or ((exitcond_i_reg_504 = ap_const_lv1_0) and (img_data_stream_2_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_504 = ap_const_lv1_0) and (img_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_504 = ap_const_lv1_0) and (img_data_stream_0_V_full_n = ap_const_logic_0))));
end process;
ap_block_pp2_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp2_stage0_11001_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_enable_reg_pp2_iter1, eol_2_i_reg_348)
begin
ap_block_pp2_stage0_11001 <= ((eol_2_i_reg_348 = ap_const_lv1_0) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1));
end process;
ap_block_pp2_stage0_subdone_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, ap_enable_reg_pp2_iter1, eol_2_i_reg_348)
begin
ap_block_pp2_stage0_subdone <= ((eol_2_i_reg_348 = ap_const_lv1_0) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1));
end process;
ap_block_state1_assign_proc : process(ap_start, ap_done_reg, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n)
begin
ap_block_state1 <= ((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
ap_block_state5_pp1_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp1_stage0_iter1_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, exitcond_i_reg_504, ap_predicate_op71_read_state6)
begin
ap_block_state6_pp1_stage0_iter1 <= (((ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out) and (ap_predicate_op71_read_state6 = ap_const_boolean_1)) or ((exitcond_i_reg_504 = ap_const_lv1_0) and (img_data_stream_2_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_504 = ap_const_lv1_0) and (img_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond_i_reg_504 = ap_const_lv1_0) and (img_data_stream_0_V_full_n = ap_const_logic_0)));
end process;
ap_block_state8_pp2_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp2_stage0_iter1_assign_proc : process(AXI_video_strm_V_data_V_0_vld_out, eol_2_i_reg_348)
begin
ap_block_state9_pp2_stage0_iter1 <= ((eol_2_i_reg_348 = ap_const_lv1_0) and (ap_const_logic_0 = AXI_video_strm_V_data_V_0_vld_out));
end process;
ap_condition_515_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_i_reg_504)
begin
ap_condition_515 <= ((exitcond_i_reg_504 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0));
end process;
ap_done_assign_proc : process(ap_done_reg, exitcond4_i_fu_402_p2, ap_CS_fsm_state4)
begin
if (((exitcond4_i_fu_402_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_enable_pp1 <= (ap_idle_pp1 xor ap_const_logic_1);
ap_enable_pp2 <= (ap_idle_pp2 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp1_assign_proc : process(ap_enable_reg_pp1_iter1, ap_enable_reg_pp1_iter0)
begin
if (((ap_enable_reg_pp1_iter0 = ap_const_logic_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0))) then
ap_idle_pp1 <= ap_const_logic_1;
else
ap_idle_pp1 <= ap_const_logic_0;
end if;
end process;
ap_idle_pp2_assign_proc : process(ap_enable_reg_pp2_iter1, ap_enable_reg_pp2_iter0)
begin
if (((ap_enable_reg_pp2_iter0 = ap_const_logic_0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_0))) then
ap_idle_pp2 <= ap_const_logic_1;
else
ap_idle_pp2 <= ap_const_logic_0;
end if;
end process;
ap_phi_mux_axi_last_V_2_i_phi_fu_328_p4_assign_proc : process(AXI_video_strm_V_last_V_0_data_out, brmerge_i_reg_513, eol_reg_301, ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_323, ap_condition_515)
begin
if ((ap_const_boolean_1 = ap_condition_515)) then
if ((brmerge_i_reg_513 = ap_const_lv1_1)) then
ap_phi_mux_axi_last_V_2_i_phi_fu_328_p4 <= eol_reg_301;
elsif ((brmerge_i_reg_513 = ap_const_lv1_0)) then
ap_phi_mux_axi_last_V_2_i_phi_fu_328_p4 <= AXI_video_strm_V_last_V_0_data_out;
else
ap_phi_mux_axi_last_V_2_i_phi_fu_328_p4 <= ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_323;
end if;
else
ap_phi_mux_axi_last_V_2_i_phi_fu_328_p4 <= ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_323;
end if;
end process;
ap_phi_mux_eol_2_i_phi_fu_351_p4_assign_proc : process(AXI_video_strm_V_last_V_0_data_out, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, eol_2_i_reg_348)
begin
if (((eol_2_i_reg_348 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0))) then
ap_phi_mux_eol_2_i_phi_fu_351_p4 <= AXI_video_strm_V_last_V_0_data_out;
else
ap_phi_mux_eol_2_i_phi_fu_351_p4 <= eol_2_i_reg_348;
end if;
end process;
ap_phi_mux_eol_i_phi_fu_293_p4_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_i_reg_504, eol_i_reg_289, ap_phi_mux_axi_last_V_2_i_phi_fu_328_p4)
begin
if (((exitcond_i_reg_504 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
ap_phi_mux_eol_i_phi_fu_293_p4 <= ap_phi_mux_axi_last_V_2_i_phi_fu_328_p4;
else
ap_phi_mux_eol_i_phi_fu_293_p4 <= eol_i_reg_289;
end if;
end process;
ap_phi_mux_p_Val2_s_phi_fu_340_p4_assign_proc : process(AXI_video_strm_V_data_V_0_data_out, brmerge_i_reg_513, axi_data_V_1_i_reg_312, ap_phi_reg_pp1_iter1_p_Val2_s_reg_336, ap_condition_515)
begin
if ((ap_const_boolean_1 = ap_condition_515)) then
if ((brmerge_i_reg_513 = ap_const_lv1_1)) then
ap_phi_mux_p_Val2_s_phi_fu_340_p4 <= axi_data_V_1_i_reg_312;
elsif ((brmerge_i_reg_513 = ap_const_lv1_0)) then
ap_phi_mux_p_Val2_s_phi_fu_340_p4 <= AXI_video_strm_V_data_V_0_data_out;
else
ap_phi_mux_p_Val2_s_phi_fu_340_p4 <= ap_phi_reg_pp1_iter1_p_Val2_s_reg_336;
end if;
else
ap_phi_mux_p_Val2_s_phi_fu_340_p4 <= ap_phi_reg_pp1_iter1_p_Val2_s_reg_336;
end if;
end process;
ap_phi_reg_pp1_iter1_axi_last_V_2_i_reg_323 <= "X";
ap_phi_reg_pp1_iter1_p_Val2_s_reg_336 <= "XXXXXXXXXXXXXXXXXXXXXXXX";
ap_predicate_op71_read_state6_assign_proc : process(exitcond_i_reg_504, brmerge_i_reg_513)
begin
ap_predicate_op71_read_state6 <= ((brmerge_i_reg_513 = ap_const_lv1_0) and (exitcond_i_reg_504 = ap_const_lv1_0));
end process;
ap_ready_assign_proc : process(exitcond4_i_fu_402_p2, ap_CS_fsm_state4)
begin
if (((exitcond4_i_fu_402_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
brmerge_i_fu_427_p2 <= (sof_1_i_fu_176 or ap_phi_mux_eol_i_phi_fu_293_p4);
exitcond4_i_fu_402_p2 <= "1" when (t_V_reg_267 = rows_V_reg_465) else "0";
exitcond_i_fu_413_p2 <= "1" when (t_V_2_reg_278 = cols_V_reg_470) else "0";
i_V_fu_407_p2 <= std_logic_vector(unsigned(t_V_reg_267) + unsigned(ap_const_lv32_1));
img_cols_V_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, img_cols_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_cols_V_blk_n <= img_cols_V_empty_n;
else
img_cols_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_cols_V_out_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, img_cols_V_out_full_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_cols_V_out_blk_n <= img_cols_V_out_full_n;
else
img_cols_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img_cols_V_out_din <= img_cols_V_dout;
img_cols_V_out_write_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n)
begin
if ((not(((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_cols_V_out_write <= ap_const_logic_1;
else
img_cols_V_out_write <= ap_const_logic_0;
end if;
end process;
img_cols_V_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n)
begin
if ((not(((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_cols_V_read <= ap_const_logic_1;
else
img_cols_V_read <= ap_const_logic_0;
end if;
end process;
img_data_stream_0_V_blk_n_assign_proc : process(img_data_stream_0_V_full_n, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_i_reg_504)
begin
if (((exitcond_i_reg_504 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_0_V_blk_n <= img_data_stream_0_V_full_n;
else
img_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_data_stream_0_V_din <= ap_phi_mux_p_Val2_s_phi_fu_340_p4(8 - 1 downto 0);
img_data_stream_0_V_write_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, exitcond_i_reg_504, ap_block_pp1_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (exitcond_i_reg_504 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_0_V_write <= ap_const_logic_1;
else
img_data_stream_0_V_write <= ap_const_logic_0;
end if;
end process;
img_data_stream_1_V_blk_n_assign_proc : process(img_data_stream_1_V_full_n, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_i_reg_504)
begin
if (((exitcond_i_reg_504 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_1_V_blk_n <= img_data_stream_1_V_full_n;
else
img_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_data_stream_1_V_din <= ap_phi_mux_p_Val2_s_phi_fu_340_p4(15 downto 8);
img_data_stream_1_V_write_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, exitcond_i_reg_504, ap_block_pp1_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (exitcond_i_reg_504 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_1_V_write <= ap_const_logic_1;
else
img_data_stream_1_V_write <= ap_const_logic_0;
end if;
end process;
img_data_stream_2_V_blk_n_assign_proc : process(img_data_stream_2_V_full_n, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_i_reg_504)
begin
if (((exitcond_i_reg_504 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_2_V_blk_n <= img_data_stream_2_V_full_n;
else
img_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_data_stream_2_V_din <= ap_phi_mux_p_Val2_s_phi_fu_340_p4(23 downto 16);
img_data_stream_2_V_write_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, exitcond_i_reg_504, ap_block_pp1_stage0_11001)
begin
if (((ap_const_boolean_0 = ap_block_pp1_stage0_11001) and (exitcond_i_reg_504 = ap_const_lv1_0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0))) then
img_data_stream_2_V_write <= ap_const_logic_1;
else
img_data_stream_2_V_write <= ap_const_logic_0;
end if;
end process;
img_rows_V_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_rows_V_blk_n <= img_rows_V_empty_n;
else
img_rows_V_blk_n <= ap_const_logic_1;
end if;
end process;
img_rows_V_out_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_out_full_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_rows_V_out_blk_n <= img_rows_V_out_full_n;
else
img_rows_V_out_blk_n <= ap_const_logic_1;
end if;
end process;
img_rows_V_out_din <= img_rows_V_dout;
img_rows_V_out_write_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n)
begin
if ((not(((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_rows_V_out_write <= ap_const_logic_1;
else
img_rows_V_out_write <= ap_const_logic_0;
end if;
end process;
img_rows_V_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, img_rows_V_empty_n, img_cols_V_empty_n, img_rows_V_out_full_n, img_cols_V_out_full_n)
begin
if ((not(((img_cols_V_out_full_n = ap_const_logic_0) or (img_rows_V_out_full_n = ap_const_logic_0) or (img_cols_V_empty_n = ap_const_logic_0) or (img_rows_V_empty_n = ap_const_logic_0) or (ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
img_rows_V_read <= ap_const_logic_1;
else
img_rows_V_read <= ap_const_logic_0;
end if;
end process;
j_V_fu_418_p2 <= std_logic_vector(unsigned(t_V_2_reg_278) + unsigned(ap_const_lv32_1));
stream_in_TDATA_blk_n_assign_proc : process(AXI_video_strm_V_data_V_0_state, ap_CS_fsm_state2, ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0, exitcond_i_reg_504, brmerge_i_reg_513, ap_CS_fsm_pp2_stage0, ap_enable_reg_pp2_iter1, ap_block_pp2_stage0, eol_2_i_reg_348)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) or ((eol_2_i_reg_348 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp2_stage0) and (ap_enable_reg_pp2_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp2_stage0)) or ((brmerge_i_reg_513 = ap_const_lv1_0) and (exitcond_i_reg_504 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp1_stage0) and (ap_enable_reg_pp1_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp1_stage0)))) then
stream_in_TDATA_blk_n <= AXI_video_strm_V_data_V_0_state(0);
else
stream_in_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
stream_in_TREADY <= AXI_video_strm_V_dest_V_0_state(1);
tmp_user_V_fu_393_p1 <= AXI_video_strm_V_user_V_0_data_out;
end behav;
|
mit
|
b4e9db8f77911daf3f4565dc9c5abb30
| 0.600942 | 2.594252 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodAWGController/src/PkgZmodDAC.vhd
| 1 | 10,207 |
-------------------------------------------------------------------------------
--
-- File: PkgZmodDAC.vhd
-- Author: Tudor Gherman
-- Original Project: Zmod DAC 1411 Low Level Controller
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This package contains the constants and functions used for the
-- ZmodDAC1411_Controller IP
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package PkgZmodDAC is
--Timing parameters
constant ktS : time := 2 ns; -- Setup time between CSB and SCLK
constant ktH : time := 2 ns; -- Hold time between CSB and SCLK
constant ktDS : time := 2 ns; -- Setup time between the data and the rising edge of SCLK
constant ktDH : time := 2 ns; -- Hold time between the data and the rising edge of SCLK
constant ktclk : time := 40 ns; -- minimum period of the SCLK
constant kSclkHigh : time := 10 ns; -- SCLK pulse width high (min)
constant kSclkLow : time := 10 ns; -- SCLK pulse width low (min)
--constant kSclkT_Max : time := 10 ns; -- SCLK pulse width low (min)
constant kSclkT_Min : time := 50 ns; -- SCLK pulse width low (min)
--constant kNoCommandBits : integer := 16; -- minimum period of the SCLK
constant kNoDataBits : integer := 8; -- minimum period of the SCLK
constant kTdcoMax : time := 4.4 ns;
constant kRelayConfigTime : time := 3ms; -- relay set and reset signals
--ADC Model Registers
constant aReg00_Mask : std_logic_vector(7 downto 0) := "01100110";
--Implementation constants
constant kCS_PulseWidthHigh : integer := 31; --CS pulse width high not specified for AD8717
constant kSPI_DataWidth : integer := 8; --ADI_SPI module data width
constant kSPI_CommandWidth : integer := 8; --ADI_SPI module command width
constant kSPI_AddrWidth : integer := kSPI_CommandWidth - 3; --ADI_SPI module command width
constant kSPI_SysClkDiv : integer := 4; --ADI_SPI module system clock divide constant
--No minimum SPI clock frequency specified by AD9717. The maximum frequency is 25MHz.
constant kCount20us : unsigned := to_unsigned (1999, 24); --Constant used to measure 20us with a clock frequency of 100MHz
constant kCount4ms : unsigned := to_unsigned (399999, 24); --Constant used to measure 4ms with a clock frequency of 100MHz
constant kCount150ms : unsigned := to_unsigned (14999999, 24); --Constant used to measure 150ms with a clock frequency of 100MHz
constant kCfgTimeout : unsigned := to_unsigned (14999999, 24); --Constant used to measure 150ms with a clock frequency of 100MHz
type FsmStatesSPI_t is (StIdle, StWrite, StRead1, StRead2, StRead3, StDone, StAssertCS);
type FsmStates_t is (StStart, StWriteConfigReg, StWaitDoneWriteReg, StReadControlReg,
StWaitDoneReadReg, StCheckCmdCnt, StInitDone, StIdle, StExtSPI_WrCmd,
StWaitDoneExtWrReg, StExtSPI_RdCmd, StWaitDoneExtRdReg, StRegExtRxData, StError);
type DAC_SPI_Commands_t is array (13 downto 0) of std_logic_vector(15 downto 0);
type DAC_SPI_Readback_t is array (13 downto 0) of std_logic_vector(7 downto 0);
-- List of commands sent to the AD9717 during the initialization process.
constant kDAC_SPI_Cmd : DAC_SPI_Commands_t := (
x"0E00", -- 13. Cal Control: Disable calibration clock.
x"1200", -- 12. Memory R/W: clear CALEN.
x"0FC0", -- 11. Cal Memory: Read CALSTAT. Read ONLY!
x"1210", -- 10. Memory R/W: CALEN - initialize self calibration.
x"0E3A", -- 9. Cal Control - step 3: Select Q DAC, I DAC self calibration.
x"0E0A", -- 8. Cal Control - step 2: Enable calibration clock.
x"0E02", -- 7. Cal Control - step 1: DIVSEL - calibration clock divide ratio from DAC clock rate set to 64.
x"1200", -- 6. Memory R/W: Self calibration step 1 (Write 0x00 to Register 0x12).
x"1400", -- 5. CLKMODE: Clear Reaquire bit in CLKMODE register.
x"1408", -- 4. CLKMODE: Toggle (step 2-set) Reaquire bit in CLKMODE register.
x"1400", -- 3. CLKMODE: Toggle (step 1-clear) Reaquire bit in CLKMODE register.
x"02B4", -- 2. Data Control: 2's Complement input data format, IDATA latched on DCLKIO rising edge,
-- I first of pair on data input pads, data clock input enable, data clock output disable.
x"0000", -- 1. SPI Control : Clear Reset.
x"0020" -- 0. SPI Control : Set Reset.
);
-- List of data expected to be read back fro the AD9717 at each step (after each register write) of the initialization process.
constant DAC_SPI_mask : DAC_SPI_Readback_t := (
x"00",
x"00",
x"3F",
x"EF",
x"00",
x"00",
x"00",
x"EF",
x"C3",
x"CB",
x"C3",
x"40",
x"80",
x"80"
);
constant kCmdTotal : integer := 13;
constant kCmdRdCalstatIndex : integer := 11; --Read ID command index in kADC_SPI_Cmd and kADC_SPI_Rdbck arrays
-- Constant used to measure 300 calibration clock cycles with a calibration clock divide ratio from DAC clock rate set to 64.
constant kCalTimeout : unsigned := to_unsigned (19200, 24);
-- Number of commands to load in the TX command FIFO for the CommandFIFO module
constant kCmdFIFO_NoWrCmds : integer := 4;
-- Command list loaded in the TX command FIFO of the CommandFIFO module
type CmdFIFO_WrCmdList_t is array (kCmdFIFO_NoWrCmds downto 0) of std_logic_vector(23 downto 0);
constant kCmdFIFO_WrList : CmdFIFO_WrCmdList_t := (
x"801F04", -- read Version register
x"0002B4", -- write Data Control register
x"8002B0", -- read Data Control register
x"0002B0", -- write Data Control register
x"000000" -- dummy
);
-- Number of commands expected to be returned and loaded in the RX command FIFO of
-- the SPI_IAP_AD9717_TestModule module in the tb_TestTop test bench.
-- It should be equal to the number of read commands in the kCmdFIFO_WrList.
constant kCmdFIFO_NoRdCmds : integer := 2;
-- Data expected in return after sending the kCmdFIFO_WrList commands by the CommandFIFO module
type CmdFIFO_RdCmdList_t is array (kCmdFIFO_NoRdCmds-1 downto 0) of std_logic_vector(7 downto 0);
constant kCmdFIFO_RdList : CmdFIFO_RdCmdList_t := (x"04",x"B0");
constant kCmdFIFO_RdListMask : CmdFIFO_RdCmdList_t := (x"00",x"40");
constant kCmdFIFO_Timeout : unsigned (23 downto 0) := x"000600";
end PkgZmodDAC;
|
mit
|
45bdde538b13adf802eb6c7f9e7b9864
| 0.551974 | 4.996084 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/hls_saturation_enqcK.vhd
| 1 | 1,608 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity hls_saturation_enqcK is
generic (
ID :integer := 0;
NUM_STAGE :integer := 1;
din0_WIDTH :integer := 32;
din1_WIDTH :integer := 32;
din2_WIDTH :integer := 32;
din3_WIDTH :integer := 32;
din4_WIDTH :integer := 32;
dout_WIDTH :integer := 32);
port (
din0 :in std_logic_vector(27 downto 0);
din1 :in std_logic_vector(27 downto 0);
din2 :in std_logic_vector(27 downto 0);
din3 :in std_logic_vector(27 downto 0);
din4 :in std_logic_vector(1 downto 0);
dout :out std_logic_vector(27 downto 0));
end entity;
architecture rtl of hls_saturation_enqcK is
-- puts internal signals
signal sel : std_logic_vector(1 downto 0);
-- level 1 signals
signal mux_1_0 : std_logic_vector(27 downto 0);
signal mux_1_1 : std_logic_vector(27 downto 0);
-- level 2 signals
signal mux_2_0 : std_logic_vector(27 downto 0);
begin
sel <= din4;
-- Generate level 1 logic
mux_1_0 <= din0 when sel(0) = '0' else din1;
mux_1_1 <= din2 when sel(0) = '0' else din3;
-- Generate level 2 logic
mux_2_0 <= mux_1_0 when sel(1) = '0' else mux_1_1;
-- output logic
dout <= mux_2_0;
end architecture;
|
mit
|
b04325c01478bf69b99c7b3dd59e1774
| 0.561567 | 3.241935 | false | false | false | false |
JL-Grande/Ascensor_SED
|
ASCENSOR/tb_convertidor_piso_actual.vhd
| 1 | 2,508 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_convertidor_piso_actual IS
END tb_convertidor_piso_actual;
ARCHITECTURE behavior OF tb_convertidor_piso_actual IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT convertidor_piso_actual
PORT(
clk : IN std_logic;
rst : IN std_logic;
piso_actual : IN std_logic_vector(2 downto 0);
boton_seleccionado : IN std_logic_vector(2 downto 0);
piso_actual_convertido : OUT std_logic_vector(1 downto 0);
boton_seleccionado_convertido : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal piso_actual : std_logic_vector(2 downto 0) := (others => '0');
signal boton_seleccionado : std_logic_vector(2 downto 0) := (others => '0');
--Outputs
signal piso_actual_convertido : std_logic_vector(1 downto 0);
signal boton_seleccionado_convertido : std_logic_vector(1 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: convertidor_piso_actual PORT MAP (
clk => clk,
rst => rst,
piso_actual => piso_actual,
boton_seleccionado => boton_seleccionado,
piso_actual_convertido => piso_actual_convertido,
boton_seleccionado_convertido => boton_seleccionado_convertido
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '0';
boton_seleccionado <= "000";
piso_actual <= "100";
WAIT FOR 40 ns;
boton_seleccionado <= "100";
piso_actual <= "100";
WAIT FOR 10 ns;
RST <= '1';
WAIT FOR 10 ns;
RST <= '0';
WAIT FOR 45 ns;
boton_seleccionado <= "010";
piso_actual <= "010";
WAIT FOR 2 ns;
boton_seleccionado <= "101";
piso_actual <= "011";
WAIT FOR 50 ns;
boton_seleccionado <= "100";
piso_actual <= "100";
WAIT FOR 4 ns;
boton_seleccionado <= "110";
piso_actual <= "010";
WAIT FOR 2 ns;
boton_seleccionado <= "101";
piso_actual <= "101";
WAIT FOR 3 ns;
boton_seleccionado <= "010";
piso_actual <= "100";
WAIT FOR 20 ns;
boton_seleccionado <= "110";
piso_actual <= "010";
WAIT FOR 80 ns;
ASSERT false
REPORT "Simulación finalizada. Test superado."
SEVERITY FAILURE;
end process;
END;
|
gpl-3.0
|
9cd7a986a6089a138b2dbb5a8c69dda6
| 0.629984 | 3.421555 | false | false | false | false |
nhasbun/de10nano_ledtest
|
quartus/src/qsys/ledtest/ledtest_inst.vhd
| 1 | 8,122 |
component ledtest is
port (
clk_clk : in std_logic := 'X'; -- clk
hps_io_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
hps_io_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
hps_io_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
hps_io_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
hps_io_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
hps_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
hps_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
hps_io_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
hps_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
hps_io_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
hps_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
hps_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
hps_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
hps_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
jtag_debug_master_reset_reset : out std_logic; -- reset
led_array_io_export : out std_logic_vector(7 downto 0); -- export
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
switch_array_io_export : in std_logic_vector(3 downto 0) := (others => 'X') -- export
);
end component ledtest;
u0 : component ledtest
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
hps_io_hps_io_emac1_inst_TX_CLK => CONNECTED_TO_hps_io_hps_io_emac1_inst_TX_CLK, -- hps_io.hps_io_emac1_inst_TX_CLK
hps_io_hps_io_emac1_inst_TXD0 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD0, -- .hps_io_emac1_inst_TXD0
hps_io_hps_io_emac1_inst_TXD1 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD1, -- .hps_io_emac1_inst_TXD1
hps_io_hps_io_emac1_inst_TXD2 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD2, -- .hps_io_emac1_inst_TXD2
hps_io_hps_io_emac1_inst_TXD3 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD3, -- .hps_io_emac1_inst_TXD3
hps_io_hps_io_emac1_inst_RXD0 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD0, -- .hps_io_emac1_inst_RXD0
hps_io_hps_io_emac1_inst_MDIO => CONNECTED_TO_hps_io_hps_io_emac1_inst_MDIO, -- .hps_io_emac1_inst_MDIO
hps_io_hps_io_emac1_inst_MDC => CONNECTED_TO_hps_io_hps_io_emac1_inst_MDC, -- .hps_io_emac1_inst_MDC
hps_io_hps_io_emac1_inst_RX_CTL => CONNECTED_TO_hps_io_hps_io_emac1_inst_RX_CTL, -- .hps_io_emac1_inst_RX_CTL
hps_io_hps_io_emac1_inst_TX_CTL => CONNECTED_TO_hps_io_hps_io_emac1_inst_TX_CTL, -- .hps_io_emac1_inst_TX_CTL
hps_io_hps_io_emac1_inst_RX_CLK => CONNECTED_TO_hps_io_hps_io_emac1_inst_RX_CLK, -- .hps_io_emac1_inst_RX_CLK
hps_io_hps_io_emac1_inst_RXD1 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD1, -- .hps_io_emac1_inst_RXD1
hps_io_hps_io_emac1_inst_RXD2 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD2, -- .hps_io_emac1_inst_RXD2
hps_io_hps_io_emac1_inst_RXD3 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD3, -- .hps_io_emac1_inst_RXD3
jtag_debug_master_reset_reset => CONNECTED_TO_jtag_debug_master_reset_reset, -- jtag_debug_master_reset.reset
led_array_io_export => CONNECTED_TO_led_array_io_export, -- led_array_io.export
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
switch_array_io_export => CONNECTED_TO_switch_array_io_export -- switch_array_io.export
);
|
mit
|
235ee5fa89207b08e8878254788ac2b4
| 0.433637 | 3.325962 | false | false | false | false |
Gmatarrubia/Frecuencimetro-VHDL-Xilinx
|
Frecuencimentro/ContadorEventos.vhd
| 2 | 1,329 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:38:47 01/07/2015
-- Design Name:
-- Module Name: ContadorEventos - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ContadorEventos is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(3 downto 0));
end ContadorEventos;
architecture behavioral of ContadorEventos is
signal q_i: std_logic_vector(q'range):=(others => '0');
begin
p1:process(reset, clk)
begin
if reset = '1' then
q_i <= (others => '0');
elsif rising_edge(clk) then
q_i <= std_logic_vector(unsigned(q_i) + 1);
end if;
end process;
q <= q_i;
end behavioral;
|
gpl-2.0
|
92f9af307d8a334b433c1981aa866bf2
| 0.586907 | 3.70195 | false | false | false | false |
Digilent/vivado-library
|
ip/video_scaler/hdl/vhdl/video_scaler_ctrl_s_axi.vhd
| 1 | 16,290 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity video_scaler_ctrl_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
in_width :out STD_LOGIC_VECTOR(31 downto 0);
in_height :out STD_LOGIC_VECTOR(31 downto 0);
out_width :out STD_LOGIC_VECTOR(31 downto 0);
out_height :out STD_LOGIC_VECTOR(31 downto 0)
);
end entity video_scaler_ctrl_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of in_width
-- bit 31~0 - in_width[31:0] (Read/Write)
-- 0x14 : reserved
-- 0x18 : Data signal of in_height
-- bit 31~0 - in_height[31:0] (Read/Write)
-- 0x1c : reserved
-- 0x20 : Data signal of out_width
-- bit 31~0 - out_width[31:0] (Read/Write)
-- 0x24 : reserved
-- 0x28 : Data signal of out_height
-- bit 31~0 - out_height[31:0] (Read/Write)
-- 0x2c : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of video_scaler_ctrl_s_axi is
type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states
signal wstate : states := wrreset;
signal rstate : states := rdreset;
signal wnext, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_IN_WIDTH_DATA_0 : INTEGER := 16#10#;
constant ADDR_IN_WIDTH_CTRL : INTEGER := 16#14#;
constant ADDR_IN_HEIGHT_DATA_0 : INTEGER := 16#18#;
constant ADDR_IN_HEIGHT_CTRL : INTEGER := 16#1c#;
constant ADDR_OUT_WIDTH_DATA_0 : INTEGER := 16#20#;
constant ADDR_OUT_WIDTH_CTRL : INTEGER := 16#24#;
constant ADDR_OUT_HEIGHT_DATA_0 : INTEGER := 16#28#;
constant ADDR_OUT_HEIGHT_CTRL : INTEGER := 16#2c#;
constant ADDR_BITS : INTEGER := 6;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC := '0';
signal int_ap_start : STD_LOGIC := '0';
signal int_auto_restart : STD_LOGIC := '0';
signal int_gie : STD_LOGIC := '0';
signal int_ier : UNSIGNED(1 downto 0) := (others => '0');
signal int_isr : UNSIGNED(1 downto 0) := (others => '0');
signal int_in_width : UNSIGNED(31 downto 0) := (others => '0');
signal int_in_height : UNSIGNED(31 downto 0) := (others => '0');
signal int_out_width : UNSIGNED(31 downto 0) := (others => '0');
signal int_out_height : UNSIGNED(31 downto 0) := (others => '0');
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wrreset;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdreset;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_IN_WIDTH_DATA_0 =>
rdata_data <= RESIZE(int_in_width(31 downto 0), 32);
when ADDR_IN_HEIGHT_DATA_0 =>
rdata_data <= RESIZE(int_in_height(31 downto 0), 32);
when ADDR_OUT_WIDTH_DATA_0 =>
rdata_data <= RESIZE(int_out_width(31 downto 0), 32);
when ADDR_OUT_HEIGHT_DATA_0 =>
rdata_data <= RESIZE(int_out_height(31 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
in_width <= STD_LOGIC_VECTOR(int_in_width);
in_height <= STD_LOGIC_VECTOR(int_in_height);
out_width <= STD_LOGIC_VECTOR(int_out_width);
out_height <= STD_LOGIC_VECTOR(int_out_height);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_idle <= '0';
elsif (ACLK_EN = '1') then
if (true) then
int_ap_idle <= ap_idle;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_ready <= '0';
elsif (ACLK_EN = '1') then
if (true) then
int_ap_ready <= ap_ready;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IN_WIDTH_DATA_0) then
int_in_width(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in_width(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IN_HEIGHT_DATA_0) then
int_in_height(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in_height(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_OUT_WIDTH_DATA_0) then
int_out_width(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_out_width(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_OUT_HEIGHT_DATA_0) then
int_out_height(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_out_height(31 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
|
mit
|
e1f278dea26f5e6111de878e079c8b36
| 0.460835 | 3.75952 | false | false | false | false |
scottlbaker/Nova-SOC
|
src/addr.vhd
| 1 | 1,943 |
--========================================================================
-- addr.vhd :: Nova 16-bit address adder
--
-- (c) Scott L. Baker, Sierra Circuit Design
--========================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.my_types.all;
entity ADDR is
port (
SX : out std_logic_vector(15 downto 0); -- result bus
BX : in std_logic_vector(15 downto 0); -- operand bus
DISP : in std_logic_vector( 7 downto 0); -- displacement
OP : in SX_OP_TYPE -- micro op
);
end ADDR;
architecture BEHAVIORAL of ADDR is
--=================================================================
-- Types, component, and signal definitions
--=================================================================
-- internal busses
signal AX : std_logic_vector(15 downto 0);
signal DSE : std_logic_vector( 6 downto 0);
begin
--================================================================
-- Start of the behavioral description
--================================================================
--====================
-- Opcode Decoding
--====================
OPCODE_DECODING:
process(OP, DSE, DISP)
begin
case OP is
when REL => -- relative address
AX <= DSE & DISP & '0';
when DEC1 => -- decrement by 1
AX <= "1111111111111110";
when INC2 => -- increment by 2
AX <= "0000000000000100";
when others => -- increment by 1
AX <= "0000000000000010";
end case;
end process;
DSE <= (others => DISP(7));
SX <= AX + BX;
end BEHAVIORAL;
|
gpl-3.0
|
05ed6b47f14efb64f3f3d1300ea8e3c7
| 0.383428 | 5.167553 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_contrast_stretch_1_0/hdl/vhdl/Loop_loop_height_pro.vhd
| 1 | 87,115 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Loop_loop_height_pro is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
max_dout : IN STD_LOGIC_VECTOR (7 downto 0);
max_empty_n : IN STD_LOGIC;
max_read : OUT STD_LOGIC;
p_rows_assign_cast_loc_dout : IN STD_LOGIC_VECTOR (11 downto 0);
p_rows_assign_cast_loc_empty_n : IN STD_LOGIC;
p_rows_assign_cast_loc_read : OUT STD_LOGIC;
p_cols_assign_cast_loc_dout : IN STD_LOGIC_VECTOR (11 downto 0);
p_cols_assign_cast_loc_empty_n : IN STD_LOGIC;
p_cols_assign_cast_loc_read : OUT STD_LOGIC;
img2_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img2_data_stream_0_V_full_n : IN STD_LOGIC;
img2_data_stream_0_V_write : OUT STD_LOGIC;
img2_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img2_data_stream_1_V_full_n : IN STD_LOGIC;
img2_data_stream_1_V_write : OUT STD_LOGIC;
img2_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img2_data_stream_2_V_full_n : IN STD_LOGIC;
img2_data_stream_2_V_write : OUT STD_LOGIC;
img1_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img1_data_stream_0_V_empty_n : IN STD_LOGIC;
img1_data_stream_0_V_read : OUT STD_LOGIC;
img1_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img1_data_stream_1_V_empty_n : IN STD_LOGIC;
img1_data_stream_1_V_read : OUT STD_LOGIC;
img1_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img1_data_stream_2_V_empty_n : IN STD_LOGIC;
img1_data_stream_2_V_read : OUT STD_LOGIC;
min_dout : IN STD_LOGIC_VECTOR (7 downto 0);
min_empty_n : IN STD_LOGIC;
min_read : OUT STD_LOGIC;
tmp_3_cast_loc_dout : IN STD_LOGIC_VECTOR (7 downto 0);
tmp_3_cast_loc_empty_n : IN STD_LOGIC;
tmp_3_cast_loc_read : OUT STD_LOGIC );
end;
architecture behav of Loop_loop_height_pro is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_ST_fsm_state28 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal max_blk_n : STD_LOGIC;
signal p_rows_assign_cast_loc_blk_n : STD_LOGIC;
signal p_cols_assign_cast_loc_blk_n : STD_LOGIC;
signal img2_data_stream_0_V_blk_n : STD_LOGIC;
signal ap_enable_reg_pp0_iter24 : STD_LOGIC := '0';
signal ap_block_pp0_stage0 : BOOLEAN;
signal exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal img2_data_stream_1_V_blk_n : STD_LOGIC;
signal img2_data_stream_2_V_blk_n : STD_LOGIC;
signal img1_data_stream_0_V_blk_n : STD_LOGIC;
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal img1_data_stream_1_V_blk_n : STD_LOGIC;
signal img1_data_stream_2_V_blk_n : STD_LOGIC;
signal min_blk_n : STD_LOGIC;
signal tmp_3_cast_loc_blk_n : STD_LOGIC;
signal t_V_2_reg_162 : STD_LOGIC_VECTOR (10 downto 0);
signal max_read_reg_279 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_state1 : BOOLEAN;
signal min_read_reg_284 : STD_LOGIC_VECTOR (7 downto 0);
signal p_rows_assign_cast_lo_reg_289 : STD_LOGIC_VECTOR (11 downto 0);
signal p_cols_assign_cast_lo_reg_294 : STD_LOGIC_VECTOR (11 downto 0);
signal extLd_fu_189_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal extLd_reg_299 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_8_tr_cast_i_i_ca_fu_203_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_8_tr_cast_i_i_ca_reg_304 : STD_LOGIC_VECTOR (16 downto 0);
signal exitcond51_i_i_i_fu_211_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal i_V_fu_216_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal i_V_reg_313 : STD_LOGIC_VECTOR (10 downto 0);
signal exitcond_i_i_i_fu_226_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state5_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_state6_pp0_stage0_iter3 : BOOLEAN;
signal ap_block_state7_pp0_stage0_iter4 : BOOLEAN;
signal ap_block_state8_pp0_stage0_iter5 : BOOLEAN;
signal ap_block_state9_pp0_stage0_iter6 : BOOLEAN;
signal ap_block_state10_pp0_stage0_iter7 : BOOLEAN;
signal ap_block_state11_pp0_stage0_iter8 : BOOLEAN;
signal ap_block_state12_pp0_stage0_iter9 : BOOLEAN;
signal ap_block_state13_pp0_stage0_iter10 : BOOLEAN;
signal ap_block_state14_pp0_stage0_iter11 : BOOLEAN;
signal ap_block_state15_pp0_stage0_iter12 : BOOLEAN;
signal ap_block_state16_pp0_stage0_iter13 : BOOLEAN;
signal ap_block_state17_pp0_stage0_iter14 : BOOLEAN;
signal ap_block_state18_pp0_stage0_iter15 : BOOLEAN;
signal ap_block_state19_pp0_stage0_iter16 : BOOLEAN;
signal ap_block_state20_pp0_stage0_iter17 : BOOLEAN;
signal ap_block_state21_pp0_stage0_iter18 : BOOLEAN;
signal ap_block_state22_pp0_stage0_iter19 : BOOLEAN;
signal ap_block_state23_pp0_stage0_iter20 : BOOLEAN;
signal ap_block_state24_pp0_stage0_iter21 : BOOLEAN;
signal ap_block_state25_pp0_stage0_iter22 : BOOLEAN;
signal ap_block_state26_pp0_stage0_iter23 : BOOLEAN;
signal ap_block_state27_pp0_stage0_iter24 : BOOLEAN;
signal ap_block_pp0_stage0_11001 : BOOLEAN;
signal ap_reg_pp0_iter1_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter2_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter3_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter4_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter5_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter6_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter7_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter8_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter9_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter10_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter11_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter12_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter13_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter14_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter15_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter16_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter17_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter18_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter19_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter20_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter21_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter22_exitcond_i_i_i_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal j_V_fu_231_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal tmp_9_reg_327 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter8_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter9_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter10_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter11_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter12_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter13_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter14_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter15_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter16_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter17_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter18_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter19_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter20_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter21_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter22_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter23_tmp_8_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter8_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter9_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter10_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter11_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter12_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter13_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter14_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter15_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter16_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter17_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter18_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter19_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter20_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter21_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter22_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter23_tmp_reg_339 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_1_i_i_fu_237_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter3_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter4_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter5_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter6_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter7_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter8_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter9_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter10_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter11_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter12_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter13_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter14_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter15_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter16_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter17_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter18_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter19_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter20_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter21_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter22_tmp_1_i_i_reg_344 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_i_fu_241_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter3_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter4_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter5_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter6_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter7_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter8_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter9_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter10_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter11_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter12_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter13_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter14_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter15_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter16_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter17_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter18_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter19_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter20_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter21_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter22_tmp_i_i_reg_348 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_i_i_fu_265_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_10_i_i_reg_352 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_7_fu_275_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_pp0_stage0_subdone : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC;
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter5 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter6 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter7 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter8 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter9 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter10 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter11 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter12 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter13 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter14 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter15 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter16 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter17 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter18 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter19 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter20 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter21 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter22 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter23 : STD_LOGIC := '0';
signal t_V_reg_151 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_CS_fsm_state28 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state28 : signal is "none";
signal ap_phi_reg_pp0_iter0_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter1_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter2_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter3_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter4_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter5_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter6_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter7_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter8_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter9_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter10_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter11_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter12_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter13_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter14_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter15_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter16_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter17_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter18_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter19_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter20_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter21_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter22_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter23_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_reg_pp0_iter24_tmp_2_reg_173 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_pp0_stage0_01001 : BOOLEAN;
signal tmp_cast_i_i_fu_193_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_8_tr_i_i_fu_197_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal t_V_cast_i_i_fu_207_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal t_V_1_cast_i_i_fu_222_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_8_cast_i_i_fu_245_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_9_i_i_fu_248_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal p_shl_i_i_fu_257_p3 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_9_cast_i_i_fu_253_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal grp_fu_271_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal grp_fu_271_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_271_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
signal ap_condition_362 : BOOLEAN;
signal ap_condition_490 : BOOLEAN;
component hls_contrast_strefYi IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (16 downto 0);
din1 : IN STD_LOGIC_VECTOR (8 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (7 downto 0) );
end component;
begin
hls_contrast_strefYi_U47 : component hls_contrast_strefYi
generic map (
ID => 1,
NUM_STAGE => 21,
din0_WIDTH => 17,
din1_WIDTH => 9,
dout_WIDTH => 8)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => tmp_10_i_i_reg_352,
din1 => grp_fu_271_p1,
ce => grp_fu_271_ce,
dout => grp_fu_271_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_continue = ap_const_logic_1)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (exitcond51_i_i_i_fu_211_p2 = ap_const_lv1_1))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((exitcond51_i_i_i_fu_211_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3)) then
ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state3);
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end if;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter10_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter10 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter10 <= ap_enable_reg_pp0_iter9;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter11_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter11 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter11 <= ap_enable_reg_pp0_iter10;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter12_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter12 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter12 <= ap_enable_reg_pp0_iter11;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter13_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter13 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter13 <= ap_enable_reg_pp0_iter12;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter14_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter14 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter14 <= ap_enable_reg_pp0_iter13;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter15_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter15 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter15 <= ap_enable_reg_pp0_iter14;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter16_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter16 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter16 <= ap_enable_reg_pp0_iter15;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter17_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter17 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter17 <= ap_enable_reg_pp0_iter16;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter18_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter18 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter18 <= ap_enable_reg_pp0_iter17;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter19_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter19 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter19 <= ap_enable_reg_pp0_iter18;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter20_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter20 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter20 <= ap_enable_reg_pp0_iter19;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter21_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter21 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter21 <= ap_enable_reg_pp0_iter20;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter22_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter22 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter22 <= ap_enable_reg_pp0_iter21;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter23_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter23 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter23 <= ap_enable_reg_pp0_iter22;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter24_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter24 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter24 <= ap_enable_reg_pp0_iter23;
elsif (((exitcond51_i_i_i_fu_211_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_enable_reg_pp0_iter24 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter6 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter7 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter8 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter9 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter24_tmp_2_reg_173_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter23 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
if ((ap_const_boolean_1 = ap_condition_362)) then
ap_phi_reg_pp0_iter24_tmp_2_reg_173 <= tmp_7_fu_275_p1;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter24_tmp_2_reg_173 <= ap_phi_reg_pp0_iter23_tmp_2_reg_173;
end if;
end if;
end if;
end process;
ap_phi_reg_pp0_iter3_tmp_2_reg_173_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
if ((ap_const_boolean_1 = ap_condition_490)) then
ap_phi_reg_pp0_iter3_tmp_2_reg_173 <= ap_const_lv8_0;
elsif (((ap_reg_pp0_iter1_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (tmp_1_i_i_fu_237_p2 = ap_const_lv1_1))) then
ap_phi_reg_pp0_iter3_tmp_2_reg_173 <= ap_const_lv8_FF;
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_phi_reg_pp0_iter3_tmp_2_reg_173 <= ap_phi_reg_pp0_iter2_tmp_2_reg_173;
end if;
end if;
end if;
end process;
t_V_2_reg_162_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_i_i_i_fu_226_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
t_V_2_reg_162 <= j_V_fu_231_p2;
elsif (((exitcond51_i_i_i_fu_211_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
t_V_2_reg_162 <= ap_const_lv11_0;
end if;
end if;
end process;
t_V_reg_151_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state28)) then
t_V_reg_151 <= i_V_reg_313;
elsif ((not(((ap_start = ap_const_logic_0) or (tmp_3_cast_loc_empty_n = ap_const_logic_0) or (min_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (max_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
t_V_reg_151 <= ap_const_lv11_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter9 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter10_tmp_2_reg_173 <= ap_phi_reg_pp0_iter9_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter10 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter11_tmp_2_reg_173 <= ap_phi_reg_pp0_iter10_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter11 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter12_tmp_2_reg_173 <= ap_phi_reg_pp0_iter11_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter12 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter13_tmp_2_reg_173 <= ap_phi_reg_pp0_iter12_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter13 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter14_tmp_2_reg_173 <= ap_phi_reg_pp0_iter13_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter14 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter15_tmp_2_reg_173 <= ap_phi_reg_pp0_iter14_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter15 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter16_tmp_2_reg_173 <= ap_phi_reg_pp0_iter15_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter16 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter17_tmp_2_reg_173 <= ap_phi_reg_pp0_iter16_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter17 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter18_tmp_2_reg_173 <= ap_phi_reg_pp0_iter17_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter18 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter19_tmp_2_reg_173 <= ap_phi_reg_pp0_iter18_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter1_tmp_2_reg_173 <= ap_phi_reg_pp0_iter0_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter19 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter20_tmp_2_reg_173 <= ap_phi_reg_pp0_iter19_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter20 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter21_tmp_2_reg_173 <= ap_phi_reg_pp0_iter20_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter21 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter22_tmp_2_reg_173 <= ap_phi_reg_pp0_iter21_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter22 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter23_tmp_2_reg_173 <= ap_phi_reg_pp0_iter22_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter2_tmp_2_reg_173 <= ap_phi_reg_pp0_iter1_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter3 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter4_tmp_2_reg_173 <= ap_phi_reg_pp0_iter3_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter4 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter5_tmp_2_reg_173 <= ap_phi_reg_pp0_iter4_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter6_tmp_2_reg_173 <= ap_phi_reg_pp0_iter5_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter6 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter7_tmp_2_reg_173 <= ap_phi_reg_pp0_iter6_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter7 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter8_tmp_2_reg_173 <= ap_phi_reg_pp0_iter7_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_enable_reg_pp0_iter8 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_phi_reg_pp0_iter9_tmp_2_reg_173 <= ap_phi_reg_pp0_iter8_tmp_2_reg_173;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_0 = ap_block_pp0_stage0_11001)) then
ap_reg_pp0_iter10_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter9_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter10_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter9_tmp_1_i_i_reg_344;
ap_reg_pp0_iter10_tmp_8_reg_334 <= ap_reg_pp0_iter9_tmp_8_reg_334;
ap_reg_pp0_iter10_tmp_i_i_reg_348 <= ap_reg_pp0_iter9_tmp_i_i_reg_348;
ap_reg_pp0_iter10_tmp_reg_339 <= ap_reg_pp0_iter9_tmp_reg_339;
ap_reg_pp0_iter11_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter10_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter11_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter10_tmp_1_i_i_reg_344;
ap_reg_pp0_iter11_tmp_8_reg_334 <= ap_reg_pp0_iter10_tmp_8_reg_334;
ap_reg_pp0_iter11_tmp_i_i_reg_348 <= ap_reg_pp0_iter10_tmp_i_i_reg_348;
ap_reg_pp0_iter11_tmp_reg_339 <= ap_reg_pp0_iter10_tmp_reg_339;
ap_reg_pp0_iter12_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter11_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter12_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter11_tmp_1_i_i_reg_344;
ap_reg_pp0_iter12_tmp_8_reg_334 <= ap_reg_pp0_iter11_tmp_8_reg_334;
ap_reg_pp0_iter12_tmp_i_i_reg_348 <= ap_reg_pp0_iter11_tmp_i_i_reg_348;
ap_reg_pp0_iter12_tmp_reg_339 <= ap_reg_pp0_iter11_tmp_reg_339;
ap_reg_pp0_iter13_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter12_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter13_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter12_tmp_1_i_i_reg_344;
ap_reg_pp0_iter13_tmp_8_reg_334 <= ap_reg_pp0_iter12_tmp_8_reg_334;
ap_reg_pp0_iter13_tmp_i_i_reg_348 <= ap_reg_pp0_iter12_tmp_i_i_reg_348;
ap_reg_pp0_iter13_tmp_reg_339 <= ap_reg_pp0_iter12_tmp_reg_339;
ap_reg_pp0_iter14_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter13_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter14_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter13_tmp_1_i_i_reg_344;
ap_reg_pp0_iter14_tmp_8_reg_334 <= ap_reg_pp0_iter13_tmp_8_reg_334;
ap_reg_pp0_iter14_tmp_i_i_reg_348 <= ap_reg_pp0_iter13_tmp_i_i_reg_348;
ap_reg_pp0_iter14_tmp_reg_339 <= ap_reg_pp0_iter13_tmp_reg_339;
ap_reg_pp0_iter15_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter14_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter15_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter14_tmp_1_i_i_reg_344;
ap_reg_pp0_iter15_tmp_8_reg_334 <= ap_reg_pp0_iter14_tmp_8_reg_334;
ap_reg_pp0_iter15_tmp_i_i_reg_348 <= ap_reg_pp0_iter14_tmp_i_i_reg_348;
ap_reg_pp0_iter15_tmp_reg_339 <= ap_reg_pp0_iter14_tmp_reg_339;
ap_reg_pp0_iter16_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter15_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter16_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter15_tmp_1_i_i_reg_344;
ap_reg_pp0_iter16_tmp_8_reg_334 <= ap_reg_pp0_iter15_tmp_8_reg_334;
ap_reg_pp0_iter16_tmp_i_i_reg_348 <= ap_reg_pp0_iter15_tmp_i_i_reg_348;
ap_reg_pp0_iter16_tmp_reg_339 <= ap_reg_pp0_iter15_tmp_reg_339;
ap_reg_pp0_iter17_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter16_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter17_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter16_tmp_1_i_i_reg_344;
ap_reg_pp0_iter17_tmp_8_reg_334 <= ap_reg_pp0_iter16_tmp_8_reg_334;
ap_reg_pp0_iter17_tmp_i_i_reg_348 <= ap_reg_pp0_iter16_tmp_i_i_reg_348;
ap_reg_pp0_iter17_tmp_reg_339 <= ap_reg_pp0_iter16_tmp_reg_339;
ap_reg_pp0_iter18_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter17_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter18_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter17_tmp_1_i_i_reg_344;
ap_reg_pp0_iter18_tmp_8_reg_334 <= ap_reg_pp0_iter17_tmp_8_reg_334;
ap_reg_pp0_iter18_tmp_i_i_reg_348 <= ap_reg_pp0_iter17_tmp_i_i_reg_348;
ap_reg_pp0_iter18_tmp_reg_339 <= ap_reg_pp0_iter17_tmp_reg_339;
ap_reg_pp0_iter19_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter18_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter19_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter18_tmp_1_i_i_reg_344;
ap_reg_pp0_iter19_tmp_8_reg_334 <= ap_reg_pp0_iter18_tmp_8_reg_334;
ap_reg_pp0_iter19_tmp_i_i_reg_348 <= ap_reg_pp0_iter18_tmp_i_i_reg_348;
ap_reg_pp0_iter19_tmp_reg_339 <= ap_reg_pp0_iter18_tmp_reg_339;
ap_reg_pp0_iter20_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter19_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter20_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter19_tmp_1_i_i_reg_344;
ap_reg_pp0_iter20_tmp_8_reg_334 <= ap_reg_pp0_iter19_tmp_8_reg_334;
ap_reg_pp0_iter20_tmp_i_i_reg_348 <= ap_reg_pp0_iter19_tmp_i_i_reg_348;
ap_reg_pp0_iter20_tmp_reg_339 <= ap_reg_pp0_iter19_tmp_reg_339;
ap_reg_pp0_iter21_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter20_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter21_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter20_tmp_1_i_i_reg_344;
ap_reg_pp0_iter21_tmp_8_reg_334 <= ap_reg_pp0_iter20_tmp_8_reg_334;
ap_reg_pp0_iter21_tmp_i_i_reg_348 <= ap_reg_pp0_iter20_tmp_i_i_reg_348;
ap_reg_pp0_iter21_tmp_reg_339 <= ap_reg_pp0_iter20_tmp_reg_339;
ap_reg_pp0_iter22_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter21_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter22_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter21_tmp_1_i_i_reg_344;
ap_reg_pp0_iter22_tmp_8_reg_334 <= ap_reg_pp0_iter21_tmp_8_reg_334;
ap_reg_pp0_iter22_tmp_i_i_reg_348 <= ap_reg_pp0_iter21_tmp_i_i_reg_348;
ap_reg_pp0_iter22_tmp_reg_339 <= ap_reg_pp0_iter21_tmp_reg_339;
ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter22_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter23_tmp_8_reg_334 <= ap_reg_pp0_iter22_tmp_8_reg_334;
ap_reg_pp0_iter23_tmp_reg_339 <= ap_reg_pp0_iter22_tmp_reg_339;
ap_reg_pp0_iter2_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter1_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter2_tmp_8_reg_334 <= tmp_8_reg_334;
ap_reg_pp0_iter2_tmp_reg_339 <= tmp_reg_339;
ap_reg_pp0_iter3_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter2_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter3_tmp_1_i_i_reg_344 <= tmp_1_i_i_reg_344;
ap_reg_pp0_iter3_tmp_8_reg_334 <= ap_reg_pp0_iter2_tmp_8_reg_334;
ap_reg_pp0_iter3_tmp_i_i_reg_348 <= tmp_i_i_reg_348;
ap_reg_pp0_iter3_tmp_reg_339 <= ap_reg_pp0_iter2_tmp_reg_339;
ap_reg_pp0_iter4_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter3_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter4_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter3_tmp_1_i_i_reg_344;
ap_reg_pp0_iter4_tmp_8_reg_334 <= ap_reg_pp0_iter3_tmp_8_reg_334;
ap_reg_pp0_iter4_tmp_i_i_reg_348 <= ap_reg_pp0_iter3_tmp_i_i_reg_348;
ap_reg_pp0_iter4_tmp_reg_339 <= ap_reg_pp0_iter3_tmp_reg_339;
ap_reg_pp0_iter5_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter4_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter5_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter4_tmp_1_i_i_reg_344;
ap_reg_pp0_iter5_tmp_8_reg_334 <= ap_reg_pp0_iter4_tmp_8_reg_334;
ap_reg_pp0_iter5_tmp_i_i_reg_348 <= ap_reg_pp0_iter4_tmp_i_i_reg_348;
ap_reg_pp0_iter5_tmp_reg_339 <= ap_reg_pp0_iter4_tmp_reg_339;
ap_reg_pp0_iter6_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter5_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter6_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter5_tmp_1_i_i_reg_344;
ap_reg_pp0_iter6_tmp_8_reg_334 <= ap_reg_pp0_iter5_tmp_8_reg_334;
ap_reg_pp0_iter6_tmp_i_i_reg_348 <= ap_reg_pp0_iter5_tmp_i_i_reg_348;
ap_reg_pp0_iter6_tmp_reg_339 <= ap_reg_pp0_iter5_tmp_reg_339;
ap_reg_pp0_iter7_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter6_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter7_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter6_tmp_1_i_i_reg_344;
ap_reg_pp0_iter7_tmp_8_reg_334 <= ap_reg_pp0_iter6_tmp_8_reg_334;
ap_reg_pp0_iter7_tmp_i_i_reg_348 <= ap_reg_pp0_iter6_tmp_i_i_reg_348;
ap_reg_pp0_iter7_tmp_reg_339 <= ap_reg_pp0_iter6_tmp_reg_339;
ap_reg_pp0_iter8_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter7_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter8_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter7_tmp_1_i_i_reg_344;
ap_reg_pp0_iter8_tmp_8_reg_334 <= ap_reg_pp0_iter7_tmp_8_reg_334;
ap_reg_pp0_iter8_tmp_i_i_reg_348 <= ap_reg_pp0_iter7_tmp_i_i_reg_348;
ap_reg_pp0_iter8_tmp_reg_339 <= ap_reg_pp0_iter7_tmp_reg_339;
ap_reg_pp0_iter9_exitcond_i_i_i_reg_318 <= ap_reg_pp0_iter8_exitcond_i_i_i_reg_318;
ap_reg_pp0_iter9_tmp_1_i_i_reg_344 <= ap_reg_pp0_iter8_tmp_1_i_i_reg_344;
ap_reg_pp0_iter9_tmp_8_reg_334 <= ap_reg_pp0_iter8_tmp_8_reg_334;
ap_reg_pp0_iter9_tmp_i_i_reg_348 <= ap_reg_pp0_iter8_tmp_i_i_reg_348;
ap_reg_pp0_iter9_tmp_reg_339 <= ap_reg_pp0_iter8_tmp_reg_339;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_reg_pp0_iter1_exitcond_i_i_i_reg_318 <= exitcond_i_i_i_reg_318;
exitcond_i_i_i_reg_318 <= exitcond_i_i_i_fu_226_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_start = ap_const_logic_0) or (tmp_3_cast_loc_empty_n = ap_const_logic_0) or (min_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (max_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
extLd_reg_299(7 downto 0) <= extLd_fu_189_p1(7 downto 0);
max_read_reg_279 <= max_dout;
min_read_reg_284 <= min_dout;
p_cols_assign_cast_lo_reg_294 <= p_cols_assign_cast_loc_dout;
p_rows_assign_cast_lo_reg_289 <= p_rows_assign_cast_loc_dout;
tmp_8_tr_cast_i_i_ca_reg_304 <= tmp_8_tr_cast_i_i_ca_fu_203_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
i_V_reg_313 <= i_V_fu_216_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_i_i_fu_241_p2 = ap_const_lv1_0) and (tmp_1_i_i_fu_237_p2 = ap_const_lv1_0) and (ap_reg_pp0_iter1_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
tmp_10_i_i_reg_352 <= tmp_10_i_i_fu_265_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter1_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
tmp_1_i_i_reg_344 <= tmp_1_i_i_fu_237_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
tmp_8_reg_334 <= img1_data_stream_1_V_dout;
tmp_9_reg_327 <= img1_data_stream_0_V_dout;
tmp_reg_339 <= img1_data_stream_2_V_dout;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_1_i_i_fu_237_p2 = ap_const_lv1_0) and (ap_reg_pp0_iter1_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
tmp_i_i_reg_348 <= tmp_i_i_fu_241_p2;
end if;
end if;
end process;
extLd_reg_299(8) <= '0';
ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, max_empty_n, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, min_empty_n, tmp_3_cast_loc_empty_n, ap_enable_reg_pp0_iter24, ap_enable_reg_pp0_iter1, exitcond51_i_i_i_fu_211_p2, ap_CS_fsm_state2, exitcond_i_i_i_fu_226_p2, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_subdone, ap_enable_reg_pp0_iter23)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if ((not(((ap_start = ap_const_logic_0) or (tmp_3_cast_loc_empty_n = ap_const_logic_0) or (min_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (max_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (exitcond51_i_i_i_fu_211_p2 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage0 =>
if ((not(((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (exitcond_i_i_i_fu_226_p2 = ap_const_lv1_1))) and not(((ap_enable_reg_pp0_iter23 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter24 = ap_const_logic_1))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
elsif ((((ap_enable_reg_pp0_iter23 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter24 = ap_const_logic_1)) or ((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (exitcond_i_i_i_fu_226_p2 = ap_const_lv1_1)))) then
ap_NS_fsm <= ap_ST_fsm_state28;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_state28 =>
ap_NS_fsm <= ap_ST_fsm_state2;
when others =>
ap_NS_fsm <= "XXXX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state28 <= ap_CS_fsm(3);
ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_01001_assign_proc : process(img2_data_stream_0_V_full_n, img2_data_stream_1_V_full_n, img2_data_stream_2_V_full_n, img1_data_stream_0_V_empty_n, img1_data_stream_1_V_empty_n, img1_data_stream_2_V_empty_n, ap_enable_reg_pp0_iter24, exitcond_i_i_i_reg_318, ap_reg_pp0_iter23_exitcond_i_i_i_reg_318, ap_enable_reg_pp0_iter1)
begin
ap_block_pp0_stage0_01001 <= (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img1_data_stream_2_V_empty_n = ap_const_logic_0)) or ((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img1_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img1_data_stream_0_V_empty_n = ap_const_logic_0)))) or ((ap_enable_reg_pp0_iter24 = ap_const_logic_1) and (((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img2_data_stream_2_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img2_data_stream_1_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img2_data_stream_0_V_full_n = ap_const_logic_0)))));
end process;
ap_block_pp0_stage0_11001_assign_proc : process(img2_data_stream_0_V_full_n, img2_data_stream_1_V_full_n, img2_data_stream_2_V_full_n, img1_data_stream_0_V_empty_n, img1_data_stream_1_V_empty_n, img1_data_stream_2_V_empty_n, ap_enable_reg_pp0_iter24, exitcond_i_i_i_reg_318, ap_reg_pp0_iter23_exitcond_i_i_i_reg_318, ap_enable_reg_pp0_iter1)
begin
ap_block_pp0_stage0_11001 <= (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img1_data_stream_2_V_empty_n = ap_const_logic_0)) or ((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img1_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img1_data_stream_0_V_empty_n = ap_const_logic_0)))) or ((ap_enable_reg_pp0_iter24 = ap_const_logic_1) and (((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img2_data_stream_2_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img2_data_stream_1_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img2_data_stream_0_V_full_n = ap_const_logic_0)))));
end process;
ap_block_pp0_stage0_subdone_assign_proc : process(img2_data_stream_0_V_full_n, img2_data_stream_1_V_full_n, img2_data_stream_2_V_full_n, img1_data_stream_0_V_empty_n, img1_data_stream_1_V_empty_n, img1_data_stream_2_V_empty_n, ap_enable_reg_pp0_iter24, exitcond_i_i_i_reg_318, ap_reg_pp0_iter23_exitcond_i_i_i_reg_318, ap_enable_reg_pp0_iter1)
begin
ap_block_pp0_stage0_subdone <= (((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img1_data_stream_2_V_empty_n = ap_const_logic_0)) or ((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img1_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img1_data_stream_0_V_empty_n = ap_const_logic_0)))) or ((ap_enable_reg_pp0_iter24 = ap_const_logic_1) and (((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img2_data_stream_2_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img2_data_stream_1_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img2_data_stream_0_V_full_n = ap_const_logic_0)))));
end process;
ap_block_state1_assign_proc : process(ap_start, ap_done_reg, max_empty_n, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, min_empty_n, tmp_3_cast_loc_empty_n)
begin
ap_block_state1 <= ((ap_start = ap_const_logic_0) or (tmp_3_cast_loc_empty_n = ap_const_logic_0) or (min_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (max_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
ap_block_state10_pp0_stage0_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state11_pp0_stage0_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state12_pp0_stage0_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state13_pp0_stage0_iter10 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state14_pp0_stage0_iter11 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state15_pp0_stage0_iter12 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state16_pp0_stage0_iter13 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state17_pp0_stage0_iter14 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state18_pp0_stage0_iter15 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state19_pp0_stage0_iter16 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state20_pp0_stage0_iter17 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state21_pp0_stage0_iter18 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state22_pp0_stage0_iter19 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state23_pp0_stage0_iter20 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state24_pp0_stage0_iter21 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state25_pp0_stage0_iter22 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state26_pp0_stage0_iter23 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state27_pp0_stage0_iter24_assign_proc : process(img2_data_stream_0_V_full_n, img2_data_stream_1_V_full_n, img2_data_stream_2_V_full_n, ap_reg_pp0_iter23_exitcond_i_i_i_reg_318)
begin
ap_block_state27_pp0_stage0_iter24 <= (((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img2_data_stream_2_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img2_data_stream_1_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img2_data_stream_0_V_full_n = ap_const_logic_0)));
end process;
ap_block_state3_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage0_iter1_assign_proc : process(img1_data_stream_0_V_empty_n, img1_data_stream_1_V_empty_n, img1_data_stream_2_V_empty_n, exitcond_i_i_i_reg_318)
begin
ap_block_state4_pp0_stage0_iter1 <= (((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img1_data_stream_2_V_empty_n = ap_const_logic_0)) or ((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img1_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (img1_data_stream_0_V_empty_n = ap_const_logic_0)));
end process;
ap_block_state5_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage0_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp0_stage0_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_condition_362_assign_proc : process(ap_reg_pp0_iter22_exitcond_i_i_i_reg_318, ap_reg_pp0_iter22_tmp_1_i_i_reg_344, ap_reg_pp0_iter22_tmp_i_i_reg_348)
begin
ap_condition_362 <= ((ap_reg_pp0_iter22_tmp_i_i_reg_348 = ap_const_lv1_0) and (ap_reg_pp0_iter22_tmp_1_i_i_reg_344 = ap_const_lv1_0) and (ap_reg_pp0_iter22_exitcond_i_i_i_reg_318 = ap_const_lv1_0));
end process;
ap_condition_490_assign_proc : process(ap_reg_pp0_iter1_exitcond_i_i_i_reg_318, tmp_1_i_i_fu_237_p2, tmp_i_i_fu_241_p2)
begin
ap_condition_490 <= ((tmp_1_i_i_fu_237_p2 = ap_const_lv1_0) and (ap_reg_pp0_iter1_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (tmp_i_i_fu_241_p2 = ap_const_lv1_1));
end process;
ap_condition_pp0_exit_iter0_state3_assign_proc : process(exitcond_i_i_i_fu_226_p2)
begin
if ((exitcond_i_i_i_fu_226_p2 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_done_reg, exitcond51_i_i_i_fu_211_p2, ap_CS_fsm_state2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (exitcond51_i_i_i_fu_211_p2 = ap_const_lv1_1))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter24, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9, ap_enable_reg_pp0_iter10, ap_enable_reg_pp0_iter11, ap_enable_reg_pp0_iter12, ap_enable_reg_pp0_iter13, ap_enable_reg_pp0_iter14, ap_enable_reg_pp0_iter15, ap_enable_reg_pp0_iter16, ap_enable_reg_pp0_iter17, ap_enable_reg_pp0_iter18, ap_enable_reg_pp0_iter19, ap_enable_reg_pp0_iter20, ap_enable_reg_pp0_iter21, ap_enable_reg_pp0_iter22, ap_enable_reg_pp0_iter23)
begin
if (((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter24 = ap_const_logic_0) and (ap_enable_reg_pp0_iter23 = ap_const_logic_0) and (ap_enable_reg_pp0_iter22 = ap_const_logic_0) and (ap_enable_reg_pp0_iter21 = ap_const_logic_0) and (ap_enable_reg_pp0_iter20 = ap_const_logic_0) and (ap_enable_reg_pp0_iter19 = ap_const_logic_0) and (ap_enable_reg_pp0_iter18 = ap_const_logic_0) and (ap_enable_reg_pp0_iter17 = ap_const_logic_0) and (ap_enable_reg_pp0_iter16 = ap_const_logic_0) and (ap_enable_reg_pp0_iter15 = ap_const_logic_0) and (ap_enable_reg_pp0_iter14 = ap_const_logic_0) and (ap_enable_reg_pp0_iter13 = ap_const_logic_0) and (ap_enable_reg_pp0_iter12 = ap_const_logic_0) and (ap_enable_reg_pp0_iter11 = ap_const_logic_0) and (ap_enable_reg_pp0_iter10 = ap_const_logic_0) and (ap_enable_reg_pp0_iter9 = ap_const_logic_0) and (ap_enable_reg_pp0_iter8 = ap_const_logic_0) and (ap_enable_reg_pp0_iter7 = ap_const_logic_0) and (ap_enable_reg_pp0_iter6 = ap_const_logic_0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_0) and (ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_phi_reg_pp0_iter0_tmp_2_reg_173 <= "XXXXXXXX";
ap_ready_assign_proc : process(exitcond51_i_i_i_fu_211_p2, ap_CS_fsm_state2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (exitcond51_i_i_i_fu_211_p2 = ap_const_lv1_1))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
exitcond51_i_i_i_fu_211_p2 <= "1" when (t_V_cast_i_i_fu_207_p1 = p_rows_assign_cast_lo_reg_289) else "0";
exitcond_i_i_i_fu_226_p2 <= "1" when (t_V_1_cast_i_i_fu_222_p1 = p_cols_assign_cast_lo_reg_294) else "0";
extLd_fu_189_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_3_cast_loc_dout),9));
grp_fu_271_ce_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
grp_fu_271_ce <= ap_const_logic_1;
else
grp_fu_271_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_271_p1 <= tmp_8_tr_cast_i_i_ca_reg_304(9 - 1 downto 0);
i_V_fu_216_p2 <= std_logic_vector(unsigned(t_V_reg_151) + unsigned(ap_const_lv11_1));
img1_data_stream_0_V_blk_n_assign_proc : process(img1_data_stream_0_V_empty_n, ap_block_pp0_stage0, exitcond_i_i_i_reg_318, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1)
begin
if (((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
img1_data_stream_0_V_blk_n <= img1_data_stream_0_V_empty_n;
else
img1_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
img1_data_stream_0_V_read_assign_proc : process(exitcond_i_i_i_reg_318, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
img1_data_stream_0_V_read <= ap_const_logic_1;
else
img1_data_stream_0_V_read <= ap_const_logic_0;
end if;
end process;
img1_data_stream_1_V_blk_n_assign_proc : process(img1_data_stream_1_V_empty_n, ap_block_pp0_stage0, exitcond_i_i_i_reg_318, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1)
begin
if (((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
img1_data_stream_1_V_blk_n <= img1_data_stream_1_V_empty_n;
else
img1_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
img1_data_stream_1_V_read_assign_proc : process(exitcond_i_i_i_reg_318, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
img1_data_stream_1_V_read <= ap_const_logic_1;
else
img1_data_stream_1_V_read <= ap_const_logic_0;
end if;
end process;
img1_data_stream_2_V_blk_n_assign_proc : process(img1_data_stream_2_V_empty_n, ap_block_pp0_stage0, exitcond_i_i_i_reg_318, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1)
begin
if (((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
img1_data_stream_2_V_blk_n <= img1_data_stream_2_V_empty_n;
else
img1_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
img1_data_stream_2_V_read_assign_proc : process(exitcond_i_i_i_reg_318, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_11001)
begin
if (((exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
img1_data_stream_2_V_read <= ap_const_logic_1;
else
img1_data_stream_2_V_read <= ap_const_logic_0;
end if;
end process;
img2_data_stream_0_V_blk_n_assign_proc : process(img2_data_stream_0_V_full_n, ap_enable_reg_pp0_iter24, ap_block_pp0_stage0, ap_reg_pp0_iter23_exitcond_i_i_i_reg_318)
begin
if (((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter24 = ap_const_logic_1))) then
img2_data_stream_0_V_blk_n <= img2_data_stream_0_V_full_n;
else
img2_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
img2_data_stream_0_V_din <= ap_phi_reg_pp0_iter24_tmp_2_reg_173;
img2_data_stream_0_V_write_assign_proc : process(ap_enable_reg_pp0_iter24, ap_reg_pp0_iter23_exitcond_i_i_i_reg_318, ap_block_pp0_stage0_11001)
begin
if (((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter24 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
img2_data_stream_0_V_write <= ap_const_logic_1;
else
img2_data_stream_0_V_write <= ap_const_logic_0;
end if;
end process;
img2_data_stream_1_V_blk_n_assign_proc : process(img2_data_stream_1_V_full_n, ap_enable_reg_pp0_iter24, ap_block_pp0_stage0, ap_reg_pp0_iter23_exitcond_i_i_i_reg_318)
begin
if (((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter24 = ap_const_logic_1))) then
img2_data_stream_1_V_blk_n <= img2_data_stream_1_V_full_n;
else
img2_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
img2_data_stream_1_V_din <= ap_reg_pp0_iter23_tmp_8_reg_334;
img2_data_stream_1_V_write_assign_proc : process(ap_enable_reg_pp0_iter24, ap_reg_pp0_iter23_exitcond_i_i_i_reg_318, ap_block_pp0_stage0_11001)
begin
if (((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter24 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
img2_data_stream_1_V_write <= ap_const_logic_1;
else
img2_data_stream_1_V_write <= ap_const_logic_0;
end if;
end process;
img2_data_stream_2_V_blk_n_assign_proc : process(img2_data_stream_2_V_full_n, ap_enable_reg_pp0_iter24, ap_block_pp0_stage0, ap_reg_pp0_iter23_exitcond_i_i_i_reg_318)
begin
if (((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter24 = ap_const_logic_1))) then
img2_data_stream_2_V_blk_n <= img2_data_stream_2_V_full_n;
else
img2_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
img2_data_stream_2_V_din <= ap_reg_pp0_iter23_tmp_reg_339;
img2_data_stream_2_V_write_assign_proc : process(ap_enable_reg_pp0_iter24, ap_reg_pp0_iter23_exitcond_i_i_i_reg_318, ap_block_pp0_stage0_11001)
begin
if (((ap_reg_pp0_iter23_exitcond_i_i_i_reg_318 = ap_const_lv1_0) and (ap_enable_reg_pp0_iter24 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
img2_data_stream_2_V_write <= ap_const_logic_1;
else
img2_data_stream_2_V_write <= ap_const_logic_0;
end if;
end process;
j_V_fu_231_p2 <= std_logic_vector(unsigned(t_V_2_reg_162) + unsigned(ap_const_lv11_1));
max_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, max_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
max_blk_n <= max_empty_n;
else
max_blk_n <= ap_const_logic_1;
end if;
end process;
max_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, max_empty_n, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, min_empty_n, tmp_3_cast_loc_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (tmp_3_cast_loc_empty_n = ap_const_logic_0) or (min_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (max_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
max_read <= ap_const_logic_1;
else
max_read <= ap_const_logic_0;
end if;
end process;
min_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, min_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
min_blk_n <= min_empty_n;
else
min_blk_n <= ap_const_logic_1;
end if;
end process;
min_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, max_empty_n, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, min_empty_n, tmp_3_cast_loc_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (tmp_3_cast_loc_empty_n = ap_const_logic_0) or (min_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (max_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
min_read <= ap_const_logic_1;
else
min_read <= ap_const_logic_0;
end if;
end process;
p_cols_assign_cast_loc_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_cols_assign_cast_loc_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_cols_assign_cast_loc_blk_n <= p_cols_assign_cast_loc_empty_n;
else
p_cols_assign_cast_loc_blk_n <= ap_const_logic_1;
end if;
end process;
p_cols_assign_cast_loc_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, max_empty_n, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, min_empty_n, tmp_3_cast_loc_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (tmp_3_cast_loc_empty_n = ap_const_logic_0) or (min_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (max_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_cols_assign_cast_loc_read <= ap_const_logic_1;
else
p_cols_assign_cast_loc_read <= ap_const_logic_0;
end if;
end process;
p_rows_assign_cast_loc_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_rows_assign_cast_loc_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_rows_assign_cast_loc_blk_n <= p_rows_assign_cast_loc_empty_n;
else
p_rows_assign_cast_loc_blk_n <= ap_const_logic_1;
end if;
end process;
p_rows_assign_cast_loc_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, max_empty_n, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, min_empty_n, tmp_3_cast_loc_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (tmp_3_cast_loc_empty_n = ap_const_logic_0) or (min_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (max_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_rows_assign_cast_loc_read <= ap_const_logic_1;
else
p_rows_assign_cast_loc_read <= ap_const_logic_0;
end if;
end process;
p_shl_i_i_fu_257_p3 <= (tmp_9_i_i_fu_248_p2 & ap_const_lv8_0);
t_V_1_cast_i_i_fu_222_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(t_V_2_reg_162),12));
t_V_cast_i_i_fu_207_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(t_V_reg_151),12));
tmp_10_i_i_fu_265_p2 <= std_logic_vector(unsigned(p_shl_i_i_fu_257_p3) - unsigned(tmp_9_cast_i_i_fu_253_p1));
tmp_1_i_i_fu_237_p2 <= "1" when (unsigned(tmp_9_reg_327) > unsigned(max_read_reg_279)) else "0";
tmp_3_cast_loc_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, tmp_3_cast_loc_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
tmp_3_cast_loc_blk_n <= tmp_3_cast_loc_empty_n;
else
tmp_3_cast_loc_blk_n <= ap_const_logic_1;
end if;
end process;
tmp_3_cast_loc_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, max_empty_n, p_rows_assign_cast_loc_empty_n, p_cols_assign_cast_loc_empty_n, min_empty_n, tmp_3_cast_loc_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (tmp_3_cast_loc_empty_n = ap_const_logic_0) or (min_empty_n = ap_const_logic_0) or (p_cols_assign_cast_loc_empty_n = ap_const_logic_0) or (p_rows_assign_cast_loc_empty_n = ap_const_logic_0) or (max_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
tmp_3_cast_loc_read <= ap_const_logic_1;
else
tmp_3_cast_loc_read <= ap_const_logic_0;
end if;
end process;
tmp_7_fu_275_p1 <= grp_fu_271_p2(8 - 1 downto 0);
tmp_8_cast_i_i_fu_245_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_9_reg_327),9));
tmp_8_tr_cast_i_i_ca_fu_203_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_8_tr_i_i_fu_197_p2),17));
tmp_8_tr_i_i_fu_197_p2 <= std_logic_vector(unsigned(tmp_cast_i_i_fu_193_p1) - unsigned(extLd_fu_189_p1));
tmp_9_cast_i_i_fu_253_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_9_i_i_fu_248_p2),17));
tmp_9_i_i_fu_248_p2 <= std_logic_vector(unsigned(tmp_8_cast_i_i_fu_245_p1) - unsigned(extLd_reg_299));
tmp_cast_i_i_fu_193_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(max_dout),9));
tmp_i_i_fu_241_p2 <= "1" when (unsigned(tmp_9_reg_327) < unsigned(min_read_reg_284)) else "0";
end behav;
|
mit
|
5b8713a6a0a1daa1cc4375a3565d3831
| 0.602365 | 2.599051 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_saturation_enhance_1_0/hdl/vhdl/start_for_CvtColoudo.vhd
| 1 | 4,490 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity start_for_CvtColoudo_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 5);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end start_for_CvtColoudo_shiftReg;
architecture rtl of start_for_CvtColoudo_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity start_for_CvtColoudo is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 5);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of start_for_CvtColoudo is
component start_for_CvtColoudo_shiftReg is
generic (
DATA_WIDTH : integer := 1;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 5);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_start_for_CvtColoudo_shiftReg : start_for_CvtColoudo_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
mit
|
a6b6d871283326145617f8e8b3121ac3
| 0.532962 | 3.594876 | false | false | false | false |
Digilent/vivado-library
|
ip/axi_dynclk/src/axi_dynclk.vhd
| 1 | 11,757 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VComponents.all;
entity axi_dynclk is
generic (
-- Users to add parameters here
kRefClkFreqHz : natural := 100_000_000;
kVersionMajor : natural := 1;
kVersionMinor : natural := 0;
kAddBUFMR : boolean := false; --true, if BUFMR should be added between MMCM and BUFIO
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S_AXI_LITE
C_S_AXI_LITE_DATA_WIDTH : integer := 32;
C_S_AXI_LITE_ADDR_WIDTH : integer := 6
);
port (
-- Users to add ports here
REF_CLK_I : in std_logic;
PXL_CLK_O : out std_logic;
PXL_CLK_5X_O : out std_logic;
LOCKED_O : out std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S_AXI_LITE
s_axi_lite_aclk : in std_logic;
s_axi_lite_aresetn : in std_logic;
s_axi_lite_awaddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_awprot : in std_logic_vector(2 downto 0);
s_axi_lite_awvalid : in std_logic;
s_axi_lite_awready : out std_logic;
s_axi_lite_wdata : in std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_wstrb : in std_logic_vector((C_S_AXI_LITE_DATA_WIDTH/8)-1 downto 0);
s_axi_lite_wvalid : in std_logic;
s_axi_lite_wready : out std_logic;
s_axi_lite_bresp : out std_logic_vector(1 downto 0);
s_axi_lite_bvalid : out std_logic;
s_axi_lite_bready : in std_logic;
s_axi_lite_araddr : in std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);
s_axi_lite_arprot : in std_logic_vector(2 downto 0);
s_axi_lite_arvalid : in std_logic;
s_axi_lite_arready : out std_logic;
s_axi_lite_rdata : out std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
s_axi_lite_rresp : out std_logic_vector(1 downto 0);
s_axi_lite_rvalid : out std_logic;
s_axi_lite_rready : in std_logic
);
end axi_dynclk;
architecture arch_imp of axi_dynclk is
-- component declaration
component axi_dynclk_S00_AXI is
generic (
kRefClkFreqHz : natural := 100_000_000;
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
CTRL_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
STAT_REG :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_O_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FB_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FRAC_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_DIV_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_LOCK_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FLTR_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component axi_dynclk_S00_AXI;
component mmcme2_drp
generic (
DIV_F : integer
);
port(
SEN : in std_logic;
SCLK : in std_logic;
RST : in std_logic;
S1_CLKOUT0 : in std_logic_vector(35 downto 0);
S1_CLKFBOUT : in std_logic_vector(35 downto 0);
S1_DIVCLK : in std_logic_vector(13 downto 0);
S1_LOCK : in std_logic_vector(39 downto 0);
S1_DIGITAL_FILT : in std_logic_vector(9 downto 0);
REF_CLK : in std_logic;
CLKFBOUT_I : in std_logic;
CLKFBOUT_O : out std_logic;
SRDY : out std_logic;
PXL_CLK : out std_logic;
LOCKED_O : out std_logic
);
end component;
signal CTRL_REG : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
signal STAT_REG : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
signal CLK_O_REG : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
signal CLK_FB_REG : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
signal CLK_FRAC_REG : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
signal CLK_DIV_REG : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
signal CLK_LOCK_REG : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
signal CLK_FLTR_REG : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
type CLK_STATE_TYPE is (RESET, WAIT_LOCKED, WAIT_EN, WAIT_SRDY, ENABLED);
signal clk_state : CLK_STATE_TYPE := RESET;
signal srdy : std_logic;
signal pxl_clk : std_logic;
signal aLocked, xLocked, xBUFR_Rst : std_logic;
signal xLckdFallingFlag, xLckdRisingFlag : std_logic;
signal xLocked_q : std_logic_vector(1 downto 0);
signal sen_reg : std_logic := '0';
signal mmcm_fbclk_in : std_logic;
signal mmcm_fbclk_out : std_logic;
signal mmcm_clk : std_logic;
signal bufio_in : std_logic;
begin
-- Instantiation of Axi Bus Interface S00_AXI
axi_dynclk_S00_AXI_inst : axi_dynclk_S00_AXI
generic map (
kRefClkFreqHz => kRefClkFreqHz,
C_S_AXI_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH
)
port map (
CTRL_REG => CTRL_REG,
STAT_REG => STAT_REG,
CLK_O_REG => CLK_O_REG,
CLK_FB_REG => CLK_FB_REG,
CLK_FRAC_REG => CLK_FRAC_REG,
CLK_DIV_REG => CLK_DIV_REG,
CLK_LOCK_REG => CLK_LOCK_REG,
CLK_FLTR_REG => CLK_FLTR_REG,
S_AXI_ACLK => s_axi_lite_aclk,
S_AXI_ARESETN => s_axi_lite_aresetn,
S_AXI_AWADDR => s_axi_lite_awaddr,
S_AXI_AWPROT => s_axi_lite_awprot,
S_AXI_AWVALID => s_axi_lite_awvalid,
S_AXI_AWREADY => s_axi_lite_awready,
S_AXI_WDATA => s_axi_lite_wdata,
S_AXI_WSTRB => s_axi_lite_wstrb,
S_AXI_WVALID => s_axi_lite_wvalid,
S_AXI_WREADY => s_axi_lite_wready,
S_AXI_BRESP => s_axi_lite_bresp,
S_AXI_BVALID => s_axi_lite_bvalid,
S_AXI_BREADY => s_axi_lite_bready,
S_AXI_ARADDR => s_axi_lite_araddr,
S_AXI_ARPROT => s_axi_lite_arprot,
S_AXI_ARVALID => s_axi_lite_arvalid,
S_AXI_ARREADY => s_axi_lite_arready,
S_AXI_RDATA => s_axi_lite_rdata,
S_AXI_RRESP => s_axi_lite_rresp,
S_AXI_RVALID => s_axi_lite_rvalid,
S_AXI_RREADY => s_axi_lite_rready
);
GenerateBUFMR: if kAddBUFMR generate
BUFMR_inst : BUFMR
port map (
O => bufio_in, -- 1-bit output: Clock output (connect to BUFIOs/BUFRs)
I => mmcm_clk -- 1-bit input: Clock input (Connect to IBUF)
);
end generate GenerateBUFMR;
DontGenerateBUFMR: if not kAddBUFMR generate
bufio_in <= mmcm_clk;
end generate DontGenerateBUFMR;
-- Add user logic here
BUFIO_inst : BUFIO
port map (
O => PXL_CLK_5X_O, -- 1-bit output: Clock output (connect to I/O clock loads).
I => bufio_in -- 1-bit input: Clock input (connect to an IBUF or BUFMR).
);
BUFR_inst : BUFR
generic map (
BUFR_DIVIDE => "5", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => pxl_clk, -- 1-bit output: Clock output port
CE => '1', -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => xBUFR_Rst, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => bufio_in -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
xBUFR_Rst <= xLckdRisingFlag; --pulse CLR on BUFR once the clock returns
Inst_mmcme2_drp: mmcme2_drp
GENERIC MAP(
DIV_F => 2
)
PORT MAP(
SEN => sen_reg,
SCLK => s_axi_lite_aclk,
RST => not(s_axi_lite_aresetn),
SRDY => srdy,
S1_CLKOUT0 => CLK_FRAC_REG(3 downto 0) & CLK_O_REG,
S1_CLKFBOUT => CLK_FRAC_REG(19 downto 16) & CLK_FB_REG,
S1_DIVCLK => CLK_DIV_REG(13 downto 0),
S1_LOCK => CLK_FLTR_REG(7 downto 0) & CLK_LOCK_REG,
S1_DIGITAL_FILT => CLK_FLTR_REG(25 downto 16),
REF_CLK => REF_CLK_I,
PXL_CLK => mmcm_clk,
CLKFBOUT_O => mmcm_fbclk_out,
CLKFBOUT_I => mmcm_fbclk_in,
LOCKED_O => aLocked
);
mmcm_fbclk_in <= mmcm_fbclk_out; --Don't bother compensating for any delay, because we don't need a phase relationship between
--REF_CLK and PXL_CLK
SyncAsyncLocked: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2, --use double FF synchronizer
kResetPolarity => '0')
port map (
aReset => s_axi_lite_aresetn,
aIn => aLocked,
OutClk => s_axi_lite_aclk,
oOut => xLocked);
LockedDetect: process(s_axi_lite_aclk)
begin
if Rising_Edge(s_axi_lite_aclk) then
xLocked_q <= xLocked & xLocked_q(1);
xLckdFallingFlag <= xLocked_q(1) and not xLocked;
xLckdRisingFlag <= not xLocked_q(1) and xLocked;
end if;
end process LockedDetect;
PXL_CLK_O <= pxl_clk;
LOCKED_O <= aLocked; --dcm_locked of processor system reset expects direct connection to MMCM_Locked
process (s_axi_lite_aclk)
begin
if (rising_edge(s_axi_lite_aclk)) then
if (s_axi_lite_aresetn = '0') then
clk_state <= RESET;
else
case clk_state is
when RESET =>
clk_state <= WAIT_LOCKED;
when WAIT_LOCKED =>
-- This state ensures that the initial SRDY pulse
-- doesnt interfere with the WAIT_SRDY state
if (xLocked = '1') then
clk_state <= WAIT_EN;
end if;
when WAIT_EN =>
if (CTRL_REG(0) = '1') then
clk_state <= WAIT_SRDY;
end if;
when WAIT_SRDY =>
if (srdy = '1') then
clk_state <= ENABLED;
end if;
when ENABLED =>
if (CTRL_REG(0) = '0') then
clk_state <= WAIT_EN;
end if;
when others => --Never reached
clk_state <= RESET;
end case;
end if;
end if;
end process;
STAT_REG(0) <= '1' when clk_state = ENABLED else
'0';
process (s_axi_lite_aclk)
begin
if (rising_edge(s_axi_lite_aclk)) then
if (s_axi_lite_aresetn = '0') then
sen_reg <= '0';
else
if (clk_state = WAIT_EN and CTRL_REG(0) = '1') then
sen_reg <= '1';
else
sen_reg <= '0';
end if;
end if;
end if;
end process;
-- User logic ends
end arch_imp;
|
mit
|
5b5e8c85eb76d01e4753ccf89be65323
| 0.582632 | 3.039555 | false | false | false | false |
JL-Grande/Ascensor_SED
|
ASCENSOR/convertidor_piso_actual.vhd
| 1 | 1,318 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity convertidor_piso_actual is
PORT(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
piso_actual: IN std_logic_vector(2 DOWNTO 0);
boton_seleccionado: IN std_logic_vector(2 DOWNTO 0);
piso_actual_convertido: OUT std_logic_vector(1 DOWNTO 0);
boton_seleccionado_convertido: OUT std_logic_vector(1 DOWNTO 0)
);
end convertidor_piso_actual;
architecture dataflow of convertidor_piso_actual is
COMPONENT antirrebote_vector
PORT (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
vector_IN : in STD_LOGIC_VECTOR (2 downto 0);
vector_OUT : out STD_LOGIC_VECTOR (2 downto 0));
END COMPONENT;
signal boton_selec_antirrebote:std_logic_vector(2 DOWNTO 0);
begin
inst_antirrebote_vector:antirrebote_vector port map(
CLK => clk,
RST => rst,
vector_IN => boton_seleccionado,
vector_OUT => boton_selec_antirrebote
);
WITH piso_actual SELECT
piso_actual_convertido <= "01" WHEN "001",
"10" WHEN "010",
"11" WHEN "100",
"00" WHEN others;
WITH boton_selec_antirrebote SELECT
boton_seleccionado_convertido <= "01" WHEN "001",
"10" WHEN "010",
"11" WHEN "100",
"00" WHEN others;
end dataflow;
|
gpl-3.0
|
6c2f7f36d0a08e4fa6bc89bed3cd73e3
| 0.659332 | 3.230392 | false | false | false | false |
rickyzhangNYC/Pipelined_Multimedia_Cell_Lite_Unit
|
addsubmodule.vhd
| 1 | 1,455 |
-------------------------------------------------------------------------------
--
-- Title : addsubmodule
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\addsubmodule.vhd
-- Generated : Sat Dec 3 18:19:38 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {addsubmodule} architecture {behavioral}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity addsubmodule is
port(
addorsub: in std_logic;
a: in std_logic_vector (63 downto 0);
b: in std_logic_vector (63 downto 0);
output: out std_logic_vector (63 downto 0)
);
end addsubmodule;
--}} End of automatically maintained section
architecture behavioral of addsubmodule is
begin
addorsubx: process (addorsub,a,b)
begin
if addorsub = '0' then
output <= a;
elsif addorsub = '1' then
output <= b;
else
output <= (others => '-');
end if;
end process addorsubx;
end behavioral;
|
apache-2.0
|
44cbb048ece4b00151d567bb456c74b8
| 0.471478 | 4.133523 | false | false | false | false |
Digilent/vivado-library
|
ip/MIPI_CSI_2_RX/hdl/MIPI_CSI2_Rx.vhd
| 1 | 14,192 |
-------------------------------------------------------------------------------
--
-- File: MIPI_CSI2_Rx.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI CSI-2 Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.DebugLib.all;
entity MIPI_CSI2_Rx is
Generic (
kTargetDT : string := "RAW10";
kDebug : boolean := true;
--PPI
kLaneCount : natural range 1 to 4 := 2; --[1,2,4]
--Video Format
C_M_AXIS_COMPONENT_WIDTH : natural := 10; -- [8,10]
C_M_AXIS_TDATA_WIDTH : natural := 40;
C_M_MAX_SAMPLES_PER_CLOCK : natural := 4
);
Port (
--PPI
RxByteClkHS : in STD_LOGIC;
aClkStopstate : in std_logic;
aRxClkActiveHS : in std_logic;
rbRxDataHS : in STD_LOGIC_VECTOR (8 * kLaneCount - 1 downto 0);
rbRxSyncHS : in STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
rbRxValidHS : in STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
rbRxActiveHS : in STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
aDEnable : out STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
aClkEnable : out STD_LOGIC;
--axi stream signals
m_axis_video_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_video_tvalid : out std_logic;
m_axis_video_tready : in std_logic;
m_axis_video_tlast : out std_logic;
m_axis_video_tuser : out std_logic_vector(0 downto 0);
video_aresetn : in std_logic;
video_aclk : in std_logic;
vEnable : in std_logic --TODO proper buffer flushing on disable, perhaps waiting on active transfer to end
);
end MIPI_CSI2_Rx;
architecture Behavioral of MIPI_CSI2_Rx is
component LM is
Generic(
kMaxLaneCount : natural := 4;
--PPI
kLaneCount : natural range 1 to 4 := 2 --[1,2,4]
);
Port (
RxByteClkHS : in STD_LOGIC;
RxDataHS : in STD_LOGIC_VECTOR (8 * kLaneCount - 1 downto 0);
RxSyncHS : in STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
RxValidHS : in STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
RxActiveHS : in STD_LOGIC_VECTOR (kLaneCount - 1 downto 0);
--Master AXI-Stream
rbMAxisTdata : out std_logic_vector(8 * kMaxLaneCount - 1 downto 0);
rbMAxisTkeep : out std_logic_vector(kMaxLaneCount - 1 downto 0);
rbMAxisTvalid : out std_logic;
rbMAxisTready : in std_logic;
rbMAxisTlast : out std_logic;
rbErrSkew : out std_logic;
rbErrOvf : out std_logic;
rbEn : in std_logic;
rbRst : in std_logic;
dbgLMLane : out DebugLMLanes_t;
dbgLM : out DebugLM_t
);
end component LM;
component LLP is
Generic(
kMaxLaneCount : natural := 4;
--PPI
kLaneCount : natural range 1 to 4 := 2; --[1,2,4];
kTargetDT : string := "RAW10"
);
Port (
SAxisClk : in STD_LOGIC;
--Slave AXI-Stream
sAxisTdata : in std_logic_vector(8 * kMaxLaneCount - 1 downto 0);
sAxisTkeep : in std_logic_vector(kMaxLaneCount - 1 downto 0);
sAxisTvalid : in std_logic;
sAxisTready : out std_logic;
sAxisTlast : in std_logic;
MAxisClk : in std_logic;
--Master AXI-Stream
mAxisTdata : out std_logic_vector(40 - 1 downto 0);
mAxisTvalid : out std_logic;
mAxisTready : in std_logic;
mAxisTlast : out std_logic;
mAxisTuser : out std_logic_vector(0 downto 0);
sOverflow : out std_logic;
aRst : in std_logic; -- global asynchronous reset; synchronized internally to both clock domains
dbgLLP : out DebugLLP_t
);
end component;
-- VHDL-2008 back-port
function orv(vec : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in vec'range loop
result := result or vec(i);
end loop;
return result;
end orv;
-- VHDL-2008 back-port
function andv(vec : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in vec'range loop
result := result and vec(i);
end loop;
return result;
end andv;
constant kMaxLaneCount : natural := 4;
signal rbLMAxisTdata : std_logic_vector(8 * kMaxLaneCount - 1 downto 0);
signal rbLMAxisTkeep : std_logic_vector(kMaxLaneCount - 1 downto 0);
signal rbLMAxisTvalid, rbLMAxisTlast : std_logic;
signal rbLMErrOvf, rbLMErrSkew : std_logic;
signal rbLLPAxisTready : std_logic;
signal rbRst_n, rbEn : std_logic;
signal vTready, vRst : std_logic;
signal dbgLMLane : DebugLMLanes_t;
signal dbgLM : DebugLM_t;
signal dbgLLP : DebugLLP_t;
signal rbRxClkTrigOut, vRxClkTrigOut, vTrigIn, vTrigInAck, rbTrigInAck : std_logic;
signal rbRxClkLaneTrigOut, vRxClkLaneTrigOut : std_logic_vector(kMaxLaneCount - 1 downto 0);
signal aClkEnableInt : std_logic;
signal aDEnableInt : std_logic_vector(kMaxLaneCount - 1 downto 0);
begin
-- Synchronize video_aresetn into the RxByteClkHS domain
SyncReset: entity work.ResetBridge
generic map (
kPolarity => '0')
port map (
aRst => video_aresetn,
OutClk => RxByteClkHS,
oRst => rbRst_n);
-- Synchronize vEnable into the RxByteClkHS domain
SyncAsyncEnable: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2, --use double FF synchronizer
kResetPolarity => '0')
port map (
aReset => rbRst_n,
aIn => vEnable,
OutClk => RxByteClkHS,
oOut => rbEn);
GlitchFree_vRst: process(video_aclk)
begin
if Rising_Edge(video_aclk) then
vRst <= not video_aresetn;
end if;
end process;
PPI_Clock_Enable: process(video_aclk)
begin
if Rising_Edge(video_aclk) then
aClkEnableInt <= vEnable and video_aresetn;
aDEnableInt <= (others => vEnable and video_aresetn);
end if;
end process;
aClkEnable <= aClkEnableInt;
-- Initially data lanes were only enabled when the LLP module below doing
-- data buffering was ready to receive data. However, this was problematic for
-- two reasons:
-- 1. not all lanes (clock and data) were enabled simultaneously and
-- 2. since LLP requires a few RxByteClkHS clock cycles to assert ready on its
-- slave port, the data lanes were only enabled after the clock lane was already
-- transmitting clock. The data lanes still needed Stop state of T_INIT long
-- at least to complete initialization after enablement, resulting in loss of
-- the first data packets.
-- Instead, we rely on LM to do a limited buffering upon exit from reset and
-- on T_CLK_PRE
--PPI_Data_Enable: process(video_aclk)
--begin
-- if Rising_Edge(video_aclk) then
-- if (video_aresetn = '0') then
-- aDEnableInt <= (others => '0');
-- else
-- if (vEnable = '0') then
-- aDEnableInt <= (others => '0');
-- elsif (vTready = '1') then --LLP buffer should be ready to receive data before enabling the PHY
-- aDEnableInt <= (others => '1');
-- end if;
-- end if;
-- end if;
--end process;
aDEnable <= aDEnableInt(kLaneCount-1 downto 0);
SyncAsyncTready: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2, --use double FF synchronizer
kResetPolarity => '0')
port map (
aReset => video_aresetn,
aIn => rbLLPAxisTready,
OutClk => video_aclk,
oOut => vTready);
-- Lane merger compacts the CSI-2 lane into a wide AXI-Stream bus
-- Both the input and output interfaces are synchronous to RxByteClkHS
-- and it does not buffer data
LM_inst: LM
Generic Map(
kMaxLaneCount => kMaxLaneCount,
kLaneCount => kLaneCount
)
Port Map(
RxByteClkHS => RxByteClkHS,
RxDataHS => rbRxDataHS,
RxSyncHS => rbRxSyncHS,
RxValidHS => rbRxValidHS,
RxActiveHS => rbRxActiveHS,
rbMAxisTdata => rbLMAxisTdata,
rbMAxisTkeep => rbLMAxisTkeep,
rbMAxisTvalid => rbLMAxisTvalid,
rbMAxisTready => rbLLPAxisTready,
rbMAxisTlast => rbLMAxisTlast,
rbErrSkew => rbLMErrSkew,
rbErrOvf => rbLMErrOvf,
rbEn => rbEn,
rbRst => not rbRst_n,
dbgLMLane => dbgLMLane,
dbgLM => dbgLM
);
-- Link-level protocol decodes short and long packets into frames, lines
-- and pixels. It synchronizes data from the MIPI clock domain (RxByteClkHS)
-- to the video pipeline domain video_aclk. It does error detection
-- and correction, filters data according to the target data type and
-- formats it according to UG934, ready to source a video processing
-- pipeline.
LLP_inst: LLP
Generic map (
kMaxLaneCount => kMaxLaneCount,
--PPI
kLaneCount => kLaneCount, --[1,2,4]
kTargetDT => kTargetDT
)
Port map (
SAxisClk => RxByteClkHS,
--Slave AXI-Stream
sAxisTdata => rbLMAxisTdata,
sAxisTkeep => rbLMAxisTkeep,
sAxisTvalid => rbLMAxisTvalid,
sAxisTready => rbLLPAxisTready,
sAxisTlast => rbLMAxisTlast,
MAxisClk => video_aclk,
--Master AXI-Stream
mAxisTdata => m_axis_video_tdata,
mAxisTvalid => m_axis_video_tvalid,
mAxisTready => m_axis_video_tready,
mAxisTlast => m_axis_video_tlast,
mAxisTuser => m_axis_video_tuser,
aRst => vRst,
sOverflow => open,
dbgLLP => dbgLLP
);
----------------------------------------------------------------------------------
-- Debug modules
----------------------------------------------------------------------------------
GenerateDebug: if kDebug generate
ILARxClk : ila_rxclk
PORT MAP (
clk => RxByteClkHS,
trig_out => rbRxClkTrigOut,
trig_out_ack => rbTrigInAck,
probe0 => dbgLM.state,
probe1 => dbgLM.rbByteCnt,
probe2 => rbLMAxisTdata,
probe3 => rbLMAxisTkeep,
probe4(0) => rbLMAxisTvalid,
probe5(0) => rbLLPAxisTready,
probe6(0) => rbLMAxisTlast,
probe7(0) => rbLMErrSkew,
probe8(0) => rbLMErrOvf,
probe9(0) => dbgLLP.rbRst,
probe10(0) => dbgLLP.rbOvf,
probe11(0) => dbgLLP.rbFIFO_Rstn,
probe12(0) => rbRst_n,
probe13(0) => rbEn
);
ILAVidClk : ila_vidclk
PORT MAP (
clk => video_aclk,
trig_in => vTrigIn,
trig_in_ack => vTrigInAck,
probe0(0) => dbgLLP.mRst,
probe1(0) => dbgLLP.mFIFO_Tvalid,
probe2(0) => dbgLLP.mFIFO_Tready,
probe3(0) => dbgLLP.mFIFO_Tlast,
probe4 => dbgLLP.mFIFO_Tdata,
probe5 => dbgLLP.mFIFO_Tkeep,
probe6(0) => dbgLLP.mIsHeader,
probe7(0) => dbgLLP.mECC_En,
probe8(0) => dbgLLP.mECC_Ready,
probe9(0) => dbgLLP.mECC_Valid,
probe10(0) => dbgLLP.mECC_Error,
probe11 => dbgLLP.mWC,
probe12 => dbgLLP.mDT,
probe13(0) => dbgLLP.mFlush,
probe14(0) => dbgLLP.mKeep,
probe15 => dbgLLP.mWordCount,
probe16(0) => dbgLLP.mReg_Tvalid,
probe17(0) => dbgLLP.mReg_Tready,
probe18(0) => dbgLLP.mReg_Tlast,
probe19(0) => dbgLLP.mReg_Tuser,
probe20 => dbgLLP.mReg_Tdata,
probe21 => dbgLLP.mReg_Tkeep,
probe22 => dbgLLP.mCRC_Sent,
probe23(0) => dbgLLP.mCRC_En,
probe24(0) => dbgLLP.mCRC_Rst,
probe25 => dbgLLP.mCRC_Out,
probe26(0) => dbgLLP.mFmt_Tvalid,
probe27(0) => dbgLLP.mFmt_Tready,
probe28(0) => dbgLLP.mFmt_Tlast,
probe29(0) => dbgLLP.mFmt_Tuser,
probe30 => dbgLLP.mFmt_Tdata,
probe31 => dbgLLP.mFmt_cnt,
probe32 => dbgLLP.mBufDataCnt,
probe33(0) => aClkEnableInt,
probe34 => aDEnableInt,
probe35(0) => vTready
);
SyncAsyncTrigOut: entity work.SyncAsync
port map (
aReset => '0',
aIn => rbRxClkTrigOut,
OutClk => video_aclk,
oOut => vRxClkTrigOut);
SyncAsyncTrigAck: entity work.SyncAsync
port map (
aReset => '0',
aIn => vTrigInAck,
OutClk => RxByteClkHS,
oOut => rbTrigInAck);
ILA_LaneGen: for i in kLaneCount-1 downto 0 generate
ILARxClk_Lane : ila_rxclk_lane
PORT MAP (
clk => RxByteClkHS,
trig_out => rbRxClkLaneTrigOut(i),
trig_out_ack => rbTrigInAck,
probe0(0) => dbgLMLane(i).rbSkwRdEn,
probe1(0) => dbgLMLane(i).rbSkwWrEn,
probe2(0) => dbgLMLane(i).rbSkwFull,
probe3(0) => dbgLMLane(i).rbActiveHS,
probe4(0) => dbgLMLane(i).rbSyncHS,
probe5(0) => dbgLMLane(i).rbValidHS,
probe6 => dbgLMLane(i).rbDataHS
);
SyncAsyncTrigOut: entity work.SyncAsync
port map (
aReset => '0',
aIn => rbRxClkLaneTrigOut(i),
OutClk => video_aclk,
oOut => vRxClkLaneTrigOut(i));
end generate ILA_LaneGen;
vTrigIn <= orv(vRxClkLaneTrigOut) or vRxClkTrigOut;
end generate;
end Behavioral;
|
mit
|
5f3b1584fe34c9f815d28ab63cf53f97
| 0.614219 | 3.899973 | false | false | false | false |
pollow/Multi_Cycle_CPU
|
ipcore_dir/Mem_B/simulation/Mem_B_tb.vhd
| 1 | 4,438 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: Mem_B_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY Mem_B_tb IS
END ENTITY;
ARCHITECTURE Mem_B_tb_ARCH OF Mem_B_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
Mem_B_synth_inst:ENTITY work.Mem_B_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
gpl-3.0
|
e05b0fc1dcb5a29537e8df7dd0f15660
| 0.598918 | 4.420319 | false | false | false | false |
grafi-tt/Maizul
|
fpu-misc/original/finv.vhd
| 1 | 1,506 |
-- written by panooz
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity finv is
port (
clk : in std_logic;
flt_in : in std_logic_vector(31 downto 0);
flt_out : out std_logic_vector(31 downto 0));
end finv;
architecture blackbox of finv is
component finvTable is
port (
clk : in std_logic;
addr : in std_logic_vector(9 downto 0);
output : out std_logic_vector(35 downto 0));
end component;
signal sign: std_logic;
signal exp_out,exp_in : std_logic_vector(7 downto 0);
signal frac_out : std_logic_vector(22 downto 0);
signal key : std_logic_vector(9 downto 0);
signal rest : std_logic_vector(12 downto 0);
signal tvalue : std_logic_vector(35 downto 0);
signal const : std_logic_vector(22 downto 0);
signal grad : std_logic_vector(12 downto 0);
signal temp : std_logic_vector(25 downto 0);
begin
table : finvTable port map(clk, key, tvalue);
sign <= flt_in(31);
exp_in <= flt_in(30 downto 23);
key <= flt_in(22 downto 13);
rest <= flt_in(12 downto 0);
const <= tvalue(35 downto 13);
grad <= tvalue(12 downto 0);
temp <= grad * rest;
frac_out <= (others=>'0') when key = 0 and rest = 0
else const - ("000000000"&temp(25 downto 12));
exp_out <= (others=>'1') when exp_in = 255 or exp_in = 0
else (others=>'0') when exp_in = 254
else 254 - exp_in when key = 0 and rest = 0
else 253 - exp_in;
flt_out <= sign & exp_out & frac_out;
end blackbox;
|
bsd-2-clause
|
892c5fbf6362368903f63495a9d0f182
| 0.646082 | 3.163866 | false | false | false | false |
Digilent/vivado-library
|
ip/AXI_DPTI_1.0/src/AXI_DPTI_v1_0.vhd
| 1 | 28,662 |
------------------------------------------------------------------------------
--
-- File: axi_dpti_v1_0.vhd
-- Author: Sergiu Arpadi
-- Original Project: AXI DPTI
-- Date: 8 June 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
--This is the top module for the AXI DPTI project. It defines the top level ports
--for the DPTI interface, AXI Lite interface and the AXI Stream interface. The module
--is also used to declare the FIFOs (RX and TX) and the DPTI to STREAM and STREAM to
--DPTI converters as well as the module responsible for the AXI Lite interface.
--Another function for the module is the clock domain crossings for the LENGTH,
--CONTROL and STATUS AXI Lite registers, using the HandshakeData and SyncAsync
--modules. A PLL is also instantiated here which is used to compensate for the
--prog_clko BUFG delay.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity axi_dpti_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface AXI_LITE
C_AXI_LITE_DATA_WIDTH : integer := 32;
C_AXI_LITE_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
--DPTI INTERFACE
prog_clko : in STD_LOGIC;
prog_rxen : in STD_LOGIC;
prog_txen : in STD_LOGIC;
prog_spien : in STD_LOGIC;
prog_rdn : out STD_LOGIC;
prog_wrn : out STD_LOGIC;
prog_oen : out STD_LOGIC;
prog_siwun : out STD_LOGIC;
prog_d : inout STD_LOGIC_VECTOR (7 downto 0);
--AXI STREAM INTERFACE
m_axis_aclk : in std_logic;
m_axis_aresetn : in std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(31 downto 0);
m_axis_tkeep : out std_logic_vector(3 downto 0);
m_axis_tlast : out std_logic;
m_axis_tvalid : out std_logic;
s_axis_aclk : in std_logic;
s_axis_aresetn : in std_logic;
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector(31 downto 0);
s_axis_tkeep : in std_logic_vector(3 downto 0);
s_axis_tlast : in std_logic;
s_axis_tvalid : in std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface AXI_LITE
axi_lite_aclk : in std_logic;
axi_lite_aresetn : in std_logic;
axi_lite_awaddr : in std_logic_vector(C_AXI_LITE_ADDR_WIDTH-1 downto 0);
axi_lite_awprot : in std_logic_vector(2 downto 0);
axi_lite_awvalid : in std_logic;
axi_lite_awready : out std_logic;
axi_lite_wdata : in std_logic_vector(C_AXI_LITE_DATA_WIDTH-1 downto 0);
axi_lite_wstrb : in std_logic_vector((C_AXI_LITE_DATA_WIDTH/8)-1 downto 0);
axi_lite_wvalid : in std_logic;
axi_lite_wready : out std_logic;
axi_lite_bresp : out std_logic_vector(1 downto 0);
axi_lite_bvalid : out std_logic;
axi_lite_bready : in std_logic;
axi_lite_araddr : in std_logic_vector(C_AXI_LITE_ADDR_WIDTH-1 downto 0);
axi_lite_arprot : in std_logic_vector(2 downto 0);
axi_lite_arvalid : in std_logic;
axi_lite_arready : out std_logic;
axi_lite_rdata : out std_logic_vector(C_AXI_LITE_DATA_WIDTH-1 downto 0);
axi_lite_rresp : out std_logic_vector(1 downto 0);
axi_lite_rvalid : out std_logic;
axi_lite_rready : in std_logic
);
end axi_dpti_v1_0;
architecture arch_imp of axi_dpti_v1_0 is
--------------------------------------------------------------------------------------------------------------------------
-- component declaration
component axi_dpti_v1_0_AXI_LITE is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
lAXI_LiteLengthReg : out std_logic_vector (31 downto 0);
lAXI_LiteControlReg : out std_logic_vector (31 downto 0);
lAXI_LiteStatusReg : out std_logic_vector (31 downto 0);
lPushLength : out std_logic;
lPushControl : out std_logic;
lRdyLength : in std_logic;
lRdyControl : in std_logic;
lAckLength : in std_logic;
lAckControl : in std_logic;
TxLengthEmpty : in std_logic;
RxLengthEmpty : in std_logic;
prog_spien : in std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component axi_dpti_v1_0_AXI_LITE;
--------------------------------------------------------------------------------------------------------------------------
component HandshakeData is
Generic (
kDataWidth : natural := 32);
Port (
InClk : in STD_LOGIC;
OutClk : in STD_LOGIC;
iData : in STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
oData : out STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
iPush : in STD_LOGIC;
iRdy : out STD_LOGIC;
oAck : in STD_LOGIC := '1';
oValid : out STD_LOGIC;
aReset : in std_logic
);
end component;
--------------------------------------------------------------------------------------------------------------------------
component fifo_generator_dpti
PORT (
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC
);
end component;
--------------------------------------------------------------------------------------------------------------------------
component AXI_S_to_DPTI_converter is
Port (
pResetnTx : in std_logic;
PROG_CLK : in std_logic;
pTxe : in std_logic;
pWr : out std_logic;
pDataOut : out std_logic_vector (7 downto 0);
pOutTready : out std_logic;
pInTdata : in std_logic_vector (31 downto 0);
pInTvalid : in std_logic;
pInTlast : in std_logic;
pInTkeep : in std_logic_vector (3 downto 0);
pAXI_L_Length : in std_logic_vector (31 downto 0);
pOvalidLength : in std_logic;
pAXI_L_Control : in std_logic_vector (31 downto 0);
pOvalidControl : in std_logic;
pTxLengthEmpty : out std_logic
);
end component;
--------------------------------------------------------------------------------------------------------------------------
component DPTI_to_AXI_S_converter is
Port (
pResetnRx : in std_logic;
PROG_CLK : in std_logic;
pRxf : in std_logic;
pRd : out std_logic;
pOe : out std_logic;
pDataIn : in std_logic_vector (7 downto 0);
pInTready : in std_logic;
pOutTdata : out std_logic_vector (31 downto 0);
pOutTvalid : out std_logic;
pOutTlast : out std_logic;
pOutTkeep : out std_logic_vector (3 downto 0);
pAXI_L_Length : in std_logic_vector (31 downto 0);
pOvalidLength : in std_logic;
pAXI_L_Control : in std_logic_vector (31 downto 0);
pOvalidControl : in std_logic;
pRxLengthEmpty : out std_logic
);
end component;
--------------------------------------------------------------------------------------------------------------------------
signal pCtlDataOut : std_logic_vector (7 downto 0);
signal pCtlDataIn : std_logic_vector (7 downto 0);
signal pCtlOe : std_logic;
signal pCtlInTready : std_logic;
signal pCtlOutTdata : std_logic_vector(31 downto 0);
signal pCtlOutTvalid : std_logic;
signal pCtlOutTlast : std_logic;
signal pCtlOutTkeep : std_logic_vector(3 downto 0);
signal pCtlOutTready : std_logic;
signal pCtlInTdata : std_logic_vector(31 downto 0);
signal pCtlInTvalid : std_logic;
signal pCtlInTlast : std_logic;
signal pCtlInTkeep : std_logic_vector(3 downto 0);
signal lCtlAXI_LiteLengthReg : std_logic_vector(31 downto 0);
signal lCtlAXI_LiteControlReg : std_logic_vector(31 downto 0);
signal lCtlAXI_LiteStatusReg : std_logic_vector(31 downto 0);
signal lCtlPushLength : std_logic;
signal lCtlPushControl : std_logic;
---------------------------------------------------
--SYNC_ASYNC---------------------------------------
---------------------------------------------------
signal pControlRegSyncd : std_logic_vector (31 downto 0);
signal pLengthRegSyncd : std_logic_vector (31 downto 0);
--signal pStatusReg : std_logic_vector (31 downto 0);
signal lCtlRdyLength : std_logic;
signal pCtlAckLength : std_logic := '0';
signal lCtlAckLength : std_logic;
signal pCtlValidLength : std_logic;
signal aCtlResetLength : std_logic :='1';
signal lCtlRdyControl : std_logic;
signal pCtlAckControl : std_logic := '0';
signal lCtlAckControl : std_logic;
signal pCtlValidControl : std_logic;
signal aCtlResetControl : std_logic :='1';
signal iPushStatus : std_logic := '0';
signal iRdyStatus : std_logic;
signal oValidStatus : std_logic;
signal aResetStatus : std_logic :='1';
signal pCtlRxLengthEmpty : std_logic :='1';
signal pCtlTxLengthEmpty : std_logic :='1';
signal lCtlRxLengthEmpty : std_logic :='1';
signal lCtlTxLengthEmpty : std_logic :='1';
--------------------------------------------------------------------------------------------------------------------------
signal spien_syncReg : std_logic;
signal aCtlResetnRx : std_logic;
signal aCtlResetnTx : std_logic;
signal pAXI_LiteReset : std_logic := '0';
signal pM_AXIS_Reset : std_logic := '0';
signal pS_AXIS_Reset : std_logic := '0';
--------------------------------------------------------------------------------------------------------------------------
-- PLL and BUFG signals
--------------------------------------------------------------------------------------------------------------------------
signal PLL_Fb_OutClk : std_logic;
signal PLL_Fb_InClk : std_logic;
signal PROG_CLK : std_logic;
signal aPLL_Reset : std_logic;
signal aPLL_Pwrdwn : std_logic := '0';
signal pPLL_Locked : std_logic := '0';
--------------------------------------------------------------------------------------------------------------------------
signal aSoft_Reset:std_logic;
signal pSoft_Reset:std_logic;
signal prog_rdn_0 :std_logic;
signal prog_wrn_0 : std_logic;
signal prog_oen_0 : std_logic;
signal pCtlOeN :std_logic;
signal clearFlag:std_logic;
begin
pCtlOeN <= not pCtlOe;
aSoft_Reset <= lCtlAXI_LiteControlReg(2);
prog_rdn <= prog_rdn_0;
prog_wrn <= prog_wrn_0;
prog_oen <= prog_oen_0;
-- prog_spien is used as a sync reset signal by the PC.
-- spien_syncReg logic. Latch falling edge of prog_spien, prog_clk will stop. Wait until PROG_CLK is enabled again to disable reset
process (prog_clko, prog_spien)begin
if(prog_spien='1')then
spien_syncreg<=prog_spien;
else if rising_edge(prog_clko)then
spien_syncReg<=prog_spien;
end if;
end if;
end process;
-- reset signals
aCtlResetnTx <= pPLL_Locked and pAXI_LiteReset and pS_AXIS_Reset and not pSoft_Reset and not spien_syncReg; --pPLL_Locked and
aCtlResetnRx <= pPLL_Locked and pAXI_LiteReset and pM_AXIS_Reset and not pSoft_Reset and not spien_syncReg; --pPLL_Locked and
aPLL_Reset <= '0';--prog_spien;
-- status register
--pStatusReg (0) <= pCtlTxLengthEmpty;
--pStatusReg (16) <= pCtlRxLengthEmpty;
--pStatusReg (15 downto 1) <= (others => '0');
--pStatusReg (31 downto 17) <= (others => '0');
-- IOBUF is implemented
DataIOBUFs: for i in 0 to 7 generate
IOBUF_inst : IOBUF
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => pCtlDataIn(i), -- Buffer output
IO => prog_d(i), -- Buffer inout port (connect directly to top-level port)
I => pCtlDataOut(i), -- Buffer input
T => pCtlOeN -- 3-state enable input, high=input, low=output
);
end generate DataIOBUFs;
--prog_d <= pCtlDataOut when pCtlOe = '1' else "ZZZZZZZZ";
--pCtlDataIn <= prog_d;
-- SIWU signal is not used
prog_siwun <= '1';
prog_oen_0 <= pCtlOe;
aCtlResetLength <= not pPLL_Locked;
aCtlResetControl <= not pPLL_Locked;
PROG_CLK <= Pll_Fb_InClk;
--------------------------------------------------------------------------------------------------------------------------
-- Instantiations
--------------------------------------------------------------------------------------------------------------------------
BUFG_inst : BUFG -- used for PLL feedback clock
port map (
O => Pll_Fb_InClk, -- 1-bit output: Clock output
I => Pll_Fb_OutClk -- 1-bit input: Clock input
);
--BUFIO_Inst : BUFR
-- generic map (
-- BUFR_DIVIDE => "BYPASS", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
-- SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
-- )
-- port map (
-- O => PROG_CLK,
-- I => prog_clko,
-- CE => '0', -- Unused in BYPASS mode
-- CLR => '0' -- Unused in BYPASS mode
-- );
--------------------------------------------------------------------------------------------------------------------------
PLLE2_BASE_inst : PLLE2_BASE -- PLL used to correct BUFG delay for prog_clko
generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => 15, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
CLKIN1_PERIOD => 16.67, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
CLKOUT0_DIVIDE => 15,
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
DIVCLK_DIVIDE => 1, -- Master division value, (1-56)
REF_JITTER1 => 0.0, -- Reference input jitter in UI, (0.000-0.999).
STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
-- CLKOUT0 => PROG_CLK, -- 1-bit output: CLKOUT0
-- CLKOUT1 => CLKOUT1, -- 1-bit output: CLKOUT1
-- CLKOUT2 => CLKOUT2, -- 1-bit output: CLKOUT2
-- CLKOUT3 => CLKOUT3, -- 1-bit output: CLKOUT3
-- CLKOUT4 => CLKOUT4, -- 1-bit output: CLKOUT4
-- CLKOUT5 => CLKOUT5, -- 1-bit output: CLKOUT5
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => Pll_Fb_OutClk, -- 1-bit output: Feedback clock
LOCKED => pPLL_Locked, -- 1-bit output: LOCK
CLKIN1 => prog_clko, -- 1-bit input: Input clock
-- Control Ports: 1-bit (each) input: PLL control ports
PWRDWN => aPLL_Pwrdwn, -- 1-bit input: Power-down
RST => aPLL_Reset, -- 1-bit input: Reset
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => Pll_Fb_InClk -- 1-bit input: Feedback clock
);
--------------------------------------------------------------------------------------------------------------------------
-- Instantiation of Axi Bus Interface AXI_LITE
axi_dpti_v1_0_AXI_LITE_inst : axi_dpti_v1_0_AXI_LITE
generic map (
C_S_AXI_DATA_WIDTH => C_AXI_LITE_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_AXI_LITE_ADDR_WIDTH
)
port map (
lAXI_LiteLengthReg => lCtlAXI_LiteLengthReg,
lAXI_LiteControlReg => lCtlAXI_LiteControlReg,
lAXI_LiteStatusReg => lCtlAXI_LiteStatusReg,
lPushLength => lCtlPushLength,
lPushControl => lCtlPushControl,
lRdyLength => lCtlRdyLength,
lRdyControl => lCtlRdyControl,
lAckLength => lCtlAckLength,
lAckControl => lCtlAckControl,
TxLengthEmpty => lCtlTxLengthEmpty,
RxLengthEmpty => lCtlRxLengthEmpty,
prog_spien => prog_spien,
S_AXI_ACLK => axi_lite_aclk,
S_AXI_ARESETN => axi_lite_aresetn,
S_AXI_AWADDR => axi_lite_awaddr,
S_AXI_AWPROT => axi_lite_awprot,
S_AXI_AWVALID => axi_lite_awvalid,
S_AXI_AWREADY => axi_lite_awready,
S_AXI_WDATA => axi_lite_wdata,
S_AXI_WSTRB => axi_lite_wstrb,
S_AXI_WVALID => axi_lite_wvalid,
S_AXI_WREADY => axi_lite_wready,
S_AXI_BRESP => axi_lite_bresp,
S_AXI_BVALID => axi_lite_bvalid,
S_AXI_BREADY => axi_lite_bready,
S_AXI_ARADDR => axi_lite_araddr,
S_AXI_ARPROT => axi_lite_arprot,
S_AXI_ARVALID => axi_lite_arvalid,
S_AXI_ARREADY => axi_lite_arready,
S_AXI_RDATA => axi_lite_rdata,
S_AXI_RRESP => axi_lite_rresp,
S_AXI_RVALID => axi_lite_rvalid,
S_AXI_RREADY => axi_lite_rready
);
-- Add user logic here
--------------------------------------------------------------------------------------------------------------------------
in_length_sync : HandshakeData -- synchronization module for AXI LITE LENGTH register crossing to PROG_CLK clock domain
Port map (
InClk => axi_lite_aclk,
OutClk => PROG_CLK,
iData => lCtlAXI_LiteLengthReg,
oData => pLengthRegSyncd, -- synchronized output
iPush => lCtlPushLength,
iRdy => lCtlRdyLength,
oAck => pCtlAckLength,
oValid => pCtlValidLength, -- indicates valid synchronized data
aReset => aCtlResetLength
);
--------------------------------------------------------------------------------------------------------------------------
in_control_sync : HandshakeData -- synchronization module for AXI LITE CONTROL register crossing to PROG_CLK clock domain
Port map (
InClk => axi_lite_aclk,
OutClk => PROG_CLK,
iData => lCtlAXI_LiteControlReg,
oData => pControlRegSyncd, -- synchronized output
iPush => lCtlPushControl,
iRdy => lCtlRdyControl,
oAck => pCtlAckControl,
oValid => pCtlValidControl, -- indicates valid synchronized data
aReset => aCtlResetControl
);
--------------------------------------------------------------------------------------------------------------------------
SyncAsync_oAckLength: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aReset => '0',
aIn => pCtlAckLength,
OutClk => axi_lite_aclk,
oOut => lCtlAckLength);
--------------------------------------------------------------------------------------------------------------------------
SyncAsync_oAckControl: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aReset => '0',
aIn => pCtlAckControl,
OutClk => axi_lite_aclk,
oOut => lCtlAckControl);
--------------------------------------------------------------------------------------------------------------------------
--GenSyncStatusReg: for i in 0 to 31 generate -- STATUS register sync module (from PROG_CLK domain to AXI_L_CLK domain)
--SyncAsyncMultiple: entity work.SyncAsync
-- generic map (
-- kResetTo => '0',
-- kStages => 2) --use double FF synchronizer
-- port map (
-- aReset => '0',
-- aIn => pStatusReg(i),
-- OutClk => axi_lite_aclk,
-- oOut => lCtlAXI_LiteStatusReg(i)
-- );
--end generate GenSyncStatusReg;
SyncAsyncTxLenEmpty: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => '0',
aIn => pCtlTxLengthEmpty,
OutClk => axi_lite_aclk,
oOut => lCtlTxLengthEmpty
);
SyncAsyncRxLenEmpty: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => '0',
aIn => pCtlRxLengthEmpty,
OutClk => axi_lite_aclk,
oOut => lCtlRxLengthEmpty
);
------------------------------------------------------------------------------------------------
SyncReset_AXI_LITE: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => axi_lite_aresetn,
OutClk => PROG_CLK,
oRst => pAXI_LiteReset);
SyncReset_M_AXIS: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => m_axis_aresetn,
OutClk => PROG_CLK,
oRst => pM_AXIS_Reset);
SyncReset_S_AXIS: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => s_axis_aresetn,
OutClk => PROG_CLK,
oRst => pS_AXIS_Reset);
SyncReset_SoftReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aSoft_Reset,
OutClk => PROG_CLK,
oRst => pSoft_Reset);
------------------------------------------------------------------------------------------------
RX_fifo : fifo_generator_dpti PORT MAP ( -- AXI STREAM FIFO : used only for clock domain crossing. low capacity
m_aclk => m_axis_aclk,
s_aclk => PROG_CLK,
s_aresetn => aCtlResetnRx,
s_axis_tvalid => pCtlOutTvalid,
s_axis_tready => pCtlInTready,
s_axis_tdata => pCtlOutTdata,
s_axis_tkeep => pCtlOutTkeep,
s_axis_tlast => pCtlOutTlast,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
m_axis_tkeep => m_axis_tkeep,
m_axis_tlast => m_axis_tlast
);
----------------------------------------------------------------------------------------------------------
TX_fifo : fifo_generator_dpti PORT MAP ( -- AXI STREAM FIFO : used only for clock domain crossing. low capacity
m_aclk => PROG_CLK,
s_aclk => s_axis_aclk,
s_aresetn => aCtlResetnTx,
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tkeep => s_axis_tkeep,
s_axis_tlast => s_axis_tlast,
m_axis_tvalid => pCtlInTvalid,
m_axis_tready => pCtlOutTready,
m_axis_tdata => pCtlInTdata,
m_axis_tkeep => pCtlInTkeep,
m_axis_tlast => pCtlInTlast
);
----------------------------------------------------------------------------------------------------------
AXI_S_to_DPTI_inst : AXI_S_to_DPTI_converter PORT MAP ( -- converts 32bit AXI STREAM from TX_FIFO data to 8bit data which is then sent to the DPTI interface
pResetnTx => aCtlResetnTx,
PROG_CLK => PROG_CLK,
pTxe => prog_txen,
pWr => prog_wrn_0,
pDataOut => pCtlDataOut,
pOutTready => pCtlOutTready,
pInTdata => pCtlInTdata,
pInTvalid => pCtlInTvalid,
pInTlast => pCtlInTlast,
pInTkeep => pCtlInTkeep,
pAXI_L_Length => pLengthRegSyncd,
pOvalidLength => pCtlValidLength,
pAXI_L_Control => pControlRegSyncd,
pOvalidControl => pCtlValidControl,
pTxLengthEmpty => pCtlTxLengthEmpty
);
----------------------------------------------------------------------------------------------------------
DPTI_to_AXI_S_inst : DPTI_to_AXI_S_converter PORT MAP ( -- converts 8bit data received from the DPTI interface to 32bit AXI STREAM data sent to RX_FIFO
pResetnRx => aCtlResetnRx,
PROG_CLK => PROG_CLK,
pRxf => prog_rxen,
pRd => prog_rdn_0,
pOe => pCtlOe,
pDataIn => pCtlDataIn,
pInTready => pCtlInTready,
pOutTdata => pCtlOutTdata,
pOutTvalid => pCtlOutTvalid,
pOutTlast => pCtlOutTlast,
pOutTkeep => pCtlOutTkeep,
pAXI_L_Length => pLengthRegSyncd,
pOvalidLength => pCtlValidLength,
pAXI_L_Control => pControlRegSyncd,
pOvalidControl => pCtlValidControl,
pRxLengthEmpty => pCtlRxLengthEmpty
);
----------------------------------------------------------------------------------------------------------
-- processes
----------------------------------------------------------------------------------------------------------
Length_oACK: process (PROG_CLK, pCtlValidLength) is -- generates auxiliary signals for LENGTH register HandshakeData module
variable count : integer range 0 to 2;
begin
if rising_edge (PROG_CLK) then
if pCtlValidLength = '0' then
count := 2;
pCtlAckLength <= '0';
elsif count = 2 then
pCtlAckLength <= '1';
count := count - 1;
elsif count = 1 then
pCtlAckLength <= '0';
count := 0;
else
pCtlAckLength <= '0';
count := count - 1;
end if;
end if;
end process;
----------------------------------------------------------------------------------------------------------
Control_oACK: process (PROG_CLK, pCtlValidControl) is -- generates auxiliary signals for CONTROL register HandshakeData module
variable count : integer range 0 to 2;
begin
if rising_edge (PROG_CLK) then
if pCtlValidControl = '0' then
count := 2;
pCtlAckControl <= '0';
elsif count = 2 then
pCtlAckControl <= '1';
count := count - 1;
elsif count = 1 then
pCtlAckControl <= '0';
count := 0;
else
pCtlAckControl <= '0';
count := count - 1;
end if;
end if;
end process;
----------------------------------------------------------------------------------------------------------
-- User logic ends
end arch_imp;
|
mit
|
b1dba93c10d38b95b4ba05d783ed74f7
| 0.556137 | 3.988589 | false | false | false | false |
olajep/oh
|
src/adi/hdl/library/axi_spdif_tx/axi_spdif_tx.vhd
| 1 | 10,041 |
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
--
-- In this HDL repository, there are many different and unique modules, consisting
-- of various HDL (Verilog or VHDL) components. The individual modules are
-- developed independently, and may be accompanied by separate and unique license
-- terms.
--
-- The user should read each of these license terms, and understand the
-- freedoms and responsibilities that he or she has by using this source/core.
--
-- This core is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-- A PARTICULAR PURPOSE.
--
-- Redistribution and use of source or resulting binaries, with or without modification
-- of this file, are permitted under one of the following two license terms:
--
-- 1. The GNU General Public License version 2 as published by the
-- Free Software Foundation, which can be found in the top level directory
-- of this repository (LICENSE_GPL2), and also online at:
-- <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
--
-- OR
--
-- 2. An ADI specific BSD license, which can be found in the top level directory
-- of this repository (LICENSE_ADIBSD), and also on-line at:
-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
-- This will allow to generate bit files and not release the source code,
-- as long as it attaches to an ADI device.
--
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.tx_package.all;
use work.axi_ctrlif;
use work.axi_streaming_dma_tx_fifo;
use work.pl330_dma_fifo;
entity axi_spdif_tx is
generic (
S_AXI_DATA_WIDTH : integer := 32;
S_AXI_ADDRESS_WIDTH : integer := 32;
DEVICE_FAMILY : string := "virtex6";
DMA_TYPE : integer := 0
);
port (
--SPDIF ports
spdif_data_clk : in std_logic;
spdif_tx_o : out std_logic;
--AXI Lite interface
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
s_axi_awprot : in std_logic_vector(2 downto 0);
s_axi_awvalid : in std_logic;
s_axi_wdata : in std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector((S_AXI_DATA_WIDTH/8)-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
s_axi_arprot : in std_logic_vector(2 downto 0);
s_axi_arvalid : in std_logic;
s_axi_rready : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_awready : out std_logic;
--axi streaming interface
s_axis_aclk : in std_logic;
s_axis_aresetn : in std_logic;
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector(31 downto 0);
s_axis_tlast : in std_logic;
s_axis_tvalid : in std_logic;
--PL330 DMA interface
dma_req_aclk : in std_logic;
dma_req_rstn : in std_logic;
dma_req_davalid : in std_logic;
dma_req_datype : in std_logic_vector(1 downto 0);
dma_req_daready : out std_logic;
dma_req_drvalid : out std_logic;
dma_req_drtype : out std_logic_vector(1 downto 0);
dma_req_drlast : out std_logic;
dma_req_drready : in std_logic
);
end entity axi_spdif_tx;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of axi_spdif_tx is
------------------------------------------
-- SPDIF signals
------------------------------------------
signal config_reg : std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
signal chstatus_reg : std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
signal chstat_freq : std_logic_vector(1 downto 0);
signal chstat_gstat, chstat_preem, chstat_copy, chstat_audio : std_logic;
signal sample_data_ack : std_logic;
signal sample_data: std_logic_vector(15 downto 0);
signal conf_mode : std_logic_vector(3 downto 0);
signal conf_ratio : std_logic_vector(7 downto 0);
signal conf_tinten, conf_txdata, conf_txen : std_logic;
signal channel : std_logic;
signal enable : boolean;
signal fifo_data_out : std_logic_vector(31 downto 0);
signal fifo_data_ack : std_logic;
signal fifo_reset : std_logic;
signal tx_fifo_stb : std_logic;
-- Register access
signal wr_data : std_logic_vector(31 downto 0);
signal rd_data : std_logic_vector(31 downto 0);
signal wr_addr : integer range 0 to 3;
signal rd_addr : integer range 0 to 3;
signal wr_stb : std_logic;
signal rd_ack : std_logic;
begin
fifo_reset <= not conf_txdata;
enable <= conf_txdata = '1';
fifo_data_ack <= channel and sample_data_ack;
streaming_dma_gen: if DMA_TYPE = 0 generate
fifo: entity axi_streaming_dma_tx_fifo
generic map (
RAM_ADDR_WIDTH => 3,
FIFO_DWIDTH => 32
)
port map (
clk => s_axi_aclk,
resetn => s_axi_aresetn,
fifo_reset => fifo_reset,
enable => enable,
s_axis_aclk => s_axis_aclk,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tvalid => s_axis_tlast,
s_axis_tlast => s_axis_tvalid,
out_ack => fifo_data_ack,
out_data => fifo_data_out
);
end generate;
no_streaming_dma_gen: if DMA_TYPE /= 0 generate
s_axis_tready <= '0';
end generate;
pl330_dma_gen: if DMA_TYPE = 1 generate
tx_fifo_stb <= '1' when wr_addr = 3 and wr_stb = '1' else '0';
fifo: entity pl330_dma_fifo
generic map(
RAM_ADDR_WIDTH => 3,
FIFO_DWIDTH => 32,
FIFO_DIRECTION => 0
)
port map (
clk => s_axi_aclk,
resetn => s_axi_aresetn,
fifo_reset => fifo_reset,
enable => enable,
in_data => wr_data,
in_stb => tx_fifo_stb,
out_ack => fifo_data_ack,
out_data => fifo_data_out,
dclk => dma_req_aclk,
dresetn => dma_req_rstn,
davalid => dma_req_davalid,
daready => dma_req_daready,
datype => dma_req_datype,
drvalid => dma_req_drvalid,
drready => dma_req_drreadY,
drtype => dma_req_drtype,
drlast => dma_req_drlast
);
end generate;
no_pl330_dma_gen: if DMA_TYPE /= 1 generate
dma_req_daready <= '0';
dma_req_drvalid <= '0';
dma_req_drtype <= (others => '0');
dma_req_drlast <= '0';
end generate;
sample_data_mux: process (fifo_data_out, channel) is
begin
if channel = '0' then
sample_data <= fifo_data_out(15 downto 0);
else
sample_data <= fifo_data_out(31 downto 16);
end if;
end process;
-- Configuration signals update
conf_mode(3 downto 0) <= config_reg(23 downto 20);
conf_ratio(7 downto 0) <= config_reg(15 downto 8);
conf_tinten <= config_reg(2);
conf_txdata <= config_reg(1);
conf_txen <= config_reg(0);
-- Channel status signals update
chstat_freq(1 downto 0) <= chstatus_reg(7 downto 6);
chstat_gstat <= chstatus_reg(3);
chstat_preem <= chstatus_reg(2);
chstat_copy <= chstatus_reg(1);
chstat_audio <= chstatus_reg(0);
-- Transmit encoder
TENC: tx_encoder
generic map (
DATA_WIDTH => 16
)
port map (
up_clk => s_axi_aclk,
data_clk => spdif_data_clk, -- data clock
resetn => s_axi_aresetn, -- resetn
conf_mode => conf_mode, -- sample format
conf_ratio => conf_ratio, -- clock divider
conf_txdata => conf_txdata, -- sample data enable
conf_txen => conf_txen, -- spdif signal enable
chstat_freq => chstat_freq, -- sample freq.
chstat_gstat => chstat_gstat, -- generation status
chstat_preem => chstat_preem, -- preemphasis status
chstat_copy => chstat_copy, -- copyright bit
chstat_audio => chstat_audio, -- data format
sample_data => sample_data, -- audio data
sample_data_ack => sample_data_ack, -- sample buffer read
channel => channel, -- which channel should be read
spdif_tx_o => spdif_tx_o -- SPDIF output signal
);
ctrlif: entity axi_ctrlif
generic map (
C_S_AXI_ADDR_WIDTH => S_AXI_ADDRESS_WIDTH,
C_S_AXI_DATA_WIDTH => S_AXI_DATA_WIDTH,
C_NUM_REG => 4
)
port map(
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_rready => s_axi_rready,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_awready => s_axi_awready,
rd_addr => rd_addr,
rd_data => rd_data,
rd_ack => rd_ack,
rd_stb => '1',
wr_addr => wr_addr,
wr_data => wr_data,
wr_ack => '1',
wr_stb => wr_stb
);
process (s_axi_aclk)
begin
if rising_edge(s_axi_aclk) then
if s_axi_aresetn = '0' then
config_reg <= (others => '0');
chstatus_reg <= (others => '0');
else
if wr_stb = '1' then
case wr_addr is
when 0 => config_reg <= wr_data;
when 1 => chstatus_reg <= wr_data;
when others => null;
end case;
end if;
end if;
end if;
end process;
process (rd_addr, config_reg, chstatus_reg)
begin
case rd_addr is
when 0 => rd_data <= config_reg;
when 1 => rd_data <= chstatus_reg;
when others => rd_data <= (others => '0');
end case;
end process;
end IMP;
|
mit
|
b4e7d28b14a68334ec5b325f05d59cb5
| 0.609003 | 2.901185 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodDigitizerController/src/TWI_Ctl.vhd
| 1 | 23,948 |
----------------------------------------------------------------------------------
-- Company: Digilent Ro
-- Engineer: Elod Gyorgy
--
-- Create Date: 14:55:31 04/07/2011
-- Design Name:
-- Module Name: TWI_Ctl - Behavioral
-- Project Name: TWI Master Controller Reference Design
-- Target Devices:
-- Tool versions:
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- Description: TWI_Ctl is a reusabled Master Controller implementation of the
-- TWI protocol. It uses 7-bit addressing and was tested in STANDARD I2C mode.
-- FAST mode should also be theoretically possible, although it has not been
-- tested. It adheres to arbitration rules, thus supporting multi-master TWI
-- buses. Slave-wait is also supported.
--
--
-- Dependencies: digilent.PkgTWI_Utils package - TWI_Ctl.vhd
--
-- Revision:
-- Revision 1.01 - Bugfix: stop condition might be prevented device read
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.math_real.all;
library digilent;
use work.PkgTWI_Utils.ALL;
entity TWI_Ctl is
----------------------------------------------------------------------------------
-- Title : Mode of operation
-- Description: The controller can be instructed to initiate/continue/stop a
-- data transfer using the strobe (STB_I, MSG_I) signals. Data flow management is
-- provided by the done (DONE_O) and error (ERR_O, ERRTYPE_O) signals. Output
-- signals are synchronous to CLK and input signals must also be synchronous to
-- CLK. Signals are active-high.
-- Fast-track instructions (single byte transfer):
-- -put the TWI address on A_I
-- -if data is written put it on D_I
-- -assert STB_I
-- -when DONE_O pulse arrives, read data is present on D_O, if any
-- -repeat, or deassert STB_I
-- Detailed data transfer flow:
-- -when DONE_O is low, the controller is ready to accept commands
-- -data transfer can be initiated by putting a TWI slave address on the A_I
-- bus and providing a strobe (STB_I)
-- -the direction of data transfer (read/write) is determined by the LSB of the
-- address (0-write, 1-read)
-- -in case of a 'write' the data byte should also be present on the D_I bus
-- prior to the arrival of the strobe (STB_I)
-- -once the data byte gets read/written, DONE_I pulses high for one CLK cycle
-- -in case of an error, ERR_O will pulse high together with DONE_I; ERR_O low
-- together with DONE_I high indicates success
-- -after DONE_I pulses high there is a 1/4 TWI period time frame when the next
-- strobe can be sent; this is useful, when multiple bytes are sent/received
-- in a single transfer packet; for ex. for write transfers, a new byte can
-- be put on the D_I and STB_I provided;
-- -if no new strobe is provided, the transfer will end
-- -if a new strobe is provided, but the address changed, the current transfer
-- will end and a new will begin
-- -starting a new transfer can be forced with the MSG_I pin; if asserted with
-- a strobe, the data byte will be written/read in a new packet; the advantage
-- of this is relevant only in multi-master buses: rather than waiting for the
-- current transfer to end and the bus to be released, a new transfer can be
-- initiated without giving up the control over the bus (STP_I=0)
-- -a new transfer with MSG_I and STB_I can be forced to issue a Stop condition
-- first, followed by a Start condition, instead of a Restart condition with
-- STP_I=1
--+-------+-------+-------+--------+-------+--------------------------------------------------------------------------------------------------------------+
--| MSG_I | STB_I | STP_I | DONE_O | ERR_O | Effect |
--+-------+-------+-------+--------+-------+--------------------------------------------------------------------------------------------------------------+
--| 0 | 0 | 0 | 0 | - | Finish current transfer (if any) and return to idle |
--| 0 | 1 | 0 | 0 | 0 | Send/receive next byte if in transfer, start new read from A_I to D_O or new write to A_I from D_I otherwise |
--| 1 | 1 | 0 | 0 | 0 | Finish current transfer (if any) and start a new one with Repeated Start |
--| 1 | 1 | 1 | 0 | 0 | Finish current transfer (if any) with Stop and start a new one with Start condition |
--| - | - | - | 1 | 0 | Current byte read/write finished, in the next cycle MSG_I/STB_I/STP_I will be read again |
--| - | - | - | 1 | 1 | Current byte read/write failed, in the next cycle MSG_I/STB_I/STP_I will be read again |
--+-------+-------+-------+--------+-------+--------------------------------------------------------------------------------------------------------------+
----------------------------------------------------------------------------------
generic (CLOCKFREQ : natural := 100); -- input CLK frequency in MHz
port (
MSG_I : in STD_LOGIC; --new message, has effect with STB_I=1 only
STB_I : in STD_LOGIC; --strobe
STP_I : in STD_LOGIC; --if holding bus, send stop before new message, has
--effect with STB_I=1 and MSG_I=1 only
A_I : in STD_LOGIC_VECTOR (7 downto 0); --address input bus
D_I : in STD_LOGIC_VECTOR (7 downto 0); --data input bus
D_O : out STD_LOGIC_VECTOR (7 downto 0); --data output bus
DONE_O : out STD_LOGIC; --done status signal
ERR_O : out STD_LOGIC; --error status
ERRTYPE_O : out error_type; --error type
CLK : in std_logic;
SRST : in std_logic;
----------------------------------------------------------------------------------
-- TWI bus signals
----------------------------------------------------------------------------------
-- SDA : inout std_logic; --TWI SDA
-- SCL : inout std_logic --TWI SCL
s_scl_i : in std_logic; -- IIC Serial Clock Input from 3-state buffer (required)
s_scl_o : out std_logic; -- IIC Serial Clock Output to 3-state buffer (required)
s_scl_t : out std_logic; -- IIC Serial Clock Output Enable to 3-state buffer (required)
s_sda_i : in std_logic; -- IIC Serial Data Input from 3-state buffer (required)
s_sda_o : out std_logic; -- IIC Serial Data Output to 3-state buffer (required)
s_sda_t : out std_logic -- IIC Serial Data Output Enable to 3-state buffer (required)
);
end TWI_Ctl;
architecture Behavioral of TWI_Ctl is
attribute fsm_encoding: string;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO of s_scl_i: SIGNAL is "xilinx.com:interface:iic:1.0 TWI_MasterCtrl SCL_I";
ATTRIBUTE X_INTERFACE_INFO of s_scl_o: SIGNAL is "xilinx.com:interface:iic:1.0 TWI_MasterCtrl SCL_O";
ATTRIBUTE X_INTERFACE_INFO of s_scl_t: SIGNAL is "xilinx.com:interface:iic:1.0 TWI_MasterCtrl SCL_T";
ATTRIBUTE X_INTERFACE_INFO of s_sda_i: SIGNAL is "xilinx.com:interface:iic:1.0 TWI_MasterCtrl SDA_I";
ATTRIBUTE X_INTERFACE_INFO of s_sda_o: SIGNAL is "xilinx.com:interface:iic:1.0 TWI_MasterCtrl SDA_O";
ATTRIBUTE X_INTERFACE_INFO of s_sda_t: SIGNAL is "xilinx.com:interface:iic:1.0 TWI_MasterCtrl SDA_T";
constant FSCL : natural := 100_000; --in Hz SCL clock frequency
constant TIMEOUT : natural := 10; --in ms TWI timeout for slave wait period
constant TSCL_CYCLES : natural :=
natural(ceil(real(CLOCKFREQ*1_000_000/FSCL)));
constant TIMEOUT_CYCLES : natural :=
natural(ceil(real(CLOCKFREQ*TIMEOUT*1_000)));
type state_type is (stIdle, stStart, stRead, stWrite, stError, stStop,
stSAck, stMAck, stMNAckStop, stMNAckStart, stStopError);
signal state, nstate : state_type;
attribute fsm_encoding of state: signal is "gray";
signal dSda, ddSda, dScl, ddScl : std_logic;
signal fStart, fStop : std_logic;
signal busState : busState_type := busUnknown;
signal errTypeR, errType : error_type;
signal busFreeCnt, sclCnt : natural range TSCL_CYCLES downto 0 := TSCL_CYCLES;
signal timeOutCnt : natural range TIMEOUT_CYCLES downto 0 := TIMEOUT_CYCLES;
signal slaveWait, arbLost : std_logic;
signal dataByte, loadByte, currAddr : std_logic_vector(7 downto 0); --shift register and parallel load
signal rSda, rScl : std_logic := '1';
signal subState : unsigned(1 downto 0) := "00";
signal latchData, latchAddr, iDone, iErr, iSda, iScl, shiftBit, dataBitOut, rwBit, addrNData : std_logic;
signal bitCount : natural range 0 to 7 := 7;
signal int_Rst : std_logic := '0';
attribute DONT_TOUCH : string;
attribute DONT_TOUCH of state, nstate : signal is "TRUE";
begin
----------------------------------------------------------------------------------
--Bus State detection
----------------------------------------------------------------------------------
SYNC_FFS: process(CLK)
begin
if Rising_Edge(CLK) then
dSda <= to_X01(s_sda_i);
ddSda <= to_X01(dSda);
dScl <= to_X01(s_scl_i);
end if;
end process;
fStart <= dSCL and not dSda and ddSda; --if SCL high while SDA falling, start condition
fStop <= dSCL and dSda and not ddSda; --if SCL high while SDA rising, stop condition
TWISTATE: process(CLK)
begin
if Rising_Edge(CLK) then
if (int_Rst = '1') then
busState <= busUnknown;
elsif (fStart = '1') then --If START condition detected, bus is busy
busState <= busBusy;
elsif (busFreeCnt = 0) then --We counted down tBUF, so it must be free
busState <= busFree;
end if;
end if;
end process;
TBUF_CNT: process(CLK)
begin
if Rising_Edge(CLK) then
if (dSCL = '0' or dSDA = '0' or int_Rst = '1') then
busFreeCnt <= TSCL_CYCLES;
elsif (dSCL = '1' and dSDA = '1') then
busFreeCnt <= busFreeCnt - 1; --counting down 1 SCL period on free bus
end if;
end if;
end process;
----------------------------------------------------------------------------------
--Slave devices can insert wait states by keeping SCL low
----------------------------------------------------------------------------------
slaveWait <= '1' when (dSCL = '0' and rScl = '1') else
'0';
----------------------------------------------------------------------------------
--If the SDA line does not correspond to the transmitted data while the SCL line
--is at the HIGH level the master lost an arbitration to another master.
----------------------------------------------------------------------------------
arbLost <= '1' when (dSCL = '1' and dSDA = '0' and rSda = '1') else
'0';
----------------------------------------------------------------------------------
-- Internal reset signal
----------------------------------------------------------------------------------
RST_PROC: process (CLK)
begin
if Rising_Edge(CLK) then
if (state = stIdle and SRST = '0') then
int_Rst <= '0';
elsif (SRST = '1') then
int_Rst <= '1';
end if;
end if;
end process;
----------------------------------------------------------------------------------
-- SCL period counter
----------------------------------------------------------------------------------
SCL_CNT: process (CLK)
begin
if Rising_Edge(CLK) then
if (sclCnt = 0 or state = stIdle) then
sclCnt <= TSCL_CYCLES/4;
elsif (slaveWait = '0') then -- clock synchronization with other masters
sclCnt <= sclCnt - 1;
end if;
end if;
end process;
----------------------------------------------------------------------------------
-- SCL period counter
----------------------------------------------------------------------------------
TIMEOUT_CNT: process (CLK)
begin
if Rising_Edge(CLK) then
if (timeOutCnt = 0 or slaveWait = '0') then
timeOutCnt <= TIMEOUT_CYCLES;
elsif (slaveWait = '1') then -- count timeout on wait period inserted by slave
timeOutCnt <= timeOutCnt - 1;
end if;
end if;
end process;
----------------------------------------------------------------------------------
-- Title: Data byte shift register
-- Description: Stores the byte to be written or the byte read depending on the
-- transfer direction.
----------------------------------------------------------------------------------
DATABYTE_SHREG: process (CLK)
begin
if Rising_Edge(CLK) then
if ((latchData = '1' or latchAddr = '1') and sclCnt = 0) then
dataByte <= loadByte; --latch address/data
bitCount <= 7;
--set flag so that we know what is the byte we are sending
if (latchData = '1') then
addrNData <= '0';
else
addrNData <= '1';
end if;
elsif (shiftBit = '1' and sclCnt = 0) then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
end if;
end if;
end process;
loadByte <= A_I when latchAddr = '1' else
D_I;
dataBitOut <= dataByte(dataByte'high);
D_O <= dataByte;
----------------------------------------------------------------------------------
-- Title: Current address register
-- Description: Stores the TWI slave address
----------------------------------------------------------------------------------
CURRADDR_REG: process (CLK)
begin
if Rising_Edge(CLK) then
if (latchAddr = '1') then
currAddr <= A_I; --latch address/data
end if;
end if;
end process;
rwBit <= currAddr(0);
----------------------------------------------------------------------------------
-- Title: Substate counter
-- Description: Divides each state into 4, to respect the setup and hold times of
-- the TWI bus.
----------------------------------------------------------------------------------
SUBSTATE_CNT: process (CLK)
begin
if Rising_Edge(CLK) then
if (state = stIdle) then
subState <= "00";
elsif (sclCnt = 0) then
subState <= subState + 1;
end if;
end if;
end process;
SYNC_PROC: process (CLK)
begin
if Rising_Edge(CLK) then
state <= nstate;
rSda <= iSda;
rScl <= iScl;
if (int_Rst = '1') then
DONE_O <= '0';
ERR_O <= '0';
errTypeR <= errType;
else
DONE_O <= iDone;
ERR_O <= iErr;
errTypeR <= errType;
end if;
end if;
end process;
OUTPUT_DECODE: process (nstate, subState, state, errTypeR, dataByte(0),
sclCnt, bitCount, rSda, rScl, dataBitOut, arbLost, dSda, addrNData)
begin
iSda <= rSda; --no change by default
iScl <= rScl;
iDone <= '0';
iErr <= '0';
errType <= errTypeR; --keep error type
shiftBit <= '0';
latchAddr <= '0';
latchData <= '0';
if (state = stStart) then
case (subState) is
when "00" =>
iSda <= '1';
--keep SCL
when "01" =>
iSda <= '1';
iScl <= '1';
when "10" =>
iSda <= '0';
iScl <= '1';
when "11" =>
iSda <= '0';
iScl <= '0';
when others =>
end case;
end if;
if (state = stStop or state = stStopError) then
case (subState) is
when "00" =>
iSda <= '0';
--keep SCL
when "01" =>
iSda <= '0';
iScl <= '1';
when "10" =>
iSda <= '1';
iScl <= '1';
when "11" => --we will only reach this is there is an arbitration error
--keep SDA;
iScl <= '0'; --need to toggle clock
when others =>
end case;
end if;
if (state = stRead or state = stSAck) then
case (subState) is
when "00" =>
iSda <= '1'; --this will be 'Z' on SDA
--keep SCL
when "01" =>
--keep SDA
iScl <= '1';
when "10" =>
--keep SDA
iScl <= '1';
when "11" =>
--keep SDA
iScl <= '0';
when others =>
end case;
end if;
if (state = stWrite) then
case (subState) is
when "00" =>
iSda <= dataBitOut;
--keep SCL
when "01" =>
--keep SDA
iScl <= '1';
when "10" =>
--keep SDA
iScl <= '1';
when "11" =>
--keep SDA
iScl <= '0';
when others =>
end case;
end if;
if (state = stMAck) then
case (subState) is
when "00" =>
iSda <= '0'; -- acknowledge by writing 0
--keep SCL
when "01" =>
--keep SDA
iScl <= '1';
when "10" =>
--keep SDA
iScl <= '1';
when "11" =>
--keep SDA
iScl <= '0';
when others =>
end case;
end if;
if (state = stMNAckStop or state = stMNAckStart) then
case (subState) is
when "00" =>
iSda <= '1'; -- not acknowledge by writing 1
--keep SCL
when "01" =>
--keep SDA
iScl <= '1';
when "10" =>
--keep SDA
iScl <= '1';
when "11" =>
--keep SDA
iScl <= '0';
when others =>
end case;
end if;
if (state = stSAck and sclCnt = 0 and subState = "01") then
if (dSda = '1') then
iDone <= '1';
iErr <= '1'; --not acknowledged
errType <= errNAck;
elsif (addrNData = '0') then
--we are done only when the data is sent too after the address
iDone <= '1';
end if;
end if;
if (state = stRead and subState = "01" and sclCnt = 0 and bitCount = 0) then
iDone <= '1'; --read done
end if;
if (state = stWrite and arbLost = '1') then
iDone <= '1'; --write done
iErr <= '1'; --we lost the arbitration
errType <= errArb;
end if;
if ((state = stWrite and sclCnt = 0 and subState = "11") or --shift at end of bit
((state = stSAck or state = stRead) and subState = "01")) then --read in middle of bit
shiftBit <= '1';
end if;
if (state = stStart) then
latchAddr <= '1';
end if;
if (state = stSAck and subState = "11") then --get the data byte for the next write
latchData <= '1';
end if;
end process;
NEXT_STATE_DECODE: process (state, busState, slaveWait, arbLost, STB_I, MSG_I, STP_I,
SRST, subState, bitCount, int_Rst, dataByte, A_I, currAddr, rwBit, sclCnt, addrNData)
begin
nstate <= state; --default is to stay in current state
case (state) is
when stIdle =>
if (STB_I = '1' and busState = busFree and SRST = '0') then
nstate <= stStart;
end if;
when stStart =>
if (sclCnt = 0) then
if (int_Rst = '1') then
nstate <= stStop;
elsif (subState = "11") then
nstate <= stWrite;
end if;
end if;
when stWrite =>
if (arbLost = '1') then
nstate <= stIdle;
elsif (sclCnt = 0) then
if (int_Rst = '1') then
nstate <= stStop;
elsif (subState = "11" and bitCount = 0) then
nstate <= stSAck;
end if;
end if;
when stSAck =>
if (sclCnt = 0) then
if (int_Rst = '1' or (subState = "11" and dataByte(0) = '1')) then
nstate <= stStop;
elsif (subState = "11") then
if (addrNData = '1') then --if we have just sent the address, tx/rx the data too
if (rwBit = '1') then
nstate <= stRead;
else
nstate <= stWrite;
end if;
elsif (STB_I = '1') then -- Continue...
if (MSG_I = '1' or currAddr /= A_I) then -- ...with new transfer...
if (STP_I = '0') then -- ...by Repeated Start.
nstate <= stStart;
else -- ...by Stop and Start.
nstate <= stStop;
end if;
else -- ...with next...
if (rwBit = '1') then
nstate <= stRead; -- read byte.
else
nstate <= stWrite; -- write byte.
end if;
end if;
else -- Stop transfer.
nstate <= stStop;
end if;
end if;
end if;
when stStop =>
--bugfix: if device is driving SDA low (read transfer) we cannot send stop bit
--check the arbitration flag
if (subState = "10" and sclCnt = 0 and arbLost = '0') then
nstate <= stIdle;
end if;
--stay here, if stop bit cannot be sent, pulse clock an retry
when stRead =>
if (sclCnt = 0) then
if (int_Rst = '1') then
nstate <= stStop;
elsif (subState = "11" and bitCount = 7) then --bitCount will underflow
if (STB_I = '1') then -- Continue...
if (MSG_I = '1' or currAddr /= A_I) then -- with new transfer...
if (STP_I = '0') then -- by Repeated Start.
nstate <= stMNAckStart;
else -- by Stop and Start.
nstate <= stMNAckStop;
end if;
else -- with next read byte
nstate <= stMAck;
end if;
else -- Stop transfer.
nstate <= stMNAckStop;
end if;
end if;
end if;
when stMAck =>
if (sclCnt = 0) then
if (int_Rst = '1') then
nstate <= stStop;
elsif (subState = "11") then
nstate <= stRead;
end if;
end if;
when stMNAckStart =>
if (arbLost = '1') then
nstate <= stIdle; -- arbitration lost, back off, no error because we got all the data
elsif (sclCnt = 0) then
if (int_Rst = '1') then
nstate <= stStop;
elsif (subState = "11") then
nstate <= stStart;
end if;
end if;
when stMNAckStop =>
if (arbLost = '1') then
nstate <= stIdle; -- arbitration lost, back off, no error because we got all the data
elsif (sclCnt = 0) then
if (int_Rst = '1') then
nstate <= stStop;
elsif (subState = "11") then
nstate <= stStop;
end if;
end if;
when others =>
nstate <= stIdle;
end case;
end process;
----------------------------------------------------------------------------------
-- Open-drain outputs for bi-directional SDA and SCL
----------------------------------------------------------------------------------
-- SDA <= 'Z' when rSDA = '1' else
-- '0';
-- SCL <= 'Z' when rSCL = '1' else
-- '0';
s_sda_t <= '1' when rSDA = '1' else '0';
s_sda_o <= '0';
s_scl_o <= '0';
s_scl_t <= '1' when rSCL = '1' else '0';
end Behavioral;
|
mit
|
02a76a3b6798e9860a53189942e77493
| 0.535327 | 3.842131 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_gamma_correction_1_0/hdl/vhdl/Loop_loop_height_cud.vhd
| 1 | 11,878 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Loop_loop_height_cud_rom is
generic(
dwidth : integer := 8;
awidth : integer := 8;
mem_size : integer := 256
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
addr2 : in std_logic_vector(awidth-1 downto 0);
ce2 : in std_logic;
q2 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of Loop_loop_height_cud_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
signal addr2_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem0 : mem_array := (
0 to 21=> "00000000", 22 to 32=> "00000001", 33 to 40=> "00000010", 41 to 45=> "00000011",
46 to 50=> "00000100", 51 to 54=> "00000101", 55 to 58=> "00000110", 59 to 62=> "00000111",
63 to 65=> "00001000", 66 to 68=> "00001001", 69 to 71=> "00001010", 72 to 73=> "00001011",
74 to 76=> "00001100", 77 to 78=> "00001101", 79 to 80=> "00001110", 81 to 83=> "00001111",
84 to 85=> "00010000", 86 to 87=> "00010001", 88 to 89=> "00010010", 90 to 91=> "00010011",
92 to 93=> "00010100", 94 => "00010101", 95 to 96=> "00010110", 97 to 98=> "00010111",
99 => "00011000", 100 to 101=> "00011001", 102 to 103=> "00011010", 104 => "00011011",
105 to 106=> "00011100", 107 => "00011101", 108 to 109=> "00011110", 110 => "00011111",
111 => "00100000", 112 to 113=> "00100001", 114 => "00100010", 115 => "00100011",
116 to 117=> "00100100", 118 => "00100101", 119 => "00100110", 120 => "00100111",
121 to 122=> "00101000", 123 => "00101001", 124 => "00101010", 125 => "00101011",
126 => "00101100", 127 => "00101101", 128 to 129=> "00101110", 130 => "00101111",
131 => "00110000", 132 => "00110001", 133 => "00110010", 134 => "00110011",
135 => "00110100", 136 => "00110101", 137 => "00110110", 138 => "00110111",
139 => "00111000", 140 => "00111001", 141 => "00111010", 142 => "00111011",
143 => "00111100", 144 => "00111101", 145 => "00111110", 146 => "00111111",
147 => "01000000", 148 => "01000001", 149 => "01000011", 150 => "01000100",
151 => "01000101", 152 => "01000110", 153 => "01000111", 154 => "01001000",
155 => "01001001", 156 => "01001011", 157 => "01001100", 158 => "01001101",
159 => "01001110", 160 => "01010000", 161 => "01010001", 162 => "01010010",
163 => "01010011", 164 => "01010101", 165 => "01010110", 166 => "01010111",
167 => "01011001", 168 => "01011010", 169 => "01011011", 170 => "01011101",
171 => "01011110", 172 => "01011111", 173 => "01100001", 174 => "01100010",
175 => "01100011", 176 => "01100101", 177 => "01100110", 178 => "01101000",
179 => "01101001", 180 => "01101011", 181 => "01101100", 182 => "01101110",
183 => "01101111", 184 => "01110001", 185 => "01110010", 186 => "01110100",
187 => "01110101", 188 => "01110111", 189 => "01111001", 190 => "01111010",
191 => "01111100", 192 => "01111101", 193 => "01111111", 194 => "10000001",
195 => "10000010", 196 => "10000100", 197 => "10000110", 198 => "10000111",
199 => "10001001", 200 => "10001011", 201 => "10001101", 202 => "10001110",
203 => "10010000", 204 => "10010010", 205 => "10010100", 206 => "10010110",
207 => "10010111", 208 => "10011001", 209 => "10011011", 210 => "10011101",
211 => "10011111", 212 => "10100001", 213 => "10100011", 214 => "10100101",
215 => "10100110", 216 => "10101000", 217 => "10101010", 218 => "10101100",
219 => "10101110", 220 => "10110000", 221 => "10110010", 222 => "10110100",
223 => "10110110", 224 => "10111000", 225 => "10111010", 226 => "10111101",
227 => "10111111", 228 => "11000001", 229 => "11000011", 230 => "11000101",
231 => "11000111", 232 => "11001001", 233 => "11001100", 234 => "11001110",
235 => "11010000", 236 => "11010010", 237 => "11010100", 238 => "11010111",
239 => "11011001", 240 => "11011011", 241 => "11011101", 242 => "11100000",
243 => "11100010", 244 => "11100100", 245 => "11100111", 246 => "11101001",
247 => "11101011", 248 => "11101110", 249 => "11110000", 250 => "11110011",
251 => "11110101", 252 => "11111000", 253 => "11111010", 254 => "11111101",
255 => "11111111" );
signal mem1 : mem_array := (
0 to 21=> "00000000", 22 to 32=> "00000001", 33 to 40=> "00000010", 41 to 45=> "00000011",
46 to 50=> "00000100", 51 to 54=> "00000101", 55 to 58=> "00000110", 59 to 62=> "00000111",
63 to 65=> "00001000", 66 to 68=> "00001001", 69 to 71=> "00001010", 72 to 73=> "00001011",
74 to 76=> "00001100", 77 to 78=> "00001101", 79 to 80=> "00001110", 81 to 83=> "00001111",
84 to 85=> "00010000", 86 to 87=> "00010001", 88 to 89=> "00010010", 90 to 91=> "00010011",
92 to 93=> "00010100", 94 => "00010101", 95 to 96=> "00010110", 97 to 98=> "00010111",
99 => "00011000", 100 to 101=> "00011001", 102 to 103=> "00011010", 104 => "00011011",
105 to 106=> "00011100", 107 => "00011101", 108 to 109=> "00011110", 110 => "00011111",
111 => "00100000", 112 to 113=> "00100001", 114 => "00100010", 115 => "00100011",
116 to 117=> "00100100", 118 => "00100101", 119 => "00100110", 120 => "00100111",
121 to 122=> "00101000", 123 => "00101001", 124 => "00101010", 125 => "00101011",
126 => "00101100", 127 => "00101101", 128 to 129=> "00101110", 130 => "00101111",
131 => "00110000", 132 => "00110001", 133 => "00110010", 134 => "00110011",
135 => "00110100", 136 => "00110101", 137 => "00110110", 138 => "00110111",
139 => "00111000", 140 => "00111001", 141 => "00111010", 142 => "00111011",
143 => "00111100", 144 => "00111101", 145 => "00111110", 146 => "00111111",
147 => "01000000", 148 => "01000001", 149 => "01000011", 150 => "01000100",
151 => "01000101", 152 => "01000110", 153 => "01000111", 154 => "01001000",
155 => "01001001", 156 => "01001011", 157 => "01001100", 158 => "01001101",
159 => "01001110", 160 => "01010000", 161 => "01010001", 162 => "01010010",
163 => "01010011", 164 => "01010101", 165 => "01010110", 166 => "01010111",
167 => "01011001", 168 => "01011010", 169 => "01011011", 170 => "01011101",
171 => "01011110", 172 => "01011111", 173 => "01100001", 174 => "01100010",
175 => "01100011", 176 => "01100101", 177 => "01100110", 178 => "01101000",
179 => "01101001", 180 => "01101011", 181 => "01101100", 182 => "01101110",
183 => "01101111", 184 => "01110001", 185 => "01110010", 186 => "01110100",
187 => "01110101", 188 => "01110111", 189 => "01111001", 190 => "01111010",
191 => "01111100", 192 => "01111101", 193 => "01111111", 194 => "10000001",
195 => "10000010", 196 => "10000100", 197 => "10000110", 198 => "10000111",
199 => "10001001", 200 => "10001011", 201 => "10001101", 202 => "10001110",
203 => "10010000", 204 => "10010010", 205 => "10010100", 206 => "10010110",
207 => "10010111", 208 => "10011001", 209 => "10011011", 210 => "10011101",
211 => "10011111", 212 => "10100001", 213 => "10100011", 214 => "10100101",
215 => "10100110", 216 => "10101000", 217 => "10101010", 218 => "10101100",
219 => "10101110", 220 => "10110000", 221 => "10110010", 222 => "10110100",
223 => "10110110", 224 => "10111000", 225 => "10111010", 226 => "10111101",
227 => "10111111", 228 => "11000001", 229 => "11000011", 230 => "11000101",
231 => "11000111", 232 => "11001001", 233 => "11001100", 234 => "11001110",
235 => "11010000", 236 => "11010010", 237 => "11010100", 238 => "11010111",
239 => "11011001", 240 => "11011011", 241 => "11011101", 242 => "11100000",
243 => "11100010", 244 => "11100100", 245 => "11100111", 246 => "11101001",
247 => "11101011", 248 => "11101110", 249 => "11110000", 250 => "11110011",
251 => "11110101", 252 => "11111000", 253 => "11111010", 254 => "11111101",
255 => "11111111" );
attribute syn_rom_style : string;
attribute syn_rom_style of mem0 : signal is "block_rom";
attribute syn_rom_style of mem1 : signal is "block_rom";
attribute ROM_STYLE : string;
attribute ROM_STYLE of mem0 : signal is "block";
attribute ROM_STYLE of mem1 : signal is "block";
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
memory_access_guard_2: process (addr2)
begin
addr2_tmp <= addr2;
--synthesis translate_off
if (CONV_INTEGER(addr2) > mem_size-1) then
addr2_tmp <= (others => '0');
else
addr2_tmp <= addr2;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem0(CONV_INTEGER(addr0_tmp));
end if;
if (ce1 = '1') then
q1 <= mem0(CONV_INTEGER(addr1_tmp));
end if;
if (ce2 = '1') then
q2 <= mem1(CONV_INTEGER(addr2_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity Loop_loop_height_cud is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 256;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address2 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of Loop_loop_height_cud is
component Loop_loop_height_cud_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR;
addr2 : IN STD_LOGIC_VECTOR;
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR);
end component;
begin
Loop_loop_height_cud_rom_U : component Loop_loop_height_cud_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1,
addr2 => address2,
ce2 => ce2,
q2 => q2);
end architecture;
|
mit
|
0deb1079f0d840f3c281ec06fb910cad
| 0.55144 | 3.624657 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodScopeController/src/DataPath.vhd
| 1 | 27,151 |
-------------------------------------------------------------------------------
--
-- File: DataPath.vhd
-- Author: Tudor Gherman
-- Original Project: Zmod ADC 1410 Low Level Controller
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module synchronizes the data output by the ADC on the Dco clock (DcoClk)
-- to the ADC sampling clock (ADC_SamplingClk) domain.
-- A shallow FIFO is instantiated for this purpose.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
use work.PkgZmodADC.all;
entity DataPath is
Generic (
-- sampling clock frequency (in ns).
kSamplingPeriod : real range 8.0 to 100.0:= 10.0;
-- ADC number of bits.
kADC_Width : integer range 10 to 16 := 14
);
Port (
-- Sampling clock.
ADC_SamplingClk : in STD_LOGIC;
-- Reset signal asynchronously asserted and synchronously
-- de-asserted (in the ADC_SamplingClk domain).
acRst_n : in STD_LOGIC;
-- AD92xx/AD96xx DCO output clock.
DcoClkIn : in std_logic;
-- AD92xx/AD96xx DCO output clock forwarded to the IP's upper levels.
DcoClkOut : out std_logic;
-- When logic '1', this signal enables data acquisition from the ADC. This signal
-- should be kept in logic '0' until the downstream IP (e.g. DMA controller) is
-- ready to receive the ADC data.
dEnableAcquisition : in std_logic;
-- ADC parallel interleaved output data signals.
dADC_Data : in std_logic_vector(kADC_Width-1 downto 0);
-- AD92xx/AD96xx demutiplexed Channel A data output (synchronized in
-- the ADC_SamplingClk domain).
cChannelA : out STD_LOGIC_VECTOR (kADC_Width-1 downto 0);
-- AD92xx/AD96xx demutiplexed Channel B data output (synchronized in
-- the ADC_SamplingClk domain).
cChannelB : out STD_LOGIC_VECTOR (kADC_Width-1 downto 0);
-- Channel A & B data valid indicator.
cDataOutValid : out STD_LOGIC;
-- Synchronization FIFO read enable signal; asserted by the IP's upper levels.
cFIFO_RdEn : in STD_LOGIC;
-- Signal indicating when it is safe to assert acRst_n.
-- (when dFIFO_WrRstBusy is '1', it is not safe to assert acRst_n).
dFIFO_WrRstBusy : out std_logic;
-- dDataOverflow indicates that the shallow synchronization FIFO in the DataPath
-- module is full. There are two cases in which this signal is asserted:
-- 1. The ratio between the ADC_InClk and ADC_SamplingClk clock frequencies is
-- different from kADC_ClkDiv.
-- 2. The upper levels can not accept data (cDataAxisTready is not asserted)
-- This IP is not designed to store data, the upper levels should always be able
-- to accept incoming samples. The output of this IP should be processed in real time.
dDataOverflow : out STD_LOGIC;
-- Inputs indicating when both the ADC and relay initialization is complete
-- synchronized in the ADC_SampingClk domain and in the DcoClk domain.
cInitDone : in std_logic;
dInitDone : in std_logic
);
end DataPath;
architecture Behavioral of DataPath is
-- Function used to compute the CLKOUT1_DIVIDE and CLKFBOUT_MULT_F parameters
-- of the MMCM so that the VCO frequency is in the specified range.
-- The MMCM is used for de-skew purposes, so the MMCM's input and output
-- clock frequency should be the same. The CLKOUT1_DIVIDE and CLKFBOUT_MULT_F
-- need to be adjusted to cover input clock frequencies between 10MHz and
-- 400MHz.
function MMCM_M_Coef(SamplingPeriod:real)
return real is
begin
--400MHz to 200MHz -> VCO frequency = [1200;600]
if ((SamplingPeriod > 2.5) and (SamplingPeriod <= 5.0)) then
return 3.0;
--200MHz to 100MHz
elsif ((SamplingPeriod > 5.0) and (SamplingPeriod <= 10.0)) then
return 6.0;
--100MHz to 50MHz
elsif ((SamplingPeriod > 10.0) and (SamplingPeriod <= 20.0)) then
return 12.0;
--50MHz to 25MHz
elsif ((SamplingPeriod > 20.0) and (SamplingPeriod <= 40.0)) then
return 24.0;
--25MHz to 12.5MHz
elsif ((SamplingPeriod > 40.0) and (SamplingPeriod <= 80.0)) then
return 48.0;
--12.5MHz to 10MHz
elsif (SamplingPeriod > 80.0) then
return 64.0;
--Out of specifications;
else
return 1.0;
end if;
end function;
COMPONENT ZmodADC_SynchonizationFIFO
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC);
END COMPONENT;
signal acRstFIFO, adRstFIFO : std_logic;
signal DcoBufgClk, FboutDcoClk, FbinDcoClk, DcoPLL_Clk, DcoPLL_Clk2, DcoBufioClk : std_logic;
signal dFIFO_WrEn: std_logic := '0';
signal asFIFO_Empty, dFIFO_Full : std_logic;
signal dFIFO_In : std_logic_vector(31 downto 0);
signal dChannelA, dChannelB : std_logic_vector(kADC_Width-1 downto 0);
signal dChannelA_Aux, dChannelB_Aux : std_logic_vector (16 downto 0);
signal cFIFO_Dout : std_logic_vector (31 downto 0);
signal cFIFO_Valid : std_logic;
signal dFIFO_Overflow : std_logic;
signal cFIFO_RdEnLoc : std_logic;
signal aMMCM_Locked: std_logic;
signal cMMCM_LockedLoc: std_logic;
signal cMMCM_LckdFallingFlag: std_logic;
signal cMMCM_LckdRisingFlag: std_logic;
signal cMMCM_Locked_q: std_logic_vector(3 downto 0);
signal cMMCM_Reset_q: std_logic_vector(3 downto 0);
signal aMMCM_ClkStop, cMMCM_ClkStop: std_logic;
signal cMMCM_ClkStop_q: std_logic_vector(3 downto 0);
signal cMMCM_ClkStopFallingFlag: std_logic;
signal cFIFO_Reset_q: std_logic_vector(3 downto 0);
signal dFIFO_RstInterval: std_logic_vector(5 downto 0);
signal cInitDoneDly : std_logic;
signal cInitDoneFallingFlag : std_logic;
constant kClkfboutMultF : real := MMCM_M_Coef(kSamplingPeriod);
constant kClk1Divide : integer := integer(MMCM_M_Coef(kSamplingPeriod));
constant kDummy : std_logic_vector (15 downto 0) := x"0000";
begin
DcoClkOut <= DcoBufgClk;
------------------------------------------------------------------------------------------
-- Input data interface decode
------------------------------------------------------------------------------------------
-- Demultiplex the input data bus
GenerateIDDR : for i in 0 to (kADC_Width-1) generate
InstIDDR : IDDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE", "SAME_EDGE"
-- or "SAME_EDGE_PIPELINED"
INIT_Q1 => '0', -- Initial value of Q1: '0' or '1'
INIT_Q2 => '0', -- Initial value of Q2: '0' or '1'
SRTYPE => "SYNC") -- Set/Reset type: "SYNC" or "ASYNC"
port map (
Q1 => dChannelA(i), -- 1-bit output for positive edge of clock
Q2 => dChannelB(i), -- 1-bit output for negative edge of clock
C => DcoBufioClk, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D => dADC_Data(i), -- 1-bit DDR data input
R => '0', -- 1-bit reset
S => '0' -- 1-bit set
);
end generate GenerateIDDR;
-- The synchronization FIFO has a constant width that should accommodate
-- ADC widths between 10 and 16 bit wide. Xilinx FIFO generator does not
-- provide any easy means to parametrize the FIFO width.
dChannelA_Aux <= dChannelA & kDummy(16-kADC_Width downto 0);
dChannelB_Aux <= dChannelB & kDummy(16-kADC_Width downto 0);
dFIFO_In <= dChannelA_Aux(16 downto 1) & dChannelB_Aux (16 downto 1);
------------------------------------------------------------------------------------------
-- Input data interface de-skew
------------------------------------------------------------------------------------------
--Clock buffer for write FIFO clock.
InstDcoBufg : BUFG
port map (
O => DcoBufgClk, -- 1-bit output: Clock output (connect to I/O clock loads).
I => DcoPLL_Clk -- 1-bit input: Clock input (connect to an IBUF or BUFMR).
);
--FIFO write clock de-skew.
InstBufrFeedbackPLL : BUFR
generic map (
BUFR_DIVIDE => "1", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => FbinDcoClk, -- 1-bit output: Clock output port
CE => '1', -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => '0', -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => FboutDcoClk -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
InstDcoBufio : BUFIO
port map (
O => DcoBufioClk,
I => DcoPLL_Clk2
);
MMCME2_ADV_inst : MMCME2_ADV
generic map (
BANDWIDTH => "OPTIMIZED", -- Jitter programming (OPTIMIZED, HIGH, LOW)
CLKFBOUT_MULT_F => kClkfboutMultF, -- Multiply value for all CLKOUT (2.000-64.000).
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB (-360.000-360.000).
CLKIN1_PERIOD => kSamplingPeriod, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
CLKIN2_PERIOD => kSamplingPeriod,
-- CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
CLKOUT1_DIVIDE => kClk1Divide,
CLKOUT2_DIVIDE => kClk1Divide,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT6_DIVIDE => 1,
CLKOUT0_DIVIDE_F => 1.0, -- Divide amount for CLKOUT0 (1.000-128.000).
-- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
CLKOUT6_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => IDDR_ClockPhase(kSamplingPeriod),
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
CLKOUT6_PHASE => 0.0,
CLKOUT4_CASCADE => FALSE, -- Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL
DIVCLK_DIVIDE => 1, -- Master division value (1-106)
-- REF_JITTER: Reference input jitter in UI (0.000-0.999).
REF_JITTER1 => 0.0,
REF_JITTER2 => 0.0,
STARTUP_WAIT => FALSE, -- Delays DONE until MMCM is locked (FALSE, TRUE)
-- Spread Spectrum: Spread Spectrum Attributes
SS_EN => "FALSE", -- Enables spread spectrum (FALSE, TRUE)
SS_MODE => "CENTER_HIGH", -- CENTER_HIGH, CENTER_LOW, DOWN_HIGH, DOWN_LOW
SS_MOD_PERIOD => 10000, -- Spread spectrum modulation period (ns) (VALUES)
-- USE_FINE_PS: Fine phase shift enable (TRUE/FALSE)
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_USE_FINE_PS => FALSE,
CLKOUT2_USE_FINE_PS => FALSE,
CLKOUT3_USE_FINE_PS => FALSE,
CLKOUT4_USE_FINE_PS => FALSE,
CLKOUT5_USE_FINE_PS => FALSE,
CLKOUT6_USE_FINE_PS => FALSE
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => open, -- 1-bit output: CLKOUT0
CLKOUT0B => open, -- 1-bit output: Inverted CLKOUT0
CLKOUT1 => DcoPLL_Clk, -- 1-bit output: CLKOUT1
CLKOUT1B => open, -- 1-bit output: Inverted CLKOUT1
CLKOUT2 => DcoPLL_Clk2, -- 1-bit output: CLKOUT2
CLKOUT2B => open, -- 1-bit output: Inverted CLKOUT2
CLKOUT3 => open, -- 1-bit output: CLKOUT3
CLKOUT3B => open, -- 1-bit output: Inverted CLKOUT3
CLKOUT4 => open, -- 1-bit output: CLKOUT4
CLKOUT5 => open, -- 1-bit output: CLKOUT5
CLKOUT6 => open, -- 1-bit output: CLKOUT6
-- DRP Ports: 16-bit (each) output: Dynamic reconfiguration ports
DO => open, -- 16-bit output: DRP data
DRDY => open, -- 1-bit output: DRP ready
-- Dynamic Phase Shift Ports: 1-bit (each) output: Ports used for dynamic phase shifting of the outputs
PSDONE => open, -- 1-bit output: Phase shift done
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => FboutDcoClk, -- 1-bit output: Feedback clock
CLKFBOUTB => open, -- 1-bit output: Inverted CLKFBOUT
-- Status Ports: 1-bit (each) output: MMCM status ports
CLKFBSTOPPED => open, -- 1-bit output: Feedback clock stopped
CLKINSTOPPED => aMMCM_ClkStop, -- 1-bit output: Input clock stopped
LOCKED => aMMCM_Locked, -- 1-bit output: LOCK
-- Clock Inputs: 1-bit (each) input: Clock inputs
CLKIN1 => DcoClkIn, -- 1-bit input: Primary clock
CLKIN2 => '0', -- 1-bit input: Secondary clock
-- Control Ports: 1-bit (each) input: MMCM control ports
CLKINSEL => '1', -- 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2
PWRDWN => '0', -- 1-bit input: Power-down
RST => cMMCM_Reset_q(0), -- 1-bit input: Reset
-- DRP Ports: 7-bit (each) input: Dynamic reconfiguration ports
DADDR => (others => '0'), -- 7-bit input: DRP address
DCLK => '0', -- 1-bit input: DRP clock
DEN => '0', -- 1-bit input: DRP enable
DI => (others => '0'), -- 16-bit input: DRP data
DWE => '0', -- 1-bit input: DRP write enable
-- Dynamic Phase Shift Ports: 1-bit (each) input: Ports used for dynamic phase shifting of the outputs
PSCLK => '0', -- 1-bit input: Phase shift clock
PSEN => '0', -- 1-bit input: Phase shift enable
PSINCDEC => '0', -- 1-bit input: Phase shift increment/decrement
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => FbinDcoClk -- 1-bit input: Feedback clock
);
------------------------------------------------------------------------------------------
--DcoClock presence detection
------------------------------------------------------------------------------------------
-- Not sure if LOCKED or CLKINSTOPPED should be used to reset the MMCM. For now,
-- logic relying on CLKINSTOPPED is commented out
InstMMCM_LockSampingClkSync: entity work.SyncAsync
port map (
aoReset => '0',
aIn => aMMCM_Locked,
OutClk => ADC_SamplingClk,
oOut => cMMCM_LockedLoc);
--InstMMCM_ClkInStoppedSync: entity work.SyncAsync
-- port map (
-- aoReset => '0',
-- aIn => aMMCM_ClkStop,
-- OutClk => ADC_SamplingClk,
-- oOut => cMMCM_ClkStop);
--the process has no reset signal, however the synchronous logic input
--has no reset either. I don't think this is an issue
ProcMMCM_LockedDetect: process(ADC_SamplingClk)
begin
if Rising_Edge(ADC_SamplingClk) then
cMMCM_Locked_q <= cMMCM_LockedLoc & cMMCM_Locked_q(3 downto 1);
cMMCM_LckdFallingFlag <= cMMCM_Locked_q(3) and not cMMCM_LockedLoc;
cMMCM_LckdRisingFlag <= not cMMCM_Locked_q(3) and cMMCM_LockedLoc;
end if;
end process;
--ProcMMCM_ClkInStoppedDetect: process(ADC_SamplingClk)
--begin
-- if Rising_Edge(ADC_SamplingClk) then
-- cMMCM_ClkStop_q <= cMMCM_ClkStop & cMMCM_ClkStop_q(3 downto 1);
-- cMMCM_ClkStopFallingFlag <= cMMCM_ClkStop_q(3) and not cMMCM_ClkStop;
-- --cMMCM_ClkStopRisingFlag <= not cMMCM_Locked_q(3) and cMMCM_ClkStop;
-- end if;
--end process;
------------------------------------------------------------------------------------------
--MMCM Reset
------------------------------------------------------------------------------------------
-- This process will keep the generated reset (cMMCM_Reset_q(0)) asserted for
-- 4 ADC_SamplingClk cycles. The MMCM_RSTMINPULSE Minimum Reset Pulse Width is 5.00ns
-- This condition is guaranteed for Sampling frequencies up to 800MHz.
ProcMMCM_Reset: process(acRst_n, ADC_SamplingClk)
begin
if (acRst_n = '0') then
cMMCM_Reset_q <= (others => '1');
elsif Rising_Edge(ADC_SamplingClk) then
--if (cMMCM_ClkStopFallingFlag = '1') then -- Not clear which condition should be used from Xilinx documentation
if (cMMCM_LckdFallingFlag = '1') then
cMMCM_Reset_q <= (others => '1');
else
cMMCM_Reset_q <= '0' & cMMCM_Reset_q(cMMCM_Reset_q'high downto 1);
end if;
end if;
end process;
------------------------------------------------------------------------------------------
--Synchronization FIFO Reset
------------------------------------------------------------------------------------------
-- Generate synchronization FIFO reset requirements:
-- 1. It is always recommended to have the asynchronous reset
-- asserted for at least 3 or C_SYNCHRONIZER_STAGE (whichever is maximum) slowest clock
-- cycles.
-- 2. Ensure that there is a minimum gap of 6 clocks (slower clock in case of independent
-- clock) between 2 consecutive resets when you use Asynchronous reset.
-- 3. The clock(s) must be available when the reset is applied. If for any reason, the
-- clock(s) is/are lost at the time of reset, you must apply the reset again when the
-- clock(s) is/are available. Violating this requirement may cause an unexpected behavior.
-- Sometimes, the busy signals may be stuck and might need reconfiguration of FPGA.
-- Solution:
-- 1. The asynchronous FIFO reset is generated by the LSB of a 4 bit shift register with
-- the reset value of "1111" (cMMCM_Reset_q). This guarantees that requirement 1 is respected.
-- 2. The responsibility of respecting requirement 2 is passed to the user.
-- The dFIFO_WrRstBusy which is synchronized in the top level module in the SysClk100 domain
-- indicates when it is safe to assert the reset.
-- 3. The cMMCM_LckdRisingFlag assures the FIFO is reset after a power cycle.
-- FIFO has 3 reset sources:
-- 1)IP input reset signal propagated through acRst_n.
-- 2)MMCM Locked rising edge: the cMMCM_LckdRisingFlag assures the FIFO is reset after a
-- power cycle.
-- 3)Initialization done flag from the ADC and Relay configuration modules.
-- cInitDoneFallingFlag will not trigger a FIFO reset before the initial ADC configuration is
-- completed but that it is not necessary since cMMCM_LckdRisingFlag will handle this. Upon
-- initial configuration completion any relay state change will trigger a reset through the
-- cInitDoneFallingFlag.
ProcInitDoneDly: process(acRst_n, ADC_SamplingClk)
begin
if (acRst_n = '0') then
cInitDoneDly <= '0';
elsif Rising_Edge(ADC_SamplingClk) then
cInitDoneDly <= cInitDone;
end if;
end process;
cInitDoneFallingFlag <= cInitDoneDly and (not cInitDone);
ProcFIFO_Reset: process(acRst_n, ADC_SamplingClk)
begin
if (acRst_n = '0') then
cFIFO_Reset_q <= (others => '1');
elsif Rising_Edge(ADC_SamplingClk) then
if ((cMMCM_LckdRisingFlag = '1') or (cInitDoneFallingFlag = '1')) then
cFIFO_Reset_q <= (others => '1');
else
cFIFO_Reset_q <= '0' & cFIFO_Reset_q(cFIFO_Reset_q'high downto 1);
end if;
end if;
end process;
acRstFIFO <= cFIFO_Reset_q(0);
-- Synchronize the FIFO reset signal generated in the ADC_SamplingClk domain
-- in the DcoBufgClk domain to be used by the reset busy logic and by the
-- FIFO write enable logic. The reset busy logic is designed in the DcoBufgClk
-- domain so that a BRAM FIFO implementation using the dedicated write reset
-- busy port can be easily accommodated in the design.
InstSyncDcoFIFO_Reset : entity work.ResetBridge
Generic map(
kPolarity => '1')
Port map(
aRst => acRstFIFO,
OutClk => DcoBufgClk,
aoRst => adRstFIFO);
ProcFIFO_ResetInterval: process(adRstFIFO, DcoBufgClk)
begin
if (adRstFIFO = '1') then
dFIFO_RstInterval <= (others => '1');
elsif Rising_Edge(DcoBufgClk) then
dFIFO_RstInterval <= '0' & dFIFO_RstInterval(dFIFO_RstInterval'high downto 1);
end if;
end process;
dFIFO_WrRstBusy <= dFIFO_RstInterval(0);
------------------------------------------------------------------------------------------
--Synchronization FIFO write enable
------------------------------------------------------------------------------------------
-- Requirements:
-- 1. While in reset state the full flag is asserted and wr_en should be low;
-- 2. Samples should not be loaded while the DcoClk is not stable.
-- 3. Samples should not be loaded before the initial configuration is completed
-- or while AC/DC coupling or gain select relays are changing states.
-- Solution: Allow FIFO write enable to be asserted while the DcoClk is lost
-- and count on de-asserting the output AXI Stream data interface valid signal during
-- this interval. The FIFO is reset anyway when the clock recovers, so there is no risk that
-- the user can read samples loaded into the FIFO before the MMCM locks after Dco recovery.
-- The valid signal is de-asserted with some latency caused by the SyncAsync module
-- (InstMMCM_LockSampingClkSync) that passes the aMMCM_Locked in the ADC_SamplingClk domain.
-- However, the FIFO latency is greater than that of the SyncAsync module, so there is
-- no risk that samples loaded after the MMCM locked is de-asserted can be read by the
-- user.
ProcFIFO_WrEn : process (DcoBufgClk, adRstFIFO)
begin
if (adRstFIFO = '1') then
dFIFO_WrEn <= '0';
elsif (rising_edge(DcoBufgClk)) then
if (dFIFO_Full = '1' or dInitDone = '0' or dEnableAcquisition = '0') then
dFIFO_WrEn <= '0';
else
dFIFO_WrEn <= '1';
end if;
end if;
end process;
------------------------------------------------------------------------------------------
--Synchronization FIFO write enable
------------------------------------------------------------------------------------------
-- FIFO Generator v13.2www.xilinx.com136PG057 October 4, 2017Chapter 3:
-- To avoid unexpected behavior, it is not recommended to drive/toggle wr_en/rd_en
-- when rst is asserted/high.
cFIFO_RdEnLoc <= cFIFO_RdEn and (not acRstFIFO);
------------------------------------------------------------------------------------------
--Synchronization FIFO
------------------------------------------------------------------------------------------
-- FIFO data latency specified in:
-- Xilinx pg057 Table 3-26 (Read Port Flags Update Latency Due to a Write Operation)
-- not sure if this is the correct reference. Does data have he same latency as read
-- port flags in response to write operations?
-- Latency: 1 wr_clk + (N + 4) rd_clk (+1 rd_clk)
-- 2 synchronization stages => N = 2; Extra 1 wr_clk latency added by the IDDR primitive
InstADC_FIFO : ZmodADC_SynchonizationFIFO
PORT MAP (
rst => acRstFIFO,
wr_clk => DcoBufgClk,
rd_clk => ADC_SamplingClk,
din => dFIFO_In,
wr_en => dFIFO_WrEn,
rd_en => cFIFO_RdEnLoc,
dout => cFIFO_Dout,
full => dFIFO_Full,
overflow => dFIFO_Overflow,
empty => asFIFO_Empty,
valid => cFIFO_Valid
);
------------------------------------------------------------------------------------------
-- Data Output Valid Logic:
-- The output valid flag is forced to '0' when the DCO strobe is lost and is
-- only allowed to be reasserted after the FIFO is reset on the rising edge
-- of cMMCM_Locked.
-- A disadvantage of adding this process is that it adds an extra clock latency
-- Also, the user has to extract all data from the FIFO before disabling the
-- Dco strobe
ProcOutDataValid: process(acRst_n, ADC_SamplingClk)
begin
if (acRst_n = '0') then
cDataOutValid <= '0';
cChannelA <= (others => '0');
cChannelB <= (others => '0');
elsif Rising_Edge(ADC_SamplingClk) then
cChannelA <= cFIFO_Dout (31 downto 32-kADC_Width);
cChannelB <= cFIFO_Dout (15 downto 16-kADC_Width);
if ((cMMCM_LockedLoc = '0') or (cMMCM_Locked_q /= "1111")) then
cDataOutValid <= '0';
else
cDataOutValid <= cFIFO_Valid;
end if;
end if;
end process;
-- Overflow flag logic. The assertion of dDataOverflow can only occur in
-- 2 conditions:
-- 1. The clock tree or ADC clock divider are incorrectly configured.
-- 2. The upper level logic can not accept the data provided by this IP.
-- It is the user responsibility to avoid this situation or to reduce the
-- sampling rate so that this condition s avoided.
-- dDataOverflow can only be reset by asserting the IP reset input.
ProcDataOverflow : process (DcoBufgClk, adRstFIFO)
begin
if (adRstFIFO = '1') then
dDataOverflow <= '0';
elsif (rising_edge(DcoBufgClk)) then
if (dFIFO_Overflow = '1') then
dDataOverflow <= '1';
end if;
end if;
end process;
end Behavioral;
|
mit
|
e2f9b6fbf909cc2cc6e4bb539808214e
| 0.616036 | 4.10446 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_gamma_correction_1_0/hdl/vhdl/Loop_loop_height_ibs.vhd
| 1 | 12,914 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Loop_loop_height_ibs_rom is
generic(
dwidth : integer := 8;
awidth : integer := 8;
mem_size : integer := 256
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
addr2 : in std_logic_vector(awidth-1 downto 0);
ce2 : in std_logic;
q2 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of Loop_loop_height_ibs_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
signal addr2_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem0 : mem_array := (
0 => "00000000", 1 => "00010000", 2 => "00010111", 3 => "00011100",
4 => "00100000", 5 => "00100100", 6 => "00100111", 7 => "00101010",
8 => "00101101", 9 => "00110000", 10 => "00110010", 11 => "00110101",
12 => "00110111", 13 => "00111010", 14 => "00111100", 15 => "00111110",
16 => "01000000", 17 => "01000010", 18 => "01000100", 19 => "01000110",
20 => "01000111", 21 => "01001001", 22 => "01001011", 23 => "01001101",
24 => "01001110", 25 => "01010000", 26 => "01010001", 27 => "01010011",
28 => "01010100", 29 => "01010110", 30 => "01010111", 31 => "01011001",
32 => "01011010", 33 => "01011100", 34 => "01011101", 35 => "01011110",
36 => "01100000", 37 => "01100001", 38 => "01100010", 39 => "01100100",
40 => "01100101", 41 => "01100110", 42 => "01100111", 43 => "01101001",
44 => "01101010", 45 => "01101011", 46 => "01101100", 47 => "01101101",
48 => "01101111", 49 => "01110000", 50 => "01110001", 51 => "01110010",
52 => "01110011", 53 => "01110100", 54 => "01110101", 55 => "01110110",
56 => "01110111", 57 => "01111001", 58 => "01111010", 59 => "01111011",
60 => "01111100", 61 => "01111101", 62 => "01111110", 63 => "01111111",
64 => "10000000", 65 => "10000001", 66 => "10000010", 67 => "10000011",
68 => "10000100", 69 => "10000101", 70 => "10000110", 71 to 72=> "10000111",
73 => "10001000", 74 => "10001001", 75 => "10001010", 76 => "10001011",
77 => "10001100", 78 => "10001101", 79 => "10001110", 80 => "10001111",
81 => "10010000", 82 to 83=> "10010001", 84 => "10010010", 85 => "10010011",
86 => "10010100", 87 => "10010101", 88 => "10010110", 89 to 90=> "10010111",
91 => "10011000", 92 => "10011001", 93 => "10011010", 94 => "10011011",
95 to 96=> "10011100", 97 => "10011101", 98 => "10011110", 99 => "10011111",
100 to 101=> "10100000", 102 => "10100001", 103 => "10100010", 104 => "10100011",
105 to 106=> "10100100", 107 => "10100101", 108 => "10100110", 109 to 110=> "10100111",
111 => "10101000", 112 => "10101001", 113 to 114=> "10101010", 115 => "10101011",
116 => "10101100", 117 to 118=> "10101101", 119 => "10101110", 120 => "10101111",
121 to 122=> "10110000", 123 => "10110001", 124 => "10110010", 125 to 126=> "10110011",
127 => "10110100", 128 to 129=> "10110101", 130 => "10110110", 131 to 132=> "10110111",
133 => "10111000", 134 => "10111001", 135 to 136=> "10111010", 137 => "10111011",
138 to 139=> "10111100", 140 => "10111101", 141 to 142=> "10111110", 143 => "10111111",
144 to 145=> "11000000", 146 => "11000001", 147 to 148=> "11000010", 149 => "11000011",
150 to 151=> "11000100", 152 => "11000101", 153 to 154=> "11000110", 155 to 156=> "11000111",
157 => "11001000", 158 to 159=> "11001001", 160 => "11001010", 161 to 162=> "11001011",
163 to 164=> "11001100", 165 => "11001101", 166 to 167=> "11001110", 168 => "11001111",
169 to 170=> "11010000", 171 to 172=> "11010001", 173 => "11010010", 174 to 175=> "11010011",
176 to 177=> "11010100", 178 => "11010101", 179 to 180=> "11010110", 181 to 182=> "11010111",
183 => "11011000", 184 to 185=> "11011001", 186 to 187=> "11011010", 188 => "11011011",
189 to 190=> "11011100", 191 to 192=> "11011101", 193 to 194=> "11011110", 195 => "11011111",
196 to 197=> "11100000", 198 to 199=> "11100001", 200 to 201=> "11100010", 202 => "11100011",
203 to 204=> "11100100", 205 to 206=> "11100101", 207 to 208=> "11100110", 209 to 210=> "11100111",
211 => "11101000", 212 to 213=> "11101001", 214 to 215=> "11101010", 216 to 217=> "11101011",
218 to 219=> "11101100", 220 to 221=> "11101101", 222 to 223=> "11101110", 224 => "11101111",
225 to 226=> "11110000", 227 to 228=> "11110001", 229 to 230=> "11110010", 231 to 232=> "11110011",
233 to 234=> "11110100", 235 to 236=> "11110101", 237 to 238=> "11110110", 239 to 240=> "11110111",
241 to 242=> "11111000", 243 to 244=> "11111001", 245 to 246=> "11111010", 247 to 248=> "11111011",
249 to 250=> "11111100", 251 to 252=> "11111101", 253 to 254=> "11111110", 255 => "11111111" );
signal mem1 : mem_array := (
0 => "00000000", 1 => "00010000", 2 => "00010111", 3 => "00011100",
4 => "00100000", 5 => "00100100", 6 => "00100111", 7 => "00101010",
8 => "00101101", 9 => "00110000", 10 => "00110010", 11 => "00110101",
12 => "00110111", 13 => "00111010", 14 => "00111100", 15 => "00111110",
16 => "01000000", 17 => "01000010", 18 => "01000100", 19 => "01000110",
20 => "01000111", 21 => "01001001", 22 => "01001011", 23 => "01001101",
24 => "01001110", 25 => "01010000", 26 => "01010001", 27 => "01010011",
28 => "01010100", 29 => "01010110", 30 => "01010111", 31 => "01011001",
32 => "01011010", 33 => "01011100", 34 => "01011101", 35 => "01011110",
36 => "01100000", 37 => "01100001", 38 => "01100010", 39 => "01100100",
40 => "01100101", 41 => "01100110", 42 => "01100111", 43 => "01101001",
44 => "01101010", 45 => "01101011", 46 => "01101100", 47 => "01101101",
48 => "01101111", 49 => "01110000", 50 => "01110001", 51 => "01110010",
52 => "01110011", 53 => "01110100", 54 => "01110101", 55 => "01110110",
56 => "01110111", 57 => "01111001", 58 => "01111010", 59 => "01111011",
60 => "01111100", 61 => "01111101", 62 => "01111110", 63 => "01111111",
64 => "10000000", 65 => "10000001", 66 => "10000010", 67 => "10000011",
68 => "10000100", 69 => "10000101", 70 => "10000110", 71 to 72=> "10000111",
73 => "10001000", 74 => "10001001", 75 => "10001010", 76 => "10001011",
77 => "10001100", 78 => "10001101", 79 => "10001110", 80 => "10001111",
81 => "10010000", 82 to 83=> "10010001", 84 => "10010010", 85 => "10010011",
86 => "10010100", 87 => "10010101", 88 => "10010110", 89 to 90=> "10010111",
91 => "10011000", 92 => "10011001", 93 => "10011010", 94 => "10011011",
95 to 96=> "10011100", 97 => "10011101", 98 => "10011110", 99 => "10011111",
100 to 101=> "10100000", 102 => "10100001", 103 => "10100010", 104 => "10100011",
105 to 106=> "10100100", 107 => "10100101", 108 => "10100110", 109 to 110=> "10100111",
111 => "10101000", 112 => "10101001", 113 to 114=> "10101010", 115 => "10101011",
116 => "10101100", 117 to 118=> "10101101", 119 => "10101110", 120 => "10101111",
121 to 122=> "10110000", 123 => "10110001", 124 => "10110010", 125 to 126=> "10110011",
127 => "10110100", 128 to 129=> "10110101", 130 => "10110110", 131 to 132=> "10110111",
133 => "10111000", 134 => "10111001", 135 to 136=> "10111010", 137 => "10111011",
138 to 139=> "10111100", 140 => "10111101", 141 to 142=> "10111110", 143 => "10111111",
144 to 145=> "11000000", 146 => "11000001", 147 to 148=> "11000010", 149 => "11000011",
150 to 151=> "11000100", 152 => "11000101", 153 to 154=> "11000110", 155 to 156=> "11000111",
157 => "11001000", 158 to 159=> "11001001", 160 => "11001010", 161 to 162=> "11001011",
163 to 164=> "11001100", 165 => "11001101", 166 to 167=> "11001110", 168 => "11001111",
169 to 170=> "11010000", 171 to 172=> "11010001", 173 => "11010010", 174 to 175=> "11010011",
176 to 177=> "11010100", 178 => "11010101", 179 to 180=> "11010110", 181 to 182=> "11010111",
183 => "11011000", 184 to 185=> "11011001", 186 to 187=> "11011010", 188 => "11011011",
189 to 190=> "11011100", 191 to 192=> "11011101", 193 to 194=> "11011110", 195 => "11011111",
196 to 197=> "11100000", 198 to 199=> "11100001", 200 to 201=> "11100010", 202 => "11100011",
203 to 204=> "11100100", 205 to 206=> "11100101", 207 to 208=> "11100110", 209 to 210=> "11100111",
211 => "11101000", 212 to 213=> "11101001", 214 to 215=> "11101010", 216 to 217=> "11101011",
218 to 219=> "11101100", 220 to 221=> "11101101", 222 to 223=> "11101110", 224 => "11101111",
225 to 226=> "11110000", 227 to 228=> "11110001", 229 to 230=> "11110010", 231 to 232=> "11110011",
233 to 234=> "11110100", 235 to 236=> "11110101", 237 to 238=> "11110110", 239 to 240=> "11110111",
241 to 242=> "11111000", 243 to 244=> "11111001", 245 to 246=> "11111010", 247 to 248=> "11111011",
249 to 250=> "11111100", 251 to 252=> "11111101", 253 to 254=> "11111110", 255 => "11111111" );
attribute syn_rom_style : string;
attribute syn_rom_style of mem0 : signal is "block_rom";
attribute syn_rom_style of mem1 : signal is "block_rom";
attribute ROM_STYLE : string;
attribute ROM_STYLE of mem0 : signal is "block";
attribute ROM_STYLE of mem1 : signal is "block";
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
memory_access_guard_2: process (addr2)
begin
addr2_tmp <= addr2;
--synthesis translate_off
if (CONV_INTEGER(addr2) > mem_size-1) then
addr2_tmp <= (others => '0');
else
addr2_tmp <= addr2;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem0(CONV_INTEGER(addr0_tmp));
end if;
if (ce1 = '1') then
q1 <= mem0(CONV_INTEGER(addr1_tmp));
end if;
if (ce2 = '1') then
q2 <= mem1(CONV_INTEGER(addr2_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity Loop_loop_height_ibs is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 256;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address2 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of Loop_loop_height_ibs is
component Loop_loop_height_ibs_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR;
addr2 : IN STD_LOGIC_VECTOR;
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR);
end component;
begin
Loop_loop_height_ibs_rom_U : component Loop_loop_height_ibs_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1,
addr2 => address2,
ce2 => ce2,
q2 => q2);
end architecture;
|
mit
|
0cf6bb8674b4fd997692c0c0b7135635
| 0.555676 | 3.580261 | false | false | false | false |
Digilent/vivado-library
|
ip/MIPI_CSI_2_RX/tb/tb_ECC.vhd
| 1 | 4,540 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/27/2017 03:44:54 PM
-- Design Name:
-- Module Name: tb_ECC - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library STD;
use STD.textio.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_ECC is
-- Port ( );
end tb_ECC;
architecture Behavioral of tb_ECC is
component ECC is
Port (
StreamClk : in std_logic;
sHeaderIn : in std_logic_vector(31 downto 0);
sCE : in std_logic;
sReady : out std_logic;
sHeaderOut : out std_logic_vector(31 downto 0);
sValid: out std_logic; --asserted for one cycle when ECC processing is done and correct data is present on sHeaderOut
sError: out std_logic; --asserted for one cycle when ECC processing detected an error
sRst : in std_logic
);
end component;
constant kClkPeriod : time := 10ns;
type stimulus_t is array (natural range <>) of std_logic_vector(31 downto 0);
constant kStimulus : stimulus_t := (x"3F01F037", x"3F01F037");
signal StreamClk, sRst, sCE, sReady, sValid, sError : std_logic := '0';
signal sHeaderIn, sHeaderOut : std_logic_vector(31 downto 0);
begin
StreamClk <= not StreamClk after kClkPeriod / 2;
process
variable temp : std_logic_vector(31 downto 0);
begin
sRst <= '1';
wait for 5*kClkPeriod;
sCE <= '0';
sRst <= '0';
wait until Rising_Edge(StreamClk);
for i in kStimulus'range loop
wait until Rising_Edge(StreamClk);
-- unmodified stimulus
assert (sReady = '1') report "DUT ECC is not ready when it should be" severity failure;
sCE <= '1';
sHeaderIn <= kStimulus(i);
wait until Rising_Edge(StreamClk);
sCE <= '0';
wait until Rising_Edge(StreamClk);
wait until Rising_Edge(StreamClk);
wait until Rising_Edge(StreamClk);
assert (sValid = '1' and sError = '0' and sHeaderOut = sHeaderIn) report "ECC error where there should not be one" severity failure;
for iBit in 29 downto 0 loop -- Bits 31 and 30 (7 and 6 of ECC) are always 0
wait until Rising_Edge(StreamClk);
-- modified stimulus (one bit flipped)
assert (sReady = '1') report "DUT ECC is not ready when it should be" severity failure;
sCE <= '1';
temp := kStimulus(i);
temp(iBit) := not temp(iBit);
sHeaderIn <= temp;
wait until Rising_Edge(StreamClk);
sCE <= '0';
wait until Rising_Edge(StreamClk);
wait until Rising_Edge(StreamClk);
wait until Rising_Edge(StreamClk);
assert (sValid = '1' and sError = '1' and sHeaderOut = kStimulus(i)) report "ECC one-bit error was not fixed" severity failure;
end loop;
for iBit in 29 downto 0 loop
for iBit2 in 29 downto 0 loop
if (iBit /= iBit2) then
wait until Rising_Edge(StreamClk);
-- modified stimulus (one bit flipped)
assert (sReady = '1') report "DUT ECC is not ready when it should be" severity failure;
sCE <= '1';
temp := kStimulus(i);
temp(iBit) := not temp(iBit);
temp(iBit2) := not temp(iBit2);
sHeaderIn <= temp;
wait until Rising_Edge(StreamClk);
sCE <= '0';
wait until Rising_Edge(StreamClk);
wait until Rising_Edge(StreamClk);
wait until Rising_Edge(StreamClk);
assert (sValid = '0' and sError = '1') report "ECC two-bit error was not detected" severity failure;
end if;
end loop;
end loop;
end loop;
wait;
end process;
DUT: ECC
Port map (
StreamClk => StreamClk,
sHeaderIn => sHeaderIn,
sCE => sCE,
sReady => sReady,
sHeaderOut => sHeaderOut,
sValid => sValid,
sError => sError,
sRst => sRst
);
end Behavioral;
|
mit
|
a3aa71abe9f4eb9d0d14ccecfceaf869
| 0.582819 | 4.16132 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
runhorse/runhorse.vhd
| 1 | 1,500 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity runhorse is
Port (
clock : in std_logic;
display : out std_logic_vector(15 downto 0)
);
end runhorse;
architecture Behavioral of runhorse is
signal count:std_logic_vector( 15 downto 0 );
signal number:std_logic_vector( 3 downto 0 );
begin
process( clock ) begin
if clock'event and clock = '1' then
count <= count + 1;
if count = 0 then
number <= number + 1;
end if;
end if;
end process;
display <=
"0000000000000001" when number = 0 else
"0000000000000010" when number = 1 else
"0000000000000100" when number = 2 else
"0000000000001000" when number = 3 else
"0000000000010000" when number = 4 else
"0000000000100000" when number = 5 else
"0000000001000000" when number = 6 else
"0000000010000000" when number = 7 else
"0000000100000000" when number = 8 else
"0000001000000000" when number = 9 else
"0000010000000000" when number = 10 else
"0000100000000000" when number = 11 else
"0001000000000000" when number = 12 else
"0010000000000000" when number = 13 else
"0100000000000000" when number = 14 else
"1000000000000000";
end Behavioral;
|
mit
|
73b7817a11c10411595d25439247e349
| 0.673333 | 3.722084 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_contrast_stretch_1_0/hdl/vhdl/hls_contrast_strebkb.vhd
| 1 | 1,686 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hls_contrast_strebkb_DSP48_0 is
port (
a: in std_logic_vector(8 - 1 downto 0);
b: in std_logic_vector(22 - 1 downto 0);
p: out std_logic_vector(29 - 1 downto 0));
end entity;
architecture behav of hls_contrast_strebkb_DSP48_0 is
signal a_cvt: unsigned(8 - 1 downto 0);
signal b_cvt: unsigned(22 - 1 downto 0);
signal p_cvt: unsigned(29 - 1 downto 0);
attribute keep : string;
attribute keep of a_cvt : signal is "true";
attribute keep of b_cvt : signal is "true";
attribute keep of p_cvt : signal is "true";
begin
a_cvt <= unsigned(a);
b_cvt <= unsigned(b);
p_cvt <= unsigned (resize(unsigned (unsigned (a_cvt) * unsigned (b_cvt)), 29));
p <= std_logic_vector(p_cvt);
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity hls_contrast_strebkb is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of hls_contrast_strebkb is
component hls_contrast_strebkb_DSP48_0 is
port (
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
hls_contrast_strebkb_DSP48_0_U : component hls_contrast_strebkb_DSP48_0
port map (
a => din0,
b => din1,
p => dout);
end architecture;
|
mit
|
435bd38752d0e494bc280354984eddd5
| 0.616845 | 3.305882 | false | false | false | false |
rickyzhangNYC/Pipelined_Multimedia_Cell_Lite_Unit
|
ALU.vhd
| 1 | 2,578 |
-------------------------------------------------------------------------------
--
-- Title : ALU
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\ALU.vhd
-- Generated : Wed Dec 7 15:44:11 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {ALU} architecture {structural}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ALU is
port(
rs1 : in std_logic_vector(63 downto 0);
rs2 : in std_logic_vector(63 downto 0);
alu_op : in std_logic_vector(3 downto 0);
rd : out std_logic_vector(63 downto 0);
rd_address_in: in std_logic_vector(3 downto 0);
rd_address_writeback: out std_logic_vector(3 downto 0);
writeback: out std_logic
);
end ALU;
--}} End of automatically maintained section
architecture structural of ALU is
signal s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14: std_logic_vector(63 downto 0);
begin
or64: entity or64bit port map(rs1 => rs1, rs2 => rs2, rd => s1);
and64: entity and64bit port map(rs1 => rs1, rs2 => rs2, rd => s2);
cnth: entity cnth port map(rs1 => rs1, rd => s3);
clz: entity clz port map(rs1 => rs1, rd => s4);
rot: entity rot port map(rs1 => rs1, rs2 => rs2, rd => s5);
shlhi: entity shlhi port map(rs1 => rs1, rs2 => rs2, rd => s6);
a: entity a port map(rs1 => rs1, rs2 => rs2, rd => s7);
sfw: entity sfw port map(rs1 => rs1, rs2 => rs2, rd => s8);
ah: entity ah port map(rs1 => rs1, rs2 => rs2, rd => s9);
sfh: entity sfh port map(rs1 => rs1, rs2 => rs2, rd => s10);
ahs: entity ahs port map(rs1 => rs1, rs2 => rs2, rd => s11);
sfhs: entity sfhs port map(rs1 => rs1, rs2 => rs2, rd => s12);
mpyu: entity mpyu port map(rs1 => rs1, rs2 => rs2, rd => s13);
absdb: entity absdb port map(rs1 => rs1, rs2 => rs2, rd => s14);
mux_out: entity mux14to2 port map(mux_select => alu_op, in1 => s1, in2 => s2, in3 => s3, in4 => s4, in5 => s5, in6 => s6, in7 => s7, in8 => s8, in9 => s9, in10 => s10, in11 => s11, in12 => s12, in13 => s13, in14 => s14, o1 => rd, writeback => writeback);
rd_address_writeback <= rd_address_in;
end structural;
|
apache-2.0
|
f66b282b81ba494467c422e612a325ef
| 0.527541 | 2.936219 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodScopeController/tb/tb_TestAD96xx_92xxSPI_Model_all.vhd
| 2 | 5,777 |
-------------------------------------------------------------------------------
--
-- File: tb_TestAD96xx_92xxSPI_Model_all.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 May 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Test bench used to instantiate the tb_TestAD96xx_92xxSPI_Model as multiple
-- entities so that all supported errors are inserted in the SPI transactions
-- initiated. This test bench is used to test if the tb_TestAD96xx_92xxSPI_Model
-- correctly reports the deliberately inserted errors.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_TestAD96xx_92xxSPI_Model_all is
Generic (
-- Parameter identifying the Zmod:
-- 0 -> Zmod Scope 1410 - 105 (AD9648)
-- 1 -> Zmod Scope 1010 - 40 (AD9204)
-- 2 -> Zmod Scope 1010 - 125 (AD9608)
-- 3 -> Zmod Scope 1210 - 40 (AD9231)
-- 4 -> Zmod Scope 1210 - 125 (AD9628)
-- 5 -> Zmod Scope 1410 - 40 (AD9251)
-- 6 -> Zmod Scope 1410 - 125 (AD9648)
kZmodID : integer range 0 to 6 := 0
);
end tb_TestAD96xx_92xxSPI_Model_all;
architecture Behavioral of tb_TestAD96xx_92xxSPI_Model_all is
begin
-- Test the ADI_2WireSPI_Model for a write operation and no
-- error inserted.
InstWrNoErr: entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 0,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a read operation and no
-- error inserted.
InstRdNoErr: entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 0,
kCmdRdWr => '1',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a write operation with a
-- sSDIO to sSPI_Clk Setup Time error inserted for the SPI transaction.
InstWrData2ClkSetupErr: entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 1,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a write operation with a
-- CS to sSPI_Clk and a data to sSPI_Clk setup time error inserted
-- for the SPI transaction.
InstWrCs2ClkSetupErr: entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 2,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a write operation with a
-- sSDIO to sSPI_Clk hold time error inserted for the SPI transaction.
InstWrData2ClkHoldErr: entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 3,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a write operation with a
-- sCS to sSPI_Clk hold time error inserted for the SPI transaction.
InstWrCs2ClkHoldErr: entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 4,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a write operation with a
-- pulse width errors and a SPI clock period error inserted
-- for the SPI transaction.
InstSclkPulsePeriodErr : entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 5,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a write operation with an
-- extra address bit error inserted for the SPI transaction.
InstNoBitErr : entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 6,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
end Behavioral;
|
mit
|
6e502b1c7e6600e3f8a54f6effadce69
| 0.662974 | 4.159107 | false | true | false | false |
Digilent/vivado-library
|
ip/video_scaler/hdl/vhdl/video_scaler.vhd
| 1 | 46,074 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity video_scaler is
generic (
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER := 32 );
port (
s_axi_ctrl_AWVALID : IN STD_LOGIC;
s_axi_ctrl_AWREADY : OUT STD_LOGIC;
s_axi_ctrl_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
s_axi_ctrl_WVALID : IN STD_LOGIC;
s_axi_ctrl_WREADY : OUT STD_LOGIC;
s_axi_ctrl_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
s_axi_ctrl_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_CTRL_DATA_WIDTH/8-1 downto 0);
s_axi_ctrl_ARVALID : IN STD_LOGIC;
s_axi_ctrl_ARREADY : OUT STD_LOGIC;
s_axi_ctrl_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
s_axi_ctrl_RVALID : OUT STD_LOGIC;
s_axi_ctrl_RREADY : IN STD_LOGIC;
s_axi_ctrl_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
s_axi_ctrl_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_ctrl_BVALID : OUT STD_LOGIC;
s_axi_ctrl_BREADY : IN STD_LOGIC;
s_axi_ctrl_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
stream_in_TDATA : IN STD_LOGIC_VECTOR (23 downto 0);
stream_in_TKEEP : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TSTRB : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TID : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
stream_out_TDATA : OUT STD_LOGIC_VECTOR (23 downto 0);
stream_out_TKEEP : OUT STD_LOGIC_VECTOR (2 downto 0);
stream_out_TSTRB : OUT STD_LOGIC_VECTOR (2 downto 0);
stream_out_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_in_TVALID : IN STD_LOGIC;
stream_in_TREADY : OUT STD_LOGIC;
stream_out_TVALID : OUT STD_LOGIC;
stream_out_TREADY : IN STD_LOGIC );
end;
architecture behav of video_scaler is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"video_scaler,hls_ip_2018_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=6.670000,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=6.380000,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=24,HLS_SYN_DSP=68,HLS_SYN_FF=14153,HLS_SYN_LUT=10721,HLS_VERSION=2018_2}";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant C_S_AXI_WSTRB_WIDTH : INTEGER range 63 downto 0 := 4;
constant C_S_AXI_ADDR_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_lv24_0 : STD_LOGIC_VECTOR (23 downto 0) := "000000000000000000000000";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_ready : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal in_width : STD_LOGIC_VECTOR (31 downto 0);
signal in_height : STD_LOGIC_VECTOR (31 downto 0);
signal out_width : STD_LOGIC_VECTOR (31 downto 0);
signal out_height : STD_LOGIC_VECTOR (31 downto 0);
signal Block_Mat_exit45_pro_U0_ap_start : STD_LOGIC;
signal Block_Mat_exit45_pro_U0_ap_done : STD_LOGIC;
signal Block_Mat_exit45_pro_U0_ap_continue : STD_LOGIC;
signal Block_Mat_exit45_pro_U0_ap_idle : STD_LOGIC;
signal Block_Mat_exit45_pro_U0_ap_ready : STD_LOGIC;
signal Block_Mat_exit45_pro_U0_start_out : STD_LOGIC;
signal Block_Mat_exit45_pro_U0_start_write : STD_LOGIC;
signal Block_Mat_exit45_pro_U0_img_in_rows_V_out_din : STD_LOGIC_VECTOR (31 downto 0);
signal Block_Mat_exit45_pro_U0_img_in_rows_V_out_write : STD_LOGIC;
signal Block_Mat_exit45_pro_U0_img_in_cols_V_out_din : STD_LOGIC_VECTOR (31 downto 0);
signal Block_Mat_exit45_pro_U0_img_in_cols_V_out_write : STD_LOGIC;
signal Block_Mat_exit45_pro_U0_img_out_rows_V_out_din : STD_LOGIC_VECTOR (31 downto 0);
signal Block_Mat_exit45_pro_U0_img_out_rows_V_out_write : STD_LOGIC;
signal Block_Mat_exit45_pro_U0_img_out_cols_V_out_din : STD_LOGIC_VECTOR (31 downto 0);
signal Block_Mat_exit45_pro_U0_img_out_cols_V_out_write : STD_LOGIC;
signal AXIvideo2Mat_U0_ap_start : STD_LOGIC;
signal AXIvideo2Mat_U0_ap_done : STD_LOGIC;
signal AXIvideo2Mat_U0_ap_continue : STD_LOGIC;
signal AXIvideo2Mat_U0_ap_idle : STD_LOGIC;
signal AXIvideo2Mat_U0_ap_ready : STD_LOGIC;
signal AXIvideo2Mat_U0_stream_in_TREADY : STD_LOGIC;
signal AXIvideo2Mat_U0_img_rows_V_read : STD_LOGIC;
signal AXIvideo2Mat_U0_img_cols_V_read : STD_LOGIC;
signal AXIvideo2Mat_U0_img_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal AXIvideo2Mat_U0_img_data_stream_0_V_write : STD_LOGIC;
signal AXIvideo2Mat_U0_img_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal AXIvideo2Mat_U0_img_data_stream_1_V_write : STD_LOGIC;
signal AXIvideo2Mat_U0_img_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal AXIvideo2Mat_U0_img_data_stream_2_V_write : STD_LOGIC;
signal AXIvideo2Mat_U0_img_rows_V_out_din : STD_LOGIC_VECTOR (31 downto 0);
signal AXIvideo2Mat_U0_img_rows_V_out_write : STD_LOGIC;
signal AXIvideo2Mat_U0_img_cols_V_out_din : STD_LOGIC_VECTOR (31 downto 0);
signal AXIvideo2Mat_U0_img_cols_V_out_write : STD_LOGIC;
signal Resize_U0_ap_start : STD_LOGIC;
signal Resize_U0_ap_done : STD_LOGIC;
signal Resize_U0_ap_continue : STD_LOGIC;
signal Resize_U0_ap_idle : STD_LOGIC;
signal Resize_U0_ap_ready : STD_LOGIC;
signal Resize_U0_start_out : STD_LOGIC;
signal Resize_U0_start_write : STD_LOGIC;
signal Resize_U0_p_src_rows_V_read : STD_LOGIC;
signal Resize_U0_p_src_cols_V_read : STD_LOGIC;
signal Resize_U0_p_src_data_stream_0_V_read : STD_LOGIC;
signal Resize_U0_p_src_data_stream_1_V_read : STD_LOGIC;
signal Resize_U0_p_src_data_stream_2_V_read : STD_LOGIC;
signal Resize_U0_p_dst_rows_V_read : STD_LOGIC;
signal Resize_U0_p_dst_cols_V_read : STD_LOGIC;
signal Resize_U0_p_dst_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal Resize_U0_p_dst_data_stream_0_V_write : STD_LOGIC;
signal Resize_U0_p_dst_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal Resize_U0_p_dst_data_stream_1_V_write : STD_LOGIC;
signal Resize_U0_p_dst_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal Resize_U0_p_dst_data_stream_2_V_write : STD_LOGIC;
signal Resize_U0_p_dst_rows_V_out_din : STD_LOGIC_VECTOR (31 downto 0);
signal Resize_U0_p_dst_rows_V_out_write : STD_LOGIC;
signal Resize_U0_p_dst_cols_V_out_din : STD_LOGIC_VECTOR (31 downto 0);
signal Resize_U0_p_dst_cols_V_out_write : STD_LOGIC;
signal Mat2AXIvideo_U0_ap_start : STD_LOGIC;
signal Mat2AXIvideo_U0_ap_done : STD_LOGIC;
signal Mat2AXIvideo_U0_ap_continue : STD_LOGIC;
signal Mat2AXIvideo_U0_ap_idle : STD_LOGIC;
signal Mat2AXIvideo_U0_ap_ready : STD_LOGIC;
signal Mat2AXIvideo_U0_img_rows_V_read : STD_LOGIC;
signal Mat2AXIvideo_U0_img_cols_V_read : STD_LOGIC;
signal Mat2AXIvideo_U0_img_data_stream_0_V_read : STD_LOGIC;
signal Mat2AXIvideo_U0_img_data_stream_1_V_read : STD_LOGIC;
signal Mat2AXIvideo_U0_img_data_stream_2_V_read : STD_LOGIC;
signal Mat2AXIvideo_U0_stream_out_TDATA : STD_LOGIC_VECTOR (23 downto 0);
signal Mat2AXIvideo_U0_stream_out_TVALID : STD_LOGIC;
signal Mat2AXIvideo_U0_stream_out_TKEEP : STD_LOGIC_VECTOR (2 downto 0);
signal Mat2AXIvideo_U0_stream_out_TSTRB : STD_LOGIC_VECTOR (2 downto 0);
signal Mat2AXIvideo_U0_stream_out_TUSER : STD_LOGIC_VECTOR (0 downto 0);
signal Mat2AXIvideo_U0_stream_out_TLAST : STD_LOGIC_VECTOR (0 downto 0);
signal Mat2AXIvideo_U0_stream_out_TID : STD_LOGIC_VECTOR (0 downto 0);
signal Mat2AXIvideo_U0_stream_out_TDEST : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sync_continue : STD_LOGIC;
signal img_in_rows_V_c_full_n : STD_LOGIC;
signal img_in_rows_V_c_dout : STD_LOGIC_VECTOR (31 downto 0);
signal img_in_rows_V_c_empty_n : STD_LOGIC;
signal img_in_cols_V_c_full_n : STD_LOGIC;
signal img_in_cols_V_c_dout : STD_LOGIC_VECTOR (31 downto 0);
signal img_in_cols_V_c_empty_n : STD_LOGIC;
signal img_out_rows_V_c_full_n : STD_LOGIC;
signal img_out_rows_V_c_dout : STD_LOGIC_VECTOR (31 downto 0);
signal img_out_rows_V_c_empty_n : STD_LOGIC;
signal img_out_cols_V_c_full_n : STD_LOGIC;
signal img_out_cols_V_c_dout : STD_LOGIC_VECTOR (31 downto 0);
signal img_out_cols_V_c_empty_n : STD_LOGIC;
signal img_in_data_stream_0_full_n : STD_LOGIC;
signal img_in_data_stream_0_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_in_data_stream_0_empty_n : STD_LOGIC;
signal img_in_data_stream_1_full_n : STD_LOGIC;
signal img_in_data_stream_1_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_in_data_stream_1_empty_n : STD_LOGIC;
signal img_in_data_stream_2_full_n : STD_LOGIC;
signal img_in_data_stream_2_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_in_data_stream_2_empty_n : STD_LOGIC;
signal img_in_rows_V_c13_full_n : STD_LOGIC;
signal img_in_rows_V_c13_dout : STD_LOGIC_VECTOR (31 downto 0);
signal img_in_rows_V_c13_empty_n : STD_LOGIC;
signal img_in_cols_V_c14_full_n : STD_LOGIC;
signal img_in_cols_V_c14_dout : STD_LOGIC_VECTOR (31 downto 0);
signal img_in_cols_V_c14_empty_n : STD_LOGIC;
signal img_out_data_stream_s_full_n : STD_LOGIC;
signal img_out_data_stream_s_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_out_data_stream_s_empty_n : STD_LOGIC;
signal img_out_data_stream_1_full_n : STD_LOGIC;
signal img_out_data_stream_1_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_out_data_stream_1_empty_n : STD_LOGIC;
signal img_out_data_stream_2_full_n : STD_LOGIC;
signal img_out_data_stream_2_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_out_data_stream_2_empty_n : STD_LOGIC;
signal img_out_rows_V_c15_full_n : STD_LOGIC;
signal img_out_rows_V_c15_dout : STD_LOGIC_VECTOR (31 downto 0);
signal img_out_rows_V_c15_empty_n : STD_LOGIC;
signal img_out_cols_V_c16_full_n : STD_LOGIC;
signal img_out_cols_V_c16_dout : STD_LOGIC_VECTOR (31 downto 0);
signal img_out_cols_V_c16_empty_n : STD_LOGIC;
signal ap_sync_done : STD_LOGIC;
signal ap_sync_ready : STD_LOGIC;
signal ap_sync_reg_AXIvideo2Mat_U0_ap_ready : STD_LOGIC := '0';
signal ap_sync_AXIvideo2Mat_U0_ap_ready : STD_LOGIC;
signal AXIvideo2Mat_U0_ap_ready_count : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal ap_sync_reg_Block_Mat_exit45_pro_U0_ap_ready : STD_LOGIC := '0';
signal ap_sync_Block_Mat_exit45_pro_U0_ap_ready : STD_LOGIC;
signal Block_Mat_exit45_pro_U0_ap_ready_count : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal start_for_Resize_U0_din : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_Resize_U0_full_n : STD_LOGIC;
signal start_for_Resize_U0_dout : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_Resize_U0_empty_n : STD_LOGIC;
signal AXIvideo2Mat_U0_start_full_n : STD_LOGIC;
signal AXIvideo2Mat_U0_start_write : STD_LOGIC;
signal start_for_Mat2AXIvideo_U0_din : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_Mat2AXIvideo_U0_full_n : STD_LOGIC;
signal start_for_Mat2AXIvideo_U0_dout : STD_LOGIC_VECTOR (0 downto 0);
signal start_for_Mat2AXIvideo_U0_empty_n : STD_LOGIC;
signal Mat2AXIvideo_U0_start_full_n : STD_LOGIC;
signal Mat2AXIvideo_U0_start_write : STD_LOGIC;
component Block_Mat_exit45_pro IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
start_full_n : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
start_out : OUT STD_LOGIC;
start_write : OUT STD_LOGIC;
in_width : IN STD_LOGIC_VECTOR (31 downto 0);
in_height : IN STD_LOGIC_VECTOR (31 downto 0);
out_width : IN STD_LOGIC_VECTOR (31 downto 0);
out_height : IN STD_LOGIC_VECTOR (31 downto 0);
img_in_rows_V_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
img_in_rows_V_out_full_n : IN STD_LOGIC;
img_in_rows_V_out_write : OUT STD_LOGIC;
img_in_cols_V_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
img_in_cols_V_out_full_n : IN STD_LOGIC;
img_in_cols_V_out_write : OUT STD_LOGIC;
img_out_rows_V_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
img_out_rows_V_out_full_n : IN STD_LOGIC;
img_out_rows_V_out_write : OUT STD_LOGIC;
img_out_cols_V_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
img_out_cols_V_out_full_n : IN STD_LOGIC;
img_out_cols_V_out_write : OUT STD_LOGIC );
end component;
component AXIvideo2Mat IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
stream_in_TDATA : IN STD_LOGIC_VECTOR (23 downto 0);
stream_in_TVALID : IN STD_LOGIC;
stream_in_TREADY : OUT STD_LOGIC;
stream_in_TKEEP : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TSTRB : IN STD_LOGIC_VECTOR (2 downto 0);
stream_in_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TID : IN STD_LOGIC_VECTOR (0 downto 0);
stream_in_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
img_rows_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
img_rows_V_empty_n : IN STD_LOGIC;
img_rows_V_read : OUT STD_LOGIC;
img_cols_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
img_cols_V_empty_n : IN STD_LOGIC;
img_cols_V_read : OUT STD_LOGIC;
img_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_full_n : IN STD_LOGIC;
img_data_stream_0_V_write : OUT STD_LOGIC;
img_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_full_n : IN STD_LOGIC;
img_data_stream_1_V_write : OUT STD_LOGIC;
img_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_full_n : IN STD_LOGIC;
img_data_stream_2_V_write : OUT STD_LOGIC;
img_rows_V_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
img_rows_V_out_full_n : IN STD_LOGIC;
img_rows_V_out_write : OUT STD_LOGIC;
img_cols_V_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
img_cols_V_out_full_n : IN STD_LOGIC;
img_cols_V_out_write : OUT STD_LOGIC );
end component;
component Resize IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
start_full_n : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
start_out : OUT STD_LOGIC;
start_write : OUT STD_LOGIC;
p_src_rows_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
p_src_rows_V_empty_n : IN STD_LOGIC;
p_src_rows_V_read : OUT STD_LOGIC;
p_src_cols_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
p_src_cols_V_empty_n : IN STD_LOGIC;
p_src_cols_V_read : OUT STD_LOGIC;
p_src_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_0_V_empty_n : IN STD_LOGIC;
p_src_data_stream_0_V_read : OUT STD_LOGIC;
p_src_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_1_V_empty_n : IN STD_LOGIC;
p_src_data_stream_1_V_read : OUT STD_LOGIC;
p_src_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_2_V_empty_n : IN STD_LOGIC;
p_src_data_stream_2_V_read : OUT STD_LOGIC;
p_dst_rows_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
p_dst_rows_V_empty_n : IN STD_LOGIC;
p_dst_rows_V_read : OUT STD_LOGIC;
p_dst_cols_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
p_dst_cols_V_empty_n : IN STD_LOGIC;
p_dst_cols_V_read : OUT STD_LOGIC;
p_dst_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_0_V_full_n : IN STD_LOGIC;
p_dst_data_stream_0_V_write : OUT STD_LOGIC;
p_dst_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_1_V_full_n : IN STD_LOGIC;
p_dst_data_stream_1_V_write : OUT STD_LOGIC;
p_dst_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_2_V_full_n : IN STD_LOGIC;
p_dst_data_stream_2_V_write : OUT STD_LOGIC;
p_dst_rows_V_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
p_dst_rows_V_out_full_n : IN STD_LOGIC;
p_dst_rows_V_out_write : OUT STD_LOGIC;
p_dst_cols_V_out_din : OUT STD_LOGIC_VECTOR (31 downto 0);
p_dst_cols_V_out_full_n : IN STD_LOGIC;
p_dst_cols_V_out_write : OUT STD_LOGIC );
end component;
component Mat2AXIvideo IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
img_rows_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
img_rows_V_empty_n : IN STD_LOGIC;
img_rows_V_read : OUT STD_LOGIC;
img_cols_V_dout : IN STD_LOGIC_VECTOR (31 downto 0);
img_cols_V_empty_n : IN STD_LOGIC;
img_cols_V_read : OUT STD_LOGIC;
img_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_empty_n : IN STD_LOGIC;
img_data_stream_0_V_read : OUT STD_LOGIC;
img_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_empty_n : IN STD_LOGIC;
img_data_stream_1_V_read : OUT STD_LOGIC;
img_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_empty_n : IN STD_LOGIC;
img_data_stream_2_V_read : OUT STD_LOGIC;
stream_out_TDATA : OUT STD_LOGIC_VECTOR (23 downto 0);
stream_out_TVALID : OUT STD_LOGIC;
stream_out_TREADY : IN STD_LOGIC;
stream_out_TKEEP : OUT STD_LOGIC_VECTOR (2 downto 0);
stream_out_TSTRB : OUT STD_LOGIC_VECTOR (2 downto 0);
stream_out_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
stream_out_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component fifo_w32_d2_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (31 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (31 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component fifo_w32_d3_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (31 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (31 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component fifo_w8_d2_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component start_for_Resize_U0 IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (0 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (0 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component start_for_Mat2AXImb6 IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (0 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (0 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component video_scaler_ctrl_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
in_width : OUT STD_LOGIC_VECTOR (31 downto 0);
in_height : OUT STD_LOGIC_VECTOR (31 downto 0);
out_width : OUT STD_LOGIC_VECTOR (31 downto 0);
out_height : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
video_scaler_ctrl_s_axi_U : component video_scaler_ctrl_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH)
port map (
AWVALID => s_axi_ctrl_AWVALID,
AWREADY => s_axi_ctrl_AWREADY,
AWADDR => s_axi_ctrl_AWADDR,
WVALID => s_axi_ctrl_WVALID,
WREADY => s_axi_ctrl_WREADY,
WDATA => s_axi_ctrl_WDATA,
WSTRB => s_axi_ctrl_WSTRB,
ARVALID => s_axi_ctrl_ARVALID,
ARREADY => s_axi_ctrl_ARREADY,
ARADDR => s_axi_ctrl_ARADDR,
RVALID => s_axi_ctrl_RVALID,
RREADY => s_axi_ctrl_RREADY,
RDATA => s_axi_ctrl_RDATA,
RRESP => s_axi_ctrl_RRESP,
BVALID => s_axi_ctrl_BVALID,
BREADY => s_axi_ctrl_BREADY,
BRESP => s_axi_ctrl_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
in_width => in_width,
in_height => in_height,
out_width => out_width,
out_height => out_height);
Block_Mat_exit45_pro_U0 : component Block_Mat_exit45_pro
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => Block_Mat_exit45_pro_U0_ap_start,
start_full_n => start_for_Resize_U0_full_n,
ap_done => Block_Mat_exit45_pro_U0_ap_done,
ap_continue => Block_Mat_exit45_pro_U0_ap_continue,
ap_idle => Block_Mat_exit45_pro_U0_ap_idle,
ap_ready => Block_Mat_exit45_pro_U0_ap_ready,
start_out => Block_Mat_exit45_pro_U0_start_out,
start_write => Block_Mat_exit45_pro_U0_start_write,
in_width => in_width,
in_height => in_height,
out_width => out_width,
out_height => out_height,
img_in_rows_V_out_din => Block_Mat_exit45_pro_U0_img_in_rows_V_out_din,
img_in_rows_V_out_full_n => img_in_rows_V_c_full_n,
img_in_rows_V_out_write => Block_Mat_exit45_pro_U0_img_in_rows_V_out_write,
img_in_cols_V_out_din => Block_Mat_exit45_pro_U0_img_in_cols_V_out_din,
img_in_cols_V_out_full_n => img_in_cols_V_c_full_n,
img_in_cols_V_out_write => Block_Mat_exit45_pro_U0_img_in_cols_V_out_write,
img_out_rows_V_out_din => Block_Mat_exit45_pro_U0_img_out_rows_V_out_din,
img_out_rows_V_out_full_n => img_out_rows_V_c_full_n,
img_out_rows_V_out_write => Block_Mat_exit45_pro_U0_img_out_rows_V_out_write,
img_out_cols_V_out_din => Block_Mat_exit45_pro_U0_img_out_cols_V_out_din,
img_out_cols_V_out_full_n => img_out_cols_V_c_full_n,
img_out_cols_V_out_write => Block_Mat_exit45_pro_U0_img_out_cols_V_out_write);
AXIvideo2Mat_U0 : component AXIvideo2Mat
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => AXIvideo2Mat_U0_ap_start,
ap_done => AXIvideo2Mat_U0_ap_done,
ap_continue => AXIvideo2Mat_U0_ap_continue,
ap_idle => AXIvideo2Mat_U0_ap_idle,
ap_ready => AXIvideo2Mat_U0_ap_ready,
stream_in_TDATA => stream_in_TDATA,
stream_in_TVALID => stream_in_TVALID,
stream_in_TREADY => AXIvideo2Mat_U0_stream_in_TREADY,
stream_in_TKEEP => stream_in_TKEEP,
stream_in_TSTRB => stream_in_TSTRB,
stream_in_TUSER => stream_in_TUSER,
stream_in_TLAST => stream_in_TLAST,
stream_in_TID => stream_in_TID,
stream_in_TDEST => stream_in_TDEST,
img_rows_V_dout => img_in_rows_V_c_dout,
img_rows_V_empty_n => img_in_rows_V_c_empty_n,
img_rows_V_read => AXIvideo2Mat_U0_img_rows_V_read,
img_cols_V_dout => img_in_cols_V_c_dout,
img_cols_V_empty_n => img_in_cols_V_c_empty_n,
img_cols_V_read => AXIvideo2Mat_U0_img_cols_V_read,
img_data_stream_0_V_din => AXIvideo2Mat_U0_img_data_stream_0_V_din,
img_data_stream_0_V_full_n => img_in_data_stream_0_full_n,
img_data_stream_0_V_write => AXIvideo2Mat_U0_img_data_stream_0_V_write,
img_data_stream_1_V_din => AXIvideo2Mat_U0_img_data_stream_1_V_din,
img_data_stream_1_V_full_n => img_in_data_stream_1_full_n,
img_data_stream_1_V_write => AXIvideo2Mat_U0_img_data_stream_1_V_write,
img_data_stream_2_V_din => AXIvideo2Mat_U0_img_data_stream_2_V_din,
img_data_stream_2_V_full_n => img_in_data_stream_2_full_n,
img_data_stream_2_V_write => AXIvideo2Mat_U0_img_data_stream_2_V_write,
img_rows_V_out_din => AXIvideo2Mat_U0_img_rows_V_out_din,
img_rows_V_out_full_n => img_in_rows_V_c13_full_n,
img_rows_V_out_write => AXIvideo2Mat_U0_img_rows_V_out_write,
img_cols_V_out_din => AXIvideo2Mat_U0_img_cols_V_out_din,
img_cols_V_out_full_n => img_in_cols_V_c14_full_n,
img_cols_V_out_write => AXIvideo2Mat_U0_img_cols_V_out_write);
Resize_U0 : component Resize
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => Resize_U0_ap_start,
start_full_n => start_for_Mat2AXIvideo_U0_full_n,
ap_done => Resize_U0_ap_done,
ap_continue => Resize_U0_ap_continue,
ap_idle => Resize_U0_ap_idle,
ap_ready => Resize_U0_ap_ready,
start_out => Resize_U0_start_out,
start_write => Resize_U0_start_write,
p_src_rows_V_dout => img_in_rows_V_c13_dout,
p_src_rows_V_empty_n => img_in_rows_V_c13_empty_n,
p_src_rows_V_read => Resize_U0_p_src_rows_V_read,
p_src_cols_V_dout => img_in_cols_V_c14_dout,
p_src_cols_V_empty_n => img_in_cols_V_c14_empty_n,
p_src_cols_V_read => Resize_U0_p_src_cols_V_read,
p_src_data_stream_0_V_dout => img_in_data_stream_0_dout,
p_src_data_stream_0_V_empty_n => img_in_data_stream_0_empty_n,
p_src_data_stream_0_V_read => Resize_U0_p_src_data_stream_0_V_read,
p_src_data_stream_1_V_dout => img_in_data_stream_1_dout,
p_src_data_stream_1_V_empty_n => img_in_data_stream_1_empty_n,
p_src_data_stream_1_V_read => Resize_U0_p_src_data_stream_1_V_read,
p_src_data_stream_2_V_dout => img_in_data_stream_2_dout,
p_src_data_stream_2_V_empty_n => img_in_data_stream_2_empty_n,
p_src_data_stream_2_V_read => Resize_U0_p_src_data_stream_2_V_read,
p_dst_rows_V_dout => img_out_rows_V_c_dout,
p_dst_rows_V_empty_n => img_out_rows_V_c_empty_n,
p_dst_rows_V_read => Resize_U0_p_dst_rows_V_read,
p_dst_cols_V_dout => img_out_cols_V_c_dout,
p_dst_cols_V_empty_n => img_out_cols_V_c_empty_n,
p_dst_cols_V_read => Resize_U0_p_dst_cols_V_read,
p_dst_data_stream_0_V_din => Resize_U0_p_dst_data_stream_0_V_din,
p_dst_data_stream_0_V_full_n => img_out_data_stream_s_full_n,
p_dst_data_stream_0_V_write => Resize_U0_p_dst_data_stream_0_V_write,
p_dst_data_stream_1_V_din => Resize_U0_p_dst_data_stream_1_V_din,
p_dst_data_stream_1_V_full_n => img_out_data_stream_1_full_n,
p_dst_data_stream_1_V_write => Resize_U0_p_dst_data_stream_1_V_write,
p_dst_data_stream_2_V_din => Resize_U0_p_dst_data_stream_2_V_din,
p_dst_data_stream_2_V_full_n => img_out_data_stream_2_full_n,
p_dst_data_stream_2_V_write => Resize_U0_p_dst_data_stream_2_V_write,
p_dst_rows_V_out_din => Resize_U0_p_dst_rows_V_out_din,
p_dst_rows_V_out_full_n => img_out_rows_V_c15_full_n,
p_dst_rows_V_out_write => Resize_U0_p_dst_rows_V_out_write,
p_dst_cols_V_out_din => Resize_U0_p_dst_cols_V_out_din,
p_dst_cols_V_out_full_n => img_out_cols_V_c16_full_n,
p_dst_cols_V_out_write => Resize_U0_p_dst_cols_V_out_write);
Mat2AXIvideo_U0 : component Mat2AXIvideo
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => Mat2AXIvideo_U0_ap_start,
ap_done => Mat2AXIvideo_U0_ap_done,
ap_continue => Mat2AXIvideo_U0_ap_continue,
ap_idle => Mat2AXIvideo_U0_ap_idle,
ap_ready => Mat2AXIvideo_U0_ap_ready,
img_rows_V_dout => img_out_rows_V_c15_dout,
img_rows_V_empty_n => img_out_rows_V_c15_empty_n,
img_rows_V_read => Mat2AXIvideo_U0_img_rows_V_read,
img_cols_V_dout => img_out_cols_V_c16_dout,
img_cols_V_empty_n => img_out_cols_V_c16_empty_n,
img_cols_V_read => Mat2AXIvideo_U0_img_cols_V_read,
img_data_stream_0_V_dout => img_out_data_stream_s_dout,
img_data_stream_0_V_empty_n => img_out_data_stream_s_empty_n,
img_data_stream_0_V_read => Mat2AXIvideo_U0_img_data_stream_0_V_read,
img_data_stream_1_V_dout => img_out_data_stream_1_dout,
img_data_stream_1_V_empty_n => img_out_data_stream_1_empty_n,
img_data_stream_1_V_read => Mat2AXIvideo_U0_img_data_stream_1_V_read,
img_data_stream_2_V_dout => img_out_data_stream_2_dout,
img_data_stream_2_V_empty_n => img_out_data_stream_2_empty_n,
img_data_stream_2_V_read => Mat2AXIvideo_U0_img_data_stream_2_V_read,
stream_out_TDATA => Mat2AXIvideo_U0_stream_out_TDATA,
stream_out_TVALID => Mat2AXIvideo_U0_stream_out_TVALID,
stream_out_TREADY => stream_out_TREADY,
stream_out_TKEEP => Mat2AXIvideo_U0_stream_out_TKEEP,
stream_out_TSTRB => Mat2AXIvideo_U0_stream_out_TSTRB,
stream_out_TUSER => Mat2AXIvideo_U0_stream_out_TUSER,
stream_out_TLAST => Mat2AXIvideo_U0_stream_out_TLAST,
stream_out_TID => Mat2AXIvideo_U0_stream_out_TID,
stream_out_TDEST => Mat2AXIvideo_U0_stream_out_TDEST);
img_in_rows_V_c_U : component fifo_w32_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit45_pro_U0_img_in_rows_V_out_din,
if_full_n => img_in_rows_V_c_full_n,
if_write => Block_Mat_exit45_pro_U0_img_in_rows_V_out_write,
if_dout => img_in_rows_V_c_dout,
if_empty_n => img_in_rows_V_c_empty_n,
if_read => AXIvideo2Mat_U0_img_rows_V_read);
img_in_cols_V_c_U : component fifo_w32_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit45_pro_U0_img_in_cols_V_out_din,
if_full_n => img_in_cols_V_c_full_n,
if_write => Block_Mat_exit45_pro_U0_img_in_cols_V_out_write,
if_dout => img_in_cols_V_c_dout,
if_empty_n => img_in_cols_V_c_empty_n,
if_read => AXIvideo2Mat_U0_img_cols_V_read);
img_out_rows_V_c_U : component fifo_w32_d3_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit45_pro_U0_img_out_rows_V_out_din,
if_full_n => img_out_rows_V_c_full_n,
if_write => Block_Mat_exit45_pro_U0_img_out_rows_V_out_write,
if_dout => img_out_rows_V_c_dout,
if_empty_n => img_out_rows_V_c_empty_n,
if_read => Resize_U0_p_dst_rows_V_read);
img_out_cols_V_c_U : component fifo_w32_d3_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_Mat_exit45_pro_U0_img_out_cols_V_out_din,
if_full_n => img_out_cols_V_c_full_n,
if_write => Block_Mat_exit45_pro_U0_img_out_cols_V_out_write,
if_dout => img_out_cols_V_c_dout,
if_empty_n => img_out_cols_V_c_empty_n,
if_read => Resize_U0_p_dst_cols_V_read);
img_in_data_stream_0_U : component fifo_w8_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => AXIvideo2Mat_U0_img_data_stream_0_V_din,
if_full_n => img_in_data_stream_0_full_n,
if_write => AXIvideo2Mat_U0_img_data_stream_0_V_write,
if_dout => img_in_data_stream_0_dout,
if_empty_n => img_in_data_stream_0_empty_n,
if_read => Resize_U0_p_src_data_stream_0_V_read);
img_in_data_stream_1_U : component fifo_w8_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => AXIvideo2Mat_U0_img_data_stream_1_V_din,
if_full_n => img_in_data_stream_1_full_n,
if_write => AXIvideo2Mat_U0_img_data_stream_1_V_write,
if_dout => img_in_data_stream_1_dout,
if_empty_n => img_in_data_stream_1_empty_n,
if_read => Resize_U0_p_src_data_stream_1_V_read);
img_in_data_stream_2_U : component fifo_w8_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => AXIvideo2Mat_U0_img_data_stream_2_V_din,
if_full_n => img_in_data_stream_2_full_n,
if_write => AXIvideo2Mat_U0_img_data_stream_2_V_write,
if_dout => img_in_data_stream_2_dout,
if_empty_n => img_in_data_stream_2_empty_n,
if_read => Resize_U0_p_src_data_stream_2_V_read);
img_in_rows_V_c13_U : component fifo_w32_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => AXIvideo2Mat_U0_img_rows_V_out_din,
if_full_n => img_in_rows_V_c13_full_n,
if_write => AXIvideo2Mat_U0_img_rows_V_out_write,
if_dout => img_in_rows_V_c13_dout,
if_empty_n => img_in_rows_V_c13_empty_n,
if_read => Resize_U0_p_src_rows_V_read);
img_in_cols_V_c14_U : component fifo_w32_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => AXIvideo2Mat_U0_img_cols_V_out_din,
if_full_n => img_in_cols_V_c14_full_n,
if_write => AXIvideo2Mat_U0_img_cols_V_out_write,
if_dout => img_in_cols_V_c14_dout,
if_empty_n => img_in_cols_V_c14_empty_n,
if_read => Resize_U0_p_src_cols_V_read);
img_out_data_stream_s_U : component fifo_w8_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Resize_U0_p_dst_data_stream_0_V_din,
if_full_n => img_out_data_stream_s_full_n,
if_write => Resize_U0_p_dst_data_stream_0_V_write,
if_dout => img_out_data_stream_s_dout,
if_empty_n => img_out_data_stream_s_empty_n,
if_read => Mat2AXIvideo_U0_img_data_stream_0_V_read);
img_out_data_stream_1_U : component fifo_w8_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Resize_U0_p_dst_data_stream_1_V_din,
if_full_n => img_out_data_stream_1_full_n,
if_write => Resize_U0_p_dst_data_stream_1_V_write,
if_dout => img_out_data_stream_1_dout,
if_empty_n => img_out_data_stream_1_empty_n,
if_read => Mat2AXIvideo_U0_img_data_stream_1_V_read);
img_out_data_stream_2_U : component fifo_w8_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Resize_U0_p_dst_data_stream_2_V_din,
if_full_n => img_out_data_stream_2_full_n,
if_write => Resize_U0_p_dst_data_stream_2_V_write,
if_dout => img_out_data_stream_2_dout,
if_empty_n => img_out_data_stream_2_empty_n,
if_read => Mat2AXIvideo_U0_img_data_stream_2_V_read);
img_out_rows_V_c15_U : component fifo_w32_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Resize_U0_p_dst_rows_V_out_din,
if_full_n => img_out_rows_V_c15_full_n,
if_write => Resize_U0_p_dst_rows_V_out_write,
if_dout => img_out_rows_V_c15_dout,
if_empty_n => img_out_rows_V_c15_empty_n,
if_read => Mat2AXIvideo_U0_img_rows_V_read);
img_out_cols_V_c16_U : component fifo_w32_d2_A
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Resize_U0_p_dst_cols_V_out_din,
if_full_n => img_out_cols_V_c16_full_n,
if_write => Resize_U0_p_dst_cols_V_out_write,
if_dout => img_out_cols_V_c16_dout,
if_empty_n => img_out_cols_V_c16_empty_n,
if_read => Mat2AXIvideo_U0_img_cols_V_read);
start_for_Resize_U0_U : component start_for_Resize_U0
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => start_for_Resize_U0_din,
if_full_n => start_for_Resize_U0_full_n,
if_write => Block_Mat_exit45_pro_U0_start_write,
if_dout => start_for_Resize_U0_dout,
if_empty_n => start_for_Resize_U0_empty_n,
if_read => Resize_U0_ap_ready);
start_for_Mat2AXImb6_U : component start_for_Mat2AXImb6
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => start_for_Mat2AXIvideo_U0_din,
if_full_n => start_for_Mat2AXIvideo_U0_full_n,
if_write => Resize_U0_start_write,
if_dout => start_for_Mat2AXIvideo_U0_dout,
if_empty_n => start_for_Mat2AXIvideo_U0_empty_n,
if_read => Mat2AXIvideo_U0_ap_ready);
ap_sync_reg_AXIvideo2Mat_U0_ap_ready_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_sync_reg_AXIvideo2Mat_U0_ap_ready <= ap_const_logic_0;
else
if (((ap_sync_ready and ap_start) = ap_const_logic_1)) then
ap_sync_reg_AXIvideo2Mat_U0_ap_ready <= ap_const_logic_0;
else
ap_sync_reg_AXIvideo2Mat_U0_ap_ready <= ap_sync_AXIvideo2Mat_U0_ap_ready;
end if;
end if;
end if;
end process;
ap_sync_reg_Block_Mat_exit45_pro_U0_ap_ready_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_sync_reg_Block_Mat_exit45_pro_U0_ap_ready <= ap_const_logic_0;
else
if (((ap_sync_ready and ap_start) = ap_const_logic_1)) then
ap_sync_reg_Block_Mat_exit45_pro_U0_ap_ready <= ap_const_logic_0;
else
ap_sync_reg_Block_Mat_exit45_pro_U0_ap_ready <= ap_sync_Block_Mat_exit45_pro_U0_ap_ready;
end if;
end if;
end if;
end process;
AXIvideo2Mat_U0_ap_ready_count_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_0 = AXIvideo2Mat_U0_ap_ready) and (ap_sync_ready = ap_const_logic_1))) then
AXIvideo2Mat_U0_ap_ready_count <= std_logic_vector(unsigned(AXIvideo2Mat_U0_ap_ready_count) - unsigned(ap_const_lv2_1));
elsif (((ap_const_logic_1 = AXIvideo2Mat_U0_ap_ready) and (ap_sync_ready = ap_const_logic_0))) then
AXIvideo2Mat_U0_ap_ready_count <= std_logic_vector(unsigned(AXIvideo2Mat_U0_ap_ready_count) + unsigned(ap_const_lv2_1));
end if;
end if;
end process;
Block_Mat_exit45_pro_U0_ap_ready_count_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_0 = Block_Mat_exit45_pro_U0_ap_ready) and (ap_sync_ready = ap_const_logic_1))) then
Block_Mat_exit45_pro_U0_ap_ready_count <= std_logic_vector(unsigned(Block_Mat_exit45_pro_U0_ap_ready_count) - unsigned(ap_const_lv2_1));
elsif (((ap_const_logic_1 = Block_Mat_exit45_pro_U0_ap_ready) and (ap_sync_ready = ap_const_logic_0))) then
Block_Mat_exit45_pro_U0_ap_ready_count <= std_logic_vector(unsigned(Block_Mat_exit45_pro_U0_ap_ready_count) + unsigned(ap_const_lv2_1));
end if;
end if;
end process;
AXIvideo2Mat_U0_ap_continue <= ap_const_logic_1;
AXIvideo2Mat_U0_ap_start <= ((ap_sync_reg_AXIvideo2Mat_U0_ap_ready xor ap_const_logic_1) and ap_start);
AXIvideo2Mat_U0_start_full_n <= ap_const_logic_1;
AXIvideo2Mat_U0_start_write <= ap_const_logic_0;
Block_Mat_exit45_pro_U0_ap_continue <= ap_const_logic_1;
Block_Mat_exit45_pro_U0_ap_start <= ((ap_sync_reg_Block_Mat_exit45_pro_U0_ap_ready xor ap_const_logic_1) and ap_start);
Mat2AXIvideo_U0_ap_continue <= ap_const_logic_1;
Mat2AXIvideo_U0_ap_start <= start_for_Mat2AXIvideo_U0_empty_n;
Mat2AXIvideo_U0_start_full_n <= ap_const_logic_1;
Mat2AXIvideo_U0_start_write <= ap_const_logic_0;
Resize_U0_ap_continue <= ap_const_logic_1;
Resize_U0_ap_start <= start_for_Resize_U0_empty_n;
ap_done <= Mat2AXIvideo_U0_ap_done;
ap_idle <= (Resize_U0_ap_idle and Mat2AXIvideo_U0_ap_idle and Block_Mat_exit45_pro_U0_ap_idle and AXIvideo2Mat_U0_ap_idle);
ap_ready <= ap_sync_ready;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
ap_sync_AXIvideo2Mat_U0_ap_ready <= (ap_sync_reg_AXIvideo2Mat_U0_ap_ready or AXIvideo2Mat_U0_ap_ready);
ap_sync_Block_Mat_exit45_pro_U0_ap_ready <= (ap_sync_reg_Block_Mat_exit45_pro_U0_ap_ready or Block_Mat_exit45_pro_U0_ap_ready);
ap_sync_continue <= ap_const_logic_1;
ap_sync_done <= Mat2AXIvideo_U0_ap_done;
ap_sync_ready <= (ap_sync_Block_Mat_exit45_pro_U0_ap_ready and ap_sync_AXIvideo2Mat_U0_ap_ready);
start_for_Mat2AXIvideo_U0_din <= (0=>ap_const_logic_1, others=>'-');
start_for_Resize_U0_din <= (0=>ap_const_logic_1, others=>'-');
stream_in_TREADY <= AXIvideo2Mat_U0_stream_in_TREADY;
stream_out_TDATA <= Mat2AXIvideo_U0_stream_out_TDATA;
stream_out_TDEST <= Mat2AXIvideo_U0_stream_out_TDEST;
stream_out_TID <= Mat2AXIvideo_U0_stream_out_TID;
stream_out_TKEEP <= Mat2AXIvideo_U0_stream_out_TKEEP;
stream_out_TLAST <= Mat2AXIvideo_U0_stream_out_TLAST;
stream_out_TSTRB <= Mat2AXIvideo_U0_stream_out_TSTRB;
stream_out_TUSER <= Mat2AXIvideo_U0_stream_out_TUSER;
stream_out_TVALID <= Mat2AXIvideo_U0_stream_out_TVALID;
end behav;
|
mit
|
67cc7be831ece0c8a65c4c6804117645
| 0.612341 | 2.746587 | false | false | false | false |
Digilent/vivado-library
|
ip/Zmods/ZmodScopeController/tb/CalibDataReference.vhd
| 2 | 9,370 |
-------------------------------------------------------------------------------
--
-- File: CalibDataReference.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module generates the reference output data for the GainOffsetCaib module.
-- It is supposed to run in parallel with the GainOffsetCaib module as part of
-- the test bench and share the same inputs. Malfunctions of the GainOffsetCaib
-- can be detected by comparing its output with the output of this module.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
use IEEE.numeric_std.all;
entity CalibDataReference is
Generic (
-- ADC/DAC number of bits
kWidth : integer range 10 to 16 := 14;
-- ADC/DAC dynamic/static calibration
kExtCalibEn : boolean := true;
-- Channel1 low gain multiplicative (gain) compensation coefficient parameter
kLgMultCoefStatic : std_logic_vector (17 downto 0) := "010000000000000000";
-- Channel1 low gain additive (offset) compensation coefficient parameter
kLgAddCoefStatic : std_logic_vector (17 downto 0) := "000000000000000000";
-- Channel1 high gain multiplicative (gain) compensation coefficient parameter
kHgMultCoefStatic : std_logic_vector (17 downto 0) := "010000000000000000";
-- Channel1 high gain additive (offset) compensation coefficient parameter
kHgAddCoefStatic : std_logic_vector (17 downto 0) := "000000000000000000";
-- Invert input data sign
kInvert : boolean := false;
-- Calibration stage latency
kLatency : integer := 2;
-- Calibration stage latency in test mode; Must be > 1 and < kLatency
-- The GainOffsetCaib module has different latencies in test mode
-- and in normal operation.
kTestLatency : integer := 1
);
Port (
-- Sampling clock
SamplingClk : in STD_LOGIC;
-- cTestMode is used to bypass the calibration block. When this signal
-- is asserted, raw samples are provided on the output data port.
cTestMode : in STD_LOGIC;
-- Data input port
cChIn : in STD_LOGIC_VECTOR (kWidth-1 downto 0);
-- Data output port
cChOut : out STD_LOGIC_VECTOR (kWidth-1 downto 0);
--Channel1 low gain gain compensation coefficient external port
cExtLgMultCoef : in std_logic_vector (17 downto 0);
--Channel1 low gain offset compensation coefficient external port
cExtLgAddCoef : in std_logic_vector (17 downto 0);
--Channel1 high gain gain compensation coefficient external port
cExtHgMultCoef : in std_logic_vector (17 downto 0);
--Channel1 high gain offset compensation coefficient external port;
cExtHgAddCoef : in std_logic_vector (17 downto 0);
-- Gain Relay State (1 -> High Gain; 0 -> Low Gain)
cGainState : in std_logic
);
end CalibDataReference;
architecture Behavioral of CalibDataReference is
signal cLgCoefAdd, cHgCoefAdd, cLgCoefMult, cHgCoefMult : signed (17 downto 0);
signal cLgMult, cHgMult : signed (35 downto 0) := (others => '0');
signal cChOutAux : std_logic_vector (kWidth-1 downto 0);
type ADC_ChArray_t is array (kLatency-1 downto 0) of std_logic_vector(kWidth-1 downto 0);
signal cChInDelayed : ADC_ChArray_t := (others => (others => '0'));
signal cLgCoefAddReal : real;
signal cHgCoefAddReal : real;
signal cLgCoefMultReal : real;
signal cHgCoefMultReal : real;
signal cChOutReal : real;
signal cChInReal : real;
signal cChInSigned : signed (kWidth-1 downto 0);
signal sChOutSigned : signed (kWidth-1 downto 0);
constant kTwoPow17 : real := 2.0**17.0;
constant kTwoPow16 : real := 2.0**16.0;
constant kTwoPowNadc : real := 2.0**real((kWidth-1));
-- Constants representing the minimum (negative) value and the maximum
-- (positive) value that cChIn can take. If inversion is requested by
-- setting kInvert to "true", in case cChIn = kValMin, the inversion
-- can't be performed directly on kWidth. The output of the inversion
-- needs to be forced to kValMax.
constant kValMin : std_logic_vector (15 downto 0) := x"8000";
constant kValMax : std_logic_vector (15 downto 0) := x"7FFF";
begin
-- Determine the value of the gain and offset calibration coefficients
-- based on the static/dynamic configuration option (kExtCalibEn).
cLgCoefAdd <= signed(kLgAddCoefStatic) when kExtCalibEn = false
else signed(cExtLgAddCoef);
cHgCoefAdd <= signed(kHgAddCoefStatic) when kExtCalibEn = false
else signed(cExtHgAddCoef);
cLgCoefMult <= signed(kLgMultCoefStatic) when kExtCalibEn = false
else signed(cExtLgMultCoef);
cHgCoefMult <= signed(kHgMultCoefStatic) when kExtCalibEn = false
else signed(cExtHgMultCoef);
-- The necessity of these operations is explained in the IP's
-- documentation.
cLgCoefAddReal <= Real(to_integer(cLgCoefAdd))/kTwoPow17;
cHgCoefAddReal <= Real(to_integer(cHgCoefAdd))/kTwoPow17;
cLgCoefMultReal <= Real(to_integer(cLgCoefMult))/kTwoPow16;
cHgCoefMultReal <= Real(to_integer(cHgCoefMult))/kTwoPow16;
-- Invert raw data input if the analog channel is inverted at the
-- ADC/DAC input. Inversion of the minimum negative value (-2^kWidth)
-- needs to be done explicitly.
ProcInvert : process (cChIn)
begin
if (kInvert = false) then
-- For the inverted channel, because the inversion is done at the FPGA
-- level, the minimum negative value is -2^kWidth+1. For symmetry
-- reasons the non inverted channel also limits the minimum negative value
-- at -2^kWidth+1.
if (cChIn = kValMin(15 downto 16-kWidth)) then
cChInSigned <= signed(kValMax(15 downto 16-kWidth))+1;
else
cChInSigned <= signed(cChIn);
end if;
else
if (cChIn = kValMin(15 downto 16-kWidth)) then
cChInSigned <= signed(kValMax(15 downto 16-kWidth));
else
cChInSigned <= - signed (cChIn);
end if;
end if;
end process;
cChInReal <= Real(to_integer(cChInSigned));
-- Apply the offset and gain coefficients to the input samples.
cChOutReal <= (cChInReal*cLgCoefMultReal+cLgCoefAddReal*kTwoPowNadc) when (cGainState = '0')
else (cChInReal*cHgCoefMultReal+cHgCoefAddReal*kTwoPowNadc);
-- Saturate output.
ProcCalib : process (cChOutReal)
begin
if (cChOutReal > (kTwoPowNadc-1.0)) then
sChOutSigned <= to_signed(integer(kTwoPowNadc-1.0),kWidth);
elsif (cChOutReal < (-kTwoPowNadc)) then
sChOutSigned <= to_signed(integer(-kTwoPowNadc),kWidth);
else
sChOutSigned <= to_signed(integer(cChOutReal),kWidth);
end if;
end process;
-- Bypass the calibration process if the cTestMode signal is asserted.
cChOutAux <= std_logic_vector (sChOutSigned) when (cTestMode = '0') else cChIn;
-- Simulate the GainOffsetCaib module latency.
ProcDelay : process (SamplingClk)
begin
if (rising_edge(SamplingClk)) then
cChInDelayed(0) <= cChOutAux;
for Index in 1 to (kLatency-1) loop
cChInDelayed (Index) <= cChInDelayed (Index - 1);
end loop;
end if;
end process;
ProcOutput : process (cChInDelayed)
begin
if (cTestMode = '0') then
cChOut <= cChInDelayed(kLatency-1);
else
cChOut <= cChInDelayed(kTestLatency-1);
end if;
end process;
end Behavioral;
|
mit
|
87ba99867bdd2d857206ba2c309f9bf1
| 0.683458 | 4.528758 | false | false | false | false |
JL-Grande/Ascensor_SED
|
ASCENSOR/tb_decoder.vhd
| 1 | 1,746 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_decoder IS
END tb_decoder;
ARCHITECTURE behavior OF tb_decoder IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT decoder
PORT(
CLK : IN std_logic;
RST : IN std_logic;
code : IN std_logic_vector(1 DOWNTO 0);
action : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
led : OUT std_logic_vector(6 DOWNTO 0);
dig_ctrl : OUT std_logic_vector(3 DOWNTO 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
signal code : std_logic_vector(1 downto 0) := (others => '0');
signal action: std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal led : std_logic_vector(6 downto 0);
signal dig_ctrl : std_logic_vector(3 downto 0);
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: decoder PORT MAP (
CLK => CLK,
RST => RST,
code => code,
action => action,
led => led,
dig_ctrl => dig_ctrl
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- insert stimulus here
RST <= '0';
code <= "00";
action <="00";
WAIT FOR 20 ns;
code <= "01";
action <="01";
WAIT FOR 20 ns;
RST <= '1';
code <= "10";
action <="10";
WAIT FOR 20 ns;
code <= "11";
action <="11";
WAIT FOR 20 ns;
RST <= '0';
code <= "01";
action <="01";
WAIT FOR 20 ns;
ASSERT false
REPORT "Simulación finalizada. Test superado."
SEVERITY FAILURE;
end process;
END;
|
gpl-3.0
|
b0d85381047bdc22245eb8bbbd336050
| 0.584765 | 3.21547 | false | false | false | false |
rickyzhangNYC/Pipelined_Multimedia_Cell_Lite_Unit
|
register_file_control.vhd
| 1 | 1,725 |
-------------------------------------------------------------------------------
--
-- Title : register_file_control
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\register_file_control.vhd
-- Generated : Wed Dec 7 01:59:37 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {register_file_control} architecture {behavioral}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
entity register_file_control is
port(
op_code : in std_logic_vector(3 downto 0);
rd, rs1, rs2 : in std_logic_vector(3 downto 0);
load_enable : out std_logic;
load_addr : out std_logic_vector(3 downto 0)
);
end register_file_control;
architecture behavioral of register_file_control is
begin
process(op_code, rs1, rs2, rd)
variable load_enable_v : std_logic := '0';
variable load_addr_v : std_logic_vector(3 downto 0);
variable load_data_v: std_logic_vector (11 downto 4);
begin
--load logic implementation
if op_code = "0001" then
load_enable_v := '1';
load_addr_v := rd;
else
load_enable_v := '0';
end if;
load_enable <= load_enable_v;
load_addr <= load_addr_v;
end process;
end behavioral;
|
apache-2.0
|
013f60c328a2c20e1367f260ac44a3e6
| 0.506087 | 3.685897 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_contrast_stretch_1_0/hdl/vhdl/CvtColor.vhd
| 1 | 54,272 |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CvtColor is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_src_rows_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
p_src_rows_V_empty_n : IN STD_LOGIC;
p_src_rows_V_read : OUT STD_LOGIC;
p_src_cols_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
p_src_cols_V_empty_n : IN STD_LOGIC;
p_src_cols_V_read : OUT STD_LOGIC;
p_src_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_0_V_empty_n : IN STD_LOGIC;
p_src_data_stream_0_V_read : OUT STD_LOGIC;
p_src_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_1_V_empty_n : IN STD_LOGIC;
p_src_data_stream_1_V_read : OUT STD_LOGIC;
p_src_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
p_src_data_stream_2_V_empty_n : IN STD_LOGIC;
p_src_data_stream_2_V_read : OUT STD_LOGIC;
p_dst_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_0_V_full_n : IN STD_LOGIC;
p_dst_data_stream_0_V_write : OUT STD_LOGIC;
p_dst_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_1_V_full_n : IN STD_LOGIC;
p_dst_data_stream_1_V_write : OUT STD_LOGIC;
p_dst_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
p_dst_data_stream_2_V_full_n : IN STD_LOGIC;
p_dst_data_stream_2_V_write : OUT STD_LOGIC );
end;
architecture behav of CvtColor is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
constant ap_const_lv8_80 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_lv22_0 : STD_LOGIC_VECTOR (21 downto 0) := "0000000000000000000000";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv32_59CAC0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000010110011100101011000000";
constant ap_const_lv30_3FE9FBE7 : STD_LOGIC_VECTOR (29 downto 0) := "111111111010011111101111100111";
constant ap_const_lv32_7178D4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000011100010111100011010100";
constant ap_const_lv31_7FD24DD2 : STD_LOGIC_VECTOR (30 downto 0) := "1111111110100100100110111010010";
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal p_src_rows_V_blk_n : STD_LOGIC;
signal p_src_cols_V_blk_n : STD_LOGIC;
signal p_src_data_stream_0_V_blk_n : STD_LOGIC;
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_block_pp0_stage0 : BOOLEAN;
signal tmp_35_i_reg_775 : STD_LOGIC_VECTOR (0 downto 0);
signal p_src_data_stream_1_V_blk_n : STD_LOGIC;
signal p_src_data_stream_2_V_blk_n : STD_LOGIC;
signal p_dst_data_stream_0_V_blk_n : STD_LOGIC;
signal ap_enable_reg_pp0_iter5 : STD_LOGIC := '0';
signal ap_reg_pp0_iter4_tmp_35_i_reg_775 : STD_LOGIC_VECTOR (0 downto 0);
signal p_dst_data_stream_1_V_blk_n : STD_LOGIC;
signal p_dst_data_stream_2_V_blk_n : STD_LOGIC;
signal j_i_reg_174 : STD_LOGIC_VECTOR (10 downto 0);
signal p_src_cols_V_read_reg_756 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_block_state1 : BOOLEAN;
signal p_src_rows_V_read_reg_761 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_i_fu_189_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal i_fu_194_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal i_reg_770 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_35_i_fu_204_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state5_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_state6_pp0_stage0_iter3 : BOOLEAN;
signal ap_block_state7_pp0_stage0_iter4 : BOOLEAN;
signal ap_block_state8_pp0_stage0_iter5 : BOOLEAN;
signal ap_block_pp0_stage0_11001 : BOOLEAN;
signal ap_reg_pp0_iter1_tmp_35_i_reg_775 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter2_tmp_35_i_reg_775 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter3_tmp_35_i_reg_775 : STD_LOGIC_VECTOR (0 downto 0);
signal j_fu_209_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal tmp_39_reg_784 : STD_LOGIC_VECTOR (7 downto 0);
signal i_op_assign_fu_215_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal i_op_assign_reg_789 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_i_op_assign_reg_789 : STD_LOGIC_VECTOR (7 downto 0);
signal i_op_assign_2_fu_221_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal i_op_assign_2_reg_795 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_713_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal r_V_reg_801 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal signbit_reg_806 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter3_signbit_reg_806 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_2_reg_813 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_reg_818 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_reg_823 : STD_LOGIC_VECTOR (1 downto 0);
signal grp_fu_725_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp2_reg_829 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_733_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal r_V_5_reg_834 : STD_LOGIC_VECTOR (31 downto 0);
signal signbit_3_reg_839 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter3_signbit_3_reg_839 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_30_reg_846 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_33_reg_851 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_reg_856 : STD_LOGIC_VECTOR (1 downto 0);
signal p_Val2_3_fu_324_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Val2_3_reg_862 : STD_LOGIC_VECTOR (7 downto 0);
signal p_38_i_i_i1_i_fu_367_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_38_i_i_i1_i_reg_868 : STD_LOGIC_VECTOR (0 downto 0);
signal p_39_demorgan_i_i_i2_s_fu_373_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_39_demorgan_i_i_i2_s_reg_874 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_745_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal r_V_4_reg_880 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
signal signbit_2_reg_885 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter4_signbit_2_reg_885 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_7_reg_892 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_29_reg_897 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_reg_902 : STD_LOGIC_VECTOR (1 downto 0);
signal p_Val2_31_fu_420_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Val2_31_reg_908 : STD_LOGIC_VECTOR (7 downto 0);
signal p_38_i_i_i21_i_fu_463_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_38_i_i_i21_i_reg_914 : STD_LOGIC_VECTOR (0 downto 0);
signal p_39_demorgan_i_i_i_fu_469_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_39_demorgan_i_i_i_reg_920 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_33_fu_524_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Val2_33_reg_926 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Val2_8_fu_542_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Val2_8_reg_931 : STD_LOGIC_VECTOR (7 downto 0);
signal p_38_i_i_i_i_fu_585_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_38_i_i_i_i_reg_937 : STD_LOGIC_VECTOR (0 downto 0);
signal p_39_demorgan_i_i_i_i_fu_591_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_39_demorgan_i_i_i_i_reg_943 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_s_fu_646_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Val2_s_reg_949 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_pp0_stage0_subdone : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC;
signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
signal i_i_reg_163 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_CS_fsm_state9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
signal ap_block_pp0_stage0_01001 : BOOLEAN;
signal i_cast_i_cast_fu_185_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal j_cast_i_cast_fu_200_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_i1_fu_230_p3 : STD_LOGIC_VECTOR (29 downto 0);
signal tmp_16_i_i_i_fu_314_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_27_fu_329_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_26_fu_317_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_17_i_i_i_fu_337_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal carry_fu_343_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal Range1_all_ones_fu_349_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal Range1_all_zeros_fu_354_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal deleted_zeros_fu_359_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_16_i_i12_i_fu_410_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_35_fu_425_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_34_fu_413_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_17_i_i16_i_fu_433_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal carry_2_fu_439_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal Range1_all_ones_2_fu_445_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal Range1_all_zeros_2_fu_450_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal deleted_zeros_2_fu_455_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_18_i_i_i_fu_474_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal signbit_not_i_i_fu_484_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal neg_src_not_i_i3_i_fu_489_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_39_demorgan_i_not_i_fu_499_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i_not_i_i4_fu_494_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal neg_src_9_fu_479_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i6_i_fu_504_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_mux_i_i7_i_fu_510_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_i_i8_i_fu_517_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_13_i_i_i_fu_532_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_31_fu_547_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_30_fu_535_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_14_i_i_i_fu_555_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal carry_1_fu_561_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal Range1_all_ones_1_fu_567_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal Range1_all_zeros_1_fu_572_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal deleted_zeros_1_fu_577_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_18_i_i22_i_fu_596_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal signbit_not_i25_i_fu_606_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal neg_src_not_i_i26_i_fu_611_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_39_demorgan_i_not_i_3_fu_621_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i_not_i_i2_fu_616_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal neg_src_fu_601_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i29_i_fu_626_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_mux_i_i30_i_fu_632_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_i_i31_i_fu_639_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_15_i_i_i_fu_654_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal signbit_not_i_fu_664_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal neg_src_not_i_i_i_fu_669_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_39_demorgan_i_not_i_2_fu_679_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i_not_i_i_s_fu_674_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal neg_src_10_fu_659_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal brmerge_i_i_i_fu_684_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_mux_i_i_i_fu_690_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_i_i_i_fu_697_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_713_p1 : STD_LOGIC_VECTOR (23 downto 0);
signal grp_fu_713_p2 : STD_LOGIC_VECTOR (29 downto 0);
signal tmp_22_cast_i_fu_237_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_725_p1 : STD_LOGIC_VECTOR (21 downto 0);
signal grp_fu_725_p2 : STD_LOGIC_VECTOR (29 downto 0);
signal grp_fu_733_p1 : STD_LOGIC_VECTOR (23 downto 0);
signal grp_fu_733_p2 : STD_LOGIC_VECTOR (29 downto 0);
signal grp_fu_745_p1 : STD_LOGIC_VECTOR (22 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
component hls_contrast_streg8j IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (7 downto 0);
din1 : IN STD_LOGIC_VECTOR (23 downto 0);
din2 : IN STD_LOGIC_VECTOR (29 downto 0);
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component hls_contrast_strehbi IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (7 downto 0);
din1 : IN STD_LOGIC_VECTOR (21 downto 0);
din2 : IN STD_LOGIC_VECTOR (29 downto 0);
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component hls_contrast_streibs IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (7 downto 0);
din1 : IN STD_LOGIC_VECTOR (22 downto 0);
din2 : IN STD_LOGIC_VECTOR (31 downto 0);
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
hls_contrast_streg8j_U60 : component hls_contrast_streg8j
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 8,
din1_WIDTH => 24,
din2_WIDTH => 30,
dout_WIDTH => 32)
port map (
din0 => i_op_assign_reg_789,
din1 => grp_fu_713_p1,
din2 => grp_fu_713_p2,
dout => grp_fu_713_p3);
hls_contrast_strehbi_U61 : component hls_contrast_strehbi
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 8,
din1_WIDTH => 22,
din2_WIDTH => 30,
dout_WIDTH => 32)
port map (
din0 => i_op_assign_2_reg_795,
din1 => grp_fu_725_p1,
din2 => grp_fu_725_p2,
dout => grp_fu_725_p3);
hls_contrast_streg8j_U62 : component hls_contrast_streg8j
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 8,
din1_WIDTH => 24,
din2_WIDTH => 30,
dout_WIDTH => 32)
port map (
din0 => i_op_assign_2_reg_795,
din1 => grp_fu_733_p1,
din2 => grp_fu_733_p2,
dout => grp_fu_733_p3);
hls_contrast_streibs_U63 : component hls_contrast_streibs
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 8,
din1_WIDTH => 23,
din2_WIDTH => 32,
dout_WIDTH => 32)
port map (
din0 => ap_reg_pp0_iter2_i_op_assign_reg_789,
din1 => grp_fu_745_p1,
din2 => tmp2_reg_829,
dout => grp_fu_745_p3);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_continue = ap_const_logic_1)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_189_p2 = ap_const_lv1_0))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((tmp_i_fu_189_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3)) then
ap_enable_reg_pp0_iter1 <= (ap_const_logic_1 xor ap_condition_pp0_exit_iter0_state3);
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end if;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
else
if ((ap_const_boolean_0 = ap_block_pp0_stage0_subdone)) then
ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
elsif (((tmp_i_fu_189_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
i_i_reg_163_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state9)) then
i_i_reg_163 <= i_reg_770;
elsif ((not(((ap_start = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
i_i_reg_163 <= ap_const_lv11_0;
end if;
end if;
end process;
j_i_reg_174_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_35_i_fu_204_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
j_i_reg_174 <= j_fu_209_p2;
elsif (((tmp_i_fu_189_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
j_i_reg_174 <= ap_const_lv11_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
ap_reg_pp0_iter1_tmp_35_i_reg_775 <= tmp_35_i_reg_775;
tmp_35_i_reg_775 <= tmp_35_i_fu_204_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_0 = ap_block_pp0_stage0_11001)) then
ap_reg_pp0_iter2_i_op_assign_reg_789 <= i_op_assign_reg_789;
ap_reg_pp0_iter2_tmp_35_i_reg_775 <= ap_reg_pp0_iter1_tmp_35_i_reg_775;
ap_reg_pp0_iter3_signbit_3_reg_839 <= signbit_3_reg_839;
ap_reg_pp0_iter3_signbit_reg_806 <= signbit_reg_806;
ap_reg_pp0_iter3_tmp_35_i_reg_775 <= ap_reg_pp0_iter2_tmp_35_i_reg_775;
ap_reg_pp0_iter4_signbit_2_reg_885 <= signbit_2_reg_885;
ap_reg_pp0_iter4_tmp_35_i_reg_775 <= ap_reg_pp0_iter3_tmp_35_i_reg_775;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_35_i_reg_775 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
i_op_assign_2_reg_795 <= i_op_assign_2_fu_221_p2;
i_op_assign_reg_789 <= i_op_assign_fu_215_p2;
tmp_39_reg_784 <= p_src_data_stream_0_V_dout;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
i_reg_770 <= i_fu_194_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter2_tmp_35_i_reg_775 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_38_i_i_i1_i_reg_868 <= p_38_i_i_i1_i_fu_367_p2;
p_38_i_i_i21_i_reg_914 <= p_38_i_i_i21_i_fu_463_p2;
p_39_demorgan_i_i_i2_s_reg_874 <= p_39_demorgan_i_i_i2_s_fu_373_p2;
p_39_demorgan_i_i_i_reg_920 <= p_39_demorgan_i_i_i_fu_469_p2;
p_Val2_31_reg_908 <= p_Val2_31_fu_420_p2;
p_Val2_3_reg_862 <= p_Val2_3_fu_324_p2;
p_Val2_7_reg_892 <= grp_fu_745_p3(29 downto 22);
signbit_2_reg_885 <= grp_fu_745_p3(31 downto 31);
tmp_29_reg_897 <= grp_fu_745_p3(21 downto 21);
tmp_5_reg_902 <= grp_fu_745_p3(31 downto 30);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter3_tmp_35_i_reg_775 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_38_i_i_i_i_reg_937 <= p_38_i_i_i_i_fu_585_p2;
p_39_demorgan_i_i_i_i_reg_943 <= p_39_demorgan_i_i_i_i_fu_591_p2;
p_Val2_33_reg_926 <= p_Val2_33_fu_524_p3;
p_Val2_8_reg_931 <= p_Val2_8_fu_542_p2;
p_Val2_s_reg_949 <= p_Val2_s_fu_646_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter1_tmp_35_i_reg_775 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_Val2_2_reg_813 <= grp_fu_713_p3(29 downto 22);
p_Val2_30_reg_846 <= grp_fu_733_p3(29 downto 22);
signbit_3_reg_839 <= grp_fu_733_p3(31 downto 31);
signbit_reg_806 <= grp_fu_713_p3(31 downto 31);
tmp_33_reg_851 <= grp_fu_733_p3(21 downto 21);
tmp_3_reg_823 <= grp_fu_713_p3(31 downto 30);
tmp_7_reg_856 <= grp_fu_733_p3(31 downto 30);
tmp_reg_818 <= grp_fu_713_p3(21 downto 21);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_start = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_src_cols_V_read_reg_756 <= p_src_cols_V_dout;
p_src_rows_V_read_reg_761 <= p_src_rows_V_dout;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter2_tmp_35_i_reg_775 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter3 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
r_V_4_reg_880 <= grp_fu_745_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter1_tmp_35_i_reg_775 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter2 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
r_V_5_reg_834 <= grp_fu_733_p3;
r_V_reg_801 <= grp_fu_713_p3;
tmp2_reg_829 <= grp_fu_725_p3;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, p_src_rows_V_empty_n, p_src_cols_V_empty_n, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter5, tmp_i_fu_189_p2, ap_CS_fsm_state2, tmp_35_i_fu_204_p2, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_subdone, ap_enable_reg_pp0_iter4)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if ((not(((ap_start = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_189_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage0 =>
if ((not(((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (tmp_35_i_fu_204_p2 = ap_const_lv1_0))) and not(((ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
elsif ((((ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1)) or ((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_const_boolean_0 = ap_block_pp0_stage0_subdone) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1) and (tmp_35_i_fu_204_p2 = ap_const_lv1_0)))) then
ap_NS_fsm <= ap_ST_fsm_state9;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_state9 =>
ap_NS_fsm <= ap_ST_fsm_state2;
when others =>
ap_NS_fsm <= "XXXX";
end case;
end process;
Range1_all_ones_1_fu_567_p2 <= "1" when (tmp_5_reg_902 = ap_const_lv2_3) else "0";
Range1_all_ones_2_fu_445_p2 <= "1" when (tmp_7_reg_856 = ap_const_lv2_3) else "0";
Range1_all_ones_fu_349_p2 <= "1" when (tmp_3_reg_823 = ap_const_lv2_3) else "0";
Range1_all_zeros_1_fu_572_p2 <= "1" when (tmp_5_reg_902 = ap_const_lv2_0) else "0";
Range1_all_zeros_2_fu_450_p2 <= "1" when (tmp_7_reg_856 = ap_const_lv2_0) else "0";
Range1_all_zeros_fu_354_p2 <= "1" when (tmp_3_reg_823 = ap_const_lv2_0) else "0";
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state9 <= ap_CS_fsm(3);
ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_01001_assign_proc : process(p_src_data_stream_0_V_empty_n, p_src_data_stream_1_V_empty_n, p_src_data_stream_2_V_empty_n, p_dst_data_stream_0_V_full_n, p_dst_data_stream_1_V_full_n, p_dst_data_stream_2_V_full_n, ap_enable_reg_pp0_iter1, tmp_35_i_reg_775, ap_enable_reg_pp0_iter5, ap_reg_pp0_iter4_tmp_35_i_reg_775)
begin
ap_block_pp0_stage0_01001 <= (((ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (((ap_reg_pp0_iter4_tmp_35_i_reg_775 = ap_const_lv1_1) and (p_dst_data_stream_2_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter4_tmp_35_i_reg_775 = ap_const_lv1_1) and (p_dst_data_stream_1_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter4_tmp_35_i_reg_775 = ap_const_lv1_1) and (p_dst_data_stream_0_V_full_n = ap_const_logic_0)))) or ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((tmp_35_i_reg_775 = ap_const_lv1_1) and (p_src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((tmp_35_i_reg_775 = ap_const_lv1_1) and (p_src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((tmp_35_i_reg_775 = ap_const_lv1_1) and (p_src_data_stream_0_V_empty_n = ap_const_logic_0)))));
end process;
ap_block_pp0_stage0_11001_assign_proc : process(p_src_data_stream_0_V_empty_n, p_src_data_stream_1_V_empty_n, p_src_data_stream_2_V_empty_n, p_dst_data_stream_0_V_full_n, p_dst_data_stream_1_V_full_n, p_dst_data_stream_2_V_full_n, ap_enable_reg_pp0_iter1, tmp_35_i_reg_775, ap_enable_reg_pp0_iter5, ap_reg_pp0_iter4_tmp_35_i_reg_775)
begin
ap_block_pp0_stage0_11001 <= (((ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (((ap_reg_pp0_iter4_tmp_35_i_reg_775 = ap_const_lv1_1) and (p_dst_data_stream_2_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter4_tmp_35_i_reg_775 = ap_const_lv1_1) and (p_dst_data_stream_1_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter4_tmp_35_i_reg_775 = ap_const_lv1_1) and (p_dst_data_stream_0_V_full_n = ap_const_logic_0)))) or ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((tmp_35_i_reg_775 = ap_const_lv1_1) and (p_src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((tmp_35_i_reg_775 = ap_const_lv1_1) and (p_src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((tmp_35_i_reg_775 = ap_const_lv1_1) and (p_src_data_stream_0_V_empty_n = ap_const_logic_0)))));
end process;
ap_block_pp0_stage0_subdone_assign_proc : process(p_src_data_stream_0_V_empty_n, p_src_data_stream_1_V_empty_n, p_src_data_stream_2_V_empty_n, p_dst_data_stream_0_V_full_n, p_dst_data_stream_1_V_full_n, p_dst_data_stream_2_V_full_n, ap_enable_reg_pp0_iter1, tmp_35_i_reg_775, ap_enable_reg_pp0_iter5, ap_reg_pp0_iter4_tmp_35_i_reg_775)
begin
ap_block_pp0_stage0_subdone <= (((ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (((ap_reg_pp0_iter4_tmp_35_i_reg_775 = ap_const_lv1_1) and (p_dst_data_stream_2_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter4_tmp_35_i_reg_775 = ap_const_lv1_1) and (p_dst_data_stream_1_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter4_tmp_35_i_reg_775 = ap_const_lv1_1) and (p_dst_data_stream_0_V_full_n = ap_const_logic_0)))) or ((ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (((tmp_35_i_reg_775 = ap_const_lv1_1) and (p_src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((tmp_35_i_reg_775 = ap_const_lv1_1) and (p_src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((tmp_35_i_reg_775 = ap_const_lv1_1) and (p_src_data_stream_0_V_empty_n = ap_const_logic_0)))));
end process;
ap_block_state1_assign_proc : process(ap_start, ap_done_reg, p_src_rows_V_empty_n, p_src_cols_V_empty_n)
begin
ap_block_state1 <= ((ap_start = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
ap_block_state3_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage0_iter1_assign_proc : process(p_src_data_stream_0_V_empty_n, p_src_data_stream_1_V_empty_n, p_src_data_stream_2_V_empty_n, tmp_35_i_reg_775)
begin
ap_block_state4_pp0_stage0_iter1 <= (((tmp_35_i_reg_775 = ap_const_lv1_1) and (p_src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((tmp_35_i_reg_775 = ap_const_lv1_1) and (p_src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((tmp_35_i_reg_775 = ap_const_lv1_1) and (p_src_data_stream_0_V_empty_n = ap_const_logic_0)));
end process;
ap_block_state5_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage0_iter5_assign_proc : process(p_dst_data_stream_0_V_full_n, p_dst_data_stream_1_V_full_n, p_dst_data_stream_2_V_full_n, ap_reg_pp0_iter4_tmp_35_i_reg_775)
begin
ap_block_state8_pp0_stage0_iter5 <= (((ap_reg_pp0_iter4_tmp_35_i_reg_775 = ap_const_lv1_1) and (p_dst_data_stream_2_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter4_tmp_35_i_reg_775 = ap_const_lv1_1) and (p_dst_data_stream_1_V_full_n = ap_const_logic_0)) or ((ap_reg_pp0_iter4_tmp_35_i_reg_775 = ap_const_lv1_1) and (p_dst_data_stream_0_V_full_n = ap_const_logic_0)));
end process;
ap_condition_pp0_exit_iter0_state3_assign_proc : process(tmp_35_i_fu_204_p2)
begin
if ((tmp_35_i_fu_204_p2 = ap_const_lv1_0)) then
ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_done_reg, tmp_i_fu_189_p2, ap_CS_fsm_state2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_189_p2 = ap_const_lv1_0))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4)
begin
if (((ap_enable_reg_pp0_iter5 = ap_const_logic_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (ap_enable_reg_pp0_iter4 = ap_const_logic_0) and (ap_enable_reg_pp0_iter3 = ap_const_logic_0) and (ap_enable_reg_pp0_iter2 = ap_const_logic_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(tmp_i_fu_189_p2, ap_CS_fsm_state2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_i_fu_189_p2 = ap_const_lv1_0))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
brmerge_i_i29_i_fu_626_p2 <= (p_39_demorgan_i_not_i_3_fu_621_p2 or neg_src_not_i_i26_i_fu_611_p2);
brmerge_i_i6_i_fu_504_p2 <= (p_39_demorgan_i_not_i_fu_499_p2 or neg_src_not_i_i3_i_fu_489_p2);
brmerge_i_i_i_fu_684_p2 <= (p_39_demorgan_i_not_i_2_fu_679_p2 or neg_src_not_i_i_i_fu_669_p2);
brmerge_i_i_not_i_i2_fu_616_p2 <= (p_39_demorgan_i_i_i_reg_920 and neg_src_not_i_i26_i_fu_611_p2);
brmerge_i_i_not_i_i4_fu_494_p2 <= (p_39_demorgan_i_i_i2_s_reg_874 and neg_src_not_i_i3_i_fu_489_p2);
brmerge_i_i_not_i_i_s_fu_674_p2 <= (p_39_demorgan_i_i_i_i_reg_943 and neg_src_not_i_i_i_fu_669_p2);
carry_1_fu_561_p2 <= (tmp_30_fu_535_p3 and tmp_14_i_i_i_fu_555_p2);
carry_2_fu_439_p2 <= (tmp_34_fu_413_p3 and tmp_17_i_i16_i_fu_433_p2);
carry_fu_343_p2 <= (tmp_26_fu_317_p3 and tmp_17_i_i_i_fu_337_p2);
deleted_zeros_1_fu_577_p3 <=
Range1_all_ones_1_fu_567_p2 when (carry_1_fu_561_p2(0) = '1') else
Range1_all_zeros_1_fu_572_p2;
deleted_zeros_2_fu_455_p3 <=
Range1_all_ones_2_fu_445_p2 when (carry_2_fu_439_p2(0) = '1') else
Range1_all_zeros_2_fu_450_p2;
deleted_zeros_fu_359_p3 <=
Range1_all_ones_fu_349_p2 when (carry_fu_343_p2(0) = '1') else
Range1_all_zeros_fu_354_p2;
grp_fu_713_p1 <= ap_const_lv32_59CAC0(24 - 1 downto 0);
grp_fu_713_p2 <= tmp_22_cast_i_fu_237_p1(30 - 1 downto 0);
grp_fu_725_p1 <= ap_const_lv30_3FE9FBE7(22 - 1 downto 0);
grp_fu_725_p2 <= tmp_22_cast_i_fu_237_p1(30 - 1 downto 0);
grp_fu_733_p1 <= ap_const_lv32_7178D4(24 - 1 downto 0);
grp_fu_733_p2 <= tmp_22_cast_i_fu_237_p1(30 - 1 downto 0);
grp_fu_745_p1 <= ap_const_lv31_7FD24DD2(23 - 1 downto 0);
i_cast_i_cast_fu_185_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_i_reg_163),16));
i_fu_194_p2 <= std_logic_vector(unsigned(i_i_reg_163) + unsigned(ap_const_lv11_1));
i_op_assign_2_fu_221_p2 <= (p_src_data_stream_2_V_dout xor ap_const_lv8_80);
i_op_assign_fu_215_p2 <= (p_src_data_stream_1_V_dout xor ap_const_lv8_80);
j_cast_i_cast_fu_200_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_i_reg_174),16));
j_fu_209_p2 <= std_logic_vector(unsigned(j_i_reg_174) + unsigned(ap_const_lv11_1));
neg_src_10_fu_659_p2 <= (tmp_15_i_i_i_fu_654_p2 and ap_reg_pp0_iter4_signbit_2_reg_885);
neg_src_9_fu_479_p2 <= (tmp_18_i_i_i_fu_474_p2 and ap_reg_pp0_iter3_signbit_reg_806);
neg_src_fu_601_p2 <= (tmp_18_i_i22_i_fu_596_p2 and ap_reg_pp0_iter3_signbit_3_reg_839);
neg_src_not_i_i26_i_fu_611_p2 <= (signbit_not_i25_i_fu_606_p2 or p_38_i_i_i21_i_reg_914);
neg_src_not_i_i3_i_fu_489_p2 <= (signbit_not_i_i_fu_484_p2 or p_38_i_i_i1_i_reg_868);
neg_src_not_i_i_i_fu_669_p2 <= (signbit_not_i_fu_664_p2 or p_38_i_i_i_i_reg_937);
p_38_i_i_i1_i_fu_367_p2 <= (carry_fu_343_p2 and Range1_all_ones_fu_349_p2);
p_38_i_i_i21_i_fu_463_p2 <= (carry_2_fu_439_p2 and Range1_all_ones_2_fu_445_p2);
p_38_i_i_i_i_fu_585_p2 <= (carry_1_fu_561_p2 and Range1_all_ones_1_fu_567_p2);
p_39_demorgan_i_i_i2_s_fu_373_p2 <= (signbit_reg_806 or deleted_zeros_fu_359_p3);
p_39_demorgan_i_i_i_fu_469_p2 <= (signbit_3_reg_839 or deleted_zeros_2_fu_455_p3);
p_39_demorgan_i_i_i_i_fu_591_p2 <= (signbit_2_reg_885 or deleted_zeros_1_fu_577_p3);
p_39_demorgan_i_not_i_2_fu_679_p2 <= (p_39_demorgan_i_i_i_i_reg_943 xor ap_const_lv1_1);
p_39_demorgan_i_not_i_3_fu_621_p2 <= (p_39_demorgan_i_i_i_reg_920 xor ap_const_lv1_1);
p_39_demorgan_i_not_i_fu_499_p2 <= (p_39_demorgan_i_i_i2_s_reg_874 xor ap_const_lv1_1);
p_Val2_31_fu_420_p2 <= std_logic_vector(unsigned(tmp_16_i_i12_i_fu_410_p1) + unsigned(p_Val2_30_reg_846));
p_Val2_33_fu_524_p3 <=
p_mux_i_i7_i_fu_510_p3 when (brmerge_i_i6_i_fu_504_p2(0) = '1') else
p_i_i8_i_fu_517_p3;
p_Val2_3_fu_324_p2 <= std_logic_vector(unsigned(tmp_16_i_i_i_fu_314_p1) + unsigned(p_Val2_2_reg_813));
p_Val2_8_fu_542_p2 <= std_logic_vector(unsigned(tmp_13_i_i_i_fu_532_p1) + unsigned(p_Val2_7_reg_892));
p_Val2_s_fu_646_p3 <=
p_mux_i_i30_i_fu_632_p3 when (brmerge_i_i29_i_fu_626_p2(0) = '1') else
p_i_i31_i_fu_639_p3;
p_dst_data_stream_0_V_blk_n_assign_proc : process(p_dst_data_stream_0_V_full_n, ap_block_pp0_stage0, ap_enable_reg_pp0_iter5, ap_reg_pp0_iter4_tmp_35_i_reg_775)
begin
if (((ap_reg_pp0_iter4_tmp_35_i_reg_775 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1))) then
p_dst_data_stream_0_V_blk_n <= p_dst_data_stream_0_V_full_n;
else
p_dst_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_dst_data_stream_0_V_din <= p_Val2_33_reg_926;
p_dst_data_stream_0_V_write_assign_proc : process(ap_enable_reg_pp0_iter5, ap_reg_pp0_iter4_tmp_35_i_reg_775, ap_block_pp0_stage0_11001)
begin
if (((ap_reg_pp0_iter4_tmp_35_i_reg_775 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_dst_data_stream_0_V_write <= ap_const_logic_1;
else
p_dst_data_stream_0_V_write <= ap_const_logic_0;
end if;
end process;
p_dst_data_stream_1_V_blk_n_assign_proc : process(p_dst_data_stream_1_V_full_n, ap_block_pp0_stage0, ap_enable_reg_pp0_iter5, ap_reg_pp0_iter4_tmp_35_i_reg_775)
begin
if (((ap_reg_pp0_iter4_tmp_35_i_reg_775 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1))) then
p_dst_data_stream_1_V_blk_n <= p_dst_data_stream_1_V_full_n;
else
p_dst_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_dst_data_stream_1_V_din <=
p_mux_i_i_i_fu_690_p3 when (brmerge_i_i_i_fu_684_p2(0) = '1') else
p_i_i_i_fu_697_p3;
p_dst_data_stream_1_V_write_assign_proc : process(ap_enable_reg_pp0_iter5, ap_reg_pp0_iter4_tmp_35_i_reg_775, ap_block_pp0_stage0_11001)
begin
if (((ap_reg_pp0_iter4_tmp_35_i_reg_775 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_dst_data_stream_1_V_write <= ap_const_logic_1;
else
p_dst_data_stream_1_V_write <= ap_const_logic_0;
end if;
end process;
p_dst_data_stream_2_V_blk_n_assign_proc : process(p_dst_data_stream_2_V_full_n, ap_block_pp0_stage0, ap_enable_reg_pp0_iter5, ap_reg_pp0_iter4_tmp_35_i_reg_775)
begin
if (((ap_reg_pp0_iter4_tmp_35_i_reg_775 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1))) then
p_dst_data_stream_2_V_blk_n <= p_dst_data_stream_2_V_full_n;
else
p_dst_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_dst_data_stream_2_V_din <= p_Val2_s_reg_949;
p_dst_data_stream_2_V_write_assign_proc : process(ap_enable_reg_pp0_iter5, ap_reg_pp0_iter4_tmp_35_i_reg_775, ap_block_pp0_stage0_11001)
begin
if (((ap_reg_pp0_iter4_tmp_35_i_reg_775 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter5 = ap_const_logic_1) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_dst_data_stream_2_V_write <= ap_const_logic_1;
else
p_dst_data_stream_2_V_write <= ap_const_logic_0;
end if;
end process;
p_i_i31_i_fu_639_p3 <=
ap_const_lv8_0 when (neg_src_fu_601_p2(0) = '1') else
p_Val2_31_reg_908;
p_i_i8_i_fu_517_p3 <=
ap_const_lv8_0 when (neg_src_9_fu_479_p2(0) = '1') else
p_Val2_3_reg_862;
p_i_i_i_fu_697_p3 <=
ap_const_lv8_0 when (neg_src_10_fu_659_p2(0) = '1') else
p_Val2_8_reg_931;
p_mux_i_i30_i_fu_632_p3 <=
p_Val2_31_reg_908 when (brmerge_i_i_not_i_i2_fu_616_p2(0) = '1') else
ap_const_lv8_FF;
p_mux_i_i7_i_fu_510_p3 <=
p_Val2_3_reg_862 when (brmerge_i_i_not_i_i4_fu_494_p2(0) = '1') else
ap_const_lv8_FF;
p_mux_i_i_i_fu_690_p3 <=
p_Val2_8_reg_931 when (brmerge_i_i_not_i_i_s_fu_674_p2(0) = '1') else
ap_const_lv8_FF;
p_src_cols_V_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_src_cols_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_src_cols_V_blk_n <= p_src_cols_V_empty_n;
else
p_src_cols_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_src_cols_V_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_src_rows_V_empty_n, p_src_cols_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_src_cols_V_read <= ap_const_logic_1;
else
p_src_cols_V_read <= ap_const_logic_0;
end if;
end process;
p_src_data_stream_0_V_blk_n_assign_proc : process(p_src_data_stream_0_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, tmp_35_i_reg_775)
begin
if (((tmp_35_i_reg_775 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
p_src_data_stream_0_V_blk_n <= p_src_data_stream_0_V_empty_n;
else
p_src_data_stream_0_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_src_data_stream_0_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_35_i_reg_775, ap_block_pp0_stage0_11001)
begin
if (((tmp_35_i_reg_775 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_src_data_stream_0_V_read <= ap_const_logic_1;
else
p_src_data_stream_0_V_read <= ap_const_logic_0;
end if;
end process;
p_src_data_stream_1_V_blk_n_assign_proc : process(p_src_data_stream_1_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, tmp_35_i_reg_775)
begin
if (((tmp_35_i_reg_775 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
p_src_data_stream_1_V_blk_n <= p_src_data_stream_1_V_empty_n;
else
p_src_data_stream_1_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_src_data_stream_1_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_35_i_reg_775, ap_block_pp0_stage0_11001)
begin
if (((tmp_35_i_reg_775 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_src_data_stream_1_V_read <= ap_const_logic_1;
else
p_src_data_stream_1_V_read <= ap_const_logic_0;
end if;
end process;
p_src_data_stream_2_V_blk_n_assign_proc : process(p_src_data_stream_2_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, tmp_35_i_reg_775)
begin
if (((tmp_35_i_reg_775 = ap_const_lv1_1) and (ap_const_boolean_0 = ap_block_pp0_stage0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
p_src_data_stream_2_V_blk_n <= p_src_data_stream_2_V_empty_n;
else
p_src_data_stream_2_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_src_data_stream_2_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_35_i_reg_775, ap_block_pp0_stage0_11001)
begin
if (((tmp_35_i_reg_775 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_0 = ap_block_pp0_stage0_11001))) then
p_src_data_stream_2_V_read <= ap_const_logic_1;
else
p_src_data_stream_2_V_read <= ap_const_logic_0;
end if;
end process;
p_src_rows_V_blk_n_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_src_rows_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_src_rows_V_blk_n <= p_src_rows_V_empty_n;
else
p_src_rows_V_blk_n <= ap_const_logic_1;
end if;
end process;
p_src_rows_V_read_assign_proc : process(ap_start, ap_done_reg, ap_CS_fsm_state1, p_src_rows_V_empty_n, p_src_cols_V_empty_n)
begin
if ((not(((ap_start = ap_const_logic_0) or (p_src_cols_V_empty_n = ap_const_logic_0) or (p_src_rows_V_empty_n = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
p_src_rows_V_read <= ap_const_logic_1;
else
p_src_rows_V_read <= ap_const_logic_0;
end if;
end process;
signbit_not_i25_i_fu_606_p2 <= (ap_reg_pp0_iter3_signbit_3_reg_839 xor ap_const_lv1_1);
signbit_not_i_fu_664_p2 <= (ap_reg_pp0_iter4_signbit_2_reg_885 xor ap_const_lv1_1);
signbit_not_i_i_fu_484_p2 <= (ap_reg_pp0_iter3_signbit_reg_806 xor ap_const_lv1_1);
tmp_13_i_i_i_fu_532_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_29_reg_897),8));
tmp_14_i_i_i_fu_555_p2 <= (tmp_31_fu_547_p3 xor ap_const_lv1_1);
tmp_15_i_i_i_fu_654_p2 <= (p_38_i_i_i_i_reg_937 xor ap_const_lv1_1);
tmp_16_i_i12_i_fu_410_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_33_reg_851),8));
tmp_16_i_i_i_fu_314_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_reg_818),8));
tmp_17_i_i16_i_fu_433_p2 <= (tmp_35_fu_425_p3 xor ap_const_lv1_1);
tmp_17_i_i_i_fu_337_p2 <= (tmp_27_fu_329_p3 xor ap_const_lv1_1);
tmp_18_i_i22_i_fu_596_p2 <= (p_38_i_i_i21_i_reg_914 xor ap_const_lv1_1);
tmp_18_i_i_i_fu_474_p2 <= (p_38_i_i_i1_i_reg_868 xor ap_const_lv1_1);
tmp_22_cast_i_fu_237_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_i1_fu_230_p3),32));
tmp_26_fu_317_p3 <= r_V_reg_801(29 downto 29);
tmp_27_fu_329_p3 <= p_Val2_3_fu_324_p2(7 downto 7);
tmp_30_fu_535_p3 <= r_V_4_reg_880(29 downto 29);
tmp_31_fu_547_p3 <= p_Val2_8_fu_542_p2(7 downto 7);
tmp_34_fu_413_p3 <= r_V_5_reg_834(29 downto 29);
tmp_35_fu_425_p3 <= p_Val2_31_fu_420_p2(7 downto 7);
tmp_35_i_fu_204_p2 <= "1" when (unsigned(j_cast_i_cast_fu_200_p1) < unsigned(p_src_cols_V_read_reg_756)) else "0";
tmp_i1_fu_230_p3 <= (tmp_39_reg_784 & ap_const_lv22_0);
tmp_i_fu_189_p2 <= "1" when (unsigned(i_cast_i_cast_fu_185_p1) < unsigned(p_src_rows_V_read_reg_761)) else "0";
end behav;
|
mit
|
14fd375c07c3ba70a6d0b659c90e5579
| 0.602631 | 2.521113 | false | false | false | false |
Digilent/vivado-library
|
ip/hls_gamma_correction_1_0/hdl/vhdl/hls_gamma_correction_AXILiteS_s_axi.vhd
| 1 | 9,283 |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity hls_gamma_correction_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
-- user signals
gamma :out STD_LOGIC_VECTOR(7 downto 0);
height :out STD_LOGIC_VECTOR(15 downto 0);
width :out STD_LOGIC_VECTOR(15 downto 0)
);
end entity hls_gamma_correction_AXILiteS_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : reserved
-- 0x04 : reserved
-- 0x08 : reserved
-- 0x0c : reserved
-- 0x10 : Data signal of gamma
-- bit 7~0 - gamma[7:0] (Read/Write)
-- others - reserved
-- 0x14 : reserved
-- 0x18 : Data signal of height
-- bit 15~0 - height[15:0] (Read/Write)
-- others - reserved
-- 0x1c : reserved
-- 0x20 : Data signal of width
-- bit 15~0 - width[15:0] (Read/Write)
-- others - reserved
-- 0x24 : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of hls_gamma_correction_AXILiteS_s_axi is
type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states
signal wstate : states := wrreset;
signal rstate : states := rdreset;
signal wnext, rnext: states;
constant ADDR_GAMMA_DATA_0 : INTEGER := 16#10#;
constant ADDR_GAMMA_CTRL : INTEGER := 16#14#;
constant ADDR_HEIGHT_DATA_0 : INTEGER := 16#18#;
constant ADDR_HEIGHT_CTRL : INTEGER := 16#1c#;
constant ADDR_WIDTH_DATA_0 : INTEGER := 16#20#;
constant ADDR_WIDTH_CTRL : INTEGER := 16#24#;
constant ADDR_BITS : INTEGER := 6;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_gamma : UNSIGNED(7 downto 0) := (others => '0');
signal int_height : UNSIGNED(15 downto 0) := (others => '0');
signal int_width : UNSIGNED(15 downto 0) := (others => '0');
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wrreset;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdreset;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_GAMMA_DATA_0 =>
rdata_data <= RESIZE(int_gamma(7 downto 0), 32);
when ADDR_HEIGHT_DATA_0 =>
rdata_data <= RESIZE(int_height(15 downto 0), 32);
when ADDR_WIDTH_DATA_0 =>
rdata_data <= RESIZE(int_width(15 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
gamma <= STD_LOGIC_VECTOR(int_gamma);
height <= STD_LOGIC_VECTOR(int_height);
width <= STD_LOGIC_VECTOR(int_width);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GAMMA_DATA_0) then
int_gamma(7 downto 0) <= (UNSIGNED(WDATA(7 downto 0)) and wmask(7 downto 0)) or ((not wmask(7 downto 0)) and int_gamma(7 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_HEIGHT_DATA_0) then
int_height(15 downto 0) <= (UNSIGNED(WDATA(15 downto 0)) and wmask(15 downto 0)) or ((not wmask(15 downto 0)) and int_height(15 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_WIDTH_DATA_0) then
int_width(15 downto 0) <= (UNSIGNED(WDATA(15 downto 0)) and wmask(15 downto 0)) or ((not wmask(15 downto 0)) and int_width(15 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
|
mit
|
ca26faa3218e880e2791289e05bdc369
| 0.473338 | 3.951894 | false | false | false | false |
JL-Grande/Ascensor_SED
|
ASCENSOR/tb_dec_flechas.vhd
| 1 | 1,214 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_dec_flechas IS
END tb_dec_flechas;
ARCHITECTURE behavior OF tb_dec_flechas IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT dec_flechas
PORT(
action : IN std_logic_vector(1 downto 0);
led_flechas : OUT std_logic_vector(6 downto 0);
flecha_ctrl : OUT std_logic
);
END COMPONENT;
--Inputs
signal action : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal led_flechas : std_logic_vector(6 downto 0);
signal flecha_ctrl : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: dec_flechas PORT MAP (
action => action,
led_flechas => led_flechas,
flecha_ctrl => flecha_ctrl
);
-- Stimulus process
stim_proc: process
begin
-- insert stimulus here
action <= "00";
WAIT FOR 20 ns;
action <= "01";
WAIT FOR 20 ns;
action <= "10";
WAIT FOR 20 ns;
action <= "11";
WAIT FOR 20 ns;
action <= "01";
WAIT FOR 20 ns;
ASSERT false
REPORT "Simulación finalizada. Test superado."
SEVERITY FAILURE;
wait;
end process;
END;
|
gpl-3.0
|
51fb16f1af989c819a849710493b6d3f
| 0.608731 | 3.518841 | false | true | false | false |
Digilent/vivado-library
|
module/synchronizers/HandshakeData.vhd
| 3 | 11,363 |
------------------------------------------------------------------------------
--
-- File: HandshakeData.vhd
-- Author: Elod Gyorgy
-- Original Project: Atlys2 User Demo
-- Date: 29 June 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module passes parallel data from the input clock domain (InClk) to the
-- output clock domain (OutClk) by the means of handshake signals. A
-- low-to-high transition on iPush will register iData inside the module
-- and will start propagating the handshake signals towards the output domain.
-- The data will appear on oData and is valid when oValid pulses high.
-- The reception of data by the receiver on the OutClk domain is signaled
-- by a pulse on oAck. This will propagate back to the input domain and
-- assert iRdy signaling to the sender that a new data can be pushed through.
-- If oData is always read when oValid pulses, oAck may be tied permanently
-- high.
-- Only assert iPush when iRdy is high!
-- aiReset and aoReset should be reset signals with asynchronous assertion
-- and synchronous de-assertion generated by the same reset source.
-- aiReset should be de-assertd synchronously with the InClk rising edge,
-- while aoReset should be de-assertd synchronously with the OutClk rising
-- edge.
-- Constraint Templates:
-- In the constraint templates below, please replace
-- <HandshakeData instantiation name> with the correct instantiation name of
-- the HandshakeData module.
-- This module needs the following types of constraints in the XDC file:
-- - For the SyncAsync modules inside this module, the path between the
-- input clock domain and output clock domain needs to not be analized:
-- set_false_path -through [get_pins -filter {NAME =~ *SyncAsync*/oSyncStages_reg[0]/D} -hier]
--
-- - Also for the SyncAsync modules, the path between the flip-flops in
-- the output clock domain needs to be overconstrained to half of the
-- output clock period, to leave the other half for metastability to
-- settle:
-- set ClkPeriod [get_property PERIOD [get_clocks -of_objects [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncAsyncPushTBack*/oSyncStages_reg[0]/C} -hier]]]
-- set_max_delay -from [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncAsyncPushTBack*/oSyncStages_reg[0]/C} -hier] -to [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncAsyncPushTBack*/oSyncStages_reg[1]/D} -hier] [expr {$ClkPeriod/2}]
-- set ClkPeriod [get_property PERIOD [get_clocks -of_objects [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncAsyncPushT/oSyncStages_reg[0]/C} -hier]]]
-- set_max_delay -from [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncAsyncPushT/oSyncStages_reg[0]/C} -hier] -to [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncAsyncPushT/oSyncStages_reg[1]/D} -hier] [expr {$ClkPeriod/2}]
--
-- - For the ResetBridge module inside this module, the path between the
-- flip-flops in the output clock domain needs to be overconstrained to
-- half of the output clock period, to leave the other half for
-- metastability to settle:
-- set ClkPeriod [get_property PERIOD [get_clocks -of_objects [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncReset*SyncAsync*/oSyncStages_reg[0]/C} -hier]]]
-- set_max_delay -from [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncReset*SyncAsync*/oSyncStages_reg[0]/C} -hier] -to [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncReset*SyncAsync*/oSyncStages_reg[1]/D} -hier] [expr {$ClkPeriod/2}]
--
-- - Also for the ResetBridge module, we need to disable timing analysis on
-- the reset paths, for both its edges. This is necessary because the
-- input reset of this module is considered to be fully asynchronous:
-- set_false_path -to [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*SyncReset*SyncAsync*/oSyncStages*/PRE || NAME =~ *<HandshakeData instantiation name>*SyncReset*SyncAsync*/oSyncStages*/CLR} -hier]
--
-- - For the data path between the input clock domain and the output clock
-- domain, the maximum delay needs to be set to 2 output clock cycles, so
-- the data sampled in the output clock domain is stable by the time
-- oPushTChanged is asserted.
-- set ClkPeriod [get_property PERIOD [get_clocks -of_objects [get_pins -filter {NAME =~ *<HandshakeData instantiation name>*/oData_reg[0]/C} -hier]]]
-- set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *<HandshakeData instantiation name>*/iData_int_reg[*]}] -to [get_cells -hier -filter {NAME=~ *<HandshakeData instantiation name>*/oData_reg[*]}] [expr {$ClkPeriod*2}]
-- Changelog:
-- 2016-Jun-29: Fixed oValid not being a pulse.
-- 2020-Dec-14: Changed the single asynchronous reset source (aReset)
-- with 2 RSD reset (asynchronous assertion, synchronous de-assertion)
-- reset sgnals (aiReset, aoReset).
-- 2022-Oct-03: Added direct_enable attribute to iPushRising and
-- oPushTChanged, to make sure both the InClk and OutClk data latching FFs
-- use actual clock enable (CE) pins.
-- 2022-Oct-04: Added Constraint Templates section to the header comments.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity HandshakeData is
Generic (
kDataWidth : natural := 8);
Port (
InClk : in STD_LOGIC;
OutClk : in STD_LOGIC;
iData : in STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
oData : out STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
iPush : in STD_LOGIC;
iRdy : out STD_LOGIC;
oAck : in STD_LOGIC := '1';
oValid : out STD_LOGIC;
aiReset : in std_logic;
aoReset : in std_logic);
end HandshakeData;
architecture Behavioral of HandshakeData is
signal iPush_q, iPushRising, iPushT, iPushTBack, iReset : std_logic;
signal iData_int : std_logic_vector(kDataWidth-1 downto 0);
signal oPushT, oPushT_q, oPushTBack, oPushTChanged : std_logic;
attribute DONT_TOUCH : string;
attribute DONT_TOUCH of aoReset: signal is "TRUE";
attribute direct_enable : string;
attribute direct_enable of iPushRising: signal is "yes";
attribute direct_enable of oPushTChanged: signal is "yes";
begin
DetectPush: process(aiReset, InClk)
begin
if (aiReset = '1') then
iPush_q <= '0';
elsif Rising_Edge(InClk) then
iPush_q <= iPush;
end if;
end process DetectPush;
iPushRising <= iPush and not iPush_q;
-- Register data when iPush is rising and toggle internal flag
LatchData: process(aiReset, InClk)
begin
if (aiReset = '1') then
iData_int <= (others => '0');
iPushT <= '0';
elsif Rising_Edge(InClk) then
if (iPushRising = '1') then
iData_int <= iData;
iPushT <= not iPushT;
end if;
end if;
end process;
-- Cross toggle flag through synchronizer
SyncAsyncPushT: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aoReset => aoReset,
aIn => iPushT,
OutClk => OutClk,
oOut => oPushT);
-- Detect a push edge in the OutClk domain
-- If receiver acknowledges receipt, we can propagate the push signal back
-- towards the input, where it will be used to generate iRdy
DetectToggle: process(aoReset, OutClk)
begin
if (aoReset = '1') then
oPushT_q <= '0';
oPushTBack <= '0';
elsif Rising_Edge(OutClk) then
oPushT_q <= oPushT;
if (oAck = '1') then
oPushTBack <= oPushT_q;
end if;
end if;
end process DetectToggle;
oPushTChanged <= '1' when oPushT_q /= oPushT else '0';
-- Cross data from InClk domain reg (iData_in) to OutClk domain
-- The enable for this register is the propagated and sync'd to the OutClk domain
-- We assume here that the time it took iPush to propagate to oPushTChanged is
-- more than the time it takes iData_int to propagate to the oData register's D pin
OutputData: process (aoReset, OutClk)
begin
if (aoReset = '1') then
oData <= (others => '0');
oValid <= '0';
elsif Rising_Edge(OutClk) then
if (oPushTChanged = '1') then
oData <= iData_int;
end if;
oValid <= oPushTChanged;
end if;
end process OutputData;
-- Cross toggle flag back through synchronizer
SyncAsyncPushTBack: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aoReset => aiReset,
aIn => oPushTBack,
OutClk => InClk,
oOut => iPushTBack);
-- Synchronize aoReset into the InClk domain
-- We need it to keep iRdy low, when aoReset de-asserts
SyncReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aoReset,
OutClk => InClk,
aoRst => iReset);
ReadySignal: process(aiReset, InClk)
begin
if (aiReset = '1') then
iRdy <= '0';
elsif Rising_Edge(InClk) then
iRdy <= not iPush and (iPushTBack xnor iPushT) and not iReset;
end if;
end process ReadySignal;
end Behavioral;
|
mit
|
7f1f5574cd890c66a98a0bb681ad3e5b
| 0.683358 | 4.20696 | false | false | false | false |
yanhongwang/HardwareDescriptionLanguagesDigitalSystemsDesign
|
binary_multiplier_16/binary_multiplier_16.vhd
| 1 | 2,367 |
-- Binary Multiplier with n = 4: VHDL Description
-- See Figures 8-6 and 8-7 for block diagram and ASM Chart
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity binary_multiplier is
port(CLK, RESET, G, LOADB, LOADQ: in std_logic;
MULT_IN: in std_logic_vector(15 downto 0);
MULT_OUT: out std_logic_vector(31 downto 0));
end binary_multiplier;
architecture behavior_16 of binary_multiplier is
type state_type is (IDLE, MUL0, MUL1);
signal state, next_state : state_type;
signal A, B, Q: std_logic_vector(15 downto 0);
signal P: std_logic_vector(3 downto 0);
signal C, Z: std_logic;
begin
Z <= not( P(3) OR P(2) OR P(1) OR P(0) );
MULT_OUT <= A & Q;
state_register: process (CLK, RESET)
begin
if (RESET = '1') then
state <= IDLE;
elsif (CLK'event and CLK = '1') then
state <= next_state;
end if;
end process;
next_state_func: process (G, Z, state)
begin
case state is
when IDLE =>
if G = '1' then
next_state <= MUL0;
else
next_state <= IDLE;
end if;
when MUL0 =>
next_state <= MUL1;
when MUL1 =>
if Z = '1' then
next_state <= IDLE;
else
next_state <= MUL0;
end if;
end case;
end process;
datapath_func: process (CLK)
variable CA: std_logic_vector(16 downto 0);
begin
if (CLK'event and CLK = '1') then
if LOADB = '1' then
B <= MULT_IN;
end if;
if LOADQ = '1' then
Q <= MULT_IN;
end if;
case state is
when IDLE =>
if G = '1' then
C <= '0';
A <= "0000000000000000";
P <= "1111";
end if;
when MUL0 =>
if Q(0) = '1' then
CA := ('0' & A) + ('0' & B);
else
CA := C & A;
end if;
C <= CA(16);
A <= CA(15 downto 0);
when MUL1 =>
C <= '0';
A <= C & A(15 downto 1);
Q <= A(0) & Q(15 downto 1);
P <= P - "0001";
end case;
end if;
end process;
end behavior_16;
|
mit
|
cf37658eabdb804650e76b58e27ea106
| 0.460499 | 3.630368 | false | false | false | false |
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