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nishtahir/arty-blaze
|
src/bd/system/ip/system_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/system_xadc_wiz_0_0_slave_attachment.vhd
| 1 | 22,383 |
-------------------------------------------------------------------------------
-- Slave Attachment - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: system_xadc_wiz_0_0_slave_attachment.vhd
-- Version: v1.01.a
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --system_xadc_wiz_0_0_axi_lite_ipif.vhd
-- --system_xadc_wiz_0_0_slave_attachment.vhd
-- --system_xadc_wiz_0_0_address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library work;
use work.system_xadc_wiz_0_0_proc_common_pkg.all;
use work.system_xadc_wiz_0_0_proc_common_pkg.max2;
use work.system_xadc_wiz_0_0_ipif_pkg.all;
use work.system_xadc_wiz_0_0_family_support.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- s_axi_aclk -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity system_xadc_wiz_0_0_slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity system_xadc_wiz_0_0_slave_attachment;
-------------------------------------------------------------------------------
architecture imp of system_xadc_wiz_0_0_slave_attachment is
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= s_axi_aclk;
Bus2IP_Resetn <= s_axi_aresetn;
bus2ip_rnw_i <= '1' when s_axi_arvalid='1'
else
'0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= s_axi_wstrb when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= s_axi_wdata;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
bus2ip_addr_i <= ZEROS & s_axi_araddr(C_ADDR_DECODE_BITS downto 0)
when (s_axi_arvalid='1')
else
ZEROS & s_axi_awaddr(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
start<= (s_axi_arvalid or (s_axi_awvalid and s_axi_wvalid))
when (state = SM_IDLE)
else
'0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or timeout;
wr_done <= IP2Bus_WrAck or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity work.system_xadc_wiz_0_0_address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => s_axi_aclk,
Bus_rst => s_axi_aresetn,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start,
Bus_RNW => s_axi_arvalid,
Bus_RNW_Erly => s_axi_arvalid,
CS_CE_ld_enable => start,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (s_axi_aclk) is
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
rst <= not s_axi_aresetn;
end if;
end process REGISTERING_RESET_P;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (s_axi_aclk) is
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if rst = '1' then
state <= SM_IDLE;
else
case state is
when SM_IDLE => if (s_axi_arvalid = '1') then -- Read precedence over write
state <= SM_READ;
elsif (s_axi_awvalid = '1' and s_axi_wvalid = '1') then
state <= SM_WRITE;
else
state <= SM_IDLE;
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and s_axi_bready) or
(s_axi_rvalid_i and s_axi_rready)) = '1' then
state <= SM_IDLE;
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (s_axi_aclk) is
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
s_axi_rresp <= s_axi_rresp_i;
s_axi_rdata <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (s_axi_aclk) is
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (s_axi_rready = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (s_axi_aclk) is
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
s_axi_bresp <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (s_axi_aclk) is
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (s_axi_bready = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (s_axi_aclk) is
begin
if (s_axi_aclk'event and s_axi_aclk = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= dpto_cnt(COUNTER_WIDTH);
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
s_axi_bvalid <= s_axi_bvalid_i;
s_axi_rvalid <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
s_axi_arready <= rd_done;
s_axi_awready <= wr_done;
s_axi_wready <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
apache-2.0
|
31eb5b64799ff458311652a1fcfa15c0
| 0.474154 | 4.089713 | false | false | false | false |
daniw/add
|
edk/IVK_HW/t01_hello/hdl/xps_timer_0_wrapper.vhd
| 1 | 7,218 |
-------------------------------------------------------------------------------
-- xps_timer_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_timer_v1_02_a;
use xps_timer_v1_02_a.all;
entity xps_timer_0_wrapper is
port (
CaptureTrig0 : in std_logic;
CaptureTrig1 : in std_logic;
GenerateOut0 : out std_logic;
GenerateOut1 : out std_logic;
PWM0 : out std_logic;
Interrupt : out std_logic;
Freeze : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 3);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrDBus : in std_logic_vector(0 to 31);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 31);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MWrErr : out std_logic_vector(0 to 1);
Sl_MRdErr : out std_logic_vector(0 to 1);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_MSize : in std_logic_vector(0 to 1);
PLB_lockErr : in std_logic;
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_wrBTerm : out std_logic;
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdBTerm : out std_logic;
Sl_MIRQ : out std_logic_vector(0 to 1)
);
attribute x_core_info : STRING;
attribute x_core_info of xps_timer_0_wrapper : entity is "xps_timer_v1_02_a";
end xps_timer_0_wrapper;
architecture STRUCTURE of xps_timer_0_wrapper is
component xps_timer is
generic (
C_FAMILY : STRING;
C_COUNT_WIDTH : INTEGER;
C_ONE_TIMER_ONLY : INTEGER;
C_TRIG0_ASSERT : std_logic;
C_TRIG1_ASSERT : std_logic;
C_GEN0_ASSERT : std_logic;
C_GEN1_ASSERT : std_logic;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_SPLB_AWIDTH : INTEGER;
C_SPLB_DWIDTH : INTEGER;
C_SPLB_P2P : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_SUPPORT_BURSTS : INTEGER;
C_SPLB_NATIVE_DWIDTH : INTEGER
);
port (
CaptureTrig0 : in std_logic;
CaptureTrig1 : in std_logic;
GenerateOut0 : out std_logic;
GenerateOut1 : out std_logic;
PWM0 : out std_logic;
Interrupt : out std_logic;
Freeze : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to C_SPLB_AWIDTH-1);
PLB_PAValid : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
PLB_UABus : in std_logic_vector(0 to C_SPLB_AWIDTH-1);
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_MSize : in std_logic_vector(0 to 1);
PLB_lockErr : in std_logic;
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_wrBTerm : out std_logic;
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdBTerm : out std_logic;
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1))
);
end component;
begin
xps_timer_0 : xps_timer
generic map (
C_FAMILY => "spartan6",
C_COUNT_WIDTH => 32,
C_ONE_TIMER_ONLY => 1,
C_TRIG0_ASSERT => '1',
C_TRIG1_ASSERT => '1',
C_GEN0_ASSERT => '1',
C_GEN1_ASSERT => '1',
C_BASEADDR => X"83c00000",
C_HIGHADDR => X"83c0ffff",
C_SPLB_AWIDTH => 32,
C_SPLB_DWIDTH => 32,
C_SPLB_P2P => 0,
C_SPLB_MID_WIDTH => 1,
C_SPLB_NUM_MASTERS => 2,
C_SPLB_SUPPORT_BURSTS => 0,
C_SPLB_NATIVE_DWIDTH => 32
)
port map (
CaptureTrig0 => CaptureTrig0,
CaptureTrig1 => CaptureTrig1,
GenerateOut0 => GenerateOut0,
GenerateOut1 => GenerateOut1,
PWM0 => PWM0,
Interrupt => Interrupt,
Freeze => Freeze,
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_PAValid => PLB_PAValid,
PLB_masterID => PLB_masterID,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrDBus => PLB_wrDBus,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_rdDBus => Sl_rdDBus,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
PLB_UABus => PLB_UABus,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_MSize => PLB_MSize,
PLB_lockErr => PLB_lockErr,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MIRQ => Sl_MIRQ
);
end architecture STRUCTURE;
|
gpl-2.0
|
0ab2974dd1de6bed517b10cf109191ec
| 0.586312 | 3.232423 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_clk_wiz_1_0/system_clk_wiz_1_0_sim_netlist.vhdl
| 1 | 8,330 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:46:39 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_clk_wiz_1_0/system_clk_wiz_1_0_sim_netlist.vhdl
-- Design : system_clk_wiz_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_1_0_system_clk_wiz_1_0_clk_wiz is
port (
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC;
clk_out3 : out STD_LOGIC;
clk_out4 : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_clk_wiz_1_0_system_clk_wiz_1_0_clk_wiz : entity is "system_clk_wiz_1_0_clk_wiz";
end system_clk_wiz_1_0_system_clk_wiz_1_0_clk_wiz;
architecture STRUCTURE of system_clk_wiz_1_0_system_clk_wiz_1_0_clk_wiz is
signal clk_in1_system_clk_wiz_1_0 : STD_LOGIC;
signal clk_out1_system_clk_wiz_1_0 : STD_LOGIC;
signal clk_out2_system_clk_wiz_1_0 : STD_LOGIC;
signal clk_out3_system_clk_wiz_1_0 : STD_LOGIC;
signal clk_out4_system_clk_wiz_1_0 : STD_LOGIC;
signal clkfbout_buf_system_clk_wiz_1_0 : STD_LOGIC;
signal clkfbout_system_clk_wiz_1_0 : STD_LOGIC;
signal reset_high : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout3_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout4_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_system_clk_wiz_1_0,
O => clkfbout_buf_system_clk_wiz_1_0
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_system_clk_wiz_1_0
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_system_clk_wiz_1_0,
O => clk_out1
);
clkout2_buf: unisim.vcomponents.BUFG
port map (
I => clk_out2_system_clk_wiz_1_0,
O => clk_out2
);
clkout3_buf: unisim.vcomponents.BUFG
port map (
I => clk_out3_system_clk_wiz_1_0,
O => clk_out3
);
clkout4_buf: unisim.vcomponents.BUFG
port map (
I => clk_out4_system_clk_wiz_1_0,
O => clk_out4
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 10.000000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 10.000000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 6,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 5,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 40,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_system_clk_wiz_1_0,
CLKFBOUT => clkfbout_system_clk_wiz_1_0,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_system_clk_wiz_1_0,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1_system_clk_wiz_1_0,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => clk_out2_system_clk_wiz_1_0,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => clk_out3_system_clk_wiz_1_0,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => clk_out4_system_clk_wiz_1_0,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => reset_high
);
mmcm_adv_inst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => resetn,
O => reset_high
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_1_0 is
port (
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC;
clk_out3 : out STD_LOGIC;
clk_out4 : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_clk_wiz_1_0 : entity is true;
end system_clk_wiz_1_0;
architecture STRUCTURE of system_clk_wiz_1_0 is
begin
inst: entity work.system_clk_wiz_1_0_system_clk_wiz_1_0_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
clk_out2 => clk_out2,
clk_out3 => clk_out3,
clk_out4 => clk_out4,
locked => locked,
resetn => resetn
);
end STRUCTURE;
|
apache-2.0
|
167cdcf34fc3dc39e6de380d1c62e56f
| 0.630372 | 3.210019 | false | false | false | false |
jeffmagina/ECE368
|
Lab1/ALUwithInput/debounce.vhd
| 1 | 1,927 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Debouncer
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Debouncer
-- Debounce Input Signal
-- Input is fed through two flip flops
-- If both flip flops(2 cycles) have a high then
-- the counter will increment till it goes to
-- the necessary wait time.
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.all;
entity debounce is
Generic ( wait_time : INTEGER := 20);
-- Wait_time is a fixed time to wait to validate a debounce signal
-- Wait time is based on the Nexys 50 MHZ Clock
-- XX : (2^xx + 2)/CLK
-- 21 : 41.9ms | (2^21 + 2)/50E6
-- 20 : 21.0ms | (2^20 + 2)/50E6
-- 19 : 10.5ms | (2^19 + 2)/50E6
-- 18 : 5.2ms | (2^18 + 2)/50E6
Port ( CLK : in STD_LOGIC;
INPUT : in STD_LOGIC;
OUTPUT : out STD_LOGIC);
end debounce;
architecture Logic of debounce is
signal D_STATE : STD_LOGIC_VECTOR (1 downto 0);
signal D_SET : STD_LOGIC;
signal Count : STD_LOGIC_VECTOR( wait_time downto 0) := (others => '0');
begin
D_SET <= D_STATE(0) xor D_STATE(1);
--Check what the deboune states are
-- *if there is a change in state then D_SET will be set to a high
input_monitor: process (CLK)
begin
if (CLK'event and CLK = '1') then
D_STATE(0) <= INPUT;
D_STATE(1) <= D_STATE(0);
if(D_SET = '1') then
Count <= (others => '0');
elsif(Count(wait_time) = '0') then
Count <= Count + 1;
else
OUTPUT <= D_STATE(1);
end if;
end if;
end process;
end Logic;
|
mit
|
cbeabe8d348c4cfafb4d57dc2c8b9a80
| 0.559938 | 3.472072 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 1/OMUXT_tb.vhd
| 1 | 1,440 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY OMUXT_tb IS
END OMUXT_tb;
ARCHITECTURE behavior OF OMUXT_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT OMUXT
PORT(
Crs2 : IN std_logic_vector(31 downto 0);
SEUimm : IN std_logic_vector(31 downto 0);
i : IN std_logic;
oper2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Crs2 : std_logic_vector(31 downto 0) := (others => '0');
signal SEUimm : std_logic_vector(31 downto 0) := (others => '0');
signal i : std_logic := '0';
--Outputs
signal oper2 : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: OMUXT PORT MAP (
Crs2 => Crs2,
SEUimm => SEUimm,
i => i,
oper2 => oper2
);
-- Stimulus process
stim_proc: process
begin
i<='0';
Crs2<="01000010111001000110011101010111";
SEUimm<="00000000000000000000000100110101";
wait for 20 ns;
Crs2<="00000000000010000000001000000000";
SEUimm<="11111111111111111111001000000000";
wait for 20 ns;
i<='1';
Crs2<="00001111111000000011111111100000";
SEUimm<="00000000000000000000001111111111";
wait for 20 ns;
Crs2<="00000000000000000011101001010100";
SEUimm<="00000000000000000000001111000011";
wait;
end process;
END;
|
mit
|
27a3893447358cb3405e5c691d81f67e
| 0.607639 | 3.956044 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_gpio_0_0/system_axi_gpio_0_0_sim_netlist.vhdl
| 1 | 216,123 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:48:24 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_gpio_0_0/system_axi_gpio_0_0_sim_netlist.vhdl
-- Design : system_axi_gpio_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_0_0_address_decoder is
port (
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[19]\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]\ : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 19 downto 0 );
\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13]\ : out STD_LOGIC;
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\ip2bus_data_i_D1_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
Read_Reg_Rst : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_rd_ce_or_reduce : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_wr_ce_or_reduce : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]_0\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
start2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
is_read : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\bus2ip_addr_i_reg[8]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 19 downto 0 );
\Not_Dual.gpio_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
bus2ip_reset : in STD_LOGIC;
p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
ip2bus_data : in STD_LOGIC_VECTOR ( 0 to 0 );
p_3_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
GPIO_xferAck_i : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_0_0_address_decoder : entity is "address_decoder";
end system_axi_gpio_0_0_address_decoder;
architecture STRUCTURE of system_axi_gpio_0_0_address_decoder is
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\ : STD_LOGIC;
signal \^not_dual.gpio_data_out_reg[19]\ : STD_LOGIC;
signal \^ip2bus_data_i_d1_reg[0]\ : STD_LOGIC;
signal \^ip_irpt_enable_reg_reg[0]\ : STD_LOGIC;
signal p_10_in : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_11_in : STD_LOGIC;
signal p_11_out : STD_LOGIC;
signal p_12_in : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_13_in : STD_LOGIC;
signal p_13_out : STD_LOGIC;
signal p_14_in : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal p_15_out : STD_LOGIC;
signal p_16_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in_0 : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_5_in : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_in : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_9_in : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal pselect_hit_i_1 : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[0]_i_2\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[12]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[13]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[14]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[15]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[16]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[17]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[18]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[19]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[4]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[6]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \Not_Dual.gpio_Data_Out[7]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of intr2bus_rdack_i_1 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \ip2bus_data_i_D1[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of irpt_rdack_d1_i_1 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of irpt_wrack_d1_i_1 : label is "soft_lutpair3";
begin
\Not_Dual.gpio_Data_Out_reg[19]\ <= \^not_dual.gpio_data_out_reg[19]\;
\ip2bus_data_i_D1_reg[0]\ <= \^ip2bus_data_i_d1_reg[0]\;
\ip_irpt_enable_reg_reg[0]\ <= \^ip_irpt_enable_reg_reg[0]\;
s_axi_arready <= \^s_axi_arready\;
s_axi_wready <= \^s_axi_wready\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => start2,
I2 => \^ip_irpt_enable_reg_reg[0]\,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => \^ip_irpt_enable_reg_reg[0]\,
R => '0'
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_9_out
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_9_out,
Q => p_10_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_8_out
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_8_out,
Q => p_9_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_7_out
);
\GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_7_out,
Q => \^ip2bus_data_i_d1_reg[0]\,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_6_out
);
\GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_6_out,
Q => p_7_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_5_out
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_5_out,
Q => p_6_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_4_out
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_4_out,
Q => p_5_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\,
Q => p_4_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\,
Q => p_3_in_0,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\,
Q => p_2_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => s_axi_aresetn,
I1 => \^s_axi_arready\,
I2 => \^s_axi_wready\,
O => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_15_out
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_15_out,
Q => \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\,
Q => p_16_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_14_out
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_14_out,
Q => p_15_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_13_out
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_13_out,
Q => p_14_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0200000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_12_out
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_12_out,
Q => p_13_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_11_out
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_11_out,
Q => p_12_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_10_out
);
\GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_10_out,
Q => p_11_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => intr_rd_ce_or_reduce
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00FE0000"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => ip2Bus_RdAck_intr_reg_hole_d1,
I4 => \^ip_irpt_enable_reg_reg[0]\,
O => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FE"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => intr_wr_ce_or_reduce
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => p_16_in,
I1 => p_2_in,
I2 => \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\,
I3 => p_14_in,
I4 => p_15_in,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_12_in,
I1 => p_13_in,
I2 => p_10_in,
I3 => p_11_in,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_5_in,
I1 => p_7_in,
I2 => p_3_in_0,
I3 => p_4_in,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000FE"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => \^ip_irpt_enable_reg_reg[0]\,
I4 => ip2Bus_WrAck_intr_reg_hole_d1,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\
);
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => start2,
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => \bus2ip_addr_i_reg[8]\(4),
I3 => \bus2ip_addr_i_reg[8]\(5),
I4 => \bus2ip_addr_i_reg[8]\(3),
I5 => \bus2ip_addr_i_reg[8]\(2),
O => pselect_hit_i_1
);
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => pselect_hit_i_1,
Q => \^not_dual.gpio_data_out_reg[19]\,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(19),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(19),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => GPIO_DBus_i(0)
);
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(9),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(9),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22]\
);
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(8),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(8),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23]\
);
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(7),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(7),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24]\
);
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(6),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(6),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25]\
);
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(5),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(5),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26]\
);
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(4),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(4),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27]\
);
\Not_Dual.READ_REG_GEN[16].GPIO_DBus_i[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(3),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(3),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28]\
);
\Not_Dual.READ_REG_GEN[17].GPIO_DBus_i[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(2),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(2),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29]\
);
\Not_Dual.READ_REG_GEN[18].GPIO_DBus_i[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(1),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(1),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30]\
);
\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^not_dual.gpio_data_out_reg[19]\,
I1 => GPIO_xferAck_i,
I2 => bus2ip_rnw_i_reg,
I3 => gpio_xferAck_Reg,
O => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(0),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(0),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31]\
);
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(18),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(18),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13]\
);
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(17),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(17),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14]\
);
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(16),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(16),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15]\
);
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(15),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(15),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16]\
);
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(14),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(14),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17]\
);
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(13),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(13),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18]\
);
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(12),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(12),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19]\
);
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(11),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(11),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20]\
);
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(10),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(10),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[19]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21]\
);
\Not_Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000100"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^not_dual.gpio_data_out_reg[19]\,
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => bus2ip_reset,
O => \Not_Dual.gpio_Data_Out_reg[0]\(0)
);
\Not_Dual.gpio_Data_Out[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(31),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(19),
O => D(19)
);
\Not_Dual.gpio_Data_Out[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(21),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(9),
O => D(9)
);
\Not_Dual.gpio_Data_Out[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(20),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(8),
O => D(8)
);
\Not_Dual.gpio_Data_Out[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(19),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(7),
O => D(7)
);
\Not_Dual.gpio_Data_Out[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(18),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(6),
O => D(6)
);
\Not_Dual.gpio_Data_Out[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(17),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(5),
O => D(5)
);
\Not_Dual.gpio_Data_Out[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(16),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(4),
O => D(4)
);
\Not_Dual.gpio_Data_Out[16]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(15),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(3),
O => D(3)
);
\Not_Dual.gpio_Data_Out[17]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(14),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(2),
O => D(2)
);
\Not_Dual.gpio_Data_Out[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(13),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(1),
O => D(1)
);
\Not_Dual.gpio_Data_Out[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(12),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(0),
O => D(0)
);
\Not_Dual.gpio_Data_Out[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(30),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(18),
O => D(18)
);
\Not_Dual.gpio_Data_Out[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(29),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(17),
O => D(17)
);
\Not_Dual.gpio_Data_Out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(28),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(16),
O => D(16)
);
\Not_Dual.gpio_Data_Out[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(27),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(15),
O => D(15)
);
\Not_Dual.gpio_Data_Out[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(26),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(14),
O => D(14)
);
\Not_Dual.gpio_Data_Out[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(25),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(13),
O => D(13)
);
\Not_Dual.gpio_Data_Out[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(24),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(12),
O => D(12)
);
\Not_Dual.gpio_Data_Out[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(23),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(11),
O => D(11)
);
\Not_Dual.gpio_Data_Out[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(22),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[19]\,
I3 => s_axi_wdata(10),
O => D(10)
);
\Not_Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF01000000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^not_dual.gpio_data_out_reg[19]\,
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => bus2ip_reset,
O => E(0)
);
intr2bus_rdack_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"44444440"
)
port map (
I0 => irpt_rdack_d1,
I1 => \^ip_irpt_enable_reg_reg[0]\,
I2 => p_9_in,
I3 => \^ip2bus_data_i_d1_reg[0]\,
I4 => p_6_in,
O => intr2bus_rdack0
);
intr2bus_wrack_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000FE"
)
port map (
I0 => p_9_in,
I1 => \^ip2bus_data_i_d1_reg[0]\,
I2 => p_6_in,
I3 => \^ip_irpt_enable_reg_reg[0]\,
I4 => irpt_wrack_d1,
O => interrupt_wrce_strb
);
\ip2bus_data_i_D1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000080"
)
port map (
I0 => p_0_in(0),
I1 => p_9_in,
I2 => \^ip_irpt_enable_reg_reg[0]\,
I3 => p_6_in,
I4 => \^ip2bus_data_i_d1_reg[0]\,
O => \ip2bus_data_i_D1_reg[0]_0\(1)
);
\ip2bus_data_i_D1[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEAAAAFAAAAAAA"
)
port map (
I0 => ip2bus_data(0),
I1 => p_3_in(0),
I2 => p_1_in(0),
I3 => p_6_in,
I4 => \^ip_irpt_enable_reg_reg[0]\,
I5 => \^ip2bus_data_i_d1_reg[0]\,
O => \ip2bus_data_i_D1_reg[0]_0\(0)
);
\ip_irpt_enable_reg[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(0),
I1 => p_6_in,
I2 => \^ip_irpt_enable_reg_reg[0]\,
I3 => p_1_in(0),
O => \ip_irpt_enable_reg_reg[0]_0\
);
ipif_glbl_irpt_enable_reg_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(31),
I1 => p_9_in,
I2 => \^ip_irpt_enable_reg_reg[0]\,
I3 => p_0_in(0),
O => ipif_glbl_irpt_enable_reg_reg
);
irpt_rdack_d1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => p_9_in,
I1 => \^ip2bus_data_i_d1_reg[0]\,
I2 => p_6_in,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => irpt_rdack
);
irpt_wrack_d1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00FE"
)
port map (
I0 => p_9_in,
I1 => \^ip2bus_data_i_d1_reg[0]\,
I2 => p_6_in,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => irpt_wrack
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00020000"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => is_read,
I5 => ip2bus_rdack_i_D1,
O => \^s_axi_arready\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00020000"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => is_write_reg,
I5 => ip2bus_wrack_i_D1,
O => \^s_axi_wready\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_0_0_cdc_sync is
port (
D : out STD_LOGIC_VECTOR ( 19 downto 0 );
scndry_vect_out : out STD_LOGIC_VECTOR ( 19 downto 0 );
Q : in STD_LOGIC_VECTOR ( 19 downto 0 );
gpio_io_i : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_0_0_cdc_sync : entity is "cdc_sync";
end system_axi_gpio_0_0_cdc_sync;
architecture STRUCTURE of system_axi_gpio_0_0_cdc_sync is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_10 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_11 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_12 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_13 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_14 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_15 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_16 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_17 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_18 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_19 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_2 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_3 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_4 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_5 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_6 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_7 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_8 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_9 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d2_10 : STD_LOGIC;
signal s_level_out_bus_d2_11 : STD_LOGIC;
signal s_level_out_bus_d2_12 : STD_LOGIC;
signal s_level_out_bus_d2_13 : STD_LOGIC;
signal s_level_out_bus_d2_14 : STD_LOGIC;
signal s_level_out_bus_d2_15 : STD_LOGIC;
signal s_level_out_bus_d2_16 : STD_LOGIC;
signal s_level_out_bus_d2_17 : STD_LOGIC;
signal s_level_out_bus_d2_18 : STD_LOGIC;
signal s_level_out_bus_d2_19 : STD_LOGIC;
signal s_level_out_bus_d2_2 : STD_LOGIC;
signal s_level_out_bus_d2_3 : STD_LOGIC;
signal s_level_out_bus_d2_4 : STD_LOGIC;
signal s_level_out_bus_d2_5 : STD_LOGIC;
signal s_level_out_bus_d2_6 : STD_LOGIC;
signal s_level_out_bus_d2_7 : STD_LOGIC;
signal s_level_out_bus_d2_8 : STD_LOGIC;
signal s_level_out_bus_d2_9 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
signal s_level_out_bus_d3_10 : STD_LOGIC;
signal s_level_out_bus_d3_11 : STD_LOGIC;
signal s_level_out_bus_d3_12 : STD_LOGIC;
signal s_level_out_bus_d3_13 : STD_LOGIC;
signal s_level_out_bus_d3_14 : STD_LOGIC;
signal s_level_out_bus_d3_15 : STD_LOGIC;
signal s_level_out_bus_d3_16 : STD_LOGIC;
signal s_level_out_bus_d3_17 : STD_LOGIC;
signal s_level_out_bus_d3_18 : STD_LOGIC;
signal s_level_out_bus_d3_19 : STD_LOGIC;
signal s_level_out_bus_d3_2 : STD_LOGIC;
signal s_level_out_bus_d3_3 : STD_LOGIC;
signal s_level_out_bus_d3_4 : STD_LOGIC;
signal s_level_out_bus_d3_5 : STD_LOGIC;
signal s_level_out_bus_d3_6 : STD_LOGIC;
signal s_level_out_bus_d3_7 : STD_LOGIC;
signal s_level_out_bus_d3_8 : STD_LOGIC;
signal s_level_out_bus_d3_9 : STD_LOGIC;
signal \^scndry_vect_out\ : STD_LOGIC_VECTOR ( 19 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
scndry_vect_out(19 downto 0) <= \^scndry_vect_out\(19 downto 0);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_10,
Q => s_level_out_bus_d2_10,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_11,
Q => s_level_out_bus_d2_11,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_12,
Q => s_level_out_bus_d2_12,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_13,
Q => s_level_out_bus_d2_13,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_14,
Q => s_level_out_bus_d2_14,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_15,
Q => s_level_out_bus_d2_15,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_16,
Q => s_level_out_bus_d2_16,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_17,
Q => s_level_out_bus_d2_17,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_18,
Q => s_level_out_bus_d2_18,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_19,
Q => s_level_out_bus_d2_19,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_2,
Q => s_level_out_bus_d2_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_3,
Q => s_level_out_bus_d2_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_4,
Q => s_level_out_bus_d2_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_5,
Q => s_level_out_bus_d2_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_6,
Q => s_level_out_bus_d2_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_7,
Q => s_level_out_bus_d2_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_8,
Q => s_level_out_bus_d2_8,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_9,
Q => s_level_out_bus_d2_9,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_10,
Q => s_level_out_bus_d3_10,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_11,
Q => s_level_out_bus_d3_11,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_12,
Q => s_level_out_bus_d3_12,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_13,
Q => s_level_out_bus_d3_13,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_14,
Q => s_level_out_bus_d3_14,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_15,
Q => s_level_out_bus_d3_15,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_16,
Q => s_level_out_bus_d3_16,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_17,
Q => s_level_out_bus_d3_17,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_18,
Q => s_level_out_bus_d3_18,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_19,
Q => s_level_out_bus_d3_19,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_2,
Q => s_level_out_bus_d3_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_3,
Q => s_level_out_bus_d3_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_4,
Q => s_level_out_bus_d3_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_5,
Q => s_level_out_bus_d3_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_6,
Q => s_level_out_bus_d3_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_7,
Q => s_level_out_bus_d3_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_8,
Q => s_level_out_bus_d3_8,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_9,
Q => s_level_out_bus_d3_9,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => \^scndry_vect_out\(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_10,
Q => \^scndry_vect_out\(10),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_11,
Q => \^scndry_vect_out\(11),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_12,
Q => \^scndry_vect_out\(12),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_13,
Q => \^scndry_vect_out\(13),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_14,
Q => \^scndry_vect_out\(14),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_15,
Q => \^scndry_vect_out\(15),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_16,
Q => \^scndry_vect_out\(16),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_17,
Q => \^scndry_vect_out\(17),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_18,
Q => \^scndry_vect_out\(18),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_19,
Q => \^scndry_vect_out\(19),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => \^scndry_vect_out\(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_2,
Q => \^scndry_vect_out\(2),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_3,
Q => \^scndry_vect_out\(3),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_4,
Q => \^scndry_vect_out\(4),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_5,
Q => \^scndry_vect_out\(5),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_6,
Q => \^scndry_vect_out\(6),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_7,
Q => \^scndry_vect_out\(7),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_8,
Q => \^scndry_vect_out\(8),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_9,
Q => \^scndry_vect_out\(9),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(10),
Q => s_level_out_bus_d1_cdc_to_10,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(11),
Q => s_level_out_bus_d1_cdc_to_11,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(12),
Q => s_level_out_bus_d1_cdc_to_12,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(13),
Q => s_level_out_bus_d1_cdc_to_13,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(14),
Q => s_level_out_bus_d1_cdc_to_14,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(15),
Q => s_level_out_bus_d1_cdc_to_15,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[16].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(16),
Q => s_level_out_bus_d1_cdc_to_16,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[17].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(17),
Q => s_level_out_bus_d1_cdc_to_17,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[18].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(18),
Q => s_level_out_bus_d1_cdc_to_18,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[19].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(19),
Q => s_level_out_bus_d1_cdc_to_19,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(2),
Q => s_level_out_bus_d1_cdc_to_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(3),
Q => s_level_out_bus_d1_cdc_to_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(4),
Q => s_level_out_bus_d1_cdc_to_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(5),
Q => s_level_out_bus_d1_cdc_to_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(6),
Q => s_level_out_bus_d1_cdc_to_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(7),
Q => s_level_out_bus_d1_cdc_to_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(8),
Q => s_level_out_bus_d1_cdc_to_8,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(9),
Q => s_level_out_bus_d1_cdc_to_9,
R => '0'
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(19),
I1 => \^scndry_vect_out\(19),
O => D(19)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(9),
I1 => \^scndry_vect_out\(9),
O => D(9)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(8),
I1 => \^scndry_vect_out\(8),
O => D(8)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(7),
I1 => \^scndry_vect_out\(7),
O => D(7)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(6),
I1 => \^scndry_vect_out\(6),
O => D(6)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(5),
I1 => \^scndry_vect_out\(5),
O => D(5)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(4),
I1 => \^scndry_vect_out\(4),
O => D(4)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(3),
I1 => \^scndry_vect_out\(3),
O => D(3)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(2),
I1 => \^scndry_vect_out\(2),
O => D(2)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(1),
I1 => \^scndry_vect_out\(1),
O => D(1)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(0),
I1 => \^scndry_vect_out\(0),
O => D(0)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(18),
I1 => \^scndry_vect_out\(18),
O => D(18)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(17),
I1 => \^scndry_vect_out\(17),
O => D(17)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(16),
I1 => \^scndry_vect_out\(16),
O => D(16)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(15),
I1 => \^scndry_vect_out\(15),
O => D(15)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(14),
I1 => \^scndry_vect_out\(14),
O => D(14)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(13),
I1 => \^scndry_vect_out\(13),
O => D(13)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(12),
I1 => \^scndry_vect_out\(12),
O => D(12)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(11),
I1 => \^scndry_vect_out\(11),
O => D(11)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(10),
I1 => \^scndry_vect_out\(10),
O => D(10)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_0_0_interrupt_control is
port (
irpt_wrack_d1 : out STD_LOGIC;
p_3_in : out STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : out STD_LOGIC;
p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 );
p_0_in : out STD_LOGIC_VECTOR ( 0 to 0 );
IP2INTC_Irpt_i : out STD_LOGIC;
ip2bus_wrack_i : out STD_LOGIC;
ip2bus_rdack_i : out STD_LOGIC;
bus2ip_reset : in STD_LOGIC;
irpt_wrack : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
GPIO_intr : in STD_LOGIC;
interrupt_wrce_strb : in STD_LOGIC;
irpt_rdack : in STD_LOGIC;
intr2bus_rdack0 : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\ : in STD_LOGIC;
p_8_in : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 );
Bus_RNW_reg : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole : in STD_LOGIC;
bus2ip_rnw : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_0_0_interrupt_control : entity is "interrupt_control";
end system_axi_gpio_0_0_interrupt_control;
architecture STRUCTURE of system_axi_gpio_0_0_interrupt_control is
signal \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0\ : STD_LOGIC;
signal intr2bus_rdack : STD_LOGIC;
signal intr2bus_wrack : STD_LOGIC;
signal irpt_dly1 : STD_LOGIC;
signal irpt_dly2 : STD_LOGIC;
signal \^irpt_wrack_d1\ : STD_LOGIC;
signal \^p_0_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^p_1_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^p_3_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
irpt_wrack_d1 <= \^irpt_wrack_d1\;
p_0_in(0) <= \^p_0_in\(0);
p_1_in(0) <= \^p_1_in\(0);
p_3_in(0) <= \^p_3_in\(0);
\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_intr,
Q => irpt_dly1,
S => bus2ip_reset
);
\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_dly1,
Q => irpt_dly2,
S => bus2ip_reset
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4F4F4F44FF4F4F4"
)
port map (
I0 => irpt_dly2,
I1 => irpt_dly1,
I2 => \^p_3_in\(0),
I3 => p_8_in,
I4 => s_axi_wdata(0),
I5 => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0\,
O => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^irpt_wrack_d1\,
I1 => Bus_RNW_reg,
O => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0\
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\,
Q => \^p_3_in\(0),
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2intc_irpt_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^p_3_in\(0),
I1 => \^p_1_in\(0),
I2 => \^p_0_in\(0),
O => IP2INTC_Irpt_i
);
intr2bus_rdack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr2bus_rdack0,
Q => intr2bus_rdack,
R => bus2ip_reset
);
intr2bus_wrack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => interrupt_wrce_strb,
Q => intr2bus_wrack,
R => bus2ip_reset
);
ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FEEE"
)
port map (
I0 => ip2Bus_RdAck_intr_reg_hole,
I1 => intr2bus_rdack,
I2 => bus2ip_rnw,
I3 => GPIO_xferAck_i,
O => ip2bus_rdack_i
);
ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"EFEE"
)
port map (
I0 => ip2Bus_WrAck_intr_reg_hole,
I1 => intr2bus_wrack,
I2 => bus2ip_rnw,
I3 => GPIO_xferAck_i,
O => ip2bus_wrack_i
);
\ip_irpt_enable_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\,
Q => \^p_1_in\(0),
R => bus2ip_reset
);
ipif_glbl_irpt_enable_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\,
Q => \^p_0_in\(0),
R => bus2ip_reset
);
irpt_rdack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_rdack,
Q => irpt_rdack_d1,
R => bus2ip_reset
);
irpt_wrack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_wrack,
Q => \^irpt_wrack_d1\,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_0_0_GPIO_Core is
port (
ip2bus_data : out STD_LOGIC_VECTOR ( 19 downto 0 );
GPIO_xferAck_i : out STD_LOGIC;
gpio_xferAck_Reg : out STD_LOGIC;
GPIO_intr : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 19 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 19 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 19 downto 0 );
Read_Reg_Rst : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[19]_0\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[18]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[17]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[16]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[15]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[14]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[13]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[12]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[11]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[10]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[9]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[8]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[7]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[6]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[5]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[4]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[3]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[2]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[1]_0\ : in STD_LOGIC;
GPIO_DBus_i : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_reset : in STD_LOGIC;
bus2ip_cs : in STD_LOGIC_VECTOR ( 0 to 0 );
gpio_io_i : in STD_LOGIC_VECTOR ( 19 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 19 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_0_0_GPIO_Core : entity is "GPIO_Core";
end system_axi_gpio_0_0_GPIO_Core;
architecture STRUCTURE of system_axi_gpio_0_0_GPIO_Core is
signal \^gpio_xferack_i\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_4_n_0\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0]\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11]\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[19]\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1]\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8]\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9]\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 19 downto 0 );
signal gpio_data_in_xor : STD_LOGIC_VECTOR ( 0 to 19 );
signal gpio_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 19 );
signal \^gpio_xferack_reg\ : STD_LOGIC;
signal iGPIO_xferAck : STD_LOGIC;
signal or_ints : STD_LOGIC;
signal p_11_in : STD_LOGIC;
signal p_12_in : STD_LOGIC;
signal p_13_in : STD_LOGIC;
signal p_14_in : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal p_16_in : STD_LOGIC;
signal p_17_in : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal p_5_in : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_9_in : STD_LOGIC;
begin
GPIO_xferAck_i <= \^gpio_xferack_i\;
Q(19 downto 0) <= \^q\(19 downto 0);
gpio_xferAck_Reg <= \^gpio_xferack_reg\;
\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0\,
I1 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[19]\,
I2 => p_17_in,
I3 => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0\,
I4 => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_4_n_0\,
O => or_ints
);
\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => p_12_in,
I1 => p_11_in,
I2 => p_14_in,
I3 => p_13_in,
I4 => p_15_in,
I5 => p_16_in,
O => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0\
);
\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1]\,
I1 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0]\,
I2 => p_2_in,
I3 => p_1_in,
I4 => p_3_in,
I5 => p_4_in,
O => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0\
);
\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => p_6_in,
I1 => p_5_in,
I2 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9]\,
I3 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8]\,
I4 => p_9_in,
I5 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11]\,
O => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_4_n_0\
);
\Not_Dual.GEN_INTERRUPT.GPIO_intr_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => or_ints,
Q => GPIO_intr,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(0),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0]\,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(10),
Q => p_9_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(11),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11]\,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(12),
Q => p_11_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(13),
Q => p_12_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(14),
Q => p_13_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(15),
Q => p_14_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(16),
Q => p_15_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(17),
Q => p_16_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(18),
Q => p_17_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(19),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[19]\,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(1),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1]\,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(2),
Q => p_1_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(3),
Q => p_2_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(4),
Q => p_3_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(5),
Q => p_4_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(6),
Q => p_5_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(7),
Q => p_6_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(8),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8]\,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(9),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9]\,
R => bus2ip_reset
);
\Not_Dual.INPUT_DOUBLE_REGS3\: entity work.system_axi_gpio_0_0_cdc_sync
port map (
D(19) => gpio_data_in_xor(0),
D(18) => gpio_data_in_xor(1),
D(17) => gpio_data_in_xor(2),
D(16) => gpio_data_in_xor(3),
D(15) => gpio_data_in_xor(4),
D(14) => gpio_data_in_xor(5),
D(13) => gpio_data_in_xor(6),
D(12) => gpio_data_in_xor(7),
D(11) => gpio_data_in_xor(8),
D(10) => gpio_data_in_xor(9),
D(9) => gpio_data_in_xor(10),
D(8) => gpio_data_in_xor(11),
D(7) => gpio_data_in_xor(12),
D(6) => gpio_data_in_xor(13),
D(5) => gpio_data_in_xor(14),
D(4) => gpio_data_in_xor(15),
D(3) => gpio_data_in_xor(16),
D(2) => gpio_data_in_xor(17),
D(1) => gpio_data_in_xor(18),
D(0) => gpio_data_in_xor(19),
Q(19 downto 0) => \^q\(19 downto 0),
gpio_io_i(19 downto 0) => gpio_io_i(19 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(19) => gpio_io_i_d2(0),
scndry_vect_out(18) => gpio_io_i_d2(1),
scndry_vect_out(17) => gpio_io_i_d2(2),
scndry_vect_out(16) => gpio_io_i_d2(3),
scndry_vect_out(15) => gpio_io_i_d2(4),
scndry_vect_out(14) => gpio_io_i_d2(5),
scndry_vect_out(13) => gpio_io_i_d2(6),
scndry_vect_out(12) => gpio_io_i_d2(7),
scndry_vect_out(11) => gpio_io_i_d2(8),
scndry_vect_out(10) => gpio_io_i_d2(9),
scndry_vect_out(9) => gpio_io_i_d2(10),
scndry_vect_out(8) => gpio_io_i_d2(11),
scndry_vect_out(7) => gpio_io_i_d2(12),
scndry_vect_out(6) => gpio_io_i_d2(13),
scndry_vect_out(5) => gpio_io_i_d2(14),
scndry_vect_out(4) => gpio_io_i_d2(15),
scndry_vect_out(3) => gpio_io_i_d2(16),
scndry_vect_out(2) => gpio_io_i_d2(17),
scndry_vect_out(1) => gpio_io_i_d2(18),
scndry_vect_out(0) => gpio_io_i_d2(19)
);
\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus_i(0),
Q => ip2bus_data(19),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[10]_0\,
Q => ip2bus_data(9),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[11]_0\,
Q => ip2bus_data(8),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[12]_0\,
Q => ip2bus_data(7),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[13]_0\,
Q => ip2bus_data(6),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[14]_0\,
Q => ip2bus_data(5),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[15]_0\,
Q => ip2bus_data(4),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[16]_0\,
Q => ip2bus_data(3),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[17]_0\,
Q => ip2bus_data(2),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[18]_0\,
Q => ip2bus_data(1),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[19]_0\,
Q => ip2bus_data(0),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[1]_0\,
Q => ip2bus_data(18),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[2]_0\,
Q => ip2bus_data(17),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[3]_0\,
Q => ip2bus_data(16),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[4]_0\,
Q => ip2bus_data(15),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[5]_0\,
Q => ip2bus_data(14),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[6]_0\,
Q => ip2bus_data(13),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[7]_0\,
Q => ip2bus_data(12),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[8]_0\,
Q => ip2bus_data(11),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[9]_0\,
Q => ip2bus_data(10),
R => Read_Reg_Rst
);
\Not_Dual.gpio_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(0),
Q => \^q\(19),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(10),
Q => \^q\(9),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(11),
Q => \^q\(8),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(12),
Q => \^q\(7),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(13),
Q => \^q\(6),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(14),
Q => \^q\(5),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(15),
Q => \^q\(4),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(16),
Q => \^q\(3),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(17),
Q => \^q\(2),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(18),
Q => \^q\(1),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(19),
Q => \^q\(0),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(1),
Q => \^q\(18),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(2),
Q => \^q\(17),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(3),
Q => \^q\(16),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(4),
Q => \^q\(15),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(5),
Q => \^q\(14),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(6),
Q => \^q\(13),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(7),
Q => \^q\(12),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(8),
Q => \^q\(11),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(9),
Q => \^q\(10),
R => '0'
);
\Not_Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(19),
Q => gpio_io_o(19),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(9),
Q => gpio_io_o(9),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(8),
Q => gpio_io_o(8),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(7),
Q => gpio_io_o(7),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(6),
Q => gpio_io_o(6),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(5),
Q => gpio_io_o(5),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(4),
Q => gpio_io_o(4),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(3),
Q => gpio_io_o(3),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(2),
Q => gpio_io_o(2),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(1),
Q => gpio_io_o(1),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(0),
Q => gpio_io_o(0),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(18),
Q => gpio_io_o(18),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(17),
Q => gpio_io_o(17),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(16),
Q => gpio_io_o(16),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(15),
Q => gpio_io_o(15),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(14),
Q => gpio_io_o(14),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(13),
Q => gpio_io_o(13),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(12),
Q => gpio_io_o(12),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(11),
Q => gpio_io_o(11),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(10),
Q => gpio_io_o(10),
R => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(19),
Q => gpio_io_t(19),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(9),
Q => gpio_io_t(9),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(8),
Q => gpio_io_t(8),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(7),
Q => gpio_io_t(7),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(6),
Q => gpio_io_t(6),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(5),
Q => gpio_io_t(5),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(4),
Q => gpio_io_t(4),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(3),
Q => gpio_io_t(3),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(2),
Q => gpio_io_t(2),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(1),
Q => gpio_io_t(1),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(0),
Q => gpio_io_t(0),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(18),
Q => gpio_io_t(18),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(17),
Q => gpio_io_t(17),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(16),
Q => gpio_io_t(16),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(15),
Q => gpio_io_t(15),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(14),
Q => gpio_io_t(14),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(13),
Q => gpio_io_t(13),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(12),
Q => gpio_io_t(12),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(11),
Q => gpio_io_t(11),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(10),
Q => gpio_io_t(10),
S => bus2ip_reset
);
gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_xferack_i\,
Q => \^gpio_xferack_reg\,
R => bus2ip_reset
);
iGPIO_xferAck_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => \^gpio_xferack_reg\,
I1 => \^gpio_xferack_i\,
I2 => bus2ip_cs(0),
O => iGPIO_xferAck
);
iGPIO_xferAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck,
Q => \^gpio_xferack_i\,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_0_0_slave_attachment is
port (
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC;
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[19]\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 19 downto 0 );
\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13]\ : out STD_LOGIC;
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\ip2bus_data_i_D1_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
Read_Reg_Rst : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_rd_ce_or_reduce : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_wr_ce_or_reduce : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]_0\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 20 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 19 downto 0 );
Q : in STD_LOGIC_VECTOR ( 19 downto 0 );
p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
ip2bus_data : in STD_LOGIC_VECTOR ( 0 to 0 );
p_3_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
GPIO_xferAck_i : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC;
\ip2bus_data_i_D1_reg[0]_1\ : in STD_LOGIC_VECTOR ( 20 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_0_0_slave_attachment : entity is "slave_attachment";
end system_axi_gpio_0_0_slave_attachment;
architecture STRUCTURE of system_axi_gpio_0_0_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^not_dual.gpio_oe_reg[0]\ : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 6 );
signal bus2ip_rnw_i06_out : STD_LOGIC;
signal clear : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal \p_0_out__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 8 downto 2 );
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal s_axi_rdata_i : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \bus2ip_addr_i[4]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair12";
begin
\Not_Dual.gpio_OE_reg[0]\ <= \^not_dual.gpio_oe_reg[0]\;
s_axi_arready <= \^s_axi_arready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(1),
I1 => state(0),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
I_DECODER: entity work.system_axi_gpio_0_0_address_decoder
port map (
D(19 downto 0) => D(19 downto 0),
E(0) => E(0),
GPIO_DBus_i(0) => GPIO_DBus_i(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\,
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22]\ => \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22]\,
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23]\ => \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23]\,
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24]\ => \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24]\,
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25]\ => \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25]\,
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26]\ => \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26]\,
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27]\ => \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27]\,
\Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28]\ => \Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28]\,
\Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29]\ => \Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29]\,
\Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30]\ => \Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30]\,
\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31]\ => \Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31]\,
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13]\ => \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13]\,
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14]\ => \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14]\,
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15]\ => \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15]\,
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16]\ => \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16]\,
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17]\ => \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17]\,
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18]\ => \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18]\,
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19]\ => \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19]\,
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20]\ => \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20]\,
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21]\ => \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21]\,
\Not_Dual.gpio_Data_In_reg[0]\(19 downto 0) => Q(19 downto 0),
\Not_Dual.gpio_Data_Out_reg[0]\(0) => \Not_Dual.gpio_Data_Out_reg[0]\(0),
\Not_Dual.gpio_Data_Out_reg[19]\ => \Not_Dual.gpio_Data_Out_reg[19]\,
Q(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0),
Read_Reg_Rst => Read_Reg_Rst,
\bus2ip_addr_i_reg[8]\(6) => bus2ip_addr(0),
\bus2ip_addr_i_reg[8]\(5) => bus2ip_addr(1),
\bus2ip_addr_i_reg[8]\(4) => bus2ip_addr(2),
\bus2ip_addr_i_reg[8]\(3) => bus2ip_addr(3),
\bus2ip_addr_i_reg[8]\(2) => bus2ip_addr(4),
\bus2ip_addr_i_reg[8]\(1) => bus2ip_addr(5),
\bus2ip_addr_i_reg[8]\(0) => bus2ip_addr(6),
bus2ip_reset => bus2ip_reset,
bus2ip_rnw_i_reg => \^not_dual.gpio_oe_reg[0]\,
gpio_io_t(19 downto 0) => gpio_io_t(19 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_rd_ce_or_reduce => intr_rd_ce_or_reduce,
intr_wr_ce_or_reduce => intr_wr_ce_or_reduce,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2bus_data(0) => ip2bus_data(0),
\ip2bus_data_i_D1_reg[0]\ => \ip2bus_data_i_D1_reg[0]\,
\ip2bus_data_i_D1_reg[0]_0\(1 downto 0) => \ip2bus_data_i_D1_reg[0]_0\(1 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
\ip_irpt_enable_reg_reg[0]\ => \ip_irpt_enable_reg_reg[0]\,
\ip_irpt_enable_reg_reg[0]_0\ => \ip_irpt_enable_reg_reg[0]_0\,
ipif_glbl_irpt_enable_reg_reg => ipif_glbl_irpt_enable_reg_reg,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
p_0_in(0) => p_0_in(0),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => \^s_axi_arready\,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => \^s_axi_wready\,
start2 => start2
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(0),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(0),
O => \p_1_in__0\(2)
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(1),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(1),
O => \p_1_in__0\(3)
);
\bus2ip_addr_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(2),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(2),
O => \p_1_in__0\(4)
);
\bus2ip_addr_i[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(3),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(3),
O => \p_1_in__0\(5)
);
\bus2ip_addr_i[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(4),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(4),
O => \p_1_in__0\(6)
);
\bus2ip_addr_i[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(5),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(5),
O => \p_1_in__0\(7)
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(6),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(6),
O => \p_1_in__0\(8)
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(2),
Q => bus2ip_addr(6),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(3),
Q => bus2ip_addr(5),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(4),
Q => bus2ip_addr(4),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(5),
Q => bus2ip_addr(3),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(6),
Q => bus2ip_addr(2),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(7),
Q => bus2ip_addr(1),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(8),
Q => bus2ip_addr(0),
R => bus2ip_reset
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => s_axi_arvalid,
I1 => state(0),
I2 => state(1),
O => bus2ip_rnw_i06_out
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => bus2ip_rnw_i06_out,
Q => \^not_dual.gpio_oe_reg[0]\,
R => bus2ip_reset
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state[1]_i_2_n_0\,
I2 => state(1),
I3 => state(0),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => bus2ip_reset
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"1000FFFF10000000"
)
port map (
I0 => state(1),
I1 => s_axi_arvalid,
I2 => s_axi_wvalid,
I3 => s_axi_awvalid,
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
I4 => state(1),
I5 => state(0),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => bus2ip_reset
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(1),
I2 => state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => bus2ip_reset
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => s_axi_rdata_i
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(0),
Q => s_axi_rdata(0),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(10),
Q => s_axi_rdata(10),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(11),
Q => s_axi_rdata(11),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(12),
Q => s_axi_rdata(12),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(13),
Q => s_axi_rdata(13),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(14),
Q => s_axi_rdata(14),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(15),
Q => s_axi_rdata(15),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(16),
Q => s_axi_rdata(16),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(17),
Q => s_axi_rdata(17),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(18),
Q => s_axi_rdata(18),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(19),
Q => s_axi_rdata(19),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(1),
Q => s_axi_rdata(1),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(2),
Q => s_axi_rdata(2),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(20),
Q => s_axi_rdata(20),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(3),
Q => s_axi_rdata(3),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(4),
Q => s_axi_rdata(4),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(5),
Q => s_axi_rdata(5),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(6),
Q => s_axi_rdata(6),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(7),
Q => s_axi_rdata(7),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(8),
Q => s_axi_rdata(8),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(9),
Q => s_axi_rdata(9),
R => bus2ip_reset
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => bus2ip_reset
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(0),
I4 => state(1),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => bus2ip_reset
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FFFAACC"
)
port map (
I0 => \^s_axi_wready\,
I1 => s_axi_arvalid,
I2 => \state[1]_i_2_n_0\,
I3 => state(1),
I4 => state(0),
O => \p_0_out__0\(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2E2E2E2ECCCCFFCC"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(1),
I2 => \state[1]_i_2_n_0\,
I3 => \state[1]_i_3_n_0\,
I4 => s_axi_arvalid,
I5 => state(0),
O => \p_0_out__0\(1)
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \p_0_out__0\(0),
Q => state(0),
R => bus2ip_reset
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \p_0_out__0\(1),
Q => state(1),
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_0_0_axi_lite_ipif is
port (
p_8_in : out STD_LOGIC;
bus2ip_rnw : out STD_LOGIC;
bus2ip_cs : out STD_LOGIC_VECTOR ( 0 to 0 );
Bus_RNW_reg : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 19 downto 0 );
\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13]\ : out STD_LOGIC;
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
Read_Reg_Rst : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_rd_ce_or_reduce : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_wr_ce_or_reduce : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 20 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 19 downto 0 );
Q : in STD_LOGIC_VECTOR ( 19 downto 0 );
p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
ip2bus_data : in STD_LOGIC_VECTOR ( 0 to 0 );
p_3_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
GPIO_xferAck_i : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC;
\ip2bus_data_i_D1_reg[0]_0\ : in STD_LOGIC_VECTOR ( 20 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_0_0_axi_lite_ipif : entity is "axi_lite_ipif";
end system_axi_gpio_0_0_axi_lite_ipif;
architecture STRUCTURE of system_axi_gpio_0_0_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.system_axi_gpio_0_0_slave_attachment
port map (
D(19 downto 0) => D(19 downto 0),
E(0) => E(0),
GPIO_DBus_i(0) => GPIO_DBus_i(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\,
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22]\ => \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22]\,
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23]\ => \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23]\,
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24]\ => \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24]\,
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25]\ => \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25]\,
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26]\ => \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26]\,
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27]\ => \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27]\,
\Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28]\ => \Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28]\,
\Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29]\ => \Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29]\,
\Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30]\ => \Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30]\,
\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31]\ => \Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31]\,
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13]\ => \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13]\,
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14]\ => \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14]\,
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15]\ => \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15]\,
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16]\ => \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16]\,
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17]\ => \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17]\,
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18]\ => \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18]\,
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19]\ => \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19]\,
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20]\ => \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20]\,
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21]\ => \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21]\,
\Not_Dual.gpio_Data_Out_reg[0]\(0) => \Not_Dual.gpio_Data_Out_reg[0]\(0),
\Not_Dual.gpio_Data_Out_reg[19]\ => bus2ip_cs(0),
\Not_Dual.gpio_OE_reg[0]\ => bus2ip_rnw,
Q(19 downto 0) => Q(19 downto 0),
Read_Reg_Rst => Read_Reg_Rst,
bus2ip_reset => bus2ip_reset,
gpio_io_t(19 downto 0) => gpio_io_t(19 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_rd_ce_or_reduce => intr_rd_ce_or_reduce,
intr_wr_ce_or_reduce => intr_wr_ce_or_reduce,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2bus_data(0) => ip2bus_data(0),
\ip2bus_data_i_D1_reg[0]\ => p_8_in,
\ip2bus_data_i_D1_reg[0]_0\(1 downto 0) => \ip2bus_data_i_D1_reg[0]\(1 downto 0),
\ip2bus_data_i_D1_reg[0]_1\(20 downto 0) => \ip2bus_data_i_D1_reg[0]_0\(20 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
\ip_irpt_enable_reg_reg[0]\ => Bus_RNW_reg,
\ip_irpt_enable_reg_reg[0]_0\ => \ip_irpt_enable_reg_reg[0]\,
ipif_glbl_irpt_enable_reg_reg => ipif_glbl_irpt_enable_reg_reg,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_0_in(0) => p_0_in(0),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(6 downto 0) => s_axi_araddr(6 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(6 downto 0) => s_axi_awaddr(6 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(20 downto 0) => s_axi_rdata(20 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_0_0_axi_gpio is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 19 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 19 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 19 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of system_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of system_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of system_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of system_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of system_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of system_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of system_axi_gpio_0_0_axi_gpio : entity is "artix7";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of system_axi_gpio_0_0_axi_gpio : entity is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of system_axi_gpio_0_0_axi_gpio : entity is 20;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of system_axi_gpio_0_0_axi_gpio : entity is 1;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of system_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of system_axi_gpio_0_0_axi_gpio : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_axi_gpio_0_0_axi_gpio : entity is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of system_axi_gpio_0_0_axi_gpio : entity is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of system_axi_gpio_0_0_axi_gpio : entity is -1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_0_0_axi_gpio : entity is "axi_gpio";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_gpio_0_0_axi_gpio : entity is "yes";
attribute ip_group : string;
attribute ip_group of system_axi_gpio_0_0_axi_gpio : entity is "LOGICORE";
end system_axi_gpio_0_0_axi_gpio;
architecture STRUCTURE of system_axi_gpio_0_0_axi_gpio is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_28 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_29 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_30 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_31 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_32 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_33 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_34 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_35 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_36 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_37 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_38 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_39 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_40 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_41 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_42 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_43 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_44 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_45 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_46 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_48 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_49 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_57 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_59 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_61 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_62 : STD_LOGIC;
signal DBus_Reg : STD_LOGIC_VECTOR ( 0 to 19 );
signal GPIO_DBus_i : STD_LOGIC_VECTOR ( 12 to 12 );
signal GPIO_intr : STD_LOGIC;
signal GPIO_xferAck_i : STD_LOGIC;
signal IP2INTC_Irpt_i : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\ : STD_LOGIC;
signal Read_Reg_Rst : STD_LOGIC;
signal bus2ip_cs : STD_LOGIC_VECTOR ( 1 to 1 );
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_reset_i_1_n_0 : STD_LOGIC;
signal bus2ip_rnw : STD_LOGIC;
signal gpio_Data_In : STD_LOGIC_VECTOR ( 0 to 19 );
signal \^gpio_io_t\ : STD_LOGIC_VECTOR ( 19 downto 0 );
signal gpio_xferAck_Reg : STD_LOGIC;
signal interrupt_wrce_strb : STD_LOGIC;
signal intr2bus_rdack0 : STD_LOGIC;
signal intr_rd_ce_or_reduce : STD_LOGIC;
signal intr_wr_ce_or_reduce : STD_LOGIC;
signal ip2Bus_RdAck_intr_reg_hole : STD_LOGIC;
signal ip2Bus_RdAck_intr_reg_hole_d1 : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole_d1 : STD_LOGIC;
signal ip2bus_data : STD_LOGIC_VECTOR ( 12 to 31 );
signal ip2bus_data_i : STD_LOGIC_VECTOR ( 31 to 31 );
signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 0 to 31 );
signal ip2bus_rdack_i : STD_LOGIC;
signal ip2bus_rdack_i_D1 : STD_LOGIC;
signal ip2bus_wrack_i : STD_LOGIC;
signal ip2bus_wrack_i_D1 : STD_LOGIC;
signal irpt_rdack : STD_LOGIC;
signal irpt_rdack_d1 : STD_LOGIC;
signal irpt_wrack : STD_LOGIC;
signal irpt_wrack_d1 : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 31 to 31 );
signal p_0_out : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_3_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wready\ : STD_LOGIC;
attribute sigis : string;
attribute sigis of \INTR_CTRLR_GEN.ip2intc_irpt_reg\ : label is "INTR_LEVEL_HIGH";
begin
gpio2_io_o(31) <= \<const0>\;
gpio2_io_o(30) <= \<const0>\;
gpio2_io_o(29) <= \<const0>\;
gpio2_io_o(28) <= \<const0>\;
gpio2_io_o(27) <= \<const0>\;
gpio2_io_o(26) <= \<const0>\;
gpio2_io_o(25) <= \<const0>\;
gpio2_io_o(24) <= \<const0>\;
gpio2_io_o(23) <= \<const0>\;
gpio2_io_o(22) <= \<const0>\;
gpio2_io_o(21) <= \<const0>\;
gpio2_io_o(20) <= \<const0>\;
gpio2_io_o(19) <= \<const0>\;
gpio2_io_o(18) <= \<const0>\;
gpio2_io_o(17) <= \<const0>\;
gpio2_io_o(16) <= \<const0>\;
gpio2_io_o(15) <= \<const0>\;
gpio2_io_o(14) <= \<const0>\;
gpio2_io_o(13) <= \<const0>\;
gpio2_io_o(12) <= \<const0>\;
gpio2_io_o(11) <= \<const0>\;
gpio2_io_o(10) <= \<const0>\;
gpio2_io_o(9) <= \<const0>\;
gpio2_io_o(8) <= \<const0>\;
gpio2_io_o(7) <= \<const0>\;
gpio2_io_o(6) <= \<const0>\;
gpio2_io_o(5) <= \<const0>\;
gpio2_io_o(4) <= \<const0>\;
gpio2_io_o(3) <= \<const0>\;
gpio2_io_o(2) <= \<const0>\;
gpio2_io_o(1) <= \<const0>\;
gpio2_io_o(0) <= \<const0>\;
gpio2_io_t(31) <= \<const1>\;
gpio2_io_t(30) <= \<const1>\;
gpio2_io_t(29) <= \<const1>\;
gpio2_io_t(28) <= \<const1>\;
gpio2_io_t(27) <= \<const1>\;
gpio2_io_t(26) <= \<const1>\;
gpio2_io_t(25) <= \<const1>\;
gpio2_io_t(24) <= \<const1>\;
gpio2_io_t(23) <= \<const1>\;
gpio2_io_t(22) <= \<const1>\;
gpio2_io_t(21) <= \<const1>\;
gpio2_io_t(20) <= \<const1>\;
gpio2_io_t(19) <= \<const1>\;
gpio2_io_t(18) <= \<const1>\;
gpio2_io_t(17) <= \<const1>\;
gpio2_io_t(16) <= \<const1>\;
gpio2_io_t(15) <= \<const1>\;
gpio2_io_t(14) <= \<const1>\;
gpio2_io_t(13) <= \<const1>\;
gpio2_io_t(12) <= \<const1>\;
gpio2_io_t(11) <= \<const1>\;
gpio2_io_t(10) <= \<const1>\;
gpio2_io_t(9) <= \<const1>\;
gpio2_io_t(8) <= \<const1>\;
gpio2_io_t(7) <= \<const1>\;
gpio2_io_t(6) <= \<const1>\;
gpio2_io_t(5) <= \<const1>\;
gpio2_io_t(4) <= \<const1>\;
gpio2_io_t(3) <= \<const1>\;
gpio2_io_t(2) <= \<const1>\;
gpio2_io_t(1) <= \<const1>\;
gpio2_io_t(0) <= \<const1>\;
gpio_io_t(19 downto 0) <= \^gpio_io_t\(19 downto 0);
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \^s_axi_rdata\(31);
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19 downto 0) <= \^s_axi_rdata\(19 downto 0);
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI_LITE_IPIF_I: entity work.system_axi_gpio_0_0_axi_lite_ipif
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
D(19) => DBus_Reg(0),
D(18) => DBus_Reg(1),
D(17) => DBus_Reg(2),
D(16) => DBus_Reg(3),
D(15) => DBus_Reg(4),
D(14) => DBus_Reg(5),
D(13) => DBus_Reg(6),
D(12) => DBus_Reg(7),
D(11) => DBus_Reg(8),
D(10) => DBus_Reg(9),
D(9) => DBus_Reg(10),
D(8) => DBus_Reg(11),
D(7) => DBus_Reg(12),
D(6) => DBus_Reg(13),
D(5) => DBus_Reg(14),
D(4) => DBus_Reg(15),
D(3) => DBus_Reg(16),
D(2) => DBus_Reg(17),
D(1) => DBus_Reg(18),
D(0) => DBus_Reg(19),
E(0) => AXI_LITE_IPIF_I_n_48,
GPIO_DBus_i(0) => GPIO_DBus_i(12),
GPIO_xferAck_i => GPIO_xferAck_i,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => AXI_LITE_IPIF_I_n_57,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => AXI_LITE_IPIF_I_n_59,
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[22]\ => AXI_LITE_IPIF_I_n_37,
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[23]\ => AXI_LITE_IPIF_I_n_36,
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[24]\ => AXI_LITE_IPIF_I_n_35,
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[25]\ => AXI_LITE_IPIF_I_n_34,
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[26]\ => AXI_LITE_IPIF_I_n_33,
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[27]\ => AXI_LITE_IPIF_I_n_32,
\Not_Dual.READ_REG_GEN[16].GPIO_DBus_i_reg[28]\ => AXI_LITE_IPIF_I_n_31,
\Not_Dual.READ_REG_GEN[17].GPIO_DBus_i_reg[29]\ => AXI_LITE_IPIF_I_n_30,
\Not_Dual.READ_REG_GEN[18].GPIO_DBus_i_reg[30]\ => AXI_LITE_IPIF_I_n_29,
\Not_Dual.READ_REG_GEN[19].GPIO_DBus_i_reg[31]\ => AXI_LITE_IPIF_I_n_28,
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[13]\ => AXI_LITE_IPIF_I_n_46,
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[14]\ => AXI_LITE_IPIF_I_n_45,
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[15]\ => AXI_LITE_IPIF_I_n_44,
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[16]\ => AXI_LITE_IPIF_I_n_43,
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[17]\ => AXI_LITE_IPIF_I_n_42,
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[18]\ => AXI_LITE_IPIF_I_n_41,
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[19]\ => AXI_LITE_IPIF_I_n_40,
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[20]\ => AXI_LITE_IPIF_I_n_39,
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[21]\ => AXI_LITE_IPIF_I_n_38,
\Not_Dual.gpio_Data_Out_reg[0]\(0) => AXI_LITE_IPIF_I_n_49,
Q(19) => gpio_Data_In(0),
Q(18) => gpio_Data_In(1),
Q(17) => gpio_Data_In(2),
Q(16) => gpio_Data_In(3),
Q(15) => gpio_Data_In(4),
Q(14) => gpio_Data_In(5),
Q(13) => gpio_Data_In(6),
Q(12) => gpio_Data_In(7),
Q(11) => gpio_Data_In(8),
Q(10) => gpio_Data_In(9),
Q(9) => gpio_Data_In(10),
Q(8) => gpio_Data_In(11),
Q(7) => gpio_Data_In(12),
Q(6) => gpio_Data_In(13),
Q(5) => gpio_Data_In(14),
Q(4) => gpio_Data_In(15),
Q(3) => gpio_Data_In(16),
Q(2) => gpio_Data_In(17),
Q(1) => gpio_Data_In(18),
Q(0) => gpio_Data_In(19),
Read_Reg_Rst => Read_Reg_Rst,
bus2ip_cs(0) => bus2ip_cs(1),
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
gpio_io_t(19 downto 0) => \^gpio_io_t\(19 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_rd_ce_or_reduce => intr_rd_ce_or_reduce,
intr_wr_ce_or_reduce => intr_wr_ce_or_reduce,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2bus_data(0) => ip2bus_data(31),
\ip2bus_data_i_D1_reg[0]\(1) => p_0_out(0),
\ip2bus_data_i_D1_reg[0]\(0) => ip2bus_data_i(31),
\ip2bus_data_i_D1_reg[0]_0\(20) => ip2bus_data_i_D1(0),
\ip2bus_data_i_D1_reg[0]_0\(19) => ip2bus_data_i_D1(12),
\ip2bus_data_i_D1_reg[0]_0\(18) => ip2bus_data_i_D1(13),
\ip2bus_data_i_D1_reg[0]_0\(17) => ip2bus_data_i_D1(14),
\ip2bus_data_i_D1_reg[0]_0\(16) => ip2bus_data_i_D1(15),
\ip2bus_data_i_D1_reg[0]_0\(15) => ip2bus_data_i_D1(16),
\ip2bus_data_i_D1_reg[0]_0\(14) => ip2bus_data_i_D1(17),
\ip2bus_data_i_D1_reg[0]_0\(13) => ip2bus_data_i_D1(18),
\ip2bus_data_i_D1_reg[0]_0\(12) => ip2bus_data_i_D1(19),
\ip2bus_data_i_D1_reg[0]_0\(11) => ip2bus_data_i_D1(20),
\ip2bus_data_i_D1_reg[0]_0\(10) => ip2bus_data_i_D1(21),
\ip2bus_data_i_D1_reg[0]_0\(9) => ip2bus_data_i_D1(22),
\ip2bus_data_i_D1_reg[0]_0\(8) => ip2bus_data_i_D1(23),
\ip2bus_data_i_D1_reg[0]_0\(7) => ip2bus_data_i_D1(24),
\ip2bus_data_i_D1_reg[0]_0\(6) => ip2bus_data_i_D1(25),
\ip2bus_data_i_D1_reg[0]_0\(5) => ip2bus_data_i_D1(26),
\ip2bus_data_i_D1_reg[0]_0\(4) => ip2bus_data_i_D1(27),
\ip2bus_data_i_D1_reg[0]_0\(3) => ip2bus_data_i_D1(28),
\ip2bus_data_i_D1_reg[0]_0\(2) => ip2bus_data_i_D1(29),
\ip2bus_data_i_D1_reg[0]_0\(1) => ip2bus_data_i_D1(30),
\ip2bus_data_i_D1_reg[0]_0\(0) => ip2bus_data_i_D1(31),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
\ip_irpt_enable_reg_reg[0]\ => AXI_LITE_IPIF_I_n_61,
ipif_glbl_irpt_enable_reg_reg => AXI_LITE_IPIF_I_n_62,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_0_in(0) => p_0_in(31),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
p_8_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(6 downto 0) => s_axi_araddr(8 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(6 downto 0) => s_axi_awaddr(8 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(20) => \^s_axi_rdata\(31),
s_axi_rdata(19 downto 0) => \^s_axi_rdata\(19 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I\: entity work.system_axi_gpio_0_0_interrupt_control
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\ => AXI_LITE_IPIF_I_n_62,
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\ => AXI_LITE_IPIF_I_n_61,
GPIO_intr => GPIO_intr,
GPIO_xferAck_i => GPIO_xferAck_i,
IP2INTC_Irpt_i => IP2INTC_Irpt_i,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
ip2Bus_RdAck_intr_reg_hole => ip2Bus_RdAck_intr_reg_hole,
ip2Bus_WrAck_intr_reg_hole => ip2Bus_WrAck_intr_reg_hole,
ip2bus_rdack_i => ip2bus_rdack_i,
ip2bus_wrack_i => ip2bus_wrack_i,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_0_in(0) => p_0_in(31),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
p_8_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(0) => s_axi_wdata(0)
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr_rd_ce_or_reduce,
Q => ip2Bus_RdAck_intr_reg_hole_d1,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => AXI_LITE_IPIF_I_n_57,
Q => ip2Bus_RdAck_intr_reg_hole,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr_wr_ce_or_reduce,
Q => ip2Bus_WrAck_intr_reg_hole_d1,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => AXI_LITE_IPIF_I_n_59,
Q => ip2Bus_WrAck_intr_reg_hole,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2intc_irpt_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => IP2INTC_Irpt_i,
Q => ip2intc_irpt,
R => bus2ip_reset
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
bus2ip_reset_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => bus2ip_reset_i_1_n_0
);
bus2ip_reset_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => bus2ip_reset_i_1_n_0,
Q => bus2ip_reset,
R => '0'
);
gpio_core_1: entity work.system_axi_gpio_0_0_GPIO_Core
port map (
D(19) => DBus_Reg(0),
D(18) => DBus_Reg(1),
D(17) => DBus_Reg(2),
D(16) => DBus_Reg(3),
D(15) => DBus_Reg(4),
D(14) => DBus_Reg(5),
D(13) => DBus_Reg(6),
D(12) => DBus_Reg(7),
D(11) => DBus_Reg(8),
D(10) => DBus_Reg(9),
D(9) => DBus_Reg(10),
D(8) => DBus_Reg(11),
D(7) => DBus_Reg(12),
D(6) => DBus_Reg(13),
D(5) => DBus_Reg(14),
D(4) => DBus_Reg(15),
D(3) => DBus_Reg(16),
D(2) => DBus_Reg(17),
D(1) => DBus_Reg(18),
D(0) => DBus_Reg(19),
E(0) => AXI_LITE_IPIF_I_n_49,
GPIO_DBus_i(0) => GPIO_DBus_i(12),
GPIO_intr => GPIO_intr,
GPIO_xferAck_i => GPIO_xferAck_i,
\Not_Dual.gpio_OE_reg[10]_0\ => AXI_LITE_IPIF_I_n_37,
\Not_Dual.gpio_OE_reg[11]_0\ => AXI_LITE_IPIF_I_n_36,
\Not_Dual.gpio_OE_reg[12]_0\ => AXI_LITE_IPIF_I_n_35,
\Not_Dual.gpio_OE_reg[13]_0\ => AXI_LITE_IPIF_I_n_34,
\Not_Dual.gpio_OE_reg[14]_0\ => AXI_LITE_IPIF_I_n_33,
\Not_Dual.gpio_OE_reg[15]_0\ => AXI_LITE_IPIF_I_n_32,
\Not_Dual.gpio_OE_reg[16]_0\ => AXI_LITE_IPIF_I_n_31,
\Not_Dual.gpio_OE_reg[17]_0\ => AXI_LITE_IPIF_I_n_30,
\Not_Dual.gpio_OE_reg[18]_0\ => AXI_LITE_IPIF_I_n_29,
\Not_Dual.gpio_OE_reg[19]_0\ => AXI_LITE_IPIF_I_n_28,
\Not_Dual.gpio_OE_reg[1]_0\ => AXI_LITE_IPIF_I_n_46,
\Not_Dual.gpio_OE_reg[2]_0\ => AXI_LITE_IPIF_I_n_45,
\Not_Dual.gpio_OE_reg[3]_0\ => AXI_LITE_IPIF_I_n_44,
\Not_Dual.gpio_OE_reg[4]_0\ => AXI_LITE_IPIF_I_n_43,
\Not_Dual.gpio_OE_reg[5]_0\ => AXI_LITE_IPIF_I_n_42,
\Not_Dual.gpio_OE_reg[6]_0\ => AXI_LITE_IPIF_I_n_41,
\Not_Dual.gpio_OE_reg[7]_0\ => AXI_LITE_IPIF_I_n_40,
\Not_Dual.gpio_OE_reg[8]_0\ => AXI_LITE_IPIF_I_n_39,
\Not_Dual.gpio_OE_reg[9]_0\ => AXI_LITE_IPIF_I_n_38,
Q(19) => gpio_Data_In(0),
Q(18) => gpio_Data_In(1),
Q(17) => gpio_Data_In(2),
Q(16) => gpio_Data_In(3),
Q(15) => gpio_Data_In(4),
Q(14) => gpio_Data_In(5),
Q(13) => gpio_Data_In(6),
Q(12) => gpio_Data_In(7),
Q(11) => gpio_Data_In(8),
Q(10) => gpio_Data_In(9),
Q(9) => gpio_Data_In(10),
Q(8) => gpio_Data_In(11),
Q(7) => gpio_Data_In(12),
Q(6) => gpio_Data_In(13),
Q(5) => gpio_Data_In(14),
Q(4) => gpio_Data_In(15),
Q(3) => gpio_Data_In(16),
Q(2) => gpio_Data_In(17),
Q(1) => gpio_Data_In(18),
Q(0) => gpio_Data_In(19),
Read_Reg_Rst => Read_Reg_Rst,
bus2ip_cs(0) => bus2ip_cs(1),
bus2ip_reset => bus2ip_reset,
bus2ip_rnw_i_reg(0) => AXI_LITE_IPIF_I_n_48,
gpio_io_i(19 downto 0) => gpio_io_i(19 downto 0),
gpio_io_o(19 downto 0) => gpio_io_o(19 downto 0),
gpio_io_t(19 downto 0) => \^gpio_io_t\(19 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_data(19) => ip2bus_data(12),
ip2bus_data(18) => ip2bus_data(13),
ip2bus_data(17) => ip2bus_data(14),
ip2bus_data(16) => ip2bus_data(15),
ip2bus_data(15) => ip2bus_data(16),
ip2bus_data(14) => ip2bus_data(17),
ip2bus_data(13) => ip2bus_data(18),
ip2bus_data(12) => ip2bus_data(19),
ip2bus_data(11) => ip2bus_data(20),
ip2bus_data(10) => ip2bus_data(21),
ip2bus_data(9) => ip2bus_data(22),
ip2bus_data(8) => ip2bus_data(23),
ip2bus_data(7) => ip2bus_data(24),
ip2bus_data(6) => ip2bus_data(25),
ip2bus_data(5) => ip2bus_data(26),
ip2bus_data(4) => ip2bus_data(27),
ip2bus_data(3) => ip2bus_data(28),
ip2bus_data(2) => ip2bus_data(29),
ip2bus_data(1) => ip2bus_data(30),
ip2bus_data(0) => ip2bus_data(31),
s_axi_aclk => s_axi_aclk
);
\ip2bus_data_i_D1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(0),
Q => ip2bus_data_i_D1(0),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(12),
Q => ip2bus_data_i_D1(12),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(13),
Q => ip2bus_data_i_D1(13),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(14),
Q => ip2bus_data_i_D1(14),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(15),
Q => ip2bus_data_i_D1(15),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(16),
Q => ip2bus_data_i_D1(16),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(17),
Q => ip2bus_data_i_D1(17),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(18),
Q => ip2bus_data_i_D1(18),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(19),
Q => ip2bus_data_i_D1(19),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(20),
Q => ip2bus_data_i_D1(20),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(21),
Q => ip2bus_data_i_D1(21),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(22),
Q => ip2bus_data_i_D1(22),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(23),
Q => ip2bus_data_i_D1(23),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(24),
Q => ip2bus_data_i_D1(24),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(25),
Q => ip2bus_data_i_D1(25),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(26),
Q => ip2bus_data_i_D1(26),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(27),
Q => ip2bus_data_i_D1(27),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(28),
Q => ip2bus_data_i_D1(28),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(29),
Q => ip2bus_data_i_D1(29),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(30),
Q => ip2bus_data_i_D1(30),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data_i(31),
Q => ip2bus_data_i_D1(31),
R => bus2ip_reset
);
ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_i,
Q => ip2bus_rdack_i_D1,
R => bus2ip_reset
);
ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_wrack_i,
Q => ip2bus_wrack_i_D1,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 19 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 19 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_axi_gpio_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_axi_gpio_0_0 : entity is "system_axi_gpio_0_0,axi_gpio,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_gpio_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_axi_gpio_0_0 : entity is "axi_gpio,Vivado 2016.4";
end system_axi_gpio_0_0;
architecture STRUCTURE of system_axi_gpio_0_0 is
signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of U0 : label is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of U0 : label is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of U0 : label is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of U0 : label is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of U0 : label is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of U0 : label is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of U0 : label is 20;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of U0 : label is 1;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of U0 : label is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of U0 : label is -1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
begin
U0: entity work.system_axi_gpio_0_0_axi_gpio
port map (
gpio2_io_i(31 downto 0) => B"00000000000000000000000000000000",
gpio2_io_o(31 downto 0) => NLW_U0_gpio2_io_o_UNCONNECTED(31 downto 0),
gpio2_io_t(31 downto 0) => NLW_U0_gpio2_io_t_UNCONNECTED(31 downto 0),
gpio_io_i(19 downto 0) => gpio_io_i(19 downto 0),
gpio_io_o(19 downto 0) => gpio_io_o(19 downto 0),
gpio_io_t(19 downto 0) => gpio_io_t(19 downto 0),
ip2intc_irpt => ip2intc_irpt,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
apache-2.0
|
601ede1d9e9cb7eef9cb87cdd66ff953
| 0.584487 | 2.54841 | false | false | false | false |
daniw/add
|
lab1/Ex2/FIR_1x5_load_coeff/vhd/fir_1d_trn_load.vhd
| 1 | 1,457 |
-------------------------------------------------------------------------------
-- Company : HSLU
-- Engineer : Gai, Waj
--
-- Create Date: 19-May-11
-- Project : RT Video Lab 1: Exercise 2
-- Description: 5-tap FIR filter in transposed form with loadable coefficients
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity fir_1d_trn_load is
generic
(IN_DW : integer := 8; -- Input word width
OUT_DW : integer := 19; -- Output word width
COEF_DW : integer := 7; -- coefficient word width
TAPS : integer := 5; -- # of taps + 1 output register
DELAY : integer := 8); -- output delay line
-- (to adapt latency to system architecture)
port
(ce_1 : in std_logic; -- clock enable
clk_1 : in std_logic; -- clock
load : in std_logic; -- load coeff pulse
coef : in std_logic_vector(COEF_DW-1 downto 0);
din : in std_logic_vector(IN_DW-1 downto 0);
out_data : out std_logic_vector(OUT_DW-1 downto 0)
);
end fir_1d_trn_load;
architecture Behavioral of fir_1d_trn_load is
-- Implement here:
-- * 1x5 FIR filter transposed form
-- * logic for reloading of coefficients
end Behavioral;
|
gpl-2.0
|
b834300ab5f2870e69e8186aa9043bbf
| 0.487303 | 3.948509 | false | false | false | false |
daniw/add
|
cpu/mcu.vhd
| 1 | 4,341 |
-------------------------------------------------------------------------------
-- Entity: mcu
-- Author: Waj
-------------------------------------------------------------------------------
-- Top-level description of a simple von-Neumann MCU.
-- All top-level component are instantiated here. Also, tri-state buffers for
-- bi-directional GPIO pins are described here.
-------------------------------------------------------------------------------
-- Total # of FFs: 0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity mcu is
port(rst : in std_logic;
clk : in std_logic;
-- General-Purpose I/O ports
GPIO_0 : inout std_logic_vector(DW-1 downto 0);
GPIO_1 : inout std_logic_vector(DW-1 downto 0);
GPIO_2 : inout std_logic_vector(DW-1 downto 0);
GPIO_3 : inout std_logic_vector(DW-1 downto 0);
-- Dedicated LCD port
LCD : out std_logic_vector(LCD_PW-1 downto 0)
);
end mcu;
architecture rtl of mcu is
-- CPU signals
signal cpu2bus : t_cpu2bus;
signal bus2cpu : t_bus2cpu;
-- ROM signals
signal bus2rom : t_bus2ros;
signal rom2bus : t_ros2bus;
-- ROM signals
signal bus2ram : t_bus2rws;
signal ram2bus : t_rws2bus;
-- GPIO signals
signal bus2gpio : t_bus2rws;
signal gpio2bus : t_rws2bus;
signal gpio_in : t_gpio_pin_in;
signal gpio_out : t_gpio_pin_out;
-- LCD signals
signal bus2lcd : t_bus2rws;
signal lcd2bus : t_rws2bus;
signal lcd_out : std_logic_vector(LCD_PW-1 downto 0);
begin
-----------------------------------------------------------------------------
-- Tri-state buffers for GPIO pins
-----------------------------------------------------------------------------
gpio_in.in_0 <= GPIO_0;
gpio_in.in_1 <= GPIO_1;
gpio_in.in_2 <= GPIO_2;
gpio_in.in_3 <= GPIO_3;
gen_gpin: for k in 0 to DW-1 generate
GPIO_0(k) <= gpio_out.out_0(k) when gpio_out.enb_0(k) = '1' else 'Z';
GPIO_1(k) <= gpio_out.out_1(k) when gpio_out.enb_1(k) = '1' else 'Z';
GPIO_2(k) <= gpio_out.out_2(k) when gpio_out.enb_2(k) = '1' else 'Z';
GPIO_3(k) <= gpio_out.out_3(k) when gpio_out.enb_3(k) = '1' else 'Z';
end generate;
-----------------------------------------------------------------------------
-- LCD interface pins
-----------------------------------------------------------------------------
LCD <= lcd_out;
-----------------------------------------------------------------------------
-- Instantiation of top-level components (assumed to be in library work)
-----------------------------------------------------------------------------
-- CPU ----------------------------------------------------------------------
i_cpu: entity work.cpu
port map(
rst => rst,
clk => clk,
bus_in => bus2cpu,
bus_out => cpu2bus
);
-- BUS ----------------------------------------------------------------------
i_bus: entity work.buss
port map(
rst => rst,
clk => clk,
cpu_in => cpu2bus,
cpu_out => bus2cpu,
rom_in => rom2bus,
rom_out => bus2rom,
ram_in => ram2bus,
ram_out => bus2ram,
gpio_in => gpio2bus,
gpio_out => bus2gpio,
lcd_in => lcd2bus,
lcd_out => bus2lcd
);
-- ROM ----------------------------------------------------------------------
i_rom: entity work.rom
port map(
clk => clk,
bus_in => bus2rom,
bus_out => rom2bus
);
-- RAM ----------------------------------------------------------------------
i_ram: entity work.ram
port map(
clk => clk,
bus_in => bus2ram,
bus_out => ram2bus
);
-- GPIO ---------------------------------------------------------------------
i_gpio: entity work.gpio
port map(
rst => rst,
clk => clk,
bus_in => bus2gpio,
bus_out => gpio2bus,
pin_in => gpio_in,
pin_out => gpio_out
);
-- LCD ----------------------------------------------------------------------
i_lcd: entity work.lcd
port map(
rst => rst,
clk => clk,
bus_in => bus2lcd,
bus_out => lcd2bus,
lcd_out => lcd_out
);
end rtl;
|
gpl-2.0
|
e4a5a241c4827fff538e78cc06ef91ae
| 0.403363 | 3.921409 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 2/ALU_tb.vhd
| 1 | 7,455 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ALU_tb IS
END ALU_tb;
ARCHITECTURE behavior OF ALU_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU
PORT(
Oper1 : IN std_logic_vector(31 downto 0);
Oper2 : IN std_logic_vector(31 downto 0);
ALUOP : IN std_logic_vector(5 downto 0);
C: IN std_logic;
ALURESULT : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Oper1 : std_logic_vector(31 downto 0) := (others => '0');
signal Oper2 : std_logic_vector(31 downto 0) := (others => '0');
signal ALUOP : std_logic_vector(5 downto 0) := (others => '0');
signal C : std_logic:='0';
--Outputs
signal ALURESULT : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU PORT MAP (
Oper1 => Oper1,
Oper2 => Oper2,
ALUOP => ALUOP,
C => C,
ALURESULT => ALURESULT
);
-- Stimulus process
stim_proc: process
begin
C<='1';
------------------SUB-------------------------------
ALUOP<="000111";
-- 5 - 28
Oper1<="00000000000000000000000000000101"; -- +5
Oper2<="00000000000000000000000000011100"; -- +28
wait for 20 ns;
-- 32 - 20
Oper1<="00000000000000000000000000100000";-- +32
Oper2<="00000000000000000000000000010100";-- +20
wait for 20 ns;
-- -45 - (+33)
Oper1<="11111111111111111111111111010011";-- -45
Oper2<="00000000000000000000000000100001";-- +33
wait for 20 ns;
-- -45 - (+63)
Oper1<="11111111111111111111111111010011";-- -45
Oper2<="00000000000000000000000000111111";-- +63
wait for 20 ns;
-- -45 - (-33)
Oper1<="11111111111111111111111111010011";-- -45
Oper2<="11111111111111111111111111011111";-- -33
wait for 20 ns;
-- -45 - (-63)
Oper1<="11111111111111111111111111010011";-- -45
Oper2<="11111111111111111111111111000001";-- -63
wait for 20 ns;
-- 45 - (-63)
Oper1<="00000000000000000000000000101101";-- 45
Oper2<="11111111111111111111111111000001";-- -63
wait for 20 ns;
-- 45 - (-33)
Oper1<="00000000000000000000000000101101";-- 45
Oper2<="11111111111111111111111111011111";-- -33
wait for 20 ns;
----------------SUMA----------------
ALUOP<="000110";-- 75 + 25
Oper1<="00000000000000000000000001001011";-- 75
Oper2<="00000000000000000000000000011001";-- 25
wait for 20 ns;
-- 75 + (-25)
Oper1<="00000000000000000000000001001011";-- 75
Oper2<="11111111111111111111111111100111";-- -25
wait for 20 ns;
-- 75 + (-100)
Oper1<="00000000000000000000000001001011";-- 75
Oper2<="11111111111111111111111110011100";-- -100
wait for 20 ns;
-- -75 + 25
Oper1<="11111111111111111111111110110101";-- -75
Oper2<="00000000000000000000000000011001";-- 25
wait for 20 ns;
-- -75 + 100
Oper1<="11111111111111111111111110110101";-- -75
Oper2<="00000000000000000000000001100100";-- +100
wait for 20 ns;
-- -75 + (-25)
Oper1<="11111111111111111111111110110101";-- -75
Oper2<="11111111111111111111111111100111";-- -25
wait for 20 ns;
-- -75 + (-100)
Oper1<="11111111111111111111111110110101";-- -75
Oper2<="11111111111111111111111110011100";-- -100
wait for 20 ns;
-------------------OR--------------------
ALUOP<="000010";
Oper1<="11111111111111111100011110110101";
Oper2<="00000011101010001001010000001100";
wait for 20 ns;
-----------------orn---------------------
ALUOP<="000011";
wait for 20 ns;
-----------------xor-------------------
ALUOP<="000100";
wait for 20 ns;
-----------------xnor-------------------
ALUOP<="000101";
wait for 20 ns;
-----------------and-------------------
ALUOP<="000000";
wait for 20 ns;
-----------------andn-------------------
ALUOP<="000001";
wait for 20 ns;
-----------------SLL------------------
ALUOP<="001000";
Oper1<="00000000000000011110001110011011";
Oper2<="00000000000000000000000000000011";
wait for 20 ns;
-----------------SRL-------------------
ALUOP<="001001";
Oper1<="11111000000000011110001110011011";
Oper2<="00000000000000000000000000000011";
wait for 20 ns;
-----------------SRA----------------------
ALUOP<="001010";
Oper1<="11111000000000011110001110011011";
Oper2<="00000000000000000000000000000011";
wait for 20 ns;
-----------------ANDcc---------------------
ALUOP<="001011";
Oper1<="00000111111000000010010000000111";
Oper2<="00000111111111000000000000000011";
wait for 20 ns;
-----------------ANDNcc--------------------
ALUOP<="001100";
Oper1<="00000000111111111000000010100000";
Oper2<="00001111111100000000000000000011";
wait for 20 ns;
-----------------ORcc----------------------
ALUOP<="001101";
Oper1<="00000001111111111100000000000000";
Oper2<="11111000000000111111110000000000";
wait for 20 ns;
-----------------ORNcc---------------------
ALUOP<="001110";
Oper1<="00000011111111100000011111000000";
Oper2<="00000000001111111111111100000000";
wait for 20 ns;
-----------------XORcc---------------------
ALUOP<="001111";
Oper1<="00001000100000000111111111100000";
Oper2<="00000001111110000110000011000000";
wait for 20 ns;
-----------------XNORcc--------------------
ALUOP<="010000";
Oper1<="00000001111111111100000000000111";
Oper2<="11110000001111100000110001000000";
wait for 20 ns;
-----------------ADDcc---------------------
ALUOP<="010001";
Oper1<="00000000000000000000000001101000";
Oper2<="00000000000000000000000000000101";
wait for 20 ns;
C<='0';
wait for 20 ns;
-----------------ADDX----------------------
ALUOP<="010010";
Oper1<="00000000000000100101010000000000";
Oper2<="00000000000000000000000100000011";
wait for 20 ns;
C<='1';
wait for 20 ns;
-----------------ADDXcc--------------------
ALUOP<="010011";
Oper1<="00000000000000000000000000101010";
Oper2<="00000000000000000000000000001101";
wait for 20 ns;
C<='0';
wait for 20 ns;
-----------------SUBcc---------------------
ALUOP<="010100";
Oper1<="00000000000000000000000100000000";
Oper2<="00000000000000000000000000010000";
wait for 20 ns;
C<='1';
wait for 20 ns;
-----------------SUBX----------------------
ALUOP<="010101";
Oper1<="00000000000000000000000000001111";
Oper2<="00000000000000000000000000001011";
wait for 20 ns;
C<='0';
wait for 20 ns;
-----------------SUBXcc--------------------
ALUOP<="010110";
Oper1<="00000000000000000000000100011011";
Oper2<="00000000000000000000000000000011";
wait for 20 ns;
C<='1';
wait for 20 ns;
-----------------SAVE----------------------
ALUOP<="010111";
Oper1<="00000000000000000000000000011011";
Oper2<="00000000000000000000000000001100";
wait for 20 ns;
-----------------RESTORE-------------------
ALUOP<="011000";
Oper1<="00000000000000000000000000010000";
Oper2<="00000000000000000000000000000111";
wait for 20 ns;
---------------Instrucciones no definidas--------------------------
ALUOP<="111111";
Oper1<="00000000000000011110001110011011";
Oper2<="00000000000000000000000011111111";
wait;
end process;
END;
|
mit
|
f87c90c650459bc7a4ba618e39988652
| 0.560966 | 4.515445 | false | false | false | false |
jeffmagina/ECE368
|
Lab2/RISC Machine SSEG_for lab/RISC_MACHINE_FOR_LAB.vhd
| 1 | 2,550 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Jeffrey Magina and Jon Leidhold
--
-- Create Date: SPRING 2015
-- Module Name: RISC_MACHINE
-- Project Name: RISC_MACHINE
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: RISC Machine possibly for future
-- design of UMD RISC Machine. Takes in a 0 - F
-- on the ASCII_DATA line outputs, it to the BUFFER
-- concatenated together to form the Instruction
-- which is sent to the ALU to perform a function and
-- outputs it to the seven segment display
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.all;
entity RISC_MACHINE is
Port( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
PS2_CLK : inout STD_LOGIC;
PS2_DATA : inout STD_LOGIC;
SEG : out STD_LOGIC_VECTOR (6 downto 0);
DP : out STD_LOGIC;
AN : out STD_LOGIC_VECTOR (3 downto 0);
LED : out STD_LOGIC_VECTOR (3 downto 0));
end RISC_MACHINE;
architecture Structural of RISC_MACHINE is
signal RD,WE :STD_LOGIC;
signal KEY_DATA : STD_LOGIC_VECTOR (7 downto 0);
signal TO_SEG : STD_LOGIC_VECTOR(7 downto 0);
signal TO_ALU : STD_LOGIC_VECTOR(19 downto 0);
signal RegA : STD_LOGIC_VECTOR(7 downto 0);
signal cen : STD_LOGIC := '0';
signal enl : STD_LOGIC := '1';
signal dpc : STD_LOGIC_VECTOR (3 downto 0) := "1111";
begin
Keyboard: entity work.KEYBOARD_CONTROLLER
Port MAP ( CLK => CLK,
RST => RST,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
ASCII_OUT => KEY_DATA,
ASCII_RD => RD,
ASCII_WE => WE);
Debug_Unit: entity work.ASCII_BUFFER
port MAP(
ASCII_DATA => KEY_DATA,
ASCII_RD => RD,
ASCII_WE => WE,
CLK => CLK,
RST => RST,
ASCII_BUFF => TO_ALU);
SSeg: entity work.SSegDriver
port map( CLK => CLK,
RST => '0',
EN => enl,
SEG_0 => "0000",
SEG_1 => "0000",
SEG_2 => TO_SEG(7 downto 4),
SEG_3 => TO_SEG(3 downto 0),
DP_CTRL => dpc,
COL_EN => cen,
SEG_OUT => SEG,
DP_OUT => DP,
AN_OUT => AN);
ALU: entity work.ALU
Port map ( CLK => CLK,
RA => TO_ALU(15 downto 8),
RB => TO_ALU(7 downto 0),
OPCODE => TO_ALU(19 downto 16),
CCR => LED(3 downto 0),
ALU_OUT => TO_SEG(7 downto 0));
end Structural;
|
mit
|
4a81b13402d393b8f6a738a3fec48a2b
| 0.56 | 3.373016 | false | false | false | false |
daniw/add
|
edk/IVK_HW/t01_hello/hdl/system.vhd
| 1 | 113,715 |
-------------------------------------------------------------------------------
-- system.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
fpga_0_RS232_USB_RX_pin : in std_logic;
fpga_0_RS232_USB_TX_pin : out std_logic;
fpga_0_LEDs_8Bit_GPIO_IO_O_pin : out std_logic_vector(0 to 7);
fpga_0_Push_Buttons_3Bit_GPIO_IO_I_pin : in std_logic_vector(0 to 2);
fpga_0_clk_1_sys_clk_pin : in std_logic;
fpga_0_rst_1_sys_rst_pin : in std_logic
);
end system;
architecture STRUCTURE of system is
component microblaze_0_wrapper is
port (
CLK : in std_logic;
RESET : in std_logic;
MB_RESET : in std_logic;
INTERRUPT : in std_logic;
EXT_BRK : in std_logic;
EXT_NM_BRK : in std_logic;
DBG_STOP : in std_logic;
MB_Halted : out std_logic;
MB_Error : out std_logic;
LOCKSTEP_MASTER_OUT : out std_logic_vector(0 to 4095);
LOCKSTEP_SLAVE_IN : in std_logic_vector(0 to 4095);
LOCKSTEP_OUT : out std_logic_vector(0 to 4095);
INSTR : in std_logic_vector(0 to 31);
IREADY : in std_logic;
IWAIT : in std_logic;
ICE : in std_logic;
IUE : in std_logic;
INSTR_ADDR : out std_logic_vector(0 to 31);
IFETCH : out std_logic;
I_AS : out std_logic;
IPLB_M_ABort : out std_logic;
IPLB_M_ABus : out std_logic_vector(0 to 31);
IPLB_M_UABus : out std_logic_vector(0 to 31);
IPLB_M_BE : out std_logic_vector(0 to 3);
IPLB_M_busLock : out std_logic;
IPLB_M_lockErr : out std_logic;
IPLB_M_MSize : out std_logic_vector(0 to 1);
IPLB_M_priority : out std_logic_vector(0 to 1);
IPLB_M_rdBurst : out std_logic;
IPLB_M_request : out std_logic;
IPLB_M_RNW : out std_logic;
IPLB_M_size : out std_logic_vector(0 to 3);
IPLB_M_TAttribute : out std_logic_vector(0 to 15);
IPLB_M_type : out std_logic_vector(0 to 2);
IPLB_M_wrBurst : out std_logic;
IPLB_M_wrDBus : out std_logic_vector(0 to 31);
IPLB_MBusy : in std_logic;
IPLB_MRdErr : in std_logic;
IPLB_MWrErr : in std_logic;
IPLB_MIRQ : in std_logic;
IPLB_MWrBTerm : in std_logic;
IPLB_MWrDAck : in std_logic;
IPLB_MAddrAck : in std_logic;
IPLB_MRdBTerm : in std_logic;
IPLB_MRdDAck : in std_logic;
IPLB_MRdDBus : in std_logic_vector(0 to 31);
IPLB_MRdWdAddr : in std_logic_vector(0 to 3);
IPLB_MRearbitrate : in std_logic;
IPLB_MSSize : in std_logic_vector(0 to 1);
IPLB_MTimeout : in std_logic;
DATA_READ : in std_logic_vector(0 to 31);
DREADY : in std_logic;
DWAIT : in std_logic;
DCE : in std_logic;
DUE : in std_logic;
DATA_WRITE : out std_logic_vector(0 to 31);
DATA_ADDR : out std_logic_vector(0 to 31);
D_AS : out std_logic;
READ_STROBE : out std_logic;
WRITE_STROBE : out std_logic;
BYTE_ENABLE : out std_logic_vector(0 to 3);
DPLB_M_ABort : out std_logic;
DPLB_M_ABus : out std_logic_vector(0 to 31);
DPLB_M_UABus : out std_logic_vector(0 to 31);
DPLB_M_BE : out std_logic_vector(0 to 3);
DPLB_M_busLock : out std_logic;
DPLB_M_lockErr : out std_logic;
DPLB_M_MSize : out std_logic_vector(0 to 1);
DPLB_M_priority : out std_logic_vector(0 to 1);
DPLB_M_rdBurst : out std_logic;
DPLB_M_request : out std_logic;
DPLB_M_RNW : out std_logic;
DPLB_M_size : out std_logic_vector(0 to 3);
DPLB_M_TAttribute : out std_logic_vector(0 to 15);
DPLB_M_type : out std_logic_vector(0 to 2);
DPLB_M_wrBurst : out std_logic;
DPLB_M_wrDBus : out std_logic_vector(0 to 31);
DPLB_MBusy : in std_logic;
DPLB_MRdErr : in std_logic;
DPLB_MWrErr : in std_logic;
DPLB_MIRQ : in std_logic;
DPLB_MWrBTerm : in std_logic;
DPLB_MWrDAck : in std_logic;
DPLB_MAddrAck : in std_logic;
DPLB_MRdBTerm : in std_logic;
DPLB_MRdDAck : in std_logic;
DPLB_MRdDBus : in std_logic_vector(0 to 31);
DPLB_MRdWdAddr : in std_logic_vector(0 to 3);
DPLB_MRearbitrate : in std_logic;
DPLB_MSSize : in std_logic_vector(0 to 1);
DPLB_MTimeout : in std_logic;
M_AXI_IP_AWID : out std_logic_vector(0 downto 0);
M_AXI_IP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_AWLOCK : out std_logic;
M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_AWVALID : out std_logic;
M_AXI_IP_AWREADY : in std_logic;
M_AXI_IP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IP_WLAST : out std_logic;
M_AXI_IP_WVALID : out std_logic;
M_AXI_IP_WREADY : in std_logic;
M_AXI_IP_BID : in std_logic_vector(0 downto 0);
M_AXI_IP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_BVALID : in std_logic;
M_AXI_IP_BREADY : out std_logic;
M_AXI_IP_ARID : out std_logic_vector(0 downto 0);
M_AXI_IP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_ARLOCK : out std_logic;
M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_ARVALID : out std_logic;
M_AXI_IP_ARREADY : in std_logic;
M_AXI_IP_RID : in std_logic_vector(0 downto 0);
M_AXI_IP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_RLAST : in std_logic;
M_AXI_IP_RVALID : in std_logic;
M_AXI_IP_RREADY : out std_logic;
M_AXI_DP_AWID : out std_logic_vector(0 downto 0);
M_AXI_DP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_AWLOCK : out std_logic;
M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_AWVALID : out std_logic;
M_AXI_DP_AWREADY : in std_logic;
M_AXI_DP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DP_WLAST : out std_logic;
M_AXI_DP_WVALID : out std_logic;
M_AXI_DP_WREADY : in std_logic;
M_AXI_DP_BID : in std_logic_vector(0 downto 0);
M_AXI_DP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_BVALID : in std_logic;
M_AXI_DP_BREADY : out std_logic;
M_AXI_DP_ARID : out std_logic_vector(0 downto 0);
M_AXI_DP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_ARLOCK : out std_logic;
M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_ARVALID : out std_logic;
M_AXI_DP_ARREADY : in std_logic;
M_AXI_DP_RID : in std_logic_vector(0 downto 0);
M_AXI_DP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_RLAST : in std_logic;
M_AXI_DP_RVALID : in std_logic;
M_AXI_DP_RREADY : out std_logic;
M_AXI_IC_AWID : out std_logic_vector(0 downto 0);
M_AXI_IC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_AWLOCK : out std_logic;
M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_AWVALID : out std_logic;
M_AXI_IC_AWREADY : in std_logic;
M_AXI_IC_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_IC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IC_WLAST : out std_logic;
M_AXI_IC_WVALID : out std_logic;
M_AXI_IC_WREADY : in std_logic;
M_AXI_IC_WUSER : out std_logic_vector(0 downto 0);
M_AXI_IC_BID : in std_logic_vector(0 downto 0);
M_AXI_IC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_BVALID : in std_logic;
M_AXI_IC_BREADY : out std_logic;
M_AXI_IC_BUSER : in std_logic_vector(0 downto 0);
M_AXI_IC_ARID : out std_logic_vector(0 downto 0);
M_AXI_IC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_ARLOCK : out std_logic;
M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_ARVALID : out std_logic;
M_AXI_IC_ARREADY : in std_logic;
M_AXI_IC_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_IC_RID : in std_logic_vector(0 downto 0);
M_AXI_IC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_RLAST : in std_logic;
M_AXI_IC_RVALID : in std_logic;
M_AXI_IC_RREADY : out std_logic;
M_AXI_IC_RUSER : in std_logic_vector(0 downto 0);
M_AXI_DC_AWID : out std_logic_vector(0 downto 0);
M_AXI_DC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_AWLOCK : out std_logic;
M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_AWVALID : out std_logic;
M_AXI_DC_AWREADY : in std_logic;
M_AXI_DC_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_DC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DC_WLAST : out std_logic;
M_AXI_DC_WVALID : out std_logic;
M_AXI_DC_WREADY : in std_logic;
M_AXI_DC_WUSER : out std_logic_vector(0 downto 0);
M_AXI_DC_BID : in std_logic_vector(0 downto 0);
M_AXI_DC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_BVALID : in std_logic;
M_AXI_DC_BREADY : out std_logic;
M_AXI_DC_BUSER : in std_logic_vector(0 downto 0);
M_AXI_DC_ARID : out std_logic_vector(0 downto 0);
M_AXI_DC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_ARLOCK : out std_logic;
M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_ARVALID : out std_logic;
M_AXI_DC_ARREADY : in std_logic;
M_AXI_DC_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_DC_RID : in std_logic_vector(0 downto 0);
M_AXI_DC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_RLAST : in std_logic;
M_AXI_DC_RVALID : in std_logic;
M_AXI_DC_RREADY : out std_logic;
M_AXI_DC_RUSER : in std_logic_vector(0 downto 0);
DBG_CLK : in std_logic;
DBG_TDI : in std_logic;
DBG_TDO : out std_logic;
DBG_REG_EN : in std_logic_vector(0 to 7);
DBG_SHIFT : in std_logic;
DBG_CAPTURE : in std_logic;
DBG_UPDATE : in std_logic;
DEBUG_RST : in std_logic;
Trace_Instruction : out std_logic_vector(0 to 31);
Trace_Valid_Instr : out std_logic;
Trace_PC : out std_logic_vector(0 to 31);
Trace_Reg_Write : out std_logic;
Trace_Reg_Addr : out std_logic_vector(0 to 4);
Trace_MSR_Reg : out std_logic_vector(0 to 14);
Trace_PID_Reg : out std_logic_vector(0 to 7);
Trace_New_Reg_Value : out std_logic_vector(0 to 31);
Trace_Exception_Taken : out std_logic;
Trace_Exception_Kind : out std_logic_vector(0 to 4);
Trace_Jump_Taken : out std_logic;
Trace_Delay_Slot : out std_logic;
Trace_Data_Address : out std_logic_vector(0 to 31);
Trace_Data_Access : out std_logic;
Trace_Data_Read : out std_logic;
Trace_Data_Write : out std_logic;
Trace_Data_Write_Value : out std_logic_vector(0 to 31);
Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
Trace_DCache_Req : out std_logic;
Trace_DCache_Hit : out std_logic;
Trace_DCache_Rdy : out std_logic;
Trace_DCache_Read : out std_logic;
Trace_ICache_Req : out std_logic;
Trace_ICache_Hit : out std_logic;
Trace_ICache_Rdy : out std_logic;
Trace_OF_PipeRun : out std_logic;
Trace_EX_PipeRun : out std_logic;
Trace_MEM_PipeRun : out std_logic;
Trace_MB_Halted : out std_logic;
Trace_Jump_Hit : out std_logic;
FSL0_S_CLK : out std_logic;
FSL0_S_READ : out std_logic;
FSL0_S_DATA : in std_logic_vector(0 to 31);
FSL0_S_CONTROL : in std_logic;
FSL0_S_EXISTS : in std_logic;
FSL0_M_CLK : out std_logic;
FSL0_M_WRITE : out std_logic;
FSL0_M_DATA : out std_logic_vector(0 to 31);
FSL0_M_CONTROL : out std_logic;
FSL0_M_FULL : in std_logic;
FSL1_S_CLK : out std_logic;
FSL1_S_READ : out std_logic;
FSL1_S_DATA : in std_logic_vector(0 to 31);
FSL1_S_CONTROL : in std_logic;
FSL1_S_EXISTS : in std_logic;
FSL1_M_CLK : out std_logic;
FSL1_M_WRITE : out std_logic;
FSL1_M_DATA : out std_logic_vector(0 to 31);
FSL1_M_CONTROL : out std_logic;
FSL1_M_FULL : in std_logic;
FSL2_S_CLK : out std_logic;
FSL2_S_READ : out std_logic;
FSL2_S_DATA : in std_logic_vector(0 to 31);
FSL2_S_CONTROL : in std_logic;
FSL2_S_EXISTS : in std_logic;
FSL2_M_CLK : out std_logic;
FSL2_M_WRITE : out std_logic;
FSL2_M_DATA : out std_logic_vector(0 to 31);
FSL2_M_CONTROL : out std_logic;
FSL2_M_FULL : in std_logic;
FSL3_S_CLK : out std_logic;
FSL3_S_READ : out std_logic;
FSL3_S_DATA : in std_logic_vector(0 to 31);
FSL3_S_CONTROL : in std_logic;
FSL3_S_EXISTS : in std_logic;
FSL3_M_CLK : out std_logic;
FSL3_M_WRITE : out std_logic;
FSL3_M_DATA : out std_logic_vector(0 to 31);
FSL3_M_CONTROL : out std_logic;
FSL3_M_FULL : in std_logic;
FSL4_S_CLK : out std_logic;
FSL4_S_READ : out std_logic;
FSL4_S_DATA : in std_logic_vector(0 to 31);
FSL4_S_CONTROL : in std_logic;
FSL4_S_EXISTS : in std_logic;
FSL4_M_CLK : out std_logic;
FSL4_M_WRITE : out std_logic;
FSL4_M_DATA : out std_logic_vector(0 to 31);
FSL4_M_CONTROL : out std_logic;
FSL4_M_FULL : in std_logic;
FSL5_S_CLK : out std_logic;
FSL5_S_READ : out std_logic;
FSL5_S_DATA : in std_logic_vector(0 to 31);
FSL5_S_CONTROL : in std_logic;
FSL5_S_EXISTS : in std_logic;
FSL5_M_CLK : out std_logic;
FSL5_M_WRITE : out std_logic;
FSL5_M_DATA : out std_logic_vector(0 to 31);
FSL5_M_CONTROL : out std_logic;
FSL5_M_FULL : in std_logic;
FSL6_S_CLK : out std_logic;
FSL6_S_READ : out std_logic;
FSL6_S_DATA : in std_logic_vector(0 to 31);
FSL6_S_CONTROL : in std_logic;
FSL6_S_EXISTS : in std_logic;
FSL6_M_CLK : out std_logic;
FSL6_M_WRITE : out std_logic;
FSL6_M_DATA : out std_logic_vector(0 to 31);
FSL6_M_CONTROL : out std_logic;
FSL6_M_FULL : in std_logic;
FSL7_S_CLK : out std_logic;
FSL7_S_READ : out std_logic;
FSL7_S_DATA : in std_logic_vector(0 to 31);
FSL7_S_CONTROL : in std_logic;
FSL7_S_EXISTS : in std_logic;
FSL7_M_CLK : out std_logic;
FSL7_M_WRITE : out std_logic;
FSL7_M_DATA : out std_logic_vector(0 to 31);
FSL7_M_CONTROL : out std_logic;
FSL7_M_FULL : in std_logic;
FSL8_S_CLK : out std_logic;
FSL8_S_READ : out std_logic;
FSL8_S_DATA : in std_logic_vector(0 to 31);
FSL8_S_CONTROL : in std_logic;
FSL8_S_EXISTS : in std_logic;
FSL8_M_CLK : out std_logic;
FSL8_M_WRITE : out std_logic;
FSL8_M_DATA : out std_logic_vector(0 to 31);
FSL8_M_CONTROL : out std_logic;
FSL8_M_FULL : in std_logic;
FSL9_S_CLK : out std_logic;
FSL9_S_READ : out std_logic;
FSL9_S_DATA : in std_logic_vector(0 to 31);
FSL9_S_CONTROL : in std_logic;
FSL9_S_EXISTS : in std_logic;
FSL9_M_CLK : out std_logic;
FSL9_M_WRITE : out std_logic;
FSL9_M_DATA : out std_logic_vector(0 to 31);
FSL9_M_CONTROL : out std_logic;
FSL9_M_FULL : in std_logic;
FSL10_S_CLK : out std_logic;
FSL10_S_READ : out std_logic;
FSL10_S_DATA : in std_logic_vector(0 to 31);
FSL10_S_CONTROL : in std_logic;
FSL10_S_EXISTS : in std_logic;
FSL10_M_CLK : out std_logic;
FSL10_M_WRITE : out std_logic;
FSL10_M_DATA : out std_logic_vector(0 to 31);
FSL10_M_CONTROL : out std_logic;
FSL10_M_FULL : in std_logic;
FSL11_S_CLK : out std_logic;
FSL11_S_READ : out std_logic;
FSL11_S_DATA : in std_logic_vector(0 to 31);
FSL11_S_CONTROL : in std_logic;
FSL11_S_EXISTS : in std_logic;
FSL11_M_CLK : out std_logic;
FSL11_M_WRITE : out std_logic;
FSL11_M_DATA : out std_logic_vector(0 to 31);
FSL11_M_CONTROL : out std_logic;
FSL11_M_FULL : in std_logic;
FSL12_S_CLK : out std_logic;
FSL12_S_READ : out std_logic;
FSL12_S_DATA : in std_logic_vector(0 to 31);
FSL12_S_CONTROL : in std_logic;
FSL12_S_EXISTS : in std_logic;
FSL12_M_CLK : out std_logic;
FSL12_M_WRITE : out std_logic;
FSL12_M_DATA : out std_logic_vector(0 to 31);
FSL12_M_CONTROL : out std_logic;
FSL12_M_FULL : in std_logic;
FSL13_S_CLK : out std_logic;
FSL13_S_READ : out std_logic;
FSL13_S_DATA : in std_logic_vector(0 to 31);
FSL13_S_CONTROL : in std_logic;
FSL13_S_EXISTS : in std_logic;
FSL13_M_CLK : out std_logic;
FSL13_M_WRITE : out std_logic;
FSL13_M_DATA : out std_logic_vector(0 to 31);
FSL13_M_CONTROL : out std_logic;
FSL13_M_FULL : in std_logic;
FSL14_S_CLK : out std_logic;
FSL14_S_READ : out std_logic;
FSL14_S_DATA : in std_logic_vector(0 to 31);
FSL14_S_CONTROL : in std_logic;
FSL14_S_EXISTS : in std_logic;
FSL14_M_CLK : out std_logic;
FSL14_M_WRITE : out std_logic;
FSL14_M_DATA : out std_logic_vector(0 to 31);
FSL14_M_CONTROL : out std_logic;
FSL14_M_FULL : in std_logic;
FSL15_S_CLK : out std_logic;
FSL15_S_READ : out std_logic;
FSL15_S_DATA : in std_logic_vector(0 to 31);
FSL15_S_CONTROL : in std_logic;
FSL15_S_EXISTS : in std_logic;
FSL15_M_CLK : out std_logic;
FSL15_M_WRITE : out std_logic;
FSL15_M_DATA : out std_logic_vector(0 to 31);
FSL15_M_CONTROL : out std_logic;
FSL15_M_FULL : in std_logic;
M0_AXIS_TLAST : out std_logic;
M0_AXIS_TDATA : out std_logic_vector(31 downto 0);
M0_AXIS_TVALID : out std_logic;
M0_AXIS_TREADY : in std_logic;
S0_AXIS_TLAST : in std_logic;
S0_AXIS_TDATA : in std_logic_vector(31 downto 0);
S0_AXIS_TVALID : in std_logic;
S0_AXIS_TREADY : out std_logic;
M1_AXIS_TLAST : out std_logic;
M1_AXIS_TDATA : out std_logic_vector(31 downto 0);
M1_AXIS_TVALID : out std_logic;
M1_AXIS_TREADY : in std_logic;
S1_AXIS_TLAST : in std_logic;
S1_AXIS_TDATA : in std_logic_vector(31 downto 0);
S1_AXIS_TVALID : in std_logic;
S1_AXIS_TREADY : out std_logic;
M2_AXIS_TLAST : out std_logic;
M2_AXIS_TDATA : out std_logic_vector(31 downto 0);
M2_AXIS_TVALID : out std_logic;
M2_AXIS_TREADY : in std_logic;
S2_AXIS_TLAST : in std_logic;
S2_AXIS_TDATA : in std_logic_vector(31 downto 0);
S2_AXIS_TVALID : in std_logic;
S2_AXIS_TREADY : out std_logic;
M3_AXIS_TLAST : out std_logic;
M3_AXIS_TDATA : out std_logic_vector(31 downto 0);
M3_AXIS_TVALID : out std_logic;
M3_AXIS_TREADY : in std_logic;
S3_AXIS_TLAST : in std_logic;
S3_AXIS_TDATA : in std_logic_vector(31 downto 0);
S3_AXIS_TVALID : in std_logic;
S3_AXIS_TREADY : out std_logic;
M4_AXIS_TLAST : out std_logic;
M4_AXIS_TDATA : out std_logic_vector(31 downto 0);
M4_AXIS_TVALID : out std_logic;
M4_AXIS_TREADY : in std_logic;
S4_AXIS_TLAST : in std_logic;
S4_AXIS_TDATA : in std_logic_vector(31 downto 0);
S4_AXIS_TVALID : in std_logic;
S4_AXIS_TREADY : out std_logic;
M5_AXIS_TLAST : out std_logic;
M5_AXIS_TDATA : out std_logic_vector(31 downto 0);
M5_AXIS_TVALID : out std_logic;
M5_AXIS_TREADY : in std_logic;
S5_AXIS_TLAST : in std_logic;
S5_AXIS_TDATA : in std_logic_vector(31 downto 0);
S5_AXIS_TVALID : in std_logic;
S5_AXIS_TREADY : out std_logic;
M6_AXIS_TLAST : out std_logic;
M6_AXIS_TDATA : out std_logic_vector(31 downto 0);
M6_AXIS_TVALID : out std_logic;
M6_AXIS_TREADY : in std_logic;
S6_AXIS_TLAST : in std_logic;
S6_AXIS_TDATA : in std_logic_vector(31 downto 0);
S6_AXIS_TVALID : in std_logic;
S6_AXIS_TREADY : out std_logic;
M7_AXIS_TLAST : out std_logic;
M7_AXIS_TDATA : out std_logic_vector(31 downto 0);
M7_AXIS_TVALID : out std_logic;
M7_AXIS_TREADY : in std_logic;
S7_AXIS_TLAST : in std_logic;
S7_AXIS_TDATA : in std_logic_vector(31 downto 0);
S7_AXIS_TVALID : in std_logic;
S7_AXIS_TREADY : out std_logic;
M8_AXIS_TLAST : out std_logic;
M8_AXIS_TDATA : out std_logic_vector(31 downto 0);
M8_AXIS_TVALID : out std_logic;
M8_AXIS_TREADY : in std_logic;
S8_AXIS_TLAST : in std_logic;
S8_AXIS_TDATA : in std_logic_vector(31 downto 0);
S8_AXIS_TVALID : in std_logic;
S8_AXIS_TREADY : out std_logic;
M9_AXIS_TLAST : out std_logic;
M9_AXIS_TDATA : out std_logic_vector(31 downto 0);
M9_AXIS_TVALID : out std_logic;
M9_AXIS_TREADY : in std_logic;
S9_AXIS_TLAST : in std_logic;
S9_AXIS_TDATA : in std_logic_vector(31 downto 0);
S9_AXIS_TVALID : in std_logic;
S9_AXIS_TREADY : out std_logic;
M10_AXIS_TLAST : out std_logic;
M10_AXIS_TDATA : out std_logic_vector(31 downto 0);
M10_AXIS_TVALID : out std_logic;
M10_AXIS_TREADY : in std_logic;
S10_AXIS_TLAST : in std_logic;
S10_AXIS_TDATA : in std_logic_vector(31 downto 0);
S10_AXIS_TVALID : in std_logic;
S10_AXIS_TREADY : out std_logic;
M11_AXIS_TLAST : out std_logic;
M11_AXIS_TDATA : out std_logic_vector(31 downto 0);
M11_AXIS_TVALID : out std_logic;
M11_AXIS_TREADY : in std_logic;
S11_AXIS_TLAST : in std_logic;
S11_AXIS_TDATA : in std_logic_vector(31 downto 0);
S11_AXIS_TVALID : in std_logic;
S11_AXIS_TREADY : out std_logic;
M12_AXIS_TLAST : out std_logic;
M12_AXIS_TDATA : out std_logic_vector(31 downto 0);
M12_AXIS_TVALID : out std_logic;
M12_AXIS_TREADY : in std_logic;
S12_AXIS_TLAST : in std_logic;
S12_AXIS_TDATA : in std_logic_vector(31 downto 0);
S12_AXIS_TVALID : in std_logic;
S12_AXIS_TREADY : out std_logic;
M13_AXIS_TLAST : out std_logic;
M13_AXIS_TDATA : out std_logic_vector(31 downto 0);
M13_AXIS_TVALID : out std_logic;
M13_AXIS_TREADY : in std_logic;
S13_AXIS_TLAST : in std_logic;
S13_AXIS_TDATA : in std_logic_vector(31 downto 0);
S13_AXIS_TVALID : in std_logic;
S13_AXIS_TREADY : out std_logic;
M14_AXIS_TLAST : out std_logic;
M14_AXIS_TDATA : out std_logic_vector(31 downto 0);
M14_AXIS_TVALID : out std_logic;
M14_AXIS_TREADY : in std_logic;
S14_AXIS_TLAST : in std_logic;
S14_AXIS_TDATA : in std_logic_vector(31 downto 0);
S14_AXIS_TVALID : in std_logic;
S14_AXIS_TREADY : out std_logic;
M15_AXIS_TLAST : out std_logic;
M15_AXIS_TDATA : out std_logic_vector(31 downto 0);
M15_AXIS_TVALID : out std_logic;
M15_AXIS_TREADY : in std_logic;
S15_AXIS_TLAST : in std_logic;
S15_AXIS_TDATA : in std_logic_vector(31 downto 0);
S15_AXIS_TVALID : in std_logic;
S15_AXIS_TREADY : out std_logic;
ICACHE_FSL_IN_CLK : out std_logic;
ICACHE_FSL_IN_READ : out std_logic;
ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
ICACHE_FSL_IN_CONTROL : in std_logic;
ICACHE_FSL_IN_EXISTS : in std_logic;
ICACHE_FSL_OUT_CLK : out std_logic;
ICACHE_FSL_OUT_WRITE : out std_logic;
ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
ICACHE_FSL_OUT_CONTROL : out std_logic;
ICACHE_FSL_OUT_FULL : in std_logic;
DCACHE_FSL_IN_CLK : out std_logic;
DCACHE_FSL_IN_READ : out std_logic;
DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
DCACHE_FSL_IN_CONTROL : in std_logic;
DCACHE_FSL_IN_EXISTS : in std_logic;
DCACHE_FSL_OUT_CLK : out std_logic;
DCACHE_FSL_OUT_WRITE : out std_logic;
DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
DCACHE_FSL_OUT_CONTROL : out std_logic;
DCACHE_FSL_OUT_FULL : in std_logic
);
end component;
component mb_plb_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 4);
MPLB_Rst : out std_logic_vector(0 to 1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 63);
M_UABus : in std_logic_vector(0 to 63);
M_BE : in std_logic_vector(0 to 7);
M_RNW : in std_logic_vector(0 to 1);
M_abort : in std_logic_vector(0 to 1);
M_busLock : in std_logic_vector(0 to 1);
M_TAttribute : in std_logic_vector(0 to 31);
M_lockErr : in std_logic_vector(0 to 1);
M_MSize : in std_logic_vector(0 to 3);
M_priority : in std_logic_vector(0 to 3);
M_rdBurst : in std_logic_vector(0 to 1);
M_request : in std_logic_vector(0 to 1);
M_size : in std_logic_vector(0 to 7);
M_type : in std_logic_vector(0 to 5);
M_wrBurst : in std_logic_vector(0 to 1);
M_wrDBus : in std_logic_vector(0 to 63);
Sl_addrAck : in std_logic_vector(0 to 4);
Sl_MRdErr : in std_logic_vector(0 to 9);
Sl_MWrErr : in std_logic_vector(0 to 9);
Sl_MBusy : in std_logic_vector(0 to 9);
Sl_rdBTerm : in std_logic_vector(0 to 4);
Sl_rdComp : in std_logic_vector(0 to 4);
Sl_rdDAck : in std_logic_vector(0 to 4);
Sl_rdDBus : in std_logic_vector(0 to 159);
Sl_rdWdAddr : in std_logic_vector(0 to 19);
Sl_rearbitrate : in std_logic_vector(0 to 4);
Sl_SSize : in std_logic_vector(0 to 9);
Sl_wait : in std_logic_vector(0 to 4);
Sl_wrBTerm : in std_logic_vector(0 to 4);
Sl_wrComp : in std_logic_vector(0 to 4);
Sl_wrDAck : in std_logic_vector(0 to 4);
Sl_MIRQ : in std_logic_vector(0 to 9);
PLB_MIRQ : out std_logic_vector(0 to 1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 3);
PLB_MAddrAck : out std_logic_vector(0 to 1);
PLB_MTimeout : out std_logic_vector(0 to 1);
PLB_MBusy : out std_logic_vector(0 to 1);
PLB_MRdErr : out std_logic_vector(0 to 1);
PLB_MWrErr : out std_logic_vector(0 to 1);
PLB_MRdBTerm : out std_logic_vector(0 to 1);
PLB_MRdDAck : out std_logic_vector(0 to 1);
PLB_MRdDBus : out std_logic_vector(0 to 63);
PLB_MRdWdAddr : out std_logic_vector(0 to 7);
PLB_MRearbitrate : out std_logic_vector(0 to 1);
PLB_MWrBTerm : out std_logic_vector(0 to 1);
PLB_MWrDAck : out std_logic_vector(0 to 1);
PLB_MSSize : out std_logic_vector(0 to 3);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 0);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 4);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 31);
PLB_wrPrim : out std_logic_vector(0 to 4);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 1);
PLB_SMWrErr : out std_logic_vector(0 to 1);
PLB_SMBusy : out std_logic_vector(0 to 1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 31);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
end component;
component ilmb_wrapper is
port (
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to 31);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to 31);
M_BE : in std_logic_vector(0 to 3);
Sl_DBus : in std_logic_vector(0 to 31);
Sl_Ready : in std_logic_vector(0 to 0);
Sl_Wait : in std_logic_vector(0 to 0);
Sl_UE : in std_logic_vector(0 to 0);
Sl_CE : in std_logic_vector(0 to 0);
LMB_ABus : out std_logic_vector(0 to 31);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to 31);
LMB_WriteDBus : out std_logic_vector(0 to 31);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to 3)
);
end component;
component dlmb_wrapper is
port (
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to 31);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to 31);
M_BE : in std_logic_vector(0 to 3);
Sl_DBus : in std_logic_vector(0 to 31);
Sl_Ready : in std_logic_vector(0 to 0);
Sl_Wait : in std_logic_vector(0 to 0);
Sl_UE : in std_logic_vector(0 to 0);
Sl_CE : in std_logic_vector(0 to 0);
LMB_ABus : out std_logic_vector(0 to 31);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to 31);
LMB_WriteDBus : out std_logic_vector(0 to 31);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to 3)
);
end component;
component dlmb_cntlr_wrapper is
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to 31);
LMB_WriteDBus : in std_logic_vector(0 to 31);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to 3);
Sl_DBus : out std_logic_vector(0 to 31);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to 3);
BRAM_Addr_A : out std_logic_vector(0 to 31);
BRAM_Din_A : in std_logic_vector(0 to 31);
BRAM_Dout_A : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0);
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31);
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31);
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0);
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end component;
component ilmb_cntlr_wrapper is
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to 31);
LMB_WriteDBus : in std_logic_vector(0 to 31);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to 3);
Sl_DBus : out std_logic_vector(0 to 31);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to 3);
BRAM_Addr_A : out std_logic_vector(0 to 31);
BRAM_Din_A : in std_logic_vector(0 to 31);
BRAM_Dout_A : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0);
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31);
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31);
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0);
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end component;
component lmb_bram_wrapper is
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to 3);
BRAM_Addr_A : in std_logic_vector(0 to 31);
BRAM_Din_A : out std_logic_vector(0 to 31);
BRAM_Dout_A : in std_logic_vector(0 to 31);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to 3);
BRAM_Addr_B : in std_logic_vector(0 to 31);
BRAM_Din_B : out std_logic_vector(0 to 31);
BRAM_Dout_B : in std_logic_vector(0 to 31)
);
end component;
component rs232_usb_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 3);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrDBus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_MSize : in std_logic_vector(0 to 1);
PLB_lockErr : in std_logic;
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 31);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MWrErr : out std_logic_vector(0 to 1);
Sl_MRdErr : out std_logic_vector(0 to 1);
Sl_wrBTerm : out std_logic;
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdBTerm : out std_logic;
Sl_MIRQ : out std_logic_vector(0 to 1);
RX : in std_logic;
TX : out std_logic;
Interrupt : out std_logic
);
end component;
component leds_8bit_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 3);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 31);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 31);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MWrErr : out std_logic_vector(0 to 1);
Sl_MRdErr : out std_logic_vector(0 to 1);
Sl_MIRQ : out std_logic_vector(0 to 1);
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(0 to 7);
GPIO_IO_O : out std_logic_vector(0 to 7);
GPIO_IO_T : out std_logic_vector(0 to 7);
GPIO2_IO_I : in std_logic_vector(0 to 31);
GPIO2_IO_O : out std_logic_vector(0 to 31);
GPIO2_IO_T : out std_logic_vector(0 to 31)
);
end component;
component push_buttons_3bit_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 3);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 31);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 31);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MWrErr : out std_logic_vector(0 to 1);
Sl_MRdErr : out std_logic_vector(0 to 1);
Sl_MIRQ : out std_logic_vector(0 to 1);
IP2INTC_Irpt : out std_logic;
GPIO_IO_I : in std_logic_vector(0 to 2);
GPIO_IO_O : out std_logic_vector(0 to 2);
GPIO_IO_T : out std_logic_vector(0 to 2);
GPIO2_IO_I : in std_logic_vector(0 to 31);
GPIO2_IO_O : out std_logic_vector(0 to 31);
GPIO2_IO_T : out std_logic_vector(0 to 31)
);
end component;
component xps_timer_0_wrapper is
port (
CaptureTrig0 : in std_logic;
CaptureTrig1 : in std_logic;
GenerateOut0 : out std_logic;
GenerateOut1 : out std_logic;
PWM0 : out std_logic;
Interrupt : out std_logic;
Freeze : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 3);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrDBus : in std_logic_vector(0 to 31);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 31);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MWrErr : out std_logic_vector(0 to 1);
Sl_MRdErr : out std_logic_vector(0 to 1);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_MSize : in std_logic_vector(0 to 1);
PLB_lockErr : in std_logic;
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_wrBTerm : out std_logic;
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdBTerm : out std_logic;
Sl_MIRQ : out std_logic_vector(0 to 1)
);
end component;
component clock_generator_0_wrapper is
port (
CLKIN : in std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUT6 : out std_logic;
CLKOUT7 : out std_logic;
CLKOUT8 : out std_logic;
CLKOUT9 : out std_logic;
CLKOUT10 : out std_logic;
CLKOUT11 : out std_logic;
CLKOUT12 : out std_logic;
CLKOUT13 : out std_logic;
CLKOUT14 : out std_logic;
CLKOUT15 : out std_logic;
CLKFBIN : in std_logic;
CLKFBOUT : out std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSDONE : out std_logic;
RST : in std_logic;
LOCKED : out std_logic
);
end component;
component mdm_0_wrapper is
port (
Interrupt : out std_logic;
Debug_SYS_Rst : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 3);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 31);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 31);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MWrErr : out std_logic_vector(0 to 1);
Sl_MRdErr : out std_logic_vector(0 to 1);
Sl_MIRQ : out std_logic_vector(0 to 1);
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
bscan_tdi : out std_logic;
bscan_reset : out std_logic;
bscan_shift : out std_logic;
bscan_update : out std_logic;
bscan_capture : out std_logic;
bscan_sel1 : out std_logic;
bscan_drck1 : out std_logic;
bscan_tdo1 : in std_logic;
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end component;
component proc_sys_reset_0_wrapper is
port (
Slowest_sync_clk : in std_logic;
Ext_Reset_In : in std_logic;
Aux_Reset_In : in std_logic;
MB_Debug_Sys_Rst : in std_logic;
Core_Reset_Req_0 : in std_logic;
Chip_Reset_Req_0 : in std_logic;
System_Reset_Req_0 : in std_logic;
Core_Reset_Req_1 : in std_logic;
Chip_Reset_Req_1 : in std_logic;
System_Reset_Req_1 : in std_logic;
Dcm_locked : in std_logic;
RstcPPCresetcore_0 : out std_logic;
RstcPPCresetchip_0 : out std_logic;
RstcPPCresetsys_0 : out std_logic;
RstcPPCresetcore_1 : out std_logic;
RstcPPCresetchip_1 : out std_logic;
RstcPPCresetsys_1 : out std_logic;
MB_Reset : out std_logic;
Bus_Struct_Reset : out std_logic_vector(0 to 0);
Peripheral_Reset : out std_logic_vector(0 to 0);
Interconnect_aresetn : out std_logic_vector(0 to 0);
Peripheral_aresetn : out std_logic_vector(0 to 0)
);
end component;
-- Internal signals
signal CLK_S : std_logic;
signal Dcm_all_locked : std_logic;
signal Debug_SYS_Rst : std_logic;
signal Ext_BRK : std_logic;
signal Ext_NM_BRK : std_logic;
signal clk_50_0000MHz : std_logic;
signal dlmb_LMB_ABus : std_logic_vector(0 to 31);
signal dlmb_LMB_AddrStrobe : std_logic;
signal dlmb_LMB_BE : std_logic_vector(0 to 3);
signal dlmb_LMB_CE : std_logic;
signal dlmb_LMB_ReadDBus : std_logic_vector(0 to 31);
signal dlmb_LMB_ReadStrobe : std_logic;
signal dlmb_LMB_Ready : std_logic;
signal dlmb_LMB_Rst : std_logic;
signal dlmb_LMB_UE : std_logic;
signal dlmb_LMB_Wait : std_logic;
signal dlmb_LMB_WriteDBus : std_logic_vector(0 to 31);
signal dlmb_LMB_WriteStrobe : std_logic;
signal dlmb_M_ABus : std_logic_vector(0 to 31);
signal dlmb_M_AddrStrobe : std_logic;
signal dlmb_M_BE : std_logic_vector(0 to 3);
signal dlmb_M_DBus : std_logic_vector(0 to 31);
signal dlmb_M_ReadStrobe : std_logic;
signal dlmb_M_WriteStrobe : std_logic;
signal dlmb_Sl_CE : std_logic_vector(0 to 0);
signal dlmb_Sl_DBus : std_logic_vector(0 to 31);
signal dlmb_Sl_Ready : std_logic_vector(0 to 0);
signal dlmb_Sl_UE : std_logic_vector(0 to 0);
signal dlmb_Sl_Wait : std_logic_vector(0 to 0);
signal dlmb_port_BRAM_Addr : std_logic_vector(0 to 31);
signal dlmb_port_BRAM_Clk : std_logic;
signal dlmb_port_BRAM_Din : std_logic_vector(0 to 31);
signal dlmb_port_BRAM_Dout : std_logic_vector(0 to 31);
signal dlmb_port_BRAM_EN : std_logic;
signal dlmb_port_BRAM_Rst : std_logic;
signal dlmb_port_BRAM_WEN : std_logic_vector(0 to 3);
signal ilmb_LMB_ABus : std_logic_vector(0 to 31);
signal ilmb_LMB_AddrStrobe : std_logic;
signal ilmb_LMB_BE : std_logic_vector(0 to 3);
signal ilmb_LMB_CE : std_logic;
signal ilmb_LMB_ReadDBus : std_logic_vector(0 to 31);
signal ilmb_LMB_ReadStrobe : std_logic;
signal ilmb_LMB_Ready : std_logic;
signal ilmb_LMB_Rst : std_logic;
signal ilmb_LMB_UE : std_logic;
signal ilmb_LMB_Wait : std_logic;
signal ilmb_LMB_WriteDBus : std_logic_vector(0 to 31);
signal ilmb_LMB_WriteStrobe : std_logic;
signal ilmb_M_ABus : std_logic_vector(0 to 31);
signal ilmb_M_AddrStrobe : std_logic;
signal ilmb_M_ReadStrobe : std_logic;
signal ilmb_Sl_CE : std_logic_vector(0 to 0);
signal ilmb_Sl_DBus : std_logic_vector(0 to 31);
signal ilmb_Sl_Ready : std_logic_vector(0 to 0);
signal ilmb_Sl_UE : std_logic_vector(0 to 0);
signal ilmb_Sl_Wait : std_logic_vector(0 to 0);
signal ilmb_port_BRAM_Addr : std_logic_vector(0 to 31);
signal ilmb_port_BRAM_Clk : std_logic;
signal ilmb_port_BRAM_Din : std_logic_vector(0 to 31);
signal ilmb_port_BRAM_Dout : std_logic_vector(0 to 31);
signal ilmb_port_BRAM_EN : std_logic;
signal ilmb_port_BRAM_Rst : std_logic;
signal ilmb_port_BRAM_WEN : std_logic_vector(0 to 3);
signal mb_plb_M_ABort : std_logic_vector(0 to 1);
signal mb_plb_M_ABus : std_logic_vector(0 to 63);
signal mb_plb_M_BE : std_logic_vector(0 to 7);
signal mb_plb_M_MSize : std_logic_vector(0 to 3);
signal mb_plb_M_RNW : std_logic_vector(0 to 1);
signal mb_plb_M_TAttribute : std_logic_vector(0 to 31);
signal mb_plb_M_UABus : std_logic_vector(0 to 63);
signal mb_plb_M_busLock : std_logic_vector(0 to 1);
signal mb_plb_M_lockErr : std_logic_vector(0 to 1);
signal mb_plb_M_priority : std_logic_vector(0 to 3);
signal mb_plb_M_rdBurst : std_logic_vector(0 to 1);
signal mb_plb_M_request : std_logic_vector(0 to 1);
signal mb_plb_M_size : std_logic_vector(0 to 7);
signal mb_plb_M_type : std_logic_vector(0 to 5);
signal mb_plb_M_wrBurst : std_logic_vector(0 to 1);
signal mb_plb_M_wrDBus : std_logic_vector(0 to 63);
signal mb_plb_PLB_ABus : std_logic_vector(0 to 31);
signal mb_plb_PLB_BE : std_logic_vector(0 to 3);
signal mb_plb_PLB_MAddrAck : std_logic_vector(0 to 1);
signal mb_plb_PLB_MBusy : std_logic_vector(0 to 1);
signal mb_plb_PLB_MIRQ : std_logic_vector(0 to 1);
signal mb_plb_PLB_MRdBTerm : std_logic_vector(0 to 1);
signal mb_plb_PLB_MRdDAck : std_logic_vector(0 to 1);
signal mb_plb_PLB_MRdDBus : std_logic_vector(0 to 63);
signal mb_plb_PLB_MRdErr : std_logic_vector(0 to 1);
signal mb_plb_PLB_MRdWdAddr : std_logic_vector(0 to 7);
signal mb_plb_PLB_MRearbitrate : std_logic_vector(0 to 1);
signal mb_plb_PLB_MSSize : std_logic_vector(0 to 3);
signal mb_plb_PLB_MSize : std_logic_vector(0 to 1);
signal mb_plb_PLB_MTimeout : std_logic_vector(0 to 1);
signal mb_plb_PLB_MWrBTerm : std_logic_vector(0 to 1);
signal mb_plb_PLB_MWrDAck : std_logic_vector(0 to 1);
signal mb_plb_PLB_MWrErr : std_logic_vector(0 to 1);
signal mb_plb_PLB_PAValid : std_logic;
signal mb_plb_PLB_RNW : std_logic;
signal mb_plb_PLB_SAValid : std_logic;
signal mb_plb_PLB_TAttribute : std_logic_vector(0 to 15);
signal mb_plb_PLB_UABus : std_logic_vector(0 to 31);
signal mb_plb_PLB_abort : std_logic;
signal mb_plb_PLB_busLock : std_logic;
signal mb_plb_PLB_lockErr : std_logic;
signal mb_plb_PLB_masterID : std_logic_vector(0 to 0);
signal mb_plb_PLB_rdBurst : std_logic;
signal mb_plb_PLB_rdPendPri : std_logic_vector(0 to 1);
signal mb_plb_PLB_rdPendReq : std_logic;
signal mb_plb_PLB_rdPrim : std_logic_vector(0 to 4);
signal mb_plb_PLB_reqPri : std_logic_vector(0 to 1);
signal mb_plb_PLB_size : std_logic_vector(0 to 3);
signal mb_plb_PLB_type : std_logic_vector(0 to 2);
signal mb_plb_PLB_wrBurst : std_logic;
signal mb_plb_PLB_wrDBus : std_logic_vector(0 to 31);
signal mb_plb_PLB_wrPendPri : std_logic_vector(0 to 1);
signal mb_plb_PLB_wrPendReq : std_logic;
signal mb_plb_PLB_wrPrim : std_logic_vector(0 to 4);
signal mb_plb_SPLB_Rst : std_logic_vector(0 to 4);
signal mb_plb_Sl_MBusy : std_logic_vector(0 to 9);
signal mb_plb_Sl_MIRQ : std_logic_vector(0 to 9);
signal mb_plb_Sl_MRdErr : std_logic_vector(0 to 9);
signal mb_plb_Sl_MWrErr : std_logic_vector(0 to 9);
signal mb_plb_Sl_SSize : std_logic_vector(0 to 9);
signal mb_plb_Sl_addrAck : std_logic_vector(0 to 4);
signal mb_plb_Sl_rdBTerm : std_logic_vector(0 to 4);
signal mb_plb_Sl_rdComp : std_logic_vector(0 to 4);
signal mb_plb_Sl_rdDAck : std_logic_vector(0 to 4);
signal mb_plb_Sl_rdDBus : std_logic_vector(0 to 159);
signal mb_plb_Sl_rdWdAddr : std_logic_vector(0 to 19);
signal mb_plb_Sl_rearbitrate : std_logic_vector(0 to 4);
signal mb_plb_Sl_wait : std_logic_vector(0 to 4);
signal mb_plb_Sl_wrBTerm : std_logic_vector(0 to 4);
signal mb_plb_Sl_wrComp : std_logic_vector(0 to 4);
signal mb_plb_Sl_wrDAck : std_logic_vector(0 to 4);
signal mb_reset : std_logic;
signal microblaze_0_mdm_bus_Dbg_Capture : std_logic;
signal microblaze_0_mdm_bus_Dbg_Clk : std_logic;
signal microblaze_0_mdm_bus_Dbg_Reg_En : std_logic_vector(0 to 7);
signal microblaze_0_mdm_bus_Dbg_Shift : std_logic;
signal microblaze_0_mdm_bus_Dbg_TDI : std_logic;
signal microblaze_0_mdm_bus_Dbg_TDO : std_logic;
signal microblaze_0_mdm_bus_Dbg_Update : std_logic;
signal microblaze_0_mdm_bus_Debug_Rst : std_logic;
signal net_gnd0 : std_logic;
signal net_gnd1 : std_logic_vector(0 downto 0);
signal net_gnd2 : std_logic_vector(1 downto 0);
signal net_gnd3 : std_logic_vector(0 to 2);
signal net_gnd4 : std_logic_vector(0 to 3);
signal net_gnd8 : std_logic_vector(0 to 7);
signal net_gnd10 : std_logic_vector(0 to 9);
signal net_gnd16 : std_logic_vector(0 to 15);
signal net_gnd32 : std_logic_vector(0 to 31);
signal net_gnd4096 : std_logic_vector(0 to 4095);
signal net_vcc0 : std_logic;
signal sys_bus_reset : std_logic_vector(0 to 0);
signal sys_rst_s : std_logic;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of microblaze_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of mb_plb_wrapper : component is "user_black_box";
attribute BOX_TYPE of ilmb_wrapper : component is "user_black_box";
attribute BOX_TYPE of dlmb_wrapper : component is "user_black_box";
attribute BOX_TYPE of dlmb_cntlr_wrapper : component is "user_black_box";
attribute BOX_TYPE of ilmb_cntlr_wrapper : component is "user_black_box";
attribute BOX_TYPE of lmb_bram_wrapper : component is "user_black_box";
attribute BOX_TYPE of rs232_usb_wrapper : component is "user_black_box";
attribute BOX_TYPE of leds_8bit_wrapper : component is "user_black_box";
attribute BOX_TYPE of push_buttons_3bit_wrapper : component is "user_black_box";
attribute BOX_TYPE of xps_timer_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of clock_generator_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of mdm_0_wrapper : component is "user_black_box";
attribute BOX_TYPE of proc_sys_reset_0_wrapper : component is "user_black_box";
begin
-- Internal assignments
CLK_S <= fpga_0_clk_1_sys_clk_pin;
sys_rst_s <= fpga_0_rst_1_sys_rst_pin;
net_gnd0 <= '0';
net_gnd1(0 downto 0) <= B"0";
net_gnd10(0 to 9) <= B"0000000000";
net_gnd16(0 to 15) <= B"0000000000000000";
net_gnd2(1 downto 0) <= B"00";
net_gnd3(0 to 2) <= B"000";
net_gnd32(0 to 31) <= B"00000000000000000000000000000000";
net_gnd4(0 to 3) <= B"0000";
net_gnd4096(0 to 4095) <= X"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
net_gnd8(0 to 7) <= B"00000000";
net_vcc0 <= '1';
microblaze_0 : microblaze_0_wrapper
port map (
CLK => clk_50_0000MHz,
RESET => dlmb_LMB_Rst,
MB_RESET => mb_reset,
INTERRUPT => net_gnd0,
EXT_BRK => Ext_BRK,
EXT_NM_BRK => Ext_NM_BRK,
DBG_STOP => net_gnd0,
MB_Halted => open,
MB_Error => open,
LOCKSTEP_MASTER_OUT => open,
LOCKSTEP_SLAVE_IN => net_gnd4096,
LOCKSTEP_OUT => open,
INSTR => ilmb_LMB_ReadDBus,
IREADY => ilmb_LMB_Ready,
IWAIT => ilmb_LMB_Wait,
ICE => ilmb_LMB_CE,
IUE => ilmb_LMB_UE,
INSTR_ADDR => ilmb_M_ABus,
IFETCH => ilmb_M_ReadStrobe,
I_AS => ilmb_M_AddrStrobe,
IPLB_M_ABort => mb_plb_M_ABort(1),
IPLB_M_ABus => mb_plb_M_ABus(32 to 63),
IPLB_M_UABus => mb_plb_M_UABus(32 to 63),
IPLB_M_BE => mb_plb_M_BE(4 to 7),
IPLB_M_busLock => mb_plb_M_busLock(1),
IPLB_M_lockErr => mb_plb_M_lockErr(1),
IPLB_M_MSize => mb_plb_M_MSize(2 to 3),
IPLB_M_priority => mb_plb_M_priority(2 to 3),
IPLB_M_rdBurst => mb_plb_M_rdBurst(1),
IPLB_M_request => mb_plb_M_request(1),
IPLB_M_RNW => mb_plb_M_RNW(1),
IPLB_M_size => mb_plb_M_size(4 to 7),
IPLB_M_TAttribute => mb_plb_M_TAttribute(16 to 31),
IPLB_M_type => mb_plb_M_type(3 to 5),
IPLB_M_wrBurst => mb_plb_M_wrBurst(1),
IPLB_M_wrDBus => mb_plb_M_wrDBus(32 to 63),
IPLB_MBusy => mb_plb_PLB_MBusy(1),
IPLB_MRdErr => mb_plb_PLB_MRdErr(1),
IPLB_MWrErr => mb_plb_PLB_MWrErr(1),
IPLB_MIRQ => mb_plb_PLB_MIRQ(1),
IPLB_MWrBTerm => mb_plb_PLB_MWrBTerm(1),
IPLB_MWrDAck => mb_plb_PLB_MWrDAck(1),
IPLB_MAddrAck => mb_plb_PLB_MAddrAck(1),
IPLB_MRdBTerm => mb_plb_PLB_MRdBTerm(1),
IPLB_MRdDAck => mb_plb_PLB_MRdDAck(1),
IPLB_MRdDBus => mb_plb_PLB_MRdDBus(32 to 63),
IPLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(4 to 7),
IPLB_MRearbitrate => mb_plb_PLB_MRearbitrate(1),
IPLB_MSSize => mb_plb_PLB_MSSize(2 to 3),
IPLB_MTimeout => mb_plb_PLB_MTimeout(1),
DATA_READ => dlmb_LMB_ReadDBus,
DREADY => dlmb_LMB_Ready,
DWAIT => dlmb_LMB_Wait,
DCE => dlmb_LMB_CE,
DUE => dlmb_LMB_UE,
DATA_WRITE => dlmb_M_DBus,
DATA_ADDR => dlmb_M_ABus,
D_AS => dlmb_M_AddrStrobe,
READ_STROBE => dlmb_M_ReadStrobe,
WRITE_STROBE => dlmb_M_WriteStrobe,
BYTE_ENABLE => dlmb_M_BE,
DPLB_M_ABort => mb_plb_M_ABort(0),
DPLB_M_ABus => mb_plb_M_ABus(0 to 31),
DPLB_M_UABus => mb_plb_M_UABus(0 to 31),
DPLB_M_BE => mb_plb_M_BE(0 to 3),
DPLB_M_busLock => mb_plb_M_busLock(0),
DPLB_M_lockErr => mb_plb_M_lockErr(0),
DPLB_M_MSize => mb_plb_M_MSize(0 to 1),
DPLB_M_priority => mb_plb_M_priority(0 to 1),
DPLB_M_rdBurst => mb_plb_M_rdBurst(0),
DPLB_M_request => mb_plb_M_request(0),
DPLB_M_RNW => mb_plb_M_RNW(0),
DPLB_M_size => mb_plb_M_size(0 to 3),
DPLB_M_TAttribute => mb_plb_M_TAttribute(0 to 15),
DPLB_M_type => mb_plb_M_type(0 to 2),
DPLB_M_wrBurst => mb_plb_M_wrBurst(0),
DPLB_M_wrDBus => mb_plb_M_wrDBus(0 to 31),
DPLB_MBusy => mb_plb_PLB_MBusy(0),
DPLB_MRdErr => mb_plb_PLB_MRdErr(0),
DPLB_MWrErr => mb_plb_PLB_MWrErr(0),
DPLB_MIRQ => mb_plb_PLB_MIRQ(0),
DPLB_MWrBTerm => mb_plb_PLB_MWrBTerm(0),
DPLB_MWrDAck => mb_plb_PLB_MWrDAck(0),
DPLB_MAddrAck => mb_plb_PLB_MAddrAck(0),
DPLB_MRdBTerm => mb_plb_PLB_MRdBTerm(0),
DPLB_MRdDAck => mb_plb_PLB_MRdDAck(0),
DPLB_MRdDBus => mb_plb_PLB_MRdDBus(0 to 31),
DPLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr(0 to 3),
DPLB_MRearbitrate => mb_plb_PLB_MRearbitrate(0),
DPLB_MSSize => mb_plb_PLB_MSSize(0 to 1),
DPLB_MTimeout => mb_plb_PLB_MTimeout(0),
M_AXI_IP_AWID => open,
M_AXI_IP_AWADDR => open,
M_AXI_IP_AWLEN => open,
M_AXI_IP_AWSIZE => open,
M_AXI_IP_AWBURST => open,
M_AXI_IP_AWLOCK => open,
M_AXI_IP_AWCACHE => open,
M_AXI_IP_AWPROT => open,
M_AXI_IP_AWQOS => open,
M_AXI_IP_AWVALID => open,
M_AXI_IP_AWREADY => net_gnd0,
M_AXI_IP_WDATA => open,
M_AXI_IP_WSTRB => open,
M_AXI_IP_WLAST => open,
M_AXI_IP_WVALID => open,
M_AXI_IP_WREADY => net_gnd0,
M_AXI_IP_BID => net_gnd1(0 downto 0),
M_AXI_IP_BRESP => net_gnd2,
M_AXI_IP_BVALID => net_gnd0,
M_AXI_IP_BREADY => open,
M_AXI_IP_ARID => open,
M_AXI_IP_ARADDR => open,
M_AXI_IP_ARLEN => open,
M_AXI_IP_ARSIZE => open,
M_AXI_IP_ARBURST => open,
M_AXI_IP_ARLOCK => open,
M_AXI_IP_ARCACHE => open,
M_AXI_IP_ARPROT => open,
M_AXI_IP_ARQOS => open,
M_AXI_IP_ARVALID => open,
M_AXI_IP_ARREADY => net_gnd0,
M_AXI_IP_RID => net_gnd1(0 downto 0),
M_AXI_IP_RDATA => net_gnd32(0 to 31),
M_AXI_IP_RRESP => net_gnd2,
M_AXI_IP_RLAST => net_gnd0,
M_AXI_IP_RVALID => net_gnd0,
M_AXI_IP_RREADY => open,
M_AXI_DP_AWID => open,
M_AXI_DP_AWADDR => open,
M_AXI_DP_AWLEN => open,
M_AXI_DP_AWSIZE => open,
M_AXI_DP_AWBURST => open,
M_AXI_DP_AWLOCK => open,
M_AXI_DP_AWCACHE => open,
M_AXI_DP_AWPROT => open,
M_AXI_DP_AWQOS => open,
M_AXI_DP_AWVALID => open,
M_AXI_DP_AWREADY => net_gnd0,
M_AXI_DP_WDATA => open,
M_AXI_DP_WSTRB => open,
M_AXI_DP_WLAST => open,
M_AXI_DP_WVALID => open,
M_AXI_DP_WREADY => net_gnd0,
M_AXI_DP_BID => net_gnd1(0 downto 0),
M_AXI_DP_BRESP => net_gnd2,
M_AXI_DP_BVALID => net_gnd0,
M_AXI_DP_BREADY => open,
M_AXI_DP_ARID => open,
M_AXI_DP_ARADDR => open,
M_AXI_DP_ARLEN => open,
M_AXI_DP_ARSIZE => open,
M_AXI_DP_ARBURST => open,
M_AXI_DP_ARLOCK => open,
M_AXI_DP_ARCACHE => open,
M_AXI_DP_ARPROT => open,
M_AXI_DP_ARQOS => open,
M_AXI_DP_ARVALID => open,
M_AXI_DP_ARREADY => net_gnd0,
M_AXI_DP_RID => net_gnd1(0 downto 0),
M_AXI_DP_RDATA => net_gnd32(0 to 31),
M_AXI_DP_RRESP => net_gnd2,
M_AXI_DP_RLAST => net_gnd0,
M_AXI_DP_RVALID => net_gnd0,
M_AXI_DP_RREADY => open,
M_AXI_IC_AWID => open,
M_AXI_IC_AWADDR => open,
M_AXI_IC_AWLEN => open,
M_AXI_IC_AWSIZE => open,
M_AXI_IC_AWBURST => open,
M_AXI_IC_AWLOCK => open,
M_AXI_IC_AWCACHE => open,
M_AXI_IC_AWPROT => open,
M_AXI_IC_AWQOS => open,
M_AXI_IC_AWVALID => open,
M_AXI_IC_AWREADY => net_gnd0,
M_AXI_IC_AWUSER => open,
M_AXI_IC_WDATA => open,
M_AXI_IC_WSTRB => open,
M_AXI_IC_WLAST => open,
M_AXI_IC_WVALID => open,
M_AXI_IC_WREADY => net_gnd0,
M_AXI_IC_WUSER => open,
M_AXI_IC_BID => net_gnd1(0 downto 0),
M_AXI_IC_BRESP => net_gnd2,
M_AXI_IC_BVALID => net_gnd0,
M_AXI_IC_BREADY => open,
M_AXI_IC_BUSER => net_gnd1(0 downto 0),
M_AXI_IC_ARID => open,
M_AXI_IC_ARADDR => open,
M_AXI_IC_ARLEN => open,
M_AXI_IC_ARSIZE => open,
M_AXI_IC_ARBURST => open,
M_AXI_IC_ARLOCK => open,
M_AXI_IC_ARCACHE => open,
M_AXI_IC_ARPROT => open,
M_AXI_IC_ARQOS => open,
M_AXI_IC_ARVALID => open,
M_AXI_IC_ARREADY => net_gnd0,
M_AXI_IC_ARUSER => open,
M_AXI_IC_RID => net_gnd1(0 downto 0),
M_AXI_IC_RDATA => net_gnd32(0 to 31),
M_AXI_IC_RRESP => net_gnd2,
M_AXI_IC_RLAST => net_gnd0,
M_AXI_IC_RVALID => net_gnd0,
M_AXI_IC_RREADY => open,
M_AXI_IC_RUSER => net_gnd1(0 downto 0),
M_AXI_DC_AWID => open,
M_AXI_DC_AWADDR => open,
M_AXI_DC_AWLEN => open,
M_AXI_DC_AWSIZE => open,
M_AXI_DC_AWBURST => open,
M_AXI_DC_AWLOCK => open,
M_AXI_DC_AWCACHE => open,
M_AXI_DC_AWPROT => open,
M_AXI_DC_AWQOS => open,
M_AXI_DC_AWVALID => open,
M_AXI_DC_AWREADY => net_gnd0,
M_AXI_DC_AWUSER => open,
M_AXI_DC_WDATA => open,
M_AXI_DC_WSTRB => open,
M_AXI_DC_WLAST => open,
M_AXI_DC_WVALID => open,
M_AXI_DC_WREADY => net_gnd0,
M_AXI_DC_WUSER => open,
M_AXI_DC_BID => net_gnd1(0 downto 0),
M_AXI_DC_BRESP => net_gnd2,
M_AXI_DC_BVALID => net_gnd0,
M_AXI_DC_BREADY => open,
M_AXI_DC_BUSER => net_gnd1(0 downto 0),
M_AXI_DC_ARID => open,
M_AXI_DC_ARADDR => open,
M_AXI_DC_ARLEN => open,
M_AXI_DC_ARSIZE => open,
M_AXI_DC_ARBURST => open,
M_AXI_DC_ARLOCK => open,
M_AXI_DC_ARCACHE => open,
M_AXI_DC_ARPROT => open,
M_AXI_DC_ARQOS => open,
M_AXI_DC_ARVALID => open,
M_AXI_DC_ARREADY => net_gnd0,
M_AXI_DC_ARUSER => open,
M_AXI_DC_RID => net_gnd1(0 downto 0),
M_AXI_DC_RDATA => net_gnd32(0 to 31),
M_AXI_DC_RRESP => net_gnd2,
M_AXI_DC_RLAST => net_gnd0,
M_AXI_DC_RVALID => net_gnd0,
M_AXI_DC_RREADY => open,
M_AXI_DC_RUSER => net_gnd1(0 downto 0),
DBG_CLK => microblaze_0_mdm_bus_Dbg_Clk,
DBG_TDI => microblaze_0_mdm_bus_Dbg_TDI,
DBG_TDO => microblaze_0_mdm_bus_Dbg_TDO,
DBG_REG_EN => microblaze_0_mdm_bus_Dbg_Reg_En,
DBG_SHIFT => microblaze_0_mdm_bus_Dbg_Shift,
DBG_CAPTURE => microblaze_0_mdm_bus_Dbg_Capture,
DBG_UPDATE => microblaze_0_mdm_bus_Dbg_Update,
DEBUG_RST => microblaze_0_mdm_bus_Debug_Rst,
Trace_Instruction => open,
Trace_Valid_Instr => open,
Trace_PC => open,
Trace_Reg_Write => open,
Trace_Reg_Addr => open,
Trace_MSR_Reg => open,
Trace_PID_Reg => open,
Trace_New_Reg_Value => open,
Trace_Exception_Taken => open,
Trace_Exception_Kind => open,
Trace_Jump_Taken => open,
Trace_Delay_Slot => open,
Trace_Data_Address => open,
Trace_Data_Access => open,
Trace_Data_Read => open,
Trace_Data_Write => open,
Trace_Data_Write_Value => open,
Trace_Data_Byte_Enable => open,
Trace_DCache_Req => open,
Trace_DCache_Hit => open,
Trace_DCache_Rdy => open,
Trace_DCache_Read => open,
Trace_ICache_Req => open,
Trace_ICache_Hit => open,
Trace_ICache_Rdy => open,
Trace_OF_PipeRun => open,
Trace_EX_PipeRun => open,
Trace_MEM_PipeRun => open,
Trace_MB_Halted => open,
Trace_Jump_Hit => open,
FSL0_S_CLK => open,
FSL0_S_READ => open,
FSL0_S_DATA => net_gnd32,
FSL0_S_CONTROL => net_gnd0,
FSL0_S_EXISTS => net_gnd0,
FSL0_M_CLK => open,
FSL0_M_WRITE => open,
FSL0_M_DATA => open,
FSL0_M_CONTROL => open,
FSL0_M_FULL => net_gnd0,
FSL1_S_CLK => open,
FSL1_S_READ => open,
FSL1_S_DATA => net_gnd32,
FSL1_S_CONTROL => net_gnd0,
FSL1_S_EXISTS => net_gnd0,
FSL1_M_CLK => open,
FSL1_M_WRITE => open,
FSL1_M_DATA => open,
FSL1_M_CONTROL => open,
FSL1_M_FULL => net_gnd0,
FSL2_S_CLK => open,
FSL2_S_READ => open,
FSL2_S_DATA => net_gnd32,
FSL2_S_CONTROL => net_gnd0,
FSL2_S_EXISTS => net_gnd0,
FSL2_M_CLK => open,
FSL2_M_WRITE => open,
FSL2_M_DATA => open,
FSL2_M_CONTROL => open,
FSL2_M_FULL => net_gnd0,
FSL3_S_CLK => open,
FSL3_S_READ => open,
FSL3_S_DATA => net_gnd32,
FSL3_S_CONTROL => net_gnd0,
FSL3_S_EXISTS => net_gnd0,
FSL3_M_CLK => open,
FSL3_M_WRITE => open,
FSL3_M_DATA => open,
FSL3_M_CONTROL => open,
FSL3_M_FULL => net_gnd0,
FSL4_S_CLK => open,
FSL4_S_READ => open,
FSL4_S_DATA => net_gnd32,
FSL4_S_CONTROL => net_gnd0,
FSL4_S_EXISTS => net_gnd0,
FSL4_M_CLK => open,
FSL4_M_WRITE => open,
FSL4_M_DATA => open,
FSL4_M_CONTROL => open,
FSL4_M_FULL => net_gnd0,
FSL5_S_CLK => open,
FSL5_S_READ => open,
FSL5_S_DATA => net_gnd32,
FSL5_S_CONTROL => net_gnd0,
FSL5_S_EXISTS => net_gnd0,
FSL5_M_CLK => open,
FSL5_M_WRITE => open,
FSL5_M_DATA => open,
FSL5_M_CONTROL => open,
FSL5_M_FULL => net_gnd0,
FSL6_S_CLK => open,
FSL6_S_READ => open,
FSL6_S_DATA => net_gnd32,
FSL6_S_CONTROL => net_gnd0,
FSL6_S_EXISTS => net_gnd0,
FSL6_M_CLK => open,
FSL6_M_WRITE => open,
FSL6_M_DATA => open,
FSL6_M_CONTROL => open,
FSL6_M_FULL => net_gnd0,
FSL7_S_CLK => open,
FSL7_S_READ => open,
FSL7_S_DATA => net_gnd32,
FSL7_S_CONTROL => net_gnd0,
FSL7_S_EXISTS => net_gnd0,
FSL7_M_CLK => open,
FSL7_M_WRITE => open,
FSL7_M_DATA => open,
FSL7_M_CONTROL => open,
FSL7_M_FULL => net_gnd0,
FSL8_S_CLK => open,
FSL8_S_READ => open,
FSL8_S_DATA => net_gnd32,
FSL8_S_CONTROL => net_gnd0,
FSL8_S_EXISTS => net_gnd0,
FSL8_M_CLK => open,
FSL8_M_WRITE => open,
FSL8_M_DATA => open,
FSL8_M_CONTROL => open,
FSL8_M_FULL => net_gnd0,
FSL9_S_CLK => open,
FSL9_S_READ => open,
FSL9_S_DATA => net_gnd32,
FSL9_S_CONTROL => net_gnd0,
FSL9_S_EXISTS => net_gnd0,
FSL9_M_CLK => open,
FSL9_M_WRITE => open,
FSL9_M_DATA => open,
FSL9_M_CONTROL => open,
FSL9_M_FULL => net_gnd0,
FSL10_S_CLK => open,
FSL10_S_READ => open,
FSL10_S_DATA => net_gnd32,
FSL10_S_CONTROL => net_gnd0,
FSL10_S_EXISTS => net_gnd0,
FSL10_M_CLK => open,
FSL10_M_WRITE => open,
FSL10_M_DATA => open,
FSL10_M_CONTROL => open,
FSL10_M_FULL => net_gnd0,
FSL11_S_CLK => open,
FSL11_S_READ => open,
FSL11_S_DATA => net_gnd32,
FSL11_S_CONTROL => net_gnd0,
FSL11_S_EXISTS => net_gnd0,
FSL11_M_CLK => open,
FSL11_M_WRITE => open,
FSL11_M_DATA => open,
FSL11_M_CONTROL => open,
FSL11_M_FULL => net_gnd0,
FSL12_S_CLK => open,
FSL12_S_READ => open,
FSL12_S_DATA => net_gnd32,
FSL12_S_CONTROL => net_gnd0,
FSL12_S_EXISTS => net_gnd0,
FSL12_M_CLK => open,
FSL12_M_WRITE => open,
FSL12_M_DATA => open,
FSL12_M_CONTROL => open,
FSL12_M_FULL => net_gnd0,
FSL13_S_CLK => open,
FSL13_S_READ => open,
FSL13_S_DATA => net_gnd32,
FSL13_S_CONTROL => net_gnd0,
FSL13_S_EXISTS => net_gnd0,
FSL13_M_CLK => open,
FSL13_M_WRITE => open,
FSL13_M_DATA => open,
FSL13_M_CONTROL => open,
FSL13_M_FULL => net_gnd0,
FSL14_S_CLK => open,
FSL14_S_READ => open,
FSL14_S_DATA => net_gnd32,
FSL14_S_CONTROL => net_gnd0,
FSL14_S_EXISTS => net_gnd0,
FSL14_M_CLK => open,
FSL14_M_WRITE => open,
FSL14_M_DATA => open,
FSL14_M_CONTROL => open,
FSL14_M_FULL => net_gnd0,
FSL15_S_CLK => open,
FSL15_S_READ => open,
FSL15_S_DATA => net_gnd32,
FSL15_S_CONTROL => net_gnd0,
FSL15_S_EXISTS => net_gnd0,
FSL15_M_CLK => open,
FSL15_M_WRITE => open,
FSL15_M_DATA => open,
FSL15_M_CONTROL => open,
FSL15_M_FULL => net_gnd0,
M0_AXIS_TLAST => open,
M0_AXIS_TDATA => open,
M0_AXIS_TVALID => open,
M0_AXIS_TREADY => net_gnd0,
S0_AXIS_TLAST => net_gnd0,
S0_AXIS_TDATA => net_gnd32(0 to 31),
S0_AXIS_TVALID => net_gnd0,
S0_AXIS_TREADY => open,
M1_AXIS_TLAST => open,
M1_AXIS_TDATA => open,
M1_AXIS_TVALID => open,
M1_AXIS_TREADY => net_gnd0,
S1_AXIS_TLAST => net_gnd0,
S1_AXIS_TDATA => net_gnd32(0 to 31),
S1_AXIS_TVALID => net_gnd0,
S1_AXIS_TREADY => open,
M2_AXIS_TLAST => open,
M2_AXIS_TDATA => open,
M2_AXIS_TVALID => open,
M2_AXIS_TREADY => net_gnd0,
S2_AXIS_TLAST => net_gnd0,
S2_AXIS_TDATA => net_gnd32(0 to 31),
S2_AXIS_TVALID => net_gnd0,
S2_AXIS_TREADY => open,
M3_AXIS_TLAST => open,
M3_AXIS_TDATA => open,
M3_AXIS_TVALID => open,
M3_AXIS_TREADY => net_gnd0,
S3_AXIS_TLAST => net_gnd0,
S3_AXIS_TDATA => net_gnd32(0 to 31),
S3_AXIS_TVALID => net_gnd0,
S3_AXIS_TREADY => open,
M4_AXIS_TLAST => open,
M4_AXIS_TDATA => open,
M4_AXIS_TVALID => open,
M4_AXIS_TREADY => net_gnd0,
S4_AXIS_TLAST => net_gnd0,
S4_AXIS_TDATA => net_gnd32(0 to 31),
S4_AXIS_TVALID => net_gnd0,
S4_AXIS_TREADY => open,
M5_AXIS_TLAST => open,
M5_AXIS_TDATA => open,
M5_AXIS_TVALID => open,
M5_AXIS_TREADY => net_gnd0,
S5_AXIS_TLAST => net_gnd0,
S5_AXIS_TDATA => net_gnd32(0 to 31),
S5_AXIS_TVALID => net_gnd0,
S5_AXIS_TREADY => open,
M6_AXIS_TLAST => open,
M6_AXIS_TDATA => open,
M6_AXIS_TVALID => open,
M6_AXIS_TREADY => net_gnd0,
S6_AXIS_TLAST => net_gnd0,
S6_AXIS_TDATA => net_gnd32(0 to 31),
S6_AXIS_TVALID => net_gnd0,
S6_AXIS_TREADY => open,
M7_AXIS_TLAST => open,
M7_AXIS_TDATA => open,
M7_AXIS_TVALID => open,
M7_AXIS_TREADY => net_gnd0,
S7_AXIS_TLAST => net_gnd0,
S7_AXIS_TDATA => net_gnd32(0 to 31),
S7_AXIS_TVALID => net_gnd0,
S7_AXIS_TREADY => open,
M8_AXIS_TLAST => open,
M8_AXIS_TDATA => open,
M8_AXIS_TVALID => open,
M8_AXIS_TREADY => net_gnd0,
S8_AXIS_TLAST => net_gnd0,
S8_AXIS_TDATA => net_gnd32(0 to 31),
S8_AXIS_TVALID => net_gnd0,
S8_AXIS_TREADY => open,
M9_AXIS_TLAST => open,
M9_AXIS_TDATA => open,
M9_AXIS_TVALID => open,
M9_AXIS_TREADY => net_gnd0,
S9_AXIS_TLAST => net_gnd0,
S9_AXIS_TDATA => net_gnd32(0 to 31),
S9_AXIS_TVALID => net_gnd0,
S9_AXIS_TREADY => open,
M10_AXIS_TLAST => open,
M10_AXIS_TDATA => open,
M10_AXIS_TVALID => open,
M10_AXIS_TREADY => net_gnd0,
S10_AXIS_TLAST => net_gnd0,
S10_AXIS_TDATA => net_gnd32(0 to 31),
S10_AXIS_TVALID => net_gnd0,
S10_AXIS_TREADY => open,
M11_AXIS_TLAST => open,
M11_AXIS_TDATA => open,
M11_AXIS_TVALID => open,
M11_AXIS_TREADY => net_gnd0,
S11_AXIS_TLAST => net_gnd0,
S11_AXIS_TDATA => net_gnd32(0 to 31),
S11_AXIS_TVALID => net_gnd0,
S11_AXIS_TREADY => open,
M12_AXIS_TLAST => open,
M12_AXIS_TDATA => open,
M12_AXIS_TVALID => open,
M12_AXIS_TREADY => net_gnd0,
S12_AXIS_TLAST => net_gnd0,
S12_AXIS_TDATA => net_gnd32(0 to 31),
S12_AXIS_TVALID => net_gnd0,
S12_AXIS_TREADY => open,
M13_AXIS_TLAST => open,
M13_AXIS_TDATA => open,
M13_AXIS_TVALID => open,
M13_AXIS_TREADY => net_gnd0,
S13_AXIS_TLAST => net_gnd0,
S13_AXIS_TDATA => net_gnd32(0 to 31),
S13_AXIS_TVALID => net_gnd0,
S13_AXIS_TREADY => open,
M14_AXIS_TLAST => open,
M14_AXIS_TDATA => open,
M14_AXIS_TVALID => open,
M14_AXIS_TREADY => net_gnd0,
S14_AXIS_TLAST => net_gnd0,
S14_AXIS_TDATA => net_gnd32(0 to 31),
S14_AXIS_TVALID => net_gnd0,
S14_AXIS_TREADY => open,
M15_AXIS_TLAST => open,
M15_AXIS_TDATA => open,
M15_AXIS_TVALID => open,
M15_AXIS_TREADY => net_gnd0,
S15_AXIS_TLAST => net_gnd0,
S15_AXIS_TDATA => net_gnd32(0 to 31),
S15_AXIS_TVALID => net_gnd0,
S15_AXIS_TREADY => open,
ICACHE_FSL_IN_CLK => open,
ICACHE_FSL_IN_READ => open,
ICACHE_FSL_IN_DATA => net_gnd32,
ICACHE_FSL_IN_CONTROL => net_gnd0,
ICACHE_FSL_IN_EXISTS => net_gnd0,
ICACHE_FSL_OUT_CLK => open,
ICACHE_FSL_OUT_WRITE => open,
ICACHE_FSL_OUT_DATA => open,
ICACHE_FSL_OUT_CONTROL => open,
ICACHE_FSL_OUT_FULL => net_gnd0,
DCACHE_FSL_IN_CLK => open,
DCACHE_FSL_IN_READ => open,
DCACHE_FSL_IN_DATA => net_gnd32,
DCACHE_FSL_IN_CONTROL => net_gnd0,
DCACHE_FSL_IN_EXISTS => net_gnd0,
DCACHE_FSL_OUT_CLK => open,
DCACHE_FSL_OUT_WRITE => open,
DCACHE_FSL_OUT_DATA => open,
DCACHE_FSL_OUT_CONTROL => open,
DCACHE_FSL_OUT_FULL => net_gnd0
);
mb_plb : mb_plb_wrapper
port map (
PLB_Clk => clk_50_0000MHz,
SYS_Rst => sys_bus_reset(0),
PLB_Rst => open,
SPLB_Rst => mb_plb_SPLB_Rst,
MPLB_Rst => open,
PLB_dcrAck => open,
PLB_dcrDBus => open,
DCR_ABus => net_gnd10,
DCR_DBus => net_gnd32,
DCR_Read => net_gnd0,
DCR_Write => net_gnd0,
M_ABus => mb_plb_M_ABus,
M_UABus => mb_plb_M_UABus,
M_BE => mb_plb_M_BE,
M_RNW => mb_plb_M_RNW,
M_abort => mb_plb_M_ABort,
M_busLock => mb_plb_M_busLock,
M_TAttribute => mb_plb_M_TAttribute,
M_lockErr => mb_plb_M_lockErr,
M_MSize => mb_plb_M_MSize,
M_priority => mb_plb_M_priority,
M_rdBurst => mb_plb_M_rdBurst,
M_request => mb_plb_M_request,
M_size => mb_plb_M_size,
M_type => mb_plb_M_type,
M_wrBurst => mb_plb_M_wrBurst,
M_wrDBus => mb_plb_M_wrDBus,
Sl_addrAck => mb_plb_Sl_addrAck,
Sl_MRdErr => mb_plb_Sl_MRdErr,
Sl_MWrErr => mb_plb_Sl_MWrErr,
Sl_MBusy => mb_plb_Sl_MBusy,
Sl_rdBTerm => mb_plb_Sl_rdBTerm,
Sl_rdComp => mb_plb_Sl_rdComp,
Sl_rdDAck => mb_plb_Sl_rdDAck,
Sl_rdDBus => mb_plb_Sl_rdDBus,
Sl_rdWdAddr => mb_plb_Sl_rdWdAddr,
Sl_rearbitrate => mb_plb_Sl_rearbitrate,
Sl_SSize => mb_plb_Sl_SSize,
Sl_wait => mb_plb_Sl_wait,
Sl_wrBTerm => mb_plb_Sl_wrBTerm,
Sl_wrComp => mb_plb_Sl_wrComp,
Sl_wrDAck => mb_plb_Sl_wrDAck,
Sl_MIRQ => mb_plb_Sl_MIRQ,
PLB_MIRQ => mb_plb_PLB_MIRQ,
PLB_ABus => mb_plb_PLB_ABus,
PLB_UABus => mb_plb_PLB_UABus,
PLB_BE => mb_plb_PLB_BE,
PLB_MAddrAck => mb_plb_PLB_MAddrAck,
PLB_MTimeout => mb_plb_PLB_MTimeout,
PLB_MBusy => mb_plb_PLB_MBusy,
PLB_MRdErr => mb_plb_PLB_MRdErr,
PLB_MWrErr => mb_plb_PLB_MWrErr,
PLB_MRdBTerm => mb_plb_PLB_MRdBTerm,
PLB_MRdDAck => mb_plb_PLB_MRdDAck,
PLB_MRdDBus => mb_plb_PLB_MRdDBus,
PLB_MRdWdAddr => mb_plb_PLB_MRdWdAddr,
PLB_MRearbitrate => mb_plb_PLB_MRearbitrate,
PLB_MWrBTerm => mb_plb_PLB_MWrBTerm,
PLB_MWrDAck => mb_plb_PLB_MWrDAck,
PLB_MSSize => mb_plb_PLB_MSSize,
PLB_PAValid => mb_plb_PLB_PAValid,
PLB_RNW => mb_plb_PLB_RNW,
PLB_SAValid => mb_plb_PLB_SAValid,
PLB_abort => mb_plb_PLB_abort,
PLB_busLock => mb_plb_PLB_busLock,
PLB_TAttribute => mb_plb_PLB_TAttribute,
PLB_lockErr => mb_plb_PLB_lockErr,
PLB_masterID => mb_plb_PLB_masterID(0 to 0),
PLB_MSize => mb_plb_PLB_MSize,
PLB_rdPendPri => mb_plb_PLB_rdPendPri,
PLB_wrPendPri => mb_plb_PLB_wrPendPri,
PLB_rdPendReq => mb_plb_PLB_rdPendReq,
PLB_wrPendReq => mb_plb_PLB_wrPendReq,
PLB_rdBurst => mb_plb_PLB_rdBurst,
PLB_rdPrim => mb_plb_PLB_rdPrim,
PLB_reqPri => mb_plb_PLB_reqPri,
PLB_size => mb_plb_PLB_size,
PLB_type => mb_plb_PLB_type,
PLB_wrBurst => mb_plb_PLB_wrBurst,
PLB_wrDBus => mb_plb_PLB_wrDBus,
PLB_wrPrim => mb_plb_PLB_wrPrim,
PLB_SaddrAck => open,
PLB_SMRdErr => open,
PLB_SMWrErr => open,
PLB_SMBusy => open,
PLB_SrdBTerm => open,
PLB_SrdComp => open,
PLB_SrdDAck => open,
PLB_SrdDBus => open,
PLB_SrdWdAddr => open,
PLB_Srearbitrate => open,
PLB_Sssize => open,
PLB_Swait => open,
PLB_SwrBTerm => open,
PLB_SwrComp => open,
PLB_SwrDAck => open,
Bus_Error_Det => open
);
ilmb : ilmb_wrapper
port map (
LMB_Clk => clk_50_0000MHz,
SYS_Rst => sys_bus_reset(0),
LMB_Rst => ilmb_LMB_Rst,
M_ABus => ilmb_M_ABus,
M_ReadStrobe => ilmb_M_ReadStrobe,
M_WriteStrobe => net_gnd0,
M_AddrStrobe => ilmb_M_AddrStrobe,
M_DBus => net_gnd32,
M_BE => net_gnd4,
Sl_DBus => ilmb_Sl_DBus,
Sl_Ready => ilmb_Sl_Ready(0 to 0),
Sl_Wait => ilmb_Sl_Wait(0 to 0),
Sl_UE => ilmb_Sl_UE(0 to 0),
Sl_CE => ilmb_Sl_CE(0 to 0),
LMB_ABus => ilmb_LMB_ABus,
LMB_ReadStrobe => ilmb_LMB_ReadStrobe,
LMB_WriteStrobe => ilmb_LMB_WriteStrobe,
LMB_AddrStrobe => ilmb_LMB_AddrStrobe,
LMB_ReadDBus => ilmb_LMB_ReadDBus,
LMB_WriteDBus => ilmb_LMB_WriteDBus,
LMB_Ready => ilmb_LMB_Ready,
LMB_Wait => ilmb_LMB_Wait,
LMB_UE => ilmb_LMB_UE,
LMB_CE => ilmb_LMB_CE,
LMB_BE => ilmb_LMB_BE
);
dlmb : dlmb_wrapper
port map (
LMB_Clk => clk_50_0000MHz,
SYS_Rst => sys_bus_reset(0),
LMB_Rst => dlmb_LMB_Rst,
M_ABus => dlmb_M_ABus,
M_ReadStrobe => dlmb_M_ReadStrobe,
M_WriteStrobe => dlmb_M_WriteStrobe,
M_AddrStrobe => dlmb_M_AddrStrobe,
M_DBus => dlmb_M_DBus,
M_BE => dlmb_M_BE,
Sl_DBus => dlmb_Sl_DBus,
Sl_Ready => dlmb_Sl_Ready(0 to 0),
Sl_Wait => dlmb_Sl_Wait(0 to 0),
Sl_UE => dlmb_Sl_UE(0 to 0),
Sl_CE => dlmb_Sl_CE(0 to 0),
LMB_ABus => dlmb_LMB_ABus,
LMB_ReadStrobe => dlmb_LMB_ReadStrobe,
LMB_WriteStrobe => dlmb_LMB_WriteStrobe,
LMB_AddrStrobe => dlmb_LMB_AddrStrobe,
LMB_ReadDBus => dlmb_LMB_ReadDBus,
LMB_WriteDBus => dlmb_LMB_WriteDBus,
LMB_Ready => dlmb_LMB_Ready,
LMB_Wait => dlmb_LMB_Wait,
LMB_UE => dlmb_LMB_UE,
LMB_CE => dlmb_LMB_CE,
LMB_BE => dlmb_LMB_BE
);
dlmb_cntlr : dlmb_cntlr_wrapper
port map (
LMB_Clk => clk_50_0000MHz,
LMB_Rst => dlmb_LMB_Rst,
LMB_ABus => dlmb_LMB_ABus,
LMB_WriteDBus => dlmb_LMB_WriteDBus,
LMB_AddrStrobe => dlmb_LMB_AddrStrobe,
LMB_ReadStrobe => dlmb_LMB_ReadStrobe,
LMB_WriteStrobe => dlmb_LMB_WriteStrobe,
LMB_BE => dlmb_LMB_BE,
Sl_DBus => dlmb_Sl_DBus,
Sl_Ready => dlmb_Sl_Ready(0),
Sl_Wait => dlmb_Sl_Wait(0),
Sl_UE => dlmb_Sl_UE(0),
Sl_CE => dlmb_Sl_CE(0),
BRAM_Rst_A => dlmb_port_BRAM_Rst,
BRAM_Clk_A => dlmb_port_BRAM_Clk,
BRAM_EN_A => dlmb_port_BRAM_EN,
BRAM_WEN_A => dlmb_port_BRAM_WEN,
BRAM_Addr_A => dlmb_port_BRAM_Addr,
BRAM_Din_A => dlmb_port_BRAM_Din,
BRAM_Dout_A => dlmb_port_BRAM_Dout,
Interrupt => open,
SPLB_CTRL_PLB_ABus => net_gnd32,
SPLB_CTRL_PLB_PAValid => net_gnd0,
SPLB_CTRL_PLB_masterID => net_gnd1(0 downto 0),
SPLB_CTRL_PLB_RNW => net_gnd0,
SPLB_CTRL_PLB_BE => net_gnd4,
SPLB_CTRL_PLB_size => net_gnd4,
SPLB_CTRL_PLB_type => net_gnd3,
SPLB_CTRL_PLB_wrDBus => net_gnd32,
SPLB_CTRL_Sl_addrAck => open,
SPLB_CTRL_Sl_SSize => open,
SPLB_CTRL_Sl_wait => open,
SPLB_CTRL_Sl_rearbitrate => open,
SPLB_CTRL_Sl_wrDAck => open,
SPLB_CTRL_Sl_wrComp => open,
SPLB_CTRL_Sl_rdDBus => open,
SPLB_CTRL_Sl_rdDAck => open,
SPLB_CTRL_Sl_rdComp => open,
SPLB_CTRL_Sl_MBusy => open,
SPLB_CTRL_Sl_MWrErr => open,
SPLB_CTRL_Sl_MRdErr => open,
SPLB_CTRL_PLB_UABus => net_gnd32,
SPLB_CTRL_PLB_SAValid => net_gnd0,
SPLB_CTRL_PLB_rdPrim => net_gnd0,
SPLB_CTRL_PLB_wrPrim => net_gnd0,
SPLB_CTRL_PLB_abort => net_gnd0,
SPLB_CTRL_PLB_busLock => net_gnd0,
SPLB_CTRL_PLB_MSize => net_gnd2(1 downto 0),
SPLB_CTRL_PLB_lockErr => net_gnd0,
SPLB_CTRL_PLB_wrBurst => net_gnd0,
SPLB_CTRL_PLB_rdBurst => net_gnd0,
SPLB_CTRL_PLB_wrPendReq => net_gnd0,
SPLB_CTRL_PLB_rdPendReq => net_gnd0,
SPLB_CTRL_PLB_wrPendPri => net_gnd2(1 downto 0),
SPLB_CTRL_PLB_rdPendPri => net_gnd2(1 downto 0),
SPLB_CTRL_PLB_reqPri => net_gnd2(1 downto 0),
SPLB_CTRL_PLB_TAttribute => net_gnd16,
SPLB_CTRL_Sl_wrBTerm => open,
SPLB_CTRL_Sl_rdWdAddr => open,
SPLB_CTRL_Sl_rdBTerm => open,
SPLB_CTRL_Sl_MIRQ => open,
S_AXI_CTRL_ACLK => net_vcc0,
S_AXI_CTRL_ARESETN => net_gnd0,
S_AXI_CTRL_AWADDR => net_gnd32(0 to 31),
S_AXI_CTRL_AWVALID => net_gnd0,
S_AXI_CTRL_AWREADY => open,
S_AXI_CTRL_WDATA => net_gnd32(0 to 31),
S_AXI_CTRL_WSTRB => net_gnd4(0 to 3),
S_AXI_CTRL_WVALID => net_gnd0,
S_AXI_CTRL_WREADY => open,
S_AXI_CTRL_BRESP => open,
S_AXI_CTRL_BVALID => open,
S_AXI_CTRL_BREADY => net_gnd0,
S_AXI_CTRL_ARADDR => net_gnd32(0 to 31),
S_AXI_CTRL_ARVALID => net_gnd0,
S_AXI_CTRL_ARREADY => open,
S_AXI_CTRL_RDATA => open,
S_AXI_CTRL_RRESP => open,
S_AXI_CTRL_RVALID => open,
S_AXI_CTRL_RREADY => net_gnd0
);
ilmb_cntlr : ilmb_cntlr_wrapper
port map (
LMB_Clk => clk_50_0000MHz,
LMB_Rst => ilmb_LMB_Rst,
LMB_ABus => ilmb_LMB_ABus,
LMB_WriteDBus => ilmb_LMB_WriteDBus,
LMB_AddrStrobe => ilmb_LMB_AddrStrobe,
LMB_ReadStrobe => ilmb_LMB_ReadStrobe,
LMB_WriteStrobe => ilmb_LMB_WriteStrobe,
LMB_BE => ilmb_LMB_BE,
Sl_DBus => ilmb_Sl_DBus,
Sl_Ready => ilmb_Sl_Ready(0),
Sl_Wait => ilmb_Sl_Wait(0),
Sl_UE => ilmb_Sl_UE(0),
Sl_CE => ilmb_Sl_CE(0),
BRAM_Rst_A => ilmb_port_BRAM_Rst,
BRAM_Clk_A => ilmb_port_BRAM_Clk,
BRAM_EN_A => ilmb_port_BRAM_EN,
BRAM_WEN_A => ilmb_port_BRAM_WEN,
BRAM_Addr_A => ilmb_port_BRAM_Addr,
BRAM_Din_A => ilmb_port_BRAM_Din,
BRAM_Dout_A => ilmb_port_BRAM_Dout,
Interrupt => open,
SPLB_CTRL_PLB_ABus => net_gnd32,
SPLB_CTRL_PLB_PAValid => net_gnd0,
SPLB_CTRL_PLB_masterID => net_gnd1(0 downto 0),
SPLB_CTRL_PLB_RNW => net_gnd0,
SPLB_CTRL_PLB_BE => net_gnd4,
SPLB_CTRL_PLB_size => net_gnd4,
SPLB_CTRL_PLB_type => net_gnd3,
SPLB_CTRL_PLB_wrDBus => net_gnd32,
SPLB_CTRL_Sl_addrAck => open,
SPLB_CTRL_Sl_SSize => open,
SPLB_CTRL_Sl_wait => open,
SPLB_CTRL_Sl_rearbitrate => open,
SPLB_CTRL_Sl_wrDAck => open,
SPLB_CTRL_Sl_wrComp => open,
SPLB_CTRL_Sl_rdDBus => open,
SPLB_CTRL_Sl_rdDAck => open,
SPLB_CTRL_Sl_rdComp => open,
SPLB_CTRL_Sl_MBusy => open,
SPLB_CTRL_Sl_MWrErr => open,
SPLB_CTRL_Sl_MRdErr => open,
SPLB_CTRL_PLB_UABus => net_gnd32,
SPLB_CTRL_PLB_SAValid => net_gnd0,
SPLB_CTRL_PLB_rdPrim => net_gnd0,
SPLB_CTRL_PLB_wrPrim => net_gnd0,
SPLB_CTRL_PLB_abort => net_gnd0,
SPLB_CTRL_PLB_busLock => net_gnd0,
SPLB_CTRL_PLB_MSize => net_gnd2(1 downto 0),
SPLB_CTRL_PLB_lockErr => net_gnd0,
SPLB_CTRL_PLB_wrBurst => net_gnd0,
SPLB_CTRL_PLB_rdBurst => net_gnd0,
SPLB_CTRL_PLB_wrPendReq => net_gnd0,
SPLB_CTRL_PLB_rdPendReq => net_gnd0,
SPLB_CTRL_PLB_wrPendPri => net_gnd2(1 downto 0),
SPLB_CTRL_PLB_rdPendPri => net_gnd2(1 downto 0),
SPLB_CTRL_PLB_reqPri => net_gnd2(1 downto 0),
SPLB_CTRL_PLB_TAttribute => net_gnd16,
SPLB_CTRL_Sl_wrBTerm => open,
SPLB_CTRL_Sl_rdWdAddr => open,
SPLB_CTRL_Sl_rdBTerm => open,
SPLB_CTRL_Sl_MIRQ => open,
S_AXI_CTRL_ACLK => net_vcc0,
S_AXI_CTRL_ARESETN => net_gnd0,
S_AXI_CTRL_AWADDR => net_gnd32(0 to 31),
S_AXI_CTRL_AWVALID => net_gnd0,
S_AXI_CTRL_AWREADY => open,
S_AXI_CTRL_WDATA => net_gnd32(0 to 31),
S_AXI_CTRL_WSTRB => net_gnd4(0 to 3),
S_AXI_CTRL_WVALID => net_gnd0,
S_AXI_CTRL_WREADY => open,
S_AXI_CTRL_BRESP => open,
S_AXI_CTRL_BVALID => open,
S_AXI_CTRL_BREADY => net_gnd0,
S_AXI_CTRL_ARADDR => net_gnd32(0 to 31),
S_AXI_CTRL_ARVALID => net_gnd0,
S_AXI_CTRL_ARREADY => open,
S_AXI_CTRL_RDATA => open,
S_AXI_CTRL_RRESP => open,
S_AXI_CTRL_RVALID => open,
S_AXI_CTRL_RREADY => net_gnd0
);
lmb_bram : lmb_bram_wrapper
port map (
BRAM_Rst_A => ilmb_port_BRAM_Rst,
BRAM_Clk_A => ilmb_port_BRAM_Clk,
BRAM_EN_A => ilmb_port_BRAM_EN,
BRAM_WEN_A => ilmb_port_BRAM_WEN,
BRAM_Addr_A => ilmb_port_BRAM_Addr,
BRAM_Din_A => ilmb_port_BRAM_Din,
BRAM_Dout_A => ilmb_port_BRAM_Dout,
BRAM_Rst_B => dlmb_port_BRAM_Rst,
BRAM_Clk_B => dlmb_port_BRAM_Clk,
BRAM_EN_B => dlmb_port_BRAM_EN,
BRAM_WEN_B => dlmb_port_BRAM_WEN,
BRAM_Addr_B => dlmb_port_BRAM_Addr,
BRAM_Din_B => dlmb_port_BRAM_Din,
BRAM_Dout_B => dlmb_port_BRAM_Dout
);
RS232_USB : rs232_usb_wrapper
port map (
SPLB_Clk => clk_50_0000MHz,
SPLB_Rst => mb_plb_SPLB_Rst(0),
PLB_ABus => mb_plb_PLB_ABus,
PLB_PAValid => mb_plb_PLB_PAValid,
PLB_masterID => mb_plb_PLB_masterID(0 to 0),
PLB_RNW => mb_plb_PLB_RNW,
PLB_BE => mb_plb_PLB_BE,
PLB_size => mb_plb_PLB_size,
PLB_type => mb_plb_PLB_type,
PLB_wrDBus => mb_plb_PLB_wrDBus,
PLB_UABus => mb_plb_PLB_UABus,
PLB_SAValid => mb_plb_PLB_SAValid,
PLB_rdPrim => mb_plb_PLB_rdPrim(0),
PLB_wrPrim => mb_plb_PLB_wrPrim(0),
PLB_abort => mb_plb_PLB_abort,
PLB_busLock => mb_plb_PLB_busLock,
PLB_MSize => mb_plb_PLB_MSize,
PLB_lockErr => mb_plb_PLB_lockErr,
PLB_wrBurst => mb_plb_PLB_wrBurst,
PLB_rdBurst => mb_plb_PLB_rdBurst,
PLB_wrPendReq => mb_plb_PLB_wrPendReq,
PLB_rdPendReq => mb_plb_PLB_rdPendReq,
PLB_wrPendPri => mb_plb_PLB_wrPendPri,
PLB_rdPendPri => mb_plb_PLB_rdPendPri,
PLB_reqPri => mb_plb_PLB_reqPri,
PLB_TAttribute => mb_plb_PLB_TAttribute,
Sl_addrAck => mb_plb_Sl_addrAck(0),
Sl_SSize => mb_plb_Sl_SSize(0 to 1),
Sl_wait => mb_plb_Sl_wait(0),
Sl_rearbitrate => mb_plb_Sl_rearbitrate(0),
Sl_wrDAck => mb_plb_Sl_wrDAck(0),
Sl_wrComp => mb_plb_Sl_wrComp(0),
Sl_rdDBus => mb_plb_Sl_rdDBus(0 to 31),
Sl_rdDAck => mb_plb_Sl_rdDAck(0),
Sl_rdComp => mb_plb_Sl_rdComp(0),
Sl_MBusy => mb_plb_Sl_MBusy(0 to 1),
Sl_MWrErr => mb_plb_Sl_MWrErr(0 to 1),
Sl_MRdErr => mb_plb_Sl_MRdErr(0 to 1),
Sl_wrBTerm => mb_plb_Sl_wrBTerm(0),
Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(0 to 3),
Sl_rdBTerm => mb_plb_Sl_rdBTerm(0),
Sl_MIRQ => mb_plb_Sl_MIRQ(0 to 1),
RX => fpga_0_RS232_USB_RX_pin,
TX => fpga_0_RS232_USB_TX_pin,
Interrupt => open
);
LEDs_8Bit : leds_8bit_wrapper
port map (
SPLB_Clk => clk_50_0000MHz,
SPLB_Rst => mb_plb_SPLB_Rst(1),
PLB_ABus => mb_plb_PLB_ABus,
PLB_UABus => mb_plb_PLB_UABus,
PLB_PAValid => mb_plb_PLB_PAValid,
PLB_SAValid => mb_plb_PLB_SAValid,
PLB_rdPrim => mb_plb_PLB_rdPrim(1),
PLB_wrPrim => mb_plb_PLB_wrPrim(1),
PLB_masterID => mb_plb_PLB_masterID(0 to 0),
PLB_abort => mb_plb_PLB_abort,
PLB_busLock => mb_plb_PLB_busLock,
PLB_RNW => mb_plb_PLB_RNW,
PLB_BE => mb_plb_PLB_BE,
PLB_MSize => mb_plb_PLB_MSize,
PLB_size => mb_plb_PLB_size,
PLB_type => mb_plb_PLB_type,
PLB_lockErr => mb_plb_PLB_lockErr,
PLB_wrDBus => mb_plb_PLB_wrDBus,
PLB_wrBurst => mb_plb_PLB_wrBurst,
PLB_rdBurst => mb_plb_PLB_rdBurst,
PLB_wrPendReq => mb_plb_PLB_wrPendReq,
PLB_rdPendReq => mb_plb_PLB_rdPendReq,
PLB_wrPendPri => mb_plb_PLB_wrPendPri,
PLB_rdPendPri => mb_plb_PLB_rdPendPri,
PLB_reqPri => mb_plb_PLB_reqPri,
PLB_TAttribute => mb_plb_PLB_TAttribute,
Sl_addrAck => mb_plb_Sl_addrAck(1),
Sl_SSize => mb_plb_Sl_SSize(2 to 3),
Sl_wait => mb_plb_Sl_wait(1),
Sl_rearbitrate => mb_plb_Sl_rearbitrate(1),
Sl_wrDAck => mb_plb_Sl_wrDAck(1),
Sl_wrComp => mb_plb_Sl_wrComp(1),
Sl_wrBTerm => mb_plb_Sl_wrBTerm(1),
Sl_rdDBus => mb_plb_Sl_rdDBus(32 to 63),
Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(4 to 7),
Sl_rdDAck => mb_plb_Sl_rdDAck(1),
Sl_rdComp => mb_plb_Sl_rdComp(1),
Sl_rdBTerm => mb_plb_Sl_rdBTerm(1),
Sl_MBusy => mb_plb_Sl_MBusy(2 to 3),
Sl_MWrErr => mb_plb_Sl_MWrErr(2 to 3),
Sl_MRdErr => mb_plb_Sl_MRdErr(2 to 3),
Sl_MIRQ => mb_plb_Sl_MIRQ(2 to 3),
IP2INTC_Irpt => open,
GPIO_IO_I => net_gnd8,
GPIO_IO_O => fpga_0_LEDs_8Bit_GPIO_IO_O_pin,
GPIO_IO_T => open,
GPIO2_IO_I => net_gnd32,
GPIO2_IO_O => open,
GPIO2_IO_T => open
);
Push_Buttons_3Bit : push_buttons_3bit_wrapper
port map (
SPLB_Clk => clk_50_0000MHz,
SPLB_Rst => mb_plb_SPLB_Rst(2),
PLB_ABus => mb_plb_PLB_ABus,
PLB_UABus => mb_plb_PLB_UABus,
PLB_PAValid => mb_plb_PLB_PAValid,
PLB_SAValid => mb_plb_PLB_SAValid,
PLB_rdPrim => mb_plb_PLB_rdPrim(2),
PLB_wrPrim => mb_plb_PLB_wrPrim(2),
PLB_masterID => mb_plb_PLB_masterID(0 to 0),
PLB_abort => mb_plb_PLB_abort,
PLB_busLock => mb_plb_PLB_busLock,
PLB_RNW => mb_plb_PLB_RNW,
PLB_BE => mb_plb_PLB_BE,
PLB_MSize => mb_plb_PLB_MSize,
PLB_size => mb_plb_PLB_size,
PLB_type => mb_plb_PLB_type,
PLB_lockErr => mb_plb_PLB_lockErr,
PLB_wrDBus => mb_plb_PLB_wrDBus,
PLB_wrBurst => mb_plb_PLB_wrBurst,
PLB_rdBurst => mb_plb_PLB_rdBurst,
PLB_wrPendReq => mb_plb_PLB_wrPendReq,
PLB_rdPendReq => mb_plb_PLB_rdPendReq,
PLB_wrPendPri => mb_plb_PLB_wrPendPri,
PLB_rdPendPri => mb_plb_PLB_rdPendPri,
PLB_reqPri => mb_plb_PLB_reqPri,
PLB_TAttribute => mb_plb_PLB_TAttribute,
Sl_addrAck => mb_plb_Sl_addrAck(2),
Sl_SSize => mb_plb_Sl_SSize(4 to 5),
Sl_wait => mb_plb_Sl_wait(2),
Sl_rearbitrate => mb_plb_Sl_rearbitrate(2),
Sl_wrDAck => mb_plb_Sl_wrDAck(2),
Sl_wrComp => mb_plb_Sl_wrComp(2),
Sl_wrBTerm => mb_plb_Sl_wrBTerm(2),
Sl_rdDBus => mb_plb_Sl_rdDBus(64 to 95),
Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(8 to 11),
Sl_rdDAck => mb_plb_Sl_rdDAck(2),
Sl_rdComp => mb_plb_Sl_rdComp(2),
Sl_rdBTerm => mb_plb_Sl_rdBTerm(2),
Sl_MBusy => mb_plb_Sl_MBusy(4 to 5),
Sl_MWrErr => mb_plb_Sl_MWrErr(4 to 5),
Sl_MRdErr => mb_plb_Sl_MRdErr(4 to 5),
Sl_MIRQ => mb_plb_Sl_MIRQ(4 to 5),
IP2INTC_Irpt => open,
GPIO_IO_I => fpga_0_Push_Buttons_3Bit_GPIO_IO_I_pin,
GPIO_IO_O => open,
GPIO_IO_T => open,
GPIO2_IO_I => net_gnd32,
GPIO2_IO_O => open,
GPIO2_IO_T => open
);
xps_timer_0 : xps_timer_0_wrapper
port map (
CaptureTrig0 => net_gnd0,
CaptureTrig1 => net_gnd0,
GenerateOut0 => open,
GenerateOut1 => open,
PWM0 => open,
Interrupt => open,
Freeze => net_gnd0,
SPLB_Clk => clk_50_0000MHz,
SPLB_Rst => mb_plb_SPLB_Rst(3),
PLB_ABus => mb_plb_PLB_ABus,
PLB_PAValid => mb_plb_PLB_PAValid,
PLB_masterID => mb_plb_PLB_masterID(0 to 0),
PLB_RNW => mb_plb_PLB_RNW,
PLB_BE => mb_plb_PLB_BE,
PLB_size => mb_plb_PLB_size,
PLB_type => mb_plb_PLB_type,
PLB_wrDBus => mb_plb_PLB_wrDBus,
Sl_addrAck => mb_plb_Sl_addrAck(3),
Sl_SSize => mb_plb_Sl_SSize(6 to 7),
Sl_wait => mb_plb_Sl_wait(3),
Sl_rearbitrate => mb_plb_Sl_rearbitrate(3),
Sl_wrDAck => mb_plb_Sl_wrDAck(3),
Sl_wrComp => mb_plb_Sl_wrComp(3),
Sl_rdDBus => mb_plb_Sl_rdDBus(96 to 127),
Sl_rdDAck => mb_plb_Sl_rdDAck(3),
Sl_rdComp => mb_plb_Sl_rdComp(3),
Sl_MBusy => mb_plb_Sl_MBusy(6 to 7),
Sl_MWrErr => mb_plb_Sl_MWrErr(6 to 7),
Sl_MRdErr => mb_plb_Sl_MRdErr(6 to 7),
PLB_UABus => mb_plb_PLB_UABus,
PLB_SAValid => mb_plb_PLB_SAValid,
PLB_rdPrim => mb_plb_PLB_rdPrim(3),
PLB_wrPrim => mb_plb_PLB_wrPrim(3),
PLB_abort => mb_plb_PLB_abort,
PLB_busLock => mb_plb_PLB_busLock,
PLB_MSize => mb_plb_PLB_MSize,
PLB_lockErr => mb_plb_PLB_lockErr,
PLB_wrBurst => mb_plb_PLB_wrBurst,
PLB_rdBurst => mb_plb_PLB_rdBurst,
PLB_wrPendReq => mb_plb_PLB_wrPendReq,
PLB_rdPendReq => mb_plb_PLB_rdPendReq,
PLB_wrPendPri => mb_plb_PLB_wrPendPri,
PLB_rdPendPri => mb_plb_PLB_rdPendPri,
PLB_reqPri => mb_plb_PLB_reqPri,
PLB_TAttribute => mb_plb_PLB_TAttribute,
Sl_wrBTerm => mb_plb_Sl_wrBTerm(3),
Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(12 to 15),
Sl_rdBTerm => mb_plb_Sl_rdBTerm(3),
Sl_MIRQ => mb_plb_Sl_MIRQ(6 to 7)
);
clock_generator_0 : clock_generator_0_wrapper
port map (
CLKIN => CLK_S,
CLKOUT0 => clk_50_0000MHz,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
CLKOUT7 => open,
CLKOUT8 => open,
CLKOUT9 => open,
CLKOUT10 => open,
CLKOUT11 => open,
CLKOUT12 => open,
CLKOUT13 => open,
CLKOUT14 => open,
CLKOUT15 => open,
CLKFBIN => net_gnd0,
CLKFBOUT => open,
PSCLK => net_gnd0,
PSEN => net_gnd0,
PSINCDEC => net_gnd0,
PSDONE => open,
RST => sys_rst_s,
LOCKED => Dcm_all_locked
);
mdm_0 : mdm_0_wrapper
port map (
Interrupt => open,
Debug_SYS_Rst => Debug_SYS_Rst,
Ext_BRK => Ext_BRK,
Ext_NM_BRK => Ext_NM_BRK,
S_AXI_ACLK => net_gnd0,
S_AXI_ARESETN => net_gnd0,
S_AXI_AWADDR => net_gnd32(0 to 31),
S_AXI_AWVALID => net_gnd0,
S_AXI_AWREADY => open,
S_AXI_WDATA => net_gnd32(0 to 31),
S_AXI_WSTRB => net_gnd4(0 to 3),
S_AXI_WVALID => net_gnd0,
S_AXI_WREADY => open,
S_AXI_BRESP => open,
S_AXI_BVALID => open,
S_AXI_BREADY => net_gnd0,
S_AXI_ARADDR => net_gnd32(0 to 31),
S_AXI_ARVALID => net_gnd0,
S_AXI_ARREADY => open,
S_AXI_RDATA => open,
S_AXI_RRESP => open,
S_AXI_RVALID => open,
S_AXI_RREADY => net_gnd0,
SPLB_Clk => clk_50_0000MHz,
SPLB_Rst => mb_plb_SPLB_Rst(4),
PLB_ABus => mb_plb_PLB_ABus,
PLB_UABus => mb_plb_PLB_UABus,
PLB_PAValid => mb_plb_PLB_PAValid,
PLB_SAValid => mb_plb_PLB_SAValid,
PLB_rdPrim => mb_plb_PLB_rdPrim(4),
PLB_wrPrim => mb_plb_PLB_wrPrim(4),
PLB_masterID => mb_plb_PLB_masterID(0 to 0),
PLB_abort => mb_plb_PLB_abort,
PLB_busLock => mb_plb_PLB_busLock,
PLB_RNW => mb_plb_PLB_RNW,
PLB_BE => mb_plb_PLB_BE,
PLB_MSize => mb_plb_PLB_MSize,
PLB_size => mb_plb_PLB_size,
PLB_type => mb_plb_PLB_type,
PLB_lockErr => mb_plb_PLB_lockErr,
PLB_wrDBus => mb_plb_PLB_wrDBus,
PLB_wrBurst => mb_plb_PLB_wrBurst,
PLB_rdBurst => mb_plb_PLB_rdBurst,
PLB_wrPendReq => mb_plb_PLB_wrPendReq,
PLB_rdPendReq => mb_plb_PLB_rdPendReq,
PLB_wrPendPri => mb_plb_PLB_wrPendPri,
PLB_rdPendPri => mb_plb_PLB_rdPendPri,
PLB_reqPri => mb_plb_PLB_reqPri,
PLB_TAttribute => mb_plb_PLB_TAttribute,
Sl_addrAck => mb_plb_Sl_addrAck(4),
Sl_SSize => mb_plb_Sl_SSize(8 to 9),
Sl_wait => mb_plb_Sl_wait(4),
Sl_rearbitrate => mb_plb_Sl_rearbitrate(4),
Sl_wrDAck => mb_plb_Sl_wrDAck(4),
Sl_wrComp => mb_plb_Sl_wrComp(4),
Sl_wrBTerm => mb_plb_Sl_wrBTerm(4),
Sl_rdDBus => mb_plb_Sl_rdDBus(128 to 159),
Sl_rdWdAddr => mb_plb_Sl_rdWdAddr(16 to 19),
Sl_rdDAck => mb_plb_Sl_rdDAck(4),
Sl_rdComp => mb_plb_Sl_rdComp(4),
Sl_rdBTerm => mb_plb_Sl_rdBTerm(4),
Sl_MBusy => mb_plb_Sl_MBusy(8 to 9),
Sl_MWrErr => mb_plb_Sl_MWrErr(8 to 9),
Sl_MRdErr => mb_plb_Sl_MRdErr(8 to 9),
Sl_MIRQ => mb_plb_Sl_MIRQ(8 to 9),
Dbg_Clk_0 => microblaze_0_mdm_bus_Dbg_Clk,
Dbg_TDI_0 => microblaze_0_mdm_bus_Dbg_TDI,
Dbg_TDO_0 => microblaze_0_mdm_bus_Dbg_TDO,
Dbg_Reg_En_0 => microblaze_0_mdm_bus_Dbg_Reg_En,
Dbg_Capture_0 => microblaze_0_mdm_bus_Dbg_Capture,
Dbg_Shift_0 => microblaze_0_mdm_bus_Dbg_Shift,
Dbg_Update_0 => microblaze_0_mdm_bus_Dbg_Update,
Dbg_Rst_0 => microblaze_0_mdm_bus_Debug_Rst,
Dbg_Clk_1 => open,
Dbg_TDI_1 => open,
Dbg_TDO_1 => net_gnd0,
Dbg_Reg_En_1 => open,
Dbg_Capture_1 => open,
Dbg_Shift_1 => open,
Dbg_Update_1 => open,
Dbg_Rst_1 => open,
Dbg_Clk_2 => open,
Dbg_TDI_2 => open,
Dbg_TDO_2 => net_gnd0,
Dbg_Reg_En_2 => open,
Dbg_Capture_2 => open,
Dbg_Shift_2 => open,
Dbg_Update_2 => open,
Dbg_Rst_2 => open,
Dbg_Clk_3 => open,
Dbg_TDI_3 => open,
Dbg_TDO_3 => net_gnd0,
Dbg_Reg_En_3 => open,
Dbg_Capture_3 => open,
Dbg_Shift_3 => open,
Dbg_Update_3 => open,
Dbg_Rst_3 => open,
Dbg_Clk_4 => open,
Dbg_TDI_4 => open,
Dbg_TDO_4 => net_gnd0,
Dbg_Reg_En_4 => open,
Dbg_Capture_4 => open,
Dbg_Shift_4 => open,
Dbg_Update_4 => open,
Dbg_Rst_4 => open,
Dbg_Clk_5 => open,
Dbg_TDI_5 => open,
Dbg_TDO_5 => net_gnd0,
Dbg_Reg_En_5 => open,
Dbg_Capture_5 => open,
Dbg_Shift_5 => open,
Dbg_Update_5 => open,
Dbg_Rst_5 => open,
Dbg_Clk_6 => open,
Dbg_TDI_6 => open,
Dbg_TDO_6 => net_gnd0,
Dbg_Reg_En_6 => open,
Dbg_Capture_6 => open,
Dbg_Shift_6 => open,
Dbg_Update_6 => open,
Dbg_Rst_6 => open,
Dbg_Clk_7 => open,
Dbg_TDI_7 => open,
Dbg_TDO_7 => net_gnd0,
Dbg_Reg_En_7 => open,
Dbg_Capture_7 => open,
Dbg_Shift_7 => open,
Dbg_Update_7 => open,
Dbg_Rst_7 => open,
bscan_tdi => open,
bscan_reset => open,
bscan_shift => open,
bscan_update => open,
bscan_capture => open,
bscan_sel1 => open,
bscan_drck1 => open,
bscan_tdo1 => net_gnd0,
Ext_JTAG_DRCK => open,
Ext_JTAG_RESET => open,
Ext_JTAG_SEL => open,
Ext_JTAG_CAPTURE => open,
Ext_JTAG_SHIFT => open,
Ext_JTAG_UPDATE => open,
Ext_JTAG_TDI => open,
Ext_JTAG_TDO => net_gnd0
);
proc_sys_reset_0 : proc_sys_reset_0_wrapper
port map (
Slowest_sync_clk => clk_50_0000MHz,
Ext_Reset_In => sys_rst_s,
Aux_Reset_In => net_gnd0,
MB_Debug_Sys_Rst => Debug_SYS_Rst,
Core_Reset_Req_0 => net_gnd0,
Chip_Reset_Req_0 => net_gnd0,
System_Reset_Req_0 => net_gnd0,
Core_Reset_Req_1 => net_gnd0,
Chip_Reset_Req_1 => net_gnd0,
System_Reset_Req_1 => net_gnd0,
Dcm_locked => Dcm_all_locked,
RstcPPCresetcore_0 => open,
RstcPPCresetchip_0 => open,
RstcPPCresetsys_0 => open,
RstcPPCresetcore_1 => open,
RstcPPCresetchip_1 => open,
RstcPPCresetsys_1 => open,
MB_Reset => mb_reset,
Bus_Struct_Reset => sys_bus_reset(0 to 0),
Peripheral_Reset => open,
Interconnect_aresetn => open,
Peripheral_aresetn => open
);
end architecture STRUCTURE;
|
gpl-2.0
|
6438e69b72450a296727ae9a7e0aec52
| 0.594908 | 2.960557 | false | false | false | false |
alextrem/red-diamond
|
fpga/vhdl/tb_i2s_tx.vhd
| 1 | 1,902 |
------------------------------------------------------------------------------
-- Company: Red Diamond
-- Engineer: Alexander Geissler
--
-- Create Date: 22:10:00 12/14/2016
-- Design Name: i2s_tx_tb.vhd
-- Project Name: red-diamond
-- Target Device: EP4CE22C8N
-- Tool Versions: 16.0
-- Description: This is a i2s tx modul Testbench.
-- Two 24 bit shift registers clock data to a D/A.
-- Key Features:
-- - configure receiver/transmitter, clock master/slave
-- word select master/slave
-- - ARM AMBA AXI4-Lite Bus (in future)
-- - Justification modes: normal, left, right
-- - Up to 8 I2S instances, configurable in different ways
-- - Testmodes
--
-- Dependencies:
--
-- Revision:
-- Revision 0.1 - File created
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.i2s_pkg.all;
use ieee.std_logic_textio.all;
entity i2s_tx_tb is
end entity i2s_tx_tb;
architecture sim of i2s_tx_tb is
signal sl_reset : std_logic := '0';
signal sl_clock : std_logic := '0';
signal slv_addr : std_logic_vector(c_addr-1 downto 0);
signal slv_l_channel : std_logic_vector(23 downto 0);
signal slv_r_channel : std_logic_vector(23 downto 0);
signal sl_wclk : std_logic;
signal sl_bclk : std_logic;
signal sl_sdata : std_logic;
begin
sl_clock <= not sl_clock after 10 ns;
sl_reset <= '0' after 20 ns, '1' after 60 ns;
uut: i2s_tx port map (
reset_n => sl_reset,
mclk => sl_clock,
-- input
i2s_in.l_channel => slv_l_channel,
i2s_in.r_channel => slv_r_channel,
-- output
i2s_out.wclk => sl_wclk,
i2s_out.bclk => sl_bclk,
i2s_out.sdata => sl_sdata
);
end sim;
|
gpl-3.0
|
7c3d55acce43690c8d615939175af616
| 0.543113 | 3.390374 | false | false | false | false |
jeffmagina/ECE368
|
Project1/FETCH/FETCH.vhd
| 1 | 1,707 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:35:41 03/04/2015
-- Design Name:
-- Module Name: FETCH_TOPLEVEL - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.all;
use IEEE.NUMERIC_STD.ALL;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;
entity FETCH is
Port ( CLK : in STD_LOGIC;
DATAIN : in STD_LOGIC_VECTOR( 15 downto 0);
INST_ENB : IN STD_LOGIC;
INST_OUT : out STD_LOGIC_VECTOR( 15 downto 0);
PC_OUT : out STD_LOGIC_VECTOR(9 downto 0);
WE : in STD_LOGIC);
end FETCH;
architecture Structural of FETCH is
signal instruction : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal PC : STD_LOGIC_VECTOR (9 downto 0) := (OTHERS => '0');
signal INC : STD_LOGIC_VECTOR (9 downto 0) := (OTHERS => '0');
begin
U1: entity work.INST_REG
port map( CLK => CLK,
INST_ENB => INST_ENB,
INST => instruction,
INST_OUT => INST_OUT);
U2: entity work.INST_MEM
port map( CLKA => CLK,
WEA(0)=> WE,
ADDRA => PC, -- (9 DOWNTO 0)
DINA => DATAIN, -- (15 DOWNTO 0)
CLKB => CLK,
ADDRB => PC, -- (9 DOWNTO 0)
DOUTB => instruction);
INC <= (PC + "0000000001");
U3: entity work.ProgramCounter
port map ( CLK => CLK,
NEW_PC => INC,
PC_OUT => PC);
PC_OUT <= PC;
end Structural;
|
mit
|
5540ca383956d0243675a9bd7cc5ba6f
| 0.524312 | 3.448485 | false | false | false | false |
jeffmagina/ECE368
|
Project1/OPERAND_ACCESS/register_bank.vhd
| 1 | 2,127 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Josh Tombs
--
-- Create Date: SPRING 2015
-- Module Name: Register Bank
-- Project Name: UMD_RISC16
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Create a register bank to hold m
-- registers of size n bits.
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity register_bank is
GENERIC ( M : INTEGER := 16; --Number of registers
N : INTEGER := 16; --Size of registers
A : INTEGER := 4); --Size of Addresses
Port( CLK : in STD_LOGIC;
ADDR_A : in STD_LOGIC_VECTOR (A-1 downto 0);
ADDR_B : in STD_LOGIC_VECTOR (A-1 downto 0);
W_ADDR : in STD_LOGIC_VECTOR (A-1 downto 0);
R_W : in STD_LOGIC; -- 0 = read, 1 = write
ENB : in STD_LOGIC;
DATA_IN : in STD_LOGIC_VECTOR (N-1 downto 0);
REG_A : out STD_LOGIC_VECTOR (N-1 downto 0);
REG_B : out STD_LOGIC_VECTOR (N-1 downto 0));
end register_bank;
architecture Behavioral of register_bank is
type bank_type is array (0 to M-1) of std_logic_vector (N-1 downto 0);
signal bank: bank_type := (others=> (others=>'0')); -- initialize all registers to "0000"
begin
PROCESS(CLK, ENB, R_W)
begin
if (CLK'EVENT and CLK = '1') then --rising edge event (read)
if(ENB = '1') then --enabled and read
REG_A <= bank(to_integer(unsigned(ADDR_A)));
REG_B <= bank(to_integer(unsigned(ADDR_B)));
end if;
end if;
end PROCESS;
PROCESS(CLK, ENB, R_W)
begin
if (CLK'EVENT and CLK = '0') then --falling edge event (write)
if(ENB = '1' and R_W = '1') then --enabled and write
bank(to_integer(unsigned(W_ADDR))) <= DATA_IN;
end if;
end if;
end PROCESS;
end Behavioral;
|
mit
|
d981d926e3196f257617179ebcbecf36
| 0.536906 | 3.635897 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ipshared/2479/hdl/axi_uartlite_v2_0_vh_rfs.vhd
| 2 | 106,753 |
-- dynshreg_i_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg_i_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
-- This version allows the client to specify the initial value
-- of the contents of the shift register, as applied
-- during configuration.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
--
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.all;
use lib_pkg_v1_0_2.lib_pkg.clog2;
--------------------------------------------------------------------------------
-- Explanations of generics and ports regarding aspects that may not be obvious.
--
-- C_DWIDTH
--------
-- Theoretically, C_DWIDTH may be set to zero and this could be a more
-- natural or preferrable way of excluding a dynamic shift register
-- in a client than using a VHDL Generate statement. However, this usage is not
-- tested, and the user should expect that some VHDL tools will be deficient
-- with respect to handling this properly.
--
-- C_INIT_VALUE
---------------
-- C_INIT_VALUE can be used to specify the initial values of the elements
-- in the dynamic shift register, i.e. the values to be present after config-
-- uration. C_INIT_VALUE need not be the same size as the dynamic shift
-- register, i.e. C_DWIDTH*C_DEPTH. When smaller, C_INIT_VALUE
-- is replicated as many times as needed (possibly fractionally the last time)
-- to form a full initial value that is the size of the shift register.
-- So, if C_INIT_VALUE is left at its default value--an array of size one
-- whose value is '0'--the shift register will initialize with all bits at
-- all addresses set to '0'. This will also be the case if C_INIT_VALUE is a
-- null (size zero) array.
-- When determined according to the rules outlined above, the full
-- initial value is a std_logic_vector value from (0 to C_DWIDTH*C_DEPTH-1). It
-- is allocated to the addresses of the dynamic shift register in this
-- manner: The first C_DWIDTH values (i.e. 0 to C_CWIDTH-1) assigned to
-- the corresponding indices at address 0, the second C_DWIDTH values
-- assigned to address 1, and so forth.
-- Please note that the shift register is not resettable after configuration.
--
-- Addr
----
-- Addr addresses the elements of the dynamic shift register. Addr=0 causes
-- the most recently shifted-in element to appear at Dout, Addr=1
-- the second most recently shifted in element, etc. If C_DEPTH is not
-- a power of two, then not all of the values of Addr correspond to an
-- element in the shift register. When such an address is applied, the value
-- of Dout is undefined until a valid address is established.
--------------------------------------------------------------------------------
entity dynshreg_i_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_INIT_VALUE : bit_vector := "0";
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg_i_f;
architecture behavioral of dynshreg_i_f is
constant USE_INFERRED : boolean := true;
type bv2sl_type is array(bit) of std_logic;
constant bv2sl : bv2sl_type := ('0' => '0', '1' => '1');
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
--
------------------------------------------------------------------------------
-- Function used to establish the full initial value. (See the comments for
-- C_INIT_VALUE, above.)
------------------------------------------------------------------------------
function full_initial_value(w : natural; d : positive; v : bit_vector
) return bit_vector is
variable r : bit_vector(0 to w*d-1);
variable i, j : natural;
-- i - the index where filling of r continues
-- j - the amount to fill on the cur. iteration of the while loop
begin
if w = 0 then null; -- Handle the case where the shift reg width is zero
elsif v'length = 0 then r := (others => '0');
else
i := 0;
while i /= r'length loop
j := min(v'length, r'length-i);
r(i to i+j-1) := v(0 to j-1);
i := i+j;
end loop;
end if;
return r;
end full_initial_value;
constant FULL_INIT_VAL : bit_vector(0 to C_DWIDTH*C_DEPTH -1)
:= full_initial_value(C_DWIDTH, C_DEPTH, C_INIT_VALUE);
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
begin
INFERRED_GEN : if USE_INFERRED = true generate
--
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
--
function fill_data(w: natural; d: positive; v: bit_vector
) return dataType is
variable r : dataType;
begin
for i in 0 to d-1 loop
for j in 0 to w-1 loop
r(i)(j) := bv2sl(v(i*w+j));
end loop;
end loop;
return r;
end fill_data;
signal data: dataType := fill_data(C_DWIDTH, C_DEPTH, FULL_INIT_VAL);
--
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
end behavioral;
-------------------------------------------------------------------------------
-- uartlite_tx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_tx.vhd
-- Version: v2.0
-- Description: UART Lite Transmit Interface Module
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.UNSIGNED;
use IEEE.numeric_std.to_unsigned;
use IEEE.numeric_std."-";
library lib_srl_fifo_v1_0_2;
-- dynshreg_i_f refered from proc_common_v4_0_20_a
library axi_uartlite_v2_0_15;
-- uartlite_core refered from axi_uartlite_v2_0_15
use axi_uartlite_v2_0_15.all;
-- srl_fifo_f refered from proc_common_v4_0_20_a
use lib_srl_fifo_v1_0_2.srl_fifo_f;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- UART Lite interface
-- TX -- Transmit Data
-- Internal UART interface signals
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
-- Write_TX_FIFO -- Write transmit FIFO
-- Reset_TX_FIFO -- Reset transmit FIFO
-- TX_Data -- Transmit data input
-- TX_Buffer_Full -- Transmit buffer full
-- TX_Buffer_Empty -- Transmit buffer empty
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_tx is
generic
(
C_FAMILY : string := "virtex7";
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
EN_16x_Baud : in std_logic;
TX : out std_logic;
Write_TX_FIFO : in std_logic;
Reset_TX_FIFO : in std_logic;
TX_Data : in std_logic_vector(0 to C_DATA_BITS-1);
TX_Buffer_Full : out std_logic;
TX_Buffer_Empty : out std_logic
);
end entity uartlite_tx;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_tx is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
type bo2sl_type is array(boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
-------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------
constant MUX_SEL_INIT : std_logic_vector(0 to 2) :=
std_logic_vector(to_unsigned(C_DATA_BITS-1, 3));
-------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------
signal parity : std_logic;
signal tx_Run1 : std_logic;
signal select_Parity : std_logic;
signal data_to_transfer : std_logic_vector(0 to C_DATA_BITS-1);
signal div16 : std_logic;
signal tx_Data_Enable : std_logic;
signal tx_Start : std_logic;
signal tx_DataBits : std_logic;
signal tx_Run : std_logic;
signal mux_sel : std_logic_vector(0 to 2);
signal mux_sel_is_zero : std_logic;
signal mux_01 : std_logic;
signal mux_23 : std_logic;
signal mux_45 : std_logic;
signal mux_67 : std_logic;
signal mux_0123 : std_logic;
signal mux_4567 : std_logic;
signal mux_Out : std_logic;
signal serial_Data : std_logic;
signal fifo_Read : std_logic;
signal fifo_Data_Present : std_logic := '0';
signal fifo_Data_Empty : std_logic;
signal fifo_DOut : std_logic_vector(0 to C_DATA_BITS-1);
signal fifo_wr : std_logic;
signal fifo_rd : std_logic;
signal tx_buffer_full_i : std_logic;
signal TX_FIFO_Reset : std_logic;
begin -- architecture IMP
---------------------------------------------------------------------------
--MID_START_BIT_SRL16_I : Shift register is used to generate div16 that
-- gets shifted for 16 times(as Addr = 15) when
-- EN_16x_Baud is high.
---------------------------------------------------------------------------
MID_START_BIT_SRL16_I : entity axi_uartlite_v2_0_15.dynshreg_i_f
generic map
(
C_DEPTH => 16,
C_DWIDTH => 1,
C_INIT_VALUE => X"8000",
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Clken => EN_16x_Baud,
Addr => "1111",
Din(0) => div16,
Dout(0) => div16
);
------------------------------------------------------------------------
-- TX_DATA_ENABLE_DFF : tx_Data_Enable is '1' when div16 is 1 and
-- EN_16x_Baud is 1. It will deasserted in the
-- next clock cycle.
------------------------------------------------------------------------
TX_DATA_ENABLE_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Data_Enable <= '0';
else
if (tx_Data_Enable = '1') then
tx_Data_Enable <= '0';
elsif (EN_16x_Baud = '1') then
tx_Data_Enable <= div16;
end if;
end if;
end if;
end process TX_DATA_ENABLE_DFF;
------------------------------------------------------------------------
-- TX_START_DFF : tx_start is '1' for the start bit in a transmission
------------------------------------------------------------------------
TX_START_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Start <= '0';
else
tx_Start <= (not(tx_Run) and (tx_Start or
(fifo_Data_Present and tx_Data_Enable)));
end if;
end if;
end process TX_START_DFF;
--------------------------------------------------------------------------
-- TX_DATA_DFF : tx_DataBits is '1' during all databits transmission
--------------------------------------------------------------------------
TX_DATA_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_DataBits <= '0';
else
tx_DataBits <= (not(fifo_Read) and (tx_DataBits or
(tx_Start and tx_Data_Enable)));
end if;
end if;
end process TX_DATA_DFF;
-------------------------------------------------------------------------
-- COUNTER : If mux_sel is zero then reload with the init value else if
-- tx_DataBits = '1', decrement
-------------------------------------------------------------------------
COUNTER : process (Clk) is
begin -- process Mux_Addr_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
mux_sel <= std_logic_vector(to_unsigned(C_DATA_BITS-1,
mux_sel'length));
elsif (tx_Data_Enable = '1') then
if (mux_sel_is_zero = '1') then
mux_sel <= MUX_SEL_INIT;
elsif (tx_DataBits = '1') then
mux_sel <= std_logic_vector(UNSIGNED(mux_sel) - 1);
end if;
end if;
end if;
end process COUNTER;
------------------------------------------------------------------------
-- Detecting when mux_sel is zero, i.e. all data bits are transfered
------------------------------------------------------------------------
mux_sel_is_zero <= '1' when mux_sel = "000" else '0';
--------------------------------------------------------------------------
-- FIFO_READ_DFF : Read out the next data from the transmit fifo when the
-- data has been transmitted
--------------------------------------------------------------------------
FIFO_READ_DFF : process (Clk) is
begin -- process FIFO_Read_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
fifo_Read <= '0';
else
fifo_Read <= tx_Data_Enable and mux_sel_is_zero;
end if;
end if;
end process FIFO_READ_DFF;
--------------------------------------------------------------------------
-- Select which bit within the data word to transmit
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- PARITY_BIT_INSERTION : Need special treatment for inserting the parity
-- bit because of parity generation
--------------------------------------------------------------------------
data_to_transfer(0 to C_DATA_BITS-2) <= fifo_DOut(0 to C_DATA_BITS-2);
data_to_transfer(C_DATA_BITS-1) <= parity when select_Parity = '1' else
fifo_DOut(C_DATA_BITS-1);
mux_01 <= data_to_transfer(1) when mux_sel(2) = '1' else
data_to_transfer(0);
mux_23 <= data_to_transfer(3) when mux_sel(2) = '1' else
data_to_transfer(2);
--------------------------------------------------------------------------
-- DATA_BITS_IS_5 : Select total 5 data bits when C_DATA_BITS = 5
--------------------------------------------------------------------------
DATA_BITS_IS_5 : if (C_DATA_BITS = 5) generate
mux_45 <= data_to_transfer(4);
mux_67 <= '0';
end generate DATA_BITS_IS_5;
--------------------------------------------------------------------------
-- DATA_BITS_IS_6 : Select total 6 data bits when C_DATA_BITS = 6
--------------------------------------------------------------------------
DATA_BITS_IS_6 : if (C_DATA_BITS = 6) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= '0';
end generate DATA_BITS_IS_6;
--------------------------------------------------------------------------
-- DATA_BITS_IS_7 : Select total 7 data bits when C_DATA_BITS = 7
--------------------------------------------------------------------------
DATA_BITS_IS_7 : if (C_DATA_BITS = 7) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= data_to_transfer(6);
end generate DATA_BITS_IS_7;
--------------------------------------------------------------------------
-- DATA_BITS_IS_8 : Select total 8 data bits when C_DATA_BITS = 8
--------------------------------------------------------------------------
DATA_BITS_IS_8 : if (C_DATA_BITS = 8) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= data_to_transfer(7) when mux_sel(2) = '1' else
data_to_transfer(6);
end generate DATA_BITS_IS_8;
mux_0123 <= mux_23 when mux_sel(1) = '1' else mux_01;
mux_4567 <= mux_67 when mux_sel(1) = '1' else mux_45;
mux_Out <= mux_4567 when mux_sel(0) = '1' else mux_0123;
--------------------------------------------------------------------------
-- SERIAL_DATA_DFF : Register the mux_Out
--------------------------------------------------------------------------
SERIAL_DATA_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
serial_Data <= '0';
else
serial_Data <= mux_Out;
end if;
end if;
end process SERIAL_DATA_DFF;
--------------------------------------------------------------------------
-- SERIAL_OUT_DFF :Force a '0' when tx_start is '1', Start_bit
-- Force a '1' when tx_run is '0', Idle
-- otherwise put out the serial_data
--------------------------------------------------------------------------
SERIAL_OUT_DFF : process (Clk) is
begin -- process Serial_Out_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
TX <= '1';
else
TX <= (not(tx_Run) or serial_Data) and (not(tx_Start));
end if;
end if;
end process SERIAL_OUT_DFF;
--------------------------------------------------------------------------
-- USING_PARITY : Generate parity handling when C_USE_PARITY = 1
--------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
PARITY_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (tx_Start = '1') then
parity <= bo2sl(C_ODD_PARITY = 1);
elsif (tx_Data_Enable = '1') then
parity <= parity xor serial_Data;
end if;
end if;
end process PARITY_DFF;
TX_RUN1_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Run1 <= '0';
elsif (tx_Data_Enable = '1') then
tx_Run1 <= tx_DataBits;
end if;
end if;
end process TX_RUN1_DFF;
tx_Run <= tx_Run1 or tx_DataBits;
SELECT_PARITY_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
select_Parity <= '0';
elsif (tx_Data_Enable = '1') then
select_Parity <= mux_sel_is_zero;
end if;
end if;
end process SELECT_PARITY_DFF;
end generate USING_PARITY;
--------------------------------------------------------------------------
-- NO_PARITY : When C_USE_PARITY = 0 select parity as '0'
--------------------------------------------------------------------------
NO_PARITY : if (C_USE_PARITY = 0) generate
tx_Run <= tx_DataBits;
select_Parity <= '0';
end generate NO_PARITY;
--------------------------------------------------------------------------
-- Write TX FIFO when FIFO is not full when AXI writes data in TX FIFO
--------------------------------------------------------------------------
fifo_wr <= Write_TX_FIFO and (not tx_buffer_full_i);
--------------------------------------------------------------------------
-- Read TX FIFO when FIFO is not empty when AXI reads data from TX FIFO
--------------------------------------------------------------------------
fifo_rd <= fifo_Read and (not fifo_Data_Empty);
--------------------------------------------------------------------------
-- Reset TX FIFO when requested from the control register or system reset
--------------------------------------------------------------------------
TX_FIFO_Reset <= Reset_TX_FIFO or Reset;
--------------------------------------------------------------------------
-- SRL_FIFO_I : Transmit FIFO Interface
--------------------------------------------------------------------------
SRL_FIFO_I : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map
(
C_DWIDTH => C_DATA_BITS,
C_DEPTH => 16,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Reset => TX_FIFO_Reset,
FIFO_Write => fifo_wr,
Data_In => TX_Data,
FIFO_Read => fifo_rd,
Data_Out => fifo_DOut,
FIFO_Full => tx_buffer_full_i,
FIFO_Empty => fifo_Data_Empty
);
TX_Buffer_Full <= tx_buffer_full_i;
TX_Buffer_Empty <= fifo_Data_Empty;
fifo_Data_Present <= not fifo_Data_Empty;
end architecture RTL;
-------------------------------------------------------------------------------
-- uartlite_rx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_rx.vhd
-- Version: v2.0
-- Description: UART Lite Receive Interface Module
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lib_srl_fifo_v1_0_2;
library lib_cdc_v1_0_2;
use lib_cdc_v1_0_2.cdc_sync;
-- dynshreg_i_f refered from proc_common_v4_0_2
-- srl_fifo_f refered from proc_common_v4_0_2
use lib_srl_fifo_v1_0_2.srl_fifo_f;
library axi_uartlite_v2_0_15;
-- uartlite_core refered from axi_uartlite_v2_0_15
use axi_uartlite_v2_0_15.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
--
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- UART Lite interface
-- RX -- Receive Data
-- Internal UART interface signals
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
-- Read_RX_FIFO -- Read receive FIFO
-- Reset_RX_FIFO -- Reset receive FIFO
-- RX_Data -- Receive data output
-- RX_Data_Present -- Receive data present
-- RX_Buffer_Full -- Receive buffer full
-- RX_Frame_Error -- Receive frame error
-- RX_Overrun_Error -- Receive overrun error
-- RX_Parity_Error -- Receive parity error
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_rx is
generic
(
C_FAMILY : string := "virtex7";
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
EN_16x_Baud : in std_logic;
RX : in std_logic;
Read_RX_FIFO : in std_logic;
Reset_RX_FIFO : in std_logic;
RX_Data : out std_logic_vector(0 to C_DATA_BITS-1);
RX_Data_Present : out std_logic;
RX_Buffer_Full : out std_logic;
RX_Frame_Error : out std_logic;
RX_Overrun_Error : out std_logic;
RX_Parity_Error : out std_logic
);
end entity uartlite_rx;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_rx is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
type bo2sl_type is array(boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
---------------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------------
constant SERIAL_TO_PAR_LENGTH : integer :=
C_DATA_BITS + C_USE_PARITY;
constant STOP_BIT_POS : integer := SERIAL_TO_PAR_LENGTH;
constant DATA_LSB_POS : integer := SERIAL_TO_PAR_LENGTH;
constant CALC_PAR_POS : integer := SERIAL_TO_PAR_LENGTH;
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
signal start_Edge_Detected : boolean;
signal start_Edge_Detected_Bit : std_logic;
signal running : boolean;
signal recycle : std_logic;
signal sample_Point : std_logic;
signal stop_Bit_Position : std_logic;
signal fifo_Write : std_logic;
signal fifo_din : std_logic_vector(0 to SERIAL_TO_PAR_LENGTH);
signal serial_to_Par : std_logic_vector(1 to SERIAL_TO_PAR_LENGTH);
signal calc_parity : std_logic;
signal parity : std_logic;
signal RX_Buffer_Full_I : std_logic;
signal RX_D1 : std_logic;
signal RX_D2 : std_logic;
signal rx_1 : std_logic;
signal rx_2 : std_logic;
signal rx_3 : std_logic;
signal rx_4 : std_logic;
signal rx_5 : std_logic;
signal rx_6 : std_logic;
signal rx_7 : std_logic;
signal rx_8 : std_logic;
signal rx_9 : std_logic;
signal rx_Data_Empty : std_logic := '0';
signal fifo_wr : std_logic;
signal fifo_rd : std_logic;
signal RX_FIFO_Reset : std_logic;
signal valid_rx : std_logic;
signal valid_start : std_logic;
signal frame_err_ocrd : std_logic;
signal frame_err : std_logic;
begin -- architecture RTL
---------------------------------------------------------------------------
-- RX_SAMPLING : Double sample RX to avoid meta-stability
---------------------------------------------------------------------------
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => RX,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => RX_D2,
scndry_vect_out => open
);
-- RX_SAMPLING: process (Clk) is
-- begin -- process RX_Sampling
-- if Clk'event and Clk = '1' then -- rising clock edge
-- if Reset = '1' then -- synchronous reset (active high)
-- RX_D1 <= '1';
-- RX_D2 <= '1';
-- else
-- RX_D1 <= RX;
-- RX_D2 <= RX_D1;
-- end if;
-- end if;
-- end process RX_SAMPLING;
-------------------------------------------------------------------------------
-- Detect a falling edge on RX and start a new reception if idle
-------------------------------------------------------------------------------
---------------------------------------------------------------------------
-- detect the start of the frame
---------------------------------------------------------------------------
RX_DFFS : process (Clk) is
begin -- process Prev_RX_DFFS
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then
rx_1 <= '0';
rx_2 <= '0';
rx_3 <= '0';
rx_4 <= '0';
rx_5 <= '0';
rx_6 <= '0';
rx_7 <= '0';
rx_8 <= '0';
rx_9 <= '0';
elsif (EN_16x_Baud = '1') then
rx_1 <= RX_D2;
rx_2 <= rx_1;
rx_3 <= rx_2;
rx_4 <= rx_3;
rx_5 <= rx_4;
rx_6 <= rx_5;
rx_7 <= rx_6;
rx_8 <= rx_7;
rx_9 <= rx_8;
end if;
end if;
end process RX_DFFS;
---------------------------------------------------------------------------
-- Start bit valid when RX is continuously low for atleast 8 samples
---------------------------------------------------------------------------
valid_start <= rx_8 or rx_7 or rx_6 or rx_5 or
rx_4 or rx_3 or rx_2 or rx_1;
---------------------------------------------------------------------------
-- START_EDGE_DFF : Start a new reception if idle
---------------------------------------------------------------------------
START_EDGE_DFF : process (Clk) is
begin -- process Start_Edge_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then
start_Edge_Detected <= false;
elsif (EN_16x_Baud = '1') then
start_Edge_Detected <= ((not running) and
(frame_err_ocrd = '0') and
(rx_9 = '1') and
(valid_start = '0'));
end if;
end if;
end process START_EDGE_DFF;
---------------------------------------------------------------------------
-- FRAME_ERR_CAPTURE : frame_err_ocrd is '1' when a frame error is occured
-- and deasserted when the next low to high on RX
---------------------------------------------------------------------------
FRAME_ERR_CAPTURE : process (Clk) is
begin -- process valid_rx_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
frame_err_ocrd <= '0';
elsif (frame_err = '1') then
frame_err_ocrd <= '1';
elsif (RX_D2 = '1') then
frame_err_ocrd <= '0';
end if;
end if;
end process FRAME_ERR_CAPTURE;
---------------------------------------------------------------------------
-- VALID_XFER : valid_rx is '1' when a valid start edge detected
---------------------------------------------------------------------------
VALID_XFER : process (Clk) is
begin -- process valid_rx_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
valid_rx <= '0';
elsif (start_Edge_Detected = true) then
valid_rx <= '1';
elsif (fifo_Write = '1') then
valid_rx <= '0';
end if;
end if;
end process VALID_XFER;
---------------------------------------------------------------------------
-- RUNNING_DFF : Running is '1' during a reception
---------------------------------------------------------------------------
RUNNING_DFF : process (Clk) is
begin -- process Running_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
running <= false;
elsif (EN_16x_Baud = '1') then
if (start_Edge_Detected) then
running <= true;
elsif ((sample_Point = '1') and (stop_Bit_Position = '1')) then
running <= false;
end if;
end if;
end if;
end process RUNNING_DFF;
---------------------------------------------------------------------------
-- Boolean to std logic conversion of start edge
---------------------------------------------------------------------------
start_Edge_Detected_Bit <= '1' when start_Edge_Detected else '0';
---------------------------------------------------------------------------
-- After the start edge is detected, generate recycle to generate sample
-- point
---------------------------------------------------------------------------
recycle <= (valid_rx and (not stop_Bit_Position) and
(start_Edge_Detected_Bit or sample_Point));
-------------------------------------------------------------------------
-- DELAY_16_I : Keep regenerating new values into the 16 clock delay,
-- Starting with the first start_Edge_Detected_Bit and for every new
-- sample_points until stop_Bit_Position is reached
-------------------------------------------------------------------------
DELAY_16_I : entity axi_uartlite_v2_0_15.dynshreg_i_f
generic map
(
C_DEPTH => 16,
C_DWIDTH => 1,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Clken => EN_16x_Baud,
Addr => "1111",
Din(0) => recycle,
Dout(0) => sample_Point
);
---------------------------------------------------------------------------
-- STOP_BIT_HANDLER : Detect when the stop bit is received
---------------------------------------------------------------------------
STOP_BIT_HANDLER : process (Clk) is
begin -- process Stop_Bit_Handler
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
stop_Bit_Position <= '0';
elsif (EN_16x_Baud = '1') then
if (stop_Bit_Position = '0') then
-- Start bit has reached the end of the shift register
-- (Stop bit position)
stop_Bit_Position <= sample_Point and
fifo_din(STOP_BIT_POS);
elsif (sample_Point = '1') then
-- if stop_Bit_Position is 1 clear it at next sample_Point
stop_Bit_Position <= '0';
end if;
end if;
end if;
end process STOP_BIT_HANDLER;
USING_PARITY_NO : if (C_USE_PARITY = 0) generate
RX_Parity_Error <= '0' ;
end generate USING_PARITY_NO;
---------------------------------------------------------------------------
-- USING_PARITY : Generate parity handling when C_USE_PARITY = 1
---------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
PARITY_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1' or start_Edge_Detected_Bit = '1') then
parity <= bo2sl(C_ODD_PARITY = 1);
elsif (EN_16x_Baud = '1') then
parity <= calc_parity;
end if;
end if;
end process PARITY_DFF;
calc_parity <= parity when (stop_Bit_Position or
(not sample_Point)) = '1'
else parity xor RX_D2;
RX_Parity_Error <= (EN_16x_Baud and sample_Point) and
(fifo_din(CALC_PAR_POS)) and not stop_Bit_Position
when running and (RX_D2 /= parity) else '0';
end generate USING_PARITY;
fifo_din(0) <= RX_D2 and not Reset;
---------------------------------------------------------------------------
-- SERIAL_TO_PARALLEL : Serial to parrallel conversion data part
---------------------------------------------------------------------------
SERIAL_TO_PARALLEL : for i in 1 to serial_to_Par'length generate
serial_to_Par(i) <= fifo_din(i) when (stop_Bit_Position or
not sample_Point) = '1'
else fifo_din(i-1);
BIT_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
fifo_din(i) <= '0'; -- Bit STOP_BIT_POS resets to '0';
else -- others to '1'
if (start_Edge_Detected_Bit = '1') then
fifo_din(i) <= bo2sl(i=1); -- Bit 1 resets to '1';
-- others to '0'
elsif (EN_16x_Baud = '1') then
fifo_din(i) <= serial_to_Par(i);
end if;
end if;
end if;
end process BIT_I;
end generate SERIAL_TO_PARALLEL;
--------------------------------------------------------------------------
-- FIFO_WRITE_DFF : Write in the received word when the stop_bit has been
-- received and it is a '1'
--------------------------------------------------------------------------
FIFO_WRITE_DFF : process (Clk) is
begin -- process FIFO_Write_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
fifo_Write <= '0';
else
fifo_Write <= stop_Bit_Position and RX_D2 and sample_Point
and EN_16x_Baud;
end if;
end if;
end process FIFO_WRITE_DFF;
frame_err <= stop_Bit_Position and sample_Point and EN_16x_Baud
and not RX_D2;
RX_Frame_Error <= frame_err;
--------------------------------------------------------------------------
-- Write RX FIFO when FIFO is not full when valid data is reveived
--------------------------------------------------------------------------
fifo_wr <= fifo_Write and (not RX_Buffer_Full_I) and valid_rx;
--------------------------------------------------------------------------
-- Read RX FIFO when FIFO is not empty when AXI reads data from RX FIFO
--------------------------------------------------------------------------
fifo_rd <= Read_RX_FIFO and (not rx_Data_Empty);
--------------------------------------------------------------------------
-- Reset RX FIFO when requested from the control register or system reset
--------------------------------------------------------------------------
RX_FIFO_Reset <= Reset_RX_FIFO or Reset;
---------------------------------------------------------------------------
-- SRL_FIFO_I : Receive FIFO Interface
---------------------------------------------------------------------------
SRL_FIFO_I : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map
(
C_DWIDTH => C_DATA_BITS,
C_DEPTH => 16,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Reset => RX_FIFO_Reset,
FIFO_Write => fifo_wr,
Data_In => fifo_din((DATA_LSB_POS-C_DATA_BITS + 1) to DATA_LSB_POS),
FIFO_Read => fifo_rd,
Data_Out => RX_Data,
FIFO_Full => RX_Buffer_Full_I,
FIFO_Empty => rx_Data_Empty,
Addr => open
);
RX_Data_Present <= not rx_Data_Empty;
RX_Overrun_Error <= RX_Buffer_Full_I and fifo_Write; -- Note that if
-- the RX FIFO is read on the same cycle as it is written while full,
-- there is no loss of data. However this case is not optimized and
-- is also reported as an overrun.
RX_Buffer_Full <= RX_Buffer_Full_I;
end architecture RTL;
-------------------------------------------------------------------------------
-- baudrate - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: baudrate.vhd
-- Version: v2.0
-- Description: Baud rate enable logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_RATIO -- The ratio between clk and the asked baudrate
-- multiplied with 16
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Reset -- Reset signal
-- Internal UART interface signals
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity baudrate is
generic
(
C_RATIO : integer := 48 -- The ratio between clk and the asked
-- baudrate multiplied with 16
);
port
(
Clk : in std_logic;
Reset : in std_logic;
EN_16x_Baud : out std_logic
);
end entity baudrate;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of baudrate is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
---------------------------------------------------------------------------
-- Signal Declarations
---------------------------------------------------------------------------
signal count : natural range 0 to C_RATIO-1;
begin -- architecture VHDL_RTL
---------------------------------------------------------------------------
-- COUNTER_PROCESS : Down counter for generating EN_16x_Baud signal
---------------------------------------------------------------------------
COUNTER_PROCESS : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then
count <= 0;
EN_16x_Baud <= '0';
else
if (count = 0) then
count <= C_RATIO-1;
EN_16x_Baud <= '1';
else
count <= count - 1;
EN_16x_Baud <= '0';
end if;
end if;
end if;
end process COUNTER_PROCESS;
end architecture RTL;
-------------------------------------------------------------------------------
-- uartlite_core - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2012] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_core.vhd
-- Version: v2.0
-- Description: UART Lite core for implementing UART logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_uartlite_v2_0_15;
-- baudrate refered from axi_uartlite_v2_0_15
use axi_uartlite_v2_0_15.baudrate;
-- uartlite_rx refered from axi_uartlite_v2_0_15
use axi_uartlite_v2_0_15.uartlite_rx;
-- uartlite_tx refered from axi_uartlite_v2_0_15
use axi_uartlite_v2_0_15.uartlite_tx;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_S_AXI_ACLK_FREQ_HZ -- System clock frequency driving UART lite
-- peripheral in Hz
-- C_BAUDRATE -- Baud rate of UART Lite in bits per second
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- Slave attachment interface
-- bus2ip_data -- bus2ip data signal
-- bus2ip_rdce -- bus2ip read CE
-- bus2ip_wrce -- bus2ip write CE
-- ip2bus_rdack -- ip2bus read acknowledgement
-- ip2bus_wrack -- ip2bus write acknowledgement
-- ip2bus_error -- ip2bus error
-- SIn_DBus -- ip2bus data
-- UART Lite interface
-- RX -- Receive Data
-- TX -- Transmit Data
-- Interrupt -- UART Interrupt
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_core is
generic
(
C_FAMILY : string := "virtex7";
C_S_AXI_ACLK_FREQ_HZ: integer := 100_000_000;
C_BAUDRATE : integer := 9600;
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
-- IPIF signals
bus2ip_data : in std_logic_vector(0 to 7);
bus2ip_rdce : in std_logic_vector(0 to 3);
bus2ip_wrce : in std_logic_vector(0 to 3);
bus2ip_cs : in std_logic;
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
ip2bus_error : out std_logic;
SIn_DBus : out std_logic_vector(0 to 7);
-- UART signals
RX : in std_logic;
TX : out std_logic;
Interrupt : out std_logic
);
end entity uartlite_core;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
---------------------------------------------------------------------------
-- function declarations
---------------------------------------------------------------------------
function CALC_RATIO ( C_S_AXI_ACLK_FREQ_HZ : integer;
C_BAUDRATE : integer ) return Integer is
constant C_BAUDRATE_16_BY_2: integer := (16 * C_BAUDRATE) / 2;
constant REMAINDER : integer :=
C_S_AXI_ACLK_FREQ_HZ rem (16 * C_BAUDRATE);
constant RATIO : integer :=
C_S_AXI_ACLK_FREQ_HZ / (16 * C_BAUDRATE);
begin
if (C_BAUDRATE_16_BY_2 < REMAINDER) then
return (RATIO + 1);
else
return RATIO;
end if;
end function CALC_RATIO;
---------------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------------
constant RATIO : integer := CALC_RATIO( C_S_AXI_ACLK_FREQ_HZ, C_BAUDRATE);
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
-- Read Only
signal status_reg : std_logic_vector(0 to 7) := (others => '0');
-- bit 7 rx_Data_Present
-- bit 6 rx_Buffer_Full
-- bit 5 tx_Buffer_Empty
-- bit 4 tx_Buffer_Full
-- bit 3 enable_interrupts
-- bit 2 Overrun Error
-- bit 1 Frame Error
-- bit 0 Parity Error (If C_USE_PARITY is true, otherwise '0')
-- Write Only
-- Below mentioned bits belong to Control Register and are declared as
-- signals below
-- bit 0-2 Dont'Care
-- bit 3 enable_interrupts
-- bit 4-5 Dont'Care
-- bit 6 Reset_RX_FIFO
-- bit 7 Reset_TX_FIFO
signal en_16x_Baud : std_logic;
signal enable_interrupts : std_logic;
signal reset_RX_FIFO : std_logic;
signal rx_Data : std_logic_vector(0 to C_DATA_BITS-1);
signal rx_Data_Present : std_logic;
signal rx_Buffer_Full : std_logic;
signal rx_Frame_Error : std_logic;
signal rx_Overrun_Error : std_logic;
signal rx_Parity_Error : std_logic;
signal clr_Status : std_logic;
signal reset_TX_FIFO : std_logic;
signal tx_Buffer_Full : std_logic;
signal tx_Buffer_Empty : std_logic;
signal tx_Buffer_Empty_Pre : std_logic;
signal rx_Data_Present_Pre : std_logic;
begin -- architecture IMP
---------------------------------------------------------------------------
-- Generating the acknowledgement and error signals
---------------------------------------------------------------------------
ip2bus_rdack <= bus2ip_rdce(0) or bus2ip_rdce(2) or bus2ip_rdce(1)
or bus2ip_rdce(3);
ip2bus_wrack <= bus2ip_wrce(1) or bus2ip_wrce(3) or bus2ip_wrce(0)
or bus2ip_wrce(2);
ip2bus_error <= ((bus2ip_rdce(0) and not rx_Data_Present) or
(bus2ip_wrce(1) and tx_Buffer_Full) );
-------------------------------------------------------------------------
-- BAUD_RATE_I : Instansiating the baudrate module
-------------------------------------------------------------------------
BAUD_RATE_I : entity axi_uartlite_v2_0_15.baudrate
generic map
(
C_RATIO => RATIO
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud
);
-------------------------------------------------------------------------
-- Status register handling
-------------------------------------------------------------------------
status_reg(7) <= rx_Data_Present;
status_reg(6) <= rx_Buffer_Full;
status_reg(5) <= tx_Buffer_Empty;
status_reg(4) <= tx_Buffer_Full;
status_reg(3) <= enable_interrupts;
-------------------------------------------------------------------------
-- CLEAR_STATUS_REG : Process to clear status register
-------------------------------------------------------------------------
CLEAR_STATUS_REG : process (Clk) is
begin -- process Ctrl_Reg_DFF
if Clk'event and Clk = '1' then
if Reset = '1' then
clr_Status <= '0';
else
clr_Status <= bus2ip_rdce(2);
end if;
end if;
end process CLEAR_STATUS_REG;
-------------------------------------------------------------------------
-- Process to register rx_Overrun_Error
-------------------------------------------------------------------------
RX_OVERRUN_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if ((Reset = '1') or (clr_Status = '1')) then
status_reg(2) <= '0';
elsif (rx_Overrun_Error = '1') then
status_reg(2) <= '1';
end if;
end if;
end process RX_OVERRUN_ERROR_DFF;
-------------------------------------------------------------------------
-- Process to register rx_Frame_Error
-------------------------------------------------------------------------
RX_FRAME_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
status_reg(1) <= '0';
else
if (clr_Status = '1') then
status_reg(1) <= '0';
elsif (rx_Frame_Error = '1') then
status_reg(1) <= '1';
end if;
end if;
end if;
end process RX_FRAME_ERROR_DFF;
-------------------------------------------------------------------------
-- If C_USE_PARITY = 1, register rx_Parity_Error
-------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
RX_PARITY_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
status_reg(0) <= '0';
else
if (clr_Status = '1') then
status_reg(0) <= '0';
elsif (rx_Parity_Error = '1') then
status_reg(0) <= '1';
end if;
end if;
end if;
end process RX_PARITY_ERROR_DFF;
end generate USING_PARITY;
-------------------------------------------------------------------------
-- NO_PARITY : If C_USE_PARITY = 0, rx_Parity_Error bit is not present
-------------------------------------------------------------------------
NO_PARITY : if (C_USE_PARITY = 0) generate
status_reg(0) <= '0';
end generate NO_PARITY;
-------------------------------------------------------------------------
-- CTRL_REG_DFF : Control Register Handling
-------------------------------------------------------------------------
CTRL_REG_DFF : process (Clk) is
begin -- process Ctrl_Reg_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
reset_TX_FIFO <= '1';
reset_RX_FIFO <= '1';
enable_interrupts <= '0';
elsif (bus2ip_wrce(3) = '1') then
reset_RX_FIFO <= bus2ip_data(6);
reset_TX_FIFO <= bus2ip_data(7);
enable_interrupts <= bus2ip_data(3);
else
reset_TX_FIFO <= '0';
reset_RX_FIFO <= '0';
end if;
end if;
end process CTRL_REG_DFF;
-------------------------------------------------------------------------
-- Tx Fifo Interrupt handling
-------------------------------------------------------------------------
TX_BUFFER_EMPTY_DFF_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Buffer_Empty_Pre <= '0';
else
if (bus2ip_wrce(1) = '1') then
tx_Buffer_Empty_Pre <= '0';
else
tx_Buffer_Empty_Pre <= tx_Buffer_Empty;
end if;
end if;
end if;
end process TX_BUFFER_EMPTY_DFF_I;
-------------------------------------------------------------------------
-- Rx Fifo Interrupt handling
-------------------------------------------------------------------------
RX_BUFFER_DATA_DFF_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
rx_Data_Present_Pre <= '0';
else
if (bus2ip_rdce(0) = '1') then
rx_Data_Present_Pre <= '0';
else
rx_Data_Present_Pre <= rx_Data_Present;
end if;
end if;
end if;
end process RX_BUFFER_DATA_DFF_I;
-------------------------------------------------------------------------
-- Interrupt register handling
-------------------------------------------------------------------------
INTERRUPT_DFF: process (Clk) is
begin
if Clk'event and Clk = '1' then
if Reset = '1' then -- synchronous reset (active high)
Interrupt <= '0';
else
Interrupt <= enable_interrupts and
((rx_Data_Present and not rx_Data_Present_Pre) or
(tx_Buffer_Empty and not tx_Buffer_Empty_Pre));
end if;
end if;
end process INTERRUPT_DFF;
-------------------------------------------------------------------------
-- READ_MUX : Read bus interface handling
-------------------------------------------------------------------------
READ_MUX : process (status_reg, bus2ip_rdce(2), bus2ip_rdce(0), rx_Data) is
begin -- process Read_Mux
if (bus2ip_rdce(2) = '1') then
SIn_DBus <= status_reg;
elsif (bus2ip_rdce(0) = '1') then
SIn_DBus((8-C_DATA_BITS) to 7) <= rx_Data;
SIn_DBus(0 to (7-C_DATA_BITS)) <= (others => '0');
else
SIn_DBus <= (others => '0');
end if;
end process READ_MUX;
-------------------------------------------------------------------------
-- UARTLITE_RX_I : Instansiating the receive module
-------------------------------------------------------------------------
UARTLITE_RX_I : entity axi_uartlite_v2_0_15.uartlite_rx
generic map
(
C_FAMILY => C_FAMILY,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud,
RX => RX,
Read_RX_FIFO => bus2ip_rdce(0),
Reset_RX_FIFO => reset_RX_FIFO,
RX_Data => rx_Data,
RX_Data_Present => rx_Data_Present,
RX_Buffer_Full => rx_Buffer_Full,
RX_Frame_Error => rx_Frame_Error,
RX_Overrun_Error => rx_Overrun_Error,
RX_Parity_Error => rx_Parity_Error
);
-------------------------------------------------------------------------
-- UARTLITE_TX_I : Instansiating the transmit module
-------------------------------------------------------------------------
UARTLITE_TX_I : entity axi_uartlite_v2_0_15.uartlite_tx
generic map
(
C_FAMILY => C_FAMILY,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud,
TX => TX,
Write_TX_FIFO => bus2ip_wrce(1),
Reset_TX_FIFO => reset_TX_FIFO,
TX_Data => bus2ip_data(8-C_DATA_BITS to 7),
TX_Buffer_Full => tx_Buffer_Full,
TX_Buffer_Empty => tx_Buffer_Empty
);
end architecture RTL;
-------------------------------------------------------------------------------
-- axi_uartlite - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_uartlite.vhd
-- Version: v1.02.a
-- Description: AXI UART Lite Interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_lite_ipif_v3_0_4;
-- SLV64_ARRAY_TYPE refered from ipif_pkg
use axi_lite_ipif_v3_0_4.ipif_pkg.SLV64_ARRAY_TYPE;
-- INTEGER_ARRAY_TYPE refered from ipif_pkg
use axi_lite_ipif_v3_0_4.ipif_pkg.INTEGER_ARRAY_TYPE;
-- calc_num_ce comoponent refered from ipif_pkg
use axi_lite_ipif_v3_0_4.ipif_pkg.calc_num_ce;
-- axi_lite_ipif refered from axi_lite_ipif_v2_0
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
library axi_uartlite_v2_0_15;
-- uartlite_core refered from axi_uartlite_v2_0_15
use axi_uartlite_v2_0_15.uartlite_core;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-- C_S_AXI_ACLK_FREQ_HZ -- System clock frequency driving UART lite
-- peripheral in Hz
-- AXI generics
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address Bus (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data Bus (in bits)
--
-- UART Lite generics
-- C_BAUDRATE -- Baud rate of UART Lite in bits per second
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
--System signals
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- Interrupt -- UART Interrupt
--AXI signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
--UARTLite Interface Signals
-- rx -- Receive Data
-- tx -- Transmit Data
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity axi_uartlite is
generic
(
-- -- System Parameter
C_FAMILY : string := "virtex7";
C_S_AXI_ACLK_FREQ_HZ : integer := 100_000_000;
-- -- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer := 4;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
-- -- UARTLite Parameters
C_BAUDRATE : integer := 9600;
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
-- System signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
interrupt : out std_logic;
-- AXI signals
s_axi_awaddr : in std_logic_vector
(3 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector
(31 downto 0);
s_axi_wstrb : in std_logic_vector
(3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector
(3 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector
(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- UARTLite Interface Signals
rx : in std_logic;
tx : out std_logic
);
-------------------------------------------------------------------------------
-- Attributes
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Fan-Out attributes for XST
-------------------------------------------------------------------------------
ATTRIBUTE MAX_FANOUT : string;
ATTRIBUTE MAX_FANOUT of s_axi_aclk : signal is "10000";
ATTRIBUTE MAX_FANOUT of s_axi_aresetn : signal is "10000";
end entity axi_uartlite;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of axi_uartlite is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
--------------------------------------------------------------------------
-- Constant declarations
--------------------------------------------------------------------------
constant ZEROES : std_logic_vector(31 downto 0)
:= X"00000000";
constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
-- UARTLite registers Base Address
ZEROES & X"00000000",
ZEROES & (X"00000000" or X"0000000F")
);
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 4
);
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0)
:= X"0000000F";
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 0;
--------------------------------------------------------------------------
-- Signal declarations
--------------------------------------------------------------------------
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
signal bus2ip_resetn : std_logic;
signal ip2bus_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0)
:= (others => '0');
signal ip2bus_error : std_logic := '0';
signal ip2bus_wrack : std_logic := '0';
signal ip2bus_rdack : std_logic := '0';
signal bus2ip_data : std_logic_vector
(C_S_AXI_DATA_WIDTH - 1 downto 0);
signal bus2ip_cs : std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1 downto 0);
signal bus2ip_rdce : std_logic_vector
(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_wrce : std_logic_vector
(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
begin -- architecture IMP
--------------------------------------------------------------------------
-- RESET signal assignment - IPIC RESET is active low
--------------------------------------------------------------------------
bus2ip_reset <= not bus2ip_resetn;
--------------------------------------------------------------------------
-- ip2bus_data assignment - as core is using maximum upto 8 bits
--------------------------------------------------------------------------
ip2bus_data((C_S_AXI_DATA_WIDTH-1) downto 8) <= (others => '0');
--------------------------------------------------------------------------
-- Instansiating the UART core
--------------------------------------------------------------------------
UARTLITE_CORE_I : entity axi_uartlite_v2_0_15.uartlite_core
generic map
(
C_FAMILY => C_FAMILY,
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ,
C_BAUDRATE => C_BAUDRATE,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => bus2ip_clk,
Reset => bus2ip_reset,
bus2ip_data => bus2ip_data(7 downto 0),
bus2ip_rdce => bus2ip_rdce(3 downto 0),
bus2ip_wrce => bus2ip_wrce(3 downto 0),
bus2ip_cs => bus2ip_cs(0),
ip2bus_rdack => ip2bus_rdack,
ip2bus_wrack => ip2bus_wrack,
ip2bus_error => ip2bus_error,
SIn_DBus => ip2bus_data(7 downto 0),
RX => rx,
TX => tx,
Interrupt => Interrupt
);
--------------------------------------------------------------------------
-- Instantiate AXI lite IPIF
--------------------------------------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif
generic map
(
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => 4,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map
(
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error,
Bus2IP_Addr => open,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => open,
Bus2IP_BE => open,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
end architecture RTL;
|
apache-2.0
|
a84adf79a3c720a41c1fb87903217a92
| 0.414031 | 4.874121 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ipshared/ec0d/hdl/dist_mem_gen_v8_0_vhsyn_rfs.vhd
| 1 | 187,968 |
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|
apache-2.0
|
6f6bb393986d4de3fcd764b7effd5c05
| 0.953912 | 1.836504 | false | false | false | false |
aggroskater/ee4321-vhdl-digital-design
|
Project-6-Consecutive-Ones/ones.vhd
| 1 | 820 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity maxOnesCounter is
port(
x : in std_logic;
clock : in std_logic;
maxOnes : out std_logic_vector(7 downto 0) := (others => '0')
);
end maxOnesCounter;
architecture behavioural of maxOnesCounter is
begin
clock_process: process(clock,x)
variable count:unsigned(7 downto 0) := "00000000";
variable max:unsigned(7 downto 0) := "00000000";
begin
if (clock'event and clock = '1') then
if x = '1' then
count := count +1;
if count > max then
max := count;
maxOnes <= std_logic_vector(max);
end if; --end count > max check
else
count := "00000000";
end if; --end main if elss
end if; --end posedge
end process;
end architecture behavioural;
|
agpl-3.0
|
959c2756cfc57848d3781ba72fc1ee1d
| 0.617073 | 3.612335 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 3/MUX_PCSOURCE_tb.vhd
| 1 | 1,747 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY MUX_PCSOURCE_tb IS
END MUX_PCSOURCE_tb;
ARCHITECTURE behavior OF MUX_PCSOURCE_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MUX_PCSOURCE
PORT(
PCdisp30 : IN std_logic_vector(31 downto 0);
PCSEUdisp22 : IN std_logic_vector(31 downto 0);
ALURESULT : IN std_logic_vector(31 downto 0);
PC : IN std_logic_vector(31 downto 0);
PCSOURCE : IN std_logic_vector(1 downto 0);
nPC : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal PCdisp30 : std_logic_vector(31 downto 0) := (others => '0');
signal PCSEUdisp22 : std_logic_vector(31 downto 0) := (others => '0');
signal ALURESULT : std_logic_vector(31 downto 0) := (others => '0');
signal PC : std_logic_vector(31 downto 0) := (others => '0');
signal PCSOURCE : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal nPC : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MUX_PCSOURCE PORT MAP (
PCdisp30 => PCdisp30,
PCSEUdisp22 => PCSEUdisp22,
ALURESULT => ALURESULT,
PC => PC,
PCSOURCE => PCSOURCE,
nPC => nPC
);
-- Stimulus process
stim_proc: process
begin
PCdisp30<="11111111111111111111111111111001";
PCSEUdisp22<="00000000000000000000000000000110";
ALURESULT<="00000000000000000000000000001010";
PC<="00000000000000000000000000001000";
wait for 20 ns;
PCSOURCE<="01";
wait for 20 ns;
PCSOURCE<="10";
wait for 20 ns;
PCSOURCE<="11";
wait;
end process;
END;
|
mit
|
a789d5ad0fce2a5df55baa860bf5ad4d
| 0.600458 | 3.934685 | false | false | false | false |
daniw/add
|
edk/IVK_HW/t01_hello/hdl/mdm_0_wrapper.vhd
| 1 | 17,526 |
-------------------------------------------------------------------------------
-- mdm_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library mdm_v2_00_b;
use mdm_v2_00_b.all;
entity mdm_0_wrapper is
port (
Interrupt : out std_logic;
Debug_SYS_Rst : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 3);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 31);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 31);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MWrErr : out std_logic_vector(0 to 1);
Sl_MRdErr : out std_logic_vector(0 to 1);
Sl_MIRQ : out std_logic_vector(0 to 1);
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
bscan_tdi : out std_logic;
bscan_reset : out std_logic;
bscan_shift : out std_logic;
bscan_update : out std_logic;
bscan_capture : out std_logic;
bscan_sel1 : out std_logic;
bscan_drck1 : out std_logic;
bscan_tdo1 : in std_logic;
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of mdm_0_wrapper : entity is "mdm_v2_00_b";
end mdm_0_wrapper;
architecture STRUCTURE of mdm_0_wrapper is
component mdm is
generic (
C_FAMILY : STRING;
C_JTAG_CHAIN : INTEGER;
C_INTERCONNECT : INTEGER;
C_BASEADDR : STD_LOGIC_VECTOR;
C_HIGHADDR : STD_LOGIC_VECTOR;
C_SPLB_AWIDTH : INTEGER;
C_SPLB_DWIDTH : INTEGER;
C_SPLB_P2P : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_NATIVE_DWIDTH : INTEGER;
C_SPLB_SUPPORT_BURSTS : INTEGER;
C_MB_DBG_PORTS : INTEGER;
C_USE_UART : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER
);
port (
Interrupt : out std_logic;
Debug_SYS_Rst : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8-1) downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
bscan_tdi : out std_logic;
bscan_reset : out std_logic;
bscan_shift : out std_logic;
bscan_update : out std_logic;
bscan_capture : out std_logic;
bscan_sel1 : out std_logic;
bscan_drck1 : out std_logic;
bscan_tdo1 : in std_logic;
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end component;
begin
mdm_0 : mdm
generic map (
C_FAMILY => "spartan6",
C_JTAG_CHAIN => 2,
C_INTERCONNECT => 1,
C_BASEADDR => X"84400000",
C_HIGHADDR => X"8440ffff",
C_SPLB_AWIDTH => 32,
C_SPLB_DWIDTH => 32,
C_SPLB_P2P => 0,
C_SPLB_MID_WIDTH => 1,
C_SPLB_NUM_MASTERS => 2,
C_SPLB_NATIVE_DWIDTH => 32,
C_SPLB_SUPPORT_BURSTS => 0,
C_MB_DBG_PORTS => 1,
C_USE_UART => 1,
C_S_AXI_ADDR_WIDTH => 32,
C_S_AXI_DATA_WIDTH => 32
)
port map (
Interrupt => Interrupt,
Debug_SYS_Rst => Debug_SYS_Rst,
Ext_BRK => Ext_BRK,
Ext_NM_BRK => Ext_NM_BRK,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Dbg_Clk_0 => Dbg_Clk_0,
Dbg_TDI_0 => Dbg_TDI_0,
Dbg_TDO_0 => Dbg_TDO_0,
Dbg_Reg_En_0 => Dbg_Reg_En_0,
Dbg_Capture_0 => Dbg_Capture_0,
Dbg_Shift_0 => Dbg_Shift_0,
Dbg_Update_0 => Dbg_Update_0,
Dbg_Rst_0 => Dbg_Rst_0,
Dbg_Clk_1 => Dbg_Clk_1,
Dbg_TDI_1 => Dbg_TDI_1,
Dbg_TDO_1 => Dbg_TDO_1,
Dbg_Reg_En_1 => Dbg_Reg_En_1,
Dbg_Capture_1 => Dbg_Capture_1,
Dbg_Shift_1 => Dbg_Shift_1,
Dbg_Update_1 => Dbg_Update_1,
Dbg_Rst_1 => Dbg_Rst_1,
Dbg_Clk_2 => Dbg_Clk_2,
Dbg_TDI_2 => Dbg_TDI_2,
Dbg_TDO_2 => Dbg_TDO_2,
Dbg_Reg_En_2 => Dbg_Reg_En_2,
Dbg_Capture_2 => Dbg_Capture_2,
Dbg_Shift_2 => Dbg_Shift_2,
Dbg_Update_2 => Dbg_Update_2,
Dbg_Rst_2 => Dbg_Rst_2,
Dbg_Clk_3 => Dbg_Clk_3,
Dbg_TDI_3 => Dbg_TDI_3,
Dbg_TDO_3 => Dbg_TDO_3,
Dbg_Reg_En_3 => Dbg_Reg_En_3,
Dbg_Capture_3 => Dbg_Capture_3,
Dbg_Shift_3 => Dbg_Shift_3,
Dbg_Update_3 => Dbg_Update_3,
Dbg_Rst_3 => Dbg_Rst_3,
Dbg_Clk_4 => Dbg_Clk_4,
Dbg_TDI_4 => Dbg_TDI_4,
Dbg_TDO_4 => Dbg_TDO_4,
Dbg_Reg_En_4 => Dbg_Reg_En_4,
Dbg_Capture_4 => Dbg_Capture_4,
Dbg_Shift_4 => Dbg_Shift_4,
Dbg_Update_4 => Dbg_Update_4,
Dbg_Rst_4 => Dbg_Rst_4,
Dbg_Clk_5 => Dbg_Clk_5,
Dbg_TDI_5 => Dbg_TDI_5,
Dbg_TDO_5 => Dbg_TDO_5,
Dbg_Reg_En_5 => Dbg_Reg_En_5,
Dbg_Capture_5 => Dbg_Capture_5,
Dbg_Shift_5 => Dbg_Shift_5,
Dbg_Update_5 => Dbg_Update_5,
Dbg_Rst_5 => Dbg_Rst_5,
Dbg_Clk_6 => Dbg_Clk_6,
Dbg_TDI_6 => Dbg_TDI_6,
Dbg_TDO_6 => Dbg_TDO_6,
Dbg_Reg_En_6 => Dbg_Reg_En_6,
Dbg_Capture_6 => Dbg_Capture_6,
Dbg_Shift_6 => Dbg_Shift_6,
Dbg_Update_6 => Dbg_Update_6,
Dbg_Rst_6 => Dbg_Rst_6,
Dbg_Clk_7 => Dbg_Clk_7,
Dbg_TDI_7 => Dbg_TDI_7,
Dbg_TDO_7 => Dbg_TDO_7,
Dbg_Reg_En_7 => Dbg_Reg_En_7,
Dbg_Capture_7 => Dbg_Capture_7,
Dbg_Shift_7 => Dbg_Shift_7,
Dbg_Update_7 => Dbg_Update_7,
Dbg_Rst_7 => Dbg_Rst_7,
bscan_tdi => bscan_tdi,
bscan_reset => bscan_reset,
bscan_shift => bscan_shift,
bscan_update => bscan_update,
bscan_capture => bscan_capture,
bscan_sel1 => bscan_sel1,
bscan_drck1 => bscan_drck1,
bscan_tdo1 => bscan_tdo1,
Ext_JTAG_DRCK => Ext_JTAG_DRCK,
Ext_JTAG_RESET => Ext_JTAG_RESET,
Ext_JTAG_SEL => Ext_JTAG_SEL,
Ext_JTAG_CAPTURE => Ext_JTAG_CAPTURE,
Ext_JTAG_SHIFT => Ext_JTAG_SHIFT,
Ext_JTAG_UPDATE => Ext_JTAG_UPDATE,
Ext_JTAG_TDI => Ext_JTAG_TDI,
Ext_JTAG_TDO => Ext_JTAG_TDO
);
end architecture STRUCTURE;
|
gpl-2.0
|
4aa993fa35deaab1a221f82126fccd06
| 0.5768 | 2.893989 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_quad_spi_shield_0/system_axi_quad_spi_shield_0_sim_netlist.vhdl
| 1 | 583,546 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:47:55 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_quad_spi_shield_0/system_axi_quad_spi_shield_0_sim_netlist.vhdl
-- Design : system_axi_quad_spi_shield_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized0\ is
port (
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : out STD_LOGIC;
\bus2ip_addr_i_reg[6]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized0\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized0\;
architecture STRUCTURE of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized0\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(4),
I1 => Q,
I2 => \bus2ip_addr_i_reg[6]\(2),
I3 => \bus2ip_addr_i_reg[6]\(1),
I4 => \bus2ip_addr_i_reg[6]\(3),
I5 => \bus2ip_addr_i_reg[6]\(0),
O => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized1\ is
port (
p_14_out : out STD_LOGIC;
\bus2ip_addr_i_reg[6]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized1\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized1\;
architecture STRUCTURE of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized1\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000200"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(0),
I1 => \bus2ip_addr_i_reg[6]\(2),
I2 => \bus2ip_addr_i_reg[6]\(4),
I3 => Q,
I4 => \bus2ip_addr_i_reg[6]\(3),
I5 => \bus2ip_addr_i_reg[6]\(1),
O => p_14_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized10\ is
port (
p_5_out : out STD_LOGIC;
\bus2ip_addr_i_reg[6]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized10\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized10\;
architecture STRUCTURE of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized10\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0000040000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(2),
I1 => \bus2ip_addr_i_reg[6]\(1),
I2 => \bus2ip_addr_i_reg[6]\(4),
I3 => Q,
I4 => \bus2ip_addr_i_reg[6]\(0),
I5 => \bus2ip_addr_i_reg[6]\(3),
O => p_5_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized11\ is
port (
p_4_out : out STD_LOGIC;
\bus2ip_addr_i_reg[6]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized11\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized11\;
architecture STRUCTURE of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized11\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0000400000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(2),
I1 => \bus2ip_addr_i_reg[6]\(1),
I2 => \bus2ip_addr_i_reg[6]\(0),
I3 => \bus2ip_addr_i_reg[6]\(3),
I4 => \bus2ip_addr_i_reg[6]\(4),
I5 => Q,
O => p_4_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized12\ is
port (
p_3_out : out STD_LOGIC;
\bus2ip_addr_i_reg[6]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized12\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized12\;
architecture STRUCTURE of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized12\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0000040000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(1),
I1 => \bus2ip_addr_i_reg[6]\(2),
I2 => \bus2ip_addr_i_reg[6]\(4),
I3 => Q,
I4 => \bus2ip_addr_i_reg[6]\(0),
I5 => \bus2ip_addr_i_reg[6]\(3),
O => p_3_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized13\ is
port (
p_2_out : out STD_LOGIC;
\bus2ip_addr_i_reg[6]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized13\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized13\;
architecture STRUCTURE of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized13\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"1000000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(1),
I1 => \bus2ip_addr_i_reg[6]\(4),
I2 => Q,
I3 => \bus2ip_addr_i_reg[6]\(0),
I4 => \bus2ip_addr_i_reg[6]\(3),
I5 => \bus2ip_addr_i_reg[6]\(2),
O => p_2_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized14\ is
port (
p_1_out : out STD_LOGIC;
\bus2ip_addr_i_reg[6]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized14\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized14\;
architecture STRUCTURE of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized14\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0400000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(0),
I1 => \bus2ip_addr_i_reg[6]\(1),
I2 => \bus2ip_addr_i_reg[6]\(4),
I3 => Q,
I4 => \bus2ip_addr_i_reg[6]\(3),
I5 => \bus2ip_addr_i_reg[6]\(2),
O => p_1_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized19\ is
port (
\GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]\ : out STD_LOGIC;
\bus2ip_addr_i_reg[6]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized19\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized19\;
architecture STRUCTURE of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized19\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(0),
I1 => \bus2ip_addr_i_reg[6]\(2),
I2 => \bus2ip_addr_i_reg[6]\(1),
I3 => \bus2ip_addr_i_reg[6]\(3),
I4 => Q,
I5 => \bus2ip_addr_i_reg[6]\(4),
O => \GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized2\ is
port (
p_13_out : out STD_LOGIC;
\bus2ip_addr_i_reg[6]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized2\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized2\;
architecture STRUCTURE of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized2\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000200"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(1),
I1 => \bus2ip_addr_i_reg[6]\(2),
I2 => \bus2ip_addr_i_reg[6]\(4),
I3 => Q,
I4 => \bus2ip_addr_i_reg[6]\(3),
I5 => \bus2ip_addr_i_reg[6]\(0),
O => p_13_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized23\ is
port (
\GEN_BKEND_CE_REGISTERS[22].ce_out_i_reg[22]\ : out STD_LOGIC;
\bus2ip_addr_i_reg[6]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized23\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized23\;
architecture STRUCTURE of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized23\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0200000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(2),
I1 => \bus2ip_addr_i_reg[6]\(0),
I2 => \bus2ip_addr_i_reg[6]\(3),
I3 => Q,
I4 => \bus2ip_addr_i_reg[6]\(4),
I5 => \bus2ip_addr_i_reg[6]\(1),
O => \GEN_BKEND_CE_REGISTERS[22].ce_out_i_reg[22]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized28\ is
port (
\GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26]\ : out STD_LOGIC;
\bus2ip_addr_i_reg[6]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized28\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized28\;
architecture STRUCTURE of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized28\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"1000000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(0),
I1 => \bus2ip_addr_i_reg[6]\(2),
I2 => \bus2ip_addr_i_reg[6]\(1),
I3 => \bus2ip_addr_i_reg[6]\(4),
I4 => \bus2ip_addr_i_reg[6]\(3),
I5 => Q,
O => \GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized3\ is
port (
p_12_out : out STD_LOGIC;
\bus2ip_addr_i_reg[6]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized3\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized3\;
architecture STRUCTURE of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized3\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0000004000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(3),
I1 => \bus2ip_addr_i_reg[6]\(1),
I2 => \bus2ip_addr_i_reg[6]\(0),
I3 => \bus2ip_addr_i_reg[6]\(2),
I4 => \bus2ip_addr_i_reg[6]\(4),
I5 => Q,
O => p_12_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized32\ is
port (
\GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30]\ : out STD_LOGIC;
\bus2ip_addr_i_reg[6]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized32\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized32\;
architecture STRUCTURE of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized32\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(2),
I1 => \bus2ip_addr_i_reg[6]\(0),
I2 => \bus2ip_addr_i_reg[6]\(4),
I3 => \bus2ip_addr_i_reg[6]\(3),
I4 => Q,
I5 => \bus2ip_addr_i_reg[6]\(1),
O => \GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized4\ is
port (
p_11_out : out STD_LOGIC;
\bus2ip_addr_i_reg[6]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized4\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized4\;
architecture STRUCTURE of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized4\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000200"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(2),
I1 => \bus2ip_addr_i_reg[6]\(0),
I2 => \bus2ip_addr_i_reg[6]\(4),
I3 => Q,
I4 => \bus2ip_addr_i_reg[6]\(3),
I5 => \bus2ip_addr_i_reg[6]\(1),
O => p_11_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized5\ is
port (
p_10_out : out STD_LOGIC;
\bus2ip_addr_i_reg[6]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized5\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized5\;
architecture STRUCTURE of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized5\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0000004000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(3),
I1 => \bus2ip_addr_i_reg[6]\(2),
I2 => \bus2ip_addr_i_reg[6]\(0),
I3 => \bus2ip_addr_i_reg[6]\(1),
I4 => \bus2ip_addr_i_reg[6]\(4),
I5 => Q,
O => p_10_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized6\ is
port (
p_9_out : out STD_LOGIC;
\bus2ip_addr_i_reg[6]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized6\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized6\;
architecture STRUCTURE of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized6\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0000004000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(3),
I1 => \bus2ip_addr_i_reg[6]\(1),
I2 => \bus2ip_addr_i_reg[6]\(2),
I3 => \bus2ip_addr_i_reg[6]\(0),
I4 => \bus2ip_addr_i_reg[6]\(4),
I5 => Q,
O => p_9_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized7\ is
port (
p_8_out : out STD_LOGIC;
\bus2ip_addr_i_reg[6]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized7\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized7\;
architecture STRUCTURE of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized7\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(3),
I1 => \bus2ip_addr_i_reg[6]\(1),
I2 => \bus2ip_addr_i_reg[6]\(0),
I3 => \bus2ip_addr_i_reg[6]\(4),
I4 => Q,
I5 => \bus2ip_addr_i_reg[6]\(2),
O => p_8_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized8\ is
port (
p_7_out : out STD_LOGIC;
\bus2ip_addr_i_reg[6]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized8\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized8\;
architecture STRUCTURE of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized8\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000400"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(4),
I1 => Q,
I2 => \bus2ip_addr_i_reg[6]\(2),
I3 => \bus2ip_addr_i_reg[6]\(3),
I4 => \bus2ip_addr_i_reg[6]\(1),
I5 => \bus2ip_addr_i_reg[6]\(0),
O => p_7_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized9\ is
port (
p_6_out : out STD_LOGIC;
\bus2ip_addr_i_reg[6]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized9\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized9\;
architecture STRUCTURE of \system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized9\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0000100000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(2),
I1 => \bus2ip_addr_i_reg[6]\(4),
I2 => Q,
I3 => \bus2ip_addr_i_reg[6]\(0),
I4 => \bus2ip_addr_i_reg[6]\(1),
I5 => \bus2ip_addr_i_reg[6]\(3),
O => p_6_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_cdc_sync is
port (
scndry_out : out STD_LOGIC;
prmry_in : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_cdc_sync : entity is "cdc_sync";
end system_axi_quad_spi_shield_0_cdc_sync;
architecture STRUCTURE of system_axi_quad_spi_shield_0_cdc_sync is
signal s_level_out_d1_cdc_to : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => prmry_in,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => scndry_out,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_cdc_sync_0 is
port (
Rx_FIFO_Full_Fifo_d1_synced_i : out STD_LOGIC;
scndry_out : out STD_LOGIC;
\icount_out_reg[3]\ : out STD_LOGIC;
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_sig_reg\ : out STD_LOGIC;
\out\ : in STD_LOGIC;
Rx_FIFO_Full_Fifo_d1_sig : in STD_LOGIC;
Rx_FIFO_Full_Fifo_d1_flag : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\ : in STD_LOGIC;
reset2ip_reset_int : in STD_LOGIC;
prmry_in : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_cdc_sync_0 : entity is "cdc_sync";
end system_axi_quad_spi_shield_0_cdc_sync_0;
architecture STRUCTURE of system_axi_quad_spi_shield_0_cdc_sync_0 is
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \icount_out[3]_i_5\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of rc_FIFO_Full_d1_i_1 : label is "soft_lutpair19";
begin
scndry_out <= \^scndry_out\;
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_sig_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BABABA0A"
)
port map (
I0 => Rx_FIFO_Full_Fifo_d1_sig,
I1 => Rx_FIFO_Full_Fifo_d1_flag,
I2 => \^scndry_out\,
I3 => \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\,
I4 => \out\,
I5 => reset2ip_reset_int,
O => \FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_sig_reg\
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => prmry_in,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => \^scndry_out\,
R => '0'
);
\icount_out[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => Rx_FIFO_Full_Fifo_d1_sig,
I1 => Rx_FIFO_Full_Fifo_d1_flag,
I2 => \^scndry_out\,
O => \icount_out_reg[3]\
);
rc_FIFO_Full_d1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^scndry_out\,
I1 => \out\,
O => Rx_FIFO_Full_Fifo_d1_synced_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_counter_f is
port (
rx_fifo_count : out STD_LOGIC_VECTOR ( 1 downto 0 );
\icount_out_reg[0]_0\ : out STD_LOGIC;
\icount_out_reg[3]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.Rx_FIFO_Full_i_reg\ : out STD_LOGIC;
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_sig_reg\ : in STD_LOGIC;
\RESET_FLOPS[15].RST_FLOPS\ : in STD_LOGIC;
bus2ip_reset_ipif_inverted : in STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\ : in STD_LOGIC;
reset2ip_reset_int : in STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_0\ : in STD_LOGIC;
spiXfer_done_d2 : in STD_LOGIC;
spiXfer_done_d3 : in STD_LOGIC;
Rx_FIFO_Full_i : in STD_LOGIC;
Rx_FIFO_Full_int : in STD_LOGIC;
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.Rx_FIFO_Full_int_reg\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_counter_f : entity is "counter_f";
end system_axi_quad_spi_shield_0_counter_f;
architecture STRUCTURE of system_axi_quad_spi_shield_0_counter_f is
signal RX_one_less_than_full : STD_LOGIC;
signal \icount_out[0]_i_1_n_0\ : STD_LOGIC;
signal \icount_out[1]_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out[2]_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out[3]_i_2__0_n_0\ : STD_LOGIC;
signal \^icount_out_reg[0]_0\ : STD_LOGIC;
signal \^icount_out_reg[3]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^rx_fifo_count\ : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\icount_out_reg[0]_0\ <= \^icount_out_reg[0]_0\;
\icount_out_reg[3]_0\(0) <= \^icount_out_reg[3]_0\(0);
rx_fifo_count(1 downto 0) <= \^rx_fifo_count\(1 downto 0);
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.Rx_FIFO_Full_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000000E"
)
port map (
I0 => Rx_FIFO_Full_i,
I1 => RX_one_less_than_full,
I2 => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\,
I3 => bus2ip_reset_ipif_inverted,
I4 => \RESET_FLOPS[15].RST_FLOPS\,
I5 => Rx_FIFO_Full_int,
O => \FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.Rx_FIFO_Full_i_reg\
);
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.Rx_FIFO_Full_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000600000000000"
)
port map (
I0 => spiXfer_done_d2,
I1 => spiXfer_done_d3,
I2 => \^icount_out_reg[3]_0\(0),
I3 => \^rx_fifo_count\(1),
I4 => \^icount_out_reg[0]_0\,
I5 => \^rx_fifo_count\(0),
O => RX_one_less_than_full
);
\icount_out[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => \^icount_out_reg[0]_0\,
I1 => \RESET_FLOPS[15].RST_FLOPS\,
I2 => bus2ip_reset_ipif_inverted,
I3 => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\,
O => \icount_out[0]_i_1_n_0\
);
\icount_out[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFF96"
)
port map (
I0 => \^rx_fifo_count\(0),
I1 => \^icount_out_reg[0]_0\,
I2 => \FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_sig_reg\,
I3 => \RESET_FLOPS[15].RST_FLOPS\,
I4 => bus2ip_reset_ipif_inverted,
I5 => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\,
O => \icount_out[1]_i_1__0_n_0\
);
\icount_out[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEEFFEFEFEFEEFFE"
)
port map (
I0 => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\,
I1 => reset2ip_reset_int,
I2 => \^rx_fifo_count\(1),
I3 => \FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_sig_reg\,
I4 => \^rx_fifo_count\(0),
I5 => \^icount_out_reg[0]_0\,
O => \icount_out[2]_i_1__0_n_0\
);
\icount_out[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFFFFFF77555555D"
)
port map (
I0 => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_0\,
I1 => \FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_sig_reg\,
I2 => \^rx_fifo_count\(0),
I3 => \^icount_out_reg[0]_0\,
I4 => \^rx_fifo_count\(1),
I5 => \^icount_out_reg[3]_0\(0),
O => \icount_out[3]_i_2__0_n_0\
);
\icount_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.Rx_FIFO_Full_int_reg\,
D => \icount_out[0]_i_1_n_0\,
Q => \^icount_out_reg[0]_0\,
R => '0'
);
\icount_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.Rx_FIFO_Full_int_reg\,
D => \icount_out[1]_i_1__0_n_0\,
Q => \^rx_fifo_count\(0),
R => '0'
);
\icount_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.Rx_FIFO_Full_int_reg\,
D => \icount_out[2]_i_1__0_n_0\,
Q => \^rx_fifo_count\(1),
R => '0'
);
\icount_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.Rx_FIFO_Full_int_reg\,
D => \icount_out[3]_i_2__0_n_0\,
Q => \^icount_out_reg[3]_0\(0),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_counter_f_1 is
port (
tx_fifo_count : out STD_LOGIC_VECTOR ( 2 downto 0 );
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d1_reg[3]\ : out STD_LOGIC;
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_reg\ : out STD_LOGIC;
reset_TxFIFO_ptr_int : in STD_LOGIC;
spiXfer_done_d2 : in STD_LOGIC;
spiXfer_done_d3 : in STD_LOGIC;
Bus_RNW_reg_reg : in STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\ : in STD_LOGIC;
bus2ip_reset_ipif_inverted : in STD_LOGIC;
\RESET_FLOPS[15].RST_FLOPS\ : in STD_LOGIC;
reset2ip_reset_int : in STD_LOGIC;
Tx_FIFO_Full_int : in STD_LOGIC;
Tx_FIFO_Full_i : in STD_LOGIC;
Bus_RNW_reg_reg_0 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\RESET_FLOPS[15].RST_FLOPS_0\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_counter_f_1 : entity is "counter_f";
end system_axi_quad_spi_shield_0_counter_f_1;
architecture STRUCTURE of system_axi_quad_spi_shield_0_counter_f_1 is
signal \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_i_2_n_0\ : STD_LOGIC;
signal \^fifo_exists.tx_full_emp_intr_md_0_gen.tx_fifo_count_d1_reg[3]\ : STD_LOGIC;
signal \icount_out[1]_i_1_n_0\ : STD_LOGIC;
signal \icount_out[2]_i_1_n_0\ : STD_LOGIC;
signal \icount_out[3]_i_2_n_0\ : STD_LOGIC;
signal \icount_out[3]_i_3_n_0\ : STD_LOGIC;
signal \^tx_fifo_count\ : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d1_reg[3]\ <= \^fifo_exists.tx_full_emp_intr_md_0_gen.tx_fifo_count_d1_reg[3]\;
tx_fifo_count(2 downto 0) <= \^tx_fifo_count\(2 downto 0);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_i_2_n_0\,
I1 => \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\,
I2 => bus2ip_reset_ipif_inverted,
I3 => \RESET_FLOPS[15].RST_FLOPS\,
I4 => Tx_FIFO_Full_int,
O => \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_reg\
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF20000000"
)
port map (
I0 => \^tx_fifo_count\(1),
I1 => \^tx_fifo_count\(0),
I2 => \^tx_fifo_count\(2),
I3 => \^fifo_exists.tx_full_emp_intr_md_0_gen.tx_fifo_count_d1_reg[3]\,
I4 => Bus_RNW_reg_reg,
I5 => Tx_FIFO_Full_i,
O => \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_i_2_n_0\
);
\icount_out[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BEBEBEBEBEEBEBBE"
)
port map (
I0 => reset_TxFIFO_ptr_int,
I1 => \^tx_fifo_count\(1),
I2 => \^tx_fifo_count\(0),
I3 => spiXfer_done_d2,
I4 => spiXfer_done_d3,
I5 => Bus_RNW_reg_reg,
O => \icount_out[1]_i_1_n_0\
);
\icount_out[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFF69"
)
port map (
I0 => \^tx_fifo_count\(2),
I1 => \^tx_fifo_count\(1),
I2 => \icount_out[3]_i_3_n_0\,
I3 => \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\,
I4 => bus2ip_reset_ipif_inverted,
I5 => \RESET_FLOPS[15].RST_FLOPS\,
O => \icount_out[2]_i_1_n_0\
);
\icount_out[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF7E81"
)
port map (
I0 => \^tx_fifo_count\(1),
I1 => \icount_out[3]_i_3_n_0\,
I2 => \^tx_fifo_count\(2),
I3 => \^fifo_exists.tx_full_emp_intr_md_0_gen.tx_fifo_count_d1_reg[3]\,
I4 => \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\,
I5 => reset2ip_reset_int,
O => \icount_out[3]_i_2_n_0\
);
\icount_out[3]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"BBBBB22B"
)
port map (
I0 => \^tx_fifo_count\(0),
I1 => \^tx_fifo_count\(1),
I2 => spiXfer_done_d2,
I3 => spiXfer_done_d3,
I4 => Bus_RNW_reg_reg,
O => \icount_out[3]_i_3_n_0\
);
\icount_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus_RNW_reg_reg_0,
D => \RESET_FLOPS[15].RST_FLOPS_0\,
Q => \^tx_fifo_count\(0),
R => '0'
);
\icount_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus_RNW_reg_reg_0,
D => \icount_out[1]_i_1_n_0\,
Q => \^tx_fifo_count\(1),
R => '0'
);
\icount_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus_RNW_reg_reg_0,
D => \icount_out[2]_i_1_n_0\,
Q => \^tx_fifo_count\(2),
R => '0'
);
\icount_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus_RNW_reg_reg_0,
D => \icount_out[3]_i_2_n_0\,
Q => \^fifo_exists.tx_full_emp_intr_md_0_gen.tx_fifo_count_d1_reg[3]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_cross_clk_sync_fifo_1 is
port (
\LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_1_CDC_0\ : out STD_LOGIC;
\LOGIC_GENERATION_FDR.SLV_MODF_STRB_S2AX_1_CDC_0\ : out STD_LOGIC;
tx_FIFO_Occpncy_MSB_d1_reg : out STD_LOGIC;
spiXfer_done_d2 : out STD_LOGIC;
spiXfer_done_d3 : out STD_LOGIC;
dtr_underrun_to_axi_clk : out STD_LOGIC;
spicr_0_loop_to_spi_clk : out STD_LOGIC;
spicr_1_spe_to_spi_clk : out STD_LOGIC;
SPICR_2_MST_N_SLV_to_spi_clk : out STD_LOGIC;
spicr_3_cpol_to_spi_clk : out STD_LOGIC;
spicr_4_cpha_to_spi_clk : out STD_LOGIC;
spicr_9_lsb_to_spi_clk : out STD_LOGIC;
register_Data_slvsel_int : out STD_LOGIC;
\ip_irpt_enable_reg_reg[8]\ : out STD_LOGIC;
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\ : out STD_LOGIC;
Allow_Slave_MODF_Strobe_reg : out STD_LOGIC;
transfer_start_reg : out STD_LOGIC;
\icount_out_reg[3]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ : out STD_LOGIC;
Tx_FIFO_Empty_intr : out STD_LOGIC;
tx_occ_msb : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\icount_out_reg[1]\ : out STD_LOGIC;
spiXfer_done_to_axi_1 : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[31]\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\ : out STD_LOGIC;
\SS_O_reg[0]\ : out STD_LOGIC;
modf_reg : out STD_LOGIC;
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_int_reg\ : out STD_LOGIC;
R : out STD_LOGIC;
Slave_MODF_strobe0 : out STD_LOGIC;
MODF_strobe0 : out STD_LOGIC;
\OTHER_RATIO_GENERATE.Shift_Reg_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\OTHER_RATIO_GENERATE.rx_shft_reg_s_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\OTHER_RATIO_GENERATE.sck_o_int_reg\ : out STD_LOGIC;
rx_fifo_reset : out STD_LOGIC;
\LOCAL_TX_EMPTY_FIFO_12_GEN.stop_clock_reg_reg\ : out STD_LOGIC;
D_0 : out STD_LOGIC;
SPI_TRISTATE_CONTROL_V : out STD_LOGIC;
reset2ip_reset_int : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
spisel_d1_reg : in STD_LOGIC;
\out\ : in STD_LOGIC;
Rst_to_spi : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
dtr_underrun_int : in STD_LOGIC;
spicr_0_loop_frm_axi_clk : in STD_LOGIC;
spicr_1_spe_frm_axi_clk : in STD_LOGIC;
spicr_2_mst_n_slv_frm_axi_clk : in STD_LOGIC;
spicr_3_cpol_frm_axi_clk : in STD_LOGIC;
spicr_4_cpha_frm_axi_clk : in STD_LOGIC;
spicr_7_ss_frm_axi_clk : in STD_LOGIC;
spicr_8_tr_inhibit_frm_axi_clk : in STD_LOGIC;
spicr_9_lsb_frm_axi_clk : in STD_LOGIC;
sr_3_MODF_int : in STD_LOGIC;
spicr_bits_7_8_frm_axi_clk : in STD_LOGIC_VECTOR ( 1 downto 0 );
SPISSR_frm_axi_clk : in STD_LOGIC;
\LOGIC_GENERATION_FDR.spisel_pulse_cdc_from_spi_int_2_reg_0\ : in STD_LOGIC;
p_7_out : in STD_LOGIC;
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg_0\ : in STD_LOGIC;
\RESET_FLOPS[15].RST_FLOPS\ : in STD_LOGIC;
bus2ip_reset_ipif_inverted : in STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\ : in STD_LOGIC;
Allow_Slave_MODF_Strobe : in STD_LOGIC;
stop_clock : in STD_LOGIC;
Rx_FIFO_Full_int : in STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_0\ : in STD_LOGIC;
empty_fwft_i_reg : in STD_LOGIC;
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_sig_reg\ : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 5 downto 0 );
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\ : in STD_LOGIC;
p_1_in17_in : in STD_LOGIC;
tx_occ_msb_4 : in STD_LOGIC;
tx_FIFO_Occpncy_MSB_d1 : in STD_LOGIC;
p_1_in20_in : in STD_LOGIC;
p_1_in23_in : in STD_LOGIC;
p_1_in35_in : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ : in STD_LOGIC;
tx_fifo_count_d2 : in STD_LOGIC_VECTOR ( 3 downto 0 );
spiXfer_done_to_axi_d1 : in STD_LOGIC;
Rx_FIFO_Full_Fifo_d1_sig : in STD_LOGIC;
Rx_FIFO_Full_Fifo_d1_flag : in STD_LOGIC;
scndry_out : in STD_LOGIC;
p_3_in : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
tx_fifo_count : in STD_LOGIC_VECTOR ( 2 downto 0 );
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
empty_fwft_i_reg_0 : in STD_LOGIC;
rx_fifo_count : in STD_LOGIC_VECTOR ( 1 downto 0 );
transfer_start_reg_0 : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ : in STD_LOGIC;
Bus_RNW_reg_reg : in STD_LOGIC;
Tx_FIFO_Full_i : in STD_LOGIC;
Tx_FIFO_Full_int : in STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\ : in STD_LOGIC;
modf_strobe_int : in STD_LOGIC;
spiXfer_done_int : in STD_LOGIC;
drr_Overrun_int : in STD_LOGIC;
Allow_MODF_Strobe : in STD_LOGIC;
\LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_2_0\ : in STD_LOGIC;
\goreg_dm.dout_i_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
RESET_SYNC_AX2S_2 : in STD_LOGIC;
\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg\ : in STD_LOGIC;
SR_5_Tx_comeplete_Empty : in STD_LOGIC;
serial_dout_int : in STD_LOGIC;
io1_i_sync : in STD_LOGIC;
io0_i_sync : in STD_LOGIC;
SPISEL_sync : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_cross_clk_sync_fifo_1 : entity is "cross_clk_sync_fifo_1";
end system_axi_quad_spi_shield_0_cross_clk_sync_fifo_1;
architecture STRUCTURE of system_axi_quad_spi_shield_0_cross_clk_sync_fifo_1 is
signal \^logic_generation_fdr.slv_modf_strb_s2ax_1_cdc_0\ : STD_LOGIC;
signal \LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_i_1_n_0\ : STD_LOGIC;
signal \LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_reg_n_0\ : STD_LOGIC;
signal \^logic_generation_fdr.spisel_pulse_s2ax_1_cdc_0\ : STD_LOGIC;
signal \LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_AX2S_1_CDC_n_0\ : STD_LOGIC;
signal \LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg_n_0\ : STD_LOGIC;
signal \LOGIC_GENERATION_FDR.modf_strobe_cdc_from_spi_int_2_reg_n_0\ : STD_LOGIC;
signal \LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg_n_0\ : STD_LOGIC;
signal Mst_N_Slv_mode_cdc_from_spi_d1 : STD_LOGIC;
signal Mst_N_Slv_mode_cdc_from_spi_d2 : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of Mst_N_Slv_mode_cdc_from_spi_d2 : signal is "true";
signal \^other_ratio_generate.rx_shft_reg_s_reg[7]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal SPICR_0_LOOP_cdc_from_axi_d1 : STD_LOGIC;
signal SPICR_1_SPE_cdc_from_axi_d1 : STD_LOGIC;
signal SPICR_2_MST_N_SLV_cdc_from_axi_d1 : STD_LOGIC;
signal \^spicr_2_mst_n_slv_to_spi_clk\ : STD_LOGIC;
signal SPICR_3_CPOL_cdc_from_axi_d1 : STD_LOGIC;
signal SPICR_4_CPHA_cdc_from_axi_d1 : STD_LOGIC;
signal SPICR_7_SS_cdc_from_axi_d1 : STD_LOGIC;
signal SPICR_8_TR_INHIBIT_cdc_from_axi_d1 : STD_LOGIC;
signal SPICR_9_LSB_cdc_from_axi_d1 : STD_LOGIC;
signal SPICR_bits_7_8_cdc_from_axi_d1_0 : STD_LOGIC;
signal SPICR_bits_7_8_cdc_from_axi_d1_1 : STD_LOGIC;
signal SPISR_0_CMD_Error_cdc_from_spi_d1 : STD_LOGIC;
signal SPISR_0_CMD_Error_cdc_from_spi_d2 : STD_LOGIC;
attribute RTL_KEEP of SPISR_0_CMD_Error_cdc_from_spi_d2 : signal is "true";
signal SR_3_modf_cdc_from_axi_d1 : STD_LOGIC;
signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d1 : STD_LOGIC;
signal drr_Overrun_int_cdc_from_spi_d1 : STD_LOGIC;
signal drr_Overrun_int_cdc_from_spi_d2 : STD_LOGIC;
signal drr_Overrun_int_cdc_from_spi_d3 : STD_LOGIC;
signal dtr_underrun_cdc_from_spi_d1 : STD_LOGIC;
signal modf_strobe_cdc_from_spi_d1 : STD_LOGIC;
attribute RTL_KEEP of modf_strobe_cdc_from_spi_d1 : signal is "true";
signal modf_strobe_cdc_from_spi_d2 : STD_LOGIC;
attribute RTL_KEEP of modf_strobe_cdc_from_spi_d2 : signal is "true";
signal modf_strobe_cdc_from_spi_d3 : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal \^register_data_slvsel_int\ : STD_LOGIC;
signal reset_RcFIFO_ptr_cdc_from_axi_d1 : STD_LOGIC;
signal reset_RcFIFO_ptr_cdc_from_axi_d2 : STD_LOGIC;
signal slave_MODF_strobe_cdc_from_spi_d1 : STD_LOGIC;
attribute RTL_KEEP of slave_MODF_strobe_cdc_from_spi_d1 : signal is "true";
signal slave_MODF_strobe_cdc_from_spi_d2 : STD_LOGIC;
attribute RTL_KEEP of slave_MODF_strobe_cdc_from_spi_d2 : signal is "true";
signal slave_MODF_strobe_cdc_from_spi_d3 : STD_LOGIC;
signal spiXfer_done_d1 : STD_LOGIC;
signal \^spixfer_done_d2\ : STD_LOGIC;
signal \^spixfer_done_d3\ : STD_LOGIC;
signal \^spicr_0_loop_to_spi_clk\ : STD_LOGIC;
signal \^spicr_1_spe_to_spi_clk\ : STD_LOGIC;
signal \^spicr_3_cpol_to_spi_clk\ : STD_LOGIC;
signal \^spicr_4_cpha_to_spi_clk\ : STD_LOGIC;
signal spicr_7_ss_to_spi_clk : STD_LOGIC;
signal spicr_8_tr_inhibit_to_spi_clk : STD_LOGIC;
signal \^spicr_9_lsb_to_spi_clk\ : STD_LOGIC;
signal spicr_bits_7_8_to_spi_clk : STD_LOGIC_VECTOR ( 0 to 1 );
signal spisel_d1_reg_cdc_from_spi_d1 : STD_LOGIC;
signal spisel_d1_reg_cdc_from_spi_d2 : STD_LOGIC;
attribute RTL_KEEP of spisel_d1_reg_cdc_from_spi_d2 : signal is "true";
signal spisel_pulse_cdc_from_spi_d1 : STD_LOGIC;
attribute RTL_KEEP of spisel_pulse_cdc_from_spi_d1 : signal is "true";
signal spisel_pulse_cdc_from_spi_d2 : STD_LOGIC;
attribute RTL_KEEP of spisel_pulse_cdc_from_spi_d2 : signal is "true";
signal spisel_pulse_cdc_from_spi_d3 : STD_LOGIC;
signal sr_3_modf_to_spi_clk : STD_LOGIC;
signal transfer_start_i_2_n_0 : STD_LOGIC;
signal \^tx_fifo_occpncy_msb_d1_reg\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of Allow_Slave_MODF_Strobe_i_1 : label is "soft_lutpair18";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.CMD_ERR_S2AX_1_CDC\ : label is "FDR";
attribute box_type : string;
attribute box_type of \LOGIC_GENERATION_FDR.CMD_ERR_S2AX_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.CMD_ERR_S2AX_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.CMD_ERR_S2AX_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_3\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.DTR_UNDERRUN_S2AX_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.DTR_UNDERRUN_S2AX_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.DTR_UNDERRUN_S2AX_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.DTR_UNDERRUN_S2AX_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.MODF_STROBE_S2AX_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.MODF_STROBE_S2AX_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.MODF_STROBE_S2AX_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.MODF_STROBE_S2AX_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.MODF_STROBE_S2AX_3\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.MODF_STROBE_S2AX_3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.MST_N_SLV_MODE_S2AX_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.MST_N_SLV_MODE_S2AX_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.MST_N_SLV_MODE_S2AX_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.MST_N_SLV_MODE_S2AX_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.RX_FIFO_RST_AX2S_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.RX_FIFO_RST_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.RX_FIFO_RST_AX2S_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.RX_FIFO_RST_AX2S_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SLV_MODF_STRB_S2AX_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SLV_MODF_STRB_S2AX_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SLV_MODF_STRB_S2AX_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SLV_MODF_STRB_S2AX_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SLV_MODF_STRB_S2AX_3\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SLV_MODF_STRB_S2AX_3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_1_SPE_AX2S_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_1_SPE_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_1_SPE_AX2S_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_1_SPE_AX2S_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_4_CPHA_AX2S_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_4_CPHA_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_4_CPHA_AX2S_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_4_CPHA_AX2S_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_7_SS_AX2S_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_7_SS_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_7_SS_AX2S_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_7_SS_AX2S_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_8_TR_INHIBIT_AX2S_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_8_TR_INHIBIT_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_8_TR_INHIBIT_AX2S_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_8_TR_INHIBIT_AX2S_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_9_LSB_AX2S_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_9_LSB_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_9_LSB_AX2S_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_9_LSB_AX2S_2\ : label is "PRIMITIVE";
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_1_CDC\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[1].SPICR_BITS_7_8_AX2S_1_CDC\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[1].SPICR_BITS_7_8_AX2S_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[1].SPICR_BITS_7_8_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[1].SPICR_BITS_7_8_AX2S_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[1].SPICR_BITS_7_8_AX2S_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_3\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_AX2S_1_CDC\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_AX2S_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_SYNC_AXI_2_SPI_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_SYNC_AXI_2_SPI_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SR_3_MODF_AX2S_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SR_3_MODF_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SR_3_MODF_AX2S_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SR_3_MODF_AX2S_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of Slave_MODF_strobe_i_2 : label is "soft_lutpair18";
begin
\LOGIC_GENERATION_FDR.SLV_MODF_STRB_S2AX_1_CDC_0\ <= \^logic_generation_fdr.slv_modf_strb_s2ax_1_cdc_0\;
\LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_1_CDC_0\ <= \^logic_generation_fdr.spisel_pulse_s2ax_1_cdc_0\;
\OTHER_RATIO_GENERATE.rx_shft_reg_s_reg[7]\(0) <= \^other_ratio_generate.rx_shft_reg_s_reg[7]\(0);
SPICR_2_MST_N_SLV_to_spi_clk <= \^spicr_2_mst_n_slv_to_spi_clk\;
\ip_irpt_enable_reg_reg[8]\ <= spisel_d1_reg_cdc_from_spi_d2;
register_Data_slvsel_int <= \^register_data_slvsel_int\;
spiXfer_done_d2 <= \^spixfer_done_d2\;
spiXfer_done_d3 <= \^spixfer_done_d3\;
spicr_0_loop_to_spi_clk <= \^spicr_0_loop_to_spi_clk\;
spicr_1_spe_to_spi_clk <= \^spicr_1_spe_to_spi_clk\;
spicr_3_cpol_to_spi_clk <= \^spicr_3_cpol_to_spi_clk\;
spicr_4_cpha_to_spi_clk <= \^spicr_4_cpha_to_spi_clk\;
spicr_9_lsb_to_spi_clk <= \^spicr_9_lsb_to_spi_clk\;
tx_FIFO_Occpncy_MSB_d1_reg <= \^tx_fifo_occpncy_msb_d1_reg\;
Allow_Slave_MODF_Strobe_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"E0"
)
port map (
I0 => \^spicr_2_mst_n_slv_to_spi_clk\,
I1 => \^spicr_1_spe_to_spi_clk\,
I2 => Allow_Slave_MODF_Strobe,
O => Allow_Slave_MODF_Strobe_reg
);
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFF90"
)
port map (
I0 => \^spixfer_done_d3\,
I1 => \^spixfer_done_d2\,
I2 => \FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg_0\,
I3 => \RESET_FLOPS[15].RST_FLOPS\,
I4 => bus2ip_reset_ipif_inverted,
I5 => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\,
O => \FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000E22E"
)
port map (
I0 => Tx_FIFO_Full_i,
I1 => Tx_FIFO_Full_int,
I2 => \^spixfer_done_d2\,
I3 => \^spixfer_done_d3\,
I4 => \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\,
I5 => reset2ip_reset_int,
O => \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_int_reg\
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.spiXfer_done_to_axi_d1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^spixfer_done_d3\,
I1 => \^spixfer_done_d2\,
O => spiXfer_done_to_axi_1
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF6F66F6"
)
port map (
I0 => modf_strobe_cdc_from_spi_d3,
I1 => modf_strobe_cdc_from_spi_d2,
I2 => s_axi_wdata(0),
I3 => \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\,
I4 => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\,
O => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\
);
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF6F66F6"
)
port map (
I0 => slave_MODF_strobe_cdc_from_spi_d3,
I1 => slave_MODF_strobe_cdc_from_spi_d2,
I2 => s_axi_wdata(1),
I3 => \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\,
I4 => p_1_in35_in,
O => \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\
);
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF6F66F6"
)
port map (
I0 => drr_Overrun_int_cdc_from_spi_d3,
I1 => drr_Overrun_int_cdc_from_spi_d2,
I2 => s_axi_wdata(2),
I3 => \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\,
I4 => p_1_in23_in,
O => \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]\
);
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFD0FFD0D0FFD0"
)
port map (
I0 => tx_occ_msb_4,
I1 => \^tx_fifo_occpncy_msb_d1_reg\,
I2 => tx_FIFO_Occpncy_MSB_d1,
I3 => s_axi_wdata(3),
I4 => \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\,
I5 => p_1_in20_in,
O => \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]\
);
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF6F66F6"
)
port map (
I0 => spisel_pulse_cdc_from_spi_d3,
I1 => spisel_pulse_cdc_from_spi_d2,
I2 => s_axi_wdata(4),
I3 => \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\,
I4 => p_1_in17_in,
O => \GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[29]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => \^tx_fifo_occpncy_msb_d1_reg\,
I1 => p_3_in,
I2 => Bus_RNW_reg,
I3 => tx_fifo_count(2),
I4 => empty_fwft_i_reg_0,
I5 => rx_fifo_count(1),
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[30]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => \^tx_fifo_occpncy_msb_d1_reg\,
I1 => p_3_in,
I2 => Bus_RNW_reg,
I3 => tx_fifo_count(1),
I4 => empty_fwft_i_reg_0,
I5 => rx_fifo_count(0),
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => \^tx_fifo_occpncy_msb_d1_reg\,
I1 => p_3_in,
I2 => Bus_RNW_reg,
I3 => tx_fifo_count(0),
I4 => \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\,
I5 => Q(0),
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[31]\
);
\LOCAL_TX_EMPTY_FIFO_12_GEN.stop_clock_reg_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"E0F0E000"
)
port map (
I0 => \^spicr_0_loop_to_spi_clk\,
I1 => \out\,
I2 => SR_5_Tx_comeplete_Empty,
I3 => spiXfer_done_int,
I4 => \^register_data_slvsel_int\,
O => \LOCAL_TX_EMPTY_FIFO_12_GEN.stop_clock_reg_reg\
);
\LOGIC_GENERATION_FDR.CMD_ERR_S2AX_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
Q => SPISR_0_CMD_Error_cdc_from_spi_d1,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.CMD_ERR_S2AX_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => SPISR_0_CMD_Error_cdc_from_spi_d1,
Q => SPISR_0_CMD_Error_cdc_from_spi_d2,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg_n_0\,
Q => drr_Overrun_int_cdc_from_spi_d1,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => drr_Overrun_int_cdc_from_spi_d1,
Q => drr_Overrun_int_cdc_from_spi_d2,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => drr_Overrun_int_cdc_from_spi_d2,
Q => drr_Overrun_int_cdc_from_spi_d3,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.DTR_UNDERRUN_S2AX_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => dtr_underrun_int,
Q => dtr_underrun_cdc_from_spi_d1,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.DTR_UNDERRUN_S2AX_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => dtr_underrun_cdc_from_spi_d1,
Q => dtr_underrun_to_axi_clk,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.MODF_STROBE_S2AX_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \LOGIC_GENERATION_FDR.modf_strobe_cdc_from_spi_int_2_reg_n_0\,
Q => modf_strobe_cdc_from_spi_d1,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.MODF_STROBE_S2AX_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => modf_strobe_cdc_from_spi_d1,
Q => modf_strobe_cdc_from_spi_d2,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.MODF_STROBE_S2AX_3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => modf_strobe_cdc_from_spi_d2,
Q => modf_strobe_cdc_from_spi_d3,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.MST_N_SLV_MODE_S2AX_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
Q => Mst_N_Slv_mode_cdc_from_spi_d1,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.MST_N_SLV_MODE_S2AX_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => Mst_N_Slv_mode_cdc_from_spi_d1,
Q => Mst_N_Slv_mode_cdc_from_spi_d2,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.RX_FIFO_RST_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_reg_n_0\,
Q => reset_RcFIFO_ptr_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.RX_FIFO_RST_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => reset_RcFIFO_ptr_cdc_from_axi_d1,
Q => reset_RcFIFO_ptr_cdc_from_axi_d2,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SLV_MODF_STRB_S2AX_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \^logic_generation_fdr.slv_modf_strb_s2ax_1_cdc_0\,
Q => slave_MODF_strobe_cdc_from_spi_d1,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SLV_MODF_STRB_S2AX_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => slave_MODF_strobe_cdc_from_spi_d1,
Q => slave_MODF_strobe_cdc_from_spi_d2,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SLV_MODF_STRB_S2AX_3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => slave_MODF_strobe_cdc_from_spi_d2,
Q => slave_MODF_strobe_cdc_from_spi_d3,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spicr_0_loop_frm_axi_clk,
Q => SPICR_0_LOOP_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_0_LOOP_cdc_from_axi_d1,
Q => \^spicr_0_loop_to_spi_clk\,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_1_SPE_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spicr_1_spe_frm_axi_clk,
Q => SPICR_1_SPE_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_1_SPE_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_1_SPE_cdc_from_axi_d1,
Q => \^spicr_1_spe_to_spi_clk\,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spicr_2_mst_n_slv_frm_axi_clk,
Q => SPICR_2_MST_N_SLV_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_2_MST_N_SLV_cdc_from_axi_d1,
Q => \^spicr_2_mst_n_slv_to_spi_clk\,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spicr_3_cpol_frm_axi_clk,
Q => SPICR_3_CPOL_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_3_CPOL_cdc_from_axi_d1,
Q => \^spicr_3_cpol_to_spi_clk\,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_4_CPHA_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spicr_4_cpha_frm_axi_clk,
Q => SPICR_4_CPHA_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_4_CPHA_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_4_CPHA_cdc_from_axi_d1,
Q => \^spicr_4_cpha_to_spi_clk\,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_7_SS_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spicr_7_ss_frm_axi_clk,
Q => SPICR_7_SS_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_7_SS_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_7_SS_cdc_from_axi_d1,
Q => spicr_7_ss_to_spi_clk,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_8_TR_INHIBIT_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spicr_8_tr_inhibit_frm_axi_clk,
Q => SPICR_8_TR_INHIBIT_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_8_TR_INHIBIT_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_8_TR_INHIBIT_cdc_from_axi_d1,
Q => spicr_8_tr_inhibit_to_spi_clk,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_9_LSB_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spicr_9_lsb_frm_axi_clk,
Q => SPICR_9_LSB_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_9_LSB_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_9_LSB_cdc_from_axi_d1,
Q => \^spicr_9_lsb_to_spi_clk\,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spicr_bits_7_8_frm_axi_clk(0),
Q => SPICR_bits_7_8_cdc_from_axi_d1_0,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_bits_7_8_cdc_from_axi_d1_0,
Q => spicr_bits_7_8_to_spi_clk(1),
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[1].SPICR_BITS_7_8_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spicr_bits_7_8_frm_axi_clk(1),
Q => SPICR_bits_7_8_cdc_from_axi_d1_1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[1].SPICR_BITS_7_8_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_bits_7_8_cdc_from_axi_d1_1,
Q => spicr_bits_7_8_to_spi_clk(0),
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5556"
)
port map (
I0 => \LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_reg_n_0\,
I1 => \RESET_FLOPS[15].RST_FLOPS\,
I2 => bus2ip_reset_ipif_inverted,
I3 => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\,
O => \LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_i_1_n_0\
);
\LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_i_1_n_0\,
Q => \LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_reg_n_0\,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => spisel_d1_reg,
Q => spisel_d1_reg_cdc_from_spi_d1,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => spisel_d1_reg_cdc_from_spi_d1,
Q => spisel_d1_reg_cdc_from_spi_d2,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \^logic_generation_fdr.spisel_pulse_s2ax_1_cdc_0\,
Q => spisel_pulse_cdc_from_spi_d1,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_2\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => spisel_pulse_cdc_from_spi_d1,
Q => spisel_pulse_cdc_from_spi_d2,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_3\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => spisel_pulse_cdc_from_spi_d2,
Q => spisel_pulse_cdc_from_spi_d3,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPISSR_frm_axi_clk,
Q => \LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_AX2S_1_CDC_n_0\,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_SYNC_AXI_2_SPI_2\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_AX2S_1_CDC_n_0\,
Q => \^register_data_slvsel_int\,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SR_3_MODF_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => sr_3_MODF_int,
Q => SR_3_modf_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SR_3_MODF_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SR_3_modf_cdc_from_axi_d1,
Q => sr_3_modf_to_spi_clk,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg_n_0\,
Q => spiXfer_done_d1,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => spiXfer_done_d1,
Q => \^spixfer_done_d2\,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \^spixfer_done_d2\,
Q => \^spixfer_done_d3\,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.Slave_MODF_strobe_cdc_from_spi_int_2_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => p_7_out,
Q => \^logic_generation_fdr.slv_modf_strb_s2ax_1_cdc_0\,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \out\,
Q => Tx_FIFO_Empty_SPISR_cdc_from_spi_d1,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => Tx_FIFO_Empty_SPISR_cdc_from_spi_d1,
Q => \^tx_fifo_occpncy_msb_d1_reg\,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg_n_0\,
I1 => drr_Overrun_int,
O => p_0_out
);
\LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => p_0_out,
Q => \LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg_n_0\,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.modf_strobe_cdc_from_spi_int_2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \LOGIC_GENERATION_FDR.modf_strobe_cdc_from_spi_int_2_reg_n_0\,
I1 => modf_strobe_int,
O => p_5_out
);
\LOGIC_GENERATION_FDR.modf_strobe_cdc_from_spi_int_2_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => p_5_out,
Q => \LOGIC_GENERATION_FDR.modf_strobe_cdc_from_spi_int_2_reg_n_0\,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg_n_0\,
I1 => spiXfer_done_int,
O => p_2_out
);
\LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => p_2_out,
Q => \LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg_n_0\,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.spisel_pulse_cdc_from_spi_int_2_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \LOGIC_GENERATION_FDR.spisel_pulse_cdc_from_spi_int_2_reg_0\,
Q => \^logic_generation_fdr.spisel_pulse_s2ax_1_cdc_0\,
R => Rst_to_spi
);
MODF_strobe_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^spicr_2_mst_n_slv_to_spi_clk\,
I1 => Allow_MODF_Strobe,
O => MODF_strobe0
);
\OTHER_RATIO_GENERATE.Shift_Reg[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \^other_ratio_generate.rx_shft_reg_s_reg[7]\(0),
I1 => \LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_2_0\,
I2 => \goreg_dm.dout_i_reg[7]\(1),
I3 => \^spicr_9_lsb_to_spi_clk\,
I4 => \goreg_dm.dout_i_reg[7]\(0),
O => \OTHER_RATIO_GENERATE.Shift_Reg_reg[7]\(0)
);
\OTHER_RATIO_GENERATE.rx_shft_reg_s[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^spicr_4_cpha_to_spi_clk\,
I1 => \^spicr_3_cpol_to_spi_clk\,
O => \OTHER_RATIO_GENERATE.sck_o_int_reg\
);
\OTHER_RATIO_GENERATE.rx_shft_reg_s[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => serial_dout_int,
I1 => \^spicr_0_loop_to_spi_clk\,
I2 => io1_i_sync,
I3 => \^spicr_2_mst_n_slv_to_spi_clk\,
I4 => io0_i_sync,
O => \^other_ratio_generate.rx_shft_reg_s_reg[7]\(0)
);
\RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^spicr_2_mst_n_slv_to_spi_clk\,
O => R
);
SPI_TRISTATE_CONTROL_III_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFDFF"
)
port map (
I0 => spicr_bits_7_8_to_spi_clk(1),
I1 => \^spicr_0_loop_to_spi_clk\,
I2 => modf_strobe_int,
I3 => spicr_bits_7_8_to_spi_clk(0),
I4 => sr_3_modf_to_spi_clk,
O => D_0
);
SPI_TRISTATE_CONTROL_V_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => spicr_bits_7_8_to_spi_clk(1),
I1 => \^spicr_0_loop_to_spi_clk\,
I2 => spicr_bits_7_8_to_spi_clk(0),
I3 => SPISEL_sync,
O => SPI_TRISTATE_CONTROL_V
);
\SS_O[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFAB"
)
port map (
I0 => \^register_data_slvsel_int\,
I1 => transfer_start_reg_0,
I2 => spicr_7_ss_to_spi_clk,
I3 => Rst_to_spi,
O => \SS_O_reg[0]\
);
Slave_MODF_strobe_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => Allow_Slave_MODF_Strobe,
I1 => \^spicr_1_spe_to_spi_clk\,
I2 => \^spicr_2_mst_n_slv_to_spi_clk\,
O => Slave_MODF_strobe0
);
\icount_out[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"33F33337333733F3"
)
port map (
I0 => Rx_FIFO_Full_int,
I1 => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_0\,
I2 => empty_fwft_i_reg,
I3 => \FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_sig_reg\,
I4 => \^spixfer_done_d3\,
I5 => \^spixfer_done_d2\,
O => \icount_out_reg[3]\
);
\icount_out[3]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"2022000000002022"
)
port map (
I0 => empty_fwft_i_reg,
I1 => Rx_FIFO_Full_Fifo_d1_sig,
I2 => Rx_FIFO_Full_Fifo_d1_flag,
I3 => scndry_out,
I4 => \^spixfer_done_d3\,
I5 => \^spixfer_done_d2\,
O => \icount_out_reg[1]\
);
\ip_irpt_enable_reg[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => s_axi_wdata(5),
I1 => spisel_d1_reg_cdc_from_spi_d2,
I2 => spicr_2_mst_n_slv_frm_axi_clk,
O => D(0)
);
modf_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BEBE00BE"
)
port map (
I0 => sr_3_MODF_int,
I1 => modf_strobe_cdc_from_spi_d2,
I2 => modf_strobe_cdc_from_spi_d3,
I3 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\,
I4 => Bus_RNW_reg_reg,
I5 => reset2ip_reset_int,
O => modf_reg
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"BE"
)
port map (
I0 => Rst_to_spi,
I1 => reset_RcFIFO_ptr_cdc_from_axi_d1,
I2 => reset_RcFIFO_ptr_cdc_from_axi_d2,
O => rx_fifo_reset
);
transfer_start_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"101010FF"
)
port map (
I0 => Rst_to_spi,
I1 => \^spicr_2_mst_n_slv_to_spi_clk\,
I2 => \^spicr_1_spe_to_spi_clk\,
I3 => transfer_start_i_2_n_0,
I4 => stop_clock,
O => transfer_start_reg
);
transfer_start_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFBFFFBFFFB"
)
port map (
I0 => spicr_8_tr_inhibit_to_spi_clk,
I1 => \^spicr_1_spe_to_spi_clk\,
I2 => sr_3_modf_to_spi_clk,
I3 => RESET_SYNC_AX2S_2,
I4 => \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg\,
I5 => \out\,
O => transfer_start_i_2_n_0
);
tx_FIFO_Empty_d1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => tx_fifo_count_d2(0),
I1 => tx_fifo_count_d2(1),
I2 => tx_fifo_count_d2(2),
I3 => tx_fifo_count_d2(3),
I4 => spiXfer_done_to_axi_d1,
I5 => \^tx_fifo_occpncy_msb_d1_reg\,
O => Tx_FIFO_Empty_intr
);
tx_FIFO_Occpncy_MSB_d1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => tx_occ_msb_4,
I1 => \^tx_fifo_occpncy_msb_d1_reg\,
O => tx_occ_msb
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_interrupt_control is
port (
irpt_wrack_d1 : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ : out STD_LOGIC;
p_1_in35_in : out STD_LOGIC;
p_1_in32_in : out STD_LOGIC;
p_1_in29_in : out STD_LOGIC;
p_1_in26_in : out STD_LOGIC;
p_1_in23_in : out STD_LOGIC;
p_1_in20_in : out STD_LOGIC;
p_1_in17_in : out STD_LOGIC;
p_1_in14_in : out STD_LOGIC;
irpt_rdack_d1 : out STD_LOGIC;
ipif_glbl_irpt_enable_reg : out STD_LOGIC;
IP2Bus_WrAck_1 : out STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[23]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
IP2Bus_RdAck_1 : out STD_LOGIC;
reset2ip_reset_int : in STD_LOGIC;
irpt_wrack : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\LOGIC_GENERATION_FDR.MODF_STROBE_S2AX_3\ : in STD_LOGIC;
\LOGIC_GENERATION_FDR.SLV_MODF_STRB_S2AX_3\ : in STD_LOGIC;
tx_FIFO_Empty_d1_reg : in STD_LOGIC;
dtr_underrun_d1_reg : in STD_LOGIC;
rc_FIFO_Full_d1_reg : in STD_LOGIC;
\LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_3\ : in STD_LOGIC;
\FIFO_EXISTS.tx_occ_msb_4_reg\ : in STD_LOGIC;
\LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_3\ : in STD_LOGIC;
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\ : in STD_LOGIC;
interrupt_wrce_strb : in STD_LOGIC;
irpt_rdack : in STD_LOGIC;
intr2bus_rdack0 : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\ : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole : in STD_LOGIC;
ip2Bus_WrAck_core_reg : in STD_LOGIC;
wrack : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_interrupt_control : entity is "interrupt_control";
end system_axi_quad_spi_shield_0_interrupt_control;
architecture STRUCTURE of system_axi_quad_spi_shield_0_interrupt_control is
signal \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\ : STD_LOGIC;
signal \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal ip2intc_irpt_INST_0_i_1_n_0 : STD_LOGIC;
signal ip2intc_irpt_INST_0_i_2_n_0 : STD_LOGIC;
signal ip2intc_irpt_INST_0_i_3_n_0 : STD_LOGIC;
signal ip2intc_irpt_INST_0_i_4_n_0 : STD_LOGIC;
signal \^ipif_glbl_irpt_enable_reg\ : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal \^p_1_in14_in\ : STD_LOGIC;
signal \^p_1_in17_in\ : STD_LOGIC;
signal \^p_1_in20_in\ : STD_LOGIC;
signal \^p_1_in23_in\ : STD_LOGIC;
signal \^p_1_in26_in\ : STD_LOGIC;
signal \^p_1_in29_in\ : STD_LOGIC;
signal \^p_1_in32_in\ : STD_LOGIC;
signal \^p_1_in35_in\ : STD_LOGIC;
signal p_2_in : STD_LOGIC;
begin
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ <= \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[23]\(8 downto 0) <= \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\(8 downto 0);
ipif_glbl_irpt_enable_reg <= \^ipif_glbl_irpt_enable_reg\;
p_1_in14_in <= \^p_1_in14_in\;
p_1_in17_in <= \^p_1_in17_in\;
p_1_in20_in <= \^p_1_in20_in\;
p_1_in23_in <= \^p_1_in23_in\;
p_1_in26_in <= \^p_1_in26_in\;
p_1_in29_in <= \^p_1_in29_in\;
p_1_in32_in <= \^p_1_in32_in\;
p_1_in35_in <= \^p_1_in35_in\;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \LOGIC_GENERATION_FDR.MODF_STROBE_S2AX_3\,
Q => \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \LOGIC_GENERATION_FDR.SLV_MODF_STRB_S2AX_3\,
Q => \^p_1_in35_in\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => tx_FIFO_Empty_d1_reg,
Q => \^p_1_in32_in\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => dtr_underrun_d1_reg,
Q => \^p_1_in29_in\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rc_FIFO_Full_d1_reg,
Q => \^p_1_in26_in\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_3\,
Q => \^p_1_in23_in\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FIFO_EXISTS.tx_occ_msb_4_reg\,
Q => \^p_1_in20_in\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_3\,
Q => \^p_1_in17_in\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\,
Q => \^p_1_in14_in\,
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_RdAck_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => ip2Bus_RdAck_intr_reg_hole,
I1 => p_0_in,
I2 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\,
O => IP2Bus_RdAck_1
);
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_WrAck_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\,
I1 => p_2_in,
I2 => ip2Bus_WrAck_intr_reg_hole,
I3 => ip2Bus_WrAck_core_reg,
I4 => wrack,
O => IP2Bus_WrAck_1
);
intr2bus_rdack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr2bus_rdack0,
Q => p_0_in,
R => reset2ip_reset_int
);
intr2bus_wrack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => interrupt_wrce_strb,
Q => p_2_in,
R => reset2ip_reset_int
);
ip2intc_irpt_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA8AAAA"
)
port map (
I0 => \^ipif_glbl_irpt_enable_reg\,
I1 => ip2intc_irpt_INST_0_i_1_n_0,
I2 => ip2intc_irpt_INST_0_i_2_n_0,
I3 => ip2intc_irpt_INST_0_i_3_n_0,
I4 => ip2intc_irpt_INST_0_i_4_n_0,
O => ip2intc_irpt
);
ip2intc_irpt_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\(3),
I1 => \^p_1_in29_in\,
I2 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\(7),
I3 => \^p_1_in17_in\,
O => ip2intc_irpt_INST_0_i_1_n_0
);
ip2intc_irpt_INST_0_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\(4),
I1 => \^p_1_in26_in\,
I2 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\(1),
I3 => \^p_1_in35_in\,
O => ip2intc_irpt_INST_0_i_2_n_0
);
ip2intc_irpt_INST_0_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\(8),
I1 => \^p_1_in14_in\,
I2 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\(0),
I3 => \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\,
O => ip2intc_irpt_INST_0_i_3_n_0
);
ip2intc_irpt_INST_0_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\(2),
I1 => \^p_1_in32_in\,
I2 => \^p_1_in20_in\,
I3 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\(6),
I4 => \^p_1_in23_in\,
I5 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\(5),
O => ip2intc_irpt_INST_0_i_4_n_0
);
\ip_irpt_enable_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(0),
Q => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\(0),
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(1),
Q => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\(1),
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(2),
Q => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\(2),
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(3),
Q => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\(3),
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(4),
Q => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\(4),
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(5),
Q => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\(5),
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(6),
Q => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\(6),
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(7),
Q => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\(7),
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(8),
Q => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\(8),
R => reset2ip_reset_int
);
ipif_glbl_irpt_enable_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\,
Q => \^ipif_glbl_irpt_enable_reg\,
R => reset2ip_reset_int
);
irpt_rdack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_rdack,
Q => irpt_rdack_d1,
R => reset2ip_reset_int
);
irpt_wrack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_wrack,
Q => irpt_wrack_d1,
R => reset2ip_reset_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_qspi_cntrl_reg is
port (
spicr_bits_7_8_frm_axi_clk : out STD_LOGIC_VECTOR ( 1 downto 0 );
spicr_0_loop_frm_axi_clk : out STD_LOGIC;
spicr_1_spe_frm_axi_clk : out STD_LOGIC;
\LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_1_CDC\ : out STD_LOGIC;
spicr_3_cpol_frm_axi_clk : out STD_LOGIC;
spicr_4_cpha_frm_axi_clk : out STD_LOGIC;
spicr_7_ss_frm_axi_clk : out STD_LOGIC;
spicr_8_tr_inhibit_frm_axi_clk : out STD_LOGIC;
spicr_9_lsb_frm_axi_clk : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : out STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_0\ : out STD_LOGIC;
\icount_out_reg[3]\ : out STD_LOGIC;
reset_TxFIFO_ptr_int : out STD_LOGIC;
\icount_out_reg[3]_0\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]\ : out STD_LOGIC;
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.Rx_FIFO_Full_int_reg\ : out STD_LOGIC;
reset2ip_reset_int : in STD_LOGIC;
bus2ip_wrce_int : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_aclk : in STD_LOGIC;
SPICR_data_int_reg0 : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\ : in STD_LOGIC;
p_6_in : in STD_LOGIC;
ram_full_i_reg : in STD_LOGIC;
spiXfer_done_to_axi_1 : in STD_LOGIC;
bus2ip_reset_ipif_inverted : in STD_LOGIC;
\RESET_FLOPS[15].RST_FLOPS\ : in STD_LOGIC;
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\ : in STD_LOGIC;
data_Exists_RcFIFO_int_d1 : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\ : in STD_LOGIC;
p_1_in14_in : in STD_LOGIC;
\out\ : in STD_LOGIC;
Rx_FIFO_Full_i : in STD_LOGIC;
Rx_FIFO_Full_int : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\ : in STD_LOGIC;
prmry_in : in STD_LOGIC;
p_8_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_qspi_cntrl_reg : entity is "qspi_cntrl_reg";
end system_axi_quad_spi_shield_0_qspi_cntrl_reg;
architecture STRUCTURE of system_axi_quad_spi_shield_0_qspi_cntrl_reg is
signal \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int[3]_i_1_n_0\ : STD_LOGIC;
signal \^control_reg_3_4_generate[3].spicr_data_int_reg[3]_0\ : STD_LOGIC;
signal \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int[4]_i_1_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg[8]_i_2_n_0\ : STD_LOGIC;
signal \^logic_generation_fdr.spicr_2_mst_n_slv_ax2s_1_cdc\ : STD_LOGIC;
signal \^ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : STD_LOGIC;
signal \^reset_txfifo_ptr_int\ : STD_LOGIC;
attribute box_type : string;
attribute box_type of \SPICR_REG_78_GENERATE[7].SPI_TRISTATE_CONTROL_I\ : label is "PRIMITIVE";
attribute box_type of \SPICR_REG_78_GENERATE[8].SPI_TRISTATE_CONTROL_I\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \icount_out[3]_i_3__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1\ : label is "soft_lutpair17";
begin
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_0\ <= \^control_reg_3_4_generate[3].spicr_data_int_reg[3]_0\;
\LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_1_CDC\ <= \^logic_generation_fdr.spicr_2_mst_n_slv_ax2s_1_cdc\;
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ <= \^ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\;
reset_TxFIFO_ptr_int <= \^reset_txfifo_ptr_int\;
\CONTROL_REG_1_2_GENERATE[1].SPICR_data_int_reg[1]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => SPICR_data_int_reg0,
D => s_axi_wdata(8),
Q => spicr_8_tr_inhibit_frm_axi_clk,
S => reset2ip_reset_int
);
\CONTROL_REG_1_2_GENERATE[2].SPICR_data_int_reg[2]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => SPICR_data_int_reg0,
D => s_axi_wdata(7),
Q => spicr_7_ss_frm_axi_clk,
S => reset2ip_reset_int
);
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000E200"
)
port map (
I0 => \^control_reg_3_4_generate[3].spicr_data_int_reg[3]_0\,
I1 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\,
I2 => s_axi_wdata(6),
I3 => p_8_in,
I4 => Bus_RNW_reg,
I5 => reset2ip_reset_int,
O => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int[3]_i_1_n_0\
);
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int[3]_i_1_n_0\,
Q => \^control_reg_3_4_generate[3].spicr_data_int_reg[3]_0\,
R => '0'
);
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000E200"
)
port map (
I0 => \^ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\,
I1 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\,
I2 => s_axi_wdata(5),
I3 => p_8_in,
I4 => Bus_RNW_reg,
I5 => reset2ip_reset_int,
O => \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int[4]_i_1_n_0\
);
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int[4]_i_1_n_0\,
Q => \^ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\,
R => '0'
);
\CONTROL_REG_5_9_GENERATE[5].SPICR_data_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => SPICR_data_int_reg0,
D => s_axi_wdata(4),
Q => spicr_4_cpha_frm_axi_clk,
R => reset2ip_reset_int
);
\CONTROL_REG_5_9_GENERATE[6].SPICR_data_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => SPICR_data_int_reg0,
D => s_axi_wdata(3),
Q => spicr_3_cpol_frm_axi_clk,
R => reset2ip_reset_int
);
\CONTROL_REG_5_9_GENERATE[7].SPICR_data_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => SPICR_data_int_reg0,
D => s_axi_wdata(2),
Q => \^logic_generation_fdr.spicr_2_mst_n_slv_ax2s_1_cdc\,
R => reset2ip_reset_int
);
\CONTROL_REG_5_9_GENERATE[8].SPICR_data_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => SPICR_data_int_reg0,
D => s_axi_wdata(1),
Q => spicr_1_spe_frm_axi_clk,
R => reset2ip_reset_int
);
\CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => SPICR_data_int_reg0,
D => s_axi_wdata(0),
Q => spicr_0_loop_frm_axi_clk,
R => reset2ip_reset_int
);
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.Rx_FIFO_Full_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0302030203020002"
)
port map (
I0 => Rx_FIFO_Full_i,
I1 => \^control_reg_3_4_generate[3].spicr_data_int_reg[3]_0\,
I2 => reset2ip_reset_int,
I3 => Rx_FIFO_Full_int,
I4 => \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\,
I5 => prmry_in,
O => \FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.Rx_FIFO_Full_int_reg\
);
\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF1FF01010F01"
)
port map (
I0 => \FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\,
I1 => data_Exists_RcFIFO_int_d1,
I2 => \GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg[8]_i_2_n_0\,
I3 => s_axi_wdata(8),
I4 => \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\,
I5 => p_1_in14_in,
O => \GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]\
);
\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg[8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^logic_generation_fdr.spicr_2_mst_n_slv_ax2s_1_cdc\,
I1 => \out\,
O => \GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg[8]_i_2_n_0\
);
\SPICR_REG_78_GENERATE[7].SPI_TRISTATE_CONTROL_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce_int(0),
D => s_axi_wdata(2),
Q => spicr_bits_7_8_frm_axi_clk(1),
R => reset2ip_reset_int
);
\SPICR_REG_78_GENERATE[8].SPI_TRISTATE_CONTROL_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce_int(0),
D => s_axi_wdata(1),
Q => spicr_bits_7_8_frm_axi_clk(0),
R => reset2ip_reset_int
);
\SPICR_data_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => SPICR_data_int_reg0,
D => s_axi_wdata(9),
Q => spicr_9_lsb_frm_axi_clk,
R => reset2ip_reset_int
);
\icount_out[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEFFFAAAABAAA"
)
port map (
I0 => \^reset_txfifo_ptr_int\,
I1 => Bus_RNW_reg,
I2 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\,
I3 => p_6_in,
I4 => ram_full_i_reg,
I5 => spiXfer_done_to_axi_1,
O => \icount_out_reg[3]\
);
\icount_out[3]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^control_reg_3_4_generate[3].spicr_data_int_reg[3]_0\,
I1 => bus2ip_reset_ipif_inverted,
I2 => \RESET_FLOPS[15].RST_FLOPS\,
O => \icount_out_reg[3]_0\
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \^ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\,
I1 => bus2ip_reset_ipif_inverted,
I2 => \RESET_FLOPS[15].RST_FLOPS\,
O => \^reset_txfifo_ptr_int\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_qspi_fifo_ifmodule is
port (
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_Error_reg\ : out STD_LOGIC;
p_4_in : out STD_LOGIC;
tx_FIFO_Occpncy_MSB_d1 : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\ : out STD_LOGIC;
reset2ip_reset_int : in STD_LOGIC;
Rx_FIFO_Full_Fifo_d1_synced_i : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
Tx_FIFO_Empty_intr : in STD_LOGIC;
Receive_ip2bus_error0 : in STD_LOGIC;
Transmit_ip2bus_error0 : in STD_LOGIC;
tx_occ_msb : in STD_LOGIC;
dtr_underrun_to_axi_clk : in STD_LOGIC;
scndry_out : in STD_LOGIC;
prmry_in : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 2 downto 0 );
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\ : in STD_LOGIC;
p_1_in26_in : in STD_LOGIC;
p_1_in29_in : in STD_LOGIC;
p_1_in32_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_qspi_fifo_ifmodule : entity is "qspi_fifo_ifmodule";
end system_axi_quad_spi_shield_0_qspi_fifo_ifmodule;
architecture STRUCTURE of system_axi_quad_spi_shield_0_qspi_fifo_ifmodule is
signal dtr_underrun_d1 : STD_LOGIC;
signal rc_FIFO_Full_d1 : STD_LOGIC;
signal tx_FIFO_Empty_d1 : STD_LOGIC;
begin
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4F44F4"
)
port map (
I0 => tx_FIFO_Empty_d1,
I1 => Tx_FIFO_Empty_intr,
I2 => s_axi_wdata(0),
I3 => \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\,
I4 => p_1_in32_in,
O => \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\
);
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4F44F4"
)
port map (
I0 => dtr_underrun_d1,
I1 => dtr_underrun_to_axi_clk,
I2 => s_axi_wdata(1),
I3 => \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\,
I4 => p_1_in29_in,
O => \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\
);
\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF04FF0404FF04"
)
port map (
I0 => rc_FIFO_Full_d1,
I1 => scndry_out,
I2 => prmry_in,
I3 => s_axi_wdata(2),
I4 => \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\,
I5 => p_1_in26_in,
O => \GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4]\
);
Receive_ip2bus_error_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Receive_ip2bus_error0,
Q => \LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_Error_reg\,
R => reset2ip_reset_int
);
Transmit_ip2bus_error_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Transmit_ip2bus_error0,
Q => p_4_in,
R => reset2ip_reset_int
);
dtr_underrun_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => dtr_underrun_to_axi_clk,
Q => dtr_underrun_d1,
R => reset2ip_reset_int
);
rc_FIFO_Full_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Rx_FIFO_Full_Fifo_d1_synced_i,
Q => rc_FIFO_Full_d1,
R => reset2ip_reset_int
);
tx_FIFO_Empty_d1_reg: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => Tx_FIFO_Empty_intr,
Q => tx_FIFO_Empty_d1,
S => reset2ip_reset_int
);
tx_FIFO_Occpncy_MSB_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => tx_occ_msb,
Q => tx_FIFO_Occpncy_MSB_d1,
R => reset2ip_reset_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_qspi_mode_0_module is
port (
sck_t : out STD_LOGIC;
io0_t : out STD_LOGIC;
ss_t : out STD_LOGIC;
io1_t : out STD_LOGIC;
SPISEL_sync : out STD_LOGIC;
sck_o : out STD_LOGIC;
modf_strobe_int : out STD_LOGIC;
spisel_d1_reg : out STD_LOGIC;
SPIXfer_done_int_d1_reg_0 : out STD_LOGIC;
spiXfer_done_int : out STD_LOGIC;
stop_clock : out STD_LOGIC;
transfer_start_d1_reg_0 : out STD_LOGIC;
drr_Overrun_int : out STD_LOGIC;
Allow_Slave_MODF_Strobe : out STD_LOGIC;
Allow_MODF_Strobe : out STD_LOGIC;
SR_5_Tx_comeplete_Empty : out STD_LOGIC;
io0_o : out STD_LOGIC;
serial_dout_int : out STD_LOGIC;
dtr_underrun_int : out STD_LOGIC;
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
\LOGIC_GENERATION_FDR.spisel_pulse_cdc_from_spi_int_2_reg\ : out STD_LOGIC;
p_7_out : out STD_LOGIC;
empty_fwft_fb_o_i_reg : out STD_LOGIC;
\OTHER_RATIO_GENERATE.Shift_Reg_reg[6]_0\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gpr1.dout_i_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
D_0 : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
\LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_2\ : in STD_LOGIC;
spisel : in STD_LOGIC;
sck_i : in STD_LOGIC;
R : in STD_LOGIC;
Rst_to_spi : in STD_LOGIC;
RESET_SYNC_AX2S_2 : in STD_LOGIC;
Slave_MODF_strobe0 : in STD_LOGIC;
MODF_strobe0 : in STD_LOGIC;
\out\ : in STD_LOGIC;
\LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_2\ : in STD_LOGIC;
RESET_SYNC_AX2S_2_0 : in STD_LOGIC;
\LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_SYNC_AXI_2_SPI_2\ : in STD_LOGIC;
\LOGIC_GENERATION_FDR.spisel_pulse_cdc_from_spi_int_2_reg_0\ : in STD_LOGIC;
SPICR_2_MST_N_SLV_to_spi_clk : in STD_LOGIC;
\LOGIC_GENERATION_FDR.Slave_MODF_strobe_cdc_from_spi_int_2_reg\ : in STD_LOGIC;
spicr_0_loop_to_spi_clk : in STD_LOGIC;
spicr_1_spe_to_spi_clk : in STD_LOGIC;
RESET_SYNC_AX2S_2_1 : in STD_LOGIC;
\LOGIC_GENERATION_FDR.SPICR_4_CPHA_AX2S_2\ : in STD_LOGIC;
p_6_out : in STD_LOGIC;
spicr_4_cpha_to_spi_clk : in STD_LOGIC;
spicr_3_cpol_to_spi_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
spicr_9_lsb_to_spi_clk : in STD_LOGIC;
\goreg_dm.dout_i_reg[0]\ : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
\LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_2\ : in STD_LOGIC;
register_Data_slvsel_int : in STD_LOGIC;
scndry_out : in STD_LOGIC;
ram_full_i_reg : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[7]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
RESET_SYNC_AX2S_2_2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_qspi_mode_0_module : entity is "qspi_mode_0_module";
end system_axi_quad_spi_shield_0_qspi_mode_0_module;
architecture STRUCTURE of system_axi_quad_spi_shield_0_qspi_mode_0_module is
signal \^allow_modf_strobe\ : STD_LOGIC;
signal Allow_MODF_Strobe_i_1_n_0 : STD_LOGIC;
signal Count : STD_LOGIC_VECTOR ( 4 downto 0 );
signal Count_trigger : STD_LOGIC;
signal Count_trigger_d1 : STD_LOGIC;
signal \DTR_UNDERRUN_FIFO_EXIST_GEN.DTR_underrun_i_1_n_0\ : STD_LOGIC;
signal \LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_1_n_0\ : STD_LOGIC;
signal \LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_2_n_0\ : STD_LOGIC;
signal \LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[1]_i_1_n_0\ : STD_LOGIC;
signal \LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[1]_i_2_n_0\ : STD_LOGIC;
signal \LOCAL_TX_EMPTY_FIFO_12_GEN.stop_clock_reg_i_3_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Count[2]_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Count[3]_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Count[4]_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Count[4]_i_2_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Count_reg_n_0_[0]\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Count_reg_n_0_[1]\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Count_reg_n_0_[2]\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Count_reg_n_0_[3]\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Count_trigger_d1_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Count_trigger_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Ratio_Count[0]_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Ratio_Count[1]_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Ratio_Count[2]_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Serial_Dout_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Serial_Dout_i_2_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Serial_Dout_i_3_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Serial_Dout_i_4_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Serial_Dout_i_6_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_2_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_3_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_4_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Shift_Reg[1]_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Shift_Reg[2]_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Shift_Reg[3]_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Shift_Reg[4]_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Shift_Reg[5]_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Shift_Reg[6]_i_1_n_0\ : STD_LOGIC;
signal \^other_ratio_generate.shift_reg_reg[6]_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Shift_Reg_reg_n_0_[1]\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Shift_Reg_reg_n_0_[2]\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Shift_Reg_reg_n_0_[3]\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Shift_Reg_reg_n_0_[4]\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Shift_Reg_reg_n_0_[5]\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Shift_Reg_reg_n_0_[6]\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Shift_Reg_reg_n_0_[7]\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.rx_shft_reg_s[0]_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.sck_o_int_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.sck_o_int_i_2_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.serial_dout_int_i_1_n_0\ : STD_LOGIC;
signal \RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST_i_2_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_1_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_2_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_3_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_4_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_5_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_2_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_3_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[1]_i_1_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[1]_i_2_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[1]_i_3_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[2]_i_1_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[2]_i_2_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[2]_i_3_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[3]_i_1_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[3]_i_2_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[3]_i_3_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[4]_i_1_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[5]_i_1_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[6]_i_1_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[7]_i_1_n_0\ : STD_LOGIC;
signal Ratio_Count : STD_LOGIC_VECTOR ( 0 to 2 );
signal SCK_I_sync : STD_LOGIC;
signal \^spisel_sync\ : STD_LOGIC;
signal SPIXfer_done_int_d1 : STD_LOGIC;
signal \^spixfer_done_int_d1_reg_0\ : STD_LOGIC;
signal SPIXfer_done_int_pulse : STD_LOGIC;
signal SPIXfer_done_int_pulse_d1 : STD_LOGIC;
signal SR_5_Tx_Empty_d1 : STD_LOGIC;
signal \^sr_5_tx_comeplete_empty\ : STD_LOGIC;
signal SR_5_Tx_comeplete_Empty_i_1_n_0 : STD_LOGIC;
signal \^drr_overrun_int\ : STD_LOGIC;
signal \^dtr_underrun_int\ : STD_LOGIC;
signal \^io0_o\ : STD_LOGIC;
signal load : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal p_20_out : STD_LOGIC;
signal p_37_out : STD_LOGIC;
signal p_3_in : STD_LOGIC;
signal rx_shft_reg_mode_0011 : STD_LOGIC_VECTOR ( 0 to 7 );
signal rx_shft_reg_mode_0110 : STD_LOGIC_VECTOR ( 0 to 7 );
signal rx_shft_reg_s : STD_LOGIC_VECTOR ( 0 to 7 );
signal sck_d1 : STD_LOGIC;
signal sck_d2 : STD_LOGIC;
signal sck_i_d1 : STD_LOGIC;
signal sck_o_int : STD_LOGIC;
signal slave_MODF_strobe_int : STD_LOGIC;
signal \^spixfer_done_int\ : STD_LOGIC;
signal spi_cntrl_ps : STD_LOGIC_VECTOR ( 1 downto 0 );
signal spisel_d1 : STD_LOGIC;
signal \^spisel_d1_reg\ : STD_LOGIC;
signal spisel_once_1 : STD_LOGIC;
signal spisel_once_1_i_1_n_0 : STD_LOGIC;
signal \^stop_clock\ : STD_LOGIC;
signal stop_clock_reg : STD_LOGIC;
signal transfer_start_d1 : STD_LOGIC;
signal \^transfer_start_d1_reg_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \LOCAL_TX_EMPTY_FIFO_12_GEN.DRR_Overrun_reg_int_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_2\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \LOCAL_TX_EMPTY_FIFO_12_GEN.stop_clock_reg_i_3\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \LOGIC_GENERATION_FDR.spisel_pulse_cdc_from_spi_int_2_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \OTHER_RATIO_GENERATE.Count[1]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \OTHER_RATIO_GENERATE.Count[2]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \OTHER_RATIO_GENERATE.Count[3]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \OTHER_RATIO_GENERATE.Count[4]_i_3\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \OTHER_RATIO_GENERATE.Count_trigger_d1_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \OTHER_RATIO_GENERATE.Ratio_Count[0]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \OTHER_RATIO_GENERATE.Ratio_Count[1]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \OTHER_RATIO_GENERATE.Ratio_Count[2]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \OTHER_RATIO_GENERATE.Serial_Dout_i_3\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \OTHER_RATIO_GENERATE.Serial_Dout_i_4\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \OTHER_RATIO_GENERATE.Serial_Dout_i_6\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_5\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \OTHER_RATIO_GENERATE.sck_o_int_i_2\ : label is "soft_lutpair42";
attribute IOB : string;
attribute IOB of \RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST\ : label is "TRUE";
attribute box_type : string;
attribute box_type of \RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST_i_2\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_2\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_4\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_5\ : label is "soft_lutpair36";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of SCK_I_REG : label is "FD";
attribute box_type of SCK_I_REG : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of SPISEL_REG : label is "FD";
attribute box_type of SPISEL_REG : label is "PRIMITIVE";
attribute SOFT_HLUTNM of SPIXfer_done_int_pulse_d1_i_1 : label is "soft_lutpair40";
attribute XILINX_LEGACY_PRIM of SPI_TRISTATE_CONTROL_II : label is "FD";
attribute box_type of SPI_TRISTATE_CONTROL_II : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of SPI_TRISTATE_CONTROL_III : label is "FD";
attribute box_type of SPI_TRISTATE_CONTROL_III : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of SPI_TRISTATE_CONTROL_IV : label is "FD";
attribute box_type of SPI_TRISTATE_CONTROL_IV : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of SPI_TRISTATE_CONTROL_V : label is "FD";
attribute box_type of SPI_TRISTATE_CONTROL_V : label is "PRIMITIVE";
attribute SOFT_HLUTNM of SR_5_Tx_comeplete_Empty_i_1 : label is "soft_lutpair40";
attribute SOFT_HLUTNM of spisel_once_1_i_1 : label is "soft_lutpair41";
begin
Allow_MODF_Strobe <= \^allow_modf_strobe\;
\OTHER_RATIO_GENERATE.Shift_Reg_reg[6]_0\ <= \^other_ratio_generate.shift_reg_reg[6]_0\;
SPISEL_sync <= \^spisel_sync\;
SPIXfer_done_int_d1_reg_0 <= \^spixfer_done_int_d1_reg_0\;
SR_5_Tx_comeplete_Empty <= \^sr_5_tx_comeplete_empty\;
drr_Overrun_int <= \^drr_overrun_int\;
dtr_underrun_int <= \^dtr_underrun_int\;
io0_o <= \^io0_o\;
spiXfer_done_int <= \^spixfer_done_int\;
spisel_d1_reg <= \^spisel_d1_reg\;
stop_clock <= \^stop_clock\;
transfer_start_d1_reg_0 <= \^transfer_start_d1_reg_0\;
Allow_MODF_Strobe_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^allow_modf_strobe\,
I1 => SPICR_2_MST_N_SLV_to_spi_clk,
O => Allow_MODF_Strobe_i_1_n_0
);
Allow_MODF_Strobe_reg: unisim.vcomponents.FDSE
port map (
C => ext_spi_clk,
CE => '1',
D => Allow_MODF_Strobe_i_1_n_0,
Q => \^allow_modf_strobe\,
S => RESET_SYNC_AX2S_2
);
Allow_Slave_MODF_Strobe_reg: unisim.vcomponents.FDSE
port map (
C => ext_spi_clk,
CE => '1',
D => \LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_2\,
Q => Allow_Slave_MODF_Strobe,
S => RESET_SYNC_AX2S_2
);
\DTR_UNDERRUN_FIFO_EXIST_GEN.DTR_underrun_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000C8AA"
)
port map (
I0 => \^dtr_underrun_int\,
I1 => \^sr_5_tx_comeplete_empty\,
I2 => SPIXfer_done_int_pulse,
I3 => spicr_1_spe_to_spi_clk,
I4 => RESET_SYNC_AX2S_2_1,
I5 => \^spisel_sync\,
O => \DTR_UNDERRUN_FIFO_EXIST_GEN.DTR_underrun_i_1_n_0\
);
\DTR_UNDERRUN_FIFO_EXIST_GEN.DTR_underrun_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \DTR_UNDERRUN_FIFO_EXIST_GEN.DTR_underrun_i_1_n_0\,
Q => \^dtr_underrun_int\,
R => '0'
);
\LOCAL_TX_EMPTY_FIFO_12_GEN.DRR_Overrun_reg_int_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => scndry_out,
I1 => ram_full_i_reg,
I2 => \^spixfer_done_int\,
I3 => \^drr_overrun_int\,
O => p_37_out
);
\LOCAL_TX_EMPTY_FIFO_12_GEN.DRR_Overrun_reg_int_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => p_37_out,
Q => \^drr_overrun_int\,
R => Rst_to_spi
);
\LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000F0800FF0F08"
)
port map (
I0 => SPICR_2_MST_N_SLV_to_spi_clk,
I1 => \LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_2_n_0\,
I2 => \out\,
I3 => spi_cntrl_ps(0),
I4 => spi_cntrl_ps(1),
I5 => \^sr_5_tx_comeplete_empty\,
O => \LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_1_n_0\
);
\LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^transfer_start_d1_reg_0\,
I1 => transfer_start_d1,
O => \LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_2_n_0\
);
\LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00404040"
)
port map (
I0 => spi_cntrl_ps(1),
I1 => spi_cntrl_ps(0),
I2 => \out\,
I3 => \^spixfer_done_int\,
I4 => \^sr_5_tx_comeplete_empty\,
I5 => \LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[1]_i_2_n_0\,
O => \LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[1]_i_1_n_0\
);
\LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000470000000000"
)
port map (
I0 => spicr_0_loop_to_spi_clk,
I1 => \^spixfer_done_int\,
I2 => register_Data_slvsel_int,
I3 => \^sr_5_tx_comeplete_empty\,
I4 => spi_cntrl_ps(0),
I5 => spi_cntrl_ps(1),
O => \LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[1]_i_2_n_0\
);
\LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_1_n_0\,
Q => spi_cntrl_ps(0),
R => Rst_to_spi
);
\LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[1]_i_1_n_0\,
Q => spi_cntrl_ps(1),
R => Rst_to_spi
);
\LOCAL_TX_EMPTY_FIFO_12_GEN.stop_clock_reg_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7430545474305410"
)
port map (
I0 => spi_cntrl_ps(0),
I1 => spi_cntrl_ps(1),
I2 => \out\,
I3 => \LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_2\,
I4 => \LOCAL_TX_EMPTY_FIFO_12_GEN.stop_clock_reg_i_3_n_0\,
I5 => stop_clock_reg,
O => \^stop_clock\
);
\LOCAL_TX_EMPTY_FIFO_12_GEN.stop_clock_reg_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^spixfer_done_int\,
I1 => \^sr_5_tx_comeplete_empty\,
O => \LOCAL_TX_EMPTY_FIFO_12_GEN.stop_clock_reg_i_3_n_0\
);
\LOCAL_TX_EMPTY_FIFO_12_GEN.stop_clock_reg_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \^stop_clock\,
Q => stop_clock_reg,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.Slave_MODF_strobe_cdc_from_spi_int_2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => slave_MODF_strobe_int,
I1 => \LOGIC_GENERATION_FDR.Slave_MODF_strobe_cdc_from_spi_int_2_reg\,
O => p_7_out
);
\LOGIC_GENERATION_FDR.spisel_pulse_cdc_from_spi_int_2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"A6"
)
port map (
I0 => \LOGIC_GENERATION_FDR.spisel_pulse_cdc_from_spi_int_2_reg_0\,
I1 => \^spisel_d1_reg\,
I2 => spisel_d1,
O => \LOGIC_GENERATION_FDR.spisel_pulse_cdc_from_spi_int_2_reg\
);
MODF_strobe_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => MODF_strobe0,
Q => modf_strobe_int,
R => RESET_SYNC_AX2S_2
);
\OTHER_RATIO_GENERATE.Count[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[0]\,
I1 => load,
O => Count(0)
);
\OTHER_RATIO_GENERATE.Count[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"06"
)
port map (
I0 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[1]\,
I1 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[0]\,
I2 => load,
O => Count(1)
);
\OTHER_RATIO_GENERATE.Count[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1540"
)
port map (
I0 => load,
I1 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[0]\,
I2 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[1]\,
I3 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[2]\,
O => \OTHER_RATIO_GENERATE.Count[2]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Count[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"15554000"
)
port map (
I0 => load,
I1 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[1]\,
I2 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[0]\,
I3 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[2]\,
I4 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[3]\,
O => \OTHER_RATIO_GENERATE.Count[3]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFDDFD"
)
port map (
I0 => \^transfer_start_d1_reg_0\,
I1 => Rst_to_spi,
I2 => \^spisel_sync\,
I3 => SPICR_2_MST_N_SLV_to_spi_clk,
I4 => \^spixfer_done_int_d1_reg_0\,
O => \OTHER_RATIO_GENERATE.Count[4]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Count[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"20202020202F2F20"
)
port map (
I0 => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_4_n_0\,
I1 => load,
I2 => SPICR_2_MST_N_SLV_to_spi_clk,
I3 => SCK_I_sync,
I4 => sck_i_d1,
I5 => \^spisel_sync\,
O => \OTHER_RATIO_GENERATE.Count[4]_i_2_n_0\
);
\OTHER_RATIO_GENERATE.Count[4]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00008000"
)
port map (
I0 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[2]\,
I1 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[3]\,
I2 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[0]\,
I3 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[1]\,
I4 => load,
O => Count(4)
);
\OTHER_RATIO_GENERATE.Count_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.Count[4]_i_2_n_0\,
D => Count(0),
Q => \OTHER_RATIO_GENERATE.Count_reg_n_0_[0]\,
R => \OTHER_RATIO_GENERATE.Count[4]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Count_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.Count[4]_i_2_n_0\,
D => Count(1),
Q => \OTHER_RATIO_GENERATE.Count_reg_n_0_[1]\,
R => \OTHER_RATIO_GENERATE.Count[4]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Count_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.Count[4]_i_2_n_0\,
D => \OTHER_RATIO_GENERATE.Count[2]_i_1_n_0\,
Q => \OTHER_RATIO_GENERATE.Count_reg_n_0_[2]\,
R => \OTHER_RATIO_GENERATE.Count[4]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Count_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.Count[4]_i_2_n_0\,
D => \OTHER_RATIO_GENERATE.Count[3]_i_1_n_0\,
Q => \OTHER_RATIO_GENERATE.Count_reg_n_0_[3]\,
R => \OTHER_RATIO_GENERATE.Count[4]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Count_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.Count[4]_i_2_n_0\,
D => Count(4),
Q => load,
R => \OTHER_RATIO_GENERATE.Count[4]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Count_trigger_d1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => Count_trigger,
I1 => \^transfer_start_d1_reg_0\,
I2 => Rst_to_spi,
O => \OTHER_RATIO_GENERATE.Count_trigger_d1_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Count_trigger_d1_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \OTHER_RATIO_GENERATE.Count_trigger_d1_i_1_n_0\,
Q => Count_trigger_d1,
R => '0'
);
\OTHER_RATIO_GENERATE.Count_trigger_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAA90000"
)
port map (
I0 => Count_trigger,
I1 => Ratio_Count(0),
I2 => Ratio_Count(1),
I3 => Ratio_Count(2),
I4 => \^transfer_start_d1_reg_0\,
I5 => Rst_to_spi,
O => \OTHER_RATIO_GENERATE.Count_trigger_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Count_trigger_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \OTHER_RATIO_GENERATE.Count_trigger_i_1_n_0\,
Q => Count_trigger,
R => '0'
);
\OTHER_RATIO_GENERATE.Ratio_Count[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFA9FFFF"
)
port map (
I0 => Ratio_Count(0),
I1 => Ratio_Count(1),
I2 => Ratio_Count(2),
I3 => Rst_to_spi,
I4 => \^transfer_start_d1_reg_0\,
O => \OTHER_RATIO_GENERATE.Ratio_Count[0]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Ratio_Count[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F9FF"
)
port map (
I0 => Ratio_Count(1),
I1 => Ratio_Count(2),
I2 => Rst_to_spi,
I3 => \^transfer_start_d1_reg_0\,
O => \OTHER_RATIO_GENERATE.Ratio_Count[1]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Ratio_Count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => Ratio_Count(2),
I1 => Rst_to_spi,
I2 => \^transfer_start_d1_reg_0\,
O => \OTHER_RATIO_GENERATE.Ratio_Count[2]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Ratio_Count_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \OTHER_RATIO_GENERATE.Ratio_Count[0]_i_1_n_0\,
Q => Ratio_Count(0),
R => '0'
);
\OTHER_RATIO_GENERATE.Ratio_Count_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \OTHER_RATIO_GENERATE.Ratio_Count[1]_i_1_n_0\,
Q => Ratio_Count(1),
R => '0'
);
\OTHER_RATIO_GENERATE.Ratio_Count_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \OTHER_RATIO_GENERATE.Ratio_Count[2]_i_1_n_0\,
Q => Ratio_Count(2),
R => '0'
);
\OTHER_RATIO_GENERATE.Serial_Dout_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABFFABABA800A8A8"
)
port map (
I0 => \OTHER_RATIO_GENERATE.Serial_Dout_i_2_n_0\,
I1 => \OTHER_RATIO_GENERATE.Serial_Dout_i_3_n_0\,
I2 => \^transfer_start_d1_reg_0\,
I3 => \OTHER_RATIO_GENERATE.Serial_Dout_i_4_n_0\,
I4 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[0]\,
I5 => \^io0_o\,
O => \OTHER_RATIO_GENERATE.Serial_Dout_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Serial_Dout_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF10FF1FEF00E000"
)
port map (
I0 => SPIXfer_done_int_d1,
I1 => \LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_2_n_0\,
I2 => SPICR_2_MST_N_SLV_to_spi_clk,
I3 => \goreg_dm.dout_i_reg[0]\,
I4 => \OTHER_RATIO_GENERATE.Serial_Dout_i_6_n_0\,
I5 => p_3_in,
O => \OTHER_RATIO_GENERATE.Serial_Dout_i_2_n_0\
);
\OTHER_RATIO_GENERATE.Serial_Dout_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFAE"
)
port map (
I0 => SPICR_2_MST_N_SLV_to_spi_clk,
I1 => SR_5_Tx_Empty_d1,
I2 => \out\,
I3 => \^spixfer_done_int_d1_reg_0\,
O => \OTHER_RATIO_GENERATE.Serial_Dout_i_3_n_0\
);
\OTHER_RATIO_GENERATE.Serial_Dout_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"F2FF"
)
port map (
I0 => \^transfer_start_d1_reg_0\,
I1 => transfer_start_d1,
I2 => SPIXfer_done_int_d1,
I3 => SPICR_2_MST_N_SLV_to_spi_clk,
O => \OTHER_RATIO_GENERATE.Serial_Dout_i_4_n_0\
);
\OTHER_RATIO_GENERATE.Serial_Dout_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \^spixfer_done_int_d1_reg_0\,
I1 => \out\,
I2 => SR_5_Tx_Empty_d1,
O => \OTHER_RATIO_GENERATE.Serial_Dout_i_6_n_0\
);
\OTHER_RATIO_GENERATE.Serial_Dout_reg\: unisim.vcomponents.FDSE
port map (
C => ext_spi_clk,
CE => '1',
D => \OTHER_RATIO_GENERATE.Serial_Dout_i_1_n_0\,
Q => \^io0_o\,
S => Rst_to_spi
);
\OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCCCFCCCA8880000"
)
port map (
I0 => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_3_n_0\,
I1 => \OTHER_RATIO_GENERATE.Serial_Dout_i_4_n_0\,
I2 => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_4_n_0\,
I3 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[0]\,
I4 => \^transfer_start_d1_reg_0\,
I5 => \OTHER_RATIO_GENERATE.Serial_Dout_i_3_n_0\,
O => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Shift_Reg[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \OTHER_RATIO_GENERATE.Shift_Reg_reg_n_0_[1]\,
I1 => \^other_ratio_generate.shift_reg_reg[6]_0\,
I2 => Q(0),
I3 => spicr_9_lsb_to_spi_clk,
I4 => Q(7),
O => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_2_n_0\
);
\OTHER_RATIO_GENERATE.Shift_Reg[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00060900"
)
port map (
I0 => spicr_4_cpha_to_spi_clk,
I1 => spicr_3_cpol_to_spi_clk,
I2 => \^spisel_sync\,
I3 => SCK_I_sync,
I4 => sck_i_d1,
O => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_3_n_0\
);
\OTHER_RATIO_GENERATE.Shift_Reg[0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Count_trigger,
I1 => Count_trigger_d1,
O => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_4_n_0\
);
\OTHER_RATIO_GENERATE.Shift_Reg[0]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"5D555D5D"
)
port map (
I0 => \OTHER_RATIO_GENERATE.Serial_Dout_i_3_n_0\,
I1 => SPICR_2_MST_N_SLV_to_spi_clk,
I2 => SPIXfer_done_int_d1,
I3 => transfer_start_d1,
I4 => \^transfer_start_d1_reg_0\,
O => \^other_ratio_generate.shift_reg_reg[6]_0\
);
\OTHER_RATIO_GENERATE.Shift_Reg[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \OTHER_RATIO_GENERATE.Shift_Reg_reg_n_0_[2]\,
I1 => \^other_ratio_generate.shift_reg_reg[6]_0\,
I2 => Q(1),
I3 => spicr_9_lsb_to_spi_clk,
I4 => Q(6),
O => \OTHER_RATIO_GENERATE.Shift_Reg[1]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Shift_Reg[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \OTHER_RATIO_GENERATE.Shift_Reg_reg_n_0_[3]\,
I1 => \^other_ratio_generate.shift_reg_reg[6]_0\,
I2 => Q(2),
I3 => spicr_9_lsb_to_spi_clk,
I4 => Q(5),
O => \OTHER_RATIO_GENERATE.Shift_Reg[2]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Shift_Reg[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \OTHER_RATIO_GENERATE.Shift_Reg_reg_n_0_[4]\,
I1 => \^other_ratio_generate.shift_reg_reg[6]_0\,
I2 => Q(3),
I3 => spicr_9_lsb_to_spi_clk,
I4 => Q(4),
O => \OTHER_RATIO_GENERATE.Shift_Reg[3]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Shift_Reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \OTHER_RATIO_GENERATE.Shift_Reg_reg_n_0_[5]\,
I1 => \^other_ratio_generate.shift_reg_reg[6]_0\,
I2 => Q(4),
I3 => spicr_9_lsb_to_spi_clk,
I4 => Q(3),
O => \OTHER_RATIO_GENERATE.Shift_Reg[4]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Shift_Reg[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \OTHER_RATIO_GENERATE.Shift_Reg_reg_n_0_[6]\,
I1 => \^other_ratio_generate.shift_reg_reg[6]_0\,
I2 => Q(5),
I3 => spicr_9_lsb_to_spi_clk,
I4 => Q(2),
O => \OTHER_RATIO_GENERATE.Shift_Reg[5]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Shift_Reg[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \OTHER_RATIO_GENERATE.Shift_Reg_reg_n_0_[7]\,
I1 => \^other_ratio_generate.shift_reg_reg[6]_0\,
I2 => Q(6),
I3 => spicr_9_lsb_to_spi_clk,
I4 => Q(1),
O => \OTHER_RATIO_GENERATE.Shift_Reg[6]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Shift_Reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0\,
D => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_2_n_0\,
Q => p_3_in,
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.Shift_Reg_reg[1]\: unisim.vcomponents.FDSE
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0\,
D => \OTHER_RATIO_GENERATE.Shift_Reg[1]_i_1_n_0\,
Q => \OTHER_RATIO_GENERATE.Shift_Reg_reg_n_0_[1]\,
S => Rst_to_spi
);
\OTHER_RATIO_GENERATE.Shift_Reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0\,
D => \OTHER_RATIO_GENERATE.Shift_Reg[2]_i_1_n_0\,
Q => \OTHER_RATIO_GENERATE.Shift_Reg_reg_n_0_[2]\,
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.Shift_Reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0\,
D => \OTHER_RATIO_GENERATE.Shift_Reg[3]_i_1_n_0\,
Q => \OTHER_RATIO_GENERATE.Shift_Reg_reg_n_0_[3]\,
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.Shift_Reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0\,
D => \OTHER_RATIO_GENERATE.Shift_Reg[4]_i_1_n_0\,
Q => \OTHER_RATIO_GENERATE.Shift_Reg_reg_n_0_[4]\,
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.Shift_Reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0\,
D => \OTHER_RATIO_GENERATE.Shift_Reg[5]_i_1_n_0\,
Q => \OTHER_RATIO_GENERATE.Shift_Reg_reg_n_0_[5]\,
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.Shift_Reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0\,
D => \OTHER_RATIO_GENERATE.Shift_Reg[6]_i_1_n_0\,
Q => \OTHER_RATIO_GENERATE.Shift_Reg_reg_n_0_[6]\,
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.Shift_Reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0\,
D => \goreg_dm.dout_i_reg[7]\(0),
Q => \OTHER_RATIO_GENERATE.Shift_Reg_reg_n_0_[7]\,
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0011[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => sck_d1,
I1 => \^transfer_start_d1_reg_0\,
I2 => sck_d2,
O => p_20_out
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0011_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => p_20_out,
D => rx_shft_reg_mode_0011(1),
Q => rx_shft_reg_mode_0011(0),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0011_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => p_20_out,
D => rx_shft_reg_mode_0011(2),
Q => rx_shft_reg_mode_0011(1),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0011_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => p_20_out,
D => rx_shft_reg_mode_0011(3),
Q => rx_shft_reg_mode_0011(2),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0011_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => p_20_out,
D => rx_shft_reg_mode_0011(4),
Q => rx_shft_reg_mode_0011(3),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0011_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => p_20_out,
D => rx_shft_reg_mode_0011(5),
Q => rx_shft_reg_mode_0011(4),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0011_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => p_20_out,
D => rx_shft_reg_mode_0011(6),
Q => rx_shft_reg_mode_0011(5),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0011_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => p_20_out,
D => rx_shft_reg_mode_0011(7),
Q => rx_shft_reg_mode_0011(6),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0011_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => p_20_out,
D => D(0),
Q => rx_shft_reg_mode_0011(7),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0110[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => sck_d2,
I1 => \^transfer_start_d1_reg_0\,
I2 => sck_d1,
O => p_18_out
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0110_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => p_18_out,
D => rx_shft_reg_mode_0110(1),
Q => rx_shft_reg_mode_0110(0),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0110_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => p_18_out,
D => rx_shft_reg_mode_0110(2),
Q => rx_shft_reg_mode_0110(1),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0110_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => p_18_out,
D => rx_shft_reg_mode_0110(3),
Q => rx_shft_reg_mode_0110(2),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0110_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => p_18_out,
D => rx_shft_reg_mode_0110(4),
Q => rx_shft_reg_mode_0110(3),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0110_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => p_18_out,
D => rx_shft_reg_mode_0110(5),
Q => rx_shft_reg_mode_0110(4),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0110_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => p_18_out,
D => rx_shft_reg_mode_0110(6),
Q => rx_shft_reg_mode_0110(5),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0110_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => p_18_out,
D => rx_shft_reg_mode_0110(7),
Q => rx_shft_reg_mode_0110(6),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0110_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => p_18_out,
D => D(0),
Q => rx_shft_reg_mode_0110(7),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_s[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000204"
)
port map (
I0 => sck_i_d1,
I1 => SCK_I_sync,
I2 => \^spisel_sync\,
I3 => \LOGIC_GENERATION_FDR.SPICR_4_CPHA_AX2S_2\,
I4 => \OTHER_RATIO_GENERATE.Serial_Dout_i_3_n_0\,
I5 => p_6_out,
O => \OTHER_RATIO_GENERATE.rx_shft_reg_s[0]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.rx_shft_reg_s_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.rx_shft_reg_s[0]_i_1_n_0\,
D => rx_shft_reg_s(1),
Q => rx_shft_reg_s(0),
R => '0'
);
\OTHER_RATIO_GENERATE.rx_shft_reg_s_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.rx_shft_reg_s[0]_i_1_n_0\,
D => rx_shft_reg_s(2),
Q => rx_shft_reg_s(1),
R => '0'
);
\OTHER_RATIO_GENERATE.rx_shft_reg_s_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.rx_shft_reg_s[0]_i_1_n_0\,
D => rx_shft_reg_s(3),
Q => rx_shft_reg_s(2),
R => '0'
);
\OTHER_RATIO_GENERATE.rx_shft_reg_s_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.rx_shft_reg_s[0]_i_1_n_0\,
D => rx_shft_reg_s(4),
Q => rx_shft_reg_s(3),
R => '0'
);
\OTHER_RATIO_GENERATE.rx_shft_reg_s_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.rx_shft_reg_s[0]_i_1_n_0\,
D => rx_shft_reg_s(5),
Q => rx_shft_reg_s(4),
R => '0'
);
\OTHER_RATIO_GENERATE.rx_shft_reg_s_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.rx_shft_reg_s[0]_i_1_n_0\,
D => rx_shft_reg_s(6),
Q => rx_shft_reg_s(5),
R => '0'
);
\OTHER_RATIO_GENERATE.rx_shft_reg_s_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.rx_shft_reg_s[0]_i_1_n_0\,
D => rx_shft_reg_s(7),
Q => rx_shft_reg_s(6),
R => '0'
);
\OTHER_RATIO_GENERATE.rx_shft_reg_s_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.rx_shft_reg_s[0]_i_1_n_0\,
D => D(0),
Q => rx_shft_reg_s(7),
R => '0'
);
\OTHER_RATIO_GENERATE.sck_d1_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => sck_o_int,
Q => sck_d1,
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.sck_d2_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => sck_d1,
Q => sck_d2,
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.sck_o_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FF6A006A"
)
port map (
I0 => sck_o_int,
I1 => \^transfer_start_d1_reg_0\,
I2 => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_4_n_0\,
I3 => \OTHER_RATIO_GENERATE.sck_o_int_i_2_n_0\,
I4 => \LOGIC_GENERATION_FDR.SPICR_4_CPHA_AX2S_2\,
I5 => RESET_SYNC_AX2S_2_2,
O => \OTHER_RATIO_GENERATE.sck_o_int_i_1_n_0\
);
\OTHER_RATIO_GENERATE.sck_o_int_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \^spixfer_done_int_d1_reg_0\,
I1 => transfer_start_d1,
I2 => \^transfer_start_d1_reg_0\,
O => \OTHER_RATIO_GENERATE.sck_o_int_i_2_n_0\
);
\OTHER_RATIO_GENERATE.sck_o_int_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \OTHER_RATIO_GENERATE.sck_o_int_i_1_n_0\,
Q => sck_o_int,
R => '0'
);
\OTHER_RATIO_GENERATE.serial_dout_int_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^io0_o\,
I1 => spicr_0_loop_to_spi_clk,
I2 => Rst_to_spi,
O => \OTHER_RATIO_GENERATE.serial_dout_int_i_1_n_0\
);
\OTHER_RATIO_GENERATE.serial_dout_int_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \OTHER_RATIO_GENERATE.serial_dout_int_i_1_n_0\,
Q => serial_dout_int,
R => '0'
);
\RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST_i_2_n_0\,
Q => sck_o,
R => R
);
\RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"BAAA8AAA"
)
port map (
I0 => spicr_3_cpol_to_spi_clk,
I1 => load,
I2 => transfer_start_d1,
I3 => \^transfer_start_d1_reg_0\,
I4 => sck_o_int,
O => \RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST_i_2_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000E000E0E"
)
port map (
I0 => \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_2_n_0\,
I1 => \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_3_n_0\,
I2 => \^spixfer_done_int_d1_reg_0\,
I3 => transfer_start_d1,
I4 => \^transfer_start_d1_reg_0\,
I5 => Rst_to_spi,
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_1_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_3_n_0\,
I1 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[1]\,
I2 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[2]\,
I3 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[3]\,
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_2_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"4040404000404000"
)
port map (
I0 => \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_4_n_0\,
I1 => SPICR_2_MST_N_SLV_to_spi_clk,
I2 => \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_5_n_0\,
I3 => spicr_4_cpha_to_spi_clk,
I4 => spicr_3_cpol_to_spi_clk,
I5 => Count_trigger,
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_3_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => Ratio_Count(0),
I1 => Ratio_Count(1),
I2 => Ratio_Count(2),
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_4_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[1]\,
I1 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[0]\,
I2 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[3]\,
I3 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[2]\,
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_5_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_1_n_0\,
Q => \^spixfer_done_int_d1_reg_0\,
R => '0'
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F305F5F3F305050"
)
port map (
I0 => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_2_n_0\,
I1 => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_3_n_0\,
I2 => SPICR_2_MST_N_SLV_to_spi_clk,
I3 => rx_shft_reg_s(7),
I4 => spicr_9_lsb_to_spi_clk,
I5 => rx_shft_reg_s(0),
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"14D7"
)
port map (
I0 => rx_shft_reg_mode_0110(0),
I1 => spicr_4_cpha_to_spi_clk,
I2 => spicr_3_cpol_to_spi_clk,
I3 => rx_shft_reg_mode_0011(0),
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_2_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"14D7"
)
port map (
I0 => rx_shft_reg_mode_0110(7),
I1 => spicr_4_cpha_to_spi_clk,
I2 => spicr_3_cpol_to_spi_clk,
I3 => rx_shft_reg_mode_0011(7),
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_3_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F305F5F3F305050"
)
port map (
I0 => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[1]_i_2_n_0\,
I1 => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[1]_i_3_n_0\,
I2 => SPICR_2_MST_N_SLV_to_spi_clk,
I3 => rx_shft_reg_s(6),
I4 => spicr_9_lsb_to_spi_clk,
I5 => rx_shft_reg_s(1),
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[1]_i_1_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"14D7"
)
port map (
I0 => rx_shft_reg_mode_0110(1),
I1 => spicr_4_cpha_to_spi_clk,
I2 => spicr_3_cpol_to_spi_clk,
I3 => rx_shft_reg_mode_0011(1),
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[1]_i_2_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[1]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"14D7"
)
port map (
I0 => rx_shft_reg_mode_0110(6),
I1 => spicr_4_cpha_to_spi_clk,
I2 => spicr_3_cpol_to_spi_clk,
I3 => rx_shft_reg_mode_0011(6),
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[1]_i_3_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F305F5F3F305050"
)
port map (
I0 => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[2]_i_2_n_0\,
I1 => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[2]_i_3_n_0\,
I2 => SPICR_2_MST_N_SLV_to_spi_clk,
I3 => rx_shft_reg_s(5),
I4 => spicr_9_lsb_to_spi_clk,
I5 => rx_shft_reg_s(2),
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[2]_i_1_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"14D7"
)
port map (
I0 => rx_shft_reg_mode_0110(2),
I1 => spicr_4_cpha_to_spi_clk,
I2 => spicr_3_cpol_to_spi_clk,
I3 => rx_shft_reg_mode_0011(2),
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[2]_i_2_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[2]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"14D7"
)
port map (
I0 => rx_shft_reg_mode_0110(5),
I1 => spicr_4_cpha_to_spi_clk,
I2 => spicr_3_cpol_to_spi_clk,
I3 => rx_shft_reg_mode_0011(5),
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[2]_i_3_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5F503F3F5F503030"
)
port map (
I0 => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[3]_i_2_n_0\,
I1 => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[3]_i_3_n_0\,
I2 => SPICR_2_MST_N_SLV_to_spi_clk,
I3 => rx_shft_reg_s(4),
I4 => spicr_9_lsb_to_spi_clk,
I5 => rx_shft_reg_s(3),
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[3]_i_1_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"14D7"
)
port map (
I0 => rx_shft_reg_mode_0110(4),
I1 => spicr_4_cpha_to_spi_clk,
I2 => spicr_3_cpol_to_spi_clk,
I3 => rx_shft_reg_mode_0011(4),
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[3]_i_2_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"14D7"
)
port map (
I0 => rx_shft_reg_mode_0110(3),
I1 => spicr_4_cpha_to_spi_clk,
I2 => spicr_3_cpol_to_spi_clk,
I3 => rx_shft_reg_mode_0011(3),
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[3]_i_3_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5F503F3F5F503030"
)
port map (
I0 => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[3]_i_3_n_0\,
I1 => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[3]_i_2_n_0\,
I2 => SPICR_2_MST_N_SLV_to_spi_clk,
I3 => rx_shft_reg_s(3),
I4 => spicr_9_lsb_to_spi_clk,
I5 => rx_shft_reg_s(4),
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[4]_i_1_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5F503F3F5F503030"
)
port map (
I0 => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[2]_i_2_n_0\,
I1 => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[2]_i_3_n_0\,
I2 => SPICR_2_MST_N_SLV_to_spi_clk,
I3 => rx_shft_reg_s(2),
I4 => spicr_9_lsb_to_spi_clk,
I5 => rx_shft_reg_s(5),
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[5]_i_1_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F305F5F3F305050"
)
port map (
I0 => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[1]_i_3_n_0\,
I1 => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[1]_i_2_n_0\,
I2 => SPICR_2_MST_N_SLV_to_spi_clk,
I3 => rx_shft_reg_s(1),
I4 => spicr_9_lsb_to_spi_clk,
I5 => rx_shft_reg_s(6),
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[6]_i_1_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F305F5F3F305050"
)
port map (
I0 => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_3_n_0\,
I1 => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_2_n_0\,
I2 => SPICR_2_MST_N_SLV_to_spi_clk,
I3 => rx_shft_reg_s(0),
I4 => spicr_9_lsb_to_spi_clk,
I5 => rx_shft_reg_s(7),
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[7]_i_1_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d1,
D => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1_n_0\,
Q => \gpr1.dout_i_reg[7]\(7),
R => '0'
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d1,
D => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[1]_i_1_n_0\,
Q => \gpr1.dout_i_reg[7]\(6),
R => '0'
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d1,
D => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[2]_i_1_n_0\,
Q => \gpr1.dout_i_reg[7]\(5),
R => '0'
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d1,
D => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[3]_i_1_n_0\,
Q => \gpr1.dout_i_reg[7]\(4),
R => '0'
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d1,
D => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[4]_i_1_n_0\,
Q => \gpr1.dout_i_reg[7]\(3),
R => '0'
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d1,
D => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[5]_i_1_n_0\,
Q => \gpr1.dout_i_reg[7]\(2),
R => '0'
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d1,
D => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[6]_i_1_n_0\,
Q => \gpr1.dout_i_reg[7]\(1),
R => '0'
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d1,
D => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[7]_i_1_n_0\,
Q => \gpr1.dout_i_reg[7]\(0),
R => '0'
);
SCK_I_REG: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => sck_i,
Q => SCK_I_sync,
R => '0'
);
SPISEL_REG: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spisel,
Q => \^spisel_sync\,
R => '0'
);
SPIXfer_done_int_d1_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \^spixfer_done_int_d1_reg_0\,
Q => SPIXfer_done_int_d1,
R => Rst_to_spi
);
SPIXfer_done_int_pulse_d1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^spixfer_done_int_d1_reg_0\,
I1 => SPIXfer_done_int_d1,
O => SPIXfer_done_int_pulse
);
SPIXfer_done_int_pulse_d1_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => SPIXfer_done_int_pulse,
Q => SPIXfer_done_int_pulse_d1,
R => Rst_to_spi
);
SPIXfer_done_int_pulse_d2_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => SPIXfer_done_int_pulse_d1,
Q => \^spixfer_done_int\,
R => Rst_to_spi
);
SPI_TRISTATE_CONTROL_II: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => D_0,
Q => sck_t,
R => '0'
);
SPI_TRISTATE_CONTROL_III: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => D_0,
Q => io0_t,
R => '0'
);
SPI_TRISTATE_CONTROL_IV: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => D_0,
Q => ss_t,
R => '0'
);
SPI_TRISTATE_CONTROL_V: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_2\,
Q => io1_t,
R => '0'
);
SR_5_Tx_Empty_d1_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \out\,
Q => SR_5_Tx_Empty_d1,
R => Rst_to_spi
);
SR_5_Tx_comeplete_Empty_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"BA00"
)
port map (
I0 => \^sr_5_tx_comeplete_empty\,
I1 => SPIXfer_done_int_d1,
I2 => \^spixfer_done_int_d1_reg_0\,
I3 => \out\,
O => SR_5_Tx_comeplete_Empty_i_1_n_0
);
SR_5_Tx_comeplete_Empty_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => SR_5_Tx_comeplete_Empty_i_1_n_0,
Q => \^sr_5_tx_comeplete_empty\,
R => '0'
);
\SS_O_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_SYNC_AXI_2_SPI_2\,
Q => ss_o(0),
R => '0'
);
Slave_MODF_strobe_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => Slave_MODF_strobe0,
Q => slave_MODF_strobe_int,
R => RESET_SYNC_AX2S_2
);
\gc1.count_d1[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF4040FF40"
)
port map (
I0 => spisel_d1,
I1 => \^spisel_d1_reg\,
I2 => spisel_once_1,
I3 => \^transfer_start_d1_reg_0\,
I4 => transfer_start_d1,
I5 => \^spixfer_done_int\,
O => empty_fwft_fb_o_i_reg
);
\gic0.gc1.count_d1[3]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^spixfer_done_int\,
I1 => ram_full_fb_i_reg,
O => E(0)
);
sck_i_d1_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => SCK_I_sync,
Q => sck_i_d1,
R => Rst_to_spi
);
\spisel_d1_reg__0\: unisim.vcomponents.FDSE
port map (
C => ext_spi_clk,
CE => '1',
D => \^spisel_sync\,
Q => spisel_d1,
S => Rst_to_spi
);
spisel_d2_reg: unisim.vcomponents.FDSE
port map (
C => ext_spi_clk,
CE => '1',
D => spisel_d1,
Q => \^spisel_d1_reg\,
S => Rst_to_spi
);
spisel_once_1_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => spisel_once_1,
I1 => spisel_d1,
I2 => \^spisel_d1_reg\,
O => spisel_once_1_i_1_n_0
);
spisel_once_1_reg: unisim.vcomponents.FDSE
port map (
C => ext_spi_clk,
CE => '1',
D => spisel_once_1_i_1_n_0,
Q => spisel_once_1,
S => Rst_to_spi
);
transfer_start_d1_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \^transfer_start_d1_reg_0\,
Q => transfer_start_d1,
R => Rst_to_spi
);
transfer_start_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => RESET_SYNC_AX2S_2_0,
Q => \^transfer_start_d1_reg_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_qspi_status_slave_sel_reg is
port (
sr_3_MODF_int : out STD_LOGIC;
SPISSR_frm_axi_clk : out STD_LOGIC;
modf_reg_0 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
reset2ip_reset_int : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[28].ce_out_i_reg[28]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_qspi_status_slave_sel_reg : entity is "qspi_status_slave_sel_reg";
end system_axi_quad_spi_shield_0_qspi_status_slave_sel_reg;
architecture STRUCTURE of system_axi_quad_spi_shield_0_qspi_status_slave_sel_reg is
begin
\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[28].ce_out_i_reg[28]\,
Q => SPISSR_frm_axi_clk,
S => reset2ip_reset_int
);
modf_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => modf_reg_0,
Q => sr_3_MODF_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_reset_sync_module is
port (
Allow_MODF_Strobe_reg : out STD_LOGIC;
Rst_to_spi : out STD_LOGIC;
p_6_out : out STD_LOGIC;
\DTR_UNDERRUN_FIFO_EXIST_GEN.DTR_underrun_reg\ : out STD_LOGIC;
\OTHER_RATIO_GENERATE.sck_o_int_reg\ : out STD_LOGIC;
SPISEL_sync : in STD_LOGIC;
transfer_start_reg : in STD_LOGIC;
SPICR_2_MST_N_SLV_to_spi_clk : in STD_LOGIC;
reset2ip_reset_int : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_reset_sync_module : entity is "reset_sync_module";
end system_axi_quad_spi_shield_0_reset_sync_module;
architecture STRUCTURE of system_axi_quad_spi_shield_0_reset_sync_module is
signal \^rst_to_spi\ : STD_LOGIC;
signal Soft_Reset_frm_axi_d1 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \DTR_UNDERRUN_FIFO_EXIST_GEN.DTR_underrun_i_2\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \OTHER_RATIO_GENERATE.rx_shft_reg_s[0]_i_3\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \OTHER_RATIO_GENERATE.sck_o_int_i_3\ : label is "soft_lutpair45";
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of RESET_SYNC_AX2S_1 : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of RESET_SYNC_AX2S_1 : label is "FDR";
attribute box_type : string;
attribute box_type of RESET_SYNC_AX2S_1 : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of RESET_SYNC_AX2S_2 : label is "FDR";
attribute box_type of RESET_SYNC_AX2S_2 : label is "PRIMITIVE";
attribute SOFT_HLUTNM of Slave_MODF_strobe_i_1 : label is "soft_lutpair44";
begin
Rst_to_spi <= \^rst_to_spi\;
\DTR_UNDERRUN_FIFO_EXIST_GEN.DTR_underrun_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^rst_to_spi\,
I1 => SPICR_2_MST_N_SLV_to_spi_clk,
O => \DTR_UNDERRUN_FIFO_EXIST_GEN.DTR_underrun_reg\
);
\OTHER_RATIO_GENERATE.rx_shft_reg_s[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^rst_to_spi\,
I1 => transfer_start_reg,
O => p_6_out
);
\OTHER_RATIO_GENERATE.sck_o_int_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^rst_to_spi\,
I1 => SPICR_2_MST_N_SLV_to_spi_clk,
O => \OTHER_RATIO_GENERATE.sck_o_int_reg\
);
RESET_SYNC_AX2S_1: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => reset2ip_reset_int,
Q => Soft_Reset_frm_axi_d1,
R => '0'
);
RESET_SYNC_AX2S_2: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => Soft_Reset_frm_axi_d1,
Q => \^rst_to_spi\,
R => '0'
);
Slave_MODF_strobe_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^rst_to_spi\,
I1 => SPISEL_sync,
O => Allow_MODF_Strobe_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_soft_reset is
port (
sw_rst_cond_d1 : out STD_LOGIC;
wrack : out STD_LOGIC;
\icount_out_reg[0]\ : out STD_LOGIC;
\icount_out_reg[0]_0\ : out STD_LOGIC;
reset2ip_reset_int : out STD_LOGIC;
bus2ip_reset_ipif_inverted : in STD_LOGIC;
sw_rst_cond : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
reset_trig0 : in STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_soft_reset : entity is "soft_reset";
end system_axi_quad_spi_shield_0_soft_reset;
architecture STRUCTURE of system_axi_quad_spi_shield_0_soft_reset is
signal FF_WRACK_i_1_n_0 : STD_LOGIC;
signal \RESET_FLOPS[10].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[11].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[12].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[13].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[14].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[15].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[1].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[2].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[3].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[4].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[5].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[6].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[7].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[8].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[9].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal S : STD_LOGIC;
signal flop_q_chain : STD_LOGIC_VECTOR ( 1 to 15 );
signal \^icount_out_reg[0]\ : STD_LOGIC;
attribute IS_CE_INVERTED : string;
attribute IS_CE_INVERTED of FF_WRACK : label is "1'b0";
attribute IS_S_INVERTED : string;
attribute IS_S_INVERTED of FF_WRACK : label is "1'b0";
attribute box_type : string;
attribute box_type of FF_WRACK : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of FF_WRACK_i_1 : label is "soft_lutpair47";
attribute IS_CE_INVERTED of \RESET_FLOPS[0].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[0].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[0].RST_FLOPS\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \RESET_FLOPS[10].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[10].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[10].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[10].RST_FLOPS_i_1\ : label is "soft_lutpair52";
attribute IS_CE_INVERTED of \RESET_FLOPS[11].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[11].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[11].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[11].RST_FLOPS_i_1\ : label is "soft_lutpair53";
attribute IS_CE_INVERTED of \RESET_FLOPS[12].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[12].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[12].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[12].RST_FLOPS_i_1\ : label is "soft_lutpair53";
attribute IS_CE_INVERTED of \RESET_FLOPS[13].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[13].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[13].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[13].RST_FLOPS_i_1\ : label is "soft_lutpair54";
attribute IS_CE_INVERTED of \RESET_FLOPS[14].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[14].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[14].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[14].RST_FLOPS_i_1\ : label is "soft_lutpair54";
attribute IS_CE_INVERTED of \RESET_FLOPS[15].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[15].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[15].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[15].RST_FLOPS_i_1\ : label is "soft_lutpair47";
attribute IS_CE_INVERTED of \RESET_FLOPS[1].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[1].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[1].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[1].RST_FLOPS_i_1\ : label is "soft_lutpair48";
attribute IS_CE_INVERTED of \RESET_FLOPS[2].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[2].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[2].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[2].RST_FLOPS_i_1\ : label is "soft_lutpair48";
attribute IS_CE_INVERTED of \RESET_FLOPS[3].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[3].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[3].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[3].RST_FLOPS_i_1\ : label is "soft_lutpair49";
attribute IS_CE_INVERTED of \RESET_FLOPS[4].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[4].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[4].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[4].RST_FLOPS_i_1\ : label is "soft_lutpair49";
attribute IS_CE_INVERTED of \RESET_FLOPS[5].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[5].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[5].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[5].RST_FLOPS_i_1\ : label is "soft_lutpair50";
attribute IS_CE_INVERTED of \RESET_FLOPS[6].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[6].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[6].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[6].RST_FLOPS_i_1\ : label is "soft_lutpair50";
attribute IS_CE_INVERTED of \RESET_FLOPS[7].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[7].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[7].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[7].RST_FLOPS_i_1\ : label is "soft_lutpair51";
attribute IS_CE_INVERTED of \RESET_FLOPS[8].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[8].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[8].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[8].RST_FLOPS_i_1\ : label is "soft_lutpair51";
attribute IS_CE_INVERTED of \RESET_FLOPS[9].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[9].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[9].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[9].RST_FLOPS_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of RESET_SYNC_AX2S_1_i_1 : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \icount_out[0]_i_1__0\ : label is "soft_lutpair46";
begin
\icount_out_reg[0]\ <= \^icount_out_reg[0]\;
FF_WRACK: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => FF_WRACK_i_1_n_0,
Q => wrack,
R => bus2ip_reset_ipif_inverted
);
FF_WRACK_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^icount_out_reg[0]\,
I1 => flop_q_chain(15),
O => FF_WRACK_i_1_n_0
);
\RESET_FLOPS[0].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => S,
Q => flop_q_chain(1),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[10].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[10].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(11),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[10].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(10),
O => \RESET_FLOPS[10].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[11].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[11].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(12),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[11].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(11),
O => \RESET_FLOPS[11].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[12].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[12].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(13),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[12].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(12),
O => \RESET_FLOPS[12].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[13].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[13].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(14),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[13].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(13),
O => \RESET_FLOPS[13].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[14].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[14].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(15),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[14].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(14),
O => \RESET_FLOPS[14].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[15].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[15].RST_FLOPS_i_1_n_0\,
Q => \^icount_out_reg[0]\,
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[15].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(15),
O => \RESET_FLOPS[15].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[1].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[1].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(2),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[1].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(1),
O => \RESET_FLOPS[1].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[2].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[2].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(3),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[2].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(2),
O => \RESET_FLOPS[2].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[3].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[3].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(4),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[3].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(3),
O => \RESET_FLOPS[3].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[4].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[4].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(5),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[4].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(4),
O => \RESET_FLOPS[4].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[5].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[5].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(6),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[5].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(5),
O => \RESET_FLOPS[5].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[6].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[6].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(7),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[6].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(6),
O => \RESET_FLOPS[6].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[7].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[7].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(8),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[7].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(7),
O => \RESET_FLOPS[7].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[8].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[8].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(9),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[8].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(8),
O => \RESET_FLOPS[8].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[9].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[9].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(10),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[9].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(9),
O => \RESET_FLOPS[9].RST_FLOPS_i_1_n_0\
);
RESET_SYNC_AX2S_1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^icount_out_reg[0]\,
I1 => bus2ip_reset_ipif_inverted,
O => reset2ip_reset_int
);
\icount_out[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FEFF"
)
port map (
I0 => \^icount_out_reg[0]\,
I1 => bus2ip_reset_ipif_inverted,
I2 => \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\,
I3 => D(0),
O => \icount_out_reg[0]_0\
);
reset_trig_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => reset_trig0,
Q => S,
R => bus2ip_reset_ipif_inverted
);
sw_rst_cond_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => sw_rst_cond,
Q => sw_rst_cond_d1,
R => bus2ip_reset_ipif_inverted
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_dmem is
port (
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
I93 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gc1.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
L : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ext_spi_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_dmem : entity is "dmem";
end system_axi_quad_spi_shield_0_dmem;
architecture STRUCTURE of system_axi_quad_spi_shield_0_dmem is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal RAM_reg_0_15_6_7_n_0 : STD_LOGIC;
signal RAM_reg_0_15_6_7_n_1 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_7_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_7_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_7_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_6_7 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc1.count_d2_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc1.count_d2_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc1.count_d2_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => L(3 downto 0),
DIA(1 downto 0) => s_axi_wdata(1 downto 0),
DIB(1 downto 0) => s_axi_wdata(3 downto 2),
DIC(1 downto 0) => s_axi_wdata(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => s_axi_aclk,
WE => I93
);
RAM_reg_0_15_6_7: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc1.count_d2_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc1.count_d2_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc1.count_d2_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => L(3 downto 0),
DIA(1 downto 0) => s_axi_wdata(7 downto 6),
DIB(1 downto 0) => B"00",
DIC(1 downto 0) => B"00",
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_6_7_n_0,
DOA(0) => RAM_reg_0_15_6_7_n_1,
DOB(1 downto 0) => NLW_RAM_reg_0_15_6_7_DOB_UNCONNECTED(1 downto 0),
DOC(1 downto 0) => NLW_RAM_reg_0_15_6_7_DOC_UNCONNECTED(1 downto 0),
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_7_DOD_UNCONNECTED(1 downto 0),
WCLK => s_axi_aclk,
WE => I93
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_1,
Q => Q(0)
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_0,
Q => Q(1)
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_3,
Q => Q(2)
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_2,
Q => Q(3)
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_5,
Q => Q(4)
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_4,
Q => Q(5)
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => RAM_reg_0_15_6_7_n_1,
Q => Q(6)
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => RAM_reg_0_15_6_7_n_0,
Q => Q(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_dmem_19 is
port (
\goreg_dm.dout_i_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
ext_spi_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gc1.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
L : in STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_dmem_19 : entity is "dmem";
end system_axi_quad_spi_shield_0_dmem_19;
architecture STRUCTURE of system_axi_quad_spi_shield_0_dmem_19 is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal RAM_reg_0_15_6_7_n_0 : STD_LOGIC;
signal RAM_reg_0_15_6_7_n_1 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_7_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_7_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_7_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_6_7 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc1.count_d2_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc1.count_d2_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc1.count_d2_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => L(3 downto 0),
DIA(1 downto 0) => Q(1 downto 0),
DIB(1 downto 0) => Q(3 downto 2),
DIC(1 downto 0) => Q(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => ext_spi_clk,
WE => E(0)
);
RAM_reg_0_15_6_7: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc1.count_d2_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc1.count_d2_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc1.count_d2_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => L(3 downto 0),
DIA(1 downto 0) => Q(7 downto 6),
DIB(1 downto 0) => B"00",
DIC(1 downto 0) => B"00",
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_6_7_n_0,
DOA(0) => RAM_reg_0_15_6_7_n_1,
DOB(1 downto 0) => NLW_RAM_reg_0_15_6_7_DOB_UNCONNECTED(1 downto 0),
DOC(1 downto 0) => NLW_RAM_reg_0_15_6_7_DOC_UNCONNECTED(1 downto 0),
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_7_DOD_UNCONNECTED(1 downto 0),
WCLK => ext_spi_clk,
WE => E(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_1,
Q => \goreg_dm.dout_i_reg[7]\(0)
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_0,
Q => \goreg_dm.dout_i_reg[7]\(1)
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_3,
Q => \goreg_dm.dout_i_reg[7]\(2)
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_2,
Q => \goreg_dm.dout_i_reg[7]\(3)
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_5,
Q => \goreg_dm.dout_i_reg[7]\(4)
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_4,
Q => \goreg_dm.dout_i_reg[7]\(5)
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_6_7_n_1,
Q => \goreg_dm.dout_i_reg[7]\(6)
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_6_7_n_0,
Q => \goreg_dm.dout_i_reg[7]\(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_rd_bin_cntr is
port (
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ext_spi_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_rd_bin_cntr : entity is "rd_bin_cntr";
end system_axi_quad_spi_shield_0_rd_bin_cntr;
architecture STRUCTURE of system_axi_quad_spi_shield_0_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ram_empty_i_i_4__0_n_0\ : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_pntr_plus2 : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc1.count[2]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \gc1.count[3]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[1]_i_1__0\ : label is "soft_lutpair29";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gc1.count[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rd_pntr_plus2(0),
O => \plusOp__3\(0)
);
\gc1.count[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rd_pntr_plus2(0),
I1 => rd_pntr_plus2(1),
O => \plusOp__3\(1)
);
\gc1.count[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => rd_pntr_plus2(2),
I1 => rd_pntr_plus2(1),
I2 => rd_pntr_plus2(0),
O => \plusOp__3\(2)
);
\gc1.count[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => rd_pntr_plus2(3),
I1 => rd_pntr_plus2(0),
I2 => rd_pntr_plus2(1),
I3 => rd_pntr_plus2(2),
O => \plusOp__3\(3)
);
\gc1.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => E(0),
D => rd_pntr_plus2(0),
PRE => AR(0),
Q => rd_pntr_plus1(0)
);
\gc1.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus2(1),
Q => rd_pntr_plus1(1)
);
\gc1.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus2(2),
Q => rd_pntr_plus1(2)
);
\gc1.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus2(3),
Q => rd_pntr_plus1(3)
);
\gc1.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus1(0),
Q => \^q\(0)
);
\gc1.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus1(1),
Q => \^q\(1)
);
\gc1.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus1(2),
Q => \^q\(2)
);
\gc1.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus1(3),
Q => \^q\(3)
);
\gc1.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__3\(0),
Q => rd_pntr_plus2(0)
);
\gc1.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => E(0),
D => \plusOp__3\(1),
PRE => AR(0),
Q => rd_pntr_plus2(1)
);
\gc1.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__3\(2),
Q => rd_pntr_plus2(2)
);
\gc1.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__3\(3),
Q => rd_pntr_plus2(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
O => D(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(1),
I1 => \^q\(2),
O => D(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(2),
I1 => \^q\(3),
O => D(2)
);
\ram_empty_i_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF6FF6"
)
port map (
I0 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(2),
I1 => rd_pntr_plus1(2),
I2 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
I3 => rd_pntr_plus1(3),
I4 => \ram_empty_i_i_4__0_n_0\,
O => ram_empty_i_reg
);
\ram_empty_i_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => rd_pntr_plus1(1),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(1),
I2 => rd_pntr_plus1(0),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
O => \ram_empty_i_i_4__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_rd_bin_cntr_24 is
port (
ram_empty_i0 : out STD_LOGIC;
\gnxpm_cdc.rd_pntr_gc_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc1.count_d2_reg[3]_0\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_rd_bin_cntr_24 : entity is "rd_bin_cntr";
end system_axi_quad_spi_shield_0_rd_bin_cntr_24;
architecture STRUCTURE of system_axi_quad_spi_shield_0_rd_bin_cntr_24 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_empty_i_i_2_n_0 : STD_LOGIC;
signal ram_empty_i_i_4_n_0 : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_pntr_plus2 : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc1.count[2]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \gc1.count[3]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[1]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1\ : label is "soft_lutpair23";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gc1.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rd_pntr_plus2(0),
O => \plusOp__0\(0)
);
\gc1.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rd_pntr_plus2(0),
I1 => rd_pntr_plus2(1),
O => \plusOp__0\(1)
);
\gc1.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => rd_pntr_plus2(2),
I1 => rd_pntr_plus2(1),
I2 => rd_pntr_plus2(0),
O => \plusOp__0\(2)
);
\gc1.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => rd_pntr_plus2(3),
I1 => rd_pntr_plus2(0),
I2 => rd_pntr_plus2(1),
I3 => rd_pntr_plus2(2),
O => \plusOp__0\(3)
);
\gc1.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => rd_pntr_plus2(0),
PRE => AR(0),
Q => rd_pntr_plus1(0)
);
\gc1.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus2(1),
Q => rd_pntr_plus1(1)
);
\gc1.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus2(2),
Q => rd_pntr_plus1(2)
);
\gc1.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus2(3),
Q => rd_pntr_plus1(3)
);
\gc1.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus1(0),
Q => \^q\(0)
);
\gc1.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus1(1),
Q => \^q\(1)
);
\gc1.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus1(2),
Q => \^q\(2)
);
\gc1.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus1(3),
Q => \^q\(3)
);
\gc1.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(0),
Q => rd_pntr_plus2(0)
);
\gc1.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \plusOp__0\(1),
PRE => AR(0),
Q => rd_pntr_plus2(1)
);
\gc1.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => rd_pntr_plus2(2)
);
\gc1.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => rd_pntr_plus2(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(2),
I1 => \^q\(1),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(3),
I1 => \^q\(2),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(2)
);
ram_empty_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => ram_empty_i_i_2_n_0,
I1 => E(0),
I2 => \gc1.count_d2_reg[3]_0\,
O => ram_empty_i0
);
ram_empty_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF6FF6"
)
port map (
I0 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I1 => rd_pntr_plus1(0),
I2 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
I3 => rd_pntr_plus1(3),
I4 => ram_empty_i_i_4_n_0,
O => ram_empty_i_i_2_n_0
);
ram_empty_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => rd_pntr_plus1(2),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(2),
I2 => rd_pntr_plus1(1),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(1),
O => ram_empty_i_i_4_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_rd_fwft is
port (
\out\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_i0 : out STD_LOGIC;
\goreg_dm.dout_i_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
ext_spi_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : in STD_LOGIC;
\spisel_d1_reg__0\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gc1.count_d2_reg[2]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_rd_fwft : entity is "rd_fwft";
end system_axi_quad_spi_shield_0_rd_fwft;
architecture STRUCTURE of system_axi_quad_spi_shield_0_rd_fwft is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal \gpregsm1.curr_fwft_state[1]_i_1__0_n_0\ : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
\out\ <= empty_fwft_i;
\aempty_fwft_fb_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"EA8AA88A"
)
port map (
I0 => aempty_fwft_fb_i,
I1 => ram_empty_fb_i_reg,
I2 => curr_fwft_state(1),
I3 => curr_fwft_state(0),
I4 => \spisel_d1_reg__0\,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => aempty_fwft_i0,
PRE => AR(0),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => aempty_fwft_i0,
PRE => AR(0),
Q => aempty_fwft_i
);
\empty_fwft_fb_i_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F320"
)
port map (
I0 => \spisel_d1_reg__0\,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => empty_fwft_fb_i,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => empty_fwft_i0,
PRE => AR(0),
Q => empty_fwft_fb_i
);
\empty_fwft_fb_o_i_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F320"
)
port map (
I0 => \spisel_d1_reg__0\,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => empty_fwft_fb_o_i,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => AR(0),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => empty_fwft_i0,
PRE => AR(0),
Q => empty_fwft_i
);
\gc1.count_d1[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"4555"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => \spisel_d1_reg__0\,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
O => E(0)
);
\goreg_dm.dout_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => curr_fwft_state(1),
I1 => \spisel_d1_reg__0\,
I2 => curr_fwft_state(0),
O => \goreg_dm.dout_i_reg[7]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => curr_fwft_state(1),
I1 => \spisel_d1_reg__0\,
I2 => curr_fwft_state(0),
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"40FF"
)
port map (
I0 => \spisel_d1_reg__0\,
I1 => curr_fwft_state(0),
I2 => curr_fwft_state(1),
I3 => ram_empty_fb_i_reg,
O => \gpregsm1.curr_fwft_state[1]_i_1__0_n_0\
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => \gpregsm1.curr_fwft_state[1]_i_1__0_n_0\,
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => next_fwft_state(0),
Q => user_valid
);
\ram_empty_i_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00004555"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => \spisel_d1_reg__0\,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
I5 => \gc1.count_d2_reg[2]\,
O => ram_empty_i0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_rd_fwft_22 is
port (
\out\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\icount_out_reg[3]\ : out STD_LOGIC;
Receive_ip2bus_error0 : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\ : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
p_5_in : in STD_LOGIC;
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_rd_fwft_22 : entity is "rd_fwft";
end system_axi_quad_spi_shield_0_rd_fwft_22;
architecture STRUCTURE of system_axi_quad_spi_shield_0_rd_fwft_22 is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal \gpregsm1.curr_fwft_state[1]_i_1_n_0\ : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
\out\ <= empty_fwft_i;
Receive_ip2bus_error_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"E000"
)
port map (
I0 => \FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\,
I1 => empty_fwft_i,
I2 => p_5_in,
I3 => Bus_RNW_reg,
O => Receive_ip2bus_error0
);
aempty_fwft_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FF10F000F100FF00"
)
port map (
I0 => empty_fwft_i,
I1 => \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\,
I2 => ram_empty_fb_i_reg,
I3 => aempty_fwft_fb_i,
I4 => curr_fwft_state(0),
I5 => curr_fwft_state(1),
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => AR(0),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => AR(0),
Q => aempty_fwft_i
);
empty_fwft_fb_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FF0F0100"
)
port map (
I0 => empty_fwft_i,
I1 => \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\,
I2 => curr_fwft_state(1),
I3 => curr_fwft_state(0),
I4 => empty_fwft_fb_i,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => AR(0),
Q => empty_fwft_fb_i
);
empty_fwft_fb_o_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FF0F0100"
)
port map (
I0 => empty_fwft_i,
I1 => \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\,
I2 => curr_fwft_state(1),
I3 => curr_fwft_state(0),
I4 => empty_fwft_fb_o_i,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => AR(0),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => AR(0),
Q => empty_fwft_i
);
\gc1.count_d1[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01555555"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => empty_fwft_i,
I2 => \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\,
I3 => curr_fwft_state(0),
I4 => curr_fwft_state(1),
O => E(0)
);
\goreg_dm.dout_i[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000AAAAAAAA"
)
port map (
I0 => curr_fwft_state(1),
I1 => empty_fwft_i,
I2 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\,
I3 => Bus_RNW_reg,
I4 => p_5_in,
I5 => curr_fwft_state(0),
O => \goreg_dm.dout_i_reg[7]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFAAAA2AAA"
)
port map (
I0 => curr_fwft_state(0),
I1 => p_5_in,
I2 => Bus_RNW_reg,
I3 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\,
I4 => empty_fwft_i,
I5 => curr_fwft_state(1),
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"E000FFFF"
)
port map (
I0 => empty_fwft_i,
I1 => \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => ram_empty_fb_i_reg,
O => \gpregsm1.curr_fwft_state[1]_i_1_n_0\
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \gpregsm1.curr_fwft_state[1]_i_1_n_0\,
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => next_fwft_state(0),
Q => user_valid
);
\icount_out[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => empty_fwft_i,
I1 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\,
I2 => Bus_RNW_reg,
I3 => p_5_in,
O => \icount_out_reg[3]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_rd_status_flags_as is
port (
\out\ : out STD_LOGIC;
ram_empty_i0 : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_rd_status_flags_as : entity is "rd_status_flags_as";
end system_axi_quad_spi_shield_0_rd_status_flags_as;
architecture STRUCTURE of system_axi_quad_spi_shield_0_rd_status_flags_as is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => ram_empty_i0,
PRE => AR(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => ram_empty_i0,
PRE => AR(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_rd_status_flags_as_23 is
port (
\out\ : out STD_LOGIC;
ram_empty_i0 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_rd_status_flags_as_23 : entity is "rd_status_flags_as";
end system_axi_quad_spi_shield_0_rd_status_flags_as_23;
architecture STRUCTURE of system_axi_quad_spi_shield_0_rd_status_flags_as_23 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => ram_empty_i0,
PRE => AR(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => ram_empty_i0,
PRE => AR(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
ext_spi_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_synchronizer_ff : entity is "synchronizer_ff";
end system_axi_quad_spi_shield_0_synchronizer_ff;
architecture STRUCTURE of system_axi_quad_spi_shield_0_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_synchronizer_ff_15 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_synchronizer_ff_15 : entity is "synchronizer_ff";
end system_axi_quad_spi_shield_0_synchronizer_ff_15;
architecture STRUCTURE of system_axi_quad_spi_shield_0_synchronizer_ff_15 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_synchronizer_ff_16 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
ext_spi_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_synchronizer_ff_16 : entity is "synchronizer_ff";
end system_axi_quad_spi_shield_0_synchronizer_ff_16;
architecture STRUCTURE of system_axi_quad_spi_shield_0_synchronizer_ff_16 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_synchronizer_ff_17 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_synchronizer_ff_17 : entity is "synchronizer_ff";
end system_axi_quad_spi_shield_0_synchronizer_ff_17;
architecture STRUCTURE of system_axi_quad_spi_shield_0_synchronizer_ff_17 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_synchronizer_ff_18 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_synchronizer_ff_18 : entity is "synchronizer_ff";
end system_axi_quad_spi_shield_0_synchronizer_ff_18;
architecture STRUCTURE of system_axi_quad_spi_shield_0_synchronizer_ff_18 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_synchronizer_ff_3 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_synchronizer_ff_3 : entity is "synchronizer_ff";
end system_axi_quad_spi_shield_0_synchronizer_ff_3;
architecture STRUCTURE of system_axi_quad_spi_shield_0_synchronizer_ff_3 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_synchronizer_ff_4 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_synchronizer_ff_4 : entity is "synchronizer_ff";
end system_axi_quad_spi_shield_0_synchronizer_ff_4;
architecture STRUCTURE of system_axi_quad_spi_shield_0_synchronizer_ff_4 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_synchronizer_ff_5 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_synchronizer_ff_5 : entity is "synchronizer_ff";
end system_axi_quad_spi_shield_0_synchronizer_ff_5;
architecture STRUCTURE of system_axi_quad_spi_shield_0_synchronizer_ff_5 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized0\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
ext_spi_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized0\ : entity is "synchronizer_ff";
end \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized0\;
architecture STRUCTURE of \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized0\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized0_25\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized0_25\ : entity is "synchronizer_ff";
end \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized0_25\;
architecture STRUCTURE of \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized0_25\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized1\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized1\ : entity is "synchronizer_ff";
end \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized1\;
architecture STRUCTURE of \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized1\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized1_26\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
ext_spi_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized1_26\ : entity is "synchronizer_ff";
end \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized1_26\;
architecture STRUCTURE of \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized1_26\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized2\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
ext_spi_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized2\ : entity is "synchronizer_ff";
end \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized2\;
architecture STRUCTURE of \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized2\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized2_27\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized2_27\ : entity is "synchronizer_ff";
end \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized2_27\;
architecture STRUCTURE of \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized2_27\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized3\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized3\ : entity is "synchronizer_ff";
end \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized3\;
architecture STRUCTURE of \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized3\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized3_28\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
ext_spi_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized3_28\ : entity is "synchronizer_ff";
end \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized3_28\;
architecture STRUCTURE of \system_axi_quad_spi_shield_0_synchronizer_ff__parameterized3_28\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_wr_bin_cntr is
port (
ram_full_i_reg : out STD_LOGIC;
\gic0.gc1.count_d2_reg[2]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[0]\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_wr_bin_cntr : entity is "wr_bin_cntr";
end system_axi_quad_spi_shield_0_wr_bin_cntr;
architecture STRUCTURE of system_axi_quad_spi_shield_0_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^gic0.gc1.count_d2_reg[2]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 0 to 0 );
signal \plusOp__1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_full_i_i_2_n_0 : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 downto 1 );
signal wr_pntr_plus3 : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc1.count[0]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \gic0.gc1.count[1]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \gic0.gc1.count[2]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \gic0.gc1.count[3]_i_1\ : label is "soft_lutpair30";
begin
Q(2 downto 0) <= \^q\(2 downto 0);
\gic0.gc1.count_d2_reg[2]_0\(1 downto 0) <= \^gic0.gc1.count_d2_reg[2]_0\(1 downto 0);
\gic0.gc1.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => wr_pntr_plus3(0),
O => \plusOp__1\(0)
);
\gic0.gc1.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => wr_pntr_plus3(0),
I1 => wr_pntr_plus3(1),
O => \plusOp__1\(1)
);
\gic0.gc1.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => wr_pntr_plus3(2),
I1 => wr_pntr_plus3(1),
I2 => wr_pntr_plus3(0),
O => \plusOp__1\(2)
);
\gic0.gc1.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => wr_pntr_plus3(3),
I1 => wr_pntr_plus3(0),
I2 => wr_pntr_plus3(1),
I3 => wr_pntr_plus3(2),
O => \plusOp__1\(3)
);
\gic0.gc1.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus3(0),
Q => \^gic0.gc1.count_d2_reg[2]_0\(0)
);
\gic0.gc1.count_d1_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => wr_pntr_plus3(1),
PRE => AR(0),
Q => wr_pntr_plus2(1)
);
\gic0.gc1.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus3(2),
Q => \^gic0.gc1.count_d2_reg[2]_0\(1)
);
\gic0.gc1.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus3(3),
Q => wr_pntr_plus2(3)
);
\gic0.gc1.count_d2_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \^gic0.gc1.count_d2_reg[2]_0\(0),
PRE => AR(0),
Q => p_13_out(0)
);
\gic0.gc1.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(1),
Q => \^q\(0)
);
\gic0.gc1.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc1.count_d2_reg[2]_0\(1),
Q => \^q\(1)
);
\gic0.gc1.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(3),
Q => \^q\(2)
);
\gic0.gc1.count_d3_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => p_13_out(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc1.count_d3_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc1.count_d3_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc1.count_d3_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc1.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \plusOp__1\(0),
PRE => AR(0),
Q => wr_pntr_plus3(0)
);
\gic0.gc1.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \plusOp__1\(1),
PRE => AR(0),
Q => wr_pntr_plus3(1)
);
\gic0.gc1.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(2),
Q => wr_pntr_plus3(2)
);
\gic0.gc1.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(3),
Q => wr_pntr_plus3(3)
);
ram_full_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0000EAAE"
)
port map (
I0 => ram_full_i_i_2_n_0,
I1 => \gnxpm_cdc.rd_pntr_bin_reg[3]\,
I2 => p_13_out(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
O => ram_full_i_reg
);
ram_full_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"2002000000002002"
)
port map (
I0 => E(0),
I1 => \gnxpm_cdc.rd_pntr_bin_reg[0]\,
I2 => \gnxpm_cdc.rd_pntr_bin_reg[3]_0\(2),
I3 => wr_pntr_plus2(3),
I4 => \gnxpm_cdc.rd_pntr_bin_reg[3]_0\(1),
I5 => wr_pntr_plus2(1),
O => ram_full_i_i_2_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_wr_bin_cntr_21 is
port (
ram_full_fb_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ext_spi_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_wr_bin_cntr_21 : entity is "wr_bin_cntr";
end system_axi_quad_spi_shield_0_wr_bin_cntr_21;
architecture STRUCTURE of system_axi_quad_spi_shield_0_wr_bin_cntr_21 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ram_full_i_i_4__0_n_0\ : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_pntr_plus3 : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc1.count[0]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \gic0.gc1.count[1]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \gic0.gc1.count[2]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \gic0.gc1.count[3]_i_1__0\ : label is "soft_lutpair24";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc1.count[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => wr_pntr_plus3(0),
O => \plusOp__2\(0)
);
\gic0.gc1.count[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => wr_pntr_plus3(0),
I1 => wr_pntr_plus3(1),
O => \plusOp__2\(1)
);
\gic0.gc1.count[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => wr_pntr_plus3(2),
I1 => wr_pntr_plus3(1),
I2 => wr_pntr_plus3(0),
O => \plusOp__2\(2)
);
\gic0.gc1.count[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => wr_pntr_plus3(3),
I1 => wr_pntr_plus3(0),
I2 => wr_pntr_plus3(1),
I3 => wr_pntr_plus3(2),
O => \plusOp__2\(3)
);
\gic0.gc1.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus3(0),
Q => wr_pntr_plus2(0)
);
\gic0.gc1.count_d1_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => E(0),
D => wr_pntr_plus3(1),
PRE => AR(0),
Q => wr_pntr_plus2(1)
);
\gic0.gc1.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus3(2),
Q => wr_pntr_plus2(2)
);
\gic0.gc1.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus3(3),
Q => wr_pntr_plus2(3)
);
\gic0.gc1.count_d2_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => E(0),
D => wr_pntr_plus2(0),
PRE => AR(0),
Q => \^q\(0)
);
\gic0.gc1.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(1),
Q => \^q\(1)
);
\gic0.gc1.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(2),
Q => \^q\(2)
);
\gic0.gc1.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(3),
Q => \^q\(3)
);
\gic0.gc1.count_d3_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc1.count_d3_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc1.count_d3_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc1.count_d3_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc1.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => E(0),
D => \plusOp__2\(0),
PRE => AR(0),
Q => wr_pntr_plus3(0)
);
\gic0.gc1.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => E(0),
D => \plusOp__2\(1),
PRE => AR(0),
Q => wr_pntr_plus3(1)
);
\gic0.gc1.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__2\(2),
Q => wr_pntr_plus3(2)
);
\gic0.gc1.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__2\(3),
Q => wr_pntr_plus3(3)
);
\ram_full_i_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF6FF6"
)
port map (
I0 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(3),
I1 => wr_pntr_plus2(3),
I2 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(2),
I3 => wr_pntr_plus2(2),
I4 => \ram_full_i_i_4__0_n_0\,
O => ram_full_fb_i_reg
);
\ram_full_i_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => wr_pntr_plus2(1),
I1 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(1),
I2 => wr_pntr_plus2(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => \ram_full_i_i_4__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_wr_status_flags_as is
port (
\gic0.gc1.count_reg[0]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc1.count_d2_reg[0]\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
p_6_in : in STD_LOGIC;
ip2Bus_WrAck_core_reg_1 : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_wr_status_flags_as : entity is "wr_status_flags_as";
end system_axi_quad_spi_shield_0_wr_status_flags_as;
architecture STRUCTURE of system_axi_quad_spi_shield_0_wr_status_flags_as is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc1.count_reg[0]\ <= ram_full_i;
\gic0.gc1.count_d1[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000040"
)
port map (
I0 => ram_full_i,
I1 => p_6_in,
I2 => ip2Bus_WrAck_core_reg_1,
I3 => Bus_RNW_reg,
I4 => ram_full_fb_i,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \gic0.gc1.count_d2_reg[0]\,
PRE => \out\,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \gic0.gc1.count_d2_reg[0]\,
PRE => \out\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_wr_status_flags_as_20 is
port (
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC;
Rx_FIFO_Full_Fifo : out STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
\out\ : in STD_LOGIC;
spiXfer_done_int : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC;
\gic0.gc1.count_d2_reg[3]\ : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
scndry_out : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_wr_status_flags_as_20 : entity is "wr_status_flags_as";
end system_axi_quad_spi_shield_0_wr_status_flags_as_20;
architecture STRUCTURE of system_axi_quad_spi_shield_0_wr_status_flags_as_20 is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
signal \ram_full_i_i_1__0_n_0\ : STD_LOGIC;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ <= ram_full_i;
ram_full_fb_i_reg_0 <= ram_full_fb_i;
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => ram_full_i,
I1 => scndry_out,
O => Rx_FIFO_Full_Fifo
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \ram_full_i_i_1__0_n_0\,
PRE => \out\,
Q => ram_full_fb_i
);
\ram_full_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FF02"
)
port map (
I0 => spiXfer_done_int,
I1 => ram_full_fb_i,
I2 => \gnxpm_cdc.rd_pntr_bin_reg[3]\,
I3 => \gic0.gc1.count_d2_reg[3]\,
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
O => \ram_full_i_i_1__0_n_0\
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \ram_full_i_i_1__0_n_0\,
PRE => \out\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_address_decoder is
port (
p_3_in : out STD_LOGIC;
Receive_ip2bus_error_reg : out STD_LOGIC;
Transmit_ip2bus_error_reg : out STD_LOGIC;
\SPICR_data_int_reg[0]\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1_reg : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
\icount_out_reg[1]\ : out STD_LOGIC;
SPICR_data_int_reg0 : out STD_LOGIC;
bus2ip_wrce_int : out STD_LOGIC_VECTOR ( 0 to 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 10 downto 0 );
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[31]\ : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : out STD_LOGIC;
modf_reg : out STD_LOGIC;
Transmit_ip2bus_error0 : out STD_LOGIC;
IP2Bus_Error_1 : out STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_WrAck_reg\ : out STD_LOGIC;
reset_trig0 : out STD_LOGIC;
sw_rst_cond : out STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg\ : out STD_LOGIC;
wr_ce_or_reduce_core_cmb : out STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole0 : out STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole0 : out STD_LOGIC;
intr_controller_rd_ce_or_reduce : out STD_LOGIC;
rd_ce_or_reduce_core_cmb : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg_0 : out STD_LOGIC;
\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]\ : out STD_LOGIC;
Q : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\bus2ip_addr_i_reg[6]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn : in STD_LOGIC;
p_16_out : in STD_LOGIC;
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
is_write_reg : in STD_LOGIC;
p_15_out : in STD_LOGIC;
is_read : in STD_LOGIC;
ip2Bus_WrAck_core_reg_1 : in STD_LOGIC;
\out\ : in STD_LOGIC;
irpt_rdack_d1 : in STD_LOGIC;
ipif_glbl_irpt_enable_reg : in STD_LOGIC;
\ip_irpt_enable_reg_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
rx_fifo_count : in STD_LOGIC_VECTOR ( 1 downto 0 );
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2\ : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ : in STD_LOGIC;
SPISSR_frm_axi_clk : in STD_LOGIC;
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_0\ : in STD_LOGIC;
p_1_in35_in : in STD_LOGIC;
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_1\ : in STD_LOGIC;
p_1_in32_in : in STD_LOGIC;
p_1_in29_in : in STD_LOGIC;
p_1_in26_in : in STD_LOGIC;
p_1_in23_in : in STD_LOGIC;
p_1_in20_in : in STD_LOGIC;
p_1_in17_in : in STD_LOGIC;
spicr_8_tr_inhibit_frm_axi_clk : in STD_LOGIC;
p_1_in14_in : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
\goreg_dm.dout_i_reg[7]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
scndry_out : in STD_LOGIC;
spicr_1_spe_frm_axi_clk : in STD_LOGIC;
Tx_FIFO_Empty_SPISR_to_axi_clk : in STD_LOGIC;
spicr_2_mst_n_slv_frm_axi_clk : in STD_LOGIC;
empty_fwft_i_reg : in STD_LOGIC;
spicr_4_cpha_frm_axi_clk : in STD_LOGIC;
sr_3_MODF_int : in STD_LOGIC;
\LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\ : in STD_LOGIC;
spicr_5_txfifo_rst_frm_axi_clk : in STD_LOGIC;
ip2Bus_RdAck_core_reg : in STD_LOGIC;
spicr_6_rxfifo_rst_frm_axi_clk : in STD_LOGIC;
spicr_7_ss_frm_axi_clk : in STD_LOGIC;
rx_fifo_empty_i : in STD_LOGIC;
spicr_0_loop_frm_axi_clk : in STD_LOGIC;
Tx_FIFO_Full_int : in STD_LOGIC;
tx_fifo_count : in STD_LOGIC_VECTOR ( 0 to 0 );
spicr_3_cpol_frm_axi_clk : in STD_LOGIC;
spicr_9_lsb_frm_axi_clk : in STD_LOGIC;
bus2ip_rnw_i_reg_0 : in STD_LOGIC;
Receive_ip2bus_error_reg_0 : in STD_LOGIC;
p_4_in : in STD_LOGIC;
sw_rst_cond_d1 : in STD_LOGIC;
ip2Bus_WrAck_core_reg_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_address_decoder : entity is "address_decoder";
end system_axi_quad_spi_shield_0_address_decoder;
architecture STRUCTURE of system_axi_quad_spi_shield_0_address_decoder is
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[27].ce_out_i[27]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[31].ce_out_i_reg_n_0_[31]\ : STD_LOGIC;
signal \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[0]_i_2_n_0\ : STD_LOGIC;
signal \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_2_n_0\ : STD_LOGIC;
signal \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_3_n_0\ : STD_LOGIC;
signal \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_4_n_0\ : STD_LOGIC;
signal \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[24]_i_2_n_0\ : STD_LOGIC;
signal \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[25]_i_2_n_0\ : STD_LOGIC;
signal \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[26]_i_2_n_0\ : STD_LOGIC;
signal \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[27]_i_2_n_0\ : STD_LOGIC;
signal \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[28]_i_2_n_0\ : STD_LOGIC;
signal \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[28]_i_3_n_0\ : STD_LOGIC;
signal \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[28]_i_4_n_0\ : STD_LOGIC;
signal \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[29]_i_2_n_0\ : STD_LOGIC;
signal \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[30]_i_3_n_0\ : STD_LOGIC;
signal \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[31]_i_2_n_0\ : STD_LOGIC;
signal \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[31]_i_5_n_0\ : STD_LOGIC;
signal \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[31]\ : STD_LOGIC;
signal \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_2_n_0\ : STD_LOGIC;
signal \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_3_n_0\ : STD_LOGIC;
signal \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_4_n_0\ : STD_LOGIC;
signal \MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\ : STD_LOGIC;
signal \MEM_DECODE_GEN[1].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\ : STD_LOGIC;
signal \MEM_DECODE_GEN[1].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\ : STD_LOGIC;
signal \MEM_DECODE_GEN[2].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\ : STD_LOGIC;
signal \MEM_DECODE_GEN[2].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\ : STD_LOGIC;
signal \^receive_ip2bus_error_reg\ : STD_LOGIC;
signal \^spicr_data_int_reg[0]\ : STD_LOGIC;
signal \^transmit_ip2bus_error_reg\ : STD_LOGIC;
signal cs_ce_clr : STD_LOGIC;
signal \^gpregsm1.curr_fwft_state_reg[1]\ : STD_LOGIC;
signal intr2bus_wrack_i_2_n_0 : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 : STD_LOGIC;
signal \^ipif_glbl_irpt_enable_reg_reg\ : STD_LOGIC;
signal \^modf_reg\ : STD_LOGIC;
signal p_10_in : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_11_in : STD_LOGIC;
signal p_11_out : STD_LOGIC;
signal p_12_in : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_13_in : STD_LOGIC;
signal p_13_out : STD_LOGIC;
signal p_14_in : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal p_15_out_1 : STD_LOGIC;
signal p_16_in : STD_LOGIC;
signal p_17_in : STD_LOGIC;
signal p_18_in : STD_LOGIC;
signal p_19_in : STD_LOGIC;
signal p_1_out : STD_LOGIC;
signal p_20_in : STD_LOGIC;
signal p_21_in : STD_LOGIC;
signal p_22_in : STD_LOGIC;
signal p_23_in : STD_LOGIC;
signal p_24_in : STD_LOGIC;
signal p_25_in : STD_LOGIC;
signal p_26_in : STD_LOGIC;
signal p_27_in : STD_LOGIC;
signal p_28_in : STD_LOGIC;
signal p_29_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_30_in : STD_LOGIC;
signal p_31_in : STD_LOGIC;
signal p_32_in : STD_LOGIC;
signal \^p_3_in\ : STD_LOGIC;
signal p_3_out : STD_LOGIC;
signal p_4_in_0 : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_in : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_9_in : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal s_axi_wready_INST_0_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of Bus_RNW_reg_i_1 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \CONTROL_REG_5_9_GENERATE[9].SPICR_data_int[9]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[0]_i_2\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[22]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_3\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[28]_i_4\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_Error_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_WrAck_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \SPICR_REG_78_GENERATE[7].SPI_TRISTATE_CONTROL_I_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of Transmit_ip2bus_error_i_1 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc1.count_d1[3]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \icount_out[1]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of intr2bus_wrack_i_1 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of intr2bus_wrack_i_2 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of ip2Bus_RdAck_intr_reg_hole_d1_i_1 : label is "soft_lutpair11";
attribute SOFT_HLUTNM of ip2Bus_RdAck_intr_reg_hole_i_1 : label is "soft_lutpair11";
attribute SOFT_HLUTNM of ip2Bus_WrAck_intr_reg_hole_d1_i_1 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of ip2Bus_WrAck_intr_reg_hole_i_1 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \ip_irpt_enable_reg[8]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of modf_i_2 : label is "soft_lutpair6";
attribute SOFT_HLUTNM of reset_trig_i_1 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of sw_rst_cond_d1_i_1 : label is "soft_lutpair4";
begin
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[31]\ <= \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[31]\;
Receive_ip2bus_error_reg <= \^receive_ip2bus_error_reg\;
\SPICR_data_int_reg[0]\ <= \^spicr_data_int_reg[0]\;
Transmit_ip2bus_error_reg <= \^transmit_ip2bus_error_reg\;
\gpregsm1.curr_fwft_state_reg[1]\ <= \^gpregsm1.curr_fwft_state_reg[1]\;
ipif_glbl_irpt_enable_reg_reg <= \^ipif_glbl_irpt_enable_reg_reg\;
modf_reg <= \^modf_reg\;
p_3_in <= \^p_3_in\;
s_axi_arready <= \^s_axi_arready\;
s_axi_wready <= \^s_axi_wready\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => Q,
I2 => \^ipif_glbl_irpt_enable_reg_reg\,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => \^ipif_glbl_irpt_enable_reg_reg\,
R => '0'
);
\CONTROL_REG_5_9_GENERATE[9].SPICR_data_int[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => \^spicr_data_int_reg[0]\,
I1 => \^ipif_glbl_irpt_enable_reg_reg\,
I2 => ip2Bus_WrAck_core_reg_1,
O => SPICR_data_int_reg0
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\,
Q => p_32_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_5_out,
Q => p_22_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_4_out,
Q => p_21_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_3_out,
Q => p_20_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_2_out,
Q => p_19_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_1_out,
Q => p_18_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(3),
I1 => \bus2ip_addr_i_reg[6]\(1),
I2 => \bus2ip_addr_i_reg[6]\(0),
I3 => \bus2ip_addr_i_reg[6]\(4),
I4 => Q,
I5 => \bus2ip_addr_i_reg[6]\(2),
O => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1_n_0\,
Q => p_17_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000001000000"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(0),
I1 => \bus2ip_addr_i_reg[6]\(2),
I2 => \bus2ip_addr_i_reg[6]\(3),
I3 => Q,
I4 => \bus2ip_addr_i_reg[6]\(4),
I5 => \bus2ip_addr_i_reg[6]\(1),
O => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\,
Q => p_16_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(1),
I1 => \bus2ip_addr_i_reg[6]\(2),
I2 => \bus2ip_addr_i_reg[6]\(0),
I3 => \bus2ip_addr_i_reg[6]\(3),
I4 => Q,
I5 => \bus2ip_addr_i_reg[6]\(4),
O => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\,
Q => p_15_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \MEM_DECODE_GEN[1].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\,
Q => p_14_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(3),
I1 => Q,
I2 => \bus2ip_addr_i_reg[6]\(4),
I3 => \bus2ip_addr_i_reg[6]\(2),
I4 => \bus2ip_addr_i_reg[6]\(0),
I5 => \bus2ip_addr_i_reg[6]\(1),
O => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\,
Q => p_13_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_14_out,
Q => p_31_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(0),
I1 => \bus2ip_addr_i_reg[6]\(1),
I2 => \bus2ip_addr_i_reg[6]\(3),
I3 => Q,
I4 => \bus2ip_addr_i_reg[6]\(4),
I5 => \bus2ip_addr_i_reg[6]\(2),
O => \GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[20].ce_out_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1_n_0\,
Q => p_12_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0020000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(2),
I1 => \bus2ip_addr_i_reg[6]\(1),
I2 => \bus2ip_addr_i_reg[6]\(0),
I3 => \bus2ip_addr_i_reg[6]\(3),
I4 => Q,
I5 => \bus2ip_addr_i_reg[6]\(4),
O => \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[21].ce_out_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1_n_0\,
Q => p_11_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[22].ce_out_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \MEM_DECODE_GEN[1].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\,
Q => p_10_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(3),
I1 => Q,
I2 => \bus2ip_addr_i_reg[6]\(4),
I3 => \bus2ip_addr_i_reg[6]\(2),
I4 => \bus2ip_addr_i_reg[6]\(0),
I5 => \bus2ip_addr_i_reg[6]\(1),
O => p_15_out_1
);
\GEN_BKEND_CE_REGISTERS[23].ce_out_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_15_out_1,
Q => p_9_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000010000000"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(0),
I1 => \bus2ip_addr_i_reg[6]\(2),
I2 => \bus2ip_addr_i_reg[6]\(4),
I3 => \bus2ip_addr_i_reg[6]\(3),
I4 => Q,
I5 => \bus2ip_addr_i_reg[6]\(1),
O => \GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1_n_0\,
Q => \^spicr_data_int_reg[0]\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1000000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(1),
I1 => \bus2ip_addr_i_reg[6]\(2),
I2 => \bus2ip_addr_i_reg[6]\(0),
I3 => \bus2ip_addr_i_reg[6]\(4),
I4 => \bus2ip_addr_i_reg[6]\(3),
I5 => Q,
O => \GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[25].ce_out_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_1_n_0\,
Q => p_7_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \MEM_DECODE_GEN[2].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\,
Q => \^transmit_ip2bus_error_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[27].ce_out_i[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(4),
I1 => \bus2ip_addr_i_reg[6]\(3),
I2 => Q,
I3 => \bus2ip_addr_i_reg[6]\(2),
I4 => \bus2ip_addr_i_reg[6]\(0),
I5 => \bus2ip_addr_i_reg[6]\(1),
O => \GEN_BKEND_CE_REGISTERS[27].ce_out_i[27]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[27].ce_out_i[27]_i_1_n_0\,
Q => \^receive_ip2bus_error_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1000000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(0),
I1 => \bus2ip_addr_i_reg[6]\(1),
I2 => \bus2ip_addr_i_reg[6]\(4),
I3 => \bus2ip_addr_i_reg[6]\(3),
I4 => Q,
I5 => \bus2ip_addr_i_reg[6]\(2),
O => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[28].ce_out_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_1_n_0\,
Q => p_4_in_0,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(2),
I1 => \bus2ip_addr_i_reg[6]\(1),
I2 => \bus2ip_addr_i_reg[6]\(0),
I3 => \bus2ip_addr_i_reg[6]\(4),
I4 => \bus2ip_addr_i_reg[6]\(3),
I5 => Q,
O => \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[29].ce_out_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_1_n_0\,
Q => \^p_3_in\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_13_out,
Q => p_30_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \MEM_DECODE_GEN[2].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\,
Q => p_2_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => \^s_axi_arready\,
I1 => s_axi_aresetn,
I2 => \^s_axi_wready\,
O => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\(4),
I1 => \bus2ip_addr_i_reg[6]\(3),
I2 => Q,
I3 => \bus2ip_addr_i_reg[6]\(2),
I4 => \bus2ip_addr_i_reg[6]\(0),
I5 => \bus2ip_addr_i_reg[6]\(1),
O => \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[31].ce_out_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_2_n_0\,
Q => \GEN_BKEND_CE_REGISTERS[31].ce_out_i_reg_n_0_[31]\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_12_out,
Q => p_29_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_11_out,
Q => p_28_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_10_out,
Q => p_27_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_9_out,
Q => p_26_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_8_out,
Q => p_25_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_7_out,
Q => p_24_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_6_out,
Q => p_23_in,
R => cs_ce_clr
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => p_24_in,
I1 => intr2bus_wrack_i_2_n_0,
I2 => irpt_wrack_d1,
O => \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00100000"
)
port map (
I0 => p_24_in,
I1 => p_22_in,
I2 => p_25_in,
I3 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[0]_i_2_n_0\,
I4 => ipif_glbl_irpt_enable_reg,
O => D(10)
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => s_axi_wstrb(0),
I2 => \^ipif_glbl_irpt_enable_reg_reg\,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[0]_i_2_n_0\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => spicr_9_lsb_frm_axi_clk,
I1 => \^ipif_glbl_irpt_enable_reg_reg\,
I2 => \^spicr_data_int_reg[0]\,
O => D(9)
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_2_n_0\,
I1 => \ip_irpt_enable_reg_reg[8]\(8),
I2 => spicr_8_tr_inhibit_frm_axi_clk,
I3 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_3_n_0\,
I4 => p_1_in14_in,
I5 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_4_n_0\,
O => D(8)
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"BBBFFFFF"
)
port map (
I0 => p_24_in,
I1 => p_22_in,
I2 => bus2ip_rnw_i_reg,
I3 => s_axi_wstrb(0),
I4 => \^ipif_glbl_irpt_enable_reg_reg\,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_2_n_0\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^spicr_data_int_reg[0]\,
I1 => \^ipif_glbl_irpt_enable_reg_reg\,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_3_n_0\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"57FF"
)
port map (
I0 => \^ipif_glbl_irpt_enable_reg_reg\,
I1 => s_axi_wstrb(0),
I2 => bus2ip_rnw_i_reg,
I3 => p_24_in,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_4_n_0\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4F4FFF4"
)
port map (
I0 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_2_n_0\,
I1 => \ip_irpt_enable_reg_reg[8]\(7),
I2 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[24]_i_2_n_0\,
I3 => p_1_in17_in,
I4 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_4_n_0\,
O => D(7)
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[24]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800880088008800"
)
port map (
I0 => \^spicr_data_int_reg[0]\,
I1 => spicr_7_ss_frm_axi_clk,
I2 => \^receive_ip2bus_error_reg\,
I3 => \^ipif_glbl_irpt_enable_reg_reg\,
I4 => ip2Bus_RdAck_core_reg,
I5 => \goreg_dm.dout_i_reg[7]\(6),
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[24]_i_2_n_0\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4F4FFF4"
)
port map (
I0 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_2_n_0\,
I1 => \ip_irpt_enable_reg_reg[8]\(6),
I2 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[25]_i_2_n_0\,
I3 => p_1_in20_in,
I4 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_4_n_0\,
O => D(6)
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[25]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80000080800000"
)
port map (
I0 => \^receive_ip2bus_error_reg\,
I1 => ip2Bus_RdAck_core_reg,
I2 => \goreg_dm.dout_i_reg[7]\(5),
I3 => \^spicr_data_int_reg[0]\,
I4 => \^ipif_glbl_irpt_enable_reg_reg\,
I5 => spicr_6_rxfifo_rst_frm_axi_clk,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[25]_i_2_n_0\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4F4FFF4"
)
port map (
I0 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_2_n_0\,
I1 => \ip_irpt_enable_reg_reg[8]\(5),
I2 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[26]_i_2_n_0\,
I3 => p_1_in23_in,
I4 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_4_n_0\,
O => D(5)
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[26]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \^gpregsm1.curr_fwft_state_reg[1]\,
I1 => \goreg_dm.dout_i_reg[7]\(4),
I2 => \LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\,
I3 => \^modf_reg\,
I4 => spicr_5_txfifo_rst_frm_axi_clk,
I5 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_3_n_0\,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[26]_i_2_n_0\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4F4FFF4"
)
port map (
I0 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_2_n_0\,
I1 => \ip_irpt_enable_reg_reg[8]\(4),
I2 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[27]_i_2_n_0\,
I3 => p_1_in26_in,
I4 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_4_n_0\,
O => D(4)
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[27]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \^gpregsm1.curr_fwft_state_reg[1]\,
I1 => \goreg_dm.dout_i_reg[7]\(3),
I2 => spicr_4_cpha_frm_axi_clk,
I3 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_3_n_0\,
I4 => sr_3_MODF_int,
I5 => \^modf_reg\,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[27]_i_2_n_0\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF4FFF4FFFFFFF4"
)
port map (
I0 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_2_n_0\,
I1 => \ip_irpt_enable_reg_reg[8]\(3),
I2 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[28]_i_2_n_0\,
I3 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[28]_i_3_n_0\,
I4 => p_1_in29_in,
I5 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_4_n_0\,
O => D(3)
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[28]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F44444444444444"
)
port map (
I0 => \^gpregsm1.curr_fwft_state_reg[1]\,
I1 => \goreg_dm.dout_i_reg[7]\(2),
I2 => empty_fwft_i_reg,
I3 => p_2_in,
I4 => \^ipif_glbl_irpt_enable_reg_reg\,
I5 => rx_fifo_count(1),
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[28]_i_2_n_0\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[28]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[28]_i_4_n_0\,
I1 => tx_fifo_count(0),
I2 => Tx_FIFO_Full_int,
I3 => \^modf_reg\,
I4 => spicr_3_cpol_frm_axi_clk,
I5 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_3_n_0\,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[28]_i_3_n_0\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[28]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"BF"
)
port map (
I0 => Tx_FIFO_Empty_SPISR_to_axi_clk,
I1 => \^p_3_in\,
I2 => \^ipif_glbl_irpt_enable_reg_reg\,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[28]_i_4_n_0\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF4FFF4FFFFFFF4"
)
port map (
I0 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_2_n_0\,
I1 => \ip_irpt_enable_reg_reg[8]\(2),
I2 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[29]_i_2_n_0\,
I3 => \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_1\,
I4 => p_1_in32_in,
I5 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_4_n_0\,
O => D(2)
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[29]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \^gpregsm1.curr_fwft_state_reg[1]\,
I1 => \goreg_dm.dout_i_reg[7]\(1),
I2 => Tx_FIFO_Empty_SPISR_to_axi_clk,
I3 => \^modf_reg\,
I4 => spicr_2_mst_n_slv_frm_axi_clk,
I5 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_3_n_0\,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[29]_i_2_n_0\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF4FFF4FFFFFFF4"
)
port map (
I0 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_2_n_0\,
I1 => \ip_irpt_enable_reg_reg[8]\(1),
I2 => \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_0\,
I3 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[30]_i_3_n_0\,
I4 => p_1_in35_in,
I5 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_4_n_0\,
O => D(1)
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[30]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \^gpregsm1.curr_fwft_state_reg[1]\,
I1 => \goreg_dm.dout_i_reg[7]\(0),
I2 => scndry_out,
I3 => \^modf_reg\,
I4 => spicr_1_spe_frm_axi_clk,
I5 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_3_n_0\,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[30]_i_3_n_0\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF4FFF4F4"
)
port map (
I0 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_2_n_0\,
I1 => \ip_irpt_enable_reg_reg[8]\(0),
I2 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[31]_i_2_n_0\,
I3 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[31]\,
I4 => rx_fifo_count(0),
I5 => \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2\,
O => D(0)
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF4444444"
)
port map (
I0 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_4_n_0\,
I1 => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\,
I2 => \^ipif_glbl_irpt_enable_reg_reg\,
I3 => SPISSR_frm_axi_clk,
I4 => p_4_in_0,
I5 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[31]_i_5_n_0\,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[31]_i_2_n_0\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[31]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"BF"
)
port map (
I0 => empty_fwft_i_reg,
I1 => p_2_in,
I2 => \^ipif_glbl_irpt_enable_reg_reg\,
O => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[31]\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[31]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFA80000A8A80000"
)
port map (
I0 => p_7_in,
I1 => empty_fwft_i_reg,
I2 => rx_fifo_empty_i,
I3 => \^spicr_data_int_reg[0]\,
I4 => \^ipif_glbl_irpt_enable_reg_reg\,
I5 => spicr_0_loop_frm_axi_clk,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[31]_i_5_n_0\
);
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_Error_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFF04"
)
port map (
I0 => \^ipif_glbl_irpt_enable_reg_reg\,
I1 => p_16_in,
I2 => bus2ip_rnw_i_reg_0,
I3 => Receive_ip2bus_error_reg_0,
I4 => p_4_in,
O => IP2Bus_Error_1
);
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_WrAck_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => bus2ip_rnw_i_reg_0,
I1 => p_16_in,
I2 => \^ipif_glbl_irpt_enable_reg_reg\,
O => \LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_WrAck_reg\
);
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FF75"
)
port map (
I0 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_2_n_0\,
I1 => \out\,
I2 => \^transmit_ip2bus_error_reg\,
I3 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_3_n_0\,
I4 => \^ipif_glbl_irpt_enable_reg_reg\,
O => wr_ce_or_reduce_core_cmb
);
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[31].ce_out_i_reg_n_0_[31]\,
I1 => p_11_in,
I2 => p_4_in_0,
I3 => p_10_in,
I4 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_4_n_0\,
O => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_2_n_0\
);
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_7_in,
I1 => \^spicr_data_int_reg[0]\,
I2 => \^p_3_in\,
I3 => p_2_in,
O => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_3_n_0\
);
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => p_13_in,
I1 => \^receive_ip2bus_error_reg\,
I2 => p_15_in,
I3 => p_14_in,
I4 => p_12_in,
I5 => p_9_in,
O => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_4_n_0\
);
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055551511"
)
port map (
I0 => ip2Bus_WrAck_core_reg_d1,
I1 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_2_n_0\,
I2 => \out\,
I3 => \^transmit_ip2bus_error_reg\,
I4 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_3_n_0\,
I5 => \^ipif_glbl_irpt_enable_reg_reg\,
O => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg\
);
\LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_srl4___NO_DUAL_QUAD_MODE.QSPI_NORMAL_QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_r_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA8AAAA"
)
port map (
I0 => \^ipif_glbl_irpt_enable_reg_reg\,
I1 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_3_n_0\,
I2 => p_16_in,
I3 => \^transmit_ip2bus_error_reg\,
I4 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_2_n_0\,
O => rd_ce_or_reduce_core_cmb
);
\MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized0\
port map (
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\,
Q => Q,
\bus2ip_addr_i_reg[6]\(4 downto 0) => \bus2ip_addr_i_reg[6]\(4 downto 0)
);
\MEM_DECODE_GEN[0].PER_CE_GEN[10].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized10\
port map (
Q => Q,
\bus2ip_addr_i_reg[6]\(4 downto 0) => \bus2ip_addr_i_reg[6]\(4 downto 0),
p_5_out => p_5_out
);
\MEM_DECODE_GEN[0].PER_CE_GEN[11].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized11\
port map (
Q => Q,
\bus2ip_addr_i_reg[6]\(4 downto 0) => \bus2ip_addr_i_reg[6]\(4 downto 0),
p_4_out => p_4_out
);
\MEM_DECODE_GEN[0].PER_CE_GEN[12].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized12\
port map (
Q => Q,
\bus2ip_addr_i_reg[6]\(4 downto 0) => \bus2ip_addr_i_reg[6]\(4 downto 0),
p_3_out => p_3_out
);
\MEM_DECODE_GEN[0].PER_CE_GEN[13].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized13\
port map (
Q => Q,
\bus2ip_addr_i_reg[6]\(4 downto 0) => \bus2ip_addr_i_reg[6]\(4 downto 0),
p_2_out => p_2_out
);
\MEM_DECODE_GEN[0].PER_CE_GEN[14].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized14\
port map (
Q => Q,
\bus2ip_addr_i_reg[6]\(4 downto 0) => \bus2ip_addr_i_reg[6]\(4 downto 0),
p_1_out => p_1_out
);
\MEM_DECODE_GEN[0].PER_CE_GEN[1].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized1\
port map (
Q => Q,
\bus2ip_addr_i_reg[6]\(4 downto 0) => \bus2ip_addr_i_reg[6]\(4 downto 0),
p_14_out => p_14_out
);
\MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized2\
port map (
Q => Q,
\bus2ip_addr_i_reg[6]\(4 downto 0) => \bus2ip_addr_i_reg[6]\(4 downto 0),
p_13_out => p_13_out
);
\MEM_DECODE_GEN[0].PER_CE_GEN[3].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized3\
port map (
Q => Q,
\bus2ip_addr_i_reg[6]\(4 downto 0) => \bus2ip_addr_i_reg[6]\(4 downto 0),
p_12_out => p_12_out
);
\MEM_DECODE_GEN[0].PER_CE_GEN[4].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized4\
port map (
Q => Q,
\bus2ip_addr_i_reg[6]\(4 downto 0) => \bus2ip_addr_i_reg[6]\(4 downto 0),
p_11_out => p_11_out
);
\MEM_DECODE_GEN[0].PER_CE_GEN[5].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized5\
port map (
Q => Q,
\bus2ip_addr_i_reg[6]\(4 downto 0) => \bus2ip_addr_i_reg[6]\(4 downto 0),
p_10_out => p_10_out
);
\MEM_DECODE_GEN[0].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized6\
port map (
Q => Q,
\bus2ip_addr_i_reg[6]\(4 downto 0) => \bus2ip_addr_i_reg[6]\(4 downto 0),
p_9_out => p_9_out
);
\MEM_DECODE_GEN[0].PER_CE_GEN[7].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized7\
port map (
Q => Q,
\bus2ip_addr_i_reg[6]\(4 downto 0) => \bus2ip_addr_i_reg[6]\(4 downto 0),
p_8_out => p_8_out
);
\MEM_DECODE_GEN[0].PER_CE_GEN[8].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized8\
port map (
Q => Q,
\bus2ip_addr_i_reg[6]\(4 downto 0) => \bus2ip_addr_i_reg[6]\(4 downto 0),
p_7_out => p_7_out
);
\MEM_DECODE_GEN[0].PER_CE_GEN[9].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized9\
port map (
Q => Q,
\bus2ip_addr_i_reg[6]\(4 downto 0) => \bus2ip_addr_i_reg[6]\(4 downto 0),
p_6_out => p_6_out
);
\MEM_DECODE_GEN[1].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized19\
port map (
\GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]\ => \MEM_DECODE_GEN[1].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\,
Q => Q,
\bus2ip_addr_i_reg[6]\(4 downto 0) => \bus2ip_addr_i_reg[6]\(4 downto 0)
);
\MEM_DECODE_GEN[1].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized23\
port map (
\GEN_BKEND_CE_REGISTERS[22].ce_out_i_reg[22]\ => \MEM_DECODE_GEN[1].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\,
Q => Q,
\bus2ip_addr_i_reg[6]\(4 downto 0) => \bus2ip_addr_i_reg[6]\(4 downto 0)
);
\MEM_DECODE_GEN[2].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized28\
port map (
\GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26]\ => \MEM_DECODE_GEN[2].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\,
Q => Q,
\bus2ip_addr_i_reg[6]\(4 downto 0) => \bus2ip_addr_i_reg[6]\(4 downto 0)
);
\MEM_DECODE_GEN[2].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_shield_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized32\
port map (
\GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30]\ => \MEM_DECODE_GEN[2].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\,
Q => Q,
\bus2ip_addr_i_reg[6]\(4 downto 0) => \bus2ip_addr_i_reg[6]\(4 downto 0)
);
\SPICR_REG_78_GENERATE[7].SPI_TRISTATE_CONTROL_I_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^spicr_data_int_reg[0]\,
I1 => \^ipif_glbl_irpt_enable_reg_reg\,
O => bus2ip_wrce_int(0)
);
\SPISSR_WR_GEN[0].SPISSR_Data_reg[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FBFF0800"
)
port map (
I0 => s_axi_wdata(0),
I1 => p_4_in_0,
I2 => \^ipif_glbl_irpt_enable_reg_reg\,
I3 => ip2Bus_WrAck_core_reg_1,
I4 => SPISSR_frm_axi_clk,
O => \SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]\
);
Transmit_ip2bus_error_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^transmit_ip2bus_error_reg\,
I1 => Tx_FIFO_Full_int,
I2 => \^ipif_glbl_irpt_enable_reg_reg\,
O => Transmit_ip2bus_error0
);
\gc1.count_d1[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^receive_ip2bus_error_reg\,
I1 => \^ipif_glbl_irpt_enable_reg_reg\,
I2 => ip2Bus_RdAck_core_reg,
O => \^gpregsm1.curr_fwft_state_reg[1]\
);
\icount_out[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => \^ipif_glbl_irpt_enable_reg_reg\,
I1 => ip2Bus_WrAck_core_reg_1,
I2 => \^transmit_ip2bus_error_reg\,
I3 => \out\,
O => \icount_out_reg[1]\
);
intr2bus_rdack_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"05050504"
)
port map (
I0 => irpt_rdack_d1,
I1 => p_25_in,
I2 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[0]_i_2_n_0\,
I3 => p_22_in,
I4 => p_24_in,
O => intr2bus_rdack0
);
intr2bus_wrack_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"05050504"
)
port map (
I0 => irpt_wrack_d1,
I1 => p_22_in,
I2 => intr2bus_wrack_i_2_n_0,
I3 => p_24_in,
I4 => p_25_in,
O => interrupt_wrce_strb
);
intr2bus_wrack_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"AB"
)
port map (
I0 => \^ipif_glbl_irpt_enable_reg_reg\,
I1 => bus2ip_rnw_i_reg,
I2 => s_axi_wstrb(0),
O => intr2bus_wrack_i_2_n_0
);
ip2Bus_RdAck_intr_reg_hole_d1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^ipif_glbl_irpt_enable_reg_reg\,
I1 => ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0,
O => intr_controller_rd_ce_or_reduce
);
ip2Bus_RdAck_intr_reg_hole_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0,
I1 => \^ipif_glbl_irpt_enable_reg_reg\,
I2 => ip2Bus_RdAck_intr_reg_hole_d1,
O => ip2Bus_RdAck_intr_reg_hole0
);
ip2Bus_WrAck_intr_reg_hole_d1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^ipif_glbl_irpt_enable_reg_reg\,
I1 => ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0,
O => ip2Bus_WrAck_intr_reg_hole_d1_reg
);
ip2Bus_WrAck_intr_reg_hole_d1_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0,
I1 => ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0,
I2 => p_27_in,
I3 => p_23_in,
I4 => p_26_in,
O => ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0
);
ip2Bus_WrAck_intr_reg_hole_d1_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => p_29_in,
I1 => p_32_in,
I2 => p_31_in,
I3 => p_21_in,
I4 => p_18_in,
I5 => p_20_in,
O => ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0
);
ip2Bus_WrAck_intr_reg_hole_d1_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_28_in,
I1 => p_17_in,
I2 => p_19_in,
I3 => p_30_in,
O => ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0
);
ip2Bus_WrAck_intr_reg_hole_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0,
I1 => \^ipif_glbl_irpt_enable_reg_reg\,
I2 => ip2Bus_WrAck_intr_reg_hole_d1,
O => ip2Bus_WrAck_intr_reg_hole0
);
\ip_irpt_enable_reg[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00A8"
)
port map (
I0 => p_22_in,
I1 => s_axi_wstrb(0),
I2 => bus2ip_rnw_i_reg,
I3 => \^ipif_glbl_irpt_enable_reg_reg\,
O => E(0)
);
ipif_glbl_irpt_enable_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBBBF00008880"
)
port map (
I0 => s_axi_wdata(1),
I1 => p_25_in,
I2 => s_axi_wstrb(0),
I3 => bus2ip_rnw_i_reg,
I4 => \^ipif_glbl_irpt_enable_reg_reg\,
I5 => ipif_glbl_irpt_enable_reg,
O => ipif_glbl_irpt_enable_reg_reg_0
);
irpt_rdack_d1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CCC0CCC0CCC08880"
)
port map (
I0 => p_25_in,
I1 => \^ipif_glbl_irpt_enable_reg_reg\,
I2 => s_axi_wstrb(0),
I3 => bus2ip_rnw_i_reg,
I4 => p_22_in,
I5 => p_24_in,
O => irpt_rdack
);
irpt_wrack_d1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"3330333033302220"
)
port map (
I0 => p_22_in,
I1 => \^ipif_glbl_irpt_enable_reg_reg\,
I2 => bus2ip_rnw_i_reg,
I3 => s_axi_wstrb(0),
I4 => p_24_in,
I5 => p_25_in,
O => irpt_wrack
);
modf_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^ipif_glbl_irpt_enable_reg_reg\,
I1 => p_7_in,
O => \^modf_reg\
);
reset_trig_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => \^ipif_glbl_irpt_enable_reg_reg\,
I1 => p_16_in,
I2 => bus2ip_rnw_i_reg_0,
I3 => sw_rst_cond_d1,
O => reset_trig0
);
s_axi_arready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAAAAA"
)
port map (
I0 => p_15_out,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(1),
I3 => is_read,
I4 => s_axi_wready_INST_0_i_1_n_0,
O => \^s_axi_arready\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAAAAA"
)
port map (
I0 => p_16_out,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(1),
I3 => is_write_reg,
I4 => s_axi_wready_INST_0_i_1_n_0,
O => \^s_axi_wready\
);
s_axi_wready_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(4),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(2),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(5),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(3),
O => s_axi_wready_INST_0_i_1_n_0
);
sw_rst_cond_d1_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => bus2ip_rnw_i_reg_0,
I1 => p_16_in,
I2 => \^ipif_glbl_irpt_enable_reg_reg\,
O => sw_rst_cond
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_clk_x_pntrs is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc1.count_d1_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\gic0.gc1.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gc1.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc1.count_d3_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
ext_spi_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\Q_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_clk_x_pntrs : entity is "clk_x_pntrs";
end system_axi_quad_spi_shield_0_clk_x_pntrs;
architecture STRUCTURE of system_axi_quad_spi_shield_0_clk_x_pntrs is
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \_inferred__0/i__n_0\ : STD_LOGIC;
signal \_inferred__2/i__n_0\ : STD_LOGIC;
signal \_inferred__3/i__n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[2].rd_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 2 to 2 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ram_empty_i_i_5__0_n_0\ : STD_LOGIC;
signal \^ram_empty_i_reg_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \_inferred__2/i_\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \_inferred__3/i_\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[2]_i_1\ : label is "soft_lutpair27";
begin
Q(2 downto 0) <= \^q\(2 downto 0);
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_empty_i_reg_0(3 downto 0) <= \^ram_empty_i_reg_0\(3 downto 0);
\_inferred__0/i_\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => \_inferred__0/i__n_0\
);
\_inferred__2/i_\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_6_out(1),
I1 => p_6_out(0),
I2 => p_6_out(3),
I3 => p_6_out(2),
O => \_inferred__2/i__n_0\
);
\_inferred__3/i_\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_6_out(2),
I1 => p_6_out(1),
I2 => p_6_out(3),
O => \_inferred__3/i__n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\system_axi_quad_spi_shield_0_synchronizer_ff__parameterized0\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\,
ext_spi_clk => ext_spi_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\system_axi_quad_spi_shield_0_synchronizer_ff__parameterized1\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\,
s_axi_aclk => s_axi_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\system_axi_quad_spi_shield_0_synchronizer_ff__parameterized2\
port map (
D(0) => \gnxpm_cdc.gsync_stage[2].rd_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
ext_spi_clk => ext_spi_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0)
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\system_axi_quad_spi_shield_0_synchronizer_ff__parameterized3\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
\out\(3 downto 0) => p_6_out(3 downto 0),
s_axi_aclk => s_axi_aclk
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \_inferred__2/i__n_0\,
Q => \^q\(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \_inferred__3/i__n_0\,
Q => \^q\(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
Q => p_23_out(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => p_6_out(3),
Q => \^q\(2)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc1.count_d2_reg[3]\(3),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[1]\(0),
Q => \^ram_empty_i_reg_0\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \_inferred__0/i__n_0\,
Q => \^ram_empty_i_reg_0\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.gsync_stage[2].rd_stg_inst_n_4\,
Q => \^ram_empty_i_reg_0\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => \^ram_empty_i_reg_0\(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc1.count_d3_reg[3]\(0),
I1 => \gic0.gc1.count_d3_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc1.count_d3_reg[3]\(1),
I1 => \gic0.gc1.count_d3_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc1.count_d3_reg[3]\(2),
I1 => \gic0.gc1.count_d3_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc1.count_d3_reg[3]\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\
);
\ram_empty_i_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00009009"
)
port map (
I0 => \gc1.count_d2_reg[3]\(2),
I1 => \^ram_empty_i_reg_0\(2),
I2 => \gc1.count_d2_reg[3]\(1),
I3 => \^ram_empty_i_reg_0\(1),
I4 => \ram_empty_i_i_5__0_n_0\,
O => ram_empty_i_reg
);
\ram_empty_i_i_5__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^ram_empty_i_reg_0\(0),
I1 => \gc1.count_d2_reg[3]\(0),
I2 => \^ram_empty_i_reg_0\(3),
I3 => \gc1.count_d2_reg[3]\(3),
O => \ram_empty_i_i_5__0_n_0\
);
ram_full_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(2),
I1 => \gic0.gc1.count_d2_reg[3]\(2),
I2 => p_23_out(2),
I3 => \gic0.gc1.count_d2_reg[3]\(1),
I4 => \gic0.gc1.count_d2_reg[3]\(0),
I5 => \^q\(1),
O => ram_full_i_reg_0
);
ram_full_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^q\(0),
I1 => \gic0.gc1.count_d1_reg[2]\(0),
I2 => p_23_out(2),
I3 => \gic0.gc1.count_d1_reg[2]\(1),
O => ram_full_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_clk_x_pntrs_10 is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc1.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc1.count_d3_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
ext_spi_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc1.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_clk_x_pntrs_10 : entity is "clk_x_pntrs";
end system_axi_quad_spi_shield_0_clk_x_pntrs_10;
architecture STRUCTURE of system_axi_quad_spi_shield_0_clk_x_pntrs_10 is
signal \_inferred__2/i__n_0\ : STD_LOGIC;
signal \_inferred__3/i__n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 2 downto 1 );
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_empty_i_i_5_n_0 : STD_LOGIC;
signal \^ram_empty_i_reg_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_full_i_i_5_n_0 : STD_LOGIC;
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \_inferred__2/i_\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \_inferred__3/i_\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[2]_i_1\ : label is "soft_lutpair21";
begin
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_empty_i_reg_0(3 downto 0) <= \^ram_empty_i_reg_0\(3 downto 0);
ram_full_fb_i_reg_0(3 downto 0) <= \^ram_full_fb_i_reg_0\(3 downto 0);
\_inferred__0/i_\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => gray2bin(1)
);
\_inferred__2/i_\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_6_out(1),
I1 => p_6_out(0),
I2 => p_6_out(3),
I3 => p_6_out(2),
O => \_inferred__2/i__n_0\
);
\_inferred__3/i_\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_6_out(2),
I1 => p_6_out(1),
I2 => p_6_out(3),
O => \_inferred__3/i__n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\system_axi_quad_spi_shield_0_synchronizer_ff__parameterized0_25\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3 downto 0) => wr_pntr_gc(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
s_axi_aclk => s_axi_aclk
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\system_axi_quad_spi_shield_0_synchronizer_ff__parameterized1_26\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3 downto 0) => rd_pntr_gc(3 downto 0),
ext_spi_clk => ext_spi_clk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\system_axi_quad_spi_shield_0_synchronizer_ff__parameterized2_27\
port map (
D(0) => gray2bin(2),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0),
s_axi_aclk => s_axi_aclk
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\system_axi_quad_spi_shield_0_synchronizer_ff__parameterized3_28\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
ext_spi_clk => ext_spi_clk,
\out\(3 downto 0) => p_6_out(3 downto 0)
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => \_inferred__2/i__n_0\,
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => \_inferred__3/i__n_0\,
Q => \^ram_full_fb_i_reg_0\(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
Q => \^ram_full_fb_i_reg_0\(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => p_6_out(3),
Q => \^ram_full_fb_i_reg_0\(3)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc1.count_d2_reg[3]\(0),
Q => rd_pntr_gc(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc1.count_d2_reg[3]\(1),
Q => rd_pntr_gc(1)
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc1.count_d2_reg[3]\(2),
Q => rd_pntr_gc(2)
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => rd_pntr_gc(3)
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \^ram_empty_i_reg_0\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(1),
Q => \^ram_empty_i_reg_0\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(2),
Q => \^ram_empty_i_reg_0\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => \^ram_empty_i_reg_0\(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc1.count_d3_reg[3]\(0),
I1 => \gic0.gc1.count_d3_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc1.count_d3_reg[3]\(1),
I1 => \gic0.gc1.count_d3_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc1.count_d3_reg[3]\(2),
I1 => \gic0.gc1.count_d3_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => wr_pntr_gc(0)
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => wr_pntr_gc(1)
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => wr_pntr_gc(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => \gic0.gc1.count_d3_reg[3]\(3),
Q => wr_pntr_gc(3)
);
ram_empty_i_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00009009"
)
port map (
I0 => Q(3),
I1 => \^ram_empty_i_reg_0\(3),
I2 => Q(2),
I3 => \^ram_empty_i_reg_0\(2),
I4 => ram_empty_i_i_5_n_0,
O => ram_empty_i_reg
);
ram_empty_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^ram_empty_i_reg_0\(1),
I1 => Q(1),
I2 => \^ram_empty_i_reg_0\(0),
I3 => Q(0),
O => ram_empty_i_i_5_n_0
);
\ram_full_i_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00009009"
)
port map (
I0 => \gic0.gc1.count_d2_reg[3]\(3),
I1 => \^ram_full_fb_i_reg_0\(3),
I2 => \gic0.gc1.count_d2_reg[3]\(2),
I3 => \^ram_full_fb_i_reg_0\(2),
I4 => ram_full_i_i_5_n_0,
O => ram_full_fb_i_reg
);
ram_full_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^ram_full_fb_i_reg_0\(0),
I1 => \gic0.gc1.count_d2_reg[3]\(0),
I2 => \^ram_full_fb_i_reg_0\(1),
I3 => \gic0.gc1.count_d2_reg[3]\(1),
O => ram_full_i_i_5_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_memory is
port (
\OTHER_RATIO_GENERATE.Serial_Dout_reg\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
spicr_9_lsb_to_spi_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
I93 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gc1.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
L : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ext_spi_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_memory : entity is "memory";
end system_axi_quad_spi_shield_0_memory;
architecture STRUCTURE of system_axi_quad_spi_shield_0_memory is
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_3\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_4\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_5\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_6\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_7\ : STD_LOGIC;
begin
Q(7 downto 0) <= \^q\(7 downto 0);
\OTHER_RATIO_GENERATE.Serial_Dout_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(0),
I1 => spicr_9_lsb_to_spi_clk,
I2 => \^q\(7),
O => \OTHER_RATIO_GENERATE.Serial_Dout_reg\
);
\gdm.dm_gen.dm\: entity work.system_axi_quad_spi_shield_0_dmem
port map (
AR(0) => AR(0),
E(0) => E(0),
I93 => I93,
L(3 downto 0) => L(3 downto 0),
Q(7) => \gdm.dm_gen.dm_n_0\,
Q(6) => \gdm.dm_gen.dm_n_1\,
Q(5) => \gdm.dm_gen.dm_n_2\,
Q(4) => \gdm.dm_gen.dm_n_3\,
Q(3) => \gdm.dm_gen.dm_n_4\,
Q(2) => \gdm.dm_gen.dm_n_5\,
Q(1) => \gdm.dm_gen.dm_n_6\,
Q(0) => \gdm.dm_gen.dm_n_7\,
ext_spi_clk => ext_spi_clk,
\gc1.count_d2_reg[3]\(3 downto 0) => \gc1.count_d2_reg[3]\(3 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0)
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_7\,
Q => \^q\(0)
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_6\,
Q => \^q\(1)
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_5\,
Q => \^q\(2)
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_4\,
Q => \^q\(3)
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_3\,
Q => \^q\(4)
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_2\,
Q => \^q\(5)
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_1\,
Q => \^q\(6)
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_0\,
Q => \^q\(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_memory_13 is
port (
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
ext_spi_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gc1.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
L : in STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_memory_13 : entity is "memory";
end system_axi_quad_spi_shield_0_memory_13;
architecture STRUCTURE of system_axi_quad_spi_shield_0_memory_13 is
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_3\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_4\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_5\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_6\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_7\ : STD_LOGIC;
begin
\gdm.dm_gen.dm\: entity work.system_axi_quad_spi_shield_0_dmem_19
port map (
AR(0) => AR(0),
E(0) => E(0),
L(3 downto 0) => L(3 downto 0),
Q(7 downto 0) => Q(7 downto 0),
ext_spi_clk => ext_spi_clk,
\gc1.count_d2_reg[3]\(3 downto 0) => \gc1.count_d2_reg[3]\(3 downto 0),
\goreg_dm.dout_i_reg[7]\(7) => \gdm.dm_gen.dm_n_0\,
\goreg_dm.dout_i_reg[7]\(6) => \gdm.dm_gen.dm_n_1\,
\goreg_dm.dout_i_reg[7]\(5) => \gdm.dm_gen.dm_n_2\,
\goreg_dm.dout_i_reg[7]\(4) => \gdm.dm_gen.dm_n_3\,
\goreg_dm.dout_i_reg[7]\(3) => \gdm.dm_gen.dm_n_4\,
\goreg_dm.dout_i_reg[7]\(2) => \gdm.dm_gen.dm_n_5\,
\goreg_dm.dout_i_reg[7]\(1) => \gdm.dm_gen.dm_n_6\,
\goreg_dm.dout_i_reg[7]\(0) => \gdm.dm_gen.dm_n_7\,
ram_empty_fb_i_reg(0) => ram_empty_fb_i_reg(0),
s_axi_aclk => s_axi_aclk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_7\,
Q => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\(0)
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_6\,
Q => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\(1)
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_5\,
Q => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\(2)
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_4\,
Q => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\(3)
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_3\,
Q => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\(4)
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_2\,
Q => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\(5)
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_1\,
Q => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\(6)
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_0\,
Q => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_rd_logic is
port (
\out\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ext_spi_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\spisel_d1_reg__0\ : in STD_LOGIC;
\gc1.count_d2_reg[2]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_rd_logic : entity is "rd_logic";
end system_axi_quad_spi_shield_0_rd_logic;
architecture STRUCTURE of system_axi_quad_spi_shield_0_rd_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_2_out : STD_LOGIC;
signal ram_empty_i0 : STD_LOGIC;
signal rpntr_n_7 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.system_axi_quad_spi_shield_0_rd_fwft
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
ext_spi_clk => ext_spi_clk,
\gc1.count_d2_reg[2]\ => \gc1.count_d2_reg[2]\,
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => rpntr_n_7,
\goreg_dm.dout_i_reg[7]\(0) => \goreg_dm.dout_i_reg[7]\(0),
\out\ => \out\,
ram_empty_fb_i_reg => p_2_out,
ram_empty_i0 => ram_empty_i0,
\spisel_d1_reg__0\ => \spisel_d1_reg__0\
);
\gras.rsts\: entity work.system_axi_quad_spi_shield_0_rd_status_flags_as
port map (
AR(0) => AR(0),
ext_spi_clk => ext_spi_clk,
\out\ => p_2_out,
ram_empty_i0 => ram_empty_i0
);
rpntr: entity work.system_axi_quad_spi_shield_0_rd_bin_cntr
port map (
AR(0) => AR(0),
D(2 downto 0) => D(2 downto 0),
E(0) => \^e\(0),
Q(3 downto 0) => Q(3 downto 0),
ext_spi_clk => ext_spi_clk,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0),
ram_empty_i_reg => rpntr_n_7
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_rd_logic_11 is
port (
\out\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\icount_out_reg[3]\ : out STD_LOGIC;
Receive_ip2bus_error0 : out STD_LOGIC;
\gnxpm_cdc.rd_pntr_gc_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\ : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
p_5_in : in STD_LOGIC;
\gc1.count_d2_reg[3]\ : in STD_LOGIC;
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_rd_logic_11 : entity is "rd_logic";
end system_axi_quad_spi_shield_0_rd_logic_11;
architecture STRUCTURE of system_axi_quad_spi_shield_0_rd_logic_11 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_2_out : STD_LOGIC;
signal ram_empty_i0 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.system_axi_quad_spi_shield_0_rd_fwft_22
port map (
AR(0) => AR(0),
Bus_RNW_reg => Bus_RNW_reg,
E(0) => \^e\(0),
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\ => \FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\,
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\ => \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\,
Receive_ip2bus_error0 => Receive_ip2bus_error0,
\goreg_dm.dout_i_reg[7]\(0) => \goreg_dm.dout_i_reg[7]\(0),
\icount_out_reg[3]\ => \icount_out_reg[3]\,
\out\ => \out\,
p_5_in => p_5_in,
ram_empty_fb_i_reg => p_2_out,
s_axi_aclk => s_axi_aclk
);
\gras.rsts\: entity work.system_axi_quad_spi_shield_0_rd_status_flags_as_23
port map (
AR(0) => AR(0),
\out\ => p_2_out,
ram_empty_i0 => ram_empty_i0,
s_axi_aclk => s_axi_aclk
);
rpntr: entity work.system_axi_quad_spi_shield_0_rd_bin_cntr_24
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3 downto 0) => Q(3 downto 0),
\gc1.count_d2_reg[3]_0\ => \gc1.count_d2_reg[3]\,
\gnxpm_cdc.rd_pntr_gc_reg[2]\(2 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[2]\(2 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0),
ram_empty_i0 => ram_empty_i0,
s_axi_aclk => s_axi_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc1.count_reg[0]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_i_reg : out STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
reset_TxFIFO_ptr_int : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end system_axi_quad_spi_shield_0_reset_blk_ramfifo;
architecture STRUCTURE of system_axi_quad_spi_shield_0_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc1.count_reg[0]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.system_axi_quad_spi_shield_0_synchronizer_ff
port map (
ext_spi_clk => ext_spi_clk,
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.system_axi_quad_spi_shield_0_synchronizer_ff_3
port map (
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out,
s_axi_aclk => s_axi_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.system_axi_quad_spi_shield_0_synchronizer_ff_4
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
ext_spi_clk => ext_spi_clk,
in0(0) => rd_rst_asreg,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.system_axi_quad_spi_shield_0_synchronizer_ff_5
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
in0(0) => wr_rst_asreg,
\out\ => p_8_out,
s_axi_aclk => s_axi_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => '0',
PRE => reset_TxFIFO_ptr_int,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => rst_rd_reg1,
PRE => reset_TxFIFO_ptr_int,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => reset_TxFIFO_ptr_int,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => reset_TxFIFO_ptr_int,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_reset_blk_ramfifo_14 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc1.count_reg[0]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
rx_fifo_reset : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_reset_blk_ramfifo_14 : entity is "reset_blk_ramfifo";
end system_axi_quad_spi_shield_0_reset_blk_ramfifo_14;
architecture STRUCTURE of system_axi_quad_spi_shield_0_reset_blk_ramfifo_14 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc1.count_reg[0]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.system_axi_quad_spi_shield_0_synchronizer_ff_15
port map (
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out,
s_axi_aclk => s_axi_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.system_axi_quad_spi_shield_0_synchronizer_ff_16
port map (
ext_spi_clk => ext_spi_clk,
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.system_axi_quad_spi_shield_0_synchronizer_ff_17
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
in0(0) => rd_rst_asreg,
\out\ => p_7_out,
s_axi_aclk => s_axi_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.system_axi_quad_spi_shield_0_synchronizer_ff_18
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
ext_spi_clk => ext_spi_clk,
in0(0) => wr_rst_asreg,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => rx_fifo_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => rx_fifo_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => '0',
PRE => rx_fifo_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => rst_wr_reg1,
PRE => rx_fifo_reset,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_wr_logic is
port (
\gic0.gc1.count_reg[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc1.count_d2_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[0]\ : in STD_LOGIC;
p_6_in : in STD_LOGIC;
ip2Bus_WrAck_core_reg_1 : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_wr_logic : entity is "wr_logic";
end system_axi_quad_spi_shield_0_wr_logic;
architecture STRUCTURE of system_axi_quad_spi_shield_0_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wpntr_n_0 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.system_axi_quad_spi_shield_0_wr_status_flags_as
port map (
Bus_RNW_reg => Bus_RNW_reg,
E(0) => \^e\(0),
\gic0.gc1.count_d2_reg[0]\ => wpntr_n_0,
\gic0.gc1.count_reg[0]\ => \gic0.gc1.count_reg[0]\,
ip2Bus_WrAck_core_reg_1 => ip2Bus_WrAck_core_reg_1,
\out\ => \out\,
p_6_in => p_6_in,
s_axi_aclk => s_axi_aclk
);
wpntr: entity work.system_axi_quad_spi_shield_0_wr_bin_cntr
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc1.count_d2_reg[2]_0\(1 downto 0) => \gic0.gc1.count_d2_reg[2]\(1 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[0]\ => \gnxpm_cdc.rd_pntr_bin_reg[0]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\ => \gnxpm_cdc.rd_pntr_bin_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]_0\(2 downto 0) => \gnxpm_cdc.rd_pntr_bin_reg[3]_0\(2 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => \grstd1.grst_full.grst_f.rst_d3_reg\,
ram_full_i_reg => wpntr_n_0,
s_axi_aclk => s_axi_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_wr_logic_12 is
port (
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
Rx_FIFO_Full_Fifo : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ext_spi_clk : in STD_LOGIC;
\out\ : in STD_LOGIC;
spiXfer_done_int : in STD_LOGIC;
\gic0.gc1.count_d2_reg[3]\ : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
scndry_out : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_wr_logic_12 : entity is "wr_logic";
end system_axi_quad_spi_shield_0_wr_logic_12;
architecture STRUCTURE of system_axi_quad_spi_shield_0_wr_logic_12 is
signal wpntr_n_0 : STD_LOGIC;
begin
\gwas.wsts\: entity work.system_axi_quad_spi_shield_0_wr_status_flags_as_20
port map (
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ => \FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\,
Rx_FIFO_Full_Fifo => Rx_FIFO_Full_Fifo,
ext_spi_clk => ext_spi_clk,
\gic0.gc1.count_d2_reg[3]\ => \gic0.gc1.count_d2_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\ => wpntr_n_0,
\grstd1.grst_full.grst_f.rst_d3_reg\ => \grstd1.grst_full.grst_f.rst_d3_reg\,
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg,
scndry_out => scndry_out,
spiXfer_done_int => spiXfer_done_int
);
wpntr: entity work.system_axi_quad_spi_shield_0_wr_bin_cntr_21
port map (
AR(0) => AR(0),
E(0) => E(0),
Q(3 downto 0) => Q(3 downto 0),
ext_spi_clk => ext_spi_clk,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
ram_full_fb_i_reg => wpntr_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_slave_attachment is
port (
SR : out STD_LOGIC;
p_3_in : out STD_LOGIC;
Receive_ip2bus_error_reg : out STD_LOGIC;
Transmit_ip2bus_error_reg : out STD_LOGIC;
\SPICR_data_int_reg[0]\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
ip2Bus_WrAck_intr_reg_hole_d1_reg : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
\icount_out_reg[1]\ : out STD_LOGIC;
SPICR_data_int_reg0 : out STD_LOGIC;
bus2ip_wrce_int : out STD_LOGIC_VECTOR ( 0 to 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 10 downto 0 );
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[31]\ : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : out STD_LOGIC;
modf_reg : out STD_LOGIC;
Transmit_ip2bus_error0 : out STD_LOGIC;
IP2Bus_Error_1 : out STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_WrAck_reg\ : out STD_LOGIC;
reset_trig0 : out STD_LOGIC;
sw_rst_cond : out STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg\ : out STD_LOGIC;
wr_ce_or_reduce_core_cmb : out STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole0 : out STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole0 : out STD_LOGIC;
intr_controller_rd_ce_or_reduce : out STD_LOGIC;
rd_ce_or_reduce_core_cmb : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg_0 : out STD_LOGIC;
\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_aclk : in STD_LOGIC;
IP2Bus_Error : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
p_16_out : in STD_LOGIC;
p_15_out : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
ip2Bus_WrAck_core_reg_1 : in STD_LOGIC;
\out\ : in STD_LOGIC;
irpt_rdack_d1 : in STD_LOGIC;
ipif_glbl_irpt_enable_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
rx_fifo_count : in STD_LOGIC_VECTOR ( 1 downto 0 );
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2\ : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ : in STD_LOGIC;
SPISSR_frm_axi_clk : in STD_LOGIC;
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_0\ : in STD_LOGIC;
p_1_in35_in : in STD_LOGIC;
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_1\ : in STD_LOGIC;
p_1_in32_in : in STD_LOGIC;
p_1_in29_in : in STD_LOGIC;
p_1_in26_in : in STD_LOGIC;
p_1_in23_in : in STD_LOGIC;
p_1_in20_in : in STD_LOGIC;
p_1_in17_in : in STD_LOGIC;
spicr_8_tr_inhibit_frm_axi_clk : in STD_LOGIC;
p_1_in14_in : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
\goreg_dm.dout_i_reg[7]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
scndry_out : in STD_LOGIC;
spicr_1_spe_frm_axi_clk : in STD_LOGIC;
Tx_FIFO_Empty_SPISR_to_axi_clk : in STD_LOGIC;
spicr_2_mst_n_slv_frm_axi_clk : in STD_LOGIC;
empty_fwft_i_reg : in STD_LOGIC;
spicr_4_cpha_frm_axi_clk : in STD_LOGIC;
sr_3_MODF_int : in STD_LOGIC;
\LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\ : in STD_LOGIC;
spicr_5_txfifo_rst_frm_axi_clk : in STD_LOGIC;
ip2Bus_RdAck_core_reg : in STD_LOGIC;
spicr_6_rxfifo_rst_frm_axi_clk : in STD_LOGIC;
spicr_7_ss_frm_axi_clk : in STD_LOGIC;
rx_fifo_empty_i : in STD_LOGIC;
spicr_0_loop_frm_axi_clk : in STD_LOGIC;
Tx_FIFO_Full_int : in STD_LOGIC;
tx_fifo_count : in STD_LOGIC_VECTOR ( 0 to 0 );
spicr_3_cpol_frm_axi_clk : in STD_LOGIC;
spicr_9_lsb_frm_axi_clk : in STD_LOGIC;
Receive_ip2bus_error_reg_0 : in STD_LOGIC;
p_4_in : in STD_LOGIC;
sw_rst_cond_d1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 4 downto 0 );
ip2Bus_WrAck_core_reg_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\ : in STD_LOGIC_VECTOR ( 10 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_slave_attachment : entity is "slave_attachment";
end system_axi_quad_spi_shield_0_slave_attachment;
architecture STRUCTURE of system_axi_quad_spi_shield_0_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1_n_0\ : STD_LOGIC;
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_Error_i_2_n_0\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC;
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[4]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[5]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[6]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[6]_i_2_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i_reg_n_0_[2]\ : STD_LOGIC;
signal \bus2ip_addr_i_reg_n_0_[3]\ : STD_LOGIC;
signal \bus2ip_addr_i_reg_n_0_[4]\ : STD_LOGIC;
signal \bus2ip_addr_i_reg_n_0_[5]\ : STD_LOGIC;
signal \bus2ip_addr_i_reg_n_0_[6]\ : STD_LOGIC;
signal bus2ip_rnw_i06_out : STD_LOGIC;
signal bus2ip_rnw_i_reg_n_0 : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_read_i_2_n_0 : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal p_0_in1_in : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 1 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \s_axi_bresp_i[1]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal s_axi_rdata_i : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state[0]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[4]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \bus2ip_addr_i[3]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair15";
begin
SR <= \^sr\;
s_axi_arready <= \^s_axi_arready\;
s_axi_bresp(0) <= \^s_axi_bresp\(0);
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(4)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(1),
I1 => state(0),
O => \INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1_n_0\
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4),
O => plusOp(5)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => \INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1_n_0\
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => \INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1_n_0\
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => \INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1_n_0\
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => \INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1_n_0\
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(4),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4),
R => \INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1_n_0\
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(5),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5),
R => \INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1_n_0\
);
I_DECODER: entity work.system_axi_quad_spi_shield_0_address_decoder
port map (
D(10 downto 0) => D(10 downto 0),
E(0) => E(0),
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\,
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\ => \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(5 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5 downto 0),
IP2Bus_Error_1 => IP2Bus_Error_1,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[31]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[31]\,
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_WrAck_reg\ => \LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_WrAck_reg\,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg\ => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg\,
\LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\ => \LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\,
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2\ => \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2\,
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_0\ => \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_0\,
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_1\ => \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_1\,
Q => start2,
Receive_ip2bus_error_reg => Receive_ip2bus_error_reg,
Receive_ip2bus_error_reg_0 => Receive_ip2bus_error_reg_0,
SPICR_data_int_reg0 => SPICR_data_int_reg0,
\SPICR_data_int_reg[0]\ => \SPICR_data_int_reg[0]\,
\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]\ => \SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]\,
SPISSR_frm_axi_clk => SPISSR_frm_axi_clk,
Transmit_ip2bus_error0 => Transmit_ip2bus_error0,
Transmit_ip2bus_error_reg => Transmit_ip2bus_error_reg,
Tx_FIFO_Empty_SPISR_to_axi_clk => Tx_FIFO_Empty_SPISR_to_axi_clk,
Tx_FIFO_Full_int => Tx_FIFO_Full_int,
\bus2ip_addr_i_reg[6]\(4) => \bus2ip_addr_i_reg_n_0_[6]\,
\bus2ip_addr_i_reg[6]\(3) => \bus2ip_addr_i_reg_n_0_[5]\,
\bus2ip_addr_i_reg[6]\(2) => \bus2ip_addr_i_reg_n_0_[4]\,
\bus2ip_addr_i_reg[6]\(1) => \bus2ip_addr_i_reg_n_0_[3]\,
\bus2ip_addr_i_reg[6]\(0) => \bus2ip_addr_i_reg_n_0_[2]\,
bus2ip_rnw_i_reg => bus2ip_rnw_i_reg_n_0,
bus2ip_rnw_i_reg_0 => \LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_Error_i_2_n_0\,
bus2ip_wrce_int(0) => bus2ip_wrce_int(0),
empty_fwft_i_reg => empty_fwft_i_reg,
\goreg_dm.dout_i_reg[7]\(6 downto 0) => \goreg_dm.dout_i_reg[7]\(6 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gpregsm1.curr_fwft_state_reg[1]\,
\icount_out_reg[1]\ => \icount_out_reg[1]\,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_controller_rd_ce_or_reduce => intr_controller_rd_ce_or_reduce,
ip2Bus_RdAck_core_reg => ip2Bus_RdAck_core_reg,
ip2Bus_RdAck_intr_reg_hole0 => ip2Bus_RdAck_intr_reg_hole0,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_core_reg_1 => ip2Bus_WrAck_core_reg_1,
ip2Bus_WrAck_core_reg_d1 => ip2Bus_WrAck_core_reg_d1,
ip2Bus_WrAck_intr_reg_hole0 => ip2Bus_WrAck_intr_reg_hole0,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1_reg => ip2Bus_WrAck_intr_reg_hole_d1_reg,
\ip_irpt_enable_reg_reg[8]\(8 downto 0) => Q(8 downto 0),
ipif_glbl_irpt_enable_reg => ipif_glbl_irpt_enable_reg,
ipif_glbl_irpt_enable_reg_reg => ipif_glbl_irpt_enable_reg_reg,
ipif_glbl_irpt_enable_reg_reg_0 => ipif_glbl_irpt_enable_reg_reg_0,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
modf_reg => modf_reg,
\out\ => \out\,
p_15_out => p_15_out,
p_16_out => p_16_out,
p_1_in14_in => p_1_in14_in,
p_1_in17_in => p_1_in17_in,
p_1_in20_in => p_1_in20_in,
p_1_in23_in => p_1_in23_in,
p_1_in26_in => p_1_in26_in,
p_1_in29_in => p_1_in29_in,
p_1_in32_in => p_1_in32_in,
p_1_in35_in => p_1_in35_in,
p_3_in => p_3_in,
p_4_in => p_4_in,
rd_ce_or_reduce_core_cmb => rd_ce_or_reduce_core_cmb,
reset_trig0 => reset_trig0,
rx_fifo_count(1 downto 0) => rx_fifo_count(1 downto 0),
rx_fifo_empty_i => rx_fifo_empty_i,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => \^s_axi_arready\,
s_axi_wdata(1) => s_axi_wdata(4),
s_axi_wdata(0) => s_axi_wdata(0),
s_axi_wready => \^s_axi_wready\,
s_axi_wstrb(0) => s_axi_wstrb(1),
scndry_out => scndry_out,
spicr_0_loop_frm_axi_clk => spicr_0_loop_frm_axi_clk,
spicr_1_spe_frm_axi_clk => spicr_1_spe_frm_axi_clk,
spicr_2_mst_n_slv_frm_axi_clk => spicr_2_mst_n_slv_frm_axi_clk,
spicr_3_cpol_frm_axi_clk => spicr_3_cpol_frm_axi_clk,
spicr_4_cpha_frm_axi_clk => spicr_4_cpha_frm_axi_clk,
spicr_5_txfifo_rst_frm_axi_clk => spicr_5_txfifo_rst_frm_axi_clk,
spicr_6_rxfifo_rst_frm_axi_clk => spicr_6_rxfifo_rst_frm_axi_clk,
spicr_7_ss_frm_axi_clk => spicr_7_ss_frm_axi_clk,
spicr_8_tr_inhibit_frm_axi_clk => spicr_8_tr_inhibit_frm_axi_clk,
spicr_9_lsb_frm_axi_clk => spicr_9_lsb_frm_axi_clk,
sr_3_MODF_int => sr_3_MODF_int,
sw_rst_cond => sw_rst_cond,
sw_rst_cond_d1 => sw_rst_cond_d1,
tx_fifo_count(0) => tx_fifo_count(0),
wr_ce_or_reduce_core_cmb => wr_ce_or_reduce_core_cmb
);
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_Error_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000E0000000000"
)
port map (
I0 => s_axi_wstrb(0),
I1 => bus2ip_rnw_i_reg_n_0,
I2 => s_axi_wdata(2),
I3 => s_axi_wdata(3),
I4 => s_axi_wdata(0),
I5 => s_axi_wdata(1),
O => \LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_Error_i_2_n_0\
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEF0020"
)
port map (
I0 => s_axi_araddr(0),
I1 => state(1),
I2 => s_axi_arvalid,
I3 => state(0),
I4 => s_axi_awaddr(0),
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEF0020"
)
port map (
I0 => s_axi_araddr(1),
I1 => state(1),
I2 => s_axi_arvalid,
I3 => state(0),
I4 => s_axi_awaddr(1),
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEF0020"
)
port map (
I0 => s_axi_araddr(2),
I1 => state(1),
I2 => s_axi_arvalid,
I3 => state(0),
I4 => s_axi_awaddr(2),
O => \bus2ip_addr_i[4]_i_1_n_0\
);
\bus2ip_addr_i[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEF0020"
)
port map (
I0 => s_axi_araddr(3),
I1 => state(1),
I2 => s_axi_arvalid,
I3 => state(0),
I4 => s_axi_awaddr(3),
O => \bus2ip_addr_i[5]_i_1_n_0\
);
\bus2ip_addr_i[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000EA"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_wvalid,
I2 => s_axi_awvalid,
I3 => state(1),
I4 => state(0),
O => \bus2ip_addr_i[6]_i_1_n_0\
);
\bus2ip_addr_i[6]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEF0020"
)
port map (
I0 => s_axi_araddr(4),
I1 => state(1),
I2 => s_axi_arvalid,
I3 => state(0),
I4 => s_axi_awaddr(4),
O => \bus2ip_addr_i[6]_i_2_n_0\
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[6]_i_1_n_0\,
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => \bus2ip_addr_i_reg_n_0_[2]\,
R => \^sr\
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[6]_i_1_n_0\,
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => \bus2ip_addr_i_reg_n_0_[3]\,
R => \^sr\
);
\bus2ip_addr_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[6]_i_1_n_0\,
D => \bus2ip_addr_i[4]_i_1_n_0\,
Q => \bus2ip_addr_i_reg_n_0_[4]\,
R => \^sr\
);
\bus2ip_addr_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[6]_i_1_n_0\,
D => \bus2ip_addr_i[5]_i_1_n_0\,
Q => \bus2ip_addr_i_reg_n_0_[5]\,
R => \^sr\
);
\bus2ip_addr_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[6]_i_1_n_0\,
D => \bus2ip_addr_i[6]_i_2_n_0\,
Q => \bus2ip_addr_i_reg_n_0_[6]\,
R => \^sr\
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => state(1),
I1 => s_axi_arvalid,
I2 => state(0),
O => bus2ip_rnw_i06_out
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[6]_i_1_n_0\,
D => bus2ip_rnw_i06_out,
Q => bus2ip_rnw_i_reg_n_0,
R => \^sr\
);
is_read_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => s_axi_arvalid,
I1 => state(1),
I2 => is_read_i_2_n_0,
I3 => is_read,
O => is_read_i_1_n_0
);
is_read_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
I4 => state(0),
I5 => state(1),
O => is_read_i_2_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => \^sr\
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0040FFFF00400000"
)
port map (
I0 => state(1),
I1 => s_axi_wvalid,
I2 => s_axi_awvalid,
I3 => s_axi_arvalid,
I4 => is_read_i_2_n_0,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => \^sr\
);
rst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => p_0_in1_in
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in1_in,
Q => \^sr\,
R => '0'
);
\s_axi_bresp_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => IP2Bus_Error,
I1 => state(1),
I2 => state(0),
I3 => \^s_axi_bresp\(0),
O => \s_axi_bresp_i[1]_i_1_n_0\
);
\s_axi_bresp_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \s_axi_bresp_i[1]_i_1_n_0\,
Q => \^s_axi_bresp\(0),
R => \^sr\
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"5D550C00"
)
port map (
I0 => s_axi_bready,
I1 => state(1),
I2 => state(0),
I3 => \^s_axi_wready\,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => \^sr\
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => s_axi_rdata_i
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(0),
Q => s_axi_rdata(0),
R => \^sr\
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(1),
Q => s_axi_rdata(1),
R => \^sr\
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(2),
Q => s_axi_rdata(2),
R => \^sr\
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(10),
Q => s_axi_rdata(10),
R => \^sr\
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(3),
Q => s_axi_rdata(3),
R => \^sr\
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(4),
Q => s_axi_rdata(4),
R => \^sr\
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(5),
Q => s_axi_rdata(5),
R => \^sr\
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(6),
Q => s_axi_rdata(6),
R => \^sr\
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(7),
Q => s_axi_rdata(7),
R => \^sr\
);
\s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(8),
Q => s_axi_rdata(8),
R => \^sr\
);
\s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(9),
Q => s_axi_rdata(9),
R => \^sr\
);
\s_axi_rresp_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Error,
Q => s_axi_rresp(0),
R => \^sr\
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"5D550C00"
)
port map (
I0 => s_axi_rready,
I1 => state(0),
I2 => state(1),
I3 => \^s_axi_arready\,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => \^sr\
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00000F08"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_awvalid,
I2 => state(0),
I3 => s_axi_arvalid,
I4 => state(1),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => \^sr\
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4F4FFF0"
)
port map (
I0 => state(0),
I1 => \^s_axi_wready\,
I2 => \state[0]_i_2_n_0\,
I3 => s_axi_arvalid,
I4 => state(1),
O => p_0_out(0)
);
\state[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"44444CCC4CCC4CCC"
)
port map (
I0 => state(1),
I1 => state(0),
I2 => \^s_axi_bvalid\,
I3 => s_axi_bready,
I4 => \^s_axi_rvalid\,
I5 => s_axi_rready,
O => \state[0]_i_2_n_0\
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"E2CCE2FF"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(1),
I2 => \state[1]_i_2_n_0\,
I3 => state(0),
I4 => \state[1]_i_3_n_0\,
O => p_0_out(1)
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0777"
)
port map (
I0 => \^s_axi_bvalid\,
I1 => s_axi_bready,
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"BF"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(0),
Q => state(0),
R => \^sr\
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(1),
Q => state(1),
R => \^sr\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_fifo_generator_ramfifo is
port (
\out\ : out STD_LOGIC;
\gic0.gc1.count_reg[0]\ : out STD_LOGIC;
\OTHER_RATIO_GENERATE.Serial_Dout_reg\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
ext_spi_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
reset_TxFIFO_ptr_int : in STD_LOGIC;
\spisel_d1_reg__0\ : in STD_LOGIC;
p_6_in : in STD_LOGIC;
ip2Bus_WrAck_core_reg_1 : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
spicr_9_lsb_to_spi_clk : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end system_axi_quad_spi_shield_0_fifo_generator_ramfifo;
architecture STRUCTURE of system_axi_quad_spi_shield_0_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gcx.clkx/_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_8\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_9\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_1\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_3\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 1 );
signal p_18_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC;
signal p_5_out_0 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal rstblk_n_6 : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.system_axi_quad_spi_shield_0_clk_x_pntrs
port map (
AR(0) => wr_rst_i(0),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_3\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_4\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_5\,
Q(2) => p_23_out(3),
Q(1 downto 0) => p_23_out(1 downto 0),
\Q_reg_reg[1]\(0) => \gntv_or_sync_fifo.gcx.clkx/_n_0\,
ext_spi_clk => ext_spi_clk,
\gc1.count_d2_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gic0.gc1.count_d1_reg[2]\(1) => wr_pntr_plus2(2),
\gic0.gc1.count_d1_reg[2]\(0) => wr_pntr_plus2(0),
\gic0.gc1.count_d2_reg[3]\(2 downto 0) => p_13_out(3 downto 1),
\gic0.gc1.count_d3_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_5_out_0(3 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_9\,
ram_empty_i_reg_0(3 downto 0) => p_22_out(3 downto 0),
ram_full_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_i_reg_0 => \gntv_or_sync_fifo.gcx.clkx_n_8\,
s_axi_aclk => s_axi_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_5_out_0(1),
I1 => p_5_out_0(0),
I2 => p_5_out_0(3),
I3 => p_5_out_0(2),
O => \gntv_or_sync_fifo.gcx.clkx/_n_0\
);
\gntv_or_sync_fifo.gl0.rd\: entity work.system_axi_quad_spi_shield_0_rd_logic
port map (
AR(0) => rd_rst_i(2),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_3\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_4\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_5\,
E(0) => \gntv_or_sync_fifo.gl0.rd_n_1\,
Q(3 downto 0) => p_0_out(3 downto 0),
ext_spi_clk => ext_spi_clk,
\gc1.count_d2_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_9\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => p_22_out(3 downto 0),
\goreg_dm.dout_i_reg[7]\(0) => p_5_out,
\out\ => \out\,
\spisel_d1_reg__0\ => \spisel_d1_reg__0\
);
\gntv_or_sync_fifo.gl0.wr\: entity work.system_axi_quad_spi_shield_0_wr_logic
port map (
AR(0) => wr_rst_i(1),
Bus_RNW_reg => Bus_RNW_reg,
E(0) => p_18_out,
Q(2 downto 0) => p_13_out(3 downto 1),
\gic0.gc1.count_d2_reg[2]\(1) => wr_pntr_plus2(2),
\gic0.gc1.count_d2_reg[2]\(0) => wr_pntr_plus2(0),
\gic0.gc1.count_reg[0]\ => \gic0.gc1.count_reg[0]\,
\gnxpm_cdc.rd_pntr_bin_reg[0]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_8\,
\gnxpm_cdc.rd_pntr_bin_reg[3]_0\(2) => p_23_out(3),
\gnxpm_cdc.rd_pntr_bin_reg[3]_0\(1 downto 0) => p_23_out(1 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => rstblk_n_6,
ip2Bus_WrAck_core_reg_1 => ip2Bus_WrAck_core_reg_1,
\out\ => rst_full_ff_i,
p_6_in => p_6_in,
s_axi_aclk => s_axi_aclk
);
\gntv_or_sync_fifo.mem\: entity work.system_axi_quad_spi_shield_0_memory
port map (
AR(0) => rd_rst_i(0),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_1\,
I93 => p_18_out,
L(3 downto 0) => p_12_out(3 downto 0),
\OTHER_RATIO_GENERATE.Serial_Dout_reg\ => \OTHER_RATIO_GENERATE.Serial_Dout_reg\,
Q(7 downto 0) => Q(7 downto 0),
ext_spi_clk => ext_spi_clk,
\gc1.count_d2_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => p_5_out,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
spicr_9_lsb_to_spi_clk => spicr_9_lsb_to_spi_clk
);
rstblk: entity work.system_axi_quad_spi_shield_0_reset_blk_ramfifo
port map (
ext_spi_clk => ext_spi_clk,
\gc1.count_reg[0]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_i_reg => rstblk_n_6,
reset_TxFIFO_ptr_int => reset_TxFIFO_ptr_int,
s_axi_aclk => s_axi_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_fifo_generator_ramfifo_9 is
port (
\out\ : out STD_LOGIC;
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
\icount_out_reg[3]\ : out STD_LOGIC;
Receive_ip2bus_error0 : out STD_LOGIC;
Rx_FIFO_Full_Fifo : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
rx_fifo_reset : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\ : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
p_5_in : in STD_LOGIC;
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\ : in STD_LOGIC;
spiXfer_done_int : in STD_LOGIC;
scndry_out : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_fifo_generator_ramfifo_9 : entity is "fifo_generator_ramfifo";
end system_axi_quad_spi_shield_0_fifo_generator_ramfifo_9;
architecture STRUCTURE of system_axi_quad_spi_shield_0_fifo_generator_ramfifo_9 is
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_9\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_1\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC;
signal p_5_out_0 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal rstblk_n_6 : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.system_axi_quad_spi_shield_0_clk_x_pntrs_10
port map (
AR(0) => wr_rst_i(0),
D(0) => gray2bin(0),
Q(3 downto 0) => p_0_out(3 downto 0),
ext_spi_clk => ext_spi_clk,
\gc1.count_d2_reg[3]\(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
\gc1.count_d2_reg[3]\(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
\gc1.count_d2_reg[3]\(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
\gic0.gc1.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gic0.gc1.count_d3_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_5_out_0(3 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_empty_i_reg_0(3 downto 0) => p_22_out(3 downto 0),
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_9\,
ram_full_fb_i_reg_0(3 downto 0) => p_23_out(3 downto 0),
s_axi_aclk => s_axi_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_5_out_0(1),
I1 => p_5_out_0(0),
I2 => p_5_out_0(3),
I3 => p_5_out_0(2),
O => gray2bin(0)
);
\gntv_or_sync_fifo.gl0.rd\: entity work.system_axi_quad_spi_shield_0_rd_logic_11
port map (
AR(0) => rd_rst_i(2),
Bus_RNW_reg => Bus_RNW_reg,
E(0) => \gntv_or_sync_fifo.gl0.rd_n_1\,
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\ => \FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\,
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\ => \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\,
Q(3 downto 0) => p_0_out(3 downto 0),
Receive_ip2bus_error0 => Receive_ip2bus_error0,
\gc1.count_d2_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\gnxpm_cdc.rd_pntr_gc_reg[2]\(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
\gnxpm_cdc.rd_pntr_gc_reg[2]\(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
\gnxpm_cdc.rd_pntr_gc_reg[2]\(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => p_22_out(3 downto 0),
\goreg_dm.dout_i_reg[7]\(0) => p_5_out,
\icount_out_reg[3]\ => \icount_out_reg[3]\,
\out\ => \out\,
p_5_in => p_5_in,
s_axi_aclk => s_axi_aclk
);
\gntv_or_sync_fifo.gl0.wr\: entity work.system_axi_quad_spi_shield_0_wr_logic_12
port map (
AR(0) => wr_rst_i(1),
E(0) => E(0),
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ => \FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\,
Q(3 downto 0) => p_13_out(3 downto 0),
Rx_FIFO_Full_Fifo => Rx_FIFO_Full_Fifo,
ext_spi_clk => ext_spi_clk,
\gic0.gc1.count_d2_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_9\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(3 downto 0) => p_23_out(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => rstblk_n_6,
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => ram_full_fb_i_reg,
scndry_out => scndry_out,
spiXfer_done_int => spiXfer_done_int
);
\gntv_or_sync_fifo.mem\: entity work.system_axi_quad_spi_shield_0_memory_13
port map (
AR(0) => rd_rst_i(0),
E(0) => E(0),
L(3 downto 0) => p_12_out(3 downto 0),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\(7 downto 0) => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\(7 downto 0),
Q(7 downto 0) => Q(7 downto 0),
ext_spi_clk => ext_spi_clk,
\gc1.count_d2_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => p_5_out,
ram_empty_fb_i_reg(0) => \gntv_or_sync_fifo.gl0.rd_n_1\,
s_axi_aclk => s_axi_aclk
);
rstblk: entity work.system_axi_quad_spi_shield_0_reset_blk_ramfifo_14
port map (
ext_spi_clk => ext_spi_clk,
\gc1.count_reg[0]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => rstblk_n_6,
rx_fifo_reset => rx_fifo_reset,
s_axi_aclk => s_axi_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_axi_lite_ipif is
port (
bus2ip_reset_ipif_inverted : out STD_LOGIC;
p_3_in : out STD_LOGIC;
p_5_in : out STD_LOGIC;
p_6_in : out STD_LOGIC;
p_8_in : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
Bus_RNW_reg : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
ip2Bus_WrAck_intr_reg_hole_d1_reg : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
\icount_out_reg[1]\ : out STD_LOGIC;
SPICR_data_int_reg0 : out STD_LOGIC;
bus2ip_wrce_int : out STD_LOGIC_VECTOR ( 0 to 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 10 downto 0 );
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[31]\ : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : out STD_LOGIC;
modf_reg : out STD_LOGIC;
Transmit_ip2bus_error0 : out STD_LOGIC;
IP2Bus_Error_1 : out STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_WrAck_reg\ : out STD_LOGIC;
reset_trig0 : out STD_LOGIC;
sw_rst_cond : out STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg\ : out STD_LOGIC;
wr_ce_or_reduce_core_cmb : out STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole0 : out STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole0 : out STD_LOGIC;
intr_controller_rd_ce_or_reduce : out STD_LOGIC;
rd_ce_or_reduce_core_cmb : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_aclk : in STD_LOGIC;
IP2Bus_Error : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
p_16_out : in STD_LOGIC;
p_15_out : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
ip2Bus_WrAck_core_reg_1 : in STD_LOGIC;
\out\ : in STD_LOGIC;
irpt_rdack_d1 : in STD_LOGIC;
ipif_glbl_irpt_enable_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
rx_fifo_count : in STD_LOGIC_VECTOR ( 1 downto 0 );
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2\ : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ : in STD_LOGIC;
SPISSR_frm_axi_clk : in STD_LOGIC;
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_0\ : in STD_LOGIC;
p_1_in35_in : in STD_LOGIC;
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_1\ : in STD_LOGIC;
p_1_in32_in : in STD_LOGIC;
p_1_in29_in : in STD_LOGIC;
p_1_in26_in : in STD_LOGIC;
p_1_in23_in : in STD_LOGIC;
p_1_in20_in : in STD_LOGIC;
p_1_in17_in : in STD_LOGIC;
spicr_8_tr_inhibit_frm_axi_clk : in STD_LOGIC;
p_1_in14_in : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
\goreg_dm.dout_i_reg[7]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
scndry_out : in STD_LOGIC;
spicr_1_spe_frm_axi_clk : in STD_LOGIC;
Tx_FIFO_Empty_SPISR_to_axi_clk : in STD_LOGIC;
spicr_2_mst_n_slv_frm_axi_clk : in STD_LOGIC;
empty_fwft_i_reg : in STD_LOGIC;
spicr_4_cpha_frm_axi_clk : in STD_LOGIC;
sr_3_MODF_int : in STD_LOGIC;
\LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\ : in STD_LOGIC;
spicr_5_txfifo_rst_frm_axi_clk : in STD_LOGIC;
ip2Bus_RdAck_core_reg : in STD_LOGIC;
spicr_6_rxfifo_rst_frm_axi_clk : in STD_LOGIC;
spicr_7_ss_frm_axi_clk : in STD_LOGIC;
rx_fifo_empty_i : in STD_LOGIC;
spicr_0_loop_frm_axi_clk : in STD_LOGIC;
Tx_FIFO_Full_int : in STD_LOGIC;
tx_fifo_count : in STD_LOGIC_VECTOR ( 0 to 0 );
spicr_3_cpol_frm_axi_clk : in STD_LOGIC;
spicr_9_lsb_frm_axi_clk : in STD_LOGIC;
Receive_ip2bus_error_reg : in STD_LOGIC;
p_4_in : in STD_LOGIC;
sw_rst_cond_d1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 4 downto 0 );
ip2Bus_WrAck_core_reg_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\ : in STD_LOGIC_VECTOR ( 10 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_axi_lite_ipif : entity is "axi_lite_ipif";
end system_axi_quad_spi_shield_0_axi_lite_ipif;
architecture STRUCTURE of system_axi_quad_spi_shield_0_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.system_axi_quad_spi_shield_0_slave_attachment
port map (
D(10 downto 0) => D(10 downto 0),
E(0) => E(0),
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\,
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\ => \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\,
IP2Bus_Error => IP2Bus_Error,
IP2Bus_Error_1 => IP2Bus_Error_1,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(10 downto 0) => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(10 downto 0),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[31]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[31]\,
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_WrAck_reg\ => \LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_WrAck_reg\,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg\ => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg\,
\LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\ => \LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\,
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2\ => \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2\,
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_0\ => \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_0\,
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_1\ => \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_1\,
Q(8 downto 0) => Q(8 downto 0),
Receive_ip2bus_error_reg => p_5_in,
Receive_ip2bus_error_reg_0 => Receive_ip2bus_error_reg,
SPICR_data_int_reg0 => SPICR_data_int_reg0,
\SPICR_data_int_reg[0]\ => p_8_in,
\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]\ => \SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]\,
SPISSR_frm_axi_clk => SPISSR_frm_axi_clk,
SR => bus2ip_reset_ipif_inverted,
Transmit_ip2bus_error0 => Transmit_ip2bus_error0,
Transmit_ip2bus_error_reg => p_6_in,
Tx_FIFO_Empty_SPISR_to_axi_clk => Tx_FIFO_Empty_SPISR_to_axi_clk,
Tx_FIFO_Full_int => Tx_FIFO_Full_int,
bus2ip_wrce_int(0) => bus2ip_wrce_int(0),
empty_fwft_i_reg => empty_fwft_i_reg,
\goreg_dm.dout_i_reg[7]\(6 downto 0) => \goreg_dm.dout_i_reg[7]\(6 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gpregsm1.curr_fwft_state_reg[1]\,
\icount_out_reg[1]\ => \icount_out_reg[1]\,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_controller_rd_ce_or_reduce => intr_controller_rd_ce_or_reduce,
ip2Bus_RdAck_core_reg => ip2Bus_RdAck_core_reg,
ip2Bus_RdAck_intr_reg_hole0 => ip2Bus_RdAck_intr_reg_hole0,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_core_reg_1 => ip2Bus_WrAck_core_reg_1,
ip2Bus_WrAck_core_reg_d1 => ip2Bus_WrAck_core_reg_d1,
ip2Bus_WrAck_intr_reg_hole0 => ip2Bus_WrAck_intr_reg_hole0,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1_reg => ip2Bus_WrAck_intr_reg_hole_d1_reg,
ipif_glbl_irpt_enable_reg => ipif_glbl_irpt_enable_reg,
ipif_glbl_irpt_enable_reg_reg => Bus_RNW_reg,
ipif_glbl_irpt_enable_reg_reg_0 => ipif_glbl_irpt_enable_reg_reg,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
modf_reg => modf_reg,
\out\ => \out\,
p_15_out => p_15_out,
p_16_out => p_16_out,
p_1_in14_in => p_1_in14_in,
p_1_in17_in => p_1_in17_in,
p_1_in20_in => p_1_in20_in,
p_1_in23_in => p_1_in23_in,
p_1_in26_in => p_1_in26_in,
p_1_in29_in => p_1_in29_in,
p_1_in32_in => p_1_in32_in,
p_1_in35_in => p_1_in35_in,
p_3_in => p_3_in,
p_4_in => p_4_in,
rd_ce_or_reduce_core_cmb => rd_ce_or_reduce_core_cmb,
reset_trig0 => reset_trig0,
rx_fifo_count(1 downto 0) => rx_fifo_count(1 downto 0),
rx_fifo_empty_i => rx_fifo_empty_i,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(4 downto 0) => s_axi_araddr(4 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(4 downto 0) => s_axi_awaddr(4 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(0) => s_axi_bresp(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(10 downto 0) => s_axi_rdata(10 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(0) => s_axi_rresp(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(4 downto 0) => s_axi_wdata(4 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(1 downto 0) => s_axi_wstrb(1 downto 0),
s_axi_wvalid => s_axi_wvalid,
scndry_out => scndry_out,
spicr_0_loop_frm_axi_clk => spicr_0_loop_frm_axi_clk,
spicr_1_spe_frm_axi_clk => spicr_1_spe_frm_axi_clk,
spicr_2_mst_n_slv_frm_axi_clk => spicr_2_mst_n_slv_frm_axi_clk,
spicr_3_cpol_frm_axi_clk => spicr_3_cpol_frm_axi_clk,
spicr_4_cpha_frm_axi_clk => spicr_4_cpha_frm_axi_clk,
spicr_5_txfifo_rst_frm_axi_clk => spicr_5_txfifo_rst_frm_axi_clk,
spicr_6_rxfifo_rst_frm_axi_clk => spicr_6_rxfifo_rst_frm_axi_clk,
spicr_7_ss_frm_axi_clk => spicr_7_ss_frm_axi_clk,
spicr_8_tr_inhibit_frm_axi_clk => spicr_8_tr_inhibit_frm_axi_clk,
spicr_9_lsb_frm_axi_clk => spicr_9_lsb_frm_axi_clk,
sr_3_MODF_int => sr_3_MODF_int,
sw_rst_cond => sw_rst_cond,
sw_rst_cond_d1 => sw_rst_cond_d1,
tx_fifo_count(0) => tx_fifo_count(0),
wr_ce_or_reduce_core_cmb => wr_ce_or_reduce_core_cmb
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_fifo_generator_top is
port (
\out\ : out STD_LOGIC;
\gic0.gc1.count_reg[0]\ : out STD_LOGIC;
\OTHER_RATIO_GENERATE.Serial_Dout_reg\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
ext_spi_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
reset_TxFIFO_ptr_int : in STD_LOGIC;
\spisel_d1_reg__0\ : in STD_LOGIC;
p_6_in : in STD_LOGIC;
ip2Bus_WrAck_core_reg_1 : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
spicr_9_lsb_to_spi_clk : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_fifo_generator_top : entity is "fifo_generator_top";
end system_axi_quad_spi_shield_0_fifo_generator_top;
architecture STRUCTURE of system_axi_quad_spi_shield_0_fifo_generator_top is
begin
\grf.rf\: entity work.system_axi_quad_spi_shield_0_fifo_generator_ramfifo
port map (
Bus_RNW_reg => Bus_RNW_reg,
\OTHER_RATIO_GENERATE.Serial_Dout_reg\ => \OTHER_RATIO_GENERATE.Serial_Dout_reg\,
Q(7 downto 0) => Q(7 downto 0),
ext_spi_clk => ext_spi_clk,
\gic0.gc1.count_reg[0]\ => \gic0.gc1.count_reg[0]\,
ip2Bus_WrAck_core_reg_1 => ip2Bus_WrAck_core_reg_1,
\out\ => \out\,
p_6_in => p_6_in,
reset_TxFIFO_ptr_int => reset_TxFIFO_ptr_int,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
spicr_9_lsb_to_spi_clk => spicr_9_lsb_to_spi_clk,
\spisel_d1_reg__0\ => \spisel_d1_reg__0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_fifo_generator_top_8 is
port (
\out\ : out STD_LOGIC;
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
\icount_out_reg[3]\ : out STD_LOGIC;
Receive_ip2bus_error0 : out STD_LOGIC;
Rx_FIFO_Full_Fifo : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
rx_fifo_reset : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\ : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
p_5_in : in STD_LOGIC;
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\ : in STD_LOGIC;
spiXfer_done_int : in STD_LOGIC;
scndry_out : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_fifo_generator_top_8 : entity is "fifo_generator_top";
end system_axi_quad_spi_shield_0_fifo_generator_top_8;
architecture STRUCTURE of system_axi_quad_spi_shield_0_fifo_generator_top_8 is
begin
\grf.rf\: entity work.system_axi_quad_spi_shield_0_fifo_generator_ramfifo_9
port map (
Bus_RNW_reg => Bus_RNW_reg,
E(0) => E(0),
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\ => \FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\,
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ => \FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\,
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\ => \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\(7 downto 0) => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\(7 downto 0),
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\,
Q(7 downto 0) => Q(7 downto 0),
Receive_ip2bus_error0 => Receive_ip2bus_error0,
Rx_FIFO_Full_Fifo => Rx_FIFO_Full_Fifo,
ext_spi_clk => ext_spi_clk,
\icount_out_reg[3]\ => \icount_out_reg[3]\,
\out\ => \out\,
p_5_in => p_5_in,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rx_fifo_reset => rx_fifo_reset,
s_axi_aclk => s_axi_aclk,
scndry_out => scndry_out,
spiXfer_done_int => spiXfer_done_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_fifo_generator_v13_1_3_synth is
port (
\out\ : out STD_LOGIC;
\gic0.gc1.count_reg[0]\ : out STD_LOGIC;
\OTHER_RATIO_GENERATE.Serial_Dout_reg\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
ext_spi_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
reset_TxFIFO_ptr_int : in STD_LOGIC;
\spisel_d1_reg__0\ : in STD_LOGIC;
p_6_in : in STD_LOGIC;
ip2Bus_WrAck_core_reg_1 : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
spicr_9_lsb_to_spi_clk : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_fifo_generator_v13_1_3_synth : entity is "fifo_generator_v13_1_3_synth";
end system_axi_quad_spi_shield_0_fifo_generator_v13_1_3_synth;
architecture STRUCTURE of system_axi_quad_spi_shield_0_fifo_generator_v13_1_3_synth is
begin
\gconvfifo.rf\: entity work.system_axi_quad_spi_shield_0_fifo_generator_top
port map (
Bus_RNW_reg => Bus_RNW_reg,
\OTHER_RATIO_GENERATE.Serial_Dout_reg\ => \OTHER_RATIO_GENERATE.Serial_Dout_reg\,
Q(7 downto 0) => Q(7 downto 0),
ext_spi_clk => ext_spi_clk,
\gic0.gc1.count_reg[0]\ => \gic0.gc1.count_reg[0]\,
ip2Bus_WrAck_core_reg_1 => ip2Bus_WrAck_core_reg_1,
\out\ => \out\,
p_6_in => p_6_in,
reset_TxFIFO_ptr_int => reset_TxFIFO_ptr_int,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
spicr_9_lsb_to_spi_clk => spicr_9_lsb_to_spi_clk,
\spisel_d1_reg__0\ => \spisel_d1_reg__0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_fifo_generator_v13_1_3_synth_7 is
port (
\out\ : out STD_LOGIC;
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
\icount_out_reg[3]\ : out STD_LOGIC;
Receive_ip2bus_error0 : out STD_LOGIC;
Rx_FIFO_Full_Fifo : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
rx_fifo_reset : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\ : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
p_5_in : in STD_LOGIC;
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\ : in STD_LOGIC;
spiXfer_done_int : in STD_LOGIC;
scndry_out : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_fifo_generator_v13_1_3_synth_7 : entity is "fifo_generator_v13_1_3_synth";
end system_axi_quad_spi_shield_0_fifo_generator_v13_1_3_synth_7;
architecture STRUCTURE of system_axi_quad_spi_shield_0_fifo_generator_v13_1_3_synth_7 is
begin
\gconvfifo.rf\: entity work.system_axi_quad_spi_shield_0_fifo_generator_top_8
port map (
Bus_RNW_reg => Bus_RNW_reg,
E(0) => E(0),
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\ => \FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\,
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ => \FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\,
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\ => \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\(7 downto 0) => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\(7 downto 0),
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\,
Q(7 downto 0) => Q(7 downto 0),
Receive_ip2bus_error0 => Receive_ip2bus_error0,
Rx_FIFO_Full_Fifo => Rx_FIFO_Full_Fifo,
ext_spi_clk => ext_spi_clk,
\icount_out_reg[3]\ => \icount_out_reg[3]\,
\out\ => \out\,
p_5_in => p_5_in,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rx_fifo_reset => rx_fifo_reset,
s_axi_aclk => s_axi_aclk,
scndry_out => scndry_out,
spiXfer_done_int => spiXfer_done_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_fifo_generator_v13_1_3 is
port (
\out\ : out STD_LOGIC;
\gic0.gc1.count_reg[0]\ : out STD_LOGIC;
\OTHER_RATIO_GENERATE.Serial_Dout_reg\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
ext_spi_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
reset_TxFIFO_ptr_int : in STD_LOGIC;
\spisel_d1_reg__0\ : in STD_LOGIC;
p_6_in : in STD_LOGIC;
ip2Bus_WrAck_core_reg_1 : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
spicr_9_lsb_to_spi_clk : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_fifo_generator_v13_1_3 : entity is "fifo_generator_v13_1_3";
end system_axi_quad_spi_shield_0_fifo_generator_v13_1_3;
architecture STRUCTURE of system_axi_quad_spi_shield_0_fifo_generator_v13_1_3 is
begin
inst_fifo_gen: entity work.system_axi_quad_spi_shield_0_fifo_generator_v13_1_3_synth
port map (
Bus_RNW_reg => Bus_RNW_reg,
\OTHER_RATIO_GENERATE.Serial_Dout_reg\ => \OTHER_RATIO_GENERATE.Serial_Dout_reg\,
Q(7 downto 0) => Q(7 downto 0),
ext_spi_clk => ext_spi_clk,
\gic0.gc1.count_reg[0]\ => \gic0.gc1.count_reg[0]\,
ip2Bus_WrAck_core_reg_1 => ip2Bus_WrAck_core_reg_1,
\out\ => \out\,
p_6_in => p_6_in,
reset_TxFIFO_ptr_int => reset_TxFIFO_ptr_int,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
spicr_9_lsb_to_spi_clk => spicr_9_lsb_to_spi_clk,
\spisel_d1_reg__0\ => \spisel_d1_reg__0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_fifo_generator_v13_1_3_6 is
port (
\out\ : out STD_LOGIC;
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
\icount_out_reg[3]\ : out STD_LOGIC;
Receive_ip2bus_error0 : out STD_LOGIC;
Rx_FIFO_Full_Fifo : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
rx_fifo_reset : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\ : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
p_5_in : in STD_LOGIC;
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\ : in STD_LOGIC;
spiXfer_done_int : in STD_LOGIC;
scndry_out : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_fifo_generator_v13_1_3_6 : entity is "fifo_generator_v13_1_3";
end system_axi_quad_spi_shield_0_fifo_generator_v13_1_3_6;
architecture STRUCTURE of system_axi_quad_spi_shield_0_fifo_generator_v13_1_3_6 is
begin
inst_fifo_gen: entity work.system_axi_quad_spi_shield_0_fifo_generator_v13_1_3_synth_7
port map (
Bus_RNW_reg => Bus_RNW_reg,
E(0) => E(0),
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\ => \FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\,
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ => \FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\,
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\ => \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\(7 downto 0) => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\(7 downto 0),
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\,
Q(7 downto 0) => Q(7 downto 0),
Receive_ip2bus_error0 => Receive_ip2bus_error0,
Rx_FIFO_Full_Fifo => Rx_FIFO_Full_Fifo,
ext_spi_clk => ext_spi_clk,
\icount_out_reg[3]\ => \icount_out_reg[3]\,
\out\ => \out\,
p_5_in => p_5_in,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rx_fifo_reset => rx_fifo_reset,
s_axi_aclk => s_axi_aclk,
scndry_out => scndry_out,
spiXfer_done_int => spiXfer_done_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_async_fifo_fg is
port (
\out\ : out STD_LOGIC;
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
\icount_out_reg[3]\ : out STD_LOGIC;
Receive_ip2bus_error0 : out STD_LOGIC;
Rx_FIFO_Full_Fifo : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
rx_fifo_reset : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\ : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
p_5_in : in STD_LOGIC;
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\ : in STD_LOGIC;
spiXfer_done_int : in STD_LOGIC;
scndry_out : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_async_fifo_fg : entity is "async_fifo_fg";
end system_axi_quad_spi_shield_0_async_fifo_fg;
architecture STRUCTURE of system_axi_quad_spi_shield_0_async_fifo_fg is
begin
\USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM\: entity work.system_axi_quad_spi_shield_0_fifo_generator_v13_1_3_6
port map (
Bus_RNW_reg => Bus_RNW_reg,
E(0) => E(0),
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\ => \FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\,
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ => \FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\,
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\ => \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\(7 downto 0) => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\(7 downto 0),
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\,
Q(7 downto 0) => Q(7 downto 0),
Receive_ip2bus_error0 => Receive_ip2bus_error0,
Rx_FIFO_Full_Fifo => Rx_FIFO_Full_Fifo,
ext_spi_clk => ext_spi_clk,
\icount_out_reg[3]\ => \icount_out_reg[3]\,
\out\ => \out\,
p_5_in => p_5_in,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rx_fifo_reset => rx_fifo_reset,
s_axi_aclk => s_axi_aclk,
scndry_out => scndry_out,
spiXfer_done_int => spiXfer_done_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_async_fifo_fg_2 is
port (
\out\ : out STD_LOGIC;
\gic0.gc1.count_reg[0]\ : out STD_LOGIC;
\OTHER_RATIO_GENERATE.Serial_Dout_reg\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
ext_spi_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
reset_TxFIFO_ptr_int : in STD_LOGIC;
\spisel_d1_reg__0\ : in STD_LOGIC;
p_6_in : in STD_LOGIC;
ip2Bus_WrAck_core_reg_1 : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
spicr_9_lsb_to_spi_clk : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_async_fifo_fg_2 : entity is "async_fifo_fg";
end system_axi_quad_spi_shield_0_async_fifo_fg_2;
architecture STRUCTURE of system_axi_quad_spi_shield_0_async_fifo_fg_2 is
begin
\USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM\: entity work.system_axi_quad_spi_shield_0_fifo_generator_v13_1_3
port map (
Bus_RNW_reg => Bus_RNW_reg,
\OTHER_RATIO_GENERATE.Serial_Dout_reg\ => \OTHER_RATIO_GENERATE.Serial_Dout_reg\,
Q(7 downto 0) => Q(7 downto 0),
ext_spi_clk => ext_spi_clk,
\gic0.gc1.count_reg[0]\ => \gic0.gc1.count_reg[0]\,
ip2Bus_WrAck_core_reg_1 => ip2Bus_WrAck_core_reg_1,
\out\ => \out\,
p_6_in => p_6_in,
reset_TxFIFO_ptr_int => reset_TxFIFO_ptr_int,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
spicr_9_lsb_to_spi_clk => spicr_9_lsb_to_spi_clk,
\spisel_d1_reg__0\ => \spisel_d1_reg__0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_qspi_core_interface is
port (
Tx_FIFO_Empty_SPISR_to_axi_clk : out STD_LOGIC;
spicr_0_loop_frm_axi_clk : out STD_LOGIC;
spicr_1_spe_frm_axi_clk : out STD_LOGIC;
spicr_2_mst_n_slv_frm_axi_clk : out STD_LOGIC;
spicr_3_cpol_frm_axi_clk : out STD_LOGIC;
spicr_4_cpha_frm_axi_clk : out STD_LOGIC;
spicr_7_ss_frm_axi_clk : out STD_LOGIC;
spicr_8_tr_inhibit_frm_axi_clk : out STD_LOGIC;
spicr_9_lsb_frm_axi_clk : out STD_LOGIC;
sr_3_MODF_int : out STD_LOGIC;
SPISSR_frm_axi_clk : out STD_LOGIC;
\out\ : out STD_LOGIC;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : out STD_LOGIC;
\gic0.gc1.count_reg[0]\ : out STD_LOGIC;
sck_t : out STD_LOGIC;
io0_t : out STD_LOGIC;
ss_t : out STD_LOGIC;
io1_t : out STD_LOGIC;
sck_o : out STD_LOGIC;
IP2Bus_Error : out STD_LOGIC;
sw_rst_cond_d1 : out STD_LOGIC;
irpt_wrack_d1 : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ : out STD_LOGIC;
p_1_in35_in : out STD_LOGIC;
p_1_in32_in : out STD_LOGIC;
p_1_in29_in : out STD_LOGIC;
p_1_in26_in : out STD_LOGIC;
p_1_in23_in : out STD_LOGIC;
p_1_in20_in : out STD_LOGIC;
p_1_in17_in : out STD_LOGIC;
p_1_in14_in : out STD_LOGIC;
irpt_rdack_d1 : out STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_Error_reg_0\ : out STD_LOGIC;
p_4_in : out STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : out STD_LOGIC;
ip2Bus_WrAck_core_reg_d1 : out STD_LOGIC;
p_16_out : out STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : out STD_LOGIC;
ip2Bus_RdAck_core_reg : out STD_LOGIC;
p_15_out : out STD_LOGIC;
ip2Bus_WrAck_core_reg_1 : out STD_LOGIC;
scndry_out : out STD_LOGIC;
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d1_reg[3]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
spicr_5_txfifo_rst_frm_axi_clk : out STD_LOGIC;
spicr_6_rxfifo_rst_frm_axi_clk : out STD_LOGIC;
ipif_glbl_irpt_enable_reg : out STD_LOGIC;
io0_o : out STD_LOGIC;
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
Tx_FIFO_Full_int : out STD_LOGIC;
rx_fifo_empty_i : out STD_LOGIC;
\icount_out_reg[3]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[31]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 6 downto 0 );
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]_0\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]_0\ : out STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[23]_0\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_aclk : in STD_LOGIC;
rd_ce_or_reduce_core_cmb : in STD_LOGIC;
bus2ip_wrce_int : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 );
ext_spi_clk : in STD_LOGIC;
spisel : in STD_LOGIC;
sck_i : in STD_LOGIC;
IP2Bus_Error_1 : in STD_LOGIC;
SPICR_data_int_reg0 : in STD_LOGIC;
bus2ip_reset_ipif_inverted : in STD_LOGIC;
sw_rst_cond : in STD_LOGIC;
reset_trig0 : in STD_LOGIC;
irpt_wrack : in STD_LOGIC;
interrupt_wrce_strb : in STD_LOGIC;
irpt_rdack : in STD_LOGIC;
intr2bus_rdack0 : in STD_LOGIC;
Transmit_ip2bus_error0 : in STD_LOGIC;
Bus_RNW_reg_reg : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole0 : in STD_LOGIC;
wr_ce_or_reduce_core_cmb : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_reg_0\ : in STD_LOGIC;
intr_controller_rd_ce_or_reduce : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole0 : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[28].ce_out_i_reg[28]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\ : in STD_LOGIC;
Bus_RNW_reg_reg_0 : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
p_6_in : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\ : in STD_LOGIC;
p_3_in : in STD_LOGIC;
p_5_in : in STD_LOGIC;
empty_fwft_i_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\ : in STD_LOGIC;
Bus_RNW_reg_reg_1 : in STD_LOGIC;
p_8_in : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 10 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
io1_i_sync : in STD_LOGIC;
io0_i_sync : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_qspi_core_interface : entity is "qspi_core_interface";
end system_axi_quad_spi_shield_0_qspi_core_interface;
architecture STRUCTURE of system_axi_quad_spi_shield_0_qspi_core_interface is
signal Allow_MODF_Strobe : STD_LOGIC;
signal Allow_Slave_MODF_Strobe : STD_LOGIC;
signal CONTROL_REG_I_n_12 : STD_LOGIC;
signal CONTROL_REG_I_n_14 : STD_LOGIC;
signal CONTROL_REG_I_n_15 : STD_LOGIC;
signal CONTROL_REG_I_n_16 : STD_LOGIC;
signal D_0 : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_0\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_1\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_14\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_15\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_16\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_17\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_18\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_19\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_20\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_21\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_22\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_26\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_31\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_32\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_33\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_37\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_39\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_41\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_43\ : STD_LOGIC;
signal \FIFO_EXISTS.FIFO_IF_MODULE_I_n_3\ : STD_LOGIC;
signal \FIFO_EXISTS.FIFO_IF_MODULE_I_n_4\ : STD_LOGIC;
signal \FIFO_EXISTS.FIFO_IF_MODULE_I_n_5\ : STD_LOGIC;
signal \FIFO_EXISTS.RX_FIFO_FULL_CNTR_I_n_4\ : STD_LOGIC;
signal \FIFO_EXISTS.RX_FIFO_FULL_SYNCED_SPI_2_AXI_CDC_n_2\ : STD_LOGIC;
signal \FIFO_EXISTS.RX_FIFO_FULL_SYNCED_SPI_2_AXI_CDC_n_3\ : STD_LOGIC;
signal \FIFO_EXISTS.RX_FIFO_II_n_2\ : STD_LOGIC;
signal \FIFO_EXISTS.RX_FIFO_II_n_3\ : STD_LOGIC;
signal \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_4\ : STD_LOGIC;
signal \FIFO_EXISTS.TX_FIFO_II_n_2\ : STD_LOGIC;
signal \^fifo_exists.tx_full_emp_intr_md_0_gen.tx_fifo_count_d1_reg[3]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^generate_level_p_s_cdc.single_bit.cross_plevel_in2scndry_in_cdc_to\ : STD_LOGIC;
signal \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]\ : STD_LOGIC;
signal IP2Bus_RdAck_1 : STD_LOGIC;
signal IP2Bus_WrAck_1 : STD_LOGIC;
signal \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_i_1_n_0\ : STD_LOGIC;
signal \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_1_reg_r_n_0\ : STD_LOGIC;
signal \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_2_reg_r_n_0\ : STD_LOGIC;
signal \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_3_reg_r_n_0\ : STD_LOGIC;
signal \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_r_n_0\ : STD_LOGIC;
signal \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_srl4___NO_DUAL_QUAD_MODE.QSPI_NORMAL_QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_r_n_0\ : STD_LOGIC;
signal \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_NO_DUAL_QUAD_MODE.QSPI_NORMAL_QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_r_n_0\ : STD_LOGIC;
signal \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_gate_n_0\ : STD_LOGIC;
signal \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_r_n_0\ : STD_LOGIC;
signal \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_11\ : STD_LOGIC;
signal \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_20\ : STD_LOGIC;
signal \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_22\ : STD_LOGIC;
signal \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_23\ : STD_LOGIC;
signal \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_8\ : STD_LOGIC;
signal MODF_strobe0 : STD_LOGIC;
signal R : STD_LOGIC;
signal RESET_SYNC_AXI_SPI_CLK_INST_n_0 : STD_LOGIC;
signal RESET_SYNC_AXI_SPI_CLK_INST_n_3 : STD_LOGIC;
signal RESET_SYNC_AXI_SPI_CLK_INST_n_4 : STD_LOGIC;
signal Receive_ip2bus_error0 : STD_LOGIC;
signal Rx_FIFO_Empty_Synced_in_SPI_domain : STD_LOGIC;
signal Rx_FIFO_Full_Fifo : STD_LOGIC;
signal Rx_FIFO_Full_Fifo_d1 : STD_LOGIC;
signal Rx_FIFO_Full_Fifo_d1_flag : STD_LOGIC;
signal Rx_FIFO_Full_Fifo_d1_sig : STD_LOGIC;
signal Rx_FIFO_Full_Fifo_d1_synced_i : STD_LOGIC;
signal Rx_FIFO_Full_Fifo_org : STD_LOGIC;
signal Rx_FIFO_Full_i : STD_LOGIC;
signal Rx_FIFO_Full_int : STD_LOGIC;
signal SOFT_RESET_I_n_2 : STD_LOGIC;
signal SOFT_RESET_I_n_3 : STD_LOGIC;
signal SPICR_2_MST_N_SLV_to_spi_clk : STD_LOGIC;
signal SPISEL_sync : STD_LOGIC;
signal \^spissr_frm_axi_clk\ : STD_LOGIC;
signal SR_5_Tx_comeplete_Empty : STD_LOGIC;
signal Serial_Din : STD_LOGIC;
signal Slave_MODF_strobe0 : STD_LOGIC;
signal Tx_FIFO_Empty_intr : STD_LOGIC;
signal Tx_FIFO_Full_i : STD_LOGIC;
signal \^tx_fifo_full_int\ : STD_LOGIC;
signal \USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_18_out\ : STD_LOGIC;
signal bus2IP_Data_for_interrupt_core : STD_LOGIC_VECTOR ( 23 to 23 );
signal data_Exists_RcFIFO_int_d1 : STD_LOGIC;
signal data_Exists_RcFIFO_pulse038_in : STD_LOGIC;
signal data_from_rx_fifo : STD_LOGIC_VECTOR ( 7 to 7 );
signal data_from_txfifo : STD_LOGIC_VECTOR ( 0 to 7 );
signal drr_Overrun_int : STD_LOGIC;
signal dtr_underrun_int : STD_LOGIC;
signal dtr_underrun_to_axi_clk : STD_LOGIC;
signal \^gic0.gc1.count_reg[0]\ : STD_LOGIC;
signal \^ip2bus_rdack_core_reg\ : STD_LOGIC;
signal ip2Bus_RdAck_intr_reg_hole : STD_LOGIC;
signal ip2Bus_WrAck_core_reg : STD_LOGIC;
signal \^ip2bus_wrack_core_reg_1\ : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole : STD_LOGIC;
signal modf_strobe_int : STD_LOGIC;
signal \^out\ : STD_LOGIC;
signal \^p_1_in14_in\ : STD_LOGIC;
signal \^p_1_in17_in\ : STD_LOGIC;
signal \^p_1_in20_in\ : STD_LOGIC;
signal \^p_1_in23_in\ : STD_LOGIC;
signal \^p_1_in26_in\ : STD_LOGIC;
signal \^p_1_in29_in\ : STD_LOGIC;
signal \^p_1_in32_in\ : STD_LOGIC;
signal \^p_1_in35_in\ : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal read_ack_delay_6 : STD_LOGIC;
signal read_ack_delay_7 : STD_LOGIC;
signal receive_Data_int : STD_LOGIC_VECTOR ( 0 to 7 );
signal register_Data_slvsel_int : STD_LOGIC;
signal reset2ip_reset_int : STD_LOGIC;
signal reset_TxFIFO_ptr_int : STD_LOGIC;
signal rst_to_spi_int : STD_LOGIC;
signal rx_fifo_count : STD_LOGIC_VECTOR ( 2 downto 1 );
signal \^rx_fifo_empty_i\ : STD_LOGIC;
signal rx_fifo_reset : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
signal serial_dout_int : STD_LOGIC;
signal spiXfer_done_d2 : STD_LOGIC;
signal spiXfer_done_d3 : STD_LOGIC;
signal spiXfer_done_int : STD_LOGIC;
signal spiXfer_done_to_axi_1 : STD_LOGIC;
signal spiXfer_done_to_axi_d1 : STD_LOGIC;
signal \^spicr_0_loop_frm_axi_clk\ : STD_LOGIC;
signal spicr_0_loop_to_spi_clk : STD_LOGIC;
signal \^spicr_1_spe_frm_axi_clk\ : STD_LOGIC;
signal spicr_1_spe_to_spi_clk : STD_LOGIC;
signal \^spicr_2_mst_n_slv_frm_axi_clk\ : STD_LOGIC;
signal \^spicr_3_cpol_frm_axi_clk\ : STD_LOGIC;
signal spicr_3_cpol_to_spi_clk : STD_LOGIC;
signal \^spicr_4_cpha_frm_axi_clk\ : STD_LOGIC;
signal spicr_4_cpha_to_spi_clk : STD_LOGIC;
signal \^spicr_5_txfifo_rst_frm_axi_clk\ : STD_LOGIC;
signal \^spicr_6_rxfifo_rst_frm_axi_clk\ : STD_LOGIC;
signal \^spicr_7_ss_frm_axi_clk\ : STD_LOGIC;
signal \^spicr_8_tr_inhibit_frm_axi_clk\ : STD_LOGIC;
signal \^spicr_9_lsb_frm_axi_clk\ : STD_LOGIC;
signal spicr_9_lsb_to_spi_clk : STD_LOGIC;
signal spicr_bits_7_8_frm_axi_clk : STD_LOGIC_VECTOR ( 1 downto 0 );
signal spisel_d1_reg : STD_LOGIC;
signal \^sr_3_modf_int\ : STD_LOGIC;
signal stop_clock : STD_LOGIC;
signal tx_FIFO_Occpncy_MSB_d1 : STD_LOGIC;
signal tx_fifo_count : STD_LOGIC_VECTOR ( 2 downto 0 );
signal tx_fifo_count_d1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal tx_fifo_count_d2 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal tx_fifo_empty : STD_LOGIC;
signal tx_occ_msb : STD_LOGIC;
signal tx_occ_msb_4 : STD_LOGIC;
signal wrack : STD_LOGIC;
attribute srl_name : string;
attribute srl_name of \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_srl4___NO_DUAL_QUAD_MODE.QSPI_NORMAL_QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_r\ : label is "U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_srl4___NO_DUAL_QUAD_MODE.QSPI_NORMAL_QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_r ";
begin
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d1_reg[3]_0\(0) <= \^fifo_exists.tx_full_emp_intr_md_0_gen.tx_fifo_count_d1_reg[3]_0\(0);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ <= \^generate_level_p_s_cdc.single_bit.cross_plevel_in2scndry_in_cdc_to\;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ <= \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]\;
SPISSR_frm_axi_clk <= \^spissr_frm_axi_clk\;
Tx_FIFO_Full_int <= \^tx_fifo_full_int\;
\gic0.gc1.count_reg[0]\ <= \^gic0.gc1.count_reg[0]\;
ip2Bus_RdAck_core_reg <= \^ip2bus_rdack_core_reg\;
ip2Bus_WrAck_core_reg_1 <= \^ip2bus_wrack_core_reg_1\;
\out\ <= \^out\;
p_1_in14_in <= \^p_1_in14_in\;
p_1_in17_in <= \^p_1_in17_in\;
p_1_in20_in <= \^p_1_in20_in\;
p_1_in23_in <= \^p_1_in23_in\;
p_1_in26_in <= \^p_1_in26_in\;
p_1_in29_in <= \^p_1_in29_in\;
p_1_in32_in <= \^p_1_in32_in\;
p_1_in35_in <= \^p_1_in35_in\;
rx_fifo_empty_i <= \^rx_fifo_empty_i\;
scndry_out <= \^scndry_out\;
spicr_0_loop_frm_axi_clk <= \^spicr_0_loop_frm_axi_clk\;
spicr_1_spe_frm_axi_clk <= \^spicr_1_spe_frm_axi_clk\;
spicr_2_mst_n_slv_frm_axi_clk <= \^spicr_2_mst_n_slv_frm_axi_clk\;
spicr_3_cpol_frm_axi_clk <= \^spicr_3_cpol_frm_axi_clk\;
spicr_4_cpha_frm_axi_clk <= \^spicr_4_cpha_frm_axi_clk\;
spicr_5_txfifo_rst_frm_axi_clk <= \^spicr_5_txfifo_rst_frm_axi_clk\;
spicr_6_rxfifo_rst_frm_axi_clk <= \^spicr_6_rxfifo_rst_frm_axi_clk\;
spicr_7_ss_frm_axi_clk <= \^spicr_7_ss_frm_axi_clk\;
spicr_8_tr_inhibit_frm_axi_clk <= \^spicr_8_tr_inhibit_frm_axi_clk\;
spicr_9_lsb_frm_axi_clk <= \^spicr_9_lsb_frm_axi_clk\;
sr_3_MODF_int <= \^sr_3_modf_int\;
CONTROL_REG_I: entity work.system_axi_quad_spi_shield_0_qspi_cntrl_reg
port map (
Bus_RNW_reg => Bus_RNW_reg,
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_0\ => \^spicr_6_rxfifo_rst_frm_axi_clk\,
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.Rx_FIFO_Full_int_reg\ => CONTROL_REG_I_n_16,
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\ => \^rx_fifo_empty_i\,
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\ => \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\,
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\ => \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\,
\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]\ => CONTROL_REG_I_n_15,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\ => \^ip2bus_wrack_core_reg_1\,
\LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_1_CDC\ => \^spicr_2_mst_n_slv_frm_axi_clk\,
\RESET_FLOPS[15].RST_FLOPS\ => SOFT_RESET_I_n_2,
Rx_FIFO_Full_i => Rx_FIFO_Full_i,
Rx_FIFO_Full_int => Rx_FIFO_Full_int,
SPICR_data_int_reg0 => SPICR_data_int_reg0,
bus2ip_reset_ipif_inverted => bus2ip_reset_ipif_inverted,
bus2ip_wrce_int(0) => bus2ip_wrce_int(0),
data_Exists_RcFIFO_int_d1 => data_Exists_RcFIFO_int_d1,
\icount_out_reg[3]\ => CONTROL_REG_I_n_12,
\icount_out_reg[3]_0\ => CONTROL_REG_I_n_14,
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ => \^spicr_5_txfifo_rst_frm_axi_clk\,
\out\ => \^out\,
p_1_in14_in => \^p_1_in14_in\,
p_6_in => p_6_in,
p_8_in => p_8_in,
prmry_in => \^generate_level_p_s_cdc.single_bit.cross_plevel_in2scndry_in_cdc_to\,
ram_full_i_reg => \^gic0.gc1.count_reg[0]\,
reset2ip_reset_int => reset2ip_reset_int,
reset_TxFIFO_ptr_int => reset_TxFIFO_ptr_int,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(9 downto 0) => s_axi_wdata(9 downto 0),
spiXfer_done_to_axi_1 => spiXfer_done_to_axi_1,
spicr_0_loop_frm_axi_clk => \^spicr_0_loop_frm_axi_clk\,
spicr_1_spe_frm_axi_clk => \^spicr_1_spe_frm_axi_clk\,
spicr_3_cpol_frm_axi_clk => \^spicr_3_cpol_frm_axi_clk\,
spicr_4_cpha_frm_axi_clk => \^spicr_4_cpha_frm_axi_clk\,
spicr_7_ss_frm_axi_clk => \^spicr_7_ss_frm_axi_clk\,
spicr_8_tr_inhibit_frm_axi_clk => \^spicr_8_tr_inhibit_frm_axi_clk\,
spicr_9_lsb_frm_axi_clk => \^spicr_9_lsb_frm_axi_clk\,
spicr_bits_7_8_frm_axi_clk(1 downto 0) => spicr_bits_7_8_frm_axi_clk(1 downto 0)
);
\FIFO_EXISTS.CLK_CROSS_I\: entity work.system_axi_quad_spi_shield_0_cross_clk_sync_fifo_1
port map (
Allow_MODF_Strobe => Allow_MODF_Strobe,
Allow_Slave_MODF_Strobe => Allow_Slave_MODF_Strobe,
Allow_Slave_MODF_Strobe_reg => \FIFO_EXISTS.CLK_CROSS_I_n_15\,
Bus_RNW_reg => Bus_RNW_reg,
Bus_RNW_reg_reg => Bus_RNW_reg_reg_1,
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\ => \^spicr_6_rxfifo_rst_frm_axi_clk\,
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_0\ => CONTROL_REG_I_n_14,
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\ => \^spicr_5_txfifo_rst_frm_axi_clk\,
D(0) => bus2IP_Data_for_interrupt_core(23),
D_0 => D_0,
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\ => \FIFO_EXISTS.CLK_CROSS_I_n_14\,
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg_0\ => \^rx_fifo_empty_i\,
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_sig_reg\ => \FIFO_EXISTS.RX_FIFO_FULL_SYNCED_SPI_2_AXI_CDC_n_2\,
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_int_reg\ => \FIFO_EXISTS.CLK_CROSS_I_n_33\,
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\ => \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\,
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\ => \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ => \FIFO_EXISTS.CLK_CROSS_I_n_22\,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ => \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]\,
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ => \FIFO_EXISTS.CLK_CROSS_I_n_21\,
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]\ => \FIFO_EXISTS.CLK_CROSS_I_n_20\,
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]\ => \FIFO_EXISTS.CLK_CROSS_I_n_19\,
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]\ => \FIFO_EXISTS.CLK_CROSS_I_n_18\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]_0\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]_0\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[31]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[31]_0\,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ => \^ip2bus_rdack_core_reg\,
\LOCAL_TX_EMPTY_FIFO_12_GEN.stop_clock_reg_reg\ => \FIFO_EXISTS.CLK_CROSS_I_n_41\,
\LOGIC_GENERATION_FDR.SLV_MODF_STRB_S2AX_1_CDC_0\ => \FIFO_EXISTS.CLK_CROSS_I_n_1\,
\LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_2_0\ => \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_23\,
\LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_1_CDC_0\ => \FIFO_EXISTS.CLK_CROSS_I_n_0\,
\LOGIC_GENERATION_FDR.spisel_pulse_cdc_from_spi_int_2_reg_0\ => \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_20\,
MODF_strobe0 => MODF_strobe0,
\OTHER_RATIO_GENERATE.Shift_Reg_reg[7]\(0) => \FIFO_EXISTS.CLK_CROSS_I_n_37\,
\OTHER_RATIO_GENERATE.rx_shft_reg_s_reg[7]\(0) => Serial_Din,
\OTHER_RATIO_GENERATE.sck_o_int_reg\ => \FIFO_EXISTS.CLK_CROSS_I_n_39\,
Q(0) => data_from_rx_fifo(7),
R => R,
\RESET_FLOPS[15].RST_FLOPS\ => SOFT_RESET_I_n_2,
RESET_SYNC_AX2S_2 => RESET_SYNC_AXI_SPI_CLK_INST_n_4,
\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg\ => \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_8\,
Rst_to_spi => rst_to_spi_int,
Rx_FIFO_Full_Fifo_d1_flag => Rx_FIFO_Full_Fifo_d1_flag,
Rx_FIFO_Full_Fifo_d1_sig => Rx_FIFO_Full_Fifo_d1_sig,
Rx_FIFO_Full_int => Rx_FIFO_Full_int,
SPICR_2_MST_N_SLV_to_spi_clk => SPICR_2_MST_N_SLV_to_spi_clk,
SPISEL_sync => SPISEL_sync,
SPISSR_frm_axi_clk => \^spissr_frm_axi_clk\,
SPI_TRISTATE_CONTROL_V => \FIFO_EXISTS.CLK_CROSS_I_n_43\,
SR_5_Tx_comeplete_Empty => SR_5_Tx_comeplete_Empty,
\SS_O_reg[0]\ => \FIFO_EXISTS.CLK_CROSS_I_n_31\,
Slave_MODF_strobe0 => Slave_MODF_strobe0,
Tx_FIFO_Empty_intr => Tx_FIFO_Empty_intr,
Tx_FIFO_Full_i => Tx_FIFO_Full_i,
Tx_FIFO_Full_int => \^tx_fifo_full_int\,
bus2ip_reset_ipif_inverted => bus2ip_reset_ipif_inverted,
drr_Overrun_int => drr_Overrun_int,
dtr_underrun_int => dtr_underrun_int,
dtr_underrun_to_axi_clk => dtr_underrun_to_axi_clk,
empty_fwft_i_reg => \FIFO_EXISTS.RX_FIFO_II_n_3\,
empty_fwft_i_reg_0 => empty_fwft_i_reg,
ext_spi_clk => ext_spi_clk,
\goreg_dm.dout_i_reg[7]\(1) => data_from_txfifo(0),
\goreg_dm.dout_i_reg[7]\(0) => data_from_txfifo(7),
\icount_out_reg[1]\ => \FIFO_EXISTS.CLK_CROSS_I_n_26\,
\icount_out_reg[3]\ => \FIFO_EXISTS.CLK_CROSS_I_n_17\,
io0_i_sync => io0_i_sync,
io1_i_sync => io1_i_sync,
\ip_irpt_enable_reg_reg[8]\ => \^out\,
modf_reg => \FIFO_EXISTS.CLK_CROSS_I_n_32\,
modf_strobe_int => modf_strobe_int,
\out\ => tx_fifo_empty,
p_1_in17_in => \^p_1_in17_in\,
p_1_in20_in => \^p_1_in20_in\,
p_1_in23_in => \^p_1_in23_in\,
p_1_in35_in => \^p_1_in35_in\,
p_3_in => p_3_in,
p_7_out => p_7_out,
register_Data_slvsel_int => register_Data_slvsel_int,
reset2ip_reset_int => reset2ip_reset_int,
rx_fifo_count(1 downto 0) => rx_fifo_count(2 downto 1),
rx_fifo_reset => rx_fifo_reset,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(5 downto 2) => s_axi_wdata(8 downto 5),
s_axi_wdata(1 downto 0) => s_axi_wdata(1 downto 0),
scndry_out => \^scndry_out\,
serial_dout_int => serial_dout_int,
spiXfer_done_d2 => spiXfer_done_d2,
spiXfer_done_d3 => spiXfer_done_d3,
spiXfer_done_int => spiXfer_done_int,
spiXfer_done_to_axi_1 => spiXfer_done_to_axi_1,
spiXfer_done_to_axi_d1 => spiXfer_done_to_axi_d1,
spicr_0_loop_frm_axi_clk => \^spicr_0_loop_frm_axi_clk\,
spicr_0_loop_to_spi_clk => spicr_0_loop_to_spi_clk,
spicr_1_spe_frm_axi_clk => \^spicr_1_spe_frm_axi_clk\,
spicr_1_spe_to_spi_clk => spicr_1_spe_to_spi_clk,
spicr_2_mst_n_slv_frm_axi_clk => \^spicr_2_mst_n_slv_frm_axi_clk\,
spicr_3_cpol_frm_axi_clk => \^spicr_3_cpol_frm_axi_clk\,
spicr_3_cpol_to_spi_clk => spicr_3_cpol_to_spi_clk,
spicr_4_cpha_frm_axi_clk => \^spicr_4_cpha_frm_axi_clk\,
spicr_4_cpha_to_spi_clk => spicr_4_cpha_to_spi_clk,
spicr_7_ss_frm_axi_clk => \^spicr_7_ss_frm_axi_clk\,
spicr_8_tr_inhibit_frm_axi_clk => \^spicr_8_tr_inhibit_frm_axi_clk\,
spicr_9_lsb_frm_axi_clk => \^spicr_9_lsb_frm_axi_clk\,
spicr_9_lsb_to_spi_clk => spicr_9_lsb_to_spi_clk,
spicr_bits_7_8_frm_axi_clk(1 downto 0) => spicr_bits_7_8_frm_axi_clk(1 downto 0),
spisel_d1_reg => spisel_d1_reg,
sr_3_MODF_int => \^sr_3_modf_int\,
stop_clock => stop_clock,
transfer_start_reg => \FIFO_EXISTS.CLK_CROSS_I_n_16\,
transfer_start_reg_0 => \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_11\,
tx_FIFO_Occpncy_MSB_d1 => tx_FIFO_Occpncy_MSB_d1,
tx_FIFO_Occpncy_MSB_d1_reg => Tx_FIFO_Empty_SPISR_to_axi_clk,
tx_fifo_count(2 downto 0) => tx_fifo_count(2 downto 0),
tx_fifo_count_d2(3 downto 0) => tx_fifo_count_d2(3 downto 0),
tx_occ_msb => tx_occ_msb,
tx_occ_msb_4 => tx_occ_msb_4
);
\FIFO_EXISTS.FIFO_IF_MODULE_I\: entity work.system_axi_quad_spi_shield_0_qspi_fifo_ifmodule
port map (
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\ => \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\,
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\ => \FIFO_EXISTS.FIFO_IF_MODULE_I_n_5\,
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\ => \FIFO_EXISTS.FIFO_IF_MODULE_I_n_4\,
\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4]\ => \FIFO_EXISTS.FIFO_IF_MODULE_I_n_3\,
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_Error_reg\ => \LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_Error_reg_0\,
Receive_ip2bus_error0 => Receive_ip2bus_error0,
Rx_FIFO_Full_Fifo_d1_synced_i => Rx_FIFO_Full_Fifo_d1_synced_i,
Transmit_ip2bus_error0 => Transmit_ip2bus_error0,
Tx_FIFO_Empty_intr => Tx_FIFO_Empty_intr,
dtr_underrun_to_axi_clk => dtr_underrun_to_axi_clk,
p_1_in26_in => \^p_1_in26_in\,
p_1_in29_in => \^p_1_in29_in\,
p_1_in32_in => \^p_1_in32_in\,
p_4_in => p_4_in,
prmry_in => \^generate_level_p_s_cdc.single_bit.cross_plevel_in2scndry_in_cdc_to\,
reset2ip_reset_int => reset2ip_reset_int,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(2 downto 0) => s_axi_wdata(4 downto 2),
scndry_out => \^scndry_out\,
tx_FIFO_Occpncy_MSB_d1 => tx_FIFO_Occpncy_MSB_d1,
tx_occ_msb => tx_occ_msb
);
\FIFO_EXISTS.RX_FIFO_EMPTY_SYNC_AXI_2_SPI_CDC\: entity work.system_axi_quad_spi_shield_0_cdc_sync
port map (
ext_spi_clk => ext_spi_clk,
prmry_in => \^generate_level_p_s_cdc.single_bit.cross_plevel_in2scndry_in_cdc_to\,
scndry_out => Rx_FIFO_Empty_Synced_in_SPI_domain
);
\FIFO_EXISTS.RX_FIFO_FULL_CNTR_I\: entity work.system_axi_quad_spi_shield_0_counter_f
port map (
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\ => \^spicr_6_rxfifo_rst_frm_axi_clk\,
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_0\ => CONTROL_REG_I_n_14,
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.Rx_FIFO_Full_i_reg\ => \FIFO_EXISTS.RX_FIFO_FULL_CNTR_I_n_4\,
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.Rx_FIFO_Full_int_reg\ => \FIFO_EXISTS.CLK_CROSS_I_n_17\,
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_sig_reg\ => \FIFO_EXISTS.CLK_CROSS_I_n_26\,
\RESET_FLOPS[15].RST_FLOPS\ => SOFT_RESET_I_n_2,
Rx_FIFO_Full_i => Rx_FIFO_Full_i,
Rx_FIFO_Full_int => Rx_FIFO_Full_int,
bus2ip_reset_ipif_inverted => bus2ip_reset_ipif_inverted,
\icount_out_reg[0]_0\ => \icount_out_reg[3]\(0),
\icount_out_reg[3]_0\(0) => \icount_out_reg[3]\(1),
reset2ip_reset_int => reset2ip_reset_int,
rx_fifo_count(1 downto 0) => rx_fifo_count(2 downto 1),
s_axi_aclk => s_axi_aclk,
spiXfer_done_d2 => spiXfer_done_d2,
spiXfer_done_d3 => spiXfer_done_d3
);
\FIFO_EXISTS.RX_FIFO_FULL_SYNCED_SPI_2_AXI_CDC\: entity work.system_axi_quad_spi_shield_0_cdc_sync_0
port map (
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_sig_reg\ => \FIFO_EXISTS.RX_FIFO_FULL_SYNCED_SPI_2_AXI_CDC_n_3\,
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\ => \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\,
Rx_FIFO_Full_Fifo_d1_flag => Rx_FIFO_Full_Fifo_d1_flag,
Rx_FIFO_Full_Fifo_d1_sig => Rx_FIFO_Full_Fifo_d1_sig,
Rx_FIFO_Full_Fifo_d1_synced_i => Rx_FIFO_Full_Fifo_d1_synced_i,
\icount_out_reg[3]\ => \FIFO_EXISTS.RX_FIFO_FULL_SYNCED_SPI_2_AXI_CDC_n_2\,
\out\ => \^generate_level_p_s_cdc.single_bit.cross_plevel_in2scndry_in_cdc_to\,
prmry_in => Rx_FIFO_Full_Fifo_d1,
reset2ip_reset_int => reset2ip_reset_int,
s_axi_aclk => s_axi_aclk,
scndry_out => \^scndry_out\
);
\FIFO_EXISTS.RX_FIFO_II\: entity work.system_axi_quad_spi_shield_0_async_fifo_fg
port map (
Bus_RNW_reg => Bus_RNW_reg,
E(0) => \USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_18_out\,
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\ => \^rx_fifo_empty_i\,
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ => Rx_FIFO_Full_Fifo_org,
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\ => \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\(7 downto 1) => Q(6 downto 0),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\(0) => data_from_rx_fifo(7),
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ => \^ip2bus_rdack_core_reg\,
Q(7) => receive_Data_int(0),
Q(6) => receive_Data_int(1),
Q(5) => receive_Data_int(2),
Q(4) => receive_Data_int(3),
Q(3) => receive_Data_int(4),
Q(2) => receive_Data_int(5),
Q(1) => receive_Data_int(6),
Q(0) => receive_Data_int(7),
Receive_ip2bus_error0 => Receive_ip2bus_error0,
Rx_FIFO_Full_Fifo => Rx_FIFO_Full_Fifo,
ext_spi_clk => ext_spi_clk,
\icount_out_reg[3]\ => \FIFO_EXISTS.RX_FIFO_II_n_3\,
\out\ => \^generate_level_p_s_cdc.single_bit.cross_plevel_in2scndry_in_cdc_to\,
p_5_in => p_5_in,
ram_full_fb_i_reg => \FIFO_EXISTS.RX_FIFO_II_n_2\,
rx_fifo_reset => rx_fifo_reset,
s_axi_aclk => s_axi_aclk,
scndry_out => Rx_FIFO_Empty_Synced_in_SPI_domain,
spiXfer_done_int => spiXfer_done_int
);
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.Rx_FIFO_Full_i_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FIFO_EXISTS.RX_FIFO_FULL_CNTR_I_n_4\,
Q => Rx_FIFO_Full_i,
R => '0'
);
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.Rx_FIFO_Full_int_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => CONTROL_REG_I_n_16,
Q => Rx_FIFO_Full_int,
R => '0'
);
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FIFO_EXISTS.CLK_CROSS_I_n_14\,
Q => \^rx_fifo_empty_i\,
R => '0'
);
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_flag_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^scndry_out\,
Q => Rx_FIFO_Full_Fifo_d1_flag,
R => reset2ip_reset_int
);
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => Rx_FIFO_Full_Fifo,
Q => Rx_FIFO_Full_Fifo_d1,
R => rst_to_spi_int
);
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_sig_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FIFO_EXISTS.RX_FIFO_FULL_SYNCED_SPI_2_AXI_CDC_n_3\,
Q => Rx_FIFO_Full_Fifo_d1_sig,
R => '0'
);
\FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I\: entity work.system_axi_quad_spi_shield_0_counter_f_1
port map (
Bus_RNW_reg_reg => Bus_RNW_reg_reg_0,
Bus_RNW_reg_reg_0 => CONTROL_REG_I_n_12,
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\ => \^spicr_5_txfifo_rst_frm_axi_clk\,
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_reg\ => \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_4\,
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d1_reg[3]\ => \^fifo_exists.tx_full_emp_intr_md_0_gen.tx_fifo_count_d1_reg[3]_0\(0),
\RESET_FLOPS[15].RST_FLOPS\ => SOFT_RESET_I_n_2,
\RESET_FLOPS[15].RST_FLOPS_0\ => SOFT_RESET_I_n_3,
Tx_FIFO_Full_i => Tx_FIFO_Full_i,
Tx_FIFO_Full_int => \^tx_fifo_full_int\,
bus2ip_reset_ipif_inverted => bus2ip_reset_ipif_inverted,
reset2ip_reset_int => reset2ip_reset_int,
reset_TxFIFO_ptr_int => reset_TxFIFO_ptr_int,
s_axi_aclk => s_axi_aclk,
spiXfer_done_d2 => spiXfer_done_d2,
spiXfer_done_d3 => spiXfer_done_d3,
tx_fifo_count(2 downto 0) => tx_fifo_count(2 downto 0)
);
\FIFO_EXISTS.TX_FIFO_II\: entity work.system_axi_quad_spi_shield_0_async_fifo_fg_2
port map (
Bus_RNW_reg => Bus_RNW_reg,
\OTHER_RATIO_GENERATE.Serial_Dout_reg\ => \FIFO_EXISTS.TX_FIFO_II_n_2\,
Q(7) => data_from_txfifo(0),
Q(6) => data_from_txfifo(1),
Q(5) => data_from_txfifo(2),
Q(4) => data_from_txfifo(3),
Q(3) => data_from_txfifo(4),
Q(2) => data_from_txfifo(5),
Q(1) => data_from_txfifo(6),
Q(0) => data_from_txfifo(7),
ext_spi_clk => ext_spi_clk,
\gic0.gc1.count_reg[0]\ => \^gic0.gc1.count_reg[0]\,
ip2Bus_WrAck_core_reg_1 => \^ip2bus_wrack_core_reg_1\,
\out\ => tx_fifo_empty,
p_6_in => p_6_in,
reset_TxFIFO_ptr_int => reset_TxFIFO_ptr_int,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
spicr_9_lsb_to_spi_clk => spicr_9_lsb_to_spi_clk,
\spisel_d1_reg__0\ => \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_22\
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_4\,
Q => Tx_FIFO_Full_i,
R => '0'
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_int_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FIFO_EXISTS.CLK_CROSS_I_n_33\,
Q => \^tx_fifo_full_int\,
R => '0'
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.spiXfer_done_to_axi_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => spiXfer_done_to_axi_1,
Q => spiXfer_done_to_axi_d1,
R => reset2ip_reset_int
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => tx_fifo_count(0),
Q => tx_fifo_count_d1(0),
R => reset2ip_reset_int
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => tx_fifo_count(1),
Q => tx_fifo_count_d1(1),
R => reset2ip_reset_int
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => tx_fifo_count(2),
Q => tx_fifo_count_d1(2),
R => reset2ip_reset_int
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^fifo_exists.tx_full_emp_intr_md_0_gen.tx_fifo_count_d1_reg[3]_0\(0),
Q => tx_fifo_count_d1(3),
R => reset2ip_reset_int
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d2_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => tx_fifo_count_d1(0),
Q => tx_fifo_count_d2(0),
R => reset2ip_reset_int
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d2_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => tx_fifo_count_d1(1),
Q => tx_fifo_count_d2(1),
R => reset2ip_reset_int
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d2_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => tx_fifo_count_d1(2),
Q => tx_fifo_count_d2(2),
R => reset2ip_reset_int
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d2_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => tx_fifo_count_d1(3),
Q => tx_fifo_count_d2(3),
R => reset2ip_reset_int
);
\FIFO_EXISTS.data_Exists_RcFIFO_int_d1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^rx_fifo_empty_i\,
O => data_Exists_RcFIFO_pulse038_in
);
\FIFO_EXISTS.data_Exists_RcFIFO_int_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => data_Exists_RcFIFO_pulse038_in,
Q => data_Exists_RcFIFO_int_d1,
R => reset2ip_reset_int
);
\FIFO_EXISTS.tx_occ_msb_4_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => tx_fifo_count_d2(3),
Q => tx_occ_msb_4,
R => reset2ip_reset_int
);
INTERRUPT_CONTROL_I: entity work.system_axi_quad_spi_shield_0_interrupt_control
port map (
D(8) => bus2IP_Data_for_interrupt_core(23),
D(7 downto 0) => s_axi_wdata(7 downto 0),
E(0) => E(0),
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\ => CONTROL_REG_I_n_15,
\FIFO_EXISTS.tx_occ_msb_4_reg\ => \FIFO_EXISTS.CLK_CROSS_I_n_19\,
\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\ => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\,
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\ => \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ => \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]\,
IP2Bus_RdAck_1 => IP2Bus_RdAck_1,
IP2Bus_WrAck_1 => IP2Bus_WrAck_1,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[23]\(8 downto 0) => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[23]_0\(8 downto 0),
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ => \^ip2bus_rdack_core_reg\,
\LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_3\ => \FIFO_EXISTS.CLK_CROSS_I_n_20\,
\LOGIC_GENERATION_FDR.MODF_STROBE_S2AX_3\ => \FIFO_EXISTS.CLK_CROSS_I_n_22\,
\LOGIC_GENERATION_FDR.SLV_MODF_STRB_S2AX_3\ => \FIFO_EXISTS.CLK_CROSS_I_n_21\,
\LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_3\ => \FIFO_EXISTS.CLK_CROSS_I_n_18\,
dtr_underrun_d1_reg => \FIFO_EXISTS.FIFO_IF_MODULE_I_n_4\,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
ip2Bus_RdAck_intr_reg_hole => ip2Bus_RdAck_intr_reg_hole,
ip2Bus_WrAck_core_reg => ip2Bus_WrAck_core_reg,
ip2Bus_WrAck_intr_reg_hole => ip2Bus_WrAck_intr_reg_hole,
ip2intc_irpt => ip2intc_irpt,
ipif_glbl_irpt_enable_reg => ipif_glbl_irpt_enable_reg,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_1_in14_in => \^p_1_in14_in\,
p_1_in17_in => \^p_1_in17_in\,
p_1_in20_in => \^p_1_in20_in\,
p_1_in23_in => \^p_1_in23_in\,
p_1_in26_in => \^p_1_in26_in\,
p_1_in29_in => \^p_1_in29_in\,
p_1_in32_in => \^p_1_in32_in\,
p_1_in35_in => \^p_1_in35_in\,
rc_FIFO_Full_d1_reg => \FIFO_EXISTS.FIFO_IF_MODULE_I_n_3\,
reset2ip_reset_int => reset2ip_reset_int,
s_axi_aclk => s_axi_aclk,
tx_FIFO_Empty_d1_reg => \FIFO_EXISTS.FIFO_IF_MODULE_I_n_5\,
wrack => wrack
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => D(10),
Q => \s_axi_rdata_i_reg[31]\(10),
R => reset2ip_reset_int
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => D(9),
Q => \s_axi_rdata_i_reg[31]\(9),
R => reset2ip_reset_int
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => D(8),
Q => \s_axi_rdata_i_reg[31]\(8),
R => reset2ip_reset_int
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => D(7),
Q => \s_axi_rdata_i_reg[31]\(7),
R => reset2ip_reset_int
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => D(6),
Q => \s_axi_rdata_i_reg[31]\(6),
R => reset2ip_reset_int
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => D(5),
Q => \s_axi_rdata_i_reg[31]\(5),
R => reset2ip_reset_int
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => D(4),
Q => \s_axi_rdata_i_reg[31]\(4),
R => reset2ip_reset_int
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => D(3),
Q => \s_axi_rdata_i_reg[31]\(3),
R => reset2ip_reset_int
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => D(2),
Q => \s_axi_rdata_i_reg[31]\(2),
R => reset2ip_reset_int
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => D(1),
Q => \s_axi_rdata_i_reg[31]\(1),
R => reset2ip_reset_int
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => D(0),
Q => \s_axi_rdata_i_reg[31]\(0),
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_Error_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => IP2Bus_Error_1,
Q => IP2Bus_Error,
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_RdAck_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => IP2Bus_RdAck_1,
Q => p_15_out,
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_WrAck_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => IP2Bus_WrAck_1,
Q => p_16_out,
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => read_ack_delay_6,
I1 => read_ack_delay_7,
O => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_i_1_n_0\
);
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_i_1_n_0\,
Q => \^ip2bus_rdack_core_reg\,
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2Bus_WrAck_core_reg,
Q => \^ip2bus_wrack_core_reg_1\,
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => wr_ce_or_reduce_core_cmb,
Q => ip2Bus_WrAck_core_reg_d1,
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_reg_0\,
Q => ip2Bus_WrAck_core_reg,
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_1_reg_r\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => '1',
Q => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_1_reg_r_n_0\,
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_2_reg_r\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_1_reg_r_n_0\,
Q => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_2_reg_r_n_0\,
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_3_reg_r\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_2_reg_r_n_0\,
Q => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_3_reg_r_n_0\,
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_r\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_3_reg_r_n_0\,
Q => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_r_n_0\,
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_srl4___NO_DUAL_QUAD_MODE.QSPI_NORMAL_QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_r\: unisim.vcomponents.SRL16E
port map (
A0 => '1',
A1 => '1',
A2 => '0',
A3 => '0',
CE => '1',
CLK => s_axi_aclk,
D => rd_ce_or_reduce_core_cmb,
Q => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_srl4___NO_DUAL_QUAD_MODE.QSPI_NORMAL_QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_r_n_0\
);
\LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_NO_DUAL_QUAD_MODE.QSPI_NORMAL_QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_r\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_srl4___NO_DUAL_QUAD_MODE.QSPI_NORMAL_QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_r_n_0\,
Q => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_NO_DUAL_QUAD_MODE.QSPI_NORMAL_QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_r_n_0\,
R => '0'
);
\LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_gate\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_NO_DUAL_QUAD_MODE.QSPI_NORMAL_QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_r_n_0\,
I1 => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_r_n_0\,
O => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_gate_n_0\
);
\LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_r\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_r_n_0\,
Q => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_r_n_0\,
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_6_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_gate_n_0\,
Q => read_ack_delay_6,
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_7_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => read_ack_delay_6,
Q => read_ack_delay_7,
R => reset2ip_reset_int
);
\LOGIC_FOR_MD_0_GEN.SPI_MODULE_I\: entity work.system_axi_quad_spi_shield_0_qspi_mode_0_module
port map (
Allow_MODF_Strobe => Allow_MODF_Strobe,
Allow_Slave_MODF_Strobe => Allow_Slave_MODF_Strobe,
D(0) => Serial_Din,
D_0 => D_0,
E(0) => \USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_18_out\,
\LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_2\ => \FIFO_EXISTS.CLK_CROSS_I_n_41\,
\LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_2\ => \FIFO_EXISTS.CLK_CROSS_I_n_15\,
\LOGIC_GENERATION_FDR.SPICR_4_CPHA_AX2S_2\ => \FIFO_EXISTS.CLK_CROSS_I_n_39\,
\LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_2\ => \FIFO_EXISTS.CLK_CROSS_I_n_43\,
\LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_SYNC_AXI_2_SPI_2\ => \FIFO_EXISTS.CLK_CROSS_I_n_31\,
\LOGIC_GENERATION_FDR.Slave_MODF_strobe_cdc_from_spi_int_2_reg\ => \FIFO_EXISTS.CLK_CROSS_I_n_1\,
\LOGIC_GENERATION_FDR.spisel_pulse_cdc_from_spi_int_2_reg\ => \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_20\,
\LOGIC_GENERATION_FDR.spisel_pulse_cdc_from_spi_int_2_reg_0\ => \FIFO_EXISTS.CLK_CROSS_I_n_0\,
MODF_strobe0 => MODF_strobe0,
\OTHER_RATIO_GENERATE.Shift_Reg_reg[6]_0\ => \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_23\,
Q(7) => data_from_txfifo(0),
Q(6) => data_from_txfifo(1),
Q(5) => data_from_txfifo(2),
Q(4) => data_from_txfifo(3),
Q(3) => data_from_txfifo(4),
Q(2) => data_from_txfifo(5),
Q(1) => data_from_txfifo(6),
Q(0) => data_from_txfifo(7),
R => R,
RESET_SYNC_AX2S_2 => RESET_SYNC_AXI_SPI_CLK_INST_n_0,
RESET_SYNC_AX2S_2_0 => \FIFO_EXISTS.CLK_CROSS_I_n_16\,
RESET_SYNC_AX2S_2_1 => RESET_SYNC_AXI_SPI_CLK_INST_n_3,
RESET_SYNC_AX2S_2_2 => RESET_SYNC_AXI_SPI_CLK_INST_n_4,
Rst_to_spi => rst_to_spi_int,
SPICR_2_MST_N_SLV_to_spi_clk => SPICR_2_MST_N_SLV_to_spi_clk,
SPISEL_sync => SPISEL_sync,
SPIXfer_done_int_d1_reg_0 => \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_8\,
SR_5_Tx_comeplete_Empty => SR_5_Tx_comeplete_Empty,
Slave_MODF_strobe0 => Slave_MODF_strobe0,
drr_Overrun_int => drr_Overrun_int,
dtr_underrun_int => dtr_underrun_int,
empty_fwft_fb_o_i_reg => \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_22\,
ext_spi_clk => ext_spi_clk,
\goreg_dm.dout_i_reg[0]\ => \FIFO_EXISTS.TX_FIFO_II_n_2\,
\goreg_dm.dout_i_reg[7]\(0) => \FIFO_EXISTS.CLK_CROSS_I_n_37\,
\gpr1.dout_i_reg[7]\(7) => receive_Data_int(0),
\gpr1.dout_i_reg[7]\(6) => receive_Data_int(1),
\gpr1.dout_i_reg[7]\(5) => receive_Data_int(2),
\gpr1.dout_i_reg[7]\(4) => receive_Data_int(3),
\gpr1.dout_i_reg[7]\(3) => receive_Data_int(4),
\gpr1.dout_i_reg[7]\(2) => receive_Data_int(5),
\gpr1.dout_i_reg[7]\(1) => receive_Data_int(6),
\gpr1.dout_i_reg[7]\(0) => receive_Data_int(7),
io0_o => io0_o,
io0_t => io0_t,
io1_t => io1_t,
modf_strobe_int => modf_strobe_int,
\out\ => tx_fifo_empty,
p_6_out => p_6_out,
p_7_out => p_7_out,
ram_full_fb_i_reg => \FIFO_EXISTS.RX_FIFO_II_n_2\,
ram_full_i_reg => Rx_FIFO_Full_Fifo_org,
register_Data_slvsel_int => register_Data_slvsel_int,
sck_i => sck_i,
sck_o => sck_o,
sck_t => sck_t,
scndry_out => Rx_FIFO_Empty_Synced_in_SPI_domain,
serial_dout_int => serial_dout_int,
spiXfer_done_int => spiXfer_done_int,
spicr_0_loop_to_spi_clk => spicr_0_loop_to_spi_clk,
spicr_1_spe_to_spi_clk => spicr_1_spe_to_spi_clk,
spicr_3_cpol_to_spi_clk => spicr_3_cpol_to_spi_clk,
spicr_4_cpha_to_spi_clk => spicr_4_cpha_to_spi_clk,
spicr_9_lsb_to_spi_clk => spicr_9_lsb_to_spi_clk,
spisel => spisel,
spisel_d1_reg => spisel_d1_reg,
ss_o(0) => ss_o(0),
ss_t => ss_t,
stop_clock => stop_clock,
transfer_start_d1_reg_0 => \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_11\
);
RESET_SYNC_AXI_SPI_CLK_INST: entity work.system_axi_quad_spi_shield_0_reset_sync_module
port map (
Allow_MODF_Strobe_reg => RESET_SYNC_AXI_SPI_CLK_INST_n_0,
\DTR_UNDERRUN_FIFO_EXIST_GEN.DTR_underrun_reg\ => RESET_SYNC_AXI_SPI_CLK_INST_n_3,
\OTHER_RATIO_GENERATE.sck_o_int_reg\ => RESET_SYNC_AXI_SPI_CLK_INST_n_4,
Rst_to_spi => rst_to_spi_int,
SPICR_2_MST_N_SLV_to_spi_clk => SPICR_2_MST_N_SLV_to_spi_clk,
SPISEL_sync => SPISEL_sync,
ext_spi_clk => ext_spi_clk,
p_6_out => p_6_out,
reset2ip_reset_int => reset2ip_reset_int,
transfer_start_reg => \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_11\
);
SOFT_RESET_I: entity work.system_axi_quad_spi_shield_0_soft_reset
port map (
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\ => \^spicr_5_txfifo_rst_frm_axi_clk\,
D(0) => tx_fifo_count(0),
bus2ip_reset_ipif_inverted => bus2ip_reset_ipif_inverted,
\icount_out_reg[0]\ => SOFT_RESET_I_n_2,
\icount_out_reg[0]_0\ => SOFT_RESET_I_n_3,
reset2ip_reset_int => reset2ip_reset_int,
reset_trig0 => reset_trig0,
s_axi_aclk => s_axi_aclk,
sw_rst_cond => sw_rst_cond,
sw_rst_cond_d1 => sw_rst_cond_d1,
wrack => wrack
);
\STATUS_REG_MODE_0_GEN.STATUS_SLAVE_SEL_REG_I\: entity work.system_axi_quad_spi_shield_0_qspi_status_slave_sel_reg
port map (
\GEN_BKEND_CE_REGISTERS[28].ce_out_i_reg[28]\ => \GEN_BKEND_CE_REGISTERS[28].ce_out_i_reg[28]\,
SPISSR_frm_axi_clk => \^spissr_frm_axi_clk\,
modf_reg_0 => \FIFO_EXISTS.CLK_CROSS_I_n_32\,
reset2ip_reset_int => reset2ip_reset_int,
s_axi_aclk => s_axi_aclk,
sr_3_MODF_int => \^sr_3_modf_int\
);
ip2Bus_RdAck_intr_reg_hole_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr_controller_rd_ce_or_reduce,
Q => ip2Bus_RdAck_intr_reg_hole_d1,
R => reset2ip_reset_int
);
ip2Bus_RdAck_intr_reg_hole_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2Bus_RdAck_intr_reg_hole0,
Q => ip2Bus_RdAck_intr_reg_hole,
R => reset2ip_reset_int
);
ip2Bus_WrAck_intr_reg_hole_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg,
Q => ip2Bus_WrAck_intr_reg_hole_d1,
R => reset2ip_reset_int
);
ip2Bus_WrAck_intr_reg_hole_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2Bus_WrAck_intr_reg_hole0,
Q => ip2Bus_WrAck_intr_reg_hole,
R => reset2ip_reset_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_axi_quad_spi_top is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
sck_t : out STD_LOGIC;
io0_t : out STD_LOGIC;
ss_t : out STD_LOGIC;
io1_t : out STD_LOGIC;
sck_o : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
io0_o : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 1 downto 0 );
io0_i : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
io1_i : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 10 downto 0 );
spisel : in STD_LOGIC;
sck_i : in STD_LOGIC;
s_axi4_aclk : in STD_LOGIC;
s_axi4_aresetn : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_axi_quad_spi_top : entity is "axi_quad_spi_top";
end system_axi_quad_spi_shield_0_axi_quad_spi_top;
architecture STRUCTURE of system_axi_quad_spi_shield_0_axi_quad_spi_top is
signal \CONTROL_REG_I/SPICR_data_int_reg0\ : STD_LOGIC;
signal \FIFO_EXISTS.FIFO_IF_MODULE_I/Transmit_ip2bus_error0\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/interrupt_wrce_strb\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/intr2bus_rdack0\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/ipif_glbl_irpt_enable_reg\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/irpt_rdack\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/irpt_rdack_d1\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/irpt_wrack\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/irpt_wrack_d1\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/irpt_wrack_d11\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_0_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_0_in10_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_0_in13_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_0_in16_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_0_in19_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_0_in1_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_0_in4_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_0_in7_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_1_in14_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_1_in17_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_1_in20_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_1_in23_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_1_in26_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_1_in29_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_1_in32_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_1_in35_in\ : STD_LOGIC;
signal IP2Bus_Data : STD_LOGIC_VECTOR ( 0 to 31 );
signal IP2Bus_Error : STD_LOGIC;
signal IP2Bus_Error_1 : STD_LOGIC;
signal IP2Bus_SPICR_Data_int : STD_LOGIC_VECTOR ( 0 to 0 );
signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/p_3_in\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/p_5_in\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/p_6_in\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\ : STD_LOGIC;
signal \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_10\ : STD_LOGIC;
signal \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_13\ : STD_LOGIC;
signal \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_29\ : STD_LOGIC;
signal \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_33\ : STD_LOGIC;
signal \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_34\ : STD_LOGIC;
signal \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_37\ : STD_LOGIC;
signal \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_40\ : STD_LOGIC;
signal \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_46\ : STD_LOGIC;
signal \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_47\ : STD_LOGIC;
signal \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_48\ : STD_LOGIC;
signal \QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_n_22\ : STD_LOGIC;
signal \QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_n_32\ : STD_LOGIC;
signal \QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_n_52\ : STD_LOGIC;
signal \QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_n_60\ : STD_LOGIC;
signal \QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_n_61\ : STD_LOGIC;
signal \QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_n_71\ : STD_LOGIC;
signal Rx_FIFO_Empty : STD_LOGIC;
signal Rx_FIFO_Full_Fifo_d1_synced : STD_LOGIC;
signal \SOFT_RESET_I/reset_trig0\ : STD_LOGIC;
signal \SOFT_RESET_I/sw_rst_cond\ : STD_LOGIC;
signal \SOFT_RESET_I/sw_rst_cond_d1\ : STD_LOGIC;
signal SPISSR_frm_axi_clk : STD_LOGIC;
signal Tx_FIFO_Empty_SPISR_to_axi_clk : STD_LOGIC;
signal Tx_FIFO_Full_int : STD_LOGIC;
signal bus2ip_reset_ipif_inverted : STD_LOGIC;
signal bus2ip_wrce_int : STD_LOGIC_VECTOR ( 7 to 7 );
signal data_from_rx_fifo : STD_LOGIC_VECTOR ( 0 to 6 );
signal intr_controller_rd_ce_or_reduce : STD_LOGIC;
signal intr_ip2bus_data : STD_LOGIC_VECTOR ( 0 to 0 );
signal io0_i_sync : STD_LOGIC;
signal io1_i_sync : STD_LOGIC;
signal ip2Bus_Data_1 : STD_LOGIC_VECTOR ( 23 to 31 );
signal ip2Bus_RdAck_core_reg : STD_LOGIC;
signal ip2Bus_RdAck_intr_reg_hole0 : STD_LOGIC;
signal ip2Bus_RdAck_intr_reg_hole_d1 : STD_LOGIC;
signal ip2Bus_WrAck_core_reg_1 : STD_LOGIC;
signal ip2Bus_WrAck_core_reg_d1 : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole0 : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole_d1 : STD_LOGIC;
signal p_15_out : STD_LOGIC;
signal p_16_out : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal rd_ce_or_reduce_core_cmb : STD_LOGIC;
signal rx_fifo_count : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rx_fifo_empty_i : STD_LOGIC;
signal spicr_0_loop_frm_axi_clk : STD_LOGIC;
signal spicr_1_spe_frm_axi_clk : STD_LOGIC;
signal spicr_2_mst_n_slv_frm_axi_clk : STD_LOGIC;
signal spicr_3_cpol_frm_axi_clk : STD_LOGIC;
signal spicr_4_cpha_frm_axi_clk : STD_LOGIC;
signal spicr_5_txfifo_rst_frm_axi_clk : STD_LOGIC;
signal spicr_6_rxfifo_rst_frm_axi_clk : STD_LOGIC;
signal spicr_7_ss_frm_axi_clk : STD_LOGIC;
signal spicr_8_tr_inhibit_frm_axi_clk : STD_LOGIC;
signal spicr_9_lsb_frm_axi_clk : STD_LOGIC;
signal spisel_d1_reg_to_axi_clk : STD_LOGIC;
signal sr_3_MODF_int : STD_LOGIC;
signal tx_fifo_count : STD_LOGIC_VECTOR ( 3 to 3 );
signal tx_fifo_full : STD_LOGIC;
signal wr_ce_or_reduce_core_cmb : STD_LOGIC;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of IO0_I_REG : label is "FD";
attribute box_type : string;
attribute box_type of IO0_I_REG : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of IO1_I_REG : label is "FD";
attribute box_type of IO1_I_REG : label is "PRIMITIVE";
begin
IO0_I_REG: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => io0_i,
Q => io0_i_sync,
R => '0'
);
IO1_I_REG: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => io1_i,
Q => io1_i_sync,
R => '0'
);
\QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I\: entity work.system_axi_quad_spi_shield_0_axi_lite_ipif
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
D(10) => intr_ip2bus_data(0),
D(9) => IP2Bus_SPICR_Data_int(0),
D(8) => ip2Bus_Data_1(23),
D(7) => ip2Bus_Data_1(24),
D(6) => ip2Bus_Data_1(25),
D(5) => ip2Bus_Data_1(26),
D(4) => ip2Bus_Data_1(27),
D(3) => ip2Bus_Data_1(28),
D(2) => ip2Bus_Data_1(29),
D(1) => ip2Bus_Data_1(30),
D(0) => ip2Bus_Data_1(31),
E(0) => \INTERRUPT_CONTROL_I/irpt_wrack_d11\,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ => \QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_n_22\,
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\ => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_46\,
IP2Bus_Error => IP2Bus_Error,
IP2Bus_Error_1 => IP2Bus_Error_1,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(10) => IP2Bus_Data(0),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(9) => IP2Bus_Data(22),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(8) => IP2Bus_Data(23),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(7) => IP2Bus_Data(24),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(6) => IP2Bus_Data(25),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(5) => IP2Bus_Data(26),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(4) => IP2Bus_Data(27),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(3) => IP2Bus_Data(28),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(2) => IP2Bus_Data(29),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(1) => IP2Bus_Data(30),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(0) => IP2Bus_Data(31),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[31]\ => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_29\,
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_WrAck_reg\ => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_37\,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg\ => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_40\,
\LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\ => spisel_d1_reg_to_axi_clk,
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2\ => \QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_n_52\,
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_0\ => \QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_n_60\,
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_1\ => \QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_n_61\,
Q(8) => \INTERRUPT_CONTROL_I/p_0_in19_in\,
Q(7) => \INTERRUPT_CONTROL_I/p_0_in16_in\,
Q(6) => \INTERRUPT_CONTROL_I/p_0_in13_in\,
Q(5) => \INTERRUPT_CONTROL_I/p_0_in10_in\,
Q(4) => \INTERRUPT_CONTROL_I/p_0_in7_in\,
Q(3) => \INTERRUPT_CONTROL_I/p_0_in4_in\,
Q(2) => \INTERRUPT_CONTROL_I/p_0_in1_in\,
Q(1) => \INTERRUPT_CONTROL_I/p_0_in\,
Q(0) => \QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_n_71\,
Receive_ip2bus_error_reg => \QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_n_32\,
SPICR_data_int_reg0 => \CONTROL_REG_I/SPICR_data_int_reg0\,
\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]\ => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_48\,
SPISSR_frm_axi_clk => SPISSR_frm_axi_clk,
Transmit_ip2bus_error0 => \FIFO_EXISTS.FIFO_IF_MODULE_I/Transmit_ip2bus_error0\,
Tx_FIFO_Empty_SPISR_to_axi_clk => Tx_FIFO_Empty_SPISR_to_axi_clk,
Tx_FIFO_Full_int => Tx_FIFO_Full_int,
bus2ip_reset_ipif_inverted => bus2ip_reset_ipif_inverted,
bus2ip_wrce_int(0) => bus2ip_wrce_int(7),
empty_fwft_i_reg => Rx_FIFO_Empty,
\goreg_dm.dout_i_reg[7]\(6) => data_from_rx_fifo(0),
\goreg_dm.dout_i_reg[7]\(5) => data_from_rx_fifo(1),
\goreg_dm.dout_i_reg[7]\(4) => data_from_rx_fifo(2),
\goreg_dm.dout_i_reg[7]\(3) => data_from_rx_fifo(3),
\goreg_dm.dout_i_reg[7]\(2) => data_from_rx_fifo(4),
\goreg_dm.dout_i_reg[7]\(1) => data_from_rx_fifo(5),
\goreg_dm.dout_i_reg[7]\(0) => data_from_rx_fifo(6),
\gpregsm1.curr_fwft_state_reg[1]\ => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_33\,
\icount_out_reg[1]\ => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_13\,
interrupt_wrce_strb => \INTERRUPT_CONTROL_I/interrupt_wrce_strb\,
intr2bus_rdack0 => \INTERRUPT_CONTROL_I/intr2bus_rdack0\,
intr_controller_rd_ce_or_reduce => intr_controller_rd_ce_or_reduce,
ip2Bus_RdAck_core_reg => ip2Bus_RdAck_core_reg,
ip2Bus_RdAck_intr_reg_hole0 => ip2Bus_RdAck_intr_reg_hole0,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_core_reg_1 => ip2Bus_WrAck_core_reg_1,
ip2Bus_WrAck_core_reg_d1 => ip2Bus_WrAck_core_reg_d1,
ip2Bus_WrAck_intr_reg_hole0 => ip2Bus_WrAck_intr_reg_hole0,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1_reg => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_10\,
ipif_glbl_irpt_enable_reg => \INTERRUPT_CONTROL_I/ipif_glbl_irpt_enable_reg\,
ipif_glbl_irpt_enable_reg_reg => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_47\,
irpt_rdack => \INTERRUPT_CONTROL_I/irpt_rdack\,
irpt_rdack_d1 => \INTERRUPT_CONTROL_I/irpt_rdack_d1\,
irpt_wrack => \INTERRUPT_CONTROL_I/irpt_wrack\,
irpt_wrack_d1 => \INTERRUPT_CONTROL_I/irpt_wrack_d1\,
modf_reg => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_34\,
\out\ => tx_fifo_full,
p_15_out => p_15_out,
p_16_out => p_16_out,
p_1_in14_in => \INTERRUPT_CONTROL_I/p_1_in14_in\,
p_1_in17_in => \INTERRUPT_CONTROL_I/p_1_in17_in\,
p_1_in20_in => \INTERRUPT_CONTROL_I/p_1_in20_in\,
p_1_in23_in => \INTERRUPT_CONTROL_I/p_1_in23_in\,
p_1_in26_in => \INTERRUPT_CONTROL_I/p_1_in26_in\,
p_1_in29_in => \INTERRUPT_CONTROL_I/p_1_in29_in\,
p_1_in32_in => \INTERRUPT_CONTROL_I/p_1_in32_in\,
p_1_in35_in => \INTERRUPT_CONTROL_I/p_1_in35_in\,
p_3_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_3_in\,
p_4_in => p_4_in,
p_5_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_5_in\,
p_6_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_6_in\,
p_8_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\,
rd_ce_or_reduce_core_cmb => rd_ce_or_reduce_core_cmb,
reset_trig0 => \SOFT_RESET_I/reset_trig0\,
rx_fifo_count(1) => rx_fifo_count(3),
rx_fifo_count(0) => rx_fifo_count(0),
rx_fifo_empty_i => rx_fifo_empty_i,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(4 downto 0) => s_axi_araddr(4 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(4 downto 0) => s_axi_awaddr(4 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(0) => s_axi_bresp(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(10 downto 0) => s_axi_rdata(10 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(0) => s_axi_rresp(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(4) => s_axi_wdata(10),
s_axi_wdata(3 downto 0) => s_axi_wdata(3 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(1 downto 0) => s_axi_wstrb(1 downto 0),
s_axi_wvalid => s_axi_wvalid,
scndry_out => Rx_FIFO_Full_Fifo_d1_synced,
spicr_0_loop_frm_axi_clk => spicr_0_loop_frm_axi_clk,
spicr_1_spe_frm_axi_clk => spicr_1_spe_frm_axi_clk,
spicr_2_mst_n_slv_frm_axi_clk => spicr_2_mst_n_slv_frm_axi_clk,
spicr_3_cpol_frm_axi_clk => spicr_3_cpol_frm_axi_clk,
spicr_4_cpha_frm_axi_clk => spicr_4_cpha_frm_axi_clk,
spicr_5_txfifo_rst_frm_axi_clk => spicr_5_txfifo_rst_frm_axi_clk,
spicr_6_rxfifo_rst_frm_axi_clk => spicr_6_rxfifo_rst_frm_axi_clk,
spicr_7_ss_frm_axi_clk => spicr_7_ss_frm_axi_clk,
spicr_8_tr_inhibit_frm_axi_clk => spicr_8_tr_inhibit_frm_axi_clk,
spicr_9_lsb_frm_axi_clk => spicr_9_lsb_frm_axi_clk,
sr_3_MODF_int => sr_3_MODF_int,
sw_rst_cond => \SOFT_RESET_I/sw_rst_cond\,
sw_rst_cond_d1 => \SOFT_RESET_I/sw_rst_cond_d1\,
tx_fifo_count(0) => tx_fifo_count(3),
wr_ce_or_reduce_core_cmb => wr_ce_or_reduce_core_cmb
);
\QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I\: entity work.system_axi_quad_spi_shield_0_qspi_core_interface
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
Bus_RNW_reg_reg => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_10\,
Bus_RNW_reg_reg_0 => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_13\,
Bus_RNW_reg_reg_1 => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_34\,
D(10) => intr_ip2bus_data(0),
D(9) => IP2Bus_SPICR_Data_int(0),
D(8) => ip2Bus_Data_1(23),
D(7) => ip2Bus_Data_1(24),
D(6) => ip2Bus_Data_1(25),
D(5) => ip2Bus_Data_1(26),
D(4) => ip2Bus_Data_1(27),
D(3) => ip2Bus_Data_1(28),
D(2) => ip2Bus_Data_1(29),
D(1) => ip2Bus_Data_1(30),
D(0) => ip2Bus_Data_1(31),
E(0) => \INTERRUPT_CONTROL_I/irpt_wrack_d11\,
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d1_reg[3]_0\(0) => tx_fifo_count(3),
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ => Rx_FIFO_Empty,
\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\ => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_37\,
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\ => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_33\,
\GEN_BKEND_CE_REGISTERS[28].ce_out_i_reg[28]\ => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_48\,
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\ => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_47\,
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\ => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_46\,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ => \QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_n_22\,
IP2Bus_Error => IP2Bus_Error,
IP2Bus_Error_1 => IP2Bus_Error_1,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[23]_0\(8) => \INTERRUPT_CONTROL_I/p_0_in19_in\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[23]_0\(7) => \INTERRUPT_CONTROL_I/p_0_in16_in\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[23]_0\(6) => \INTERRUPT_CONTROL_I/p_0_in13_in\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[23]_0\(5) => \INTERRUPT_CONTROL_I/p_0_in10_in\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[23]_0\(4) => \INTERRUPT_CONTROL_I/p_0_in7_in\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[23]_0\(3) => \INTERRUPT_CONTROL_I/p_0_in4_in\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[23]_0\(2) => \INTERRUPT_CONTROL_I/p_0_in1_in\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[23]_0\(1) => \INTERRUPT_CONTROL_I/p_0_in\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[23]_0\(0) => \QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_n_71\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]_0\ => \QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_n_61\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]_0\ => \QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_n_60\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[31]_0\ => \QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_n_52\,
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_Error_reg_0\ => \QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_n_32\,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_reg_0\ => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_40\,
Q(6) => data_from_rx_fifo(0),
Q(5) => data_from_rx_fifo(1),
Q(4) => data_from_rx_fifo(2),
Q(3) => data_from_rx_fifo(3),
Q(2) => data_from_rx_fifo(4),
Q(1) => data_from_rx_fifo(5),
Q(0) => data_from_rx_fifo(6),
SPICR_data_int_reg0 => \CONTROL_REG_I/SPICR_data_int_reg0\,
SPISSR_frm_axi_clk => SPISSR_frm_axi_clk,
Transmit_ip2bus_error0 => \FIFO_EXISTS.FIFO_IF_MODULE_I/Transmit_ip2bus_error0\,
Tx_FIFO_Empty_SPISR_to_axi_clk => Tx_FIFO_Empty_SPISR_to_axi_clk,
Tx_FIFO_Full_int => Tx_FIFO_Full_int,
bus2ip_reset_ipif_inverted => bus2ip_reset_ipif_inverted,
bus2ip_wrce_int(0) => bus2ip_wrce_int(7),
empty_fwft_i_reg => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_29\,
ext_spi_clk => ext_spi_clk,
\gic0.gc1.count_reg[0]\ => tx_fifo_full,
\icount_out_reg[3]\(1) => rx_fifo_count(3),
\icount_out_reg[3]\(0) => rx_fifo_count(0),
interrupt_wrce_strb => \INTERRUPT_CONTROL_I/interrupt_wrce_strb\,
intr2bus_rdack0 => \INTERRUPT_CONTROL_I/intr2bus_rdack0\,
intr_controller_rd_ce_or_reduce => intr_controller_rd_ce_or_reduce,
io0_i_sync => io0_i_sync,
io0_o => io0_o,
io0_t => io0_t,
io1_i_sync => io1_i_sync,
io1_t => io1_t,
ip2Bus_RdAck_core_reg => ip2Bus_RdAck_core_reg,
ip2Bus_RdAck_intr_reg_hole0 => ip2Bus_RdAck_intr_reg_hole0,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_core_reg_1 => ip2Bus_WrAck_core_reg_1,
ip2Bus_WrAck_core_reg_d1 => ip2Bus_WrAck_core_reg_d1,
ip2Bus_WrAck_intr_reg_hole0 => ip2Bus_WrAck_intr_reg_hole0,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2intc_irpt => ip2intc_irpt,
ipif_glbl_irpt_enable_reg => \INTERRUPT_CONTROL_I/ipif_glbl_irpt_enable_reg\,
irpt_rdack => \INTERRUPT_CONTROL_I/irpt_rdack\,
irpt_rdack_d1 => \INTERRUPT_CONTROL_I/irpt_rdack_d1\,
irpt_wrack => \INTERRUPT_CONTROL_I/irpt_wrack\,
irpt_wrack_d1 => \INTERRUPT_CONTROL_I/irpt_wrack_d1\,
\out\ => spisel_d1_reg_to_axi_clk,
p_15_out => p_15_out,
p_16_out => p_16_out,
p_1_in14_in => \INTERRUPT_CONTROL_I/p_1_in14_in\,
p_1_in17_in => \INTERRUPT_CONTROL_I/p_1_in17_in\,
p_1_in20_in => \INTERRUPT_CONTROL_I/p_1_in20_in\,
p_1_in23_in => \INTERRUPT_CONTROL_I/p_1_in23_in\,
p_1_in26_in => \INTERRUPT_CONTROL_I/p_1_in26_in\,
p_1_in29_in => \INTERRUPT_CONTROL_I/p_1_in29_in\,
p_1_in32_in => \INTERRUPT_CONTROL_I/p_1_in32_in\,
p_1_in35_in => \INTERRUPT_CONTROL_I/p_1_in35_in\,
p_3_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_3_in\,
p_4_in => p_4_in,
p_5_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_5_in\,
p_6_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_6_in\,
p_8_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\,
rd_ce_or_reduce_core_cmb => rd_ce_or_reduce_core_cmb,
reset_trig0 => \SOFT_RESET_I/reset_trig0\,
rx_fifo_empty_i => rx_fifo_empty_i,
s_axi_aclk => s_axi_aclk,
\s_axi_rdata_i_reg[31]\(10) => IP2Bus_Data(0),
\s_axi_rdata_i_reg[31]\(9) => IP2Bus_Data(22),
\s_axi_rdata_i_reg[31]\(8) => IP2Bus_Data(23),
\s_axi_rdata_i_reg[31]\(7) => IP2Bus_Data(24),
\s_axi_rdata_i_reg[31]\(6) => IP2Bus_Data(25),
\s_axi_rdata_i_reg[31]\(5) => IP2Bus_Data(26),
\s_axi_rdata_i_reg[31]\(4) => IP2Bus_Data(27),
\s_axi_rdata_i_reg[31]\(3) => IP2Bus_Data(28),
\s_axi_rdata_i_reg[31]\(2) => IP2Bus_Data(29),
\s_axi_rdata_i_reg[31]\(1) => IP2Bus_Data(30),
\s_axi_rdata_i_reg[31]\(0) => IP2Bus_Data(31),
s_axi_wdata(9 downto 0) => s_axi_wdata(9 downto 0),
sck_i => sck_i,
sck_o => sck_o,
sck_t => sck_t,
scndry_out => Rx_FIFO_Full_Fifo_d1_synced,
spicr_0_loop_frm_axi_clk => spicr_0_loop_frm_axi_clk,
spicr_1_spe_frm_axi_clk => spicr_1_spe_frm_axi_clk,
spicr_2_mst_n_slv_frm_axi_clk => spicr_2_mst_n_slv_frm_axi_clk,
spicr_3_cpol_frm_axi_clk => spicr_3_cpol_frm_axi_clk,
spicr_4_cpha_frm_axi_clk => spicr_4_cpha_frm_axi_clk,
spicr_5_txfifo_rst_frm_axi_clk => spicr_5_txfifo_rst_frm_axi_clk,
spicr_6_rxfifo_rst_frm_axi_clk => spicr_6_rxfifo_rst_frm_axi_clk,
spicr_7_ss_frm_axi_clk => spicr_7_ss_frm_axi_clk,
spicr_8_tr_inhibit_frm_axi_clk => spicr_8_tr_inhibit_frm_axi_clk,
spicr_9_lsb_frm_axi_clk => spicr_9_lsb_frm_axi_clk,
spisel => spisel,
sr_3_MODF_int => sr_3_MODF_int,
ss_o(0) => ss_o(0),
ss_t => ss_t,
sw_rst_cond => \SOFT_RESET_I/sw_rst_cond\,
sw_rst_cond_d1 => \SOFT_RESET_I/sw_rst_cond_d1\,
wr_ce_or_reduce_core_cmb => wr_ce_or_reduce_core_cmb
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0_axi_quad_spi is
port (
ext_spi_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi4_aclk : in STD_LOGIC;
s_axi4_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi4_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi4_awaddr : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axi4_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi4_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi4_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi4_awlock : in STD_LOGIC;
s_axi4_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi4_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi4_awvalid : in STD_LOGIC;
s_axi4_awready : out STD_LOGIC;
s_axi4_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi4_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi4_wlast : in STD_LOGIC;
s_axi4_wvalid : in STD_LOGIC;
s_axi4_wready : out STD_LOGIC;
s_axi4_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi4_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi4_bvalid : out STD_LOGIC;
s_axi4_bready : in STD_LOGIC;
s_axi4_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi4_araddr : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axi4_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi4_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi4_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi4_arlock : in STD_LOGIC;
s_axi4_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi4_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi4_arvalid : in STD_LOGIC;
s_axi4_arready : out STD_LOGIC;
s_axi4_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi4_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi4_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi4_rlast : out STD_LOGIC;
s_axi4_rvalid : out STD_LOGIC;
s_axi4_rready : in STD_LOGIC;
io0_i : in STD_LOGIC;
io0_o : out STD_LOGIC;
io0_t : out STD_LOGIC;
io1_i : in STD_LOGIC;
io1_o : out STD_LOGIC;
io1_t : out STD_LOGIC;
io2_i : in STD_LOGIC;
io2_o : out STD_LOGIC;
io2_t : out STD_LOGIC;
io3_i : in STD_LOGIC;
io3_o : out STD_LOGIC;
io3_t : out STD_LOGIC;
io0_1_i : in STD_LOGIC;
io0_1_o : out STD_LOGIC;
io0_1_t : out STD_LOGIC;
io1_1_i : in STD_LOGIC;
io1_1_o : out STD_LOGIC;
io1_1_t : out STD_LOGIC;
io2_1_i : in STD_LOGIC;
io2_1_o : out STD_LOGIC;
io2_1_t : out STD_LOGIC;
io3_1_i : in STD_LOGIC;
io3_1_o : out STD_LOGIC;
io3_1_t : out STD_LOGIC;
spisel : in STD_LOGIC;
sck_i : in STD_LOGIC;
sck_o : out STD_LOGIC;
sck_t : out STD_LOGIC;
ss_i : in STD_LOGIC_VECTOR ( 0 to 0 );
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
ss_t : out STD_LOGIC;
ss_1_i : in STD_LOGIC;
ss_1_o : out STD_LOGIC;
ss_1_t : out STD_LOGIC;
cfgclk : out STD_LOGIC;
cfgmclk : out STD_LOGIC;
eos : out STD_LOGIC;
preq : out STD_LOGIC;
clk : in STD_LOGIC;
gsr : in STD_LOGIC;
gts : in STD_LOGIC;
keyclearb : in STD_LOGIC;
usrcclkts : in STD_LOGIC;
usrdoneo : in STD_LOGIC;
usrdonets : in STD_LOGIC;
pack : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC
);
attribute Async_Clk : integer;
attribute Async_Clk of system_axi_quad_spi_shield_0_axi_quad_spi : entity is 0;
attribute C_DUAL_QUAD_MODE : integer;
attribute C_DUAL_QUAD_MODE of system_axi_quad_spi_shield_0_axi_quad_spi : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of system_axi_quad_spi_shield_0_axi_quad_spi : entity is "artix7";
attribute C_FIFO_DEPTH : integer;
attribute C_FIFO_DEPTH of system_axi_quad_spi_shield_0_axi_quad_spi : entity is 16;
attribute C_INSTANCE : string;
attribute C_INSTANCE of system_axi_quad_spi_shield_0_axi_quad_spi : entity is "axi_quad_spi_inst";
attribute C_LSB_STUP : integer;
attribute C_LSB_STUP of system_axi_quad_spi_shield_0_axi_quad_spi : entity is 0;
attribute C_NUM_SS_BITS : integer;
attribute C_NUM_SS_BITS of system_axi_quad_spi_shield_0_axi_quad_spi : entity is 1;
attribute C_NUM_TRANSFER_BITS : integer;
attribute C_NUM_TRANSFER_BITS of system_axi_quad_spi_shield_0_axi_quad_spi : entity is 8;
attribute C_SCK_RATIO : integer;
attribute C_SCK_RATIO of system_axi_quad_spi_shield_0_axi_quad_spi : entity is 16;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of system_axi_quad_spi_shield_0_axi_quad_spi : entity is 0;
attribute C_SHARED_STARTUP : integer;
attribute C_SHARED_STARTUP of system_axi_quad_spi_shield_0_axi_quad_spi : entity is 0;
attribute C_SPI_MEMORY : integer;
attribute C_SPI_MEMORY of system_axi_quad_spi_shield_0_axi_quad_spi : entity is 1;
attribute C_SPI_MEM_ADDR_BITS : integer;
attribute C_SPI_MEM_ADDR_BITS of system_axi_quad_spi_shield_0_axi_quad_spi : entity is 24;
attribute C_SPI_MODE : integer;
attribute C_SPI_MODE of system_axi_quad_spi_shield_0_axi_quad_spi : entity is 0;
attribute C_SUB_FAMILY : string;
attribute C_SUB_FAMILY of system_axi_quad_spi_shield_0_axi_quad_spi : entity is "artix7";
attribute C_S_AXI4_ADDR_WIDTH : integer;
attribute C_S_AXI4_ADDR_WIDTH of system_axi_quad_spi_shield_0_axi_quad_spi : entity is 24;
attribute C_S_AXI4_BASEADDR : integer;
attribute C_S_AXI4_BASEADDR of system_axi_quad_spi_shield_0_axi_quad_spi : entity is -1;
attribute C_S_AXI4_DATA_WIDTH : integer;
attribute C_S_AXI4_DATA_WIDTH of system_axi_quad_spi_shield_0_axi_quad_spi : entity is 32;
attribute C_S_AXI4_HIGHADDR : integer;
attribute C_S_AXI4_HIGHADDR of system_axi_quad_spi_shield_0_axi_quad_spi : entity is 0;
attribute C_S_AXI4_ID_WIDTH : integer;
attribute C_S_AXI4_ID_WIDTH of system_axi_quad_spi_shield_0_axi_quad_spi : entity is 1;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of system_axi_quad_spi_shield_0_axi_quad_spi : entity is 7;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_axi_quad_spi_shield_0_axi_quad_spi : entity is 32;
attribute C_TYPE_OF_AXI4_INTERFACE : integer;
attribute C_TYPE_OF_AXI4_INTERFACE of system_axi_quad_spi_shield_0_axi_quad_spi : entity is 0;
attribute C_UC_FAMILY : integer;
attribute C_UC_FAMILY of system_axi_quad_spi_shield_0_axi_quad_spi : entity is 0;
attribute C_USE_STARTUP : integer;
attribute C_USE_STARTUP of system_axi_quad_spi_shield_0_axi_quad_spi : entity is 0;
attribute C_USE_STARTUP_EXT : integer;
attribute C_USE_STARTUP_EXT of system_axi_quad_spi_shield_0_axi_quad_spi : entity is 0;
attribute C_XIP_MODE : integer;
attribute C_XIP_MODE of system_axi_quad_spi_shield_0_axi_quad_spi : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_shield_0_axi_quad_spi : entity is "axi_quad_spi";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_quad_spi_shield_0_axi_quad_spi : entity is "yes";
end system_axi_quad_spi_shield_0_axi_quad_spi;
architecture STRUCTURE of system_axi_quad_spi_shield_0_axi_quad_spi is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^io0_o\ : STD_LOGIC;
signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_rresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^s_axi_wready\ : STD_LOGIC;
begin
cfgclk <= \<const0>\;
cfgmclk <= \<const0>\;
eos <= \<const0>\;
io0_1_o <= \<const0>\;
io0_1_t <= \<const0>\;
io0_o <= \^io0_o\;
io1_1_o <= \<const0>\;
io1_1_t <= \<const0>\;
io1_o <= \^io0_o\;
io2_1_o <= \<const0>\;
io2_1_t <= \<const0>\;
io2_o <= \<const0>\;
io2_t <= \<const1>\;
io3_1_o <= \<const0>\;
io3_1_t <= \<const0>\;
io3_o <= \<const0>\;
io3_t <= \<const1>\;
preq <= \<const0>\;
s_axi4_arready <= \<const0>\;
s_axi4_awready <= \<const0>\;
s_axi4_bid(0) <= \<const0>\;
s_axi4_bresp(1) <= \<const0>\;
s_axi4_bresp(0) <= \<const0>\;
s_axi4_bvalid <= \<const0>\;
s_axi4_rdata(31) <= \<const0>\;
s_axi4_rdata(30) <= \<const0>\;
s_axi4_rdata(29) <= \<const0>\;
s_axi4_rdata(28) <= \<const0>\;
s_axi4_rdata(27) <= \<const0>\;
s_axi4_rdata(26) <= \<const0>\;
s_axi4_rdata(25) <= \<const0>\;
s_axi4_rdata(24) <= \<const0>\;
s_axi4_rdata(23) <= \<const0>\;
s_axi4_rdata(22) <= \<const0>\;
s_axi4_rdata(21) <= \<const0>\;
s_axi4_rdata(20) <= \<const0>\;
s_axi4_rdata(19) <= \<const0>\;
s_axi4_rdata(18) <= \<const0>\;
s_axi4_rdata(17) <= \<const0>\;
s_axi4_rdata(16) <= \<const0>\;
s_axi4_rdata(15) <= \<const0>\;
s_axi4_rdata(14) <= \<const0>\;
s_axi4_rdata(13) <= \<const0>\;
s_axi4_rdata(12) <= \<const0>\;
s_axi4_rdata(11) <= \<const0>\;
s_axi4_rdata(10) <= \<const0>\;
s_axi4_rdata(9) <= \<const0>\;
s_axi4_rdata(8) <= \<const0>\;
s_axi4_rdata(7) <= \<const0>\;
s_axi4_rdata(6) <= \<const0>\;
s_axi4_rdata(5) <= \<const0>\;
s_axi4_rdata(4) <= \<const0>\;
s_axi4_rdata(3) <= \<const0>\;
s_axi4_rdata(2) <= \<const0>\;
s_axi4_rdata(1) <= \<const0>\;
s_axi4_rdata(0) <= \<const0>\;
s_axi4_rid(0) <= \<const0>\;
s_axi4_rlast <= \<const0>\;
s_axi4_rresp(1) <= \<const0>\;
s_axi4_rresp(0) <= \<const0>\;
s_axi4_rvalid <= \<const0>\;
s_axi4_wready <= \<const0>\;
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \^s_axi_bresp\(1);
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \^s_axi_rdata\(31);
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9 downto 0) <= \^s_axi_rdata\(9 downto 0);
s_axi_rresp(1) <= \^s_axi_rresp\(1);
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
ss_1_o <= \<const0>\;
ss_1_t <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\NO_DUAL_QUAD_MODE.QSPI_NORMAL\: entity work.system_axi_quad_spi_shield_0_axi_quad_spi_top
port map (
ext_spi_clk => ext_spi_clk,
io0_i => io0_i,
io0_o => \^io0_o\,
io0_t => io0_t,
io1_i => io1_i,
io1_t => io1_t,
ip2intc_irpt => ip2intc_irpt,
s_axi4_aclk => s_axi4_aclk,
s_axi4_aresetn => s_axi4_aresetn,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(4 downto 0) => s_axi_araddr(6 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(4 downto 0) => s_axi_awaddr(6 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(0) => \^s_axi_bresp\(1),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(10) => \^s_axi_rdata\(31),
s_axi_rdata(9 downto 0) => \^s_axi_rdata\(9 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(0) => \^s_axi_rresp\(1),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(10) => s_axi_wdata(31),
s_axi_wdata(9 downto 0) => s_axi_wdata(9 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wstrb(1) => s_axi_wstrb(3),
s_axi_wstrb(0) => s_axi_wstrb(0),
s_axi_wvalid => s_axi_wvalid,
sck_i => sck_i,
sck_o => sck_o,
sck_t => sck_t,
spisel => spisel,
ss_o(0) => ss_o(0),
ss_t => ss_t
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_shield_0 is
port (
ext_spi_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
io0_i : in STD_LOGIC;
io0_o : out STD_LOGIC;
io0_t : out STD_LOGIC;
io1_i : in STD_LOGIC;
io1_o : out STD_LOGIC;
io1_t : out STD_LOGIC;
sck_i : in STD_LOGIC;
sck_o : out STD_LOGIC;
sck_t : out STD_LOGIC;
ss_i : in STD_LOGIC_VECTOR ( 0 to 0 );
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
ss_t : out STD_LOGIC;
ip2intc_irpt : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_axi_quad_spi_shield_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_axi_quad_spi_shield_0 : entity is "system_axi_quad_spi_shield_0,axi_quad_spi,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_quad_spi_shield_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_axi_quad_spi_shield_0 : entity is "axi_quad_spi,Vivado 2016.4";
end system_axi_quad_spi_shield_0;
architecture STRUCTURE of system_axi_quad_spi_shield_0 is
signal NLW_U0_cfgclk_UNCONNECTED : STD_LOGIC;
signal NLW_U0_cfgmclk_UNCONNECTED : STD_LOGIC;
signal NLW_U0_eos_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io0_1_o_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io0_1_t_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io1_1_o_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io1_1_t_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io2_1_o_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io2_1_t_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io2_o_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io2_t_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io3_1_o_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io3_1_t_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io3_o_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io3_t_UNCONNECTED : STD_LOGIC;
signal NLW_U0_preq_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi4_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi4_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi4_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi4_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi4_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi4_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_ss_1_o_UNCONNECTED : STD_LOGIC;
signal NLW_U0_ss_1_t_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi4_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi4_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi4_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi4_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi4_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute Async_Clk : integer;
attribute Async_Clk of U0 : label is 0;
attribute C_DUAL_QUAD_MODE : integer;
attribute C_DUAL_QUAD_MODE of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_FIFO_DEPTH : integer;
attribute C_FIFO_DEPTH of U0 : label is 16;
attribute C_INSTANCE : string;
attribute C_INSTANCE of U0 : label is "axi_quad_spi_inst";
attribute C_LSB_STUP : integer;
attribute C_LSB_STUP of U0 : label is 0;
attribute C_NUM_SS_BITS : integer;
attribute C_NUM_SS_BITS of U0 : label is 1;
attribute C_NUM_TRANSFER_BITS : integer;
attribute C_NUM_TRANSFER_BITS of U0 : label is 8;
attribute C_SCK_RATIO : integer;
attribute C_SCK_RATIO of U0 : label is 16;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SHARED_STARTUP : integer;
attribute C_SHARED_STARTUP of U0 : label is 0;
attribute C_SPI_MEMORY : integer;
attribute C_SPI_MEMORY of U0 : label is 1;
attribute C_SPI_MEM_ADDR_BITS : integer;
attribute C_SPI_MEM_ADDR_BITS of U0 : label is 24;
attribute C_SPI_MODE : integer;
attribute C_SPI_MODE of U0 : label is 0;
attribute C_SUB_FAMILY : string;
attribute C_SUB_FAMILY of U0 : label is "artix7";
attribute C_S_AXI4_ADDR_WIDTH : integer;
attribute C_S_AXI4_ADDR_WIDTH of U0 : label is 24;
attribute C_S_AXI4_BASEADDR : integer;
attribute C_S_AXI4_BASEADDR of U0 : label is -1;
attribute C_S_AXI4_DATA_WIDTH : integer;
attribute C_S_AXI4_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI4_HIGHADDR : integer;
attribute C_S_AXI4_HIGHADDR of U0 : label is 0;
attribute C_S_AXI4_ID_WIDTH : integer;
attribute C_S_AXI4_ID_WIDTH of U0 : label is 1;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 7;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TYPE_OF_AXI4_INTERFACE : integer;
attribute C_TYPE_OF_AXI4_INTERFACE of U0 : label is 0;
attribute C_UC_FAMILY : integer;
attribute C_UC_FAMILY of U0 : label is 0;
attribute C_USE_STARTUP : integer;
attribute C_USE_STARTUP of U0 : label is 0;
attribute C_USE_STARTUP_EXT : integer;
attribute C_USE_STARTUP_EXT of U0 : label is 0;
attribute C_XIP_MODE : integer;
attribute C_XIP_MODE of U0 : label is 0;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.system_axi_quad_spi_shield_0_axi_quad_spi
port map (
cfgclk => NLW_U0_cfgclk_UNCONNECTED,
cfgmclk => NLW_U0_cfgmclk_UNCONNECTED,
clk => '0',
eos => NLW_U0_eos_UNCONNECTED,
ext_spi_clk => ext_spi_clk,
gsr => '0',
gts => '0',
io0_1_i => '0',
io0_1_o => NLW_U0_io0_1_o_UNCONNECTED,
io0_1_t => NLW_U0_io0_1_t_UNCONNECTED,
io0_i => io0_i,
io0_o => io0_o,
io0_t => io0_t,
io1_1_i => '0',
io1_1_o => NLW_U0_io1_1_o_UNCONNECTED,
io1_1_t => NLW_U0_io1_1_t_UNCONNECTED,
io1_i => io1_i,
io1_o => io1_o,
io1_t => io1_t,
io2_1_i => '0',
io2_1_o => NLW_U0_io2_1_o_UNCONNECTED,
io2_1_t => NLW_U0_io2_1_t_UNCONNECTED,
io2_i => '0',
io2_o => NLW_U0_io2_o_UNCONNECTED,
io2_t => NLW_U0_io2_t_UNCONNECTED,
io3_1_i => '0',
io3_1_o => NLW_U0_io3_1_o_UNCONNECTED,
io3_1_t => NLW_U0_io3_1_t_UNCONNECTED,
io3_i => '0',
io3_o => NLW_U0_io3_o_UNCONNECTED,
io3_t => NLW_U0_io3_t_UNCONNECTED,
ip2intc_irpt => ip2intc_irpt,
keyclearb => '0',
pack => '0',
preq => NLW_U0_preq_UNCONNECTED,
s_axi4_aclk => '0',
s_axi4_araddr(23 downto 0) => B"000000000000000000000000",
s_axi4_arburst(1 downto 0) => B"00",
s_axi4_arcache(3 downto 0) => B"0000",
s_axi4_aresetn => '0',
s_axi4_arid(0) => '0',
s_axi4_arlen(7 downto 0) => B"00000000",
s_axi4_arlock => '0',
s_axi4_arprot(2 downto 0) => B"000",
s_axi4_arready => NLW_U0_s_axi4_arready_UNCONNECTED,
s_axi4_arsize(2 downto 0) => B"000",
s_axi4_arvalid => '0',
s_axi4_awaddr(23 downto 0) => B"000000000000000000000000",
s_axi4_awburst(1 downto 0) => B"00",
s_axi4_awcache(3 downto 0) => B"0000",
s_axi4_awid(0) => '0',
s_axi4_awlen(7 downto 0) => B"00000000",
s_axi4_awlock => '0',
s_axi4_awprot(2 downto 0) => B"000",
s_axi4_awready => NLW_U0_s_axi4_awready_UNCONNECTED,
s_axi4_awsize(2 downto 0) => B"000",
s_axi4_awvalid => '0',
s_axi4_bid(0) => NLW_U0_s_axi4_bid_UNCONNECTED(0),
s_axi4_bready => '0',
s_axi4_bresp(1 downto 0) => NLW_U0_s_axi4_bresp_UNCONNECTED(1 downto 0),
s_axi4_bvalid => NLW_U0_s_axi4_bvalid_UNCONNECTED,
s_axi4_rdata(31 downto 0) => NLW_U0_s_axi4_rdata_UNCONNECTED(31 downto 0),
s_axi4_rid(0) => NLW_U0_s_axi4_rid_UNCONNECTED(0),
s_axi4_rlast => NLW_U0_s_axi4_rlast_UNCONNECTED,
s_axi4_rready => '0',
s_axi4_rresp(1 downto 0) => NLW_U0_s_axi4_rresp_UNCONNECTED(1 downto 0),
s_axi4_rvalid => NLW_U0_s_axi4_rvalid_UNCONNECTED,
s_axi4_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi4_wlast => '0',
s_axi4_wready => NLW_U0_s_axi4_wready_UNCONNECTED,
s_axi4_wstrb(3 downto 0) => B"0000",
s_axi4_wvalid => '0',
s_axi_aclk => s_axi_aclk,
s_axi_araddr(6 downto 0) => s_axi_araddr(6 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(6 downto 0) => s_axi_awaddr(6 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid,
sck_i => sck_i,
sck_o => sck_o,
sck_t => sck_t,
spisel => '1',
ss_1_i => '0',
ss_1_o => NLW_U0_ss_1_o_UNCONNECTED,
ss_1_t => NLW_U0_ss_1_t_UNCONNECTED,
ss_i(0) => ss_i(0),
ss_o(0) => ss_o(0),
ss_t => ss_t,
usrcclkts => '0',
usrdoneo => '1',
usrdonets => '0'
);
end STRUCTURE;
|
apache-2.0
|
49d941f57b831a26ff741ae25e1e3218
| 0.590529 | 2.620606 | false | false | false | false |
daniw/add
|
rot_enc/cpu_ctrl.vhd
| 3 | 7,838 |
-------------------------------------------------------------------------------
-- Entity: cpu_ctrl
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- Control unit without instruction pipelining for the RISC-CPU of the
-- von-Neuman MCU.
-------------------------------------------------------------------------------
-- Total # of FFs: ... tbd ...
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity cpu_ctrl is
port(rst : in std_logic;
clk : in std_logic;
-- bus interface signals
data_in : in std_logic_vector(DW-1 downto 0);
addr : out std_logic_vector(AW-1 downto 0);
data_out : out std_logic_vector(DW-1 downto 0);
wr_enb : out std_logic;
rd_enb : out std_logic;
-- CPU internal interfaces
reg_in : in t_reg2ctr;
reg_out : out t_ctr2reg;
prc_in : in t_prc2ctr;
prc_out : out t_ctr2prc;
alu_in : in t_alu2ctr;
alu_out : out t_ctr2alu
);
end cpu_ctrl;
architecture rtl of cpu_ctrl is
-- FSM signals
type state is (s_if, s_id, s_ex, s_ma, s_rw);
signal c_st, n_st : state;
-- Instruction register & decoding
signal instr_reg : std_logic_vector(DW-1 downto 0);
signal instr_enb : std_logic;
signal opcode : natural range 0 to 2**OPCW-1;
-- write enable signals registered
signal reg_enb_res : std_logic;
signal reg_enb_data : std_logic;
begin
-----------------------------------------------------------------------------
-- Bus Interface
-----------------------------------------------------------------------------
data_out <= reg_in.data;
-----------------------------------------------------------------------------
-- Register Block Interface
-- registered to break comb. path from bus system to register block
-----------------------------------------------------------------------------
P_rbi: process(clk)
begin
if rising_edge(clk) then
-- write enable and data signals to reg block;
reg_out.enb_res <= reg_enb_res;
reg_out.enb_data <= reg_enb_data;
if opcode = 16 then
-- load instruction, register low & high byte from bus system
reg_out.data <= data_in;
elsif opcode = 15 then
-- setih instruction, register low byte from instr. reg as high byte
reg_out.data(DW-1 downto DW/2) <= instr_reg(DW/2-1 downto 0);
else
-- e.g. setil instruction, register low byte from instr. reg as low byte
reg_out.data <= instr_reg;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Instruction register
-----------------------------------------------------------------------------
P_ir: process(clk)
begin
if rising_edge(clk) then
-- instruction register
if instr_enb = '1' then
instr_reg <= data_in;
end if;
end if;
end process;
-- Instruction register decoding
opcode <= to_integer(unsigned(instr_reg(DW-1 downto DW-OPCW)));
alu_out.op <= instr_reg(DW-1-(OPCW-OPAW) downto DW-OPCW);
alu_out.imm <= instr_reg(IOWW-1 downto 0);
reg_out.dest <= instr_reg(10 downto 8);
reg_out.src1 <= instr_reg(10 downto 8) when (opcode >= 12 and opcode <= 15) else
instr_reg( 7 downto 5);
reg_out.src2 <= instr_reg( 4 downto 2);
prc_out.addr <= instr_reg(AW-1 downto 0);
-----------------------------------------------------------------------------
-- FSM: Mealy-type
-----------------------------------------------------------------------------
-- memoryless process
p_fsm_com: process (c_st, opcode, alu_in, reg_in, prc_in)
begin
-- default assignments for all outputs
n_st <= c_st; -- remain in current state
rd_enb <= '0';
wr_enb <= '0';
instr_enb <= '0';
reg_enb_res <= '0';
reg_enb_data <= '0';
alu_out.enb <= '0';
prc_out.enb <= '0';
prc_out.mode <= linear;
addr <= (others => '1'); -- reset vector
-- specific assignments
case c_st is
when s_if =>
-- instruction fetch ----------------------------------
rd_enb <= '1';
if prc_in.exc = no_err then
-- normal fetch if no exception, otherwise go to reset vector
addr <= prc_in.pc;
end if;
n_st <= s_id;
when s_id =>
-- instruction decode ---------------------------------
instr_enb <= '1';
n_st <= s_ex;
when s_ex =>
-- instruction execute --------------------------------
if opcode <= 7 or (opcode >= 12 and opcode <= 15) then
-- reg/reg-instruction, addil/h instruction, setil/h instruction
-- increase PC, store result/flags from ALU, start next instr. cycle
prc_out.enb <= '1';
reg_enb_res <= '1';
alu_out.enb <= '1';
n_st <= s_if;
elsif opcode = 16 or opcode = 17 then
-- load/store instruction
-- increase PC, go to "Memory Access" state
prc_out.enb <= '1';
n_st <= s_ma;
elsif opcode = 24 then
-- jump instruction
-- set PC to absolute address, start next instr. cycle
prc_out.enb <= '1';
prc_out.mode <= abs_jump;
n_st <= s_if;
elsif opcode >= 25 and opcode <= 29 then
-- branch instructions
prc_out.enb <= '1';
n_st <= s_if;
-- bne: branch if not equal (not Z)
if opcode = 25 and alu_in.flag(Z) = '0' then
prc_out.mode <= rel_offset;
end if;
-- bge: branch if greater/equal (not N or Z)
if opcode = 26 and (alu_in.flag(N) = '0' or alu_in.flag(Z) = '1') then
prc_out.mode <= rel_offset;
end if;
-- blt: branch if less than (N)
if opcode = 27 and alu_in.flag(N) = '1' then
prc_out.mode <= rel_offset;
end if;
-- bca: branch if carry set (C)
if opcode = 28 and alu_in.flag(C) = '1' then
prc_out.mode <= rel_offset;
end if;
-- bov: branch if overflow set (O)
if opcode = 29 and alu_in.flag(O) = '1' then
prc_out.mode <= rel_offset;
end if;
else
-- NOP instruction
prc_out.enb <= '1';
n_st <= s_if;
end if;
when s_ma =>
-- memory access -------------------------------------
if opcode = 16 then
-- load instruction
-- read data from memory and go to "Register Write-Back" state
rd_enb <= '1';
n_st <= s_rw;
else
-- store instruction
-- write data from register to memory and start next instr. cycle
wr_enb <= '1';
n_st <= s_if;
end if;
addr <= reg_in.addr;
when s_rw =>
-- register write-back -------------------------------
-- store data from memory in register and start next instr. cycle
reg_enb_data <= '1';
n_st <= s_if;
when others =>
n_st <= s_if; -- handle parasitic states
end case;
end process;
-----------------------------------------------------------------------------
-- sequential process
-- # of FFs: 3 (assuming binary state encoding)
P_fsm_seq: process(rst, clk)
begin
if rst = '1' then
c_st <= s_if;
elsif rising_edge(clk) then
c_st <= n_st;
end if;
end process;
end rtl;
|
gpl-2.0
|
f88b1435f391411a9e2479726a3543d4
| 0.446415 | 4.09295 | false | false | false | false |
KPU-RISC/KPU
|
VHDL/Not8Bit.vhd
| 1 | 1,300 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/20/2015 05:45:05 PM
-- Design Name:
-- Module Name: Not8Bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Not8Bit is
Port
(
Input : in BIT_VECTOR(7 downto 0); -- 1st 8-bit input value
Output : out BIT_VECTOR(7 downto 0) -- 8-bit output value
);
end Not8Bit;
architecture Behavioral of Not8Bit is
begin
Output(0) <= not Input(0);
Output(1) <= not Input(1);
Output(2) <= not Input(2);
Output(3) <= not Input(3);
Output(4) <= not Input(4);
Output(5) <= not Input(5);
Output(6) <= not Input(6);
Output(7) <= not Input(7);
end Behavioral;
|
mit
|
65bd45749fe5bc70fbde21d6e2d155ae
| 0.566923 | 3.735632 | false | false | false | false |
KPU-RISC/KPU
|
VHDL/CPU8Bit.vhd
| 1 | 39,284 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/20/2015 10:41:46 PM
-- Design Name:
-- Module Name: CPU8Bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CPU8Bit is
port
(
Clock : in BIT;
Start : in BIT;
Reset : in BIT;
Load_RAM : in BIT;
Select_RAM : in BIT;
Address_RAM : in BIT_VECTOR(15 downto 0);
Input_RAM : in BIT_VECTOR(7 downto 0);
PC : in BIT_VECTOR(15 downto 0);
Load_PC : in BIT;
InputPort_A : in BIT_VECTOR(7 downto 0);
InputPort_B : in BIT_VECTOR(7 downto 0);
OutputPort_C : out BIT_VECTOR(7 downto 0);
OutputPort_D : out BIT_VECTOR(7 downto 0);
Instruction : out BIT_VECTOR(7 downto 0)
);
end CPU8Bit;
architecture Behavioral of CPU8Bit is
component Counter4Bit is
port
(
Clock : in BIT;
Reset : in BIT;
Output: out STD_LOGIC_VECTOR(3 downto 0)
);
end component Counter4Bit;
component Decoder3to8 is
Port
(
F : in BIT_VECTOR(2 downto 0); -- 3-Bit Function Code (Input)
X : out BIT_VECTOR(7 downto 0); -- 8-Bit State (Output)
Started: in BIT -- Is the CPU already running?
);
end component Decoder3to8;
component RAM_Wrapper is
port
(
Clock: IN BIT;
Load: IN BIT;
Sel: IN BIT; -- Requests the data from the RAM
Ret: IN BIT; -- Returns the data from the RAM and places it onto the data bus
Address: IN BIT_VECTOR(15 DOWNTO 0);
Input: IN BIT_VECTOR(7 DOWNTO 0);
Output: OUT BIT_VECTOR(7 DOWNTO 0)
);
end component RAM_Wrapper;
component Register8Bit is
Port
(
Load : in BIT; -- Load Line
Sel : in BIT; -- Select Line
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
State : out BIT_VECTOR(7 downto 0) -- Current state of the Flip Flop
);
end component Register8Bit;
component Register8Bit2WayOutput is
Port
(
Load : in BIT; -- Load Line
Sel1 : in BIT; -- Select Line #1
Sel2 : in BIT; -- Select Line #2
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Output1 : out BIT_VECTOR(7 downto 0); -- 8-bit output value #1
Output2 : out BIT_VECTOR(7 downto 0); -- 8-bit output value #2
State : out BIT_VECTOR(7 downto 0) -- Current state of the Flip Flop
);
end component Register8Bit2WayOutput;
component Register8Bit2WayInput is
Port
(
Load1 : in BIT; -- Load Line #1
Load2 : in BIT; -- Load Line #2
Sel : in BIT; -- Select Line
Input1 : in BIT_VECTOR(7 downto 0); -- 8-bit input value #1
Input2 : in BIT_VECTOR(7 downto 0); -- 8-bit input value #2
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
State : out BIT_VECTOR(7 downto 0) -- Current state of the Flip Flop
);
end component Register8Bit2WayInput;
component Register16Bit is
Port
(
Load : in BIT; -- Load Line
Sel : in BIT; -- Select Line
Input : in BIT_VECTOR(15 downto 0); -- 16-bit input value
Output : out BIT_VECTOR(15 downto 0); -- 16-bit output value
State : out BIT_VECTOR(15 downto 0) -- Current state of the Flip Flop
);
end component Register16Bit;
component RegisterExtended16Bit is
Port
(
Load_8Bit_L: in BIT; -- Load Line #1 (bits 0 - 7)
Load_8Bit_H: in BIT; -- Load Line #2 (bits 8 - 15)
Load_16Bit: in BIT; -- Load Line #3 (bits 0 - 15)
Select_8Bit_L: in BIT; -- Select Line #1 (bits 0 - 7)
Select_8Bit_H: in BIT; -- Select Line #2 (bits 8 - 15)
Select_16Bit: in BIT; -- Select Line #3 (bits 0 - 15)
Input_8Bit_L: in BIT_VECTOR(7 downto 0); -- 8-bit input value (bits 0 - 7)
Input_8Bit_H: in BIT_VECTOR(7 downto 0); -- 8-bit input value (bits 8 - 15)
Input_16Bit: in BIT_VECTOR(15 downto 0); -- 16-bit input value (bits 0 - 15)
Output_8Bit_L: out BIT_VECTOR(7 downto 0); -- 8-bit output value (bits 0 - 7)
Output_8Bit_H: out BIT_VECTOR(7 downto 0); -- 8-bit output value (bits 8 - 15)
Output_16Bit: out BIT_VECTOR(15 downto 0); -- 16-bit output value (bits 0 - 15)
State_8Bit_L: out BIT_VECTOR(7 downto 0); -- Current state of the Flip Flop (bits 0 - 7)
State_8Bit_H: out BIT_VECTOR(7 downto 0); -- Current state of the Flip Flop (bits 8 - 15)
State_16Bit: out BIT_VECTOR(15 downto 0) -- Current state of the Flip Flop (bits 0 - 15)
);
end component RegisterExtended16Bit;
component Increment8Bit is
Port
(
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Cin : in BIT; -- Carry-in flag
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
Cout : out BIT -- Carry-out flag
);
end component Increment8Bit;
component Increment16Bit is
Port
(
Input : in BIT_VECTOR(15 downto 0); -- 16-bit input value
Cin : in BIT; -- Carry-in flag
Output : out BIT_VECTOR(15 downto 0); -- 16-bit output value
Cout : out BIT -- Carry-out flag
);
end component Increment16Bit;
component InstructionDecoder is
port
(
TimingSignals : in BIT_VECTOR(7 downto 0); -- The 8 different timing states
Instruction : in BIT_VECTOR(7 downto 0); -- The instruction to execute
Flags : in BIT_VECTOR(7 downto 0); -- Content of the FLAGS register - needed for conditional jumps
-- ==============================================================
-- The various control lines of the CPU which go low/high
-- depending on the timing state and the instruction to execute:
-- ==============================================================
Load_PC : out BIT;
Select_PC : out BIT;
Load_SRAM: out BIT;
Select_SRAM: out BIT;
Return_SRAM: out BIT;
Load_INC: out BIT;
Select_INC: out BIT;
Load_INSTR: out BIT;
Select_INSTR_To_DataBus: out BIT;
Select_INSTR_To_ALU: out BIT;
Load_A_From_DataBus: out BIT;
Select_A_To_ALU: out BIT;
Load_B_From_DataBus: out BIT;
Select_B_To_ALU: out BIT;
Load_C_From_DataBus: out BIT;
Load_InternalA_From_DataBus: out BIT;
Select_InternalA_To_DataBus: out BIT;
Load_Flags: out BIT;
Select_A_To_DataBus: out BIT;
Select_B_To_DataBus: out BIT;
Select_C_To_DataBus: out BIT;
Load_D_From_DataBus: out BIT;
Select_D_To_DataBus: out BIT;
Load_E_From_DataBus: out BIT;
Select_E_To_DataBus: out BIT;
Load_F_From_DataBus: out BIT;
Select_F_To_DataBus: out BIT;
Load_G_From_DataBus: out BIT;
Select_G_To_DataBus: out BIT;
Load_H_From_DataBus: out BIT;
Select_H_To_DataBus: out BIT;
load_M_From_AddressBus: out BIT;
select_M_To_AddressBus: out BIT;
load_XL_From_DataBus: out BIT;
load_XH_From_DataBus: out BIT;
load_X_From_AddressBus: out BIT;
select_XL_To_DataBus: out BIT;
select_XH_To_DataBus: out BIT;
select_X_To_AddressBus: out BIT;
Load_J_From_AddressBus: out BIT;
Select_J_To_AddressBus: out BIT;
Load_SP_From_AddressBus: out BIT;
Select_SP_To_AddressBus: out BIT;
Load_BP_From_AddressBus: out BIT;
Select_BP_To_AddressBus: out BIT;
Load_Y_From_AddressBus: out BIT;
Select_Y_To_AddressBus: out BIT;
Load_Z_From_AddressBus: out BIT;
Select_Z_To_AddressBus: out BIT;
Load_Adder16Bit_InputA: out BIT;
Select_Adder16Bit_InputA: out BIT;
Load_Adder16Bit_InputB: out BIT;
Select_Adder16Bit_InputB: out BIT;
Load_Adder16Bit_OutputC: out BIT;
Select_Adder16Bit_OutputC: out BIT;
load_FlagsSaved_From_FlagsRegister: out BIT;
load_FlagsSaved_To_FlagsRegister: out BIT;
Load_FlagsFromDataBus: out BIT;
Select_FlagsToFlagsBus: out BIT;
Load_FlagsFromFlagsBus: out BIT;
Select_FlagsToDataBus: out BIT;
Select_Flags: out BIT;
Select_PortA_To_DataBus: out BIT;
Select_PortB_To_DataBus: out BIT;
Load_PortC_From_DataBus: out BIT;
Load_PortD_From_DataBus: out BIT;
StopCPU: out BIT
);
end component InstructionDecoder;
component ALU8Bit is
Port
(
InputA : in BIT_VECTOR(7 downto 0); -- 1st 8-bit input value
InputB : in BIT_VECTOR(7 downto 0); -- 2nd 8-bit input value
FunctionCode: in BIT_VECTOR(3 downto 0); -- 4-bit function code
CarryIn: in BIT; -- Carry-Bit
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
Sign : out BIT; -- Do we have a negative number?
Zero : out BIT; -- Do we have a zero value?
Carry : out BIT; -- Do we have a carry?
Overflow: out BIT -- Do we have an overflow?
);
end component ALU8Bit;
component RippleCarryAdder16Bit is
Port
(
InputA : in BIT_VECTOR(15 downto 0); -- 1st 8-bit input value
InputB : in BIT_VECTOR(15 downto 0); -- 2nd 8-bit input value
Cin : in BIT; -- Carry-in flag
Output : out BIT_VECTOR(15 downto 0); -- 8-bit output value
Cout : out BIT -- Carry-out flag
);
end component RippleCarryAdder16Bit;
-- 4-bit binary counter & Control Lines
signal CounterOutput : STD_LOGIC_VECTOR(3 downto 0);
signal CounterOutputBitVector : BIT_VECTOR(3 downto 0);
signal TimingSignals : BIT_VECTOR(7 downto 0);
-- Signals needed for the RAM memory cell
signal loadRAM: BIT;
signal selectRAM: BIT;
signal returnRAM: BIT;
signal addressRAM: BIT_VECTOR(15 downto 0);
signal inputRAM: BIT_VECTOR(7 downto 0);
signal outputRAM: BIT_VECTOR(7 downto 0);
-- Signals needed for register "A"
signal load_A_From_DataBus : BIT; -- Load Line
signal select_A_To_DataBus : BIT; -- Select Line to Data Bus
signal select_A_To_ALU : BIT; -- Select Line to ALU
signal in_A_From_DataBus : BIT_VECTOR(7 downto 0); -- Input Data
signal out_A_To_DataBus : BIT_VECTOR(7 downto 0); -- Output Data
signal out_A_To_ALU : BIT_VECTOR(7 downto 0); -- Output Data
-- Signals needed for register "B"
signal load_B_From_DataBus : BIT; -- Load Line
signal select_B_To_DataBus : BIT; -- Select Line to Data Bus
signal select_B_To_ALU : BIT; -- Select Line to ALU
signal in_B_From_DataBus : BIT_VECTOR(7 downto 0); -- Input Data
signal out_B_To_DataBus : BIT_VECTOR(7 downto 0); -- Output Data
signal out_B_To_ALU : BIT_VECTOR(7 downto 0); -- Output Data
-- Signals needed for register "C"
signal load_C_From_DataBus : BIT; -- Load Line
signal select_C_To_DataBus : BIT; -- Select Line
signal in_C_From_DataBus : BIT_VECTOR(7 downto 0); -- Input Data
signal out_C_To_DataBus : BIT_VECTOR(7 downto 0); -- Output Data
-- Signals needed for register "D"
signal load_D_From_DataBus : BIT; -- Load Line
signal select_D_To_DataBus : BIT; -- Select Line
signal in_D_From_DataBus : BIT_VECTOR(7 downto 0); -- Input Data
signal out_D_To_DataBus : BIT_VECTOR(7 downto 0); -- Output Data
-- Signals needed for register "E"
signal load_E_From_DataBus : BIT; -- Load Line
signal select_E_To_DataBus : BIT; -- Select Line
signal in_E_From_DataBus : BIT_VECTOR(7 downto 0); -- Input Data
signal out_E_To_DataBus : BIT_VECTOR(7 downto 0); -- Output Data
-- Signals needed for register "F"
signal load_F_From_DataBus : BIT; -- Load Line
signal select_F_To_DataBus : BIT; -- Select Line
signal in_F_From_DataBus : BIT_VECTOR(7 downto 0); -- Input Data
signal out_F_To_DataBus : BIT_VECTOR(7 downto 0); -- Output Data
-- Signals needed for register "G"
signal load_G_From_DataBus : BIT; -- Load Line
signal select_G_To_DataBus : BIT; -- Select Line
signal in_G_From_DataBus : BIT_VECTOR(7 downto 0); -- Input Data
signal out_G_To_DataBus : BIT_VECTOR(7 downto 0); -- Output Data
-- Signals needed for register "H"
signal load_H_From_DataBus : BIT; -- Load Line
signal select_H_To_DataBus : BIT; -- Select Line
signal in_H_From_DataBus : BIT_VECTOR(7 downto 0); -- Input Data
signal out_H_To_DataBus : BIT_VECTOR(7 downto 0); -- Output Data
-- Signals needed for register "Flags"
signal load_Flags : BIT; -- Load Line
signal select_Flags : BIT; -- Select Line
signal in_Flags_From_ALU : BIT_VECTOR(7 downto 0); -- Input Data
signal out_Flags : BIT_VECTOR(7 downto 0); -- Output Data
signal in_Flags : BIT_VECTOR(7 downto 0);
signal state_Flags: BIT_VECTOR(7 downto 0);
-- Signals needed for register "FlagsSaved"
signal load_FlagsSaved_From_FlagsBus: BIT;
signal select_FlagsSaved_To_FlagsBus: BIT;
signal out_FlagsSaved_To_FlagsBus: BIT_VECTOR(7 downto 0);
signal in_FlagsSaved_From_FlagsBus : BIT_VECTOR(7 downto 0);
-- Signals needed for register "FlagsInBuffer"
signal load_FlagsFromDataBus: BIT;
signal select_FlagsToFlagsBus: BIT;
signal in_FlagsFromDataBus: BIT_VECTOR(7 downto 0);
signal out_FlagsToFlagsBus: BIT_VECTOR(7 downto 0);
-- Signals needed for register "FlagsOutBuffer"
signal load_FlagsFromFlagsBus: BIT;
signal select_FlagsToDataBus: BIT;
signal in_FlagsFromFlagsBus: BIT_VECTOR(7 downto 0);
signal out_FlagsToDataBus: BIT_VECTOR(7 downto 0);
-- Signals needed for register "Internal A"
signal load_InternalA_From_DataBus : BIT; -- Load Line
signal select_InternalA_To_DataBus : BIT; -- Select Line
signal in_InternalA_From_DataBus : BIT_VECTOR(7 downto 0); -- Input Data
signal out_InternalA : BIT_VECTOR(7 downto 0); -- Output Data
-- Signals needed for register "Program Counter"
signal l_PC : BIT; -- Load Line
signal select_PC : BIT; -- Select Line
signal in_PC : BIT_VECTOR(15 downto 0); -- Input Data
signal out_PC : BIT_VECTOR(15 downto 0); -- Output Data
-- Signals needed for register "Increment Program Counter"
signal load_INC : BIT; -- Load Line
signal select_INC : BIT; -- Select Line
signal in_INC : BIT_VECTOR(15 downto 0); -- Input Data
signal out_INC : BIT_VECTOR(15 downto 0); -- Output Data
-- Signals needed for 16-bit register "M"
signal load_M_From_AddressBus: BIT;
signal select_M_To_AddressBus: BIT;
signal in_M_From_AddressBus: BIT_VECTOR(15 downto 0);
signal out_M_To_AddressBus: BIT_VECTOR(15 downto 0);
-- Signals needed for 16-bit register "X"
signal load_XL_From_DataBus: BIT;
signal load_XH_From_DataBus: BIT;
signal load_X_From_AddressBus: BIT;
signal select_XL_To_DataBus: BIT;
signal select_XH_To_DataBus: BIT;
signal select_X_To_AddressBus: BIT;
signal in_XL_From_DataBus: BIT_VECTOR(7 downto 0);
signal in_XH_From_DataBus: BIT_VECTOR(7 downto 0);
signal in_X_From_AddressBus: BIT_VECTOR(15 downto 0);
signal out_XL_To_DataBus: BIT_VECTOR(7 downto 0);
signal out_XH_To_DataBus: BIT_VECTOR(7 downto 0);
signal out_X_To_AddressBus: BIT_VECTOR(15 downto 0);
-- Signals needed for register "J"
signal load_J_From_AddressBus: BIT;
signal select_J_To_AddressBus: BIT;
signal in_J_From_AddressBus: BIT_VECTOR(15 downto 0);
signal out_J_To_AddressBus: BIT_VECTOR(15 downto 0);
-- Signals needed for register "SP"
signal load_SP_From_AddressBus: BIT;
signal select_SP_To_AddressBus: BIT;
signal in_SP_From_AddressBus: BIT_VECTOR(15 downto 0);
signal out_SP_To_AddressBus: BIT_VECTOR(15 downto 0);
-- Signals needed for register "BP"
signal load_BP_From_AddressBus: BIT;
signal select_BP_To_AddressBus: BIT;
signal in_BP_From_AddressBus: BIT_VECTOR(15 downto 0);
signal out_BP_To_AddressBus: BIT_VECTOR(15 downto 0);
-- Signals needed for register "Y"
signal load_Y_From_AddressBus: BIT;
signal select_Y_To_AddressBus: BIT;
signal in_Y_From_AddressBus: BIT_VECTOR(15 downto 0);
signal out_Y_To_AddressBus: BIT_VECTOR(15 downto 0);
-- Signals needed for register "Z"
signal load_Z_From_AddressBus: BIT;
signal select_Z_To_AddressBus: BIT;
signal in_Z_From_AddressBus: BIT_VECTOR(15 downto 0);
signal out_Z_To_AddressBus: BIT_VECTOR(15 downto 0);
-- Signals needed for the register "Instruction"
signal load_INSTR : BIT; -- Load Line
signal select_INSTR_To_DataBus : BIT; -- Select Line to Data Bus
signal select_INSTR_To_ALU: BIT; -- Select Line to ALU
signal in_INSTR : BIT_VECTOR(7 downto 0); -- Input Data
signal out_INSTR_To_DataBus : BIT_VECTOR(7 downto 0); -- Output Data to Data Bus
signal out_INSTR_To_ALU : BIT_VECTOR(7 downto 0); -- Output Data to ALU
signal currentInstruction : BIT_VECTOR(7 downto 0); -- The current instruction to be processed
-- Signals needed for the 16-bit Ripple Carry Adder
signal Output_Adder16Bit: BIT_VECTOR(15 downto 0); -- 16-bit output value for the 16-bit adder
-- Signals needed for the register "Adder16Bit_OutputC"
signal load_Adder16Bit_OutputC: BIT;
signal select_Adder16Bit_OutputC: BIT;
signal Output_RegisterAdder16Bit: BIT_VECTOR(15 downto 0);
-- Signals needed for the register "Adder16Bit_InputA"
signal load_Adder16Bit_InputA: BIT;
signal select_Adder16Bit_InputA: BIT;
signal in_Adder16Bit_InputA_From_AddressBus: BIT_VECTOR(15 downto 0);
signal out_Adder16Bit_InputA: BIT_VECTOR(15 downto 0);
-- Signals needed for the register "Adder16Bit_InputB"
signal load_Adder16Bit_InputB: BIT;
signal select_Adder16Bit_InputB: BIT;
signal in_Adder16Bit_InputB_From_AddressBus: BIT_VECTOR(15 downto 0);
signal out_Adder16Bit_InputB: BIT_VECTOR(15 downto 0);
-- Signals needed for Input Port "A"
signal select_PortA_To_DataBus: BIT;
signal out_PortA_To_DataBus: BIT_VECTOR(7 downto 0);
-- Signals needed for Output Port "C"
signal load_PortC_From_DataBus: BIT;
signal in_PortC_FromDataBus: BIT_VECTOR(7 downto 0);
-- Signals needed for Output Port "D"
signal load_PortD_From_DataBus: BIT;
signal in_PortD_FromDataBus: BIT_VECTOR(7 downto 0);
-- Signals needed for Input Port "B"
signal select_PortB_To_DataBus: BIT;
signal out_PortB_To_DataBus: BIT_VECTOR(7 downto 0);
-- 16-bit Address Bus
signal AddressBus : BIT_VECTOR(15 downto 0);
-- 8-bit Data Bus
signal DataBus : BIT_VECTOR(7 downto 0);
-- 8-bit Flags Bus
signal FlagsBus : BIT_VECTOR(7 downto 0);
signal FlagsTemp: BIT_VECTOR(7 downto 0);
-- Incrementer for Program Counter
signal CarryOutIncrementer : BIT;
-- Signals needed to connect the TestBench to the CPU
signal load_SRAM : BIT;
signal select_SRAM : BIT;
signal load_PC1 : BIT;
-- ALU output flags
signal ALU_Sign: BIT := '0';
signal ALU_Zero: BIT := '0';
signal ALU_Carry: BIT := '0';
signal out_ALU: BIT_VECTOR(7 downto 0);
signal stopped: BIT := '0';
-- This line stores the first 5 bits from the Register "Internal A"
signal Truncated_InternalA : BIT_VECTOR(7 downto 0);
begin
-- =============================================================
-- The following section contains the definition of the various
-- components of the CPU
-- =============================================================
-- That's the 4-bit binary counter
Counter: Counter4Bit port map (Clock, Reset, CounterOutput);
CounterOutputBitVector <= TO_BITVECTOR(CounterOutput);
-- The decoder generates the signals along the 8 control lines out from the 4-bit binary counter
Decoder: Decoder3to8 port map(CounterOutputBitVector(2 downto 0), TimingSignals, Start and not stopped);
-- This is our main-memory - 64K
ram: RAM_Wrapper port map(Clock, loadRAM, selectRAM, returnRAM, addressRAM, inputRAM, OutputRAM);
-- Connects the address bus to the SRAM address input
addressRAM <= AddressBus or
Address_RAM;
-- The Instruction Decoder - the brain within the brain.
-- Based on the timing signal and the current instruction the
-- various CPU control lines are going high/low.
instrDecoder: InstructionDecoder port map(TimingSignals,
currentInstruction,
out_Flags,
load_PC1,
select_PC,
load_SRAM,
select_SRAM,
returnRAM,
load_INC,
select_INC,
load_INSTR,
select_INSTR_To_DataBus,
select_INSTR_To_ALU,
load_A_From_DataBus,
select_A_To_ALU,
load_B_From_DataBus,
select_B_To_ALU,
load_C_From_DataBus,
load_InternalA_From_DataBus,
select_InternalA_To_DataBus,
load_Flags,
select_A_To_DataBus,
select_B_To_DataBus,
select_C_To_DataBus,
load_D_From_DataBus,
select_D_To_DataBus,
load_E_From_DataBus,
select_E_To_DataBus,
load_F_From_DataBus,
select_F_To_DataBus,
load_G_From_DataBus,
select_G_To_DataBus,
load_H_From_DataBus,
select_H_To_DataBus,
load_M_From_AddressBus,
select_M_To_AddressBus,
load_XL_From_DataBus,
load_XH_From_DataBus,
load_X_From_AddressBus,
select_XL_To_DataBus,
select_XH_To_DataBus,
select_X_To_AddressBus,
load_J_From_AddressBus,
select_J_To_AddressBus,
load_SP_From_AddressBus,
select_SP_To_AddressBus,
load_BP_From_AddressBus,
select_BP_To_AddressBus,
load_Y_From_AddressBus,
select_Y_To_AddressBus,
load_Z_From_AddressBus,
select_Z_To_AddressBus,
load_Adder16Bit_InputA,
select_Adder16Bit_InputA,
load_Adder16Bit_InputB,
select_Adder16Bit_InputB,
load_Adder16Bit_OutputC,
select_Adder16Bit_OutputC,
load_FlagsSaved_From_FlagsBus,
select_FlagsSaved_To_FlagsBus,
load_FlagsFromDataBus,
select_FlagsToFlagsBus,
load_FlagsFromFlagsBus,
select_FlagsToDataBus,
select_Flags,
select_PortA_To_DataBus,
select_PortB_To_DataBus,
load_PortC_From_DataBus,
load_PortD_From_DataBus,
stopped);
-- 16-bit Register Definitions
rPC: Register16Bit port map(l_PC, select_PC, in_PC, out_PC); -- Register "Program Counter" (PC)
rINC: Register16Bit port map(load_INC, select_INC, in_INC, out_INC); -- Register "Program Counter Increment" (INC)
rJ: Register16Bit port map(load_J_From_AddressBus, select_J_To_AddressBus, in_J_From_AddressBus, out_J_To_AddressBus); -- Register "Jump" - stores the JMP target address
rM: Register16Bit port map(load_M_From_AddressBus, select_M_To_AddressBus, in_M_From_AddressBus, out_M_To_AddressBus); -- Register "M"
rSP: Register16Bit port map(load_SP_From_AddressBus, select_SP_To_AddressBus, in_SP_From_AddressBus, out_SP_To_AddressBus); -- Register "SP"
rBP: Register16Bit port map(load_BP_From_AddressBus, select_BP_To_AddressBus, in_BP_From_AddressBus, out_BP_To_AddressBus); -- Register "BP"
rY: Register16Bit port map(load_Y_From_AddressBus, select_Y_To_AddressBus, in_Y_From_AddressBus, out_Y_To_AddressBus); -- Register "Y"
rZ: Register16Bit port map(load_Z_From_AddressBus, select_Z_To_AddressBus, in_Z_From_AddressBus, out_Z_To_AddressBus); -- Register "Z"
-- 16-bit Ripple Carry Adder
adder16Bit: RippleCarryAdder16Bit port map(out_Adder16Bit_InputA, out_Adder16Bit_InputB, '0', Output_Adder16Bit);
rAdder16Bit_InputA: Register16Bit port map(load_Adder16Bit_InputA, select_Adder16Bit_InputA, in_Adder16Bit_InputA_From_AddressBus, out_Adder16Bit_InputA);
rAdder16Bit_InputB: Register16Bit port map(load_Adder16Bit_InputB, select_Adder16Bit_InputB, in_Adder16Bit_InputB_From_AddressBus, out_Adder16Bit_InputB);
rAdder16Bit_OutputC: Register16Bit port map(load_Adder16Bit_OutputC, select_Adder16Bit_OutputC, Output_Adder16Bit, Output_RegisterAdder16Bit);
-- Incrementer for Program Counter
-- It takes the input from the AddressBus and writes
-- the output into the input of the INC register (=> in_INC)
inc: Increment16Bit port map(AddressBus, '0', in_INC, CarryOutIncrementer);
-- 8-bit Instruction Register
rINSTR: Register8Bit2WayOutput port map(load_INSTR, select_INSTR_To_DataBus, select_INSTR_To_ALU, in_INSTR, out_INSTR_To_DataBus, out_INSTR_To_ALU, currentInstruction);
-- Internal ALU registers
rA: Register8Bit2WayOutput port map(load_A_From_DataBus, select_A_To_DataBus, select_A_To_ALU, in_A_From_DataBus, out_A_To_DataBus, out_A_To_ALU); -- Register "A": Input to ALU
rB: Register8Bit2WayOutput port map(load_B_From_DataBus, select_B_To_DataBus, select_B_To_ALU, in_B_From_DataBus, out_B_To_DataBus, out_B_To_ALU); -- Register "B": Input to ALU
rC: Register8Bit port map(load_C_From_DataBus, select_C_To_DataBus, in_C_From_DataBus, out_C_To_DataBus); -- Register "C": Output from ALU
rInternalA: Register8Bit port map(load_InternalA_From_DataBus, select_InternalA_To_DataBus, in_InternalA_From_DataBus, out_InternalA); -- Register "Internal A" for ALU
-- General purpose 8-bit Register Definitions
rD: Register8Bit port map(load_D_From_DataBus, select_D_To_DataBus, in_D_From_DataBus, out_D_To_DataBus); -- Register "D"
rE: Register8Bit port map(load_E_From_DataBus, select_E_To_DataBus, in_E_From_DataBus, out_E_To_DataBus); -- Register "E"
rF: Register8Bit port map(load_F_From_DataBus, select_F_To_DataBus, in_F_From_DataBus, out_F_To_DataBus); -- Register "F"
rG: Register8Bit port map(load_G_From_DataBus, select_G_To_DataBus, in_G_From_DataBus, out_G_To_DataBus); -- Register "G"
rH: Register8Bit port map(load_H_From_DataBus, select_H_To_DataBus, in_H_From_DataBus, out_H_To_DataBus); -- Register "H"
-- 16-bit Extended Register "X"
-- Consists of the 2 internal 8-bit wide registers "XL" and "XH"
rX: RegisterExtended16Bit port map(load_XL_From_DataBus,
load_XH_From_DataBus,
load_X_From_AddressBus,
select_XL_To_DataBus,
select_XH_To_DataBus,
select_X_To_AddressBus,
in_XL_From_DataBus,
in_XH_From_DataBus,
in_X_From_AddressBus,
out_XL_To_DataBus,
out_XH_To_DataBus,
out_X_To_AddressBus);
-- Input/Output Ports
pA: Register8Bit port map('1', select_PortA_To_DataBus, InputPort_A, out_PortA_To_DataBus); -- Input Port "A"
pB: Register8Bit port map('1', select_PortB_To_DataBus, InputPort_B, out_PortB_To_DataBus); -- Input Port "B"
p_outC: Register8Bit port map(load_PortC_From_DataBus, '1', in_PortC_FromDataBus, OutputPort_C); -- Output Port "C"
p_outD: Register8Bit port map(load_PortD_From_DataBus, '1', in_PortD_FromDataBus, OutputPort_D); -- Output Port "D"
-- Flags related registers
rFlags : Register8Bit port map(load_Flags, select_Flags, in_Flags, out_Flags);
rFlagsSaved : Register8Bit port map(load_FlagsSaved_From_FlagsBus, select_FlagsSaved_To_FlagsBus, in_FlagsSaved_From_FlagsBus, out_FlagsSaved_To_FlagsBus, state_Flags); -- Stores a copy of the Flags register so that we can perform ALU operations without affecting the original content of the Flags register
rFlagsInBuffer : Register8Bit port map(load_FlagsFromDataBus, select_FlagsToFlagsBus, in_FlagsFromDataBus, out_FlagsToFlagsBus); -- Buffers the flags when read from the data bus (needed for the POPF operation)
rFlagsOutBuffer : Register8Bit port map(load_FlagsFromFlagsBus, select_FlagsToDataBus, in_FlagsFromFlagsBus, out_FlagsToDataBus); -- Buffers the flags when written to the data bus (needed for the PUSHF operation)
-- This is our ALU
-- The ALU receives the input from Register A and Register B.
-- The output is written to Register C for further processing.
-- state_Flags(2)
alu: ALU8Bit port map(out_A_To_ALU, out_B_To_ALU, out_INSTR_To_ALU(3 downto 0), state_Flags(2), out_ALU, in_Flags_From_ALU(0), in_Flags_From_ALU(1), in_Flags_From_ALU(2), in_Flags_From_ALU(3));
FlagsTemp(0) <= in_Flags_From_ALU(0);
FlagsTemp(1) <= in_Flags_From_ALU(1);
FlagsTemp(2) <= in_Flags_From_ALU(2);
FlagsTemp(3) <= in_Flags_From_ALU(3);
-- Writes the flags onto the Flags Bus
FlagsBus <= FlagsTemp or
out_Flags or
out_FlagsSaved_To_FlagsBus or
out_FlagsToFlagsBus;
-- Writes the content from the Flags Bus into the Flags register
in_Flags <= FlagsBus;
-- Writes the content from the Flags Bus into the FlagsSaved register
in_FlagsSaved_From_FlagsBus <= FlagsBus;
in_FlagsFromFlagsBus <= FlagsBus;
-- =======================================================================
-- The following section contains the wiring of the individual registers
-- with the Address and Data Bus
-- =======================================================================
-- Connects the Address Bus to the Program Counter register
in_PC <= AddressBus or PC;
-- Connects the 16-bit wide registers to the Address Bus
in_M_From_AddressBus <= AddressBus;
in_X_From_AddressBus <= AddressBus;
in_J_From_AddressBus <= AddressBus;
in_SP_From_AddressBus <= AddressBus;
in_BP_From_AddressBus <= AddressBus;
in_Y_From_AddressBus <= AddressBus;
in_Z_From_AddressBus <= AddressBus;
in_Adder16Bit_InputA_From_AddressBus <= AddressBus;
in_Adder16Bit_InputB_From_AddressBus <= AddressBus;
-- Connects the Program Counter register, the Increment register, and the 16-bit registers to the Address Bus
AddressBus <= out_PC or
out_INC or
out_M_To_AddressBus or
out_X_To_AddressBus or
out_J_To_AddressBus or
out_SP_To_AddressBus or
out_BP_To_AddressBus or
out_Y_To_AddressBus or
out_Z_To_AddressBus or
Output_RegisterAdder16Bit;
-- Connects the general purpose registers and the instruction
-- register to the data bus
in_A_From_DataBus <= DataBus;
in_B_From_DataBus <= DataBus;
in_C_From_DataBus <= DataBus;
in_D_From_DataBus <= DataBus;
in_E_From_DataBus <= DataBus;
in_F_From_DataBus <= DataBus;
in_G_From_DataBus <= DataBus;
in_H_From_DataBus <= DataBus;
in_InternalA_From_DataBus <= DataBus;
in_INSTR <= DataBus;
in_XL_From_DataBus <= DataBus;
in_XH_From_DataBus <= DataBus;
in_FlagsFromDataBus <= DataBus;
in_PortC_FromDataBus <= DataBus;
in_PortD_FromDataBus <= DataBus;
-- Just store the first 4 bits from the Register D.
-- This eliminates the 4 bits from SETAB opcode and the destination register (A or B)
Truncated_InternalA <= out_InternalA and "00001111";
-- Connects the data bus to the general purpose registers, and the
-- SRAM memory output.
-- !!!!IT'S VERY IMPORTANT THAT ONLY *ONE* REGISTER CONCURRENTLY WRITES
-- TO THE DATA BUS!!!!
DataBus <= out_A_To_DataBus or
out_B_To_DataBus or
out_C_To_DataBus or
out_INSTR_To_DataBus or
outputRAM or
Truncated_InternalA or
out_ALU or
out_D_To_DataBus or
out_E_To_DataBus or
out_F_To_DataBus or
out_G_To_DataBus or
out_H_To_DataBus or
out_XL_To_DataBus or
out_XH_To_DataBus or
out_FlagsToDataBus or
out_PortA_To_DataBus or
out_PortB_To_DataBus;
-- =======================================================================
-- The following section contains a few additional connections
-- that are needed to connect the TestBench to the CPU itself.
-- These are the Control Lines that also accept inputs from the TestBench.
-- They just take their input from the Instruction Decoder and ORed with the
-- input from the TestBench.
-- ========================================================================
loadRAM <= load_SRAM or Load_RAM;
inputRAM <= Input_RAM or DataBus;
l_PC <= load_PC1 or Load_PC;
selectRAM <= select_SRAM or Select_RAM;
-- Just provide from the CPU an output value, so that the implementation on the FPGA works
Instruction <= currentInstruction;
end Behavioral;
|
mit
|
7661d58f7d45555ba06de3b7482d98ab
| 0.540118 | 4.195664 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_iic_0_0/sim/system_axi_iic_0_0.vhd
| 1 | 9,254 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_iic:2.0
-- IP Revision: 14
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_iic_v2_0_14;
USE axi_iic_v2_0_14.axi_iic;
ENTITY system_axi_iic_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
iic2intc_irpt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
sda_i : IN STD_LOGIC;
sda_o : OUT STD_LOGIC;
sda_t : OUT STD_LOGIC;
scl_i : IN STD_LOGIC;
scl_o : OUT STD_LOGIC;
scl_t : OUT STD_LOGIC;
gpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_axi_iic_0_0;
ARCHITECTURE system_axi_iic_0_0_arch OF system_axi_iic_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_iic_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_iic IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_IIC_FREQ : INTEGER;
C_TEN_BIT_ADR : INTEGER;
C_GPO_WIDTH : INTEGER;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_SCL_INERTIAL_DELAY : INTEGER;
C_SDA_INERTIAL_DELAY : INTEGER;
C_SDA_LEVEL : INTEGER;
C_SMBUS_PMBUS_HOST : INTEGER;
C_DEFAULT_VALUE : STD_LOGIC_VECTOR(7 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
iic2intc_irpt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
sda_i : IN STD_LOGIC;
sda_o : OUT STD_LOGIC;
sda_t : OUT STD_LOGIC;
scl_i : IN STD_LOGIC;
scl_o : OUT STD_LOGIC;
scl_t : OUT STD_LOGIC;
gpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT axi_iic;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF iic2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF sda_i: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_I";
ATTRIBUTE X_INTERFACE_INFO OF sda_o: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_O";
ATTRIBUTE X_INTERFACE_INFO OF sda_t: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_T";
ATTRIBUTE X_INTERFACE_INFO OF scl_i: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_I";
ATTRIBUTE X_INTERFACE_INFO OF scl_o: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_O";
ATTRIBUTE X_INTERFACE_INFO OF scl_t: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_T";
BEGIN
U0 : axi_iic
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_IIC_FREQ => 100000,
C_TEN_BIT_ADR => 0,
C_GPO_WIDTH => 1,
C_S_AXI_ACLK_FREQ_HZ => 100000000,
C_SCL_INERTIAL_DELAY => 0,
C_SDA_INERTIAL_DELAY => 0,
C_SDA_LEVEL => 1,
C_SMBUS_PMBUS_HOST => 0,
C_DEFAULT_VALUE => X"00"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
iic2intc_irpt => iic2intc_irpt,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
sda_i => sda_i,
sda_o => sda_o,
sda_t => sda_t,
scl_i => scl_i,
scl_o => scl_o,
scl_t => scl_t,
gpo => gpo
);
END system_axi_iic_0_0_arch;
|
apache-2.0
|
1db9a380a7be530bccbc8b8ca51c0873
| 0.678085 | 3.223267 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_ethernetlite_0_0/synth/system_axi_ethernetlite_0_0.vhd
| 1 | 13,311 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_ethernetlite:3.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_axi_ethernetlite_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
phy_tx_clk : IN STD_LOGIC;
phy_rx_clk : IN STD_LOGIC;
phy_crs : IN STD_LOGIC;
phy_dv : IN STD_LOGIC;
phy_rx_data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_col : IN STD_LOGIC;
phy_rx_er : IN STD_LOGIC;
phy_rst_n : OUT STD_LOGIC;
phy_tx_en : OUT STD_LOGIC;
phy_tx_data : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_mdio_i : IN STD_LOGIC;
phy_mdio_o : OUT STD_LOGIC;
phy_mdio_t : OUT STD_LOGIC;
phy_mdc : OUT STD_LOGIC
);
END system_axi_ethernetlite_0_0;
ARCHITECTURE system_axi_ethernetlite_0_0_arch OF system_axi_ethernetlite_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_ethernetlite_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_ethernetlite IS
GENERIC (
C_FAMILY : STRING;
C_SELECT_XPM : INTEGER;
C_INSTANCE : STRING;
C_S_AXI_ACLK_PERIOD_PS : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_INCLUDE_MDIO : INTEGER;
C_INCLUDE_INTERNAL_LOOPBACK : INTEGER;
C_INCLUDE_GLOBAL_BUFFERS : INTEGER;
C_DUPLEX : INTEGER;
C_TX_PING_PONG : INTEGER;
C_RX_PING_PONG : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
phy_tx_clk : IN STD_LOGIC;
phy_rx_clk : IN STD_LOGIC;
phy_crs : IN STD_LOGIC;
phy_dv : IN STD_LOGIC;
phy_rx_data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_col : IN STD_LOGIC;
phy_rx_er : IN STD_LOGIC;
phy_rst_n : OUT STD_LOGIC;
phy_tx_en : OUT STD_LOGIC;
phy_tx_data : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_mdio_i : IN STD_LOGIC;
phy_mdio_o : OUT STD_LOGIC;
phy_mdio_t : OUT STD_LOGIC;
phy_mdc : OUT STD_LOGIC
);
END COMPONENT axi_ethernetlite;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_axi_ethernetlite_0_0_arch: ARCHITECTURE IS "axi_ethernetlite,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_axi_ethernetlite_0_0_arch : ARCHITECTURE IS "system_axi_ethernetlite_0_0,axi_ethernetlite,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_axi_ethernetlite_0_0_arch: ARCHITECTURE IS "system_axi_ethernetlite_0_0,axi_ethernetlite,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_ethernetlite,x_ipVersion=3.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_SELECT_XPM=1,C_INSTANCE=axi_ethernetlite_inst,C_S_AXI_ACLK_PERIOD_PS=10000,C_S_AXI_ADDR_WIDTH=13,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=1,C_S_AXI_PROTOCOL=AXI4LITE,C_INCLUDE_MDIO=1,C_INCLUDE_INTERNAL_LOOPBACK=0,C_INCLUDE_GLOBAL_BUFFERS=1,C_DUPLEX=1,C_TX_PING_PONG=1,C_RX_P" &
"ING_PONG=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF phy_tx_clk: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TX_CLK";
ATTRIBUTE X_INTERFACE_INFO OF phy_rx_clk: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_CLK";
ATTRIBUTE X_INTERFACE_INFO OF phy_crs: SIGNAL IS "xilinx.com:interface:mii:1.0 MII CRS";
ATTRIBUTE X_INTERFACE_INFO OF phy_dv: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_DV";
ATTRIBUTE X_INTERFACE_INFO OF phy_rx_data: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RXD";
ATTRIBUTE X_INTERFACE_INFO OF phy_col: SIGNAL IS "xilinx.com:interface:mii:1.0 MII COL";
ATTRIBUTE X_INTERFACE_INFO OF phy_rx_er: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_ER";
ATTRIBUTE X_INTERFACE_INFO OF phy_rst_n: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RST_N";
ATTRIBUTE X_INTERFACE_INFO OF phy_tx_en: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TX_EN";
ATTRIBUTE X_INTERFACE_INFO OF phy_tx_data: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TXD";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdio_i: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDIO_I";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdio_o: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDIO_O";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdio_t: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDIO_T";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdc: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDC";
BEGIN
U0 : axi_ethernetlite
GENERIC MAP (
C_FAMILY => "artix7",
C_SELECT_XPM => 1,
C_INSTANCE => "axi_ethernetlite_inst",
C_S_AXI_ACLK_PERIOD_PS => 10000,
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 1,
C_S_AXI_PROTOCOL => "AXI4LITE",
C_INCLUDE_MDIO => 1,
C_INCLUDE_INTERNAL_LOOPBACK => 0,
C_INCLUDE_GLOBAL_BUFFERS => 1,
C_DUPLEX => 1,
C_TX_PING_PONG => 1,
C_RX_PING_PONG => 1
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
ip2intc_irpt => ip2intc_irpt,
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => '1',
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => s_axi_araddr,
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
phy_tx_clk => phy_tx_clk,
phy_rx_clk => phy_rx_clk,
phy_crs => phy_crs,
phy_dv => phy_dv,
phy_rx_data => phy_rx_data,
phy_col => phy_col,
phy_rx_er => phy_rx_er,
phy_rst_n => phy_rst_n,
phy_tx_en => phy_tx_en,
phy_tx_data => phy_tx_data,
phy_mdio_i => phy_mdio_i,
phy_mdio_o => phy_mdio_o,
phy_mdio_t => phy_mdio_t,
phy_mdc => phy_mdc
);
END system_axi_ethernetlite_0_0_arch;
|
apache-2.0
|
a680d12f0c1c5a846838e1d35ab528a4
| 0.678537 | 3.143093 | false | false | false | false |
daniw/add
|
floppy/mcu/gpio.vhd
| 1 | 6,002 |
-------------------------------------------------------------------------------
-- Entity: ram
-- Author: Waj
-- Date : 11-May-13
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- GPIO block for simple von-Neumann MCU.
-------------------------------------------------------------------------------
-- Total # of FFs: ... tbd ...
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity gpio is
port(rst : in std_logic;
clk : in std_logic;
-- GPIO bus signals
bus_in : in t_bus2rws;
bus_out : out t_rws2bus;
-- LED, Switches and Buttons
to_LED : out std_logic_vector(7 downto 0);
from_SW : in std_logic_vector(3 downto 0);
from_BTN_ROT_C : in std_logic;
from_BTN_EAST : in std_logic;
from_BTN_WEST : in std_logic;
from_BTN_NORTH : in std_logic;
-- Floppy connection
step_to_floppy : out std_logic;
dir_to_floppy : out std_logic
en_to_floppy : out std_logic
);
end gpio;
architecture rtl of gpio is
component floppy is
port(
rst : in std_logic;
clk : in std_logic;
-- input signals from cpu
enable : in std_logic;
mode : in std_logic;
pitch_fix : in std_logic_vector(15 downto 0);
-- output signals to cpu
status_init : out std_logic;
status_melody : out std_logic;
-- output signals to floppy
floppy_step : out std_logic;
floppy_dir : out std_logic
floppy_en : out std_logic
);
end component floppy;
signal in_1, in_2 : std_logic_vector(7 downto 0);
signal next_out, current_out : std_logic_vector(7 downto 0);
signal f_status_init : std_logic;
signal f_status_melody : std_logic;
signal f_enable : std_logic;
signal f_mode : std_logic;
signal f_pitch_fix : std_logic_vector(15 downto 0);
begin
floppy1 : floppy
port map(
rst => rst,
clk => clk,
enable => f_enable,
mode => f_mode,
pitch_fix => f_pitch_fix,
status_init => f_status_init,
status_melody => f_status_melody,
floppy_step => step_to_floppy,
floppy_dir => dir_to_floppy,
floppy_en => en_to_floppy
);
-----------------------------------------------------------------------------
-- sequential process: DUMMY to avoid logic optimization
-- To be replaced.....
-- # of FFs: ......
-----------------------------------------------------------------------------
-- For testing only !!! inout without CPU
-- to_LED(7 downto 4) <= from_SW;
-- to_LED(3) <= from_BTN_ROT_C;
-- to_LED(2) <= from_BTN_EAST;
-- to_LED(1) <= from_BTN_WEST;
-- to_LED(7) <= from_BTN_NORTH;
P_synch : process(rst,clk) -- for synchronizing the inputs with 2 FFs
begin
if rst = '1' then
in_1 <= (others => '0');
in_2 <= (others => '0');
elsif rising_edge(clk) then
in_1(3 downto 0) <= from_SW;
in_1(4) <= from_BTN_EAST;
in_1(5) <= from_BTN_NORTH;
in_1(6) <= from_BTN_WEST;
in_1(7) <= from_BTN_ROT_C;
in_2 <= in_1;
end if;
end process;
-- Connecting the internal Signals
to_LED <= current_out;
current_out <= next_out;
P_busaccess : process(rst, clk)
begin
if rst = '1' then
bus_out.data <= (others => '0');
elsif rising_edge(clk) then
next_out <= current_out; -- take the same output if no new data avaiable
if unsigned(bus_in.addr) = to_unsigned(16#00#,AWL) then
bus_out.data(7 downto 0) <= in_2; -- Only the low byte is used !
bus_out.data(15 downto 8) <= (others => '0');
elsif unsigned(bus_in.addr) = to_unsigned(16#01#,AWL) then
bus_out.data(7 downto 0) <= current_out; -- Only the low byte is used !
bus_out.data(15 downto 8) <= (others => '0');
elsif unsigned(bus_in.addr) = to_unsigned(16#02#,AWL) then
bus_out.data(0) <= f_enable;
bus_out.data(15 downto 1) <= (others => '0');
elsif unsigned(bus_in.addr) = to_unsigned(16#03#,AWL) then
bus_out.data(0) <= f_mode;
bus_out.data(15 downto 1) <= (others => '0');
elsif unsigned(bus_in.addr) = to_unsigned(16#04#,AWL) then
bus_out.data(0) <= f_status_init;
bus_out.data(15 downto 1) <= (others => '0');
elsif unsigned(bus_in.addr) = to_unsigned(16#05#,AWL) then
bus_out.data(0) <= f_status_melody;
bus_out.data(15 downto 1) <= (others => '0');
elsif unsigned(bus_in.addr) = to_unsigned(16#06#,AWL) then
bus_out.data(15 downto 0) <= f_pitch_fix;
end if;
if bus_in.we = '1' then -- write to register
if unsigned(bus_in.addr) = to_unsigned(16#01#,AWL) then
next_out <= bus_in.data(7 downto 0);--<= "01010111";
elsif unsigned(bus_in.addr) = to_unsigned(16#02#,AWL) then
f_enable <= bus_in.data(0);
elsif unsigned(bus_in.addr) = to_unsigned(16#03#,AWL) then
f_mode <= bus_in.data(0);
elsif unsigned(bus_in.addr) = to_unsigned(16#06#,AWL) then
f_pitch_fix <= bus_in.data;
end if;
end if;
end if;
end process;
end rtl;
|
gpl-2.0
|
eb355584a4343301f9b561c5ff7f0bc4
| 0.459014 | 3.73491 | false | false | false | false |
KPU-RISC/KPU
|
VHDL/SHR8Bit.vhd
| 1 | 1,347 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07/17/2015 02:39:38 PM
-- Design Name:
-- Module Name: SHR8Bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SHR8Bit is
Port
(
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
Cout : out BIT -- Carry-out flag
);
end SHR8Bit;
architecture Behavioral of SHR8Bit is
begin
Cout <= Input(0);
Output(0) <= Input(1);
Output(1) <= Input(2);
Output(2) <= Input(3);
Output(3) <= Input(4);
Output(4) <= Input(5);
Output(5) <= Input(6);
Output(6) <= Input(7);
Output(7) <= '0';
end Behavioral;
|
mit
|
9d7bd4576d7e99eb78f8ebc4650fdc8e
| 0.547142 | 3.773109 | false | false | false | false |
KPU-RISC/KPU
|
VHDL/FlipFlop1Bit2WayOutput.vhd
| 1 | 1,748 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/24/2015 01:06:25 PM
-- Design Name:
-- Module Name: FlipFlop1Bit2WayOutput - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FlipFlop1Bit2WayOutput is
Port
(
Load : in BIT; -- Load Line
Sel1 : in BIT; -- Select Line #1
Sel2 : in BIT; -- Select Line #2
Input : in BIT; -- Input Data
Output1 : out BIT; -- Output Data #1
Output2 : out BIT; -- OUtput Data #2
State : out BIT -- Current state of the Flip Flop
);
end FlipFlop1Bit2WayOutput;
architecture Behavioral of FlipFlop1Bit2WayOutput is
signal Nand1 : BIT;
signal Nand2 : BIT;
signal Not1 : BIT;
signal F1 : BIT;
signal F2 : BIT;
begin
Nand1 <= not(Load and Input);
Not1 <= not Input;
Nand2 <= not(Not1 and Load);
F1 <= not (F2 and Nand1);
F2 <= not (Nand2 and F1) after 1 ns;
-- Return the internal state for debugging/monitoring purposes
State <= F1;
Output1 <= F1 and Sel1;
Output2 <= F1 and Sel2;
end Behavioral;
|
mit
|
c40cae0afda6924581b99f9f5de4827d
| 0.566362 | 3.893096 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_auto_cc_0/system_auto_cc_0_sim_netlist.vhdl
| 1 | 903,411 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:45:31 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_auto_cc_0/system_auto_cc_0_sim_netlist.vhdl
-- Design : system_auto_cc_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_dmem is
port (
dout_i : out STD_LOGIC_VECTOR ( 57 downto 0 );
s_aclk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
DI : in STD_LOGIC_VECTOR ( 57 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_dmem : entity is "dmem";
end system_auto_cc_0_dmem;
architecture STRUCTURE of system_auto_cc_0_dmem is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_0 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_1 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_2 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_3 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_4 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_5 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_0 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_1 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_2 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_3 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_4 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_5 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_0 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_1 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_2 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_3 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_4 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_5 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_0 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_1 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_2 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_3 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_4 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_5 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_0 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_1 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_2 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_3 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_4 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_5 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_0 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_1 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_2 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_3 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_4 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_5 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_0 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_1 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_2 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_3 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_4 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_5 : STD_LOGIC;
signal RAM_reg_0_15_54_57_n_0 : STD_LOGIC;
signal RAM_reg_0_15_54_57_n_1 : STD_LOGIC;
signal RAM_reg_0_15_54_57_n_2 : STD_LOGIC;
signal RAM_reg_0_15_54_57_n_3 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_0 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_1 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_2 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_3 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_4 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_5 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_54_57_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_54_57_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_12_17 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_18_23 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_24_29 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_30_35 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_36_41 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_42_47 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_48_53 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_54_57 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_6_11 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(1 downto 0),
DIB(1 downto 0) => DI(3 downto 2),
DIC(1 downto 0) => DI(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(13 downto 12),
DIB(1 downto 0) => DI(15 downto 14),
DIC(1 downto 0) => DI(17 downto 16),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_12_17_n_0,
DOA(0) => RAM_reg_0_15_12_17_n_1,
DOB(1) => RAM_reg_0_15_12_17_n_2,
DOB(0) => RAM_reg_0_15_12_17_n_3,
DOC(1) => RAM_reg_0_15_12_17_n_4,
DOC(0) => RAM_reg_0_15_12_17_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(19 downto 18),
DIB(1 downto 0) => DI(21 downto 20),
DIC(1 downto 0) => DI(23 downto 22),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_18_23_n_0,
DOA(0) => RAM_reg_0_15_18_23_n_1,
DOB(1) => RAM_reg_0_15_18_23_n_2,
DOB(0) => RAM_reg_0_15_18_23_n_3,
DOC(1) => RAM_reg_0_15_18_23_n_4,
DOC(0) => RAM_reg_0_15_18_23_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(25 downto 24),
DIB(1 downto 0) => DI(27 downto 26),
DIC(1 downto 0) => DI(29 downto 28),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_24_29_n_0,
DOA(0) => RAM_reg_0_15_24_29_n_1,
DOB(1) => RAM_reg_0_15_24_29_n_2,
DOB(0) => RAM_reg_0_15_24_29_n_3,
DOC(1) => RAM_reg_0_15_24_29_n_4,
DOC(0) => RAM_reg_0_15_24_29_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_30_35: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(31 downto 30),
DIB(1 downto 0) => DI(33 downto 32),
DIC(1 downto 0) => DI(35 downto 34),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_30_35_n_0,
DOA(0) => RAM_reg_0_15_30_35_n_1,
DOB(1) => RAM_reg_0_15_30_35_n_2,
DOB(0) => RAM_reg_0_15_30_35_n_3,
DOC(1) => RAM_reg_0_15_30_35_n_4,
DOC(0) => RAM_reg_0_15_30_35_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_36_41: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(37 downto 36),
DIB(1 downto 0) => DI(39 downto 38),
DIC(1 downto 0) => DI(41 downto 40),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_36_41_n_0,
DOA(0) => RAM_reg_0_15_36_41_n_1,
DOB(1) => RAM_reg_0_15_36_41_n_2,
DOB(0) => RAM_reg_0_15_36_41_n_3,
DOC(1) => RAM_reg_0_15_36_41_n_4,
DOC(0) => RAM_reg_0_15_36_41_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_42_47: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(43 downto 42),
DIB(1 downto 0) => DI(45 downto 44),
DIC(1 downto 0) => DI(47 downto 46),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_42_47_n_0,
DOA(0) => RAM_reg_0_15_42_47_n_1,
DOB(1) => RAM_reg_0_15_42_47_n_2,
DOB(0) => RAM_reg_0_15_42_47_n_3,
DOC(1) => RAM_reg_0_15_42_47_n_4,
DOC(0) => RAM_reg_0_15_42_47_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_48_53: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(49 downto 48),
DIB(1 downto 0) => DI(51 downto 50),
DIC(1 downto 0) => DI(53 downto 52),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_48_53_n_0,
DOA(0) => RAM_reg_0_15_48_53_n_1,
DOB(1) => RAM_reg_0_15_48_53_n_2,
DOB(0) => RAM_reg_0_15_48_53_n_3,
DOC(1) => RAM_reg_0_15_48_53_n_4,
DOC(0) => RAM_reg_0_15_48_53_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_54_57: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(55 downto 54),
DIB(1 downto 0) => DI(57 downto 56),
DIC(1 downto 0) => B"00",
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_54_57_n_0,
DOA(0) => RAM_reg_0_15_54_57_n_1,
DOB(1) => RAM_reg_0_15_54_57_n_2,
DOB(0) => RAM_reg_0_15_54_57_n_3,
DOC(1 downto 0) => NLW_RAM_reg_0_15_54_57_DOC_UNCONNECTED(1 downto 0),
DOD(1 downto 0) => NLW_RAM_reg_0_15_54_57_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(7 downto 6),
DIB(1 downto 0) => DI(9 downto 8),
DIC(1 downto 0) => DI(11 downto 10),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_6_11_n_0,
DOA(0) => RAM_reg_0_15_6_11_n_1,
DOB(1) => RAM_reg_0_15_6_11_n_2,
DOB(0) => RAM_reg_0_15_6_11_n_3,
DOC(1) => RAM_reg_0_15_6_11_n_4,
DOC(0) => RAM_reg_0_15_6_11_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_1,
Q => dout_i(0),
R => '0'
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_5,
Q => dout_i(10),
R => '0'
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_4,
Q => dout_i(11),
R => '0'
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_1,
Q => dout_i(12),
R => '0'
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_0,
Q => dout_i(13),
R => '0'
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_3,
Q => dout_i(14),
R => '0'
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_2,
Q => dout_i(15),
R => '0'
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_5,
Q => dout_i(16),
R => '0'
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_4,
Q => dout_i(17),
R => '0'
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_1,
Q => dout_i(18),
R => '0'
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_0,
Q => dout_i(19),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_0,
Q => dout_i(1),
R => '0'
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_3,
Q => dout_i(20),
R => '0'
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_2,
Q => dout_i(21),
R => '0'
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_5,
Q => dout_i(22),
R => '0'
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_4,
Q => dout_i(23),
R => '0'
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_1,
Q => dout_i(24),
R => '0'
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_0,
Q => dout_i(25),
R => '0'
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_3,
Q => dout_i(26),
R => '0'
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_2,
Q => dout_i(27),
R => '0'
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_5,
Q => dout_i(28),
R => '0'
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_4,
Q => dout_i(29),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_3,
Q => dout_i(2),
R => '0'
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_1,
Q => dout_i(30),
R => '0'
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_0,
Q => dout_i(31),
R => '0'
);
\gpr1.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_3,
Q => dout_i(32),
R => '0'
);
\gpr1.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_2,
Q => dout_i(33),
R => '0'
);
\gpr1.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_5,
Q => dout_i(34),
R => '0'
);
\gpr1.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_4,
Q => dout_i(35),
R => '0'
);
\gpr1.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_1,
Q => dout_i(36),
R => '0'
);
\gpr1.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_0,
Q => dout_i(37),
R => '0'
);
\gpr1.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_3,
Q => dout_i(38),
R => '0'
);
\gpr1.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_2,
Q => dout_i(39),
R => '0'
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_2,
Q => dout_i(3),
R => '0'
);
\gpr1.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_5,
Q => dout_i(40),
R => '0'
);
\gpr1.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_4,
Q => dout_i(41),
R => '0'
);
\gpr1.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_1,
Q => dout_i(42),
R => '0'
);
\gpr1.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_0,
Q => dout_i(43),
R => '0'
);
\gpr1.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_3,
Q => dout_i(44),
R => '0'
);
\gpr1.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_2,
Q => dout_i(45),
R => '0'
);
\gpr1.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_5,
Q => dout_i(46),
R => '0'
);
\gpr1.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_4,
Q => dout_i(47),
R => '0'
);
\gpr1.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_1,
Q => dout_i(48),
R => '0'
);
\gpr1.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_0,
Q => dout_i(49),
R => '0'
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_5,
Q => dout_i(4),
R => '0'
);
\gpr1.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_3,
Q => dout_i(50),
R => '0'
);
\gpr1.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_2,
Q => dout_i(51),
R => '0'
);
\gpr1.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_5,
Q => dout_i(52),
R => '0'
);
\gpr1.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_4,
Q => dout_i(53),
R => '0'
);
\gpr1.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_57_n_1,
Q => dout_i(54),
R => '0'
);
\gpr1.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_57_n_0,
Q => dout_i(55),
R => '0'
);
\gpr1.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_57_n_3,
Q => dout_i(56),
R => '0'
);
\gpr1.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_57_n_2,
Q => dout_i(57),
R => '0'
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_4,
Q => dout_i(5),
R => '0'
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_1,
Q => dout_i(6),
R => '0'
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_0,
Q => dout_i(7),
R => '0'
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_3,
Q => dout_i(8),
R => '0'
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_2,
Q => dout_i(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_dmem_81 is
port (
Q : out STD_LOGIC_VECTOR ( 57 downto 0 );
s_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I123 : in STD_LOGIC_VECTOR ( 57 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_dmem_81 : entity is "dmem";
end system_auto_cc_0_dmem_81;
architecture STRUCTURE of system_auto_cc_0_dmem_81 is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_0 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_1 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_2 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_3 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_4 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_5 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_0 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_1 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_2 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_3 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_4 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_5 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_0 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_1 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_2 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_3 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_4 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_5 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_0 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_1 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_2 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_3 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_4 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_5 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_0 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_1 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_2 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_3 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_4 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_5 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_0 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_1 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_2 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_3 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_4 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_5 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_0 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_1 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_2 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_3 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_4 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_5 : STD_LOGIC;
signal RAM_reg_0_15_54_57_n_0 : STD_LOGIC;
signal RAM_reg_0_15_54_57_n_1 : STD_LOGIC;
signal RAM_reg_0_15_54_57_n_2 : STD_LOGIC;
signal RAM_reg_0_15_54_57_n_3 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_0 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_1 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_2 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_3 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_4 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_5 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_54_57_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_54_57_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_12_17 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_18_23 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_24_29 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_30_35 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_36_41 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_42_47 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_48_53 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_54_57 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_6_11 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(1 downto 0),
DIB(1 downto 0) => I123(3 downto 2),
DIC(1 downto 0) => I123(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(13 downto 12),
DIB(1 downto 0) => I123(15 downto 14),
DIC(1 downto 0) => I123(17 downto 16),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_12_17_n_0,
DOA(0) => RAM_reg_0_15_12_17_n_1,
DOB(1) => RAM_reg_0_15_12_17_n_2,
DOB(0) => RAM_reg_0_15_12_17_n_3,
DOC(1) => RAM_reg_0_15_12_17_n_4,
DOC(0) => RAM_reg_0_15_12_17_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(19 downto 18),
DIB(1 downto 0) => I123(21 downto 20),
DIC(1 downto 0) => I123(23 downto 22),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_18_23_n_0,
DOA(0) => RAM_reg_0_15_18_23_n_1,
DOB(1) => RAM_reg_0_15_18_23_n_2,
DOB(0) => RAM_reg_0_15_18_23_n_3,
DOC(1) => RAM_reg_0_15_18_23_n_4,
DOC(0) => RAM_reg_0_15_18_23_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(25 downto 24),
DIB(1 downto 0) => I123(27 downto 26),
DIC(1 downto 0) => I123(29 downto 28),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_24_29_n_0,
DOA(0) => RAM_reg_0_15_24_29_n_1,
DOB(1) => RAM_reg_0_15_24_29_n_2,
DOB(0) => RAM_reg_0_15_24_29_n_3,
DOC(1) => RAM_reg_0_15_24_29_n_4,
DOC(0) => RAM_reg_0_15_24_29_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_30_35: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(31 downto 30),
DIB(1 downto 0) => I123(33 downto 32),
DIC(1 downto 0) => I123(35 downto 34),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_30_35_n_0,
DOA(0) => RAM_reg_0_15_30_35_n_1,
DOB(1) => RAM_reg_0_15_30_35_n_2,
DOB(0) => RAM_reg_0_15_30_35_n_3,
DOC(1) => RAM_reg_0_15_30_35_n_4,
DOC(0) => RAM_reg_0_15_30_35_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_36_41: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(37 downto 36),
DIB(1 downto 0) => I123(39 downto 38),
DIC(1 downto 0) => I123(41 downto 40),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_36_41_n_0,
DOA(0) => RAM_reg_0_15_36_41_n_1,
DOB(1) => RAM_reg_0_15_36_41_n_2,
DOB(0) => RAM_reg_0_15_36_41_n_3,
DOC(1) => RAM_reg_0_15_36_41_n_4,
DOC(0) => RAM_reg_0_15_36_41_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_42_47: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(43 downto 42),
DIB(1 downto 0) => I123(45 downto 44),
DIC(1 downto 0) => I123(47 downto 46),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_42_47_n_0,
DOA(0) => RAM_reg_0_15_42_47_n_1,
DOB(1) => RAM_reg_0_15_42_47_n_2,
DOB(0) => RAM_reg_0_15_42_47_n_3,
DOC(1) => RAM_reg_0_15_42_47_n_4,
DOC(0) => RAM_reg_0_15_42_47_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_48_53: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(49 downto 48),
DIB(1 downto 0) => I123(51 downto 50),
DIC(1 downto 0) => I123(53 downto 52),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_48_53_n_0,
DOA(0) => RAM_reg_0_15_48_53_n_1,
DOB(1) => RAM_reg_0_15_48_53_n_2,
DOB(0) => RAM_reg_0_15_48_53_n_3,
DOC(1) => RAM_reg_0_15_48_53_n_4,
DOC(0) => RAM_reg_0_15_48_53_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_54_57: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(55 downto 54),
DIB(1 downto 0) => I123(57 downto 56),
DIC(1 downto 0) => B"00",
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_54_57_n_0,
DOA(0) => RAM_reg_0_15_54_57_n_1,
DOB(1) => RAM_reg_0_15_54_57_n_2,
DOB(0) => RAM_reg_0_15_54_57_n_3,
DOC(1 downto 0) => NLW_RAM_reg_0_15_54_57_DOC_UNCONNECTED(1 downto 0),
DOD(1 downto 0) => NLW_RAM_reg_0_15_54_57_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(7 downto 6),
DIB(1 downto 0) => I123(9 downto 8),
DIC(1 downto 0) => I123(11 downto 10),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_6_11_n_0,
DOA(0) => RAM_reg_0_15_6_11_n_1,
DOB(1) => RAM_reg_0_15_6_11_n_2,
DOB(0) => RAM_reg_0_15_6_11_n_3,
DOC(1) => RAM_reg_0_15_6_11_n_4,
DOC(0) => RAM_reg_0_15_6_11_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_1,
Q => Q(0),
R => '0'
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_5,
Q => Q(10),
R => '0'
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_4,
Q => Q(11),
R => '0'
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_1,
Q => Q(12),
R => '0'
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_0,
Q => Q(13),
R => '0'
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_3,
Q => Q(14),
R => '0'
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_2,
Q => Q(15),
R => '0'
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_5,
Q => Q(16),
R => '0'
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_4,
Q => Q(17),
R => '0'
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_1,
Q => Q(18),
R => '0'
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_0,
Q => Q(19),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_0,
Q => Q(1),
R => '0'
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_3,
Q => Q(20),
R => '0'
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_2,
Q => Q(21),
R => '0'
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_5,
Q => Q(22),
R => '0'
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_4,
Q => Q(23),
R => '0'
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_1,
Q => Q(24),
R => '0'
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_0,
Q => Q(25),
R => '0'
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_3,
Q => Q(26),
R => '0'
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_2,
Q => Q(27),
R => '0'
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_5,
Q => Q(28),
R => '0'
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_4,
Q => Q(29),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_3,
Q => Q(2),
R => '0'
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_1,
Q => Q(30),
R => '0'
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_0,
Q => Q(31),
R => '0'
);
\gpr1.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_3,
Q => Q(32),
R => '0'
);
\gpr1.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_2,
Q => Q(33),
R => '0'
);
\gpr1.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_5,
Q => Q(34),
R => '0'
);
\gpr1.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_4,
Q => Q(35),
R => '0'
);
\gpr1.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_1,
Q => Q(36),
R => '0'
);
\gpr1.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_0,
Q => Q(37),
R => '0'
);
\gpr1.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_3,
Q => Q(38),
R => '0'
);
\gpr1.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_2,
Q => Q(39),
R => '0'
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_2,
Q => Q(3),
R => '0'
);
\gpr1.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_5,
Q => Q(40),
R => '0'
);
\gpr1.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_4,
Q => Q(41),
R => '0'
);
\gpr1.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_1,
Q => Q(42),
R => '0'
);
\gpr1.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_0,
Q => Q(43),
R => '0'
);
\gpr1.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_3,
Q => Q(44),
R => '0'
);
\gpr1.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_2,
Q => Q(45),
R => '0'
);
\gpr1.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_5,
Q => Q(46),
R => '0'
);
\gpr1.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_4,
Q => Q(47),
R => '0'
);
\gpr1.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_1,
Q => Q(48),
R => '0'
);
\gpr1.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_0,
Q => Q(49),
R => '0'
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_5,
Q => Q(4),
R => '0'
);
\gpr1.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_3,
Q => Q(50),
R => '0'
);
\gpr1.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_2,
Q => Q(51),
R => '0'
);
\gpr1.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_5,
Q => Q(52),
R => '0'
);
\gpr1.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_4,
Q => Q(53),
R => '0'
);
\gpr1.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_57_n_1,
Q => Q(54),
R => '0'
);
\gpr1.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_57_n_0,
Q => Q(55),
R => '0'
);
\gpr1.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_57_n_3,
Q => Q(56),
R => '0'
);
\gpr1.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_57_n_2,
Q => Q(57),
R => '0'
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_4,
Q => Q(5),
R => '0'
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_1,
Q => Q(6),
R => '0'
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_0,
Q => Q(7),
R => '0'
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_3,
Q => Q(8),
R => '0'
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_2,
Q => Q(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_dmem__parameterized0\ is
port (
Q : out STD_LOGIC_VECTOR ( 144 downto 0 );
s_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I115 : in STD_LOGIC_VECTOR ( 144 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_dmem__parameterized0\ : entity is "dmem";
end \system_auto_cc_0_dmem__parameterized0\;
architecture STRUCTURE of \system_auto_cc_0_dmem__parameterized0\ is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal RAM_reg_0_15_102_107_n_0 : STD_LOGIC;
signal RAM_reg_0_15_102_107_n_1 : STD_LOGIC;
signal RAM_reg_0_15_102_107_n_2 : STD_LOGIC;
signal RAM_reg_0_15_102_107_n_3 : STD_LOGIC;
signal RAM_reg_0_15_102_107_n_4 : STD_LOGIC;
signal RAM_reg_0_15_102_107_n_5 : STD_LOGIC;
signal RAM_reg_0_15_108_113_n_0 : STD_LOGIC;
signal RAM_reg_0_15_108_113_n_1 : STD_LOGIC;
signal RAM_reg_0_15_108_113_n_2 : STD_LOGIC;
signal RAM_reg_0_15_108_113_n_3 : STD_LOGIC;
signal RAM_reg_0_15_108_113_n_4 : STD_LOGIC;
signal RAM_reg_0_15_108_113_n_5 : STD_LOGIC;
signal RAM_reg_0_15_114_119_n_0 : STD_LOGIC;
signal RAM_reg_0_15_114_119_n_1 : STD_LOGIC;
signal RAM_reg_0_15_114_119_n_2 : STD_LOGIC;
signal RAM_reg_0_15_114_119_n_3 : STD_LOGIC;
signal RAM_reg_0_15_114_119_n_4 : STD_LOGIC;
signal RAM_reg_0_15_114_119_n_5 : STD_LOGIC;
signal RAM_reg_0_15_120_125_n_0 : STD_LOGIC;
signal RAM_reg_0_15_120_125_n_1 : STD_LOGIC;
signal RAM_reg_0_15_120_125_n_2 : STD_LOGIC;
signal RAM_reg_0_15_120_125_n_3 : STD_LOGIC;
signal RAM_reg_0_15_120_125_n_4 : STD_LOGIC;
signal RAM_reg_0_15_120_125_n_5 : STD_LOGIC;
signal RAM_reg_0_15_126_131_n_0 : STD_LOGIC;
signal RAM_reg_0_15_126_131_n_1 : STD_LOGIC;
signal RAM_reg_0_15_126_131_n_2 : STD_LOGIC;
signal RAM_reg_0_15_126_131_n_3 : STD_LOGIC;
signal RAM_reg_0_15_126_131_n_4 : STD_LOGIC;
signal RAM_reg_0_15_126_131_n_5 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_0 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_1 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_2 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_3 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_4 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_5 : STD_LOGIC;
signal RAM_reg_0_15_132_137_n_0 : STD_LOGIC;
signal RAM_reg_0_15_132_137_n_1 : STD_LOGIC;
signal RAM_reg_0_15_132_137_n_2 : STD_LOGIC;
signal RAM_reg_0_15_132_137_n_3 : STD_LOGIC;
signal RAM_reg_0_15_132_137_n_4 : STD_LOGIC;
signal RAM_reg_0_15_132_137_n_5 : STD_LOGIC;
signal RAM_reg_0_15_138_143_n_0 : STD_LOGIC;
signal RAM_reg_0_15_138_143_n_1 : STD_LOGIC;
signal RAM_reg_0_15_138_143_n_2 : STD_LOGIC;
signal RAM_reg_0_15_138_143_n_3 : STD_LOGIC;
signal RAM_reg_0_15_138_143_n_4 : STD_LOGIC;
signal RAM_reg_0_15_138_143_n_5 : STD_LOGIC;
signal RAM_reg_0_15_144_144_n_1 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_0 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_1 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_2 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_3 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_4 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_5 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_0 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_1 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_2 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_3 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_4 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_5 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_0 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_1 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_2 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_3 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_4 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_5 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_0 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_1 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_2 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_3 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_4 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_5 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_0 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_1 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_2 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_3 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_4 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_5 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_0 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_1 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_2 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_3 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_4 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_5 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_0 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_1 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_2 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_3 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_4 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_5 : STD_LOGIC;
signal RAM_reg_0_15_60_65_n_0 : STD_LOGIC;
signal RAM_reg_0_15_60_65_n_1 : STD_LOGIC;
signal RAM_reg_0_15_60_65_n_2 : STD_LOGIC;
signal RAM_reg_0_15_60_65_n_3 : STD_LOGIC;
signal RAM_reg_0_15_60_65_n_4 : STD_LOGIC;
signal RAM_reg_0_15_60_65_n_5 : STD_LOGIC;
signal RAM_reg_0_15_66_71_n_0 : STD_LOGIC;
signal RAM_reg_0_15_66_71_n_1 : STD_LOGIC;
signal RAM_reg_0_15_66_71_n_2 : STD_LOGIC;
signal RAM_reg_0_15_66_71_n_3 : STD_LOGIC;
signal RAM_reg_0_15_66_71_n_4 : STD_LOGIC;
signal RAM_reg_0_15_66_71_n_5 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_0 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_1 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_2 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_3 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_4 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_5 : STD_LOGIC;
signal RAM_reg_0_15_72_77_n_0 : STD_LOGIC;
signal RAM_reg_0_15_72_77_n_1 : STD_LOGIC;
signal RAM_reg_0_15_72_77_n_2 : STD_LOGIC;
signal RAM_reg_0_15_72_77_n_3 : STD_LOGIC;
signal RAM_reg_0_15_72_77_n_4 : STD_LOGIC;
signal RAM_reg_0_15_72_77_n_5 : STD_LOGIC;
signal RAM_reg_0_15_78_83_n_0 : STD_LOGIC;
signal RAM_reg_0_15_78_83_n_1 : STD_LOGIC;
signal RAM_reg_0_15_78_83_n_2 : STD_LOGIC;
signal RAM_reg_0_15_78_83_n_3 : STD_LOGIC;
signal RAM_reg_0_15_78_83_n_4 : STD_LOGIC;
signal RAM_reg_0_15_78_83_n_5 : STD_LOGIC;
signal RAM_reg_0_15_84_89_n_0 : STD_LOGIC;
signal RAM_reg_0_15_84_89_n_1 : STD_LOGIC;
signal RAM_reg_0_15_84_89_n_2 : STD_LOGIC;
signal RAM_reg_0_15_84_89_n_3 : STD_LOGIC;
signal RAM_reg_0_15_84_89_n_4 : STD_LOGIC;
signal RAM_reg_0_15_84_89_n_5 : STD_LOGIC;
signal RAM_reg_0_15_90_95_n_0 : STD_LOGIC;
signal RAM_reg_0_15_90_95_n_1 : STD_LOGIC;
signal RAM_reg_0_15_90_95_n_2 : STD_LOGIC;
signal RAM_reg_0_15_90_95_n_3 : STD_LOGIC;
signal RAM_reg_0_15_90_95_n_4 : STD_LOGIC;
signal RAM_reg_0_15_90_95_n_5 : STD_LOGIC;
signal RAM_reg_0_15_96_101_n_0 : STD_LOGIC;
signal RAM_reg_0_15_96_101_n_1 : STD_LOGIC;
signal RAM_reg_0_15_96_101_n_2 : STD_LOGIC;
signal RAM_reg_0_15_96_101_n_3 : STD_LOGIC;
signal RAM_reg_0_15_96_101_n_4 : STD_LOGIC;
signal RAM_reg_0_15_96_101_n_5 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_102_107_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_108_113_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_114_119_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_120_125_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_126_131_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_132_137_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_138_143_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_144_144_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_RAM_reg_0_15_144_144_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_144_144_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_144_144_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_78_83_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_84_89_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_90_95_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_96_101_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_102_107 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_108_113 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_114_119 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_120_125 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_126_131 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_12_17 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_132_137 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_138_143 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_144_144 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_18_23 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_24_29 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_30_35 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_36_41 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_42_47 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_48_53 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_54_59 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_60_65 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_66_71 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_6_11 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_72_77 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_78_83 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_84_89 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_90_95 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_96_101 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(1 downto 0),
DIB(1 downto 0) => I115(3 downto 2),
DIC(1 downto 0) => I115(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_102_107: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(103 downto 102),
DIB(1 downto 0) => I115(105 downto 104),
DIC(1 downto 0) => I115(107 downto 106),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_102_107_n_0,
DOA(0) => RAM_reg_0_15_102_107_n_1,
DOB(1) => RAM_reg_0_15_102_107_n_2,
DOB(0) => RAM_reg_0_15_102_107_n_3,
DOC(1) => RAM_reg_0_15_102_107_n_4,
DOC(0) => RAM_reg_0_15_102_107_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_102_107_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_108_113: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(109 downto 108),
DIB(1 downto 0) => I115(111 downto 110),
DIC(1 downto 0) => I115(113 downto 112),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_108_113_n_0,
DOA(0) => RAM_reg_0_15_108_113_n_1,
DOB(1) => RAM_reg_0_15_108_113_n_2,
DOB(0) => RAM_reg_0_15_108_113_n_3,
DOC(1) => RAM_reg_0_15_108_113_n_4,
DOC(0) => RAM_reg_0_15_108_113_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_108_113_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_114_119: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(115 downto 114),
DIB(1 downto 0) => I115(117 downto 116),
DIC(1 downto 0) => I115(119 downto 118),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_114_119_n_0,
DOA(0) => RAM_reg_0_15_114_119_n_1,
DOB(1) => RAM_reg_0_15_114_119_n_2,
DOB(0) => RAM_reg_0_15_114_119_n_3,
DOC(1) => RAM_reg_0_15_114_119_n_4,
DOC(0) => RAM_reg_0_15_114_119_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_114_119_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_120_125: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(121 downto 120),
DIB(1 downto 0) => I115(123 downto 122),
DIC(1 downto 0) => I115(125 downto 124),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_120_125_n_0,
DOA(0) => RAM_reg_0_15_120_125_n_1,
DOB(1) => RAM_reg_0_15_120_125_n_2,
DOB(0) => RAM_reg_0_15_120_125_n_3,
DOC(1) => RAM_reg_0_15_120_125_n_4,
DOC(0) => RAM_reg_0_15_120_125_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_120_125_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_126_131: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(127 downto 126),
DIB(1 downto 0) => I115(129 downto 128),
DIC(1 downto 0) => I115(131 downto 130),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_126_131_n_0,
DOA(0) => RAM_reg_0_15_126_131_n_1,
DOB(1) => RAM_reg_0_15_126_131_n_2,
DOB(0) => RAM_reg_0_15_126_131_n_3,
DOC(1) => RAM_reg_0_15_126_131_n_4,
DOC(0) => RAM_reg_0_15_126_131_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_126_131_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(13 downto 12),
DIB(1 downto 0) => I115(15 downto 14),
DIC(1 downto 0) => I115(17 downto 16),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_12_17_n_0,
DOA(0) => RAM_reg_0_15_12_17_n_1,
DOB(1) => RAM_reg_0_15_12_17_n_2,
DOB(0) => RAM_reg_0_15_12_17_n_3,
DOC(1) => RAM_reg_0_15_12_17_n_4,
DOC(0) => RAM_reg_0_15_12_17_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_132_137: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(133 downto 132),
DIB(1 downto 0) => I115(135 downto 134),
DIC(1 downto 0) => I115(137 downto 136),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_132_137_n_0,
DOA(0) => RAM_reg_0_15_132_137_n_1,
DOB(1) => RAM_reg_0_15_132_137_n_2,
DOB(0) => RAM_reg_0_15_132_137_n_3,
DOC(1) => RAM_reg_0_15_132_137_n_4,
DOC(0) => RAM_reg_0_15_132_137_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_132_137_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_138_143: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(139 downto 138),
DIB(1 downto 0) => I115(141 downto 140),
DIC(1 downto 0) => I115(143 downto 142),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_138_143_n_0,
DOA(0) => RAM_reg_0_15_138_143_n_1,
DOB(1) => RAM_reg_0_15_138_143_n_2,
DOB(0) => RAM_reg_0_15_138_143_n_3,
DOC(1) => RAM_reg_0_15_138_143_n_4,
DOC(0) => RAM_reg_0_15_138_143_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_138_143_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_144_144: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1) => '0',
DIA(0) => I115(144),
DIB(1 downto 0) => B"00",
DIC(1 downto 0) => B"00",
DID(1 downto 0) => B"00",
DOA(1) => NLW_RAM_reg_0_15_144_144_DOA_UNCONNECTED(1),
DOA(0) => RAM_reg_0_15_144_144_n_1,
DOB(1 downto 0) => NLW_RAM_reg_0_15_144_144_DOB_UNCONNECTED(1 downto 0),
DOC(1 downto 0) => NLW_RAM_reg_0_15_144_144_DOC_UNCONNECTED(1 downto 0),
DOD(1 downto 0) => NLW_RAM_reg_0_15_144_144_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(19 downto 18),
DIB(1 downto 0) => I115(21 downto 20),
DIC(1 downto 0) => I115(23 downto 22),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_18_23_n_0,
DOA(0) => RAM_reg_0_15_18_23_n_1,
DOB(1) => RAM_reg_0_15_18_23_n_2,
DOB(0) => RAM_reg_0_15_18_23_n_3,
DOC(1) => RAM_reg_0_15_18_23_n_4,
DOC(0) => RAM_reg_0_15_18_23_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(25 downto 24),
DIB(1 downto 0) => I115(27 downto 26),
DIC(1 downto 0) => I115(29 downto 28),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_24_29_n_0,
DOA(0) => RAM_reg_0_15_24_29_n_1,
DOB(1) => RAM_reg_0_15_24_29_n_2,
DOB(0) => RAM_reg_0_15_24_29_n_3,
DOC(1) => RAM_reg_0_15_24_29_n_4,
DOC(0) => RAM_reg_0_15_24_29_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_30_35: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(31 downto 30),
DIB(1 downto 0) => I115(33 downto 32),
DIC(1 downto 0) => I115(35 downto 34),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_30_35_n_0,
DOA(0) => RAM_reg_0_15_30_35_n_1,
DOB(1) => RAM_reg_0_15_30_35_n_2,
DOB(0) => RAM_reg_0_15_30_35_n_3,
DOC(1) => RAM_reg_0_15_30_35_n_4,
DOC(0) => RAM_reg_0_15_30_35_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_36_41: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(37 downto 36),
DIB(1 downto 0) => I115(39 downto 38),
DIC(1 downto 0) => I115(41 downto 40),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_36_41_n_0,
DOA(0) => RAM_reg_0_15_36_41_n_1,
DOB(1) => RAM_reg_0_15_36_41_n_2,
DOB(0) => RAM_reg_0_15_36_41_n_3,
DOC(1) => RAM_reg_0_15_36_41_n_4,
DOC(0) => RAM_reg_0_15_36_41_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_42_47: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(43 downto 42),
DIB(1 downto 0) => I115(45 downto 44),
DIC(1 downto 0) => I115(47 downto 46),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_42_47_n_0,
DOA(0) => RAM_reg_0_15_42_47_n_1,
DOB(1) => RAM_reg_0_15_42_47_n_2,
DOB(0) => RAM_reg_0_15_42_47_n_3,
DOC(1) => RAM_reg_0_15_42_47_n_4,
DOC(0) => RAM_reg_0_15_42_47_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_48_53: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(49 downto 48),
DIB(1 downto 0) => I115(51 downto 50),
DIC(1 downto 0) => I115(53 downto 52),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_48_53_n_0,
DOA(0) => RAM_reg_0_15_48_53_n_1,
DOB(1) => RAM_reg_0_15_48_53_n_2,
DOB(0) => RAM_reg_0_15_48_53_n_3,
DOC(1) => RAM_reg_0_15_48_53_n_4,
DOC(0) => RAM_reg_0_15_48_53_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_54_59: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(55 downto 54),
DIB(1 downto 0) => I115(57 downto 56),
DIC(1 downto 0) => I115(59 downto 58),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_54_59_n_0,
DOA(0) => RAM_reg_0_15_54_59_n_1,
DOB(1) => RAM_reg_0_15_54_59_n_2,
DOB(0) => RAM_reg_0_15_54_59_n_3,
DOC(1) => RAM_reg_0_15_54_59_n_4,
DOC(0) => RAM_reg_0_15_54_59_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_60_65: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(61 downto 60),
DIB(1 downto 0) => I115(63 downto 62),
DIC(1 downto 0) => I115(65 downto 64),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_60_65_n_0,
DOA(0) => RAM_reg_0_15_60_65_n_1,
DOB(1) => RAM_reg_0_15_60_65_n_2,
DOB(0) => RAM_reg_0_15_60_65_n_3,
DOC(1) => RAM_reg_0_15_60_65_n_4,
DOC(0) => RAM_reg_0_15_60_65_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_60_65_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_66_71: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(67 downto 66),
DIB(1 downto 0) => I115(69 downto 68),
DIC(1 downto 0) => I115(71 downto 70),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_66_71_n_0,
DOA(0) => RAM_reg_0_15_66_71_n_1,
DOB(1) => RAM_reg_0_15_66_71_n_2,
DOB(0) => RAM_reg_0_15_66_71_n_3,
DOC(1) => RAM_reg_0_15_66_71_n_4,
DOC(0) => RAM_reg_0_15_66_71_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_66_71_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(7 downto 6),
DIB(1 downto 0) => I115(9 downto 8),
DIC(1 downto 0) => I115(11 downto 10),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_6_11_n_0,
DOA(0) => RAM_reg_0_15_6_11_n_1,
DOB(1) => RAM_reg_0_15_6_11_n_2,
DOB(0) => RAM_reg_0_15_6_11_n_3,
DOC(1) => RAM_reg_0_15_6_11_n_4,
DOC(0) => RAM_reg_0_15_6_11_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_72_77: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(73 downto 72),
DIB(1 downto 0) => I115(75 downto 74),
DIC(1 downto 0) => I115(77 downto 76),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_72_77_n_0,
DOA(0) => RAM_reg_0_15_72_77_n_1,
DOB(1) => RAM_reg_0_15_72_77_n_2,
DOB(0) => RAM_reg_0_15_72_77_n_3,
DOC(1) => RAM_reg_0_15_72_77_n_4,
DOC(0) => RAM_reg_0_15_72_77_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_72_77_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_78_83: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(79 downto 78),
DIB(1 downto 0) => I115(81 downto 80),
DIC(1 downto 0) => I115(83 downto 82),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_78_83_n_0,
DOA(0) => RAM_reg_0_15_78_83_n_1,
DOB(1) => RAM_reg_0_15_78_83_n_2,
DOB(0) => RAM_reg_0_15_78_83_n_3,
DOC(1) => RAM_reg_0_15_78_83_n_4,
DOC(0) => RAM_reg_0_15_78_83_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_78_83_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_84_89: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(85 downto 84),
DIB(1 downto 0) => I115(87 downto 86),
DIC(1 downto 0) => I115(89 downto 88),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_84_89_n_0,
DOA(0) => RAM_reg_0_15_84_89_n_1,
DOB(1) => RAM_reg_0_15_84_89_n_2,
DOB(0) => RAM_reg_0_15_84_89_n_3,
DOC(1) => RAM_reg_0_15_84_89_n_4,
DOC(0) => RAM_reg_0_15_84_89_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_84_89_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_90_95: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(91 downto 90),
DIB(1 downto 0) => I115(93 downto 92),
DIC(1 downto 0) => I115(95 downto 94),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_90_95_n_0,
DOA(0) => RAM_reg_0_15_90_95_n_1,
DOB(1) => RAM_reg_0_15_90_95_n_2,
DOB(0) => RAM_reg_0_15_90_95_n_3,
DOC(1) => RAM_reg_0_15_90_95_n_4,
DOC(0) => RAM_reg_0_15_90_95_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_90_95_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_96_101: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(97 downto 96),
DIB(1 downto 0) => I115(99 downto 98),
DIC(1 downto 0) => I115(101 downto 100),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_96_101_n_0,
DOA(0) => RAM_reg_0_15_96_101_n_1,
DOB(1) => RAM_reg_0_15_96_101_n_2,
DOB(0) => RAM_reg_0_15_96_101_n_3,
DOC(1) => RAM_reg_0_15_96_101_n_4,
DOC(0) => RAM_reg_0_15_96_101_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_96_101_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_1,
Q => Q(0),
R => '0'
);
\gpr1.dout_i_reg[100]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_96_101_n_5,
Q => Q(100),
R => '0'
);
\gpr1.dout_i_reg[101]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_96_101_n_4,
Q => Q(101),
R => '0'
);
\gpr1.dout_i_reg[102]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_102_107_n_1,
Q => Q(102),
R => '0'
);
\gpr1.dout_i_reg[103]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_102_107_n_0,
Q => Q(103),
R => '0'
);
\gpr1.dout_i_reg[104]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_102_107_n_3,
Q => Q(104),
R => '0'
);
\gpr1.dout_i_reg[105]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_102_107_n_2,
Q => Q(105),
R => '0'
);
\gpr1.dout_i_reg[106]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_102_107_n_5,
Q => Q(106),
R => '0'
);
\gpr1.dout_i_reg[107]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_102_107_n_4,
Q => Q(107),
R => '0'
);
\gpr1.dout_i_reg[108]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_108_113_n_1,
Q => Q(108),
R => '0'
);
\gpr1.dout_i_reg[109]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_108_113_n_0,
Q => Q(109),
R => '0'
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_5,
Q => Q(10),
R => '0'
);
\gpr1.dout_i_reg[110]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_108_113_n_3,
Q => Q(110),
R => '0'
);
\gpr1.dout_i_reg[111]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_108_113_n_2,
Q => Q(111),
R => '0'
);
\gpr1.dout_i_reg[112]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_108_113_n_5,
Q => Q(112),
R => '0'
);
\gpr1.dout_i_reg[113]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_108_113_n_4,
Q => Q(113),
R => '0'
);
\gpr1.dout_i_reg[114]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_114_119_n_1,
Q => Q(114),
R => '0'
);
\gpr1.dout_i_reg[115]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_114_119_n_0,
Q => Q(115),
R => '0'
);
\gpr1.dout_i_reg[116]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_114_119_n_3,
Q => Q(116),
R => '0'
);
\gpr1.dout_i_reg[117]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_114_119_n_2,
Q => Q(117),
R => '0'
);
\gpr1.dout_i_reg[118]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_114_119_n_5,
Q => Q(118),
R => '0'
);
\gpr1.dout_i_reg[119]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_114_119_n_4,
Q => Q(119),
R => '0'
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_4,
Q => Q(11),
R => '0'
);
\gpr1.dout_i_reg[120]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_120_125_n_1,
Q => Q(120),
R => '0'
);
\gpr1.dout_i_reg[121]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_120_125_n_0,
Q => Q(121),
R => '0'
);
\gpr1.dout_i_reg[122]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_120_125_n_3,
Q => Q(122),
R => '0'
);
\gpr1.dout_i_reg[123]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_120_125_n_2,
Q => Q(123),
R => '0'
);
\gpr1.dout_i_reg[124]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_120_125_n_5,
Q => Q(124),
R => '0'
);
\gpr1.dout_i_reg[125]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_120_125_n_4,
Q => Q(125),
R => '0'
);
\gpr1.dout_i_reg[126]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_126_131_n_1,
Q => Q(126),
R => '0'
);
\gpr1.dout_i_reg[127]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_126_131_n_0,
Q => Q(127),
R => '0'
);
\gpr1.dout_i_reg[128]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_126_131_n_3,
Q => Q(128),
R => '0'
);
\gpr1.dout_i_reg[129]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_126_131_n_2,
Q => Q(129),
R => '0'
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_1,
Q => Q(12),
R => '0'
);
\gpr1.dout_i_reg[130]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_126_131_n_5,
Q => Q(130),
R => '0'
);
\gpr1.dout_i_reg[131]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_126_131_n_4,
Q => Q(131),
R => '0'
);
\gpr1.dout_i_reg[132]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_132_137_n_1,
Q => Q(132),
R => '0'
);
\gpr1.dout_i_reg[133]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_132_137_n_0,
Q => Q(133),
R => '0'
);
\gpr1.dout_i_reg[134]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_132_137_n_3,
Q => Q(134),
R => '0'
);
\gpr1.dout_i_reg[135]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_132_137_n_2,
Q => Q(135),
R => '0'
);
\gpr1.dout_i_reg[136]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_132_137_n_5,
Q => Q(136),
R => '0'
);
\gpr1.dout_i_reg[137]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_132_137_n_4,
Q => Q(137),
R => '0'
);
\gpr1.dout_i_reg[138]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_138_143_n_1,
Q => Q(138),
R => '0'
);
\gpr1.dout_i_reg[139]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_138_143_n_0,
Q => Q(139),
R => '0'
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_0,
Q => Q(13),
R => '0'
);
\gpr1.dout_i_reg[140]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_138_143_n_3,
Q => Q(140),
R => '0'
);
\gpr1.dout_i_reg[141]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_138_143_n_2,
Q => Q(141),
R => '0'
);
\gpr1.dout_i_reg[142]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_138_143_n_5,
Q => Q(142),
R => '0'
);
\gpr1.dout_i_reg[143]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_138_143_n_4,
Q => Q(143),
R => '0'
);
\gpr1.dout_i_reg[144]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_144_144_n_1,
Q => Q(144),
R => '0'
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_3,
Q => Q(14),
R => '0'
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_2,
Q => Q(15),
R => '0'
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_5,
Q => Q(16),
R => '0'
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_4,
Q => Q(17),
R => '0'
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_1,
Q => Q(18),
R => '0'
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_0,
Q => Q(19),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_0,
Q => Q(1),
R => '0'
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_3,
Q => Q(20),
R => '0'
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_2,
Q => Q(21),
R => '0'
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_5,
Q => Q(22),
R => '0'
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_4,
Q => Q(23),
R => '0'
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_1,
Q => Q(24),
R => '0'
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_0,
Q => Q(25),
R => '0'
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_3,
Q => Q(26),
R => '0'
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_2,
Q => Q(27),
R => '0'
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_5,
Q => Q(28),
R => '0'
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_4,
Q => Q(29),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_3,
Q => Q(2),
R => '0'
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_1,
Q => Q(30),
R => '0'
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_0,
Q => Q(31),
R => '0'
);
\gpr1.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_3,
Q => Q(32),
R => '0'
);
\gpr1.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_2,
Q => Q(33),
R => '0'
);
\gpr1.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_5,
Q => Q(34),
R => '0'
);
\gpr1.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_4,
Q => Q(35),
R => '0'
);
\gpr1.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_1,
Q => Q(36),
R => '0'
);
\gpr1.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_0,
Q => Q(37),
R => '0'
);
\gpr1.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_3,
Q => Q(38),
R => '0'
);
\gpr1.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_2,
Q => Q(39),
R => '0'
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_2,
Q => Q(3),
R => '0'
);
\gpr1.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_5,
Q => Q(40),
R => '0'
);
\gpr1.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_4,
Q => Q(41),
R => '0'
);
\gpr1.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_1,
Q => Q(42),
R => '0'
);
\gpr1.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_0,
Q => Q(43),
R => '0'
);
\gpr1.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_3,
Q => Q(44),
R => '0'
);
\gpr1.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_2,
Q => Q(45),
R => '0'
);
\gpr1.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_5,
Q => Q(46),
R => '0'
);
\gpr1.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_4,
Q => Q(47),
R => '0'
);
\gpr1.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_1,
Q => Q(48),
R => '0'
);
\gpr1.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_0,
Q => Q(49),
R => '0'
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_5,
Q => Q(4),
R => '0'
);
\gpr1.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_3,
Q => Q(50),
R => '0'
);
\gpr1.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_2,
Q => Q(51),
R => '0'
);
\gpr1.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_5,
Q => Q(52),
R => '0'
);
\gpr1.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_4,
Q => Q(53),
R => '0'
);
\gpr1.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_1,
Q => Q(54),
R => '0'
);
\gpr1.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_0,
Q => Q(55),
R => '0'
);
\gpr1.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_3,
Q => Q(56),
R => '0'
);
\gpr1.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_2,
Q => Q(57),
R => '0'
);
\gpr1.dout_i_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_5,
Q => Q(58),
R => '0'
);
\gpr1.dout_i_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_4,
Q => Q(59),
R => '0'
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_4,
Q => Q(5),
R => '0'
);
\gpr1.dout_i_reg[60]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_65_n_1,
Q => Q(60),
R => '0'
);
\gpr1.dout_i_reg[61]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_65_n_0,
Q => Q(61),
R => '0'
);
\gpr1.dout_i_reg[62]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_65_n_3,
Q => Q(62),
R => '0'
);
\gpr1.dout_i_reg[63]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_65_n_2,
Q => Q(63),
R => '0'
);
\gpr1.dout_i_reg[64]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_65_n_5,
Q => Q(64),
R => '0'
);
\gpr1.dout_i_reg[65]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_65_n_4,
Q => Q(65),
R => '0'
);
\gpr1.dout_i_reg[66]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_66_71_n_1,
Q => Q(66),
R => '0'
);
\gpr1.dout_i_reg[67]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_66_71_n_0,
Q => Q(67),
R => '0'
);
\gpr1.dout_i_reg[68]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_66_71_n_3,
Q => Q(68),
R => '0'
);
\gpr1.dout_i_reg[69]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_66_71_n_2,
Q => Q(69),
R => '0'
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_1,
Q => Q(6),
R => '0'
);
\gpr1.dout_i_reg[70]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_66_71_n_5,
Q => Q(70),
R => '0'
);
\gpr1.dout_i_reg[71]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_66_71_n_4,
Q => Q(71),
R => '0'
);
\gpr1.dout_i_reg[72]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_72_77_n_1,
Q => Q(72),
R => '0'
);
\gpr1.dout_i_reg[73]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_72_77_n_0,
Q => Q(73),
R => '0'
);
\gpr1.dout_i_reg[74]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_72_77_n_3,
Q => Q(74),
R => '0'
);
\gpr1.dout_i_reg[75]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_72_77_n_2,
Q => Q(75),
R => '0'
);
\gpr1.dout_i_reg[76]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_72_77_n_5,
Q => Q(76),
R => '0'
);
\gpr1.dout_i_reg[77]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_72_77_n_4,
Q => Q(77),
R => '0'
);
\gpr1.dout_i_reg[78]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_78_83_n_1,
Q => Q(78),
R => '0'
);
\gpr1.dout_i_reg[79]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_78_83_n_0,
Q => Q(79),
R => '0'
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_0,
Q => Q(7),
R => '0'
);
\gpr1.dout_i_reg[80]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_78_83_n_3,
Q => Q(80),
R => '0'
);
\gpr1.dout_i_reg[81]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_78_83_n_2,
Q => Q(81),
R => '0'
);
\gpr1.dout_i_reg[82]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_78_83_n_5,
Q => Q(82),
R => '0'
);
\gpr1.dout_i_reg[83]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_78_83_n_4,
Q => Q(83),
R => '0'
);
\gpr1.dout_i_reg[84]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_84_89_n_1,
Q => Q(84),
R => '0'
);
\gpr1.dout_i_reg[85]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_84_89_n_0,
Q => Q(85),
R => '0'
);
\gpr1.dout_i_reg[86]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_84_89_n_3,
Q => Q(86),
R => '0'
);
\gpr1.dout_i_reg[87]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_84_89_n_2,
Q => Q(87),
R => '0'
);
\gpr1.dout_i_reg[88]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_84_89_n_5,
Q => Q(88),
R => '0'
);
\gpr1.dout_i_reg[89]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_84_89_n_4,
Q => Q(89),
R => '0'
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_3,
Q => Q(8),
R => '0'
);
\gpr1.dout_i_reg[90]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_90_95_n_1,
Q => Q(90),
R => '0'
);
\gpr1.dout_i_reg[91]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_90_95_n_0,
Q => Q(91),
R => '0'
);
\gpr1.dout_i_reg[92]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_90_95_n_3,
Q => Q(92),
R => '0'
);
\gpr1.dout_i_reg[93]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_90_95_n_2,
Q => Q(93),
R => '0'
);
\gpr1.dout_i_reg[94]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_90_95_n_5,
Q => Q(94),
R => '0'
);
\gpr1.dout_i_reg[95]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_90_95_n_4,
Q => Q(95),
R => '0'
);
\gpr1.dout_i_reg[96]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_96_101_n_1,
Q => Q(96),
R => '0'
);
\gpr1.dout_i_reg[97]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_96_101_n_0,
Q => Q(97),
R => '0'
);
\gpr1.dout_i_reg[98]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_96_101_n_3,
Q => Q(98),
R => '0'
);
\gpr1.dout_i_reg[99]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_96_101_n_2,
Q => Q(99),
R => '0'
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_2,
Q => Q(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_dmem__parameterized1\ is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_dmem__parameterized1\ : entity is "dmem";
end \system_auto_cc_0_dmem__parameterized1\;
architecture STRUCTURE of \system_auto_cc_0_dmem__parameterized1\ is
signal RAM_reg_0_15_0_2_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_2_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_2_n_3 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_2_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_RAM_reg_0_15_0_2_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_0_2_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_2 : label is "";
begin
RAM_reg_0_15_0_2: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => m_axi_bresp(1 downto 0),
DIB(1) => '0',
DIB(0) => m_axi_bid(0),
DIC(1 downto 0) => B"00",
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_2_n_0,
DOA(0) => RAM_reg_0_15_0_2_n_1,
DOB(1) => NLW_RAM_reg_0_15_0_2_DOB_UNCONNECTED(1),
DOB(0) => RAM_reg_0_15_0_2_n_3,
DOC(1 downto 0) => NLW_RAM_reg_0_15_0_2_DOC_UNCONNECTED(1 downto 0),
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_2_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_2_n_1,
Q => Q(0),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_2_n_0,
Q => Q(1),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_2_n_3,
Q => Q(2),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_dmem__parameterized2\ is
port (
Q : out STD_LOGIC_VECTOR ( 131 downto 0 );
m_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I127 : in STD_LOGIC_VECTOR ( 131 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_dmem__parameterized2\ : entity is "dmem";
end \system_auto_cc_0_dmem__parameterized2\;
architecture STRUCTURE of \system_auto_cc_0_dmem__parameterized2\ is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal RAM_reg_0_15_102_107_n_0 : STD_LOGIC;
signal RAM_reg_0_15_102_107_n_1 : STD_LOGIC;
signal RAM_reg_0_15_102_107_n_2 : STD_LOGIC;
signal RAM_reg_0_15_102_107_n_3 : STD_LOGIC;
signal RAM_reg_0_15_102_107_n_4 : STD_LOGIC;
signal RAM_reg_0_15_102_107_n_5 : STD_LOGIC;
signal RAM_reg_0_15_108_113_n_0 : STD_LOGIC;
signal RAM_reg_0_15_108_113_n_1 : STD_LOGIC;
signal RAM_reg_0_15_108_113_n_2 : STD_LOGIC;
signal RAM_reg_0_15_108_113_n_3 : STD_LOGIC;
signal RAM_reg_0_15_108_113_n_4 : STD_LOGIC;
signal RAM_reg_0_15_108_113_n_5 : STD_LOGIC;
signal RAM_reg_0_15_114_119_n_0 : STD_LOGIC;
signal RAM_reg_0_15_114_119_n_1 : STD_LOGIC;
signal RAM_reg_0_15_114_119_n_2 : STD_LOGIC;
signal RAM_reg_0_15_114_119_n_3 : STD_LOGIC;
signal RAM_reg_0_15_114_119_n_4 : STD_LOGIC;
signal RAM_reg_0_15_114_119_n_5 : STD_LOGIC;
signal RAM_reg_0_15_120_125_n_0 : STD_LOGIC;
signal RAM_reg_0_15_120_125_n_1 : STD_LOGIC;
signal RAM_reg_0_15_120_125_n_2 : STD_LOGIC;
signal RAM_reg_0_15_120_125_n_3 : STD_LOGIC;
signal RAM_reg_0_15_120_125_n_4 : STD_LOGIC;
signal RAM_reg_0_15_120_125_n_5 : STD_LOGIC;
signal RAM_reg_0_15_126_131_n_0 : STD_LOGIC;
signal RAM_reg_0_15_126_131_n_1 : STD_LOGIC;
signal RAM_reg_0_15_126_131_n_2 : STD_LOGIC;
signal RAM_reg_0_15_126_131_n_3 : STD_LOGIC;
signal RAM_reg_0_15_126_131_n_4 : STD_LOGIC;
signal RAM_reg_0_15_126_131_n_5 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_0 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_1 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_2 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_3 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_4 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_5 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_0 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_1 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_2 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_3 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_4 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_5 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_0 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_1 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_2 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_3 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_4 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_5 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_0 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_1 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_2 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_3 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_4 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_5 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_0 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_1 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_2 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_3 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_4 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_5 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_0 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_1 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_2 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_3 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_4 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_5 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_0 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_1 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_2 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_3 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_4 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_5 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_0 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_1 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_2 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_3 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_4 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_5 : STD_LOGIC;
signal RAM_reg_0_15_60_65_n_0 : STD_LOGIC;
signal RAM_reg_0_15_60_65_n_1 : STD_LOGIC;
signal RAM_reg_0_15_60_65_n_2 : STD_LOGIC;
signal RAM_reg_0_15_60_65_n_3 : STD_LOGIC;
signal RAM_reg_0_15_60_65_n_4 : STD_LOGIC;
signal RAM_reg_0_15_60_65_n_5 : STD_LOGIC;
signal RAM_reg_0_15_66_71_n_0 : STD_LOGIC;
signal RAM_reg_0_15_66_71_n_1 : STD_LOGIC;
signal RAM_reg_0_15_66_71_n_2 : STD_LOGIC;
signal RAM_reg_0_15_66_71_n_3 : STD_LOGIC;
signal RAM_reg_0_15_66_71_n_4 : STD_LOGIC;
signal RAM_reg_0_15_66_71_n_5 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_0 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_1 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_2 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_3 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_4 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_5 : STD_LOGIC;
signal RAM_reg_0_15_72_77_n_0 : STD_LOGIC;
signal RAM_reg_0_15_72_77_n_1 : STD_LOGIC;
signal RAM_reg_0_15_72_77_n_2 : STD_LOGIC;
signal RAM_reg_0_15_72_77_n_3 : STD_LOGIC;
signal RAM_reg_0_15_72_77_n_4 : STD_LOGIC;
signal RAM_reg_0_15_72_77_n_5 : STD_LOGIC;
signal RAM_reg_0_15_78_83_n_0 : STD_LOGIC;
signal RAM_reg_0_15_78_83_n_1 : STD_LOGIC;
signal RAM_reg_0_15_78_83_n_2 : STD_LOGIC;
signal RAM_reg_0_15_78_83_n_3 : STD_LOGIC;
signal RAM_reg_0_15_78_83_n_4 : STD_LOGIC;
signal RAM_reg_0_15_78_83_n_5 : STD_LOGIC;
signal RAM_reg_0_15_84_89_n_0 : STD_LOGIC;
signal RAM_reg_0_15_84_89_n_1 : STD_LOGIC;
signal RAM_reg_0_15_84_89_n_2 : STD_LOGIC;
signal RAM_reg_0_15_84_89_n_3 : STD_LOGIC;
signal RAM_reg_0_15_84_89_n_4 : STD_LOGIC;
signal RAM_reg_0_15_84_89_n_5 : STD_LOGIC;
signal RAM_reg_0_15_90_95_n_0 : STD_LOGIC;
signal RAM_reg_0_15_90_95_n_1 : STD_LOGIC;
signal RAM_reg_0_15_90_95_n_2 : STD_LOGIC;
signal RAM_reg_0_15_90_95_n_3 : STD_LOGIC;
signal RAM_reg_0_15_90_95_n_4 : STD_LOGIC;
signal RAM_reg_0_15_90_95_n_5 : STD_LOGIC;
signal RAM_reg_0_15_96_101_n_0 : STD_LOGIC;
signal RAM_reg_0_15_96_101_n_1 : STD_LOGIC;
signal RAM_reg_0_15_96_101_n_2 : STD_LOGIC;
signal RAM_reg_0_15_96_101_n_3 : STD_LOGIC;
signal RAM_reg_0_15_96_101_n_4 : STD_LOGIC;
signal RAM_reg_0_15_96_101_n_5 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_102_107_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_108_113_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_114_119_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_120_125_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_126_131_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_78_83_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_84_89_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_90_95_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_96_101_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_102_107 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_108_113 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_114_119 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_120_125 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_126_131 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_12_17 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_18_23 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_24_29 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_30_35 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_36_41 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_42_47 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_48_53 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_54_59 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_60_65 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_66_71 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_6_11 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_72_77 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_78_83 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_84_89 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_90_95 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_96_101 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(1 downto 0),
DIB(1 downto 0) => I127(3 downto 2),
DIC(1 downto 0) => I127(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_102_107: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(103 downto 102),
DIB(1 downto 0) => I127(105 downto 104),
DIC(1 downto 0) => I127(107 downto 106),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_102_107_n_0,
DOA(0) => RAM_reg_0_15_102_107_n_1,
DOB(1) => RAM_reg_0_15_102_107_n_2,
DOB(0) => RAM_reg_0_15_102_107_n_3,
DOC(1) => RAM_reg_0_15_102_107_n_4,
DOC(0) => RAM_reg_0_15_102_107_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_102_107_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_108_113: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(109 downto 108),
DIB(1 downto 0) => I127(111 downto 110),
DIC(1 downto 0) => I127(113 downto 112),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_108_113_n_0,
DOA(0) => RAM_reg_0_15_108_113_n_1,
DOB(1) => RAM_reg_0_15_108_113_n_2,
DOB(0) => RAM_reg_0_15_108_113_n_3,
DOC(1) => RAM_reg_0_15_108_113_n_4,
DOC(0) => RAM_reg_0_15_108_113_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_108_113_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_114_119: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(115 downto 114),
DIB(1 downto 0) => I127(117 downto 116),
DIC(1 downto 0) => I127(119 downto 118),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_114_119_n_0,
DOA(0) => RAM_reg_0_15_114_119_n_1,
DOB(1) => RAM_reg_0_15_114_119_n_2,
DOB(0) => RAM_reg_0_15_114_119_n_3,
DOC(1) => RAM_reg_0_15_114_119_n_4,
DOC(0) => RAM_reg_0_15_114_119_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_114_119_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_120_125: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(121 downto 120),
DIB(1 downto 0) => I127(123 downto 122),
DIC(1 downto 0) => I127(125 downto 124),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_120_125_n_0,
DOA(0) => RAM_reg_0_15_120_125_n_1,
DOB(1) => RAM_reg_0_15_120_125_n_2,
DOB(0) => RAM_reg_0_15_120_125_n_3,
DOC(1) => RAM_reg_0_15_120_125_n_4,
DOC(0) => RAM_reg_0_15_120_125_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_120_125_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_126_131: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(127 downto 126),
DIB(1 downto 0) => I127(129 downto 128),
DIC(1 downto 0) => I127(131 downto 130),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_126_131_n_0,
DOA(0) => RAM_reg_0_15_126_131_n_1,
DOB(1) => RAM_reg_0_15_126_131_n_2,
DOB(0) => RAM_reg_0_15_126_131_n_3,
DOC(1) => RAM_reg_0_15_126_131_n_4,
DOC(0) => RAM_reg_0_15_126_131_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_126_131_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(13 downto 12),
DIB(1 downto 0) => I127(15 downto 14),
DIC(1 downto 0) => I127(17 downto 16),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_12_17_n_0,
DOA(0) => RAM_reg_0_15_12_17_n_1,
DOB(1) => RAM_reg_0_15_12_17_n_2,
DOB(0) => RAM_reg_0_15_12_17_n_3,
DOC(1) => RAM_reg_0_15_12_17_n_4,
DOC(0) => RAM_reg_0_15_12_17_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(19 downto 18),
DIB(1 downto 0) => I127(21 downto 20),
DIC(1 downto 0) => I127(23 downto 22),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_18_23_n_0,
DOA(0) => RAM_reg_0_15_18_23_n_1,
DOB(1) => RAM_reg_0_15_18_23_n_2,
DOB(0) => RAM_reg_0_15_18_23_n_3,
DOC(1) => RAM_reg_0_15_18_23_n_4,
DOC(0) => RAM_reg_0_15_18_23_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(25 downto 24),
DIB(1 downto 0) => I127(27 downto 26),
DIC(1 downto 0) => I127(29 downto 28),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_24_29_n_0,
DOA(0) => RAM_reg_0_15_24_29_n_1,
DOB(1) => RAM_reg_0_15_24_29_n_2,
DOB(0) => RAM_reg_0_15_24_29_n_3,
DOC(1) => RAM_reg_0_15_24_29_n_4,
DOC(0) => RAM_reg_0_15_24_29_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_30_35: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(31 downto 30),
DIB(1 downto 0) => I127(33 downto 32),
DIC(1 downto 0) => I127(35 downto 34),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_30_35_n_0,
DOA(0) => RAM_reg_0_15_30_35_n_1,
DOB(1) => RAM_reg_0_15_30_35_n_2,
DOB(0) => RAM_reg_0_15_30_35_n_3,
DOC(1) => RAM_reg_0_15_30_35_n_4,
DOC(0) => RAM_reg_0_15_30_35_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_36_41: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(37 downto 36),
DIB(1 downto 0) => I127(39 downto 38),
DIC(1 downto 0) => I127(41 downto 40),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_36_41_n_0,
DOA(0) => RAM_reg_0_15_36_41_n_1,
DOB(1) => RAM_reg_0_15_36_41_n_2,
DOB(0) => RAM_reg_0_15_36_41_n_3,
DOC(1) => RAM_reg_0_15_36_41_n_4,
DOC(0) => RAM_reg_0_15_36_41_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_42_47: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(43 downto 42),
DIB(1 downto 0) => I127(45 downto 44),
DIC(1 downto 0) => I127(47 downto 46),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_42_47_n_0,
DOA(0) => RAM_reg_0_15_42_47_n_1,
DOB(1) => RAM_reg_0_15_42_47_n_2,
DOB(0) => RAM_reg_0_15_42_47_n_3,
DOC(1) => RAM_reg_0_15_42_47_n_4,
DOC(0) => RAM_reg_0_15_42_47_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_48_53: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(49 downto 48),
DIB(1 downto 0) => I127(51 downto 50),
DIC(1 downto 0) => I127(53 downto 52),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_48_53_n_0,
DOA(0) => RAM_reg_0_15_48_53_n_1,
DOB(1) => RAM_reg_0_15_48_53_n_2,
DOB(0) => RAM_reg_0_15_48_53_n_3,
DOC(1) => RAM_reg_0_15_48_53_n_4,
DOC(0) => RAM_reg_0_15_48_53_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_54_59: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(55 downto 54),
DIB(1 downto 0) => I127(57 downto 56),
DIC(1 downto 0) => I127(59 downto 58),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_54_59_n_0,
DOA(0) => RAM_reg_0_15_54_59_n_1,
DOB(1) => RAM_reg_0_15_54_59_n_2,
DOB(0) => RAM_reg_0_15_54_59_n_3,
DOC(1) => RAM_reg_0_15_54_59_n_4,
DOC(0) => RAM_reg_0_15_54_59_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_60_65: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(61 downto 60),
DIB(1 downto 0) => I127(63 downto 62),
DIC(1 downto 0) => I127(65 downto 64),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_60_65_n_0,
DOA(0) => RAM_reg_0_15_60_65_n_1,
DOB(1) => RAM_reg_0_15_60_65_n_2,
DOB(0) => RAM_reg_0_15_60_65_n_3,
DOC(1) => RAM_reg_0_15_60_65_n_4,
DOC(0) => RAM_reg_0_15_60_65_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_60_65_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_66_71: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(67 downto 66),
DIB(1 downto 0) => I127(69 downto 68),
DIC(1 downto 0) => I127(71 downto 70),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_66_71_n_0,
DOA(0) => RAM_reg_0_15_66_71_n_1,
DOB(1) => RAM_reg_0_15_66_71_n_2,
DOB(0) => RAM_reg_0_15_66_71_n_3,
DOC(1) => RAM_reg_0_15_66_71_n_4,
DOC(0) => RAM_reg_0_15_66_71_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_66_71_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(7 downto 6),
DIB(1 downto 0) => I127(9 downto 8),
DIC(1 downto 0) => I127(11 downto 10),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_6_11_n_0,
DOA(0) => RAM_reg_0_15_6_11_n_1,
DOB(1) => RAM_reg_0_15_6_11_n_2,
DOB(0) => RAM_reg_0_15_6_11_n_3,
DOC(1) => RAM_reg_0_15_6_11_n_4,
DOC(0) => RAM_reg_0_15_6_11_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_72_77: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(73 downto 72),
DIB(1 downto 0) => I127(75 downto 74),
DIC(1 downto 0) => I127(77 downto 76),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_72_77_n_0,
DOA(0) => RAM_reg_0_15_72_77_n_1,
DOB(1) => RAM_reg_0_15_72_77_n_2,
DOB(0) => RAM_reg_0_15_72_77_n_3,
DOC(1) => RAM_reg_0_15_72_77_n_4,
DOC(0) => RAM_reg_0_15_72_77_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_72_77_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_78_83: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(79 downto 78),
DIB(1 downto 0) => I127(81 downto 80),
DIC(1 downto 0) => I127(83 downto 82),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_78_83_n_0,
DOA(0) => RAM_reg_0_15_78_83_n_1,
DOB(1) => RAM_reg_0_15_78_83_n_2,
DOB(0) => RAM_reg_0_15_78_83_n_3,
DOC(1) => RAM_reg_0_15_78_83_n_4,
DOC(0) => RAM_reg_0_15_78_83_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_78_83_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_84_89: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(85 downto 84),
DIB(1 downto 0) => I127(87 downto 86),
DIC(1 downto 0) => I127(89 downto 88),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_84_89_n_0,
DOA(0) => RAM_reg_0_15_84_89_n_1,
DOB(1) => RAM_reg_0_15_84_89_n_2,
DOB(0) => RAM_reg_0_15_84_89_n_3,
DOC(1) => RAM_reg_0_15_84_89_n_4,
DOC(0) => RAM_reg_0_15_84_89_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_84_89_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_90_95: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(91 downto 90),
DIB(1 downto 0) => I127(93 downto 92),
DIC(1 downto 0) => I127(95 downto 94),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_90_95_n_0,
DOA(0) => RAM_reg_0_15_90_95_n_1,
DOB(1) => RAM_reg_0_15_90_95_n_2,
DOB(0) => RAM_reg_0_15_90_95_n_3,
DOC(1) => RAM_reg_0_15_90_95_n_4,
DOC(0) => RAM_reg_0_15_90_95_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_90_95_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_96_101: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(97 downto 96),
DIB(1 downto 0) => I127(99 downto 98),
DIC(1 downto 0) => I127(101 downto 100),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_96_101_n_0,
DOA(0) => RAM_reg_0_15_96_101_n_1,
DOB(1) => RAM_reg_0_15_96_101_n_2,
DOB(0) => RAM_reg_0_15_96_101_n_3,
DOC(1) => RAM_reg_0_15_96_101_n_4,
DOC(0) => RAM_reg_0_15_96_101_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_96_101_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_1,
Q => Q(0),
R => '0'
);
\gpr1.dout_i_reg[100]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_96_101_n_5,
Q => Q(100),
R => '0'
);
\gpr1.dout_i_reg[101]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_96_101_n_4,
Q => Q(101),
R => '0'
);
\gpr1.dout_i_reg[102]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_102_107_n_1,
Q => Q(102),
R => '0'
);
\gpr1.dout_i_reg[103]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_102_107_n_0,
Q => Q(103),
R => '0'
);
\gpr1.dout_i_reg[104]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_102_107_n_3,
Q => Q(104),
R => '0'
);
\gpr1.dout_i_reg[105]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_102_107_n_2,
Q => Q(105),
R => '0'
);
\gpr1.dout_i_reg[106]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_102_107_n_5,
Q => Q(106),
R => '0'
);
\gpr1.dout_i_reg[107]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_102_107_n_4,
Q => Q(107),
R => '0'
);
\gpr1.dout_i_reg[108]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_108_113_n_1,
Q => Q(108),
R => '0'
);
\gpr1.dout_i_reg[109]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_108_113_n_0,
Q => Q(109),
R => '0'
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_5,
Q => Q(10),
R => '0'
);
\gpr1.dout_i_reg[110]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_108_113_n_3,
Q => Q(110),
R => '0'
);
\gpr1.dout_i_reg[111]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_108_113_n_2,
Q => Q(111),
R => '0'
);
\gpr1.dout_i_reg[112]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_108_113_n_5,
Q => Q(112),
R => '0'
);
\gpr1.dout_i_reg[113]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_108_113_n_4,
Q => Q(113),
R => '0'
);
\gpr1.dout_i_reg[114]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_114_119_n_1,
Q => Q(114),
R => '0'
);
\gpr1.dout_i_reg[115]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_114_119_n_0,
Q => Q(115),
R => '0'
);
\gpr1.dout_i_reg[116]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_114_119_n_3,
Q => Q(116),
R => '0'
);
\gpr1.dout_i_reg[117]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_114_119_n_2,
Q => Q(117),
R => '0'
);
\gpr1.dout_i_reg[118]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_114_119_n_5,
Q => Q(118),
R => '0'
);
\gpr1.dout_i_reg[119]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_114_119_n_4,
Q => Q(119),
R => '0'
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_4,
Q => Q(11),
R => '0'
);
\gpr1.dout_i_reg[120]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_120_125_n_1,
Q => Q(120),
R => '0'
);
\gpr1.dout_i_reg[121]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_120_125_n_0,
Q => Q(121),
R => '0'
);
\gpr1.dout_i_reg[122]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_120_125_n_3,
Q => Q(122),
R => '0'
);
\gpr1.dout_i_reg[123]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_120_125_n_2,
Q => Q(123),
R => '0'
);
\gpr1.dout_i_reg[124]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_120_125_n_5,
Q => Q(124),
R => '0'
);
\gpr1.dout_i_reg[125]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_120_125_n_4,
Q => Q(125),
R => '0'
);
\gpr1.dout_i_reg[126]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_126_131_n_1,
Q => Q(126),
R => '0'
);
\gpr1.dout_i_reg[127]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_126_131_n_0,
Q => Q(127),
R => '0'
);
\gpr1.dout_i_reg[128]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_126_131_n_3,
Q => Q(128),
R => '0'
);
\gpr1.dout_i_reg[129]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_126_131_n_2,
Q => Q(129),
R => '0'
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_1,
Q => Q(12),
R => '0'
);
\gpr1.dout_i_reg[130]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_126_131_n_5,
Q => Q(130),
R => '0'
);
\gpr1.dout_i_reg[131]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_126_131_n_4,
Q => Q(131),
R => '0'
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_0,
Q => Q(13),
R => '0'
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_3,
Q => Q(14),
R => '0'
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_2,
Q => Q(15),
R => '0'
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_5,
Q => Q(16),
R => '0'
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_4,
Q => Q(17),
R => '0'
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_1,
Q => Q(18),
R => '0'
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_0,
Q => Q(19),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_0,
Q => Q(1),
R => '0'
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_3,
Q => Q(20),
R => '0'
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_2,
Q => Q(21),
R => '0'
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_5,
Q => Q(22),
R => '0'
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_4,
Q => Q(23),
R => '0'
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_1,
Q => Q(24),
R => '0'
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_0,
Q => Q(25),
R => '0'
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_3,
Q => Q(26),
R => '0'
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_2,
Q => Q(27),
R => '0'
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_5,
Q => Q(28),
R => '0'
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_4,
Q => Q(29),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_3,
Q => Q(2),
R => '0'
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_1,
Q => Q(30),
R => '0'
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_0,
Q => Q(31),
R => '0'
);
\gpr1.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_3,
Q => Q(32),
R => '0'
);
\gpr1.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_2,
Q => Q(33),
R => '0'
);
\gpr1.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_5,
Q => Q(34),
R => '0'
);
\gpr1.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_4,
Q => Q(35),
R => '0'
);
\gpr1.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_1,
Q => Q(36),
R => '0'
);
\gpr1.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_0,
Q => Q(37),
R => '0'
);
\gpr1.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_3,
Q => Q(38),
R => '0'
);
\gpr1.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_2,
Q => Q(39),
R => '0'
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_2,
Q => Q(3),
R => '0'
);
\gpr1.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_5,
Q => Q(40),
R => '0'
);
\gpr1.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_4,
Q => Q(41),
R => '0'
);
\gpr1.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_1,
Q => Q(42),
R => '0'
);
\gpr1.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_0,
Q => Q(43),
R => '0'
);
\gpr1.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_3,
Q => Q(44),
R => '0'
);
\gpr1.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_2,
Q => Q(45),
R => '0'
);
\gpr1.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_5,
Q => Q(46),
R => '0'
);
\gpr1.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_4,
Q => Q(47),
R => '0'
);
\gpr1.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_1,
Q => Q(48),
R => '0'
);
\gpr1.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_0,
Q => Q(49),
R => '0'
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_5,
Q => Q(4),
R => '0'
);
\gpr1.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_3,
Q => Q(50),
R => '0'
);
\gpr1.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_2,
Q => Q(51),
R => '0'
);
\gpr1.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_5,
Q => Q(52),
R => '0'
);
\gpr1.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_4,
Q => Q(53),
R => '0'
);
\gpr1.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_1,
Q => Q(54),
R => '0'
);
\gpr1.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_0,
Q => Q(55),
R => '0'
);
\gpr1.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_3,
Q => Q(56),
R => '0'
);
\gpr1.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_2,
Q => Q(57),
R => '0'
);
\gpr1.dout_i_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_5,
Q => Q(58),
R => '0'
);
\gpr1.dout_i_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_4,
Q => Q(59),
R => '0'
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_4,
Q => Q(5),
R => '0'
);
\gpr1.dout_i_reg[60]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_65_n_1,
Q => Q(60),
R => '0'
);
\gpr1.dout_i_reg[61]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_65_n_0,
Q => Q(61),
R => '0'
);
\gpr1.dout_i_reg[62]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_65_n_3,
Q => Q(62),
R => '0'
);
\gpr1.dout_i_reg[63]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_65_n_2,
Q => Q(63),
R => '0'
);
\gpr1.dout_i_reg[64]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_65_n_5,
Q => Q(64),
R => '0'
);
\gpr1.dout_i_reg[65]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_65_n_4,
Q => Q(65),
R => '0'
);
\gpr1.dout_i_reg[66]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_66_71_n_1,
Q => Q(66),
R => '0'
);
\gpr1.dout_i_reg[67]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_66_71_n_0,
Q => Q(67),
R => '0'
);
\gpr1.dout_i_reg[68]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_66_71_n_3,
Q => Q(68),
R => '0'
);
\gpr1.dout_i_reg[69]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_66_71_n_2,
Q => Q(69),
R => '0'
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_1,
Q => Q(6),
R => '0'
);
\gpr1.dout_i_reg[70]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_66_71_n_5,
Q => Q(70),
R => '0'
);
\gpr1.dout_i_reg[71]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_66_71_n_4,
Q => Q(71),
R => '0'
);
\gpr1.dout_i_reg[72]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_72_77_n_1,
Q => Q(72),
R => '0'
);
\gpr1.dout_i_reg[73]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_72_77_n_0,
Q => Q(73),
R => '0'
);
\gpr1.dout_i_reg[74]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_72_77_n_3,
Q => Q(74),
R => '0'
);
\gpr1.dout_i_reg[75]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_72_77_n_2,
Q => Q(75),
R => '0'
);
\gpr1.dout_i_reg[76]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_72_77_n_5,
Q => Q(76),
R => '0'
);
\gpr1.dout_i_reg[77]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_72_77_n_4,
Q => Q(77),
R => '0'
);
\gpr1.dout_i_reg[78]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_78_83_n_1,
Q => Q(78),
R => '0'
);
\gpr1.dout_i_reg[79]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_78_83_n_0,
Q => Q(79),
R => '0'
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_0,
Q => Q(7),
R => '0'
);
\gpr1.dout_i_reg[80]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_78_83_n_3,
Q => Q(80),
R => '0'
);
\gpr1.dout_i_reg[81]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_78_83_n_2,
Q => Q(81),
R => '0'
);
\gpr1.dout_i_reg[82]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_78_83_n_5,
Q => Q(82),
R => '0'
);
\gpr1.dout_i_reg[83]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_78_83_n_4,
Q => Q(83),
R => '0'
);
\gpr1.dout_i_reg[84]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_84_89_n_1,
Q => Q(84),
R => '0'
);
\gpr1.dout_i_reg[85]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_84_89_n_0,
Q => Q(85),
R => '0'
);
\gpr1.dout_i_reg[86]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_84_89_n_3,
Q => Q(86),
R => '0'
);
\gpr1.dout_i_reg[87]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_84_89_n_2,
Q => Q(87),
R => '0'
);
\gpr1.dout_i_reg[88]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_84_89_n_5,
Q => Q(88),
R => '0'
);
\gpr1.dout_i_reg[89]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_84_89_n_4,
Q => Q(89),
R => '0'
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_3,
Q => Q(8),
R => '0'
);
\gpr1.dout_i_reg[90]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_90_95_n_1,
Q => Q(90),
R => '0'
);
\gpr1.dout_i_reg[91]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_90_95_n_0,
Q => Q(91),
R => '0'
);
\gpr1.dout_i_reg[92]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_90_95_n_3,
Q => Q(92),
R => '0'
);
\gpr1.dout_i_reg[93]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_90_95_n_2,
Q => Q(93),
R => '0'
);
\gpr1.dout_i_reg[94]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_90_95_n_5,
Q => Q(94),
R => '0'
);
\gpr1.dout_i_reg[95]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_90_95_n_4,
Q => Q(95),
R => '0'
);
\gpr1.dout_i_reg[96]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_96_101_n_1,
Q => Q(96),
R => '0'
);
\gpr1.dout_i_reg[97]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_96_101_n_0,
Q => Q(97),
R => '0'
);
\gpr1.dout_i_reg[98]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_96_101_n_3,
Q => Q(98),
R => '0'
);
\gpr1.dout_i_reg[99]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_96_101_n_2,
Q => Q(99),
R => '0'
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_2,
Q => Q(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_bin_cntr : entity is "rd_bin_cntr";
end system_auto_cc_0_rd_bin_cntr;
architecture STRUCTURE of system_auto_cc_0_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__6\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ram_empty_i_i_2__2_n_0\ : STD_LOGIC;
signal \ram_empty_i_i_3__2_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1__2\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1__2\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1__2\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1__2\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \ram_empty_i_i_2__2\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \ram_empty_i_i_3__2\ : label is "soft_lutpair27";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1__2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__6\(0)
);
\gc0.count[1]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__6\(1)
);
\gc0.count[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__6\(2)
);
\gc0.count[3]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__6\(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \plusOp__6\(0),
PRE => AR(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__6\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__6\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__6\(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => D(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => D(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => D(2)
);
\ram_empty_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \ram_empty_i_i_2__2_n_0\,
I1 => \ram_empty_i_i_3__2_n_0\,
I2 => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\,
O => ram_empty_i_reg
);
\ram_empty_i_i_2__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(2),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
O => \ram_empty_i_i_2__2_n_0\
);
\ram_empty_i_i_3__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(1),
O => \ram_empty_i_i_3__2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_bin_cntr_20 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_bin_cntr_20 : entity is "rd_bin_cntr";
end system_auto_cc_0_rd_bin_cntr_20;
architecture STRUCTURE of system_auto_cc_0_rd_bin_cntr_20 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ram_empty_i_i_2__0_n_0\ : STD_LOGIC;
signal \ram_empty_i_i_3__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \ram_empty_i_i_2__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \ram_empty_i_i_3__0\ : label is "soft_lutpair21";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gc0.count[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__0\(1)
);
\gc0.count[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__0\(2)
);
\gc0.count[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__0\(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \plusOp__0\(0),
PRE => \out\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__0\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__0\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__0\(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => D(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => D(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => D(2)
);
\ram_empty_i_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \ram_empty_i_i_2__0_n_0\,
I1 => \ram_empty_i_i_3__0_n_0\,
I2 => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\,
O => ram_empty_i_reg
);
\ram_empty_i_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(2),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
O => \ram_empty_i_i_2__0_n_0\
);
\ram_empty_i_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(1),
O => \ram_empty_i_i_3__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_bin_cntr_41 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
\gnxpm_cdc.rd_pntr_gc_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_bin_cntr_41 : entity is "rd_bin_cntr";
end system_auto_cc_0_rd_bin_cntr_41;
architecture STRUCTURE of system_auto_cc_0_rd_bin_cntr_41 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_empty_i_i_2_n_0 : STD_LOGIC;
signal ram_empty_i_i_3_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of ram_empty_i_i_2 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of ram_empty_i_i_3 : label is "soft_lutpair15";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => plusOp(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => plusOp(0),
PRE => \out\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => plusOp(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(2)
);
ram_empty_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => ram_empty_i_i_2_n_0,
I1 => ram_empty_i_i_3_n_0,
I2 => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\,
O => ram_empty_i_reg
);
ram_empty_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(2),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
O => ram_empty_i_i_2_n_0
);
ram_empty_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(1),
O => ram_empty_i_i_3_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_bin_cntr_62 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_bin_cntr_62 : entity is "rd_bin_cntr";
end system_auto_cc_0_rd_bin_cntr_62;
architecture STRUCTURE of system_auto_cc_0_rd_bin_cntr_62 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__8\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ram_empty_i_i_2__3_n_0\ : STD_LOGIC;
signal \ram_empty_i_i_3__3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1__3\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1__3\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1__3\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1__3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \ram_empty_i_i_2__3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \ram_empty_i_i_3__3\ : label is "soft_lutpair9";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__8\(0)
);
\gc0.count[1]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__8\(1)
);
\gc0.count[2]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__8\(2)
);
\gc0.count[3]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__8\(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \plusOp__8\(0),
PRE => \out\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__8\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__8\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__8\(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => D(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => D(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => D(2)
);
\ram_empty_i_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \ram_empty_i_i_2__3_n_0\,
I1 => \ram_empty_i_i_3__3_n_0\,
I2 => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\,
O => ram_empty_i_reg
);
\ram_empty_i_i_2__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(2),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
O => \ram_empty_i_i_2__3_n_0\
);
\ram_empty_i_i_3__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(1),
O => \ram_empty_i_i_3__3_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_bin_cntr_86 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_bin_cntr_86 : entity is "rd_bin_cntr";
end system_auto_cc_0_rd_bin_cntr_86;
architecture STRUCTURE of system_auto_cc_0_rd_bin_cntr_86 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ram_empty_i_i_2__1_n_0\ : STD_LOGIC;
signal \ram_empty_i_i_3__1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1__1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1__1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1__1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1__1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \ram_empty_i_i_2__1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \ram_empty_i_i_3__1\ : label is "soft_lutpair3";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__2\(0)
);
\gc0.count[1]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__2\(1)
);
\gc0.count[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__2\(2)
);
\gc0.count[3]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__2\(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \plusOp__2\(0),
PRE => \out\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__2\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__2\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__2\(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => D(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => D(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => D(2)
);
\ram_empty_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \ram_empty_i_i_2__1_n_0\,
I1 => \ram_empty_i_i_3__1_n_0\,
I2 => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\,
O => ram_empty_i_reg
);
\ram_empty_i_i_2__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(2),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
O => \ram_empty_i_i_2__1_n_0\
);
\ram_empty_i_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(1),
O => \ram_empty_i_i_3__1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_fwft is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_fwft : entity is "rd_fwft";
end system_auto_cc_0_rd_fwft;
architecture STRUCTURE of system_auto_cc_0_rd_fwft is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
\out\(1 downto 0) <= curr_fwft_state(1 downto 0);
\aempty_fwft_fb_i_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => s_axi_bready,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => AR(0),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => AR(0),
Q => aempty_fwft_i
);
\empty_fwft_fb_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_bready,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => AR(0),
Q => empty_fwft_fb_i
);
\empty_fwft_fb_o_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_bready,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => AR(0),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => AR(0),
Q => empty_fwft_i
);
\gc0.count_d1[3]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_bready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => E(0)
);
\gpregsm1.curr_fwft_state[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => s_axi_bready,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_bready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => next_fwft_state(0),
Q => user_valid
);
\ram_empty_i_i_5__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF0000000000DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_bready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
I4 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I5 => Q(0),
O => ram_empty_i_reg
);
s_axi_bvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => empty_fwft_i,
O => s_axi_bvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_fwft_18 is
port (
ram_empty_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[144]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_fwft_18 : entity is "rd_fwft";
end system_auto_cc_0_rd_fwft_18;
architecture STRUCTURE of system_auto_cc_0_rd_fwft_18 is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
\aempty_fwft_fb_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => m_axi_wready,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_i
);
\empty_fwft_fb_i_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_wready,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_fb_i
);
\empty_fwft_fb_o_i_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_wready,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \out\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_i
);
\gc0.count_d1[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_wready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => E(0)
);
\goreg_dm.dout_i[144]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => \out\(0),
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_wready,
O => \goreg_dm.dout_i_reg[144]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => m_axi_wready,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_wready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => user_valid
);
m_axi_wvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => empty_fwft_i,
O => m_axi_wvalid
);
\ram_empty_i_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF0000000000DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_wready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
I4 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I5 => Q(0),
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_fwft_39 is
port (
ram_empty_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[57]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_fwft_39 : entity is "rd_fwft";
end system_auto_cc_0_rd_fwft_39;
architecture STRUCTURE of system_auto_cc_0_rd_fwft_39 is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
aempty_fwft_fb_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => m_axi_awready,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_i
);
empty_fwft_fb_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_awready,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_fb_i
);
empty_fwft_fb_o_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_awready,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \out\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_i
);
\gc0.count_d1[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_awready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => E(0)
);
\goreg_dm.dout_i[57]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => \out\(0),
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_awready,
O => \goreg_dm.dout_i_reg[57]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => m_axi_awready,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_awready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => user_valid
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => empty_fwft_i,
O => m_axi_awvalid
);
ram_empty_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF0000000000DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_awready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
I4 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I5 => Q(0),
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_fwft_60 is
port (
ram_empty_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[131]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_fwft_60 : entity is "rd_fwft";
end system_auto_cc_0_rd_fwft_60;
architecture STRUCTURE of system_auto_cc_0_rd_fwft_60 is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
\aempty_fwft_fb_i_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => s_axi_rready,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_i
);
\empty_fwft_fb_i_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_rready,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_fb_i
);
\empty_fwft_fb_o_i_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_rready,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \out\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_i
);
\gc0.count_d1[3]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_rready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => E(0)
);
\goreg_dm.dout_i[131]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => \out\(0),
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_rready,
O => \goreg_dm.dout_i_reg[131]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => s_axi_rready,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_rready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => user_valid
);
\ram_empty_i_i_5__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF0000000000DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_rready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
I4 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I5 => Q(0),
O => ram_empty_i_reg
);
s_axi_rvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => empty_fwft_i,
O => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_fwft_84 is
port (
ram_empty_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[57]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_fwft_84 : entity is "rd_fwft";
end system_auto_cc_0_rd_fwft_84;
architecture STRUCTURE of system_auto_cc_0_rd_fwft_84 is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
\aempty_fwft_fb_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => m_axi_arready,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_i
);
\empty_fwft_fb_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_arready,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_fb_i
);
\empty_fwft_fb_o_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_arready,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \out\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_i
);
\gc0.count_d1[3]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_arready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => E(0)
);
\goreg_dm.dout_i[57]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => \out\(0),
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_arready,
O => \goreg_dm.dout_i_reg[57]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => m_axi_arready,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_arready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => user_valid
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => empty_fwft_i,
O => m_axi_arvalid
);
\ram_empty_i_i_5__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF0000000000DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_arready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
I4 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I5 => Q(0),
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_status_flags_as is
port (
\out\ : out STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_status_flags_as : entity is "rd_status_flags_as";
end system_auto_cc_0_rd_status_flags_as;
architecture STRUCTURE of system_auto_cc_0_rd_status_flags_as is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => AR(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => AR(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_status_flags_as_19 is
port (
\out\ : out STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_status_flags_as_19 : entity is "rd_status_flags_as";
end system_auto_cc_0_rd_status_flags_as_19;
architecture STRUCTURE of system_auto_cc_0_rd_status_flags_as_19 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_status_flags_as_40 is
port (
\out\ : out STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_status_flags_as_40 : entity is "rd_status_flags_as";
end system_auto_cc_0_rd_status_flags_as_40;
architecture STRUCTURE of system_auto_cc_0_rd_status_flags_as_40 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_status_flags_as_61 is
port (
\out\ : out STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_status_flags_as_61 : entity is "rd_status_flags_as";
end system_auto_cc_0_rd_status_flags_as_61;
architecture STRUCTURE of system_auto_cc_0_rd_status_flags_as_61 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_status_flags_as_85 is
port (
\out\ : out STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_status_flags_as_85 : entity is "rd_status_flags_as";
end system_auto_cc_0_rd_status_flags_as_85;
architecture STRUCTURE of system_auto_cc_0_rd_status_flags_as_85 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_1 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_1 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_1;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_10 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_10 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_10;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_10 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_11 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_11 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_11;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_11 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_12 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_12 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_12;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_12 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_13 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_13 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_13;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_13 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_14 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_14 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_14;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_14 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_15 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_15 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_15;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_15 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_2 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_2 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_2;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_3 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_3 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_3;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_3 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_31 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_31 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_31;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_31 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_32 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_32 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_32;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_32 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_33 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_33 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_33;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_33 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_34 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_34 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_34;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_34 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_35 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_35 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_35;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_35 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_36 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_36 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_36;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_36 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_4 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_4 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_4;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_4 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_5 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_5 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_5;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_5 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_52 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_52 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_52;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_52 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_53 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_53 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_53;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_53 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_54 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_54 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_54;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_54 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_55 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_55 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_55;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_55 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_56 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_56 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_56;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_56 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_57 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_57 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_57;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_57 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_75 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_75 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_75;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_75 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_76 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_76 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_76;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_76 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_77 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_77 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_77;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_77 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_78 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_78 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_78;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_78 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_79 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_79 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_79;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_79 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_synchronizer_ff_80 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_synchronizer_ff_80 : entity is "synchronizer_ff";
end system_auto_cc_0_synchronizer_ff_80;
architecture STRUCTURE of system_auto_cc_0_synchronizer_ff_80 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized0\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized0\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized0\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized0\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized0_21\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized0_21\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized0_21\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized0_21\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized0_42\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized0_42\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized0_42\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized0_42\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized0_63\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized0_63\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized0_63\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized0_63\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized0_87\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized0_87\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized0_87\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized0_87\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized1\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized1\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized1\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized1\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized1_22\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized1_22\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized1_22\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized1_22\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized1_43\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized1_43\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized1_43\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized1_43\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized1_64\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized1_64\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized1_64\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized1_64\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized1_88\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized1_88\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized1_88\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized1_88\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized2\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized2\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized2\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized2\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized2_23\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized2_23\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized2_23\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized2_23\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized2_44\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized2_44\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized2_44\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized2_44\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized2_65\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized2_65\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized2_65\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized2_65\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized2_89\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized2_89\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized2_89\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized2_89\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized3\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized3\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized3\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized3\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized3_24\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized3_24\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized3_24\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized3_24\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized3_45\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized3_45\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized3_45\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized3_45\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized3_66\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized3_66\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized3_66\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized3_66\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized3_90\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized3_90\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized3_90\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized3_90\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized4\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized4\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized4\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized4\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized4_25\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized4_25\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized4_25\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized4_25\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized4_46\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized4_46\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized4_46\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized4_46\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized4_67\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized4_67\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized4_67\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized4_67\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized4_91\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized4_91\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized4_91\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized4_91\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized5\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized5\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized5\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized5\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized5_26\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized5_26\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized5_26\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized5_26\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized5_47\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized5_47\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized5_47\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized5_47\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized5_68\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized5_68\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized5_68\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized5_68\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_synchronizer_ff__parameterized5_92\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_synchronizer_ff__parameterized5_92\ : entity is "synchronizer_ff";
end \system_auto_cc_0_synchronizer_ff__parameterized5_92\;
architecture STRUCTURE of \system_auto_cc_0_synchronizer_ff__parameterized5_92\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_bin_cntr : entity is "wr_bin_cntr";
end system_auto_cc_0_wr_bin_cntr;
architecture STRUCTURE of system_auto_cc_0_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gic0.gc0.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair29";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) <= \^gic0.gc0.count_d2_reg[3]_0\(3 downto 0);
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__1\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__1\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__1\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__1\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gic0.gc0.count_d2_reg[3]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[3]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[3]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[3]_0\(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \plusOp__1\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_bin_cntr_17 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_bin_cntr_17 : entity is "wr_bin_cntr";
end system_auto_cc_0_wr_bin_cntr_17;
architecture STRUCTURE of system_auto_cc_0_wr_bin_cntr_17 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gic0.gc0.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__5\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1__2\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1__2\ : label is "soft_lutpair23";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) <= \^gic0.gc0.count_d2_reg[3]_0\(3 downto 0);
\gic0.gc0.count[0]_i_1__2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__5\(0)
);
\gic0.gc0.count[1]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__5\(1)
);
\gic0.gc0.count[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__5\(2)
);
\gic0.gc0.count[3]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__5\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gic0.gc0.count_d2_reg[3]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[3]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[3]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[3]_0\(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__5\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \plusOp__5\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__5\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__5\(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_bin_cntr_38 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_bin_cntr_38 : entity is "wr_bin_cntr";
end system_auto_cc_0_wr_bin_cntr_38;
architecture STRUCTURE of system_auto_cc_0_wr_bin_cntr_38 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gic0.gc0.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__4\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1__1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1__1\ : label is "soft_lutpair17";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) <= \^gic0.gc0.count_d2_reg[3]_0\(3 downto 0);
\gic0.gc0.count[0]_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__4\(0)
);
\gic0.gc0.count[1]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__4\(1)
);
\gic0.gc0.count[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__4\(2)
);
\gic0.gc0.count[3]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__4\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gic0.gc0.count_d2_reg[3]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[3]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[3]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[3]_0\(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__4\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \plusOp__4\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__4\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__4\(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_bin_cntr_59 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_bin_cntr_59 : entity is "wr_bin_cntr";
end system_auto_cc_0_wr_bin_cntr_59;
architecture STRUCTURE of system_auto_cc_0_wr_bin_cntr_59 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gic0.gc0.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1__0\ : label is "soft_lutpair11";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) <= \^gic0.gc0.count_d2_reg[3]_0\(3 downto 0);
\gic0.gc0.count[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__3\(0)
);
\gic0.gc0.count[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__3\(1)
);
\gic0.gc0.count[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__3\(2)
);
\gic0.gc0.count[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__3\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gic0.gc0.count_d2_reg[3]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[3]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[3]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[3]_0\(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__3\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \plusOp__3\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__3\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__3\(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_bin_cntr_83 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_bin_cntr_83 : entity is "wr_bin_cntr";
end system_auto_cc_0_wr_bin_cntr_83;
architecture STRUCTURE of system_auto_cc_0_wr_bin_cntr_83 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gic0.gc0.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__7\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1__3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1__3\ : label is "soft_lutpair5";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) <= \^gic0.gc0.count_d2_reg[3]_0\(3 downto 0);
\gic0.gc0.count[0]_i_1__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__7\(0)
);
\gic0.gc0.count[1]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__7\(1)
);
\gic0.gc0.count[2]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__7\(2)
);
\gic0.gc0.count[3]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__7\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gic0.gc0.count_d2_reg[3]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[3]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[3]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[3]_0\(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__7\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \plusOp__7\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__7\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__7\(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_status_flags_as is
port (
ram_full_fb_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_status_flags_as : entity is "wr_status_flags_as";
end system_auto_cc_0_wr_status_flags_as;
architecture STRUCTURE of system_auto_cc_0_wr_status_flags_as is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc0.count_d1[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => m_axi_bvalid,
I1 => ram_full_fb_i,
O => E(0)
);
m_axi_bready_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ram_full_i,
O => m_axi_bready
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_fb_i
);
ram_full_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"4004"
)
port map (
I0 => ram_full_fb_i,
I1 => m_axi_bvalid,
I2 => Q(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_fb_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_status_flags_as_16 is
port (
ram_full_fb_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_status_flags_as_16 : entity is "wr_status_flags_as";
end system_auto_cc_0_wr_status_flags_as_16;
architecture STRUCTURE of system_auto_cc_0_wr_status_flags_as_16 is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc0.count_d1[3]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wvalid,
I1 => ram_full_fb_i,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_fb_i
);
\ram_full_i_i_3__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4004"
)
port map (
I0 => ram_full_fb_i,
I1 => s_axi_wvalid,
I2 => Q(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_fb_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_i
);
s_axi_wready_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ram_full_i,
O => s_axi_wready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_status_flags_as_37 is
port (
ram_full_fb_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_status_flags_as_37 : entity is "wr_status_flags_as";
end system_auto_cc_0_wr_status_flags_as_37;
architecture STRUCTURE of system_auto_cc_0_wr_status_flags_as_37 is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc0.count_d1[3]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_awvalid,
I1 => ram_full_fb_i,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_fb_i
);
\ram_full_i_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4004"
)
port map (
I0 => ram_full_fb_i,
I1 => s_axi_awvalid,
I2 => Q(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_fb_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_i
);
s_axi_awready_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ram_full_i,
O => s_axi_awready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_status_flags_as_58 is
port (
ram_full_fb_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_status_flags_as_58 : entity is "wr_status_flags_as";
end system_auto_cc_0_wr_status_flags_as_58;
architecture STRUCTURE of system_auto_cc_0_wr_status_flags_as_58 is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc0.count_d1[3]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => m_axi_rvalid,
I1 => ram_full_fb_i,
O => E(0)
);
m_axi_rready_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ram_full_i,
O => m_axi_rready
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_fb_i
);
\ram_full_i_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"4004"
)
port map (
I0 => ram_full_fb_i,
I1 => m_axi_rvalid,
I2 => Q(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_fb_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_status_flags_as_82 is
port (
ram_full_fb_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_status_flags_as_82 : entity is "wr_status_flags_as";
end system_auto_cc_0_wr_status_flags_as_82;
architecture STRUCTURE of system_auto_cc_0_wr_status_flags_as_82 is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc0.count_d1[3]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_arvalid,
I1 => ram_full_fb_i,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_fb_i
);
\ram_full_i_i_3__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4004"
)
port map (
I0 => ram_full_fb_i,
I1 => s_axi_arvalid,
I2 => Q(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_fb_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_i
);
s_axi_arready_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ram_full_i,
O => s_axi_arready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_clk_x_pntrs is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg_1 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gic0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\Q_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_clk_x_pntrs : entity is "clk_x_pntrs";
end system_auto_cc_0_clk_x_pntrs;
architecture STRUCTURE of system_auto_cc_0_clk_x_pntrs is
signal \__0_n_0\ : STD_LOGIC;
signal \__1_n_0\ : STD_LOGIC;
signal \__2_n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_empty_i_reg_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal ram_full_i_i_2_n_0 : STD_LOGIC;
signal ram_full_i_i_4_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \__1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \__2\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[2]_i_1\ : label is "soft_lutpair25";
begin
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_empty_i_reg_0(3 downto 0) <= \^ram_empty_i_reg_0\(3 downto 0);
ram_full_fb_i_reg_0(0) <= \^ram_full_fb_i_reg_0\(0);
\__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => \__0_n_0\
);
\__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(3),
I3 => p_8_out(2),
O => \__1_n_0\
);
\__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_8_out(2),
I1 => p_8_out(1),
I2 => p_8_out(3),
O => \__2_n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized0\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized1\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\,
m_aclk => m_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized2\
port map (
D(3 downto 0) => p_5_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized3\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_6_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
m_aclk => m_aclk
);
\gnxpm_cdc.gsync_stage[3].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized4\
port map (
D(0) => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_5_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[3].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized5\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_6_out(3 downto 0),
m_aclk => m_aclk,
\out\(3 downto 0) => p_8_out(3 downto 0)
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \__1_n_0\,
Q => p_23_out(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \__2_n_0\,
Q => p_23_out(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
Q => p_23_out(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => p_8_out(3),
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[1]\(0),
Q => \^ram_empty_i_reg_0\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \__0_n_0\,
Q => \^ram_empty_i_reg_0\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
Q => \^ram_empty_i_reg_0\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => \^ram_empty_i_reg_0\(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\
);
\ram_empty_i_i_4__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^ram_empty_i_reg_0\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^ram_empty_i_reg_0\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^ram_empty_i_reg_0\(0),
O => ram_empty_i_reg
);
ram_full_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F88F00008888"
)
port map (
I0 => ram_full_i_i_2_n_0,
I1 => ram_full_fb_i_reg_1,
I2 => Q(3),
I3 => \^ram_full_fb_i_reg_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => ram_full_i_i_4_n_0,
O => ram_full_fb_i_reg
);
ram_full_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_reg[2]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_reg[2]\(1),
I4 => \gic0.gc0.count_reg[2]\(0),
I5 => p_23_out(0),
O => ram_full_i_i_2_n_0
);
ram_full_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => Q(2),
I2 => p_23_out(1),
I3 => Q(1),
I4 => Q(0),
I5 => p_23_out(0),
O => ram_full_i_i_4_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_clk_x_pntrs_27 is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg_1 : in STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gic0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_clk_x_pntrs_27 : entity is "clk_x_pntrs";
end system_auto_cc_0_clk_x_pntrs_27;
architecture STRUCTURE of system_auto_cc_0_clk_x_pntrs_27 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \__1_n_0\ : STD_LOGIC;
signal \__2_n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_0_out : STD_LOGIC;
signal p_23_out_1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \ram_full_i_i_2__1_n_0\ : STD_LOGIC;
signal \ram_full_i_i_4__1_n_0\ : STD_LOGIC;
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \__1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \__2\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[0]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair13";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_full_fb_i_reg_0(0) <= \^ram_full_fb_i_reg_0\(0);
\__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => gray2bin(1)
);
\__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(3),
I3 => p_8_out(2),
O => \__1_n_0\
);
\__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_8_out(2),
I1 => p_8_out(1),
I2 => p_8_out(3),
O => \__2_n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized0_42\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3 downto 0) => wr_pntr_gc(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized1_43\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3 downto 0) => rd_pntr_gc(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized2_44\
port map (
D(3 downto 0) => p_5_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized3_45\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_6_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[3].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized4_46\
port map (
D(0) => p_0_out,
\Q_reg_reg[3]_0\(3 downto 0) => p_5_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0)
);
\gnxpm_cdc.gsync_stage[3].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized5_47\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_6_out(3 downto 0),
\out\(3 downto 0) => p_8_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__1_n_0\,
Q => p_23_out_1(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__2_n_0\,
Q => p_23_out_1(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
Q => p_23_out_1(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => p_8_out(3),
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[2]\(0),
Q => rd_pntr_gc(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[2]\(1),
Q => rd_pntr_gc(1)
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[2]\(2),
Q => rd_pntr_gc(2)
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(0),
Q => rd_pntr_gc(3)
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \^q\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(1),
Q => \^q\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_out,
Q => \^q\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => \^q\(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => wr_pntr_gc(0)
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => wr_pntr_gc(1)
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => wr_pntr_gc(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => wr_pntr_gc(3)
);
ram_empty_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^q\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^q\(0),
O => ram_empty_i_reg
);
\ram_full_i_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F88F00008888"
)
port map (
I0 => \ram_full_i_i_2__1_n_0\,
I1 => ram_full_fb_i_reg_1,
I2 => \gic0.gc0.count_d1_reg[3]\(3),
I3 => \^ram_full_fb_i_reg_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => \ram_full_i_i_4__1_n_0\,
O => ram_full_fb_i_reg
);
\ram_full_i_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out_1(2),
I1 => \gic0.gc0.count_reg[2]\(2),
I2 => p_23_out_1(1),
I3 => \gic0.gc0.count_reg[2]\(1),
I4 => \gic0.gc0.count_reg[2]\(0),
I5 => p_23_out_1(0),
O => \ram_full_i_i_2__1_n_0\
);
\ram_full_i_i_4__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out_1(2),
I1 => \gic0.gc0.count_d1_reg[3]\(2),
I2 => p_23_out_1(1),
I3 => \gic0.gc0.count_d1_reg[3]\(1),
I4 => \gic0.gc0.count_d1_reg[3]\(0),
I5 => p_23_out_1(0),
O => \ram_full_i_i_4__1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_clk_x_pntrs_48 is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg_1 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gic0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\Q_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_clk_x_pntrs_48 : entity is "clk_x_pntrs";
end system_auto_cc_0_clk_x_pntrs_48;
architecture STRUCTURE of system_auto_cc_0_clk_x_pntrs_48 is
signal \__0_n_0\ : STD_LOGIC;
signal \__1_n_0\ : STD_LOGIC;
signal \__2_n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_empty_i_reg_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \ram_full_i_i_2__0_n_0\ : STD_LOGIC;
signal \ram_full_i_i_4__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \__1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \__2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[2]_i_1\ : label is "soft_lutpair7";
begin
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_empty_i_reg_0(3 downto 0) <= \^ram_empty_i_reg_0\(3 downto 0);
ram_full_fb_i_reg_0(0) <= \^ram_full_fb_i_reg_0\(0);
\__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => \__0_n_0\
);
\__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(3),
I3 => p_8_out(2),
O => \__1_n_0\
);
\__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_8_out(2),
I1 => p_8_out(1),
I2 => p_8_out(3),
O => \__2_n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized0_63\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized1_64\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\,
m_aclk => m_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized2_65\
port map (
D(3 downto 0) => p_5_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized3_66\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_6_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
m_aclk => m_aclk
);
\gnxpm_cdc.gsync_stage[3].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized4_67\
port map (
D(0) => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_5_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[3].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized5_68\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_6_out(3 downto 0),
m_aclk => m_aclk,
\out\(3 downto 0) => p_8_out(3 downto 0)
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \__1_n_0\,
Q => p_23_out(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \__2_n_0\,
Q => p_23_out(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
Q => p_23_out(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => p_8_out(3),
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[1]\(0),
Q => \^ram_empty_i_reg_0\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \__0_n_0\,
Q => \^ram_empty_i_reg_0\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
Q => \^ram_empty_i_reg_0\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => \^ram_empty_i_reg_0\(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\
);
\ram_empty_i_i_4__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^ram_empty_i_reg_0\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^ram_empty_i_reg_0\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^ram_empty_i_reg_0\(0),
O => ram_empty_i_reg
);
\ram_full_i_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F88F00008888"
)
port map (
I0 => \ram_full_i_i_2__0_n_0\,
I1 => ram_full_fb_i_reg_1,
I2 => Q(3),
I3 => \^ram_full_fb_i_reg_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => \ram_full_i_i_4__0_n_0\,
O => ram_full_fb_i_reg
);
\ram_full_i_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_reg[2]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_reg[2]\(1),
I4 => \gic0.gc0.count_reg[2]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_2__0_n_0\
);
\ram_full_i_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => Q(2),
I2 => p_23_out(1),
I3 => Q(1),
I4 => Q(0),
I5 => p_23_out(0),
O => \ram_full_i_i_4__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_clk_x_pntrs_6 is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg_1 : in STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gic0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\Q_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_clk_x_pntrs_6 : entity is "clk_x_pntrs";
end system_auto_cc_0_clk_x_pntrs_6;
architecture STRUCTURE of system_auto_cc_0_clk_x_pntrs_6 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \__0_n_0\ : STD_LOGIC;
signal \__1_n_0\ : STD_LOGIC;
signal \__2_n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \ram_full_i_i_2__2_n_0\ : STD_LOGIC;
signal \ram_full_i_i_4__2_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \__1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \__2\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[0]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair19";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_full_fb_i_reg_0(0) <= \^ram_full_fb_i_reg_0\(0);
\__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => \__0_n_0\
);
\__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(3),
I3 => p_8_out(2),
O => \__1_n_0\
);
\__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_8_out(2),
I1 => p_8_out(1),
I2 => p_8_out(3),
O => \__2_n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized0_21\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized1_22\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\,
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized2_23\
port map (
D(3 downto 0) => p_5_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized3_24\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_6_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[3].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized4_25\
port map (
D(0) => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_5_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0)
);
\gnxpm_cdc.gsync_stage[3].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized5_26\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_6_out(3 downto 0),
\out\(3 downto 0) => p_8_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__1_n_0\,
Q => p_23_out(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__2_n_0\,
Q => p_23_out(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
Q => p_23_out(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => p_8_out(3),
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[1]\(0),
Q => \^q\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \__0_n_0\,
Q => \^q\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
Q => \^q\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => \^q\(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\
);
\ram_empty_i_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^q\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^q\(0),
O => ram_empty_i_reg
);
\ram_full_i_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F88F00008888"
)
port map (
I0 => \ram_full_i_i_2__2_n_0\,
I1 => ram_full_fb_i_reg_1,
I2 => \gic0.gc0.count_d1_reg[3]\(3),
I3 => \^ram_full_fb_i_reg_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => \ram_full_i_i_4__2_n_0\,
O => ram_full_fb_i_reg
);
\ram_full_i_i_2__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_reg[2]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_reg[2]\(1),
I4 => \gic0.gc0.count_reg[2]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_2__2_n_0\
);
\ram_full_i_i_4__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_d1_reg[3]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_d1_reg[3]\(1),
I4 => \gic0.gc0.count_d1_reg[3]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_4__2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_clk_x_pntrs_70 is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg_1 : in STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gic0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\Q_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_clk_x_pntrs_70 : entity is "clk_x_pntrs";
end system_auto_cc_0_clk_x_pntrs_70;
architecture STRUCTURE of system_auto_cc_0_clk_x_pntrs_70 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \__0_n_0\ : STD_LOGIC;
signal \__1_n_0\ : STD_LOGIC;
signal \__2_n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \ram_full_i_i_2__3_n_0\ : STD_LOGIC;
signal \ram_full_i_i_4__3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \__1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \__2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[0]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair1";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_full_fb_i_reg_0(0) <= \^ram_full_fb_i_reg_0\(0);
\__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => \__0_n_0\
);
\__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(3),
I3 => p_8_out(2),
O => \__1_n_0\
);
\__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_8_out(2),
I1 => p_8_out(1),
I2 => p_8_out(3),
O => \__2_n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized0_87\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized1_88\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\,
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized2_89\
port map (
D(3 downto 0) => p_5_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized3_90\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_6_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[3].rd_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized4_91\
port map (
D(0) => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_5_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0)
);
\gnxpm_cdc.gsync_stage[3].wr_stg_inst\: entity work.\system_auto_cc_0_synchronizer_ff__parameterized5_92\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_6_out(3 downto 0),
\out\(3 downto 0) => p_8_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__1_n_0\,
Q => p_23_out(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__2_n_0\,
Q => p_23_out(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
Q => p_23_out(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => p_8_out(3),
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[1]\(0),
Q => \^q\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \__0_n_0\,
Q => \^q\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
Q => \^q\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => \^q\(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\
);
\ram_empty_i_i_4__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^q\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^q\(0),
O => ram_empty_i_reg
);
\ram_full_i_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F88F00008888"
)
port map (
I0 => \ram_full_i_i_2__3_n_0\,
I1 => ram_full_fb_i_reg_1,
I2 => \gic0.gc0.count_d1_reg[3]\(3),
I3 => \^ram_full_fb_i_reg_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => \ram_full_i_i_4__3_n_0\,
O => ram_full_fb_i_reg
);
\ram_full_i_i_2__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_reg[2]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_reg[2]\(1),
I4 => \gic0.gc0.count_reg[2]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_2__3_n_0\
);
\ram_full_i_i_4__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_d1_reg[3]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_d1_reg[3]\(1),
I4 => \gic0.gc0.count_d1_reg[3]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_4__3_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_memory is
port (
Q : out STD_LOGIC_VECTOR ( 57 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
DI : in STD_LOGIC_VECTOR ( 57 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_memory : entity is "memory";
end system_auto_cc_0_memory;
architecture STRUCTURE of system_auto_cc_0_memory is
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_10\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_11\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_12\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_13\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_14\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_15\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_16\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_17\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_18\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_19\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_20\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_21\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_22\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_23\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_24\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_25\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_26\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_27\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_28\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_29\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_3\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_30\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_31\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_32\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_33\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_34\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_35\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_36\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_37\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_38\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_39\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_4\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_40\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_41\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_42\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_43\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_44\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_45\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_46\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_47\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_48\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_49\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_5\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_50\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_51\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_52\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_53\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_54\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_55\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_56\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_57\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_6\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_7\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_8\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_9\ : STD_LOGIC;
begin
\gdm.dm_gen.dm\: entity work.system_auto_cc_0_dmem
port map (
DI(57 downto 0) => DI(57 downto 0),
dout_i(57) => \gdm.dm_gen.dm_n_0\,
dout_i(56) => \gdm.dm_gen.dm_n_1\,
dout_i(55) => \gdm.dm_gen.dm_n_2\,
dout_i(54) => \gdm.dm_gen.dm_n_3\,
dout_i(53) => \gdm.dm_gen.dm_n_4\,
dout_i(52) => \gdm.dm_gen.dm_n_5\,
dout_i(51) => \gdm.dm_gen.dm_n_6\,
dout_i(50) => \gdm.dm_gen.dm_n_7\,
dout_i(49) => \gdm.dm_gen.dm_n_8\,
dout_i(48) => \gdm.dm_gen.dm_n_9\,
dout_i(47) => \gdm.dm_gen.dm_n_10\,
dout_i(46) => \gdm.dm_gen.dm_n_11\,
dout_i(45) => \gdm.dm_gen.dm_n_12\,
dout_i(44) => \gdm.dm_gen.dm_n_13\,
dout_i(43) => \gdm.dm_gen.dm_n_14\,
dout_i(42) => \gdm.dm_gen.dm_n_15\,
dout_i(41) => \gdm.dm_gen.dm_n_16\,
dout_i(40) => \gdm.dm_gen.dm_n_17\,
dout_i(39) => \gdm.dm_gen.dm_n_18\,
dout_i(38) => \gdm.dm_gen.dm_n_19\,
dout_i(37) => \gdm.dm_gen.dm_n_20\,
dout_i(36) => \gdm.dm_gen.dm_n_21\,
dout_i(35) => \gdm.dm_gen.dm_n_22\,
dout_i(34) => \gdm.dm_gen.dm_n_23\,
dout_i(33) => \gdm.dm_gen.dm_n_24\,
dout_i(32) => \gdm.dm_gen.dm_n_25\,
dout_i(31) => \gdm.dm_gen.dm_n_26\,
dout_i(30) => \gdm.dm_gen.dm_n_27\,
dout_i(29) => \gdm.dm_gen.dm_n_28\,
dout_i(28) => \gdm.dm_gen.dm_n_29\,
dout_i(27) => \gdm.dm_gen.dm_n_30\,
dout_i(26) => \gdm.dm_gen.dm_n_31\,
dout_i(25) => \gdm.dm_gen.dm_n_32\,
dout_i(24) => \gdm.dm_gen.dm_n_33\,
dout_i(23) => \gdm.dm_gen.dm_n_34\,
dout_i(22) => \gdm.dm_gen.dm_n_35\,
dout_i(21) => \gdm.dm_gen.dm_n_36\,
dout_i(20) => \gdm.dm_gen.dm_n_37\,
dout_i(19) => \gdm.dm_gen.dm_n_38\,
dout_i(18) => \gdm.dm_gen.dm_n_39\,
dout_i(17) => \gdm.dm_gen.dm_n_40\,
dout_i(16) => \gdm.dm_gen.dm_n_41\,
dout_i(15) => \gdm.dm_gen.dm_n_42\,
dout_i(14) => \gdm.dm_gen.dm_n_43\,
dout_i(13) => \gdm.dm_gen.dm_n_44\,
dout_i(12) => \gdm.dm_gen.dm_n_45\,
dout_i(11) => \gdm.dm_gen.dm_n_46\,
dout_i(10) => \gdm.dm_gen.dm_n_47\,
dout_i(9) => \gdm.dm_gen.dm_n_48\,
dout_i(8) => \gdm.dm_gen.dm_n_49\,
dout_i(7) => \gdm.dm_gen.dm_n_50\,
dout_i(6) => \gdm.dm_gen.dm_n_51\,
dout_i(5) => \gdm.dm_gen.dm_n_52\,
dout_i(4) => \gdm.dm_gen.dm_n_53\,
dout_i(3) => \gdm.dm_gen.dm_n_54\,
dout_i(2) => \gdm.dm_gen.dm_n_55\,
dout_i(1) => \gdm.dm_gen.dm_n_56\,
dout_i(0) => \gdm.dm_gen.dm_n_57\,
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0),
m_aclk => m_aclk,
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0),
s_aclk => s_aclk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_57\,
Q => Q(0),
R => '0'
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_47\,
Q => Q(10),
R => '0'
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_46\,
Q => Q(11),
R => '0'
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_45\,
Q => Q(12),
R => '0'
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_44\,
Q => Q(13),
R => '0'
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_43\,
Q => Q(14),
R => '0'
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_42\,
Q => Q(15),
R => '0'
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_41\,
Q => Q(16),
R => '0'
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_40\,
Q => Q(17),
R => '0'
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_39\,
Q => Q(18),
R => '0'
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_38\,
Q => Q(19),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_56\,
Q => Q(1),
R => '0'
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_37\,
Q => Q(20),
R => '0'
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_36\,
Q => Q(21),
R => '0'
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_35\,
Q => Q(22),
R => '0'
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_34\,
Q => Q(23),
R => '0'
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_33\,
Q => Q(24),
R => '0'
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_32\,
Q => Q(25),
R => '0'
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_31\,
Q => Q(26),
R => '0'
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_30\,
Q => Q(27),
R => '0'
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_29\,
Q => Q(28),
R => '0'
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_28\,
Q => Q(29),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_55\,
Q => Q(2),
R => '0'
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_27\,
Q => Q(30),
R => '0'
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_26\,
Q => Q(31),
R => '0'
);
\goreg_dm.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_25\,
Q => Q(32),
R => '0'
);
\goreg_dm.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_24\,
Q => Q(33),
R => '0'
);
\goreg_dm.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_23\,
Q => Q(34),
R => '0'
);
\goreg_dm.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_22\,
Q => Q(35),
R => '0'
);
\goreg_dm.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_21\,
Q => Q(36),
R => '0'
);
\goreg_dm.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_20\,
Q => Q(37),
R => '0'
);
\goreg_dm.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_19\,
Q => Q(38),
R => '0'
);
\goreg_dm.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_18\,
Q => Q(39),
R => '0'
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_54\,
Q => Q(3),
R => '0'
);
\goreg_dm.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_17\,
Q => Q(40),
R => '0'
);
\goreg_dm.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_16\,
Q => Q(41),
R => '0'
);
\goreg_dm.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_15\,
Q => Q(42),
R => '0'
);
\goreg_dm.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_14\,
Q => Q(43),
R => '0'
);
\goreg_dm.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_13\,
Q => Q(44),
R => '0'
);
\goreg_dm.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_12\,
Q => Q(45),
R => '0'
);
\goreg_dm.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_11\,
Q => Q(46),
R => '0'
);
\goreg_dm.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_10\,
Q => Q(47),
R => '0'
);
\goreg_dm.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_9\,
Q => Q(48),
R => '0'
);
\goreg_dm.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_8\,
Q => Q(49),
R => '0'
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_53\,
Q => Q(4),
R => '0'
);
\goreg_dm.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_7\,
Q => Q(50),
R => '0'
);
\goreg_dm.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_6\,
Q => Q(51),
R => '0'
);
\goreg_dm.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_5\,
Q => Q(52),
R => '0'
);
\goreg_dm.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_4\,
Q => Q(53),
R => '0'
);
\goreg_dm.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_3\,
Q => Q(54),
R => '0'
);
\goreg_dm.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_2\,
Q => Q(55),
R => '0'
);
\goreg_dm.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_1\,
Q => Q(56),
R => '0'
);
\goreg_dm.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_0\,
Q => Q(57),
R => '0'
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_52\,
Q => Q(5),
R => '0'
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_51\,
Q => Q(6),
R => '0'
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_50\,
Q => Q(7),
R => '0'
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_49\,
Q => Q(8),
R => '0'
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_48\,
Q => Q(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_memory_73 is
port (
\m_axi_arid[0]\ : out STD_LOGIC_VECTOR ( 57 downto 0 );
s_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I123 : in STD_LOGIC_VECTOR ( 57 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_memory_73 : entity is "memory";
end system_auto_cc_0_memory_73;
architecture STRUCTURE of system_auto_cc_0_memory_73 is
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_10\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_11\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_12\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_13\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_14\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_15\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_16\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_17\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_18\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_19\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_20\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_21\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_22\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_23\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_24\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_25\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_26\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_27\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_28\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_29\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_3\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_30\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_31\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_32\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_33\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_34\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_35\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_36\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_37\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_38\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_39\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_4\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_40\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_41\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_42\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_43\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_44\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_45\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_46\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_47\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_48\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_49\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_5\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_50\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_51\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_52\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_53\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_54\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_55\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_56\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_57\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_6\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_7\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_8\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_9\ : STD_LOGIC;
begin
\gdm.dm_gen.dm\: entity work.system_auto_cc_0_dmem_81
port map (
E(0) => E(0),
I123(57 downto 0) => I123(57 downto 0),
Q(57) => \gdm.dm_gen.dm_n_0\,
Q(56) => \gdm.dm_gen.dm_n_1\,
Q(55) => \gdm.dm_gen.dm_n_2\,
Q(54) => \gdm.dm_gen.dm_n_3\,
Q(53) => \gdm.dm_gen.dm_n_4\,
Q(52) => \gdm.dm_gen.dm_n_5\,
Q(51) => \gdm.dm_gen.dm_n_6\,
Q(50) => \gdm.dm_gen.dm_n_7\,
Q(49) => \gdm.dm_gen.dm_n_8\,
Q(48) => \gdm.dm_gen.dm_n_9\,
Q(47) => \gdm.dm_gen.dm_n_10\,
Q(46) => \gdm.dm_gen.dm_n_11\,
Q(45) => \gdm.dm_gen.dm_n_12\,
Q(44) => \gdm.dm_gen.dm_n_13\,
Q(43) => \gdm.dm_gen.dm_n_14\,
Q(42) => \gdm.dm_gen.dm_n_15\,
Q(41) => \gdm.dm_gen.dm_n_16\,
Q(40) => \gdm.dm_gen.dm_n_17\,
Q(39) => \gdm.dm_gen.dm_n_18\,
Q(38) => \gdm.dm_gen.dm_n_19\,
Q(37) => \gdm.dm_gen.dm_n_20\,
Q(36) => \gdm.dm_gen.dm_n_21\,
Q(35) => \gdm.dm_gen.dm_n_22\,
Q(34) => \gdm.dm_gen.dm_n_23\,
Q(33) => \gdm.dm_gen.dm_n_24\,
Q(32) => \gdm.dm_gen.dm_n_25\,
Q(31) => \gdm.dm_gen.dm_n_26\,
Q(30) => \gdm.dm_gen.dm_n_27\,
Q(29) => \gdm.dm_gen.dm_n_28\,
Q(28) => \gdm.dm_gen.dm_n_29\,
Q(27) => \gdm.dm_gen.dm_n_30\,
Q(26) => \gdm.dm_gen.dm_n_31\,
Q(25) => \gdm.dm_gen.dm_n_32\,
Q(24) => \gdm.dm_gen.dm_n_33\,
Q(23) => \gdm.dm_gen.dm_n_34\,
Q(22) => \gdm.dm_gen.dm_n_35\,
Q(21) => \gdm.dm_gen.dm_n_36\,
Q(20) => \gdm.dm_gen.dm_n_37\,
Q(19) => \gdm.dm_gen.dm_n_38\,
Q(18) => \gdm.dm_gen.dm_n_39\,
Q(17) => \gdm.dm_gen.dm_n_40\,
Q(16) => \gdm.dm_gen.dm_n_41\,
Q(15) => \gdm.dm_gen.dm_n_42\,
Q(14) => \gdm.dm_gen.dm_n_43\,
Q(13) => \gdm.dm_gen.dm_n_44\,
Q(12) => \gdm.dm_gen.dm_n_45\,
Q(11) => \gdm.dm_gen.dm_n_46\,
Q(10) => \gdm.dm_gen.dm_n_47\,
Q(9) => \gdm.dm_gen.dm_n_48\,
Q(8) => \gdm.dm_gen.dm_n_49\,
Q(7) => \gdm.dm_gen.dm_n_50\,
Q(6) => \gdm.dm_gen.dm_n_51\,
Q(5) => \gdm.dm_gen.dm_n_52\,
Q(4) => \gdm.dm_gen.dm_n_53\,
Q(3) => \gdm.dm_gen.dm_n_54\,
Q(2) => \gdm.dm_gen.dm_n_55\,
Q(1) => \gdm.dm_gen.dm_n_56\,
Q(0) => \gdm.dm_gen.dm_n_57\,
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0),
m_aclk => m_aclk,
s_aclk => s_aclk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_57\,
Q => \m_axi_arid[0]\(0),
R => '0'
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_47\,
Q => \m_axi_arid[0]\(10),
R => '0'
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_46\,
Q => \m_axi_arid[0]\(11),
R => '0'
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_45\,
Q => \m_axi_arid[0]\(12),
R => '0'
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_44\,
Q => \m_axi_arid[0]\(13),
R => '0'
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_43\,
Q => \m_axi_arid[0]\(14),
R => '0'
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_42\,
Q => \m_axi_arid[0]\(15),
R => '0'
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_41\,
Q => \m_axi_arid[0]\(16),
R => '0'
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_40\,
Q => \m_axi_arid[0]\(17),
R => '0'
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_39\,
Q => \m_axi_arid[0]\(18),
R => '0'
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_38\,
Q => \m_axi_arid[0]\(19),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_56\,
Q => \m_axi_arid[0]\(1),
R => '0'
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_37\,
Q => \m_axi_arid[0]\(20),
R => '0'
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_36\,
Q => \m_axi_arid[0]\(21),
R => '0'
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_35\,
Q => \m_axi_arid[0]\(22),
R => '0'
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_34\,
Q => \m_axi_arid[0]\(23),
R => '0'
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_33\,
Q => \m_axi_arid[0]\(24),
R => '0'
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_32\,
Q => \m_axi_arid[0]\(25),
R => '0'
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_31\,
Q => \m_axi_arid[0]\(26),
R => '0'
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_30\,
Q => \m_axi_arid[0]\(27),
R => '0'
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_29\,
Q => \m_axi_arid[0]\(28),
R => '0'
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_28\,
Q => \m_axi_arid[0]\(29),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_55\,
Q => \m_axi_arid[0]\(2),
R => '0'
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_27\,
Q => \m_axi_arid[0]\(30),
R => '0'
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_26\,
Q => \m_axi_arid[0]\(31),
R => '0'
);
\goreg_dm.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_25\,
Q => \m_axi_arid[0]\(32),
R => '0'
);
\goreg_dm.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_24\,
Q => \m_axi_arid[0]\(33),
R => '0'
);
\goreg_dm.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_23\,
Q => \m_axi_arid[0]\(34),
R => '0'
);
\goreg_dm.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_22\,
Q => \m_axi_arid[0]\(35),
R => '0'
);
\goreg_dm.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_21\,
Q => \m_axi_arid[0]\(36),
R => '0'
);
\goreg_dm.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_20\,
Q => \m_axi_arid[0]\(37),
R => '0'
);
\goreg_dm.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_19\,
Q => \m_axi_arid[0]\(38),
R => '0'
);
\goreg_dm.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_18\,
Q => \m_axi_arid[0]\(39),
R => '0'
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_54\,
Q => \m_axi_arid[0]\(3),
R => '0'
);
\goreg_dm.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_17\,
Q => \m_axi_arid[0]\(40),
R => '0'
);
\goreg_dm.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_16\,
Q => \m_axi_arid[0]\(41),
R => '0'
);
\goreg_dm.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_15\,
Q => \m_axi_arid[0]\(42),
R => '0'
);
\goreg_dm.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_14\,
Q => \m_axi_arid[0]\(43),
R => '0'
);
\goreg_dm.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_13\,
Q => \m_axi_arid[0]\(44),
R => '0'
);
\goreg_dm.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_12\,
Q => \m_axi_arid[0]\(45),
R => '0'
);
\goreg_dm.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_11\,
Q => \m_axi_arid[0]\(46),
R => '0'
);
\goreg_dm.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_10\,
Q => \m_axi_arid[0]\(47),
R => '0'
);
\goreg_dm.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_9\,
Q => \m_axi_arid[0]\(48),
R => '0'
);
\goreg_dm.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_8\,
Q => \m_axi_arid[0]\(49),
R => '0'
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_53\,
Q => \m_axi_arid[0]\(4),
R => '0'
);
\goreg_dm.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_7\,
Q => \m_axi_arid[0]\(50),
R => '0'
);
\goreg_dm.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_6\,
Q => \m_axi_arid[0]\(51),
R => '0'
);
\goreg_dm.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_5\,
Q => \m_axi_arid[0]\(52),
R => '0'
);
\goreg_dm.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_4\,
Q => \m_axi_arid[0]\(53),
R => '0'
);
\goreg_dm.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_3\,
Q => \m_axi_arid[0]\(54),
R => '0'
);
\goreg_dm.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_2\,
Q => \m_axi_arid[0]\(55),
R => '0'
);
\goreg_dm.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_1\,
Q => \m_axi_arid[0]\(56),
R => '0'
);
\goreg_dm.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_0\,
Q => \m_axi_arid[0]\(57),
R => '0'
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_52\,
Q => \m_axi_arid[0]\(5),
R => '0'
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_51\,
Q => \m_axi_arid[0]\(6),
R => '0'
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_50\,
Q => \m_axi_arid[0]\(7),
R => '0'
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_49\,
Q => \m_axi_arid[0]\(8),
R => '0'
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_48\,
Q => \m_axi_arid[0]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_memory__parameterized0\ is
port (
\m_axi_wdata[127]\ : out STD_LOGIC_VECTOR ( 144 downto 0 );
s_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I115 : in STD_LOGIC_VECTOR ( 144 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_memory__parameterized0\ : entity is "memory";
end \system_auto_cc_0_memory__parameterized0\;
architecture STRUCTURE of \system_auto_cc_0_memory__parameterized0\ is
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_10\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_100\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_101\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_102\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_103\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_104\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_105\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_106\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_107\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_108\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_109\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_11\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_110\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_111\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_112\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_113\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_114\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_115\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_116\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_117\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_118\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_119\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_12\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_120\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_121\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_122\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_123\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_124\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_125\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_126\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_127\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_128\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_129\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_13\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_130\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_131\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_132\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_133\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_134\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_135\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_136\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_137\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_138\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_139\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_14\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_140\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_141\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_142\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_143\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_144\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_15\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_16\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_17\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_18\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_19\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_20\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_21\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_22\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_23\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_24\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_25\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_26\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_27\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_28\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_29\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_3\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_30\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_31\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_32\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_33\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_34\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_35\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_36\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_37\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_38\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_39\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_4\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_40\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_41\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_42\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_43\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_44\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_45\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_46\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_47\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_48\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_49\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_5\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_50\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_51\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_52\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_53\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_54\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_55\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_56\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_57\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_58\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_59\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_6\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_60\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_61\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_62\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_63\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_64\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_65\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_66\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_67\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_68\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_69\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_7\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_70\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_71\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_72\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_73\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_74\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_75\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_76\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_77\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_78\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_79\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_8\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_80\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_81\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_82\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_83\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_84\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_85\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_86\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_87\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_88\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_89\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_9\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_90\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_91\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_92\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_93\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_94\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_95\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_96\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_97\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_98\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_99\ : STD_LOGIC;
begin
\gdm.dm_gen.dm\: entity work.\system_auto_cc_0_dmem__parameterized0\
port map (
E(0) => E(0),
I115(144 downto 0) => I115(144 downto 0),
Q(144) => \gdm.dm_gen.dm_n_0\,
Q(143) => \gdm.dm_gen.dm_n_1\,
Q(142) => \gdm.dm_gen.dm_n_2\,
Q(141) => \gdm.dm_gen.dm_n_3\,
Q(140) => \gdm.dm_gen.dm_n_4\,
Q(139) => \gdm.dm_gen.dm_n_5\,
Q(138) => \gdm.dm_gen.dm_n_6\,
Q(137) => \gdm.dm_gen.dm_n_7\,
Q(136) => \gdm.dm_gen.dm_n_8\,
Q(135) => \gdm.dm_gen.dm_n_9\,
Q(134) => \gdm.dm_gen.dm_n_10\,
Q(133) => \gdm.dm_gen.dm_n_11\,
Q(132) => \gdm.dm_gen.dm_n_12\,
Q(131) => \gdm.dm_gen.dm_n_13\,
Q(130) => \gdm.dm_gen.dm_n_14\,
Q(129) => \gdm.dm_gen.dm_n_15\,
Q(128) => \gdm.dm_gen.dm_n_16\,
Q(127) => \gdm.dm_gen.dm_n_17\,
Q(126) => \gdm.dm_gen.dm_n_18\,
Q(125) => \gdm.dm_gen.dm_n_19\,
Q(124) => \gdm.dm_gen.dm_n_20\,
Q(123) => \gdm.dm_gen.dm_n_21\,
Q(122) => \gdm.dm_gen.dm_n_22\,
Q(121) => \gdm.dm_gen.dm_n_23\,
Q(120) => \gdm.dm_gen.dm_n_24\,
Q(119) => \gdm.dm_gen.dm_n_25\,
Q(118) => \gdm.dm_gen.dm_n_26\,
Q(117) => \gdm.dm_gen.dm_n_27\,
Q(116) => \gdm.dm_gen.dm_n_28\,
Q(115) => \gdm.dm_gen.dm_n_29\,
Q(114) => \gdm.dm_gen.dm_n_30\,
Q(113) => \gdm.dm_gen.dm_n_31\,
Q(112) => \gdm.dm_gen.dm_n_32\,
Q(111) => \gdm.dm_gen.dm_n_33\,
Q(110) => \gdm.dm_gen.dm_n_34\,
Q(109) => \gdm.dm_gen.dm_n_35\,
Q(108) => \gdm.dm_gen.dm_n_36\,
Q(107) => \gdm.dm_gen.dm_n_37\,
Q(106) => \gdm.dm_gen.dm_n_38\,
Q(105) => \gdm.dm_gen.dm_n_39\,
Q(104) => \gdm.dm_gen.dm_n_40\,
Q(103) => \gdm.dm_gen.dm_n_41\,
Q(102) => \gdm.dm_gen.dm_n_42\,
Q(101) => \gdm.dm_gen.dm_n_43\,
Q(100) => \gdm.dm_gen.dm_n_44\,
Q(99) => \gdm.dm_gen.dm_n_45\,
Q(98) => \gdm.dm_gen.dm_n_46\,
Q(97) => \gdm.dm_gen.dm_n_47\,
Q(96) => \gdm.dm_gen.dm_n_48\,
Q(95) => \gdm.dm_gen.dm_n_49\,
Q(94) => \gdm.dm_gen.dm_n_50\,
Q(93) => \gdm.dm_gen.dm_n_51\,
Q(92) => \gdm.dm_gen.dm_n_52\,
Q(91) => \gdm.dm_gen.dm_n_53\,
Q(90) => \gdm.dm_gen.dm_n_54\,
Q(89) => \gdm.dm_gen.dm_n_55\,
Q(88) => \gdm.dm_gen.dm_n_56\,
Q(87) => \gdm.dm_gen.dm_n_57\,
Q(86) => \gdm.dm_gen.dm_n_58\,
Q(85) => \gdm.dm_gen.dm_n_59\,
Q(84) => \gdm.dm_gen.dm_n_60\,
Q(83) => \gdm.dm_gen.dm_n_61\,
Q(82) => \gdm.dm_gen.dm_n_62\,
Q(81) => \gdm.dm_gen.dm_n_63\,
Q(80) => \gdm.dm_gen.dm_n_64\,
Q(79) => \gdm.dm_gen.dm_n_65\,
Q(78) => \gdm.dm_gen.dm_n_66\,
Q(77) => \gdm.dm_gen.dm_n_67\,
Q(76) => \gdm.dm_gen.dm_n_68\,
Q(75) => \gdm.dm_gen.dm_n_69\,
Q(74) => \gdm.dm_gen.dm_n_70\,
Q(73) => \gdm.dm_gen.dm_n_71\,
Q(72) => \gdm.dm_gen.dm_n_72\,
Q(71) => \gdm.dm_gen.dm_n_73\,
Q(70) => \gdm.dm_gen.dm_n_74\,
Q(69) => \gdm.dm_gen.dm_n_75\,
Q(68) => \gdm.dm_gen.dm_n_76\,
Q(67) => \gdm.dm_gen.dm_n_77\,
Q(66) => \gdm.dm_gen.dm_n_78\,
Q(65) => \gdm.dm_gen.dm_n_79\,
Q(64) => \gdm.dm_gen.dm_n_80\,
Q(63) => \gdm.dm_gen.dm_n_81\,
Q(62) => \gdm.dm_gen.dm_n_82\,
Q(61) => \gdm.dm_gen.dm_n_83\,
Q(60) => \gdm.dm_gen.dm_n_84\,
Q(59) => \gdm.dm_gen.dm_n_85\,
Q(58) => \gdm.dm_gen.dm_n_86\,
Q(57) => \gdm.dm_gen.dm_n_87\,
Q(56) => \gdm.dm_gen.dm_n_88\,
Q(55) => \gdm.dm_gen.dm_n_89\,
Q(54) => \gdm.dm_gen.dm_n_90\,
Q(53) => \gdm.dm_gen.dm_n_91\,
Q(52) => \gdm.dm_gen.dm_n_92\,
Q(51) => \gdm.dm_gen.dm_n_93\,
Q(50) => \gdm.dm_gen.dm_n_94\,
Q(49) => \gdm.dm_gen.dm_n_95\,
Q(48) => \gdm.dm_gen.dm_n_96\,
Q(47) => \gdm.dm_gen.dm_n_97\,
Q(46) => \gdm.dm_gen.dm_n_98\,
Q(45) => \gdm.dm_gen.dm_n_99\,
Q(44) => \gdm.dm_gen.dm_n_100\,
Q(43) => \gdm.dm_gen.dm_n_101\,
Q(42) => \gdm.dm_gen.dm_n_102\,
Q(41) => \gdm.dm_gen.dm_n_103\,
Q(40) => \gdm.dm_gen.dm_n_104\,
Q(39) => \gdm.dm_gen.dm_n_105\,
Q(38) => \gdm.dm_gen.dm_n_106\,
Q(37) => \gdm.dm_gen.dm_n_107\,
Q(36) => \gdm.dm_gen.dm_n_108\,
Q(35) => \gdm.dm_gen.dm_n_109\,
Q(34) => \gdm.dm_gen.dm_n_110\,
Q(33) => \gdm.dm_gen.dm_n_111\,
Q(32) => \gdm.dm_gen.dm_n_112\,
Q(31) => \gdm.dm_gen.dm_n_113\,
Q(30) => \gdm.dm_gen.dm_n_114\,
Q(29) => \gdm.dm_gen.dm_n_115\,
Q(28) => \gdm.dm_gen.dm_n_116\,
Q(27) => \gdm.dm_gen.dm_n_117\,
Q(26) => \gdm.dm_gen.dm_n_118\,
Q(25) => \gdm.dm_gen.dm_n_119\,
Q(24) => \gdm.dm_gen.dm_n_120\,
Q(23) => \gdm.dm_gen.dm_n_121\,
Q(22) => \gdm.dm_gen.dm_n_122\,
Q(21) => \gdm.dm_gen.dm_n_123\,
Q(20) => \gdm.dm_gen.dm_n_124\,
Q(19) => \gdm.dm_gen.dm_n_125\,
Q(18) => \gdm.dm_gen.dm_n_126\,
Q(17) => \gdm.dm_gen.dm_n_127\,
Q(16) => \gdm.dm_gen.dm_n_128\,
Q(15) => \gdm.dm_gen.dm_n_129\,
Q(14) => \gdm.dm_gen.dm_n_130\,
Q(13) => \gdm.dm_gen.dm_n_131\,
Q(12) => \gdm.dm_gen.dm_n_132\,
Q(11) => \gdm.dm_gen.dm_n_133\,
Q(10) => \gdm.dm_gen.dm_n_134\,
Q(9) => \gdm.dm_gen.dm_n_135\,
Q(8) => \gdm.dm_gen.dm_n_136\,
Q(7) => \gdm.dm_gen.dm_n_137\,
Q(6) => \gdm.dm_gen.dm_n_138\,
Q(5) => \gdm.dm_gen.dm_n_139\,
Q(4) => \gdm.dm_gen.dm_n_140\,
Q(3) => \gdm.dm_gen.dm_n_141\,
Q(2) => \gdm.dm_gen.dm_n_142\,
Q(1) => \gdm.dm_gen.dm_n_143\,
Q(0) => \gdm.dm_gen.dm_n_144\,
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0),
m_aclk => m_aclk,
s_aclk => s_aclk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_144\,
Q => \m_axi_wdata[127]\(0),
R => '0'
);
\goreg_dm.dout_i_reg[100]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_44\,
Q => \m_axi_wdata[127]\(100),
R => '0'
);
\goreg_dm.dout_i_reg[101]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_43\,
Q => \m_axi_wdata[127]\(101),
R => '0'
);
\goreg_dm.dout_i_reg[102]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_42\,
Q => \m_axi_wdata[127]\(102),
R => '0'
);
\goreg_dm.dout_i_reg[103]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_41\,
Q => \m_axi_wdata[127]\(103),
R => '0'
);
\goreg_dm.dout_i_reg[104]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_40\,
Q => \m_axi_wdata[127]\(104),
R => '0'
);
\goreg_dm.dout_i_reg[105]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_39\,
Q => \m_axi_wdata[127]\(105),
R => '0'
);
\goreg_dm.dout_i_reg[106]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_38\,
Q => \m_axi_wdata[127]\(106),
R => '0'
);
\goreg_dm.dout_i_reg[107]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_37\,
Q => \m_axi_wdata[127]\(107),
R => '0'
);
\goreg_dm.dout_i_reg[108]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_36\,
Q => \m_axi_wdata[127]\(108),
R => '0'
);
\goreg_dm.dout_i_reg[109]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_35\,
Q => \m_axi_wdata[127]\(109),
R => '0'
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_134\,
Q => \m_axi_wdata[127]\(10),
R => '0'
);
\goreg_dm.dout_i_reg[110]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_34\,
Q => \m_axi_wdata[127]\(110),
R => '0'
);
\goreg_dm.dout_i_reg[111]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_33\,
Q => \m_axi_wdata[127]\(111),
R => '0'
);
\goreg_dm.dout_i_reg[112]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_32\,
Q => \m_axi_wdata[127]\(112),
R => '0'
);
\goreg_dm.dout_i_reg[113]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_31\,
Q => \m_axi_wdata[127]\(113),
R => '0'
);
\goreg_dm.dout_i_reg[114]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_30\,
Q => \m_axi_wdata[127]\(114),
R => '0'
);
\goreg_dm.dout_i_reg[115]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_29\,
Q => \m_axi_wdata[127]\(115),
R => '0'
);
\goreg_dm.dout_i_reg[116]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_28\,
Q => \m_axi_wdata[127]\(116),
R => '0'
);
\goreg_dm.dout_i_reg[117]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_27\,
Q => \m_axi_wdata[127]\(117),
R => '0'
);
\goreg_dm.dout_i_reg[118]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_26\,
Q => \m_axi_wdata[127]\(118),
R => '0'
);
\goreg_dm.dout_i_reg[119]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_25\,
Q => \m_axi_wdata[127]\(119),
R => '0'
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_133\,
Q => \m_axi_wdata[127]\(11),
R => '0'
);
\goreg_dm.dout_i_reg[120]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_24\,
Q => \m_axi_wdata[127]\(120),
R => '0'
);
\goreg_dm.dout_i_reg[121]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_23\,
Q => \m_axi_wdata[127]\(121),
R => '0'
);
\goreg_dm.dout_i_reg[122]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_22\,
Q => \m_axi_wdata[127]\(122),
R => '0'
);
\goreg_dm.dout_i_reg[123]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_21\,
Q => \m_axi_wdata[127]\(123),
R => '0'
);
\goreg_dm.dout_i_reg[124]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_20\,
Q => \m_axi_wdata[127]\(124),
R => '0'
);
\goreg_dm.dout_i_reg[125]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_19\,
Q => \m_axi_wdata[127]\(125),
R => '0'
);
\goreg_dm.dout_i_reg[126]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_18\,
Q => \m_axi_wdata[127]\(126),
R => '0'
);
\goreg_dm.dout_i_reg[127]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_17\,
Q => \m_axi_wdata[127]\(127),
R => '0'
);
\goreg_dm.dout_i_reg[128]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_16\,
Q => \m_axi_wdata[127]\(128),
R => '0'
);
\goreg_dm.dout_i_reg[129]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_15\,
Q => \m_axi_wdata[127]\(129),
R => '0'
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_132\,
Q => \m_axi_wdata[127]\(12),
R => '0'
);
\goreg_dm.dout_i_reg[130]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_14\,
Q => \m_axi_wdata[127]\(130),
R => '0'
);
\goreg_dm.dout_i_reg[131]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_13\,
Q => \m_axi_wdata[127]\(131),
R => '0'
);
\goreg_dm.dout_i_reg[132]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_12\,
Q => \m_axi_wdata[127]\(132),
R => '0'
);
\goreg_dm.dout_i_reg[133]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_11\,
Q => \m_axi_wdata[127]\(133),
R => '0'
);
\goreg_dm.dout_i_reg[134]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_10\,
Q => \m_axi_wdata[127]\(134),
R => '0'
);
\goreg_dm.dout_i_reg[135]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_9\,
Q => \m_axi_wdata[127]\(135),
R => '0'
);
\goreg_dm.dout_i_reg[136]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_8\,
Q => \m_axi_wdata[127]\(136),
R => '0'
);
\goreg_dm.dout_i_reg[137]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_7\,
Q => \m_axi_wdata[127]\(137),
R => '0'
);
\goreg_dm.dout_i_reg[138]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_6\,
Q => \m_axi_wdata[127]\(138),
R => '0'
);
\goreg_dm.dout_i_reg[139]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_5\,
Q => \m_axi_wdata[127]\(139),
R => '0'
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_131\,
Q => \m_axi_wdata[127]\(13),
R => '0'
);
\goreg_dm.dout_i_reg[140]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_4\,
Q => \m_axi_wdata[127]\(140),
R => '0'
);
\goreg_dm.dout_i_reg[141]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_3\,
Q => \m_axi_wdata[127]\(141),
R => '0'
);
\goreg_dm.dout_i_reg[142]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_2\,
Q => \m_axi_wdata[127]\(142),
R => '0'
);
\goreg_dm.dout_i_reg[143]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_1\,
Q => \m_axi_wdata[127]\(143),
R => '0'
);
\goreg_dm.dout_i_reg[144]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_0\,
Q => \m_axi_wdata[127]\(144),
R => '0'
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_130\,
Q => \m_axi_wdata[127]\(14),
R => '0'
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_129\,
Q => \m_axi_wdata[127]\(15),
R => '0'
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_128\,
Q => \m_axi_wdata[127]\(16),
R => '0'
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_127\,
Q => \m_axi_wdata[127]\(17),
R => '0'
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_126\,
Q => \m_axi_wdata[127]\(18),
R => '0'
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_125\,
Q => \m_axi_wdata[127]\(19),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_143\,
Q => \m_axi_wdata[127]\(1),
R => '0'
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_124\,
Q => \m_axi_wdata[127]\(20),
R => '0'
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_123\,
Q => \m_axi_wdata[127]\(21),
R => '0'
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_122\,
Q => \m_axi_wdata[127]\(22),
R => '0'
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_121\,
Q => \m_axi_wdata[127]\(23),
R => '0'
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_120\,
Q => \m_axi_wdata[127]\(24),
R => '0'
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_119\,
Q => \m_axi_wdata[127]\(25),
R => '0'
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_118\,
Q => \m_axi_wdata[127]\(26),
R => '0'
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_117\,
Q => \m_axi_wdata[127]\(27),
R => '0'
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_116\,
Q => \m_axi_wdata[127]\(28),
R => '0'
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_115\,
Q => \m_axi_wdata[127]\(29),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_142\,
Q => \m_axi_wdata[127]\(2),
R => '0'
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_114\,
Q => \m_axi_wdata[127]\(30),
R => '0'
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_113\,
Q => \m_axi_wdata[127]\(31),
R => '0'
);
\goreg_dm.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_112\,
Q => \m_axi_wdata[127]\(32),
R => '0'
);
\goreg_dm.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_111\,
Q => \m_axi_wdata[127]\(33),
R => '0'
);
\goreg_dm.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_110\,
Q => \m_axi_wdata[127]\(34),
R => '0'
);
\goreg_dm.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_109\,
Q => \m_axi_wdata[127]\(35),
R => '0'
);
\goreg_dm.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_108\,
Q => \m_axi_wdata[127]\(36),
R => '0'
);
\goreg_dm.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_107\,
Q => \m_axi_wdata[127]\(37),
R => '0'
);
\goreg_dm.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_106\,
Q => \m_axi_wdata[127]\(38),
R => '0'
);
\goreg_dm.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_105\,
Q => \m_axi_wdata[127]\(39),
R => '0'
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_141\,
Q => \m_axi_wdata[127]\(3),
R => '0'
);
\goreg_dm.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_104\,
Q => \m_axi_wdata[127]\(40),
R => '0'
);
\goreg_dm.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_103\,
Q => \m_axi_wdata[127]\(41),
R => '0'
);
\goreg_dm.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_102\,
Q => \m_axi_wdata[127]\(42),
R => '0'
);
\goreg_dm.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_101\,
Q => \m_axi_wdata[127]\(43),
R => '0'
);
\goreg_dm.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_100\,
Q => \m_axi_wdata[127]\(44),
R => '0'
);
\goreg_dm.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_99\,
Q => \m_axi_wdata[127]\(45),
R => '0'
);
\goreg_dm.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_98\,
Q => \m_axi_wdata[127]\(46),
R => '0'
);
\goreg_dm.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_97\,
Q => \m_axi_wdata[127]\(47),
R => '0'
);
\goreg_dm.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_96\,
Q => \m_axi_wdata[127]\(48),
R => '0'
);
\goreg_dm.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_95\,
Q => \m_axi_wdata[127]\(49),
R => '0'
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_140\,
Q => \m_axi_wdata[127]\(4),
R => '0'
);
\goreg_dm.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_94\,
Q => \m_axi_wdata[127]\(50),
R => '0'
);
\goreg_dm.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_93\,
Q => \m_axi_wdata[127]\(51),
R => '0'
);
\goreg_dm.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_92\,
Q => \m_axi_wdata[127]\(52),
R => '0'
);
\goreg_dm.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_91\,
Q => \m_axi_wdata[127]\(53),
R => '0'
);
\goreg_dm.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_90\,
Q => \m_axi_wdata[127]\(54),
R => '0'
);
\goreg_dm.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_89\,
Q => \m_axi_wdata[127]\(55),
R => '0'
);
\goreg_dm.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_88\,
Q => \m_axi_wdata[127]\(56),
R => '0'
);
\goreg_dm.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_87\,
Q => \m_axi_wdata[127]\(57),
R => '0'
);
\goreg_dm.dout_i_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_86\,
Q => \m_axi_wdata[127]\(58),
R => '0'
);
\goreg_dm.dout_i_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_85\,
Q => \m_axi_wdata[127]\(59),
R => '0'
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_139\,
Q => \m_axi_wdata[127]\(5),
R => '0'
);
\goreg_dm.dout_i_reg[60]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_84\,
Q => \m_axi_wdata[127]\(60),
R => '0'
);
\goreg_dm.dout_i_reg[61]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_83\,
Q => \m_axi_wdata[127]\(61),
R => '0'
);
\goreg_dm.dout_i_reg[62]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_82\,
Q => \m_axi_wdata[127]\(62),
R => '0'
);
\goreg_dm.dout_i_reg[63]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_81\,
Q => \m_axi_wdata[127]\(63),
R => '0'
);
\goreg_dm.dout_i_reg[64]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_80\,
Q => \m_axi_wdata[127]\(64),
R => '0'
);
\goreg_dm.dout_i_reg[65]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_79\,
Q => \m_axi_wdata[127]\(65),
R => '0'
);
\goreg_dm.dout_i_reg[66]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_78\,
Q => \m_axi_wdata[127]\(66),
R => '0'
);
\goreg_dm.dout_i_reg[67]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_77\,
Q => \m_axi_wdata[127]\(67),
R => '0'
);
\goreg_dm.dout_i_reg[68]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_76\,
Q => \m_axi_wdata[127]\(68),
R => '0'
);
\goreg_dm.dout_i_reg[69]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_75\,
Q => \m_axi_wdata[127]\(69),
R => '0'
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_138\,
Q => \m_axi_wdata[127]\(6),
R => '0'
);
\goreg_dm.dout_i_reg[70]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_74\,
Q => \m_axi_wdata[127]\(70),
R => '0'
);
\goreg_dm.dout_i_reg[71]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_73\,
Q => \m_axi_wdata[127]\(71),
R => '0'
);
\goreg_dm.dout_i_reg[72]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_72\,
Q => \m_axi_wdata[127]\(72),
R => '0'
);
\goreg_dm.dout_i_reg[73]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_71\,
Q => \m_axi_wdata[127]\(73),
R => '0'
);
\goreg_dm.dout_i_reg[74]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_70\,
Q => \m_axi_wdata[127]\(74),
R => '0'
);
\goreg_dm.dout_i_reg[75]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_69\,
Q => \m_axi_wdata[127]\(75),
R => '0'
);
\goreg_dm.dout_i_reg[76]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_68\,
Q => \m_axi_wdata[127]\(76),
R => '0'
);
\goreg_dm.dout_i_reg[77]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_67\,
Q => \m_axi_wdata[127]\(77),
R => '0'
);
\goreg_dm.dout_i_reg[78]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_66\,
Q => \m_axi_wdata[127]\(78),
R => '0'
);
\goreg_dm.dout_i_reg[79]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_65\,
Q => \m_axi_wdata[127]\(79),
R => '0'
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_137\,
Q => \m_axi_wdata[127]\(7),
R => '0'
);
\goreg_dm.dout_i_reg[80]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_64\,
Q => \m_axi_wdata[127]\(80),
R => '0'
);
\goreg_dm.dout_i_reg[81]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_63\,
Q => \m_axi_wdata[127]\(81),
R => '0'
);
\goreg_dm.dout_i_reg[82]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_62\,
Q => \m_axi_wdata[127]\(82),
R => '0'
);
\goreg_dm.dout_i_reg[83]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_61\,
Q => \m_axi_wdata[127]\(83),
R => '0'
);
\goreg_dm.dout_i_reg[84]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_60\,
Q => \m_axi_wdata[127]\(84),
R => '0'
);
\goreg_dm.dout_i_reg[85]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_59\,
Q => \m_axi_wdata[127]\(85),
R => '0'
);
\goreg_dm.dout_i_reg[86]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_58\,
Q => \m_axi_wdata[127]\(86),
R => '0'
);
\goreg_dm.dout_i_reg[87]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_57\,
Q => \m_axi_wdata[127]\(87),
R => '0'
);
\goreg_dm.dout_i_reg[88]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_56\,
Q => \m_axi_wdata[127]\(88),
R => '0'
);
\goreg_dm.dout_i_reg[89]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_55\,
Q => \m_axi_wdata[127]\(89),
R => '0'
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_136\,
Q => \m_axi_wdata[127]\(8),
R => '0'
);
\goreg_dm.dout_i_reg[90]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_54\,
Q => \m_axi_wdata[127]\(90),
R => '0'
);
\goreg_dm.dout_i_reg[91]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_53\,
Q => \m_axi_wdata[127]\(91),
R => '0'
);
\goreg_dm.dout_i_reg[92]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_52\,
Q => \m_axi_wdata[127]\(92),
R => '0'
);
\goreg_dm.dout_i_reg[93]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_51\,
Q => \m_axi_wdata[127]\(93),
R => '0'
);
\goreg_dm.dout_i_reg[94]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_50\,
Q => \m_axi_wdata[127]\(94),
R => '0'
);
\goreg_dm.dout_i_reg[95]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_49\,
Q => \m_axi_wdata[127]\(95),
R => '0'
);
\goreg_dm.dout_i_reg[96]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_48\,
Q => \m_axi_wdata[127]\(96),
R => '0'
);
\goreg_dm.dout_i_reg[97]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_47\,
Q => \m_axi_wdata[127]\(97),
R => '0'
);
\goreg_dm.dout_i_reg[98]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_46\,
Q => \m_axi_wdata[127]\(98),
R => '0'
);
\goreg_dm.dout_i_reg[99]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_45\,
Q => \m_axi_wdata[127]\(99),
R => '0'
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_135\,
Q => \m_axi_wdata[127]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_memory__parameterized1\ is
port (
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gpregsm1.curr_fwft_state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_memory__parameterized1\ : entity is "memory";
end \system_auto_cc_0_memory__parameterized1\;
architecture STRUCTURE of \system_auto_cc_0_memory__parameterized1\ is
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \goreg_dm.dout_i[0]_i_1_n_0\ : STD_LOGIC;
signal \goreg_dm.dout_i[1]_i_1_n_0\ : STD_LOGIC;
signal \goreg_dm.dout_i[2]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_bid\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
s_axi_bid(0) <= \^s_axi_bid\(0);
s_axi_bresp(1 downto 0) <= \^s_axi_bresp\(1 downto 0);
\gdm.dm_gen.dm\: entity work.\system_auto_cc_0_dmem__parameterized1\
port map (
E(0) => E(0),
Q(2) => \gdm.dm_gen.dm_n_0\,
Q(1) => \gdm.dm_gen.dm_n_1\,
Q(0) => \gdm.dm_gen.dm_n_2\,
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0),
m_aclk => m_aclk,
m_axi_bid(0) => m_axi_bid(0),
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
s_aclk => s_aclk
);
\goreg_dm.dout_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFEFFFEF20200020"
)
port map (
I0 => \gdm.dm_gen.dm_n_2\,
I1 => \out\(0),
I2 => \gpregsm1.curr_fwft_state_reg[1]_0\(1),
I3 => \gpregsm1.curr_fwft_state_reg[1]_0\(0),
I4 => s_axi_bready,
I5 => \^s_axi_bresp\(0),
O => \goreg_dm.dout_i[0]_i_1_n_0\
);
\goreg_dm.dout_i[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFEFFFEF20200020"
)
port map (
I0 => \gdm.dm_gen.dm_n_1\,
I1 => \out\(0),
I2 => \gpregsm1.curr_fwft_state_reg[1]_0\(1),
I3 => \gpregsm1.curr_fwft_state_reg[1]_0\(0),
I4 => s_axi_bready,
I5 => \^s_axi_bresp\(1),
O => \goreg_dm.dout_i[1]_i_1_n_0\
);
\goreg_dm.dout_i[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFEFFFEF20200020"
)
port map (
I0 => \gdm.dm_gen.dm_n_0\,
I1 => \out\(0),
I2 => \gpregsm1.curr_fwft_state_reg[1]_0\(1),
I3 => \gpregsm1.curr_fwft_state_reg[1]_0\(0),
I4 => s_axi_bready,
I5 => \^s_axi_bid\(0),
O => \goreg_dm.dout_i[2]_i_1_n_0\
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \goreg_dm.dout_i[0]_i_1_n_0\,
Q => \^s_axi_bresp\(0),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \goreg_dm.dout_i[1]_i_1_n_0\,
Q => \^s_axi_bresp\(1),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \goreg_dm.dout_i[2]_i_1_n_0\,
Q => \^s_axi_bid\(0),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_memory__parameterized2\ is
port (
\s_axi_rid[0]\ : out STD_LOGIC_VECTOR ( 131 downto 0 );
m_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I127 : in STD_LOGIC_VECTOR ( 131 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_memory__parameterized2\ : entity is "memory";
end \system_auto_cc_0_memory__parameterized2\;
architecture STRUCTURE of \system_auto_cc_0_memory__parameterized2\ is
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_10\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_100\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_101\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_102\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_103\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_104\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_105\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_106\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_107\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_108\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_109\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_11\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_110\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_111\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_112\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_113\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_114\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_115\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_116\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_117\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_118\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_119\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_12\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_120\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_121\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_122\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_123\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_124\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_125\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_126\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_127\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_128\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_129\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_13\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_130\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_131\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_14\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_15\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_16\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_17\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_18\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_19\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_20\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_21\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_22\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_23\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_24\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_25\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_26\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_27\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_28\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_29\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_3\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_30\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_31\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_32\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_33\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_34\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_35\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_36\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_37\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_38\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_39\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_4\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_40\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_41\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_42\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_43\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_44\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_45\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_46\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_47\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_48\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_49\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_5\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_50\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_51\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_52\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_53\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_54\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_55\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_56\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_57\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_58\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_59\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_6\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_60\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_61\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_62\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_63\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_64\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_65\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_66\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_67\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_68\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_69\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_7\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_70\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_71\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_72\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_73\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_74\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_75\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_76\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_77\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_78\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_79\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_8\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_80\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_81\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_82\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_83\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_84\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_85\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_86\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_87\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_88\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_89\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_9\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_90\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_91\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_92\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_93\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_94\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_95\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_96\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_97\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_98\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_99\ : STD_LOGIC;
begin
\gdm.dm_gen.dm\: entity work.\system_auto_cc_0_dmem__parameterized2\
port map (
E(0) => E(0),
I127(131 downto 0) => I127(131 downto 0),
Q(131) => \gdm.dm_gen.dm_n_0\,
Q(130) => \gdm.dm_gen.dm_n_1\,
Q(129) => \gdm.dm_gen.dm_n_2\,
Q(128) => \gdm.dm_gen.dm_n_3\,
Q(127) => \gdm.dm_gen.dm_n_4\,
Q(126) => \gdm.dm_gen.dm_n_5\,
Q(125) => \gdm.dm_gen.dm_n_6\,
Q(124) => \gdm.dm_gen.dm_n_7\,
Q(123) => \gdm.dm_gen.dm_n_8\,
Q(122) => \gdm.dm_gen.dm_n_9\,
Q(121) => \gdm.dm_gen.dm_n_10\,
Q(120) => \gdm.dm_gen.dm_n_11\,
Q(119) => \gdm.dm_gen.dm_n_12\,
Q(118) => \gdm.dm_gen.dm_n_13\,
Q(117) => \gdm.dm_gen.dm_n_14\,
Q(116) => \gdm.dm_gen.dm_n_15\,
Q(115) => \gdm.dm_gen.dm_n_16\,
Q(114) => \gdm.dm_gen.dm_n_17\,
Q(113) => \gdm.dm_gen.dm_n_18\,
Q(112) => \gdm.dm_gen.dm_n_19\,
Q(111) => \gdm.dm_gen.dm_n_20\,
Q(110) => \gdm.dm_gen.dm_n_21\,
Q(109) => \gdm.dm_gen.dm_n_22\,
Q(108) => \gdm.dm_gen.dm_n_23\,
Q(107) => \gdm.dm_gen.dm_n_24\,
Q(106) => \gdm.dm_gen.dm_n_25\,
Q(105) => \gdm.dm_gen.dm_n_26\,
Q(104) => \gdm.dm_gen.dm_n_27\,
Q(103) => \gdm.dm_gen.dm_n_28\,
Q(102) => \gdm.dm_gen.dm_n_29\,
Q(101) => \gdm.dm_gen.dm_n_30\,
Q(100) => \gdm.dm_gen.dm_n_31\,
Q(99) => \gdm.dm_gen.dm_n_32\,
Q(98) => \gdm.dm_gen.dm_n_33\,
Q(97) => \gdm.dm_gen.dm_n_34\,
Q(96) => \gdm.dm_gen.dm_n_35\,
Q(95) => \gdm.dm_gen.dm_n_36\,
Q(94) => \gdm.dm_gen.dm_n_37\,
Q(93) => \gdm.dm_gen.dm_n_38\,
Q(92) => \gdm.dm_gen.dm_n_39\,
Q(91) => \gdm.dm_gen.dm_n_40\,
Q(90) => \gdm.dm_gen.dm_n_41\,
Q(89) => \gdm.dm_gen.dm_n_42\,
Q(88) => \gdm.dm_gen.dm_n_43\,
Q(87) => \gdm.dm_gen.dm_n_44\,
Q(86) => \gdm.dm_gen.dm_n_45\,
Q(85) => \gdm.dm_gen.dm_n_46\,
Q(84) => \gdm.dm_gen.dm_n_47\,
Q(83) => \gdm.dm_gen.dm_n_48\,
Q(82) => \gdm.dm_gen.dm_n_49\,
Q(81) => \gdm.dm_gen.dm_n_50\,
Q(80) => \gdm.dm_gen.dm_n_51\,
Q(79) => \gdm.dm_gen.dm_n_52\,
Q(78) => \gdm.dm_gen.dm_n_53\,
Q(77) => \gdm.dm_gen.dm_n_54\,
Q(76) => \gdm.dm_gen.dm_n_55\,
Q(75) => \gdm.dm_gen.dm_n_56\,
Q(74) => \gdm.dm_gen.dm_n_57\,
Q(73) => \gdm.dm_gen.dm_n_58\,
Q(72) => \gdm.dm_gen.dm_n_59\,
Q(71) => \gdm.dm_gen.dm_n_60\,
Q(70) => \gdm.dm_gen.dm_n_61\,
Q(69) => \gdm.dm_gen.dm_n_62\,
Q(68) => \gdm.dm_gen.dm_n_63\,
Q(67) => \gdm.dm_gen.dm_n_64\,
Q(66) => \gdm.dm_gen.dm_n_65\,
Q(65) => \gdm.dm_gen.dm_n_66\,
Q(64) => \gdm.dm_gen.dm_n_67\,
Q(63) => \gdm.dm_gen.dm_n_68\,
Q(62) => \gdm.dm_gen.dm_n_69\,
Q(61) => \gdm.dm_gen.dm_n_70\,
Q(60) => \gdm.dm_gen.dm_n_71\,
Q(59) => \gdm.dm_gen.dm_n_72\,
Q(58) => \gdm.dm_gen.dm_n_73\,
Q(57) => \gdm.dm_gen.dm_n_74\,
Q(56) => \gdm.dm_gen.dm_n_75\,
Q(55) => \gdm.dm_gen.dm_n_76\,
Q(54) => \gdm.dm_gen.dm_n_77\,
Q(53) => \gdm.dm_gen.dm_n_78\,
Q(52) => \gdm.dm_gen.dm_n_79\,
Q(51) => \gdm.dm_gen.dm_n_80\,
Q(50) => \gdm.dm_gen.dm_n_81\,
Q(49) => \gdm.dm_gen.dm_n_82\,
Q(48) => \gdm.dm_gen.dm_n_83\,
Q(47) => \gdm.dm_gen.dm_n_84\,
Q(46) => \gdm.dm_gen.dm_n_85\,
Q(45) => \gdm.dm_gen.dm_n_86\,
Q(44) => \gdm.dm_gen.dm_n_87\,
Q(43) => \gdm.dm_gen.dm_n_88\,
Q(42) => \gdm.dm_gen.dm_n_89\,
Q(41) => \gdm.dm_gen.dm_n_90\,
Q(40) => \gdm.dm_gen.dm_n_91\,
Q(39) => \gdm.dm_gen.dm_n_92\,
Q(38) => \gdm.dm_gen.dm_n_93\,
Q(37) => \gdm.dm_gen.dm_n_94\,
Q(36) => \gdm.dm_gen.dm_n_95\,
Q(35) => \gdm.dm_gen.dm_n_96\,
Q(34) => \gdm.dm_gen.dm_n_97\,
Q(33) => \gdm.dm_gen.dm_n_98\,
Q(32) => \gdm.dm_gen.dm_n_99\,
Q(31) => \gdm.dm_gen.dm_n_100\,
Q(30) => \gdm.dm_gen.dm_n_101\,
Q(29) => \gdm.dm_gen.dm_n_102\,
Q(28) => \gdm.dm_gen.dm_n_103\,
Q(27) => \gdm.dm_gen.dm_n_104\,
Q(26) => \gdm.dm_gen.dm_n_105\,
Q(25) => \gdm.dm_gen.dm_n_106\,
Q(24) => \gdm.dm_gen.dm_n_107\,
Q(23) => \gdm.dm_gen.dm_n_108\,
Q(22) => \gdm.dm_gen.dm_n_109\,
Q(21) => \gdm.dm_gen.dm_n_110\,
Q(20) => \gdm.dm_gen.dm_n_111\,
Q(19) => \gdm.dm_gen.dm_n_112\,
Q(18) => \gdm.dm_gen.dm_n_113\,
Q(17) => \gdm.dm_gen.dm_n_114\,
Q(16) => \gdm.dm_gen.dm_n_115\,
Q(15) => \gdm.dm_gen.dm_n_116\,
Q(14) => \gdm.dm_gen.dm_n_117\,
Q(13) => \gdm.dm_gen.dm_n_118\,
Q(12) => \gdm.dm_gen.dm_n_119\,
Q(11) => \gdm.dm_gen.dm_n_120\,
Q(10) => \gdm.dm_gen.dm_n_121\,
Q(9) => \gdm.dm_gen.dm_n_122\,
Q(8) => \gdm.dm_gen.dm_n_123\,
Q(7) => \gdm.dm_gen.dm_n_124\,
Q(6) => \gdm.dm_gen.dm_n_125\,
Q(5) => \gdm.dm_gen.dm_n_126\,
Q(4) => \gdm.dm_gen.dm_n_127\,
Q(3) => \gdm.dm_gen.dm_n_128\,
Q(2) => \gdm.dm_gen.dm_n_129\,
Q(1) => \gdm.dm_gen.dm_n_130\,
Q(0) => \gdm.dm_gen.dm_n_131\,
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0),
m_aclk => m_aclk,
s_aclk => s_aclk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_131\,
Q => \s_axi_rid[0]\(0),
R => '0'
);
\goreg_dm.dout_i_reg[100]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_31\,
Q => \s_axi_rid[0]\(100),
R => '0'
);
\goreg_dm.dout_i_reg[101]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_30\,
Q => \s_axi_rid[0]\(101),
R => '0'
);
\goreg_dm.dout_i_reg[102]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_29\,
Q => \s_axi_rid[0]\(102),
R => '0'
);
\goreg_dm.dout_i_reg[103]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_28\,
Q => \s_axi_rid[0]\(103),
R => '0'
);
\goreg_dm.dout_i_reg[104]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_27\,
Q => \s_axi_rid[0]\(104),
R => '0'
);
\goreg_dm.dout_i_reg[105]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_26\,
Q => \s_axi_rid[0]\(105),
R => '0'
);
\goreg_dm.dout_i_reg[106]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_25\,
Q => \s_axi_rid[0]\(106),
R => '0'
);
\goreg_dm.dout_i_reg[107]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_24\,
Q => \s_axi_rid[0]\(107),
R => '0'
);
\goreg_dm.dout_i_reg[108]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_23\,
Q => \s_axi_rid[0]\(108),
R => '0'
);
\goreg_dm.dout_i_reg[109]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_22\,
Q => \s_axi_rid[0]\(109),
R => '0'
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_121\,
Q => \s_axi_rid[0]\(10),
R => '0'
);
\goreg_dm.dout_i_reg[110]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_21\,
Q => \s_axi_rid[0]\(110),
R => '0'
);
\goreg_dm.dout_i_reg[111]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_20\,
Q => \s_axi_rid[0]\(111),
R => '0'
);
\goreg_dm.dout_i_reg[112]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_19\,
Q => \s_axi_rid[0]\(112),
R => '0'
);
\goreg_dm.dout_i_reg[113]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_18\,
Q => \s_axi_rid[0]\(113),
R => '0'
);
\goreg_dm.dout_i_reg[114]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_17\,
Q => \s_axi_rid[0]\(114),
R => '0'
);
\goreg_dm.dout_i_reg[115]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_16\,
Q => \s_axi_rid[0]\(115),
R => '0'
);
\goreg_dm.dout_i_reg[116]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_15\,
Q => \s_axi_rid[0]\(116),
R => '0'
);
\goreg_dm.dout_i_reg[117]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_14\,
Q => \s_axi_rid[0]\(117),
R => '0'
);
\goreg_dm.dout_i_reg[118]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_13\,
Q => \s_axi_rid[0]\(118),
R => '0'
);
\goreg_dm.dout_i_reg[119]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_12\,
Q => \s_axi_rid[0]\(119),
R => '0'
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_120\,
Q => \s_axi_rid[0]\(11),
R => '0'
);
\goreg_dm.dout_i_reg[120]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_11\,
Q => \s_axi_rid[0]\(120),
R => '0'
);
\goreg_dm.dout_i_reg[121]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_10\,
Q => \s_axi_rid[0]\(121),
R => '0'
);
\goreg_dm.dout_i_reg[122]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_9\,
Q => \s_axi_rid[0]\(122),
R => '0'
);
\goreg_dm.dout_i_reg[123]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_8\,
Q => \s_axi_rid[0]\(123),
R => '0'
);
\goreg_dm.dout_i_reg[124]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_7\,
Q => \s_axi_rid[0]\(124),
R => '0'
);
\goreg_dm.dout_i_reg[125]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_6\,
Q => \s_axi_rid[0]\(125),
R => '0'
);
\goreg_dm.dout_i_reg[126]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_5\,
Q => \s_axi_rid[0]\(126),
R => '0'
);
\goreg_dm.dout_i_reg[127]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_4\,
Q => \s_axi_rid[0]\(127),
R => '0'
);
\goreg_dm.dout_i_reg[128]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_3\,
Q => \s_axi_rid[0]\(128),
R => '0'
);
\goreg_dm.dout_i_reg[129]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_2\,
Q => \s_axi_rid[0]\(129),
R => '0'
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_119\,
Q => \s_axi_rid[0]\(12),
R => '0'
);
\goreg_dm.dout_i_reg[130]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_1\,
Q => \s_axi_rid[0]\(130),
R => '0'
);
\goreg_dm.dout_i_reg[131]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_0\,
Q => \s_axi_rid[0]\(131),
R => '0'
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_118\,
Q => \s_axi_rid[0]\(13),
R => '0'
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_117\,
Q => \s_axi_rid[0]\(14),
R => '0'
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_116\,
Q => \s_axi_rid[0]\(15),
R => '0'
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_115\,
Q => \s_axi_rid[0]\(16),
R => '0'
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_114\,
Q => \s_axi_rid[0]\(17),
R => '0'
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_113\,
Q => \s_axi_rid[0]\(18),
R => '0'
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_112\,
Q => \s_axi_rid[0]\(19),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_130\,
Q => \s_axi_rid[0]\(1),
R => '0'
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_111\,
Q => \s_axi_rid[0]\(20),
R => '0'
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_110\,
Q => \s_axi_rid[0]\(21),
R => '0'
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_109\,
Q => \s_axi_rid[0]\(22),
R => '0'
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_108\,
Q => \s_axi_rid[0]\(23),
R => '0'
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_107\,
Q => \s_axi_rid[0]\(24),
R => '0'
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_106\,
Q => \s_axi_rid[0]\(25),
R => '0'
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_105\,
Q => \s_axi_rid[0]\(26),
R => '0'
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_104\,
Q => \s_axi_rid[0]\(27),
R => '0'
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_103\,
Q => \s_axi_rid[0]\(28),
R => '0'
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_102\,
Q => \s_axi_rid[0]\(29),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_129\,
Q => \s_axi_rid[0]\(2),
R => '0'
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_101\,
Q => \s_axi_rid[0]\(30),
R => '0'
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_100\,
Q => \s_axi_rid[0]\(31),
R => '0'
);
\goreg_dm.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_99\,
Q => \s_axi_rid[0]\(32),
R => '0'
);
\goreg_dm.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_98\,
Q => \s_axi_rid[0]\(33),
R => '0'
);
\goreg_dm.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_97\,
Q => \s_axi_rid[0]\(34),
R => '0'
);
\goreg_dm.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_96\,
Q => \s_axi_rid[0]\(35),
R => '0'
);
\goreg_dm.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_95\,
Q => \s_axi_rid[0]\(36),
R => '0'
);
\goreg_dm.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_94\,
Q => \s_axi_rid[0]\(37),
R => '0'
);
\goreg_dm.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_93\,
Q => \s_axi_rid[0]\(38),
R => '0'
);
\goreg_dm.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_92\,
Q => \s_axi_rid[0]\(39),
R => '0'
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_128\,
Q => \s_axi_rid[0]\(3),
R => '0'
);
\goreg_dm.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_91\,
Q => \s_axi_rid[0]\(40),
R => '0'
);
\goreg_dm.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_90\,
Q => \s_axi_rid[0]\(41),
R => '0'
);
\goreg_dm.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_89\,
Q => \s_axi_rid[0]\(42),
R => '0'
);
\goreg_dm.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_88\,
Q => \s_axi_rid[0]\(43),
R => '0'
);
\goreg_dm.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_87\,
Q => \s_axi_rid[0]\(44),
R => '0'
);
\goreg_dm.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_86\,
Q => \s_axi_rid[0]\(45),
R => '0'
);
\goreg_dm.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_85\,
Q => \s_axi_rid[0]\(46),
R => '0'
);
\goreg_dm.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_84\,
Q => \s_axi_rid[0]\(47),
R => '0'
);
\goreg_dm.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_83\,
Q => \s_axi_rid[0]\(48),
R => '0'
);
\goreg_dm.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_82\,
Q => \s_axi_rid[0]\(49),
R => '0'
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_127\,
Q => \s_axi_rid[0]\(4),
R => '0'
);
\goreg_dm.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_81\,
Q => \s_axi_rid[0]\(50),
R => '0'
);
\goreg_dm.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_80\,
Q => \s_axi_rid[0]\(51),
R => '0'
);
\goreg_dm.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_79\,
Q => \s_axi_rid[0]\(52),
R => '0'
);
\goreg_dm.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_78\,
Q => \s_axi_rid[0]\(53),
R => '0'
);
\goreg_dm.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_77\,
Q => \s_axi_rid[0]\(54),
R => '0'
);
\goreg_dm.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_76\,
Q => \s_axi_rid[0]\(55),
R => '0'
);
\goreg_dm.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_75\,
Q => \s_axi_rid[0]\(56),
R => '0'
);
\goreg_dm.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_74\,
Q => \s_axi_rid[0]\(57),
R => '0'
);
\goreg_dm.dout_i_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_73\,
Q => \s_axi_rid[0]\(58),
R => '0'
);
\goreg_dm.dout_i_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_72\,
Q => \s_axi_rid[0]\(59),
R => '0'
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_126\,
Q => \s_axi_rid[0]\(5),
R => '0'
);
\goreg_dm.dout_i_reg[60]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_71\,
Q => \s_axi_rid[0]\(60),
R => '0'
);
\goreg_dm.dout_i_reg[61]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_70\,
Q => \s_axi_rid[0]\(61),
R => '0'
);
\goreg_dm.dout_i_reg[62]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_69\,
Q => \s_axi_rid[0]\(62),
R => '0'
);
\goreg_dm.dout_i_reg[63]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_68\,
Q => \s_axi_rid[0]\(63),
R => '0'
);
\goreg_dm.dout_i_reg[64]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_67\,
Q => \s_axi_rid[0]\(64),
R => '0'
);
\goreg_dm.dout_i_reg[65]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_66\,
Q => \s_axi_rid[0]\(65),
R => '0'
);
\goreg_dm.dout_i_reg[66]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_65\,
Q => \s_axi_rid[0]\(66),
R => '0'
);
\goreg_dm.dout_i_reg[67]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_64\,
Q => \s_axi_rid[0]\(67),
R => '0'
);
\goreg_dm.dout_i_reg[68]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_63\,
Q => \s_axi_rid[0]\(68),
R => '0'
);
\goreg_dm.dout_i_reg[69]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_62\,
Q => \s_axi_rid[0]\(69),
R => '0'
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_125\,
Q => \s_axi_rid[0]\(6),
R => '0'
);
\goreg_dm.dout_i_reg[70]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_61\,
Q => \s_axi_rid[0]\(70),
R => '0'
);
\goreg_dm.dout_i_reg[71]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_60\,
Q => \s_axi_rid[0]\(71),
R => '0'
);
\goreg_dm.dout_i_reg[72]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_59\,
Q => \s_axi_rid[0]\(72),
R => '0'
);
\goreg_dm.dout_i_reg[73]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_58\,
Q => \s_axi_rid[0]\(73),
R => '0'
);
\goreg_dm.dout_i_reg[74]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_57\,
Q => \s_axi_rid[0]\(74),
R => '0'
);
\goreg_dm.dout_i_reg[75]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_56\,
Q => \s_axi_rid[0]\(75),
R => '0'
);
\goreg_dm.dout_i_reg[76]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_55\,
Q => \s_axi_rid[0]\(76),
R => '0'
);
\goreg_dm.dout_i_reg[77]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_54\,
Q => \s_axi_rid[0]\(77),
R => '0'
);
\goreg_dm.dout_i_reg[78]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_53\,
Q => \s_axi_rid[0]\(78),
R => '0'
);
\goreg_dm.dout_i_reg[79]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_52\,
Q => \s_axi_rid[0]\(79),
R => '0'
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_124\,
Q => \s_axi_rid[0]\(7),
R => '0'
);
\goreg_dm.dout_i_reg[80]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_51\,
Q => \s_axi_rid[0]\(80),
R => '0'
);
\goreg_dm.dout_i_reg[81]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_50\,
Q => \s_axi_rid[0]\(81),
R => '0'
);
\goreg_dm.dout_i_reg[82]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_49\,
Q => \s_axi_rid[0]\(82),
R => '0'
);
\goreg_dm.dout_i_reg[83]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_48\,
Q => \s_axi_rid[0]\(83),
R => '0'
);
\goreg_dm.dout_i_reg[84]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_47\,
Q => \s_axi_rid[0]\(84),
R => '0'
);
\goreg_dm.dout_i_reg[85]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_46\,
Q => \s_axi_rid[0]\(85),
R => '0'
);
\goreg_dm.dout_i_reg[86]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_45\,
Q => \s_axi_rid[0]\(86),
R => '0'
);
\goreg_dm.dout_i_reg[87]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_44\,
Q => \s_axi_rid[0]\(87),
R => '0'
);
\goreg_dm.dout_i_reg[88]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_43\,
Q => \s_axi_rid[0]\(88),
R => '0'
);
\goreg_dm.dout_i_reg[89]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_42\,
Q => \s_axi_rid[0]\(89),
R => '0'
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_123\,
Q => \s_axi_rid[0]\(8),
R => '0'
);
\goreg_dm.dout_i_reg[90]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_41\,
Q => \s_axi_rid[0]\(90),
R => '0'
);
\goreg_dm.dout_i_reg[91]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_40\,
Q => \s_axi_rid[0]\(91),
R => '0'
);
\goreg_dm.dout_i_reg[92]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_39\,
Q => \s_axi_rid[0]\(92),
R => '0'
);
\goreg_dm.dout_i_reg[93]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_38\,
Q => \s_axi_rid[0]\(93),
R => '0'
);
\goreg_dm.dout_i_reg[94]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_37\,
Q => \s_axi_rid[0]\(94),
R => '0'
);
\goreg_dm.dout_i_reg[95]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_36\,
Q => \s_axi_rid[0]\(95),
R => '0'
);
\goreg_dm.dout_i_reg[96]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_35\,
Q => \s_axi_rid[0]\(96),
R => '0'
);
\goreg_dm.dout_i_reg[97]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_34\,
Q => \s_axi_rid[0]\(97),
R => '0'
);
\goreg_dm.dout_i_reg[98]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_33\,
Q => \s_axi_rid[0]\(98),
R => '0'
);
\goreg_dm.dout_i_reg[99]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_32\,
Q => \s_axi_rid[0]\(99),
R => '0'
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_122\,
Q => \s_axi_rid[0]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_logic is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_logic : entity is "rd_logic";
end system_auto_cc_0_rd_logic;
architecture STRUCTURE of system_auto_cc_0_rd_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_2\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rpntr_n_4 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.system_auto_cc_0_rd_fwft
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(0) => rd_pntr_plus1(3),
\gnxpm_cdc.wr_pntr_bin_reg[3]\(0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gr1.gr1_int.rfwft_n_2\,
s_aclk => s_aclk,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid
);
\gras.rsts\: entity work.system_auto_cc_0_rd_status_flags_as
port map (
AR(0) => AR(0),
\gc0.count_d1_reg[2]\ => rpntr_n_4,
\out\ => p_2_out,
s_aclk => s_aclk
);
rpntr: entity work.system_auto_cc_0_rd_bin_cntr
port map (
AR(0) => AR(0),
D(2 downto 0) => D(2 downto 0),
E(0) => \^e\(0),
Q(3) => rd_pntr_plus1(3),
Q(2 downto 0) => Q(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gr1.gr1_int.rfwft_n_2\,
ram_empty_i_reg => rpntr_n_4,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_logic_28 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[57]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_gc_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_logic_28 : entity is "rd_logic";
end system_auto_cc_0_rd_logic_28;
architecture STRUCTURE of system_auto_cc_0_rd_logic_28 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_0\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rpntr_n_4 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.system_auto_cc_0_rd_fwft_39
port map (
E(0) => \^e\(0),
Q(0) => rd_pntr_plus1(3),
\gnxpm_cdc.wr_pntr_bin_reg[3]\(0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
\goreg_dm.dout_i_reg[57]\(0) => \goreg_dm.dout_i_reg[57]\(0),
m_aclk => m_aclk,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gr1.gr1_int.rfwft_n_0\
);
\gras.rsts\: entity work.system_auto_cc_0_rd_status_flags_as_40
port map (
\gc0.count_d1_reg[2]\ => rpntr_n_4,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out
);
rpntr: entity work.system_auto_cc_0_rd_bin_cntr_41
port map (
E(0) => \^e\(0),
Q(3) => rd_pntr_plus1(3),
Q(2 downto 0) => Q(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[2]\(2 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[2]\(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gr1.gr1_int.rfwft_n_0\,
m_aclk => m_aclk,
\out\(0) => \out\(1),
ram_empty_i_reg => rpntr_n_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_logic_49 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[131]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_logic_49 : entity is "rd_logic";
end system_auto_cc_0_rd_logic_49;
architecture STRUCTURE of system_auto_cc_0_rd_logic_49 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_0\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rpntr_n_4 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.system_auto_cc_0_rd_fwft_60
port map (
E(0) => \^e\(0),
Q(0) => rd_pntr_plus1(3),
\gnxpm_cdc.wr_pntr_bin_reg[3]\(0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
\goreg_dm.dout_i_reg[131]\(0) => \goreg_dm.dout_i_reg[131]\(0),
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gr1.gr1_int.rfwft_n_0\,
s_aclk => s_aclk,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
\gras.rsts\: entity work.system_auto_cc_0_rd_status_flags_as_61
port map (
\gc0.count_d1_reg[2]\ => rpntr_n_4,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out,
s_aclk => s_aclk
);
rpntr: entity work.system_auto_cc_0_rd_bin_cntr_62
port map (
D(2 downto 0) => D(2 downto 0),
E(0) => \^e\(0),
Q(3) => rd_pntr_plus1(3),
Q(2 downto 0) => Q(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gr1.gr1_int.rfwft_n_0\,
\out\(0) => \out\(1),
ram_empty_i_reg => rpntr_n_4,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_logic_7 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[144]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_logic_7 : entity is "rd_logic";
end system_auto_cc_0_rd_logic_7;
architecture STRUCTURE of system_auto_cc_0_rd_logic_7 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_0\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rpntr_n_4 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.system_auto_cc_0_rd_fwft_18
port map (
E(0) => \^e\(0),
Q(0) => rd_pntr_plus1(3),
\gnxpm_cdc.wr_pntr_bin_reg[3]\(0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
\goreg_dm.dout_i_reg[144]\(0) => \goreg_dm.dout_i_reg[144]\(0),
m_aclk => m_aclk,
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gr1.gr1_int.rfwft_n_0\
);
\gras.rsts\: entity work.system_auto_cc_0_rd_status_flags_as_19
port map (
\gc0.count_d1_reg[2]\ => rpntr_n_4,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out
);
rpntr: entity work.system_auto_cc_0_rd_bin_cntr_20
port map (
D(2 downto 0) => D(2 downto 0),
E(0) => \^e\(0),
Q(3) => rd_pntr_plus1(3),
Q(2 downto 0) => Q(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gr1.gr1_int.rfwft_n_0\,
m_aclk => m_aclk,
\out\(0) => \out\(1),
ram_empty_i_reg => rpntr_n_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_rd_logic_71 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[57]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_rd_logic_71 : entity is "rd_logic";
end system_auto_cc_0_rd_logic_71;
architecture STRUCTURE of system_auto_cc_0_rd_logic_71 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_0\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rpntr_n_4 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.system_auto_cc_0_rd_fwft_84
port map (
E(0) => \^e\(0),
Q(0) => rd_pntr_plus1(3),
\gnxpm_cdc.wr_pntr_bin_reg[3]\(0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
\goreg_dm.dout_i_reg[57]\(0) => \goreg_dm.dout_i_reg[57]\(0),
m_aclk => m_aclk,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gr1.gr1_int.rfwft_n_0\
);
\gras.rsts\: entity work.system_auto_cc_0_rd_status_flags_as_85
port map (
\gc0.count_d1_reg[2]\ => rpntr_n_4,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out
);
rpntr: entity work.system_auto_cc_0_rd_bin_cntr_86
port map (
D(2 downto 0) => D(2 downto 0),
E(0) => \^e\(0),
Q(3) => rd_pntr_plus1(3),
Q(2 downto 0) => Q(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gr1.gr1_int.rfwft_n_0\,
m_aclk => m_aclk,
\out\(0) => \out\(1),
ram_empty_i_reg => rpntr_n_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end system_auto_cc_0_reset_blk_ramfifo;
architecture STRUCTURE of system_auto_cc_0_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff
port map (
in0(0) => rd_rst_asreg,
\out\ => p_5_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_1
port map (
in0(0) => wr_rst_asreg,
m_aclk => m_aclk,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_2
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_7_out,
in0(0) => rd_rst_asreg,
\out\ => p_5_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_3
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
in0(0) => wr_rst_asreg,
m_aclk => m_aclk,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_4
port map (
\Q_reg_reg[0]_0\ => p_7_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_5
port map (
\Q_reg_reg[0]_0\ => p_8_out,
m_aclk => m_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_reset_blk_ramfifo_30 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_reset_blk_ramfifo_30 : entity is "reset_blk_ramfifo";
end system_auto_cc_0_reset_blk_ramfifo_30;
architecture STRUCTURE of system_auto_cc_0_reset_blk_ramfifo_30 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_31
port map (
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_32
port map (
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_33
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_7_out,
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_34
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_35
port map (
\Q_reg_reg[0]_0\ => p_7_out,
m_aclk => m_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_36
port map (
\Q_reg_reg[0]_0\ => p_8_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_reset_blk_ramfifo_51 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\ : out STD_LOGIC;
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_reset_blk_ramfifo_51 : entity is "reset_blk_ramfifo";
end system_auto_cc_0_reset_blk_ramfifo_51;
architecture STRUCTURE of system_auto_cc_0_reset_blk_ramfifo_51 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\ : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\ <= \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_52
port map (
in0(0) => rd_rst_asreg,
\out\ => p_5_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_53
port map (
in0(0) => wr_rst_asreg,
m_aclk => m_aclk,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_54
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_7_out,
in0(0) => rd_rst_asreg,
\out\ => p_5_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_55
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
in0(0) => wr_rst_asreg,
m_aclk => m_aclk,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_56
port map (
\Q_reg_reg[0]_0\ => p_7_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_57
port map (
\Q_reg_reg[0]_0\ => p_8_out,
m_aclk => m_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_aresetn,
O => \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_reset_blk_ramfifo_74 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_reset_blk_ramfifo_74 : entity is "reset_blk_ramfifo";
end system_auto_cc_0_reset_blk_ramfifo_74;
architecture STRUCTURE of system_auto_cc_0_reset_blk_ramfifo_74 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_75
port map (
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_76
port map (
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_77
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_7_out,
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_78
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_79
port map (
\Q_reg_reg[0]_0\ => p_7_out,
m_aclk => m_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_80
port map (
\Q_reg_reg[0]_0\ => p_8_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_reset_blk_ramfifo_9 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_reset_blk_ramfifo_9 : entity is "reset_blk_ramfifo";
end system_auto_cc_0_reset_blk_ramfifo_9;
architecture STRUCTURE of system_auto_cc_0_reset_blk_ramfifo_9 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_10
port map (
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_11
port map (
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_12
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_7_out,
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_13
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_14
port map (
\Q_reg_reg[0]_0\ => p_7_out,
m_aclk => m_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.system_auto_cc_0_synchronizer_ff_15
port map (
\Q_reg_reg[0]_0\ => p_8_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_logic is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC;
\gic0.gc0.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_logic : entity is "wr_logic";
end system_auto_cc_0_wr_logic;
architecture STRUCTURE of system_auto_cc_0_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.system_auto_cc_0_wr_status_flags_as
port map (
E(0) => \^e\(0),
Q(0) => wr_pntr_plus2(3),
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
m_aclk => m_aclk,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg
);
wpntr: entity work.system_auto_cc_0_wr_bin_cntr
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3) => wr_pntr_plus2(3),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
m_aclk => m_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_logic_29 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC;
\gic0.gc0.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_logic_29 : entity is "wr_logic";
end system_auto_cc_0_wr_logic_29;
architecture STRUCTURE of system_auto_cc_0_wr_logic_29 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.system_auto_cc_0_wr_status_flags_as_37
port map (
E(0) => \^e\(0),
Q(0) => wr_pntr_plus2(3),
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg,
s_aclk => s_aclk,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid
);
wpntr: entity work.system_auto_cc_0_wr_bin_cntr_38
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3) => wr_pntr_plus2(3),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_logic_50 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC;
\gic0.gc0.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_logic_50 : entity is "wr_logic";
end system_auto_cc_0_wr_logic_50;
architecture STRUCTURE of system_auto_cc_0_wr_logic_50 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.system_auto_cc_0_wr_status_flags_as_58
port map (
E(0) => \^e\(0),
Q(0) => wr_pntr_plus2(3),
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
m_aclk => m_aclk,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg
);
wpntr: entity work.system_auto_cc_0_wr_bin_cntr_59
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3) => wr_pntr_plus2(3),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
m_aclk => m_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_logic_72 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC;
\gic0.gc0.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_logic_72 : entity is "wr_logic";
end system_auto_cc_0_wr_logic_72;
architecture STRUCTURE of system_auto_cc_0_wr_logic_72 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.system_auto_cc_0_wr_status_flags_as_82
port map (
E(0) => \^e\(0),
Q(0) => wr_pntr_plus2(3),
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg,
s_aclk => s_aclk,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid
);
wpntr: entity work.system_auto_cc_0_wr_bin_cntr_83
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3) => wr_pntr_plus2(3),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_wr_logic_8 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
\gic0.gc0.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_wr_logic_8 : entity is "wr_logic";
end system_auto_cc_0_wr_logic_8;
architecture STRUCTURE of system_auto_cc_0_wr_logic_8 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.system_auto_cc_0_wr_status_flags_as_16
port map (
E(0) => \^e\(0),
Q(0) => wr_pntr_plus2(3),
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg,
s_aclk => s_aclk,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
wpntr: entity work.system_auto_cc_0_wr_bin_cntr_17
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3) => wr_pntr_plus2(3),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_fifo_generator_ramfifo is
port (
s_axi_awready : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 57 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
DI : in STD_LOGIC_VECTOR ( 57 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end system_auto_cc_0_fifo_generator_ramfifo;
architecture STRUCTURE of system_auto_cc_0_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_9\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_0_out_0 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC;
signal p_23_out_1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_7_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.system_auto_cc_0_clk_x_pntrs_27
port map (
AR(0) => wr_rst_i(0),
D(0) => gray2bin(0),
Q(3 downto 0) => p_22_out(3 downto 0),
\gc0.count_d1_reg[2]\(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
\gc0.count_d1_reg[2]\(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
\gc0.count_d1_reg[2]\(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
\gc0.count_d1_reg[3]\(0) => p_0_out_0(3),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gic0.gc0.count_d1_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gic0.gc0.count_reg[2]\(2 downto 0) => wr_pntr_plus2(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => p_23_out,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_7_out(3 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_9\,
ram_full_fb_i_reg_0(0) => p_23_out_1(3),
ram_full_fb_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_7_out(1),
I1 => p_7_out(0),
I2 => p_7_out(3),
I3 => p_7_out(2),
O => gray2bin(0)
);
\gntv_or_sync_fifo.gl0.rd\: entity work.system_auto_cc_0_rd_logic_28
port map (
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[2]\(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
\gnxpm_cdc.rd_pntr_gc_reg[2]\(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
\gnxpm_cdc.rd_pntr_gc_reg[2]\(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out_0(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => p_22_out(3 downto 0),
\goreg_dm.dout_i_reg[57]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
m_aclk => m_aclk,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0)
);
\gntv_or_sync_fifo.gl0.wr\: entity work.system_auto_cc_0_wr_logic_29
port map (
AR(0) => wr_rst_i(1),
E(0) => p_18_out,
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
\gic0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_9\,
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => p_23_out_1(3),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid
);
\gntv_or_sync_fifo.mem\: entity work.system_auto_cc_0_memory
port map (
DI(57 downto 0) => DI(57 downto 0),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
Q(57 downto 0) => Q(57 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out_0(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i,
m_aclk => m_aclk,
ram_full_fb_i_reg(0) => p_18_out,
s_aclk => s_aclk
);
rstblk: entity work.system_auto_cc_0_reset_blk_ramfifo_30
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => p_23_out,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_fifo_generator_ramfifo_69 is
port (
s_axi_arready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
\m_axi_arid[0]\ : out STD_LOGIC_VECTOR ( 57 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
I123 : in STD_LOGIC_VECTOR ( 57 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_fifo_generator_ramfifo_69 : entity is "fifo_generator_ramfifo";
end system_auto_cc_0_fifo_generator_ramfifo_69;
architecture STRUCTURE of system_auto_cc_0_fifo_generator_ramfifo_69 is
signal \gntv_or_sync_fifo.gcx.clkx/_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_9\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_7_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_busy_rach : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.system_auto_cc_0_clk_x_pntrs_70
port map (
AR(0) => wr_rst_i(0),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
Q(3 downto 0) => p_22_out(3 downto 0),
\Q_reg_reg[1]\(0) => \gntv_or_sync_fifo.gcx.clkx/_n_0\,
\gc0.count_d1_reg[3]\(0) => p_0_out(3),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gic0.gc0.count_d1_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gic0.gc0.count_reg[2]\(2 downto 0) => wr_pntr_plus2(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => wr_rst_busy_rach,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_7_out(3 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_9\,
ram_full_fb_i_reg_0(0) => p_23_out(3),
ram_full_fb_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_7_out(1),
I1 => p_7_out(0),
I2 => p_7_out(3),
I3 => p_7_out(2),
O => \gntv_or_sync_fifo.gcx.clkx/_n_0\
);
\gntv_or_sync_fifo.gl0.rd\: entity work.system_auto_cc_0_rd_logic_71
port map (
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => p_22_out(3 downto 0),
\goreg_dm.dout_i_reg[57]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
m_aclk => m_aclk,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0)
);
\gntv_or_sync_fifo.gl0.wr\: entity work.system_auto_cc_0_wr_logic_72
port map (
AR(0) => wr_rst_i(1),
E(0) => p_18_out,
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
\gic0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_9\,
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => p_23_out(3),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid
);
\gntv_or_sync_fifo.mem\: entity work.system_auto_cc_0_memory_73
port map (
E(0) => p_18_out,
I123(57 downto 0) => I123(57 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i,
m_aclk => m_aclk,
\m_axi_arid[0]\(57 downto 0) => \m_axi_arid[0]\(57 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
s_aclk => s_aclk
);
rstblk: entity work.system_auto_cc_0_reset_blk_ramfifo_74
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => wr_rst_busy_rach,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_fifo_generator_ramfifo__parameterized0\ is
port (
s_axi_wready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
\m_axi_wdata[127]\ : out STD_LOGIC_VECTOR ( 144 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
I115 : in STD_LOGIC_VECTOR ( 144 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_fifo_generator_ramfifo__parameterized0\ : entity is "fifo_generator_ramfifo";
end \system_auto_cc_0_fifo_generator_ramfifo__parameterized0\;
architecture STRUCTURE of \system_auto_cc_0_fifo_generator_ramfifo__parameterized0\ is
signal \gntv_or_sync_fifo.gcx.clkx/_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_9\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_15_out : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_7_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.system_auto_cc_0_clk_x_pntrs_6
port map (
AR(0) => wr_rst_i(0),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
Q(3 downto 0) => p_22_out(3 downto 0),
\Q_reg_reg[1]\(0) => \gntv_or_sync_fifo.gcx.clkx/_n_0\,
\gc0.count_d1_reg[3]\(0) => p_0_out(3),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gic0.gc0.count_d1_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gic0.gc0.count_reg[2]\(2 downto 0) => wr_pntr_plus2(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => p_15_out,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_7_out(3 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_9\,
ram_full_fb_i_reg_0(0) => p_23_out(3),
ram_full_fb_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_7_out(1),
I1 => p_7_out(0),
I2 => p_7_out(3),
I3 => p_7_out(2),
O => \gntv_or_sync_fifo.gcx.clkx/_n_0\
);
\gntv_or_sync_fifo.gl0.rd\: entity work.system_auto_cc_0_rd_logic_7
port map (
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => p_22_out(3 downto 0),
\goreg_dm.dout_i_reg[144]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
m_aclk => m_aclk,
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0)
);
\gntv_or_sync_fifo.gl0.wr\: entity work.system_auto_cc_0_wr_logic_8
port map (
AR(0) => wr_rst_i(1),
E(0) => p_18_out,
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
\gic0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_9\,
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => p_23_out(3),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
\gntv_or_sync_fifo.mem\: entity work.\system_auto_cc_0_memory__parameterized0\
port map (
E(0) => p_18_out,
I115(144 downto 0) => I115(144 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i,
m_aclk => m_aclk,
\m_axi_wdata[127]\(144 downto 0) => \m_axi_wdata[127]\(144 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
s_aclk => s_aclk
);
rstblk: entity work.system_auto_cc_0_reset_blk_ramfifo_9
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => p_15_out,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_fifo_generator_ramfifo__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_fifo_generator_ramfifo__parameterized1\ : entity is "fifo_generator_ramfifo";
end \system_auto_cc_0_fifo_generator_ramfifo__parameterized1\;
architecture STRUCTURE of \system_auto_cc_0_fifo_generator_ramfifo__parameterized1\ is
signal \gntv_or_sync_fifo.gcx.clkx/_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_8\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal \gr1.gr1_int.rfwft/p_0_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_7_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_busy_wrch : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.system_auto_cc_0_clk_x_pntrs
port map (
AR(0) => wr_rst_i(0),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_7\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_8\,
Q(3 downto 0) => p_13_out(3 downto 0),
\Q_reg_reg[1]\(0) => \gntv_or_sync_fifo.gcx.clkx/_n_0\,
\gc0.count_d1_reg[3]\(0) => p_0_out(3),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gic0.gc0.count_reg[2]\(2 downto 0) => wr_pntr_plus2(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => wr_rst_busy_wrch,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_7_out(3 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_6\,
ram_empty_i_reg_0(3 downto 0) => p_22_out(3 downto 0),
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg_0(0) => p_23_out(3),
ram_full_fb_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_7_out(1),
I1 => p_7_out(0),
I2 => p_7_out(3),
I3 => p_7_out(2),
O => \gntv_or_sync_fifo.gcx.clkx/_n_0\
);
\gntv_or_sync_fifo.gl0.rd\: entity work.system_auto_cc_0_rd_logic
port map (
AR(0) => rd_rst_i(2),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_7\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_8\,
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_6\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => p_22_out(3 downto 0),
\out\(1) => \gntv_or_sync_fifo.gl0.rd_n_0\,
\out\(0) => \gr1.gr1_int.rfwft/p_0_in\(0),
s_aclk => s_aclk,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid
);
\gntv_or_sync_fifo.gl0.wr\: entity work.system_auto_cc_0_wr_logic
port map (
AR(0) => wr_rst_i(1),
E(0) => p_18_out,
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
\gic0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => p_23_out(3),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
m_aclk => m_aclk,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\
);
\gntv_or_sync_fifo.mem\: entity work.\system_auto_cc_0_memory__parameterized1\
port map (
E(0) => p_18_out,
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i,
\gpregsm1.curr_fwft_state_reg[1]_0\(1) => \gntv_or_sync_fifo.gl0.rd_n_0\,
\gpregsm1.curr_fwft_state_reg[1]_0\(0) => \gr1.gr1_int.rfwft/p_0_in\(0),
m_aclk => m_aclk,
m_axi_bid(0) => m_axi_bid(0),
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
\out\(0) => rd_rst_i(0),
s_aclk => s_aclk,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0)
);
rstblk: entity work.system_auto_cc_0_reset_blk_ramfifo
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => wr_rst_busy_wrch,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_fifo_generator_ramfifo__parameterized2\ is
port (
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\s_axi_rid[0]\ : out STD_LOGIC_VECTOR ( 131 downto 0 );
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
I127 : in STD_LOGIC_VECTOR ( 131 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_fifo_generator_ramfifo__parameterized2\ : entity is "fifo_generator_ramfifo";
end \system_auto_cc_0_fifo_generator_ramfifo__parameterized2\;
architecture STRUCTURE of \system_auto_cc_0_fifo_generator_ramfifo__parameterized2\ is
signal \gntv_or_sync_fifo.gcx.clkx/_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_7_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_busy_rdch : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.system_auto_cc_0_clk_x_pntrs_48
port map (
AR(0) => wr_rst_i(0),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
Q(3 downto 0) => p_13_out(3 downto 0),
\Q_reg_reg[1]\(0) => \gntv_or_sync_fifo.gcx.clkx/_n_0\,
\gc0.count_d1_reg[3]\(0) => p_0_out(3),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gic0.gc0.count_reg[2]\(2 downto 0) => wr_pntr_plus2(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => wr_rst_busy_rdch,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_7_out(3 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_6\,
ram_empty_i_reg_0(3 downto 0) => p_22_out(3 downto 0),
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg_0(0) => p_23_out(3),
ram_full_fb_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_7_out(1),
I1 => p_7_out(0),
I2 => p_7_out(3),
I3 => p_7_out(2),
O => \gntv_or_sync_fifo.gcx.clkx/_n_0\
);
\gntv_or_sync_fifo.gl0.rd\: entity work.system_auto_cc_0_rd_logic_49
port map (
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_6\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => p_22_out(3 downto 0),
\goreg_dm.dout_i_reg[131]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0),
s_aclk => s_aclk,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
\gntv_or_sync_fifo.gl0.wr\: entity work.system_auto_cc_0_wr_logic_50
port map (
AR(0) => wr_rst_i(1),
E(0) => p_18_out,
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
\gic0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => p_23_out(3),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
m_aclk => m_aclk,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\
);
\gntv_or_sync_fifo.mem\: entity work.\system_auto_cc_0_memory__parameterized2\
port map (
E(0) => p_18_out,
I127(131 downto 0) => I127(131 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
s_aclk => s_aclk,
\s_axi_rid[0]\(131 downto 0) => \s_axi_rid[0]\(131 downto 0)
);
rstblk: entity work.system_auto_cc_0_reset_blk_ramfifo_51
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\ => \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => wr_rst_busy_rdch,
s_aclk => s_aclk,
s_aresetn => s_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_fifo_generator_top is
port (
s_axi_arready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
\m_axi_arid[0]\ : out STD_LOGIC_VECTOR ( 57 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
I123 : in STD_LOGIC_VECTOR ( 57 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_fifo_generator_top : entity is "fifo_generator_top";
end system_auto_cc_0_fifo_generator_top;
architecture STRUCTURE of system_auto_cc_0_fifo_generator_top is
begin
\grf.rf\: entity work.system_auto_cc_0_fifo_generator_ramfifo_69
port map (
I123(57 downto 0) => I123(57 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\m_axi_arid[0]\(57 downto 0) => \m_axi_arid[0]\(57 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
s_aclk => s_aclk,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_fifo_generator_top_0 is
port (
s_axi_awready : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 57 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
DI : in STD_LOGIC_VECTOR ( 57 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_fifo_generator_top_0 : entity is "fifo_generator_top";
end system_auto_cc_0_fifo_generator_top_0;
architecture STRUCTURE of system_auto_cc_0_fifo_generator_top_0 is
begin
\grf.rf\: entity work.system_auto_cc_0_fifo_generator_ramfifo
port map (
DI(57 downto 0) => DI(57 downto 0),
Q(57 downto 0) => Q(57 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
s_aclk => s_aclk,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_fifo_generator_top__parameterized0\ is
port (
s_axi_wready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
\m_axi_wdata[127]\ : out STD_LOGIC_VECTOR ( 144 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
I115 : in STD_LOGIC_VECTOR ( 144 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_fifo_generator_top__parameterized0\ : entity is "fifo_generator_top";
end \system_auto_cc_0_fifo_generator_top__parameterized0\;
architecture STRUCTURE of \system_auto_cc_0_fifo_generator_top__parameterized0\ is
begin
\grf.rf\: entity work.\system_auto_cc_0_fifo_generator_ramfifo__parameterized0\
port map (
I115(144 downto 0) => I115(144 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\m_axi_wdata[127]\(144 downto 0) => \m_axi_wdata[127]\(144 downto 0),
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
s_aclk => s_aclk,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_fifo_generator_top__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_fifo_generator_top__parameterized1\ : entity is "fifo_generator_top";
end \system_auto_cc_0_fifo_generator_top__parameterized1\;
architecture STRUCTURE of \system_auto_cc_0_fifo_generator_top__parameterized1\ is
begin
\grf.rf\: entity work.\system_auto_cc_0_fifo_generator_ramfifo__parameterized1\
port map (
inverted_reset => inverted_reset,
m_aclk => m_aclk,
m_axi_bid(0) => m_axi_bid(0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
s_aclk => s_aclk,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_0_fifo_generator_top__parameterized2\ is
port (
inverted_reset : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\s_axi_rid[0]\ : out STD_LOGIC_VECTOR ( 131 downto 0 );
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
I127 : in STD_LOGIC_VECTOR ( 131 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_0_fifo_generator_top__parameterized2\ : entity is "fifo_generator_top";
end \system_auto_cc_0_fifo_generator_top__parameterized2\;
architecture STRUCTURE of \system_auto_cc_0_fifo_generator_top__parameterized2\ is
begin
\grf.rf\: entity work.\system_auto_cc_0_fifo_generator_ramfifo__parameterized2\
port map (
I127(131 downto 0) => I127(131 downto 0),
m_aclk => m_aclk,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ => inverted_reset,
s_aclk => s_aclk,
s_aresetn => s_aresetn,
\s_axi_rid[0]\(131 downto 0) => \s_axi_rid[0]\(131 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_fifo_generator_v13_1_3_synth is
port (
Q : out STD_LOGIC_VECTOR ( 57 downto 0 );
\m_axi_wdata[127]\ : out STD_LOGIC_VECTOR ( 144 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
\m_axi_arid[0]\ : out STD_LOGIC_VECTOR ( 57 downto 0 );
\s_axi_rid[0]\ : out STD_LOGIC_VECTOR ( 131 downto 0 );
s_axi_awready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
I115 : in STD_LOGIC_VECTOR ( 144 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC;
I123 : in STD_LOGIC_VECTOR ( 57 downto 0 );
I127 : in STD_LOGIC_VECTOR ( 131 downto 0 );
DI : in STD_LOGIC_VECTOR ( 57 downto 0 );
m_axi_awready : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_fifo_generator_v13_1_3_synth : entity is "fifo_generator_v13_1_3_synth";
end system_auto_cc_0_fifo_generator_v13_1_3_synth;
architecture STRUCTURE of system_auto_cc_0_fifo_generator_v13_1_3_synth is
signal inverted_reset : STD_LOGIC;
begin
\gaxi_full_lite.gread_ch.grach2.axi_rach\: entity work.system_auto_cc_0_fifo_generator_top
port map (
I123(57 downto 0) => I123(57 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\m_axi_arid[0]\(57 downto 0) => \m_axi_arid[0]\(57 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
s_aclk => s_aclk,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid
);
\gaxi_full_lite.gread_ch.grdch2.axi_rdch\: entity work.\system_auto_cc_0_fifo_generator_top__parameterized2\
port map (
I127(131 downto 0) => I127(131 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_aclk => s_aclk,
s_aresetn => s_aresetn,
\s_axi_rid[0]\(131 downto 0) => \s_axi_rid[0]\(131 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
\gaxi_full_lite.gwrite_ch.gwach2.axi_wach\: entity work.system_auto_cc_0_fifo_generator_top_0
port map (
DI(57 downto 0) => DI(57 downto 0),
Q(57 downto 0) => Q(57 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
s_aclk => s_aclk,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid
);
\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch\: entity work.\system_auto_cc_0_fifo_generator_top__parameterized0\
port map (
I115(144 downto 0) => I115(144 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\m_axi_wdata[127]\(144 downto 0) => \m_axi_wdata[127]\(144 downto 0),
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
s_aclk => s_aclk,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch\: entity work.\system_auto_cc_0_fifo_generator_top__parameterized1\
port map (
inverted_reset => inverted_reset,
m_aclk => m_aclk,
m_axi_bid(0) => m_axi_bid(0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
s_aclk => s_aclk,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_fifo_generator_v13_1_3 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 17 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 17 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 27 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 27 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 28;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 128;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 18;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 58;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 132;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 58;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 145;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 3;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of system_auto_cc_0_fifo_generator_v13_1_3 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 18;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of system_auto_cc_0_fifo_generator_v13_1_3 : entity is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 11;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 12;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 12;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 12;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 12;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 12;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 2;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of system_auto_cc_0_fifo_generator_v13_1_3 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is "4kx4";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1021;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 13;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 15;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1021;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 3;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of system_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_fifo_generator_v13_1_3 : entity is "fifo_generator_v13_1_3";
end system_auto_cc_0_fifo_generator_v13_1_3;
architecture STRUCTURE of system_auto_cc_0_fifo_generator_v13_1_3 is
signal \<const0>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const0>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const0>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const0>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const0>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const0>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const0>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
dout(17) <= \<const0>\;
dout(16) <= \<const0>\;
dout(15) <= \<const0>\;
dout(14) <= \<const0>\;
dout(13) <= \<const0>\;
dout(12) <= \<const0>\;
dout(11) <= \<const0>\;
dout(10) <= \<const0>\;
dout(9) <= \<const0>\;
dout(8) <= \<const0>\;
dout(7) <= \<const0>\;
dout(6) <= \<const0>\;
dout(5) <= \<const0>\;
dout(4) <= \<const0>\;
dout(3) <= \<const0>\;
dout(2) <= \<const0>\;
dout(1) <= \<const0>\;
dout(0) <= \<const0>\;
empty <= \<const0>\;
full <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_fifo_gen: entity work.system_auto_cc_0_fifo_generator_v13_1_3_synth
port map (
DI(57) => s_axi_awid(0),
DI(56 downto 29) => s_axi_awaddr(27 downto 0),
DI(28 downto 21) => s_axi_awlen(7 downto 0),
DI(20 downto 18) => s_axi_awsize(2 downto 0),
DI(17 downto 16) => s_axi_awburst(1 downto 0),
DI(15) => s_axi_awlock(0),
DI(14 downto 11) => s_axi_awcache(3 downto 0),
DI(10 downto 8) => s_axi_awprot(2 downto 0),
DI(7 downto 4) => s_axi_awqos(3 downto 0),
DI(3 downto 0) => s_axi_awregion(3 downto 0),
I115(144 downto 17) => s_axi_wdata(127 downto 0),
I115(16 downto 1) => s_axi_wstrb(15 downto 0),
I115(0) => s_axi_wlast,
I123(57) => s_axi_arid(0),
I123(56 downto 29) => s_axi_araddr(27 downto 0),
I123(28 downto 21) => s_axi_arlen(7 downto 0),
I123(20 downto 18) => s_axi_arsize(2 downto 0),
I123(17 downto 16) => s_axi_arburst(1 downto 0),
I123(15) => s_axi_arlock(0),
I123(14 downto 11) => s_axi_arcache(3 downto 0),
I123(10 downto 8) => s_axi_arprot(2 downto 0),
I123(7 downto 4) => s_axi_arqos(3 downto 0),
I123(3 downto 0) => s_axi_arregion(3 downto 0),
I127(131) => m_axi_rid(0),
I127(130 downto 3) => m_axi_rdata(127 downto 0),
I127(2 downto 1) => m_axi_rresp(1 downto 0),
I127(0) => m_axi_rlast,
Q(57) => m_axi_awid(0),
Q(56 downto 29) => m_axi_awaddr(27 downto 0),
Q(28 downto 21) => m_axi_awlen(7 downto 0),
Q(20 downto 18) => m_axi_awsize(2 downto 0),
Q(17 downto 16) => m_axi_awburst(1 downto 0),
Q(15) => m_axi_awlock(0),
Q(14 downto 11) => m_axi_awcache(3 downto 0),
Q(10 downto 8) => m_axi_awprot(2 downto 0),
Q(7 downto 4) => m_axi_awqos(3 downto 0),
Q(3 downto 0) => m_axi_awregion(3 downto 0),
m_aclk => m_aclk,
\m_axi_arid[0]\(57) => m_axi_arid(0),
\m_axi_arid[0]\(56 downto 29) => m_axi_araddr(27 downto 0),
\m_axi_arid[0]\(28 downto 21) => m_axi_arlen(7 downto 0),
\m_axi_arid[0]\(20 downto 18) => m_axi_arsize(2 downto 0),
\m_axi_arid[0]\(17 downto 16) => m_axi_arburst(1 downto 0),
\m_axi_arid[0]\(15) => m_axi_arlock(0),
\m_axi_arid[0]\(14 downto 11) => m_axi_arcache(3 downto 0),
\m_axi_arid[0]\(10 downto 8) => m_axi_arprot(2 downto 0),
\m_axi_arid[0]\(7 downto 4) => m_axi_arqos(3 downto 0),
\m_axi_arid[0]\(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(0) => m_axi_bid(0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\m_axi_wdata[127]\(144 downto 17) => m_axi_wdata(127 downto 0),
\m_axi_wdata[127]\(16 downto 1) => m_axi_wstrb(15 downto 0),
\m_axi_wdata[127]\(0) => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
s_aclk => s_aclk,
s_aresetn => s_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[0]\(131) => s_axi_rid(0),
\s_axi_rid[0]\(130 downto 3) => s_axi_rdata(127 downto 0),
\s_axi_rid[0]\(2 downto 1) => s_axi_rresp(1 downto 0),
\s_axi_rid[0]\(0) => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 27 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 27 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_ARADDR_RIGHT : integer;
attribute C_ARADDR_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 29;
attribute C_ARADDR_WIDTH : integer;
attribute C_ARADDR_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 28;
attribute C_ARBURST_RIGHT : integer;
attribute C_ARBURST_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 16;
attribute C_ARBURST_WIDTH : integer;
attribute C_ARBURST_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_ARCACHE_RIGHT : integer;
attribute C_ARCACHE_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 11;
attribute C_ARCACHE_WIDTH : integer;
attribute C_ARCACHE_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_ARID_RIGHT : integer;
attribute C_ARID_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 57;
attribute C_ARID_WIDTH : integer;
attribute C_ARID_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_ARLEN_RIGHT : integer;
attribute C_ARLEN_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 21;
attribute C_ARLEN_WIDTH : integer;
attribute C_ARLEN_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 8;
attribute C_ARLOCK_RIGHT : integer;
attribute C_ARLOCK_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 15;
attribute C_ARLOCK_WIDTH : integer;
attribute C_ARLOCK_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_ARPROT_RIGHT : integer;
attribute C_ARPROT_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 8;
attribute C_ARPROT_WIDTH : integer;
attribute C_ARPROT_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_ARQOS_RIGHT : integer;
attribute C_ARQOS_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_ARQOS_WIDTH : integer;
attribute C_ARQOS_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_ARREGION_RIGHT : integer;
attribute C_ARREGION_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_ARREGION_WIDTH : integer;
attribute C_ARREGION_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_ARSIZE_RIGHT : integer;
attribute C_ARSIZE_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 18;
attribute C_ARSIZE_WIDTH : integer;
attribute C_ARSIZE_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_ARUSER_RIGHT : integer;
attribute C_ARUSER_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_ARUSER_WIDTH : integer;
attribute C_ARUSER_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AR_WIDTH : integer;
attribute C_AR_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 58;
attribute C_AWADDR_RIGHT : integer;
attribute C_AWADDR_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 29;
attribute C_AWADDR_WIDTH : integer;
attribute C_AWADDR_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 28;
attribute C_AWBURST_RIGHT : integer;
attribute C_AWBURST_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 16;
attribute C_AWBURST_WIDTH : integer;
attribute C_AWBURST_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_AWCACHE_RIGHT : integer;
attribute C_AWCACHE_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 11;
attribute C_AWCACHE_WIDTH : integer;
attribute C_AWCACHE_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_AWID_RIGHT : integer;
attribute C_AWID_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 57;
attribute C_AWID_WIDTH : integer;
attribute C_AWID_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AWLEN_RIGHT : integer;
attribute C_AWLEN_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 21;
attribute C_AWLEN_WIDTH : integer;
attribute C_AWLEN_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 8;
attribute C_AWLOCK_RIGHT : integer;
attribute C_AWLOCK_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 15;
attribute C_AWLOCK_WIDTH : integer;
attribute C_AWLOCK_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AWPROT_RIGHT : integer;
attribute C_AWPROT_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 8;
attribute C_AWPROT_WIDTH : integer;
attribute C_AWPROT_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_AWQOS_RIGHT : integer;
attribute C_AWQOS_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AWQOS_WIDTH : integer;
attribute C_AWQOS_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_AWREGION_RIGHT : integer;
attribute C_AWREGION_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_AWREGION_WIDTH : integer;
attribute C_AWREGION_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_AWSIZE_RIGHT : integer;
attribute C_AWSIZE_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 18;
attribute C_AWSIZE_WIDTH : integer;
attribute C_AWSIZE_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_AWUSER_RIGHT : integer;
attribute C_AWUSER_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AWUSER_WIDTH : integer;
attribute C_AWUSER_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AW_WIDTH : integer;
attribute C_AW_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 58;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 28;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 128;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_BID_RIGHT : integer;
attribute C_BID_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_BID_WIDTH : integer;
attribute C_BID_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_BRESP_RIGHT : integer;
attribute C_BRESP_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_BRESP_WIDTH : integer;
attribute C_BRESP_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_BUSER_RIGHT : integer;
attribute C_BUSER_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_BUSER_WIDTH : integer;
attribute C_BUSER_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_FAMILY : string;
attribute C_FAMILY of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is "artix7";
attribute C_FIFO_AR_WIDTH : integer;
attribute C_FIFO_AR_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 58;
attribute C_FIFO_AW_WIDTH : integer;
attribute C_FIFO_AW_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 58;
attribute C_FIFO_B_WIDTH : integer;
attribute C_FIFO_B_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_FIFO_R_WIDTH : integer;
attribute C_FIFO_R_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 132;
attribute C_FIFO_W_WIDTH : integer;
attribute C_FIFO_W_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 145;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_RDATA_RIGHT : integer;
attribute C_RDATA_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_RDATA_WIDTH : integer;
attribute C_RDATA_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 128;
attribute C_RID_RIGHT : integer;
attribute C_RID_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 131;
attribute C_RID_WIDTH : integer;
attribute C_RID_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_RLAST_RIGHT : integer;
attribute C_RLAST_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_RLAST_WIDTH : integer;
attribute C_RLAST_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_RRESP_RIGHT : integer;
attribute C_RRESP_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_RRESP_WIDTH : integer;
attribute C_RRESP_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_RUSER_RIGHT : integer;
attribute C_RUSER_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_RUSER_WIDTH : integer;
attribute C_RUSER_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_R_WIDTH : integer;
attribute C_R_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 132;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_WDATA_RIGHT : integer;
attribute C_WDATA_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 17;
attribute C_WDATA_WIDTH : integer;
attribute C_WDATA_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 128;
attribute C_WID_RIGHT : integer;
attribute C_WID_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 145;
attribute C_WID_WIDTH : integer;
attribute C_WID_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_WLAST_RIGHT : integer;
attribute C_WLAST_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_WLAST_WIDTH : integer;
attribute C_WLAST_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_WSTRB_RIGHT : integer;
attribute C_WSTRB_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_WSTRB_WIDTH : integer;
attribute C_WSTRB_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 16;
attribute C_WUSER_RIGHT : integer;
attribute C_WUSER_RIGHT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_WUSER_WIDTH : integer;
attribute C_WUSER_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_W_WIDTH : integer;
attribute C_W_WIDTH of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 145;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is "axi_clock_converter_v2_1_10_axi_clock_converter";
attribute P_ACLK_RATIO : integer;
attribute P_ACLK_RATIO of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute P_AXI3 : integer;
attribute P_AXI3 of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute P_FULLY_REG : integer;
attribute P_FULLY_REG of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute P_LIGHT_WT : integer;
attribute P_LIGHT_WT of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute P_LUTRAM_ASYNC : integer;
attribute P_LUTRAM_ASYNC of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 12;
attribute P_ROUNDING_OFFSET : integer;
attribute P_ROUNDING_OFFSET of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute P_SI_LT_MI : string;
attribute P_SI_LT_MI of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is "1'b1";
end system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter;
architecture STRUCTURE of system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter is
signal \<const0>\ : STD_LOGIC;
signal async_conv_reset_n : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tlast_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tvalid_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_rst_busy_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axis_tready_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_valid_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_ack_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_rst_busy_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dout_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_aruser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_awuser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wid_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wuser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdata_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdest_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tid_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tkeep_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tstrb_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tuser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_buser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_ruser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_AXI_ADDR_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 28;
attribute C_AXI_ARUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_AWUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_BUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_DATA_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 128;
attribute C_AXI_ID_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_RUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_WUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 18;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 58;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 132;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 58;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 145;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 3;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 18;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_FAMILY of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 11;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 12;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 12;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 12;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 12;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 12;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 2;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "4kx4";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1021;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 13;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1022;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 15;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1021;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_SYNCHRONIZER_STAGE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 3;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 16;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 16;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
begin
m_axi_aruser(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_clock_conv.gen_async_conv.asyncfifo_axi\: entity work.system_auto_cc_0_fifo_generator_v13_1_3
port map (
almost_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_empty_UNCONNECTED\,
almost_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_full_UNCONNECTED\,
axi_ar_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_data_count_UNCONNECTED\(4 downto 0),
axi_ar_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_dbiterr_UNCONNECTED\,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_overflow_UNCONNECTED\,
axi_ar_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_empty_UNCONNECTED\,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_full_UNCONNECTED\,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_rd_data_count_UNCONNECTED\(4 downto 0),
axi_ar_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_sbiterr_UNCONNECTED\,
axi_ar_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_underflow_UNCONNECTED\,
axi_ar_wr_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_wr_data_count_UNCONNECTED\(4 downto 0),
axi_aw_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_data_count_UNCONNECTED\(4 downto 0),
axi_aw_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_dbiterr_UNCONNECTED\,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_overflow_UNCONNECTED\,
axi_aw_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_empty_UNCONNECTED\,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_full_UNCONNECTED\,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_rd_data_count_UNCONNECTED\(4 downto 0),
axi_aw_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_sbiterr_UNCONNECTED\,
axi_aw_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_underflow_UNCONNECTED\,
axi_aw_wr_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_wr_data_count_UNCONNECTED\(4 downto 0),
axi_b_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_data_count_UNCONNECTED\(4 downto 0),
axi_b_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_dbiterr_UNCONNECTED\,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_overflow_UNCONNECTED\,
axi_b_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_empty_UNCONNECTED\,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_full_UNCONNECTED\,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_rd_data_count_UNCONNECTED\(4 downto 0),
axi_b_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_sbiterr_UNCONNECTED\,
axi_b_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_underflow_UNCONNECTED\,
axi_b_wr_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_wr_data_count_UNCONNECTED\(4 downto 0),
axi_r_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_data_count_UNCONNECTED\(4 downto 0),
axi_r_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_dbiterr_UNCONNECTED\,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_overflow_UNCONNECTED\,
axi_r_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_empty_UNCONNECTED\,
axi_r_prog_empty_thresh(3 downto 0) => B"0000",
axi_r_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_full_UNCONNECTED\,
axi_r_prog_full_thresh(3 downto 0) => B"0000",
axi_r_rd_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_rd_data_count_UNCONNECTED\(4 downto 0),
axi_r_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_sbiterr_UNCONNECTED\,
axi_r_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_underflow_UNCONNECTED\,
axi_r_wr_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_wr_data_count_UNCONNECTED\(4 downto 0),
axi_w_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_data_count_UNCONNECTED\(4 downto 0),
axi_w_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_dbiterr_UNCONNECTED\,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_overflow_UNCONNECTED\,
axi_w_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_empty_UNCONNECTED\,
axi_w_prog_empty_thresh(3 downto 0) => B"0000",
axi_w_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_full_UNCONNECTED\,
axi_w_prog_full_thresh(3 downto 0) => B"0000",
axi_w_rd_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_rd_data_count_UNCONNECTED\(4 downto 0),
axi_w_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_sbiterr_UNCONNECTED\,
axi_w_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_underflow_UNCONNECTED\,
axi_w_wr_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_wr_data_count_UNCONNECTED\(4 downto 0),
axis_data_count(10 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_data_count_UNCONNECTED\(10 downto 0),
axis_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_dbiterr_UNCONNECTED\,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_overflow_UNCONNECTED\,
axis_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_empty_UNCONNECTED\,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_full_UNCONNECTED\,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_rd_data_count_UNCONNECTED\(10 downto 0),
axis_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_sbiterr_UNCONNECTED\,
axis_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_underflow_UNCONNECTED\,
axis_wr_data_count(10 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_wr_data_count_UNCONNECTED\(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(9 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_data_count_UNCONNECTED\(9 downto 0),
dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dbiterr_UNCONNECTED\,
din(17 downto 0) => B"000000000000000000",
dout(17 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dout_UNCONNECTED\(17 downto 0),
empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_empty_UNCONNECTED\,
full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_full_UNCONNECTED\,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => m_axi_aclk,
m_aclk_en => '1',
m_axi_araddr(27 downto 0) => m_axi_araddr(27 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_arid(0) => m_axi_arid(0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_aruser(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_aruser_UNCONNECTED\(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(27 downto 0) => m_axi_awaddr(27 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awid(0) => m_axi_awid(0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awlock(0) => m_axi_awlock(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => m_axi_awregion(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awuser(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_awuser_UNCONNECTED\(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(0) => m_axi_bid(0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rid(0) => m_axi_rid(0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(127 downto 0) => m_axi_wdata(127 downto 0),
m_axi_wid(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wid_UNCONNECTED\(0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(15 downto 0) => m_axi_wstrb(15 downto 0),
m_axi_wuser(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wuser_UNCONNECTED\(0),
m_axi_wvalid => m_axi_wvalid,
m_axis_tdata(7 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdata_UNCONNECTED\(7 downto 0),
m_axis_tdest(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdest_UNCONNECTED\(0),
m_axis_tid(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tid_UNCONNECTED\(0),
m_axis_tkeep(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tkeep_UNCONNECTED\(0),
m_axis_tlast => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tlast_UNCONNECTED\,
m_axis_tready => '0',
m_axis_tstrb(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tstrb_UNCONNECTED\(0),
m_axis_tuser(3 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tuser_UNCONNECTED\(3 downto 0),
m_axis_tvalid => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tvalid_UNCONNECTED\,
overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_overflow_UNCONNECTED\,
prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_empty_UNCONNECTED\,
prog_empty_thresh(9 downto 0) => B"0000000000",
prog_empty_thresh_assert(9 downto 0) => B"0000000000",
prog_empty_thresh_negate(9 downto 0) => B"0000000000",
prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_full_UNCONNECTED\,
prog_full_thresh(9 downto 0) => B"0000000000",
prog_full_thresh_assert(9 downto 0) => B"0000000000",
prog_full_thresh_negate(9 downto 0) => B"0000000000",
rd_clk => '0',
rd_data_count(9 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_data_count_UNCONNECTED\(9 downto 0),
rd_en => '0',
rd_rst => '0',
rd_rst_busy => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_rst_busy_UNCONNECTED\,
rst => '0',
s_aclk => s_axi_aclk,
s_aclk_en => '1',
s_aresetn => async_conv_reset_n,
s_axi_araddr(27 downto 0) => s_axi_araddr(27 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(0) => s_axi_arid(0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(27 downto 0) => s_axi_awaddr(27 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(0) => s_axi_awid(0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_buser_UNCONNECTED\(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(127 downto 0) => s_axi_rdata(127 downto 0),
s_axi_rid(0) => s_axi_rid(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_ruser_UNCONNECTED\(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(127 downto 0) => s_axi_wdata(127 downto 0),
s_axi_wid(0) => '0',
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(15 downto 0) => s_axi_wstrb(15 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid,
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axis_tready_UNCONNECTED\,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_sbiterr_UNCONNECTED\,
sleep => '0',
srst => '0',
underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_underflow_UNCONNECTED\,
valid => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_valid_UNCONNECTED\,
wr_ack => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_ack_UNCONNECTED\,
wr_clk => '0',
wr_data_count(9 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_data_count_UNCONNECTED\(9 downto 0),
wr_en => '0',
wr_rst => '0',
wr_rst_busy => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_rst_busy_UNCONNECTED\
);
\gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_aresetn,
I1 => m_axi_aresetn,
O => async_conv_reset_n
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 27 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 27 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_auto_cc_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_auto_cc_0 : entity is "system_auto_cc_0,axi_clock_converter_v2_1_10_axi_clock_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_cc_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_auto_cc_0 : entity is "axi_clock_converter_v2_1_10_axi_clock_converter,Vivado 2016.4";
end system_auto_cc_0;
architecture STRUCTURE of system_auto_cc_0 is
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ARADDR_RIGHT : integer;
attribute C_ARADDR_RIGHT of inst : label is 29;
attribute C_ARADDR_WIDTH : integer;
attribute C_ARADDR_WIDTH of inst : label is 28;
attribute C_ARBURST_RIGHT : integer;
attribute C_ARBURST_RIGHT of inst : label is 16;
attribute C_ARBURST_WIDTH : integer;
attribute C_ARBURST_WIDTH of inst : label is 2;
attribute C_ARCACHE_RIGHT : integer;
attribute C_ARCACHE_RIGHT of inst : label is 11;
attribute C_ARCACHE_WIDTH : integer;
attribute C_ARCACHE_WIDTH of inst : label is 4;
attribute C_ARID_RIGHT : integer;
attribute C_ARID_RIGHT of inst : label is 57;
attribute C_ARID_WIDTH : integer;
attribute C_ARID_WIDTH of inst : label is 1;
attribute C_ARLEN_RIGHT : integer;
attribute C_ARLEN_RIGHT of inst : label is 21;
attribute C_ARLEN_WIDTH : integer;
attribute C_ARLEN_WIDTH of inst : label is 8;
attribute C_ARLOCK_RIGHT : integer;
attribute C_ARLOCK_RIGHT of inst : label is 15;
attribute C_ARLOCK_WIDTH : integer;
attribute C_ARLOCK_WIDTH of inst : label is 1;
attribute C_ARPROT_RIGHT : integer;
attribute C_ARPROT_RIGHT of inst : label is 8;
attribute C_ARPROT_WIDTH : integer;
attribute C_ARPROT_WIDTH of inst : label is 3;
attribute C_ARQOS_RIGHT : integer;
attribute C_ARQOS_RIGHT of inst : label is 0;
attribute C_ARQOS_WIDTH : integer;
attribute C_ARQOS_WIDTH of inst : label is 4;
attribute C_ARREGION_RIGHT : integer;
attribute C_ARREGION_RIGHT of inst : label is 4;
attribute C_ARREGION_WIDTH : integer;
attribute C_ARREGION_WIDTH of inst : label is 4;
attribute C_ARSIZE_RIGHT : integer;
attribute C_ARSIZE_RIGHT of inst : label is 18;
attribute C_ARSIZE_WIDTH : integer;
attribute C_ARSIZE_WIDTH of inst : label is 3;
attribute C_ARUSER_RIGHT : integer;
attribute C_ARUSER_RIGHT of inst : label is 0;
attribute C_ARUSER_WIDTH : integer;
attribute C_ARUSER_WIDTH of inst : label is 0;
attribute C_AR_WIDTH : integer;
attribute C_AR_WIDTH of inst : label is 58;
attribute C_AWADDR_RIGHT : integer;
attribute C_AWADDR_RIGHT of inst : label is 29;
attribute C_AWADDR_WIDTH : integer;
attribute C_AWADDR_WIDTH of inst : label is 28;
attribute C_AWBURST_RIGHT : integer;
attribute C_AWBURST_RIGHT of inst : label is 16;
attribute C_AWBURST_WIDTH : integer;
attribute C_AWBURST_WIDTH of inst : label is 2;
attribute C_AWCACHE_RIGHT : integer;
attribute C_AWCACHE_RIGHT of inst : label is 11;
attribute C_AWCACHE_WIDTH : integer;
attribute C_AWCACHE_WIDTH of inst : label is 4;
attribute C_AWID_RIGHT : integer;
attribute C_AWID_RIGHT of inst : label is 57;
attribute C_AWID_WIDTH : integer;
attribute C_AWID_WIDTH of inst : label is 1;
attribute C_AWLEN_RIGHT : integer;
attribute C_AWLEN_RIGHT of inst : label is 21;
attribute C_AWLEN_WIDTH : integer;
attribute C_AWLEN_WIDTH of inst : label is 8;
attribute C_AWLOCK_RIGHT : integer;
attribute C_AWLOCK_RIGHT of inst : label is 15;
attribute C_AWLOCK_WIDTH : integer;
attribute C_AWLOCK_WIDTH of inst : label is 1;
attribute C_AWPROT_RIGHT : integer;
attribute C_AWPROT_RIGHT of inst : label is 8;
attribute C_AWPROT_WIDTH : integer;
attribute C_AWPROT_WIDTH of inst : label is 3;
attribute C_AWQOS_RIGHT : integer;
attribute C_AWQOS_RIGHT of inst : label is 0;
attribute C_AWQOS_WIDTH : integer;
attribute C_AWQOS_WIDTH of inst : label is 4;
attribute C_AWREGION_RIGHT : integer;
attribute C_AWREGION_RIGHT of inst : label is 4;
attribute C_AWREGION_WIDTH : integer;
attribute C_AWREGION_WIDTH of inst : label is 4;
attribute C_AWSIZE_RIGHT : integer;
attribute C_AWSIZE_RIGHT of inst : label is 18;
attribute C_AWSIZE_WIDTH : integer;
attribute C_AWSIZE_WIDTH of inst : label is 3;
attribute C_AWUSER_RIGHT : integer;
attribute C_AWUSER_RIGHT of inst : label is 0;
attribute C_AWUSER_WIDTH : integer;
attribute C_AWUSER_WIDTH of inst : label is 0;
attribute C_AW_WIDTH : integer;
attribute C_AW_WIDTH of inst : label is 58;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 28;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 128;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 1;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of inst : label is 1;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_BID_RIGHT : integer;
attribute C_BID_RIGHT of inst : label is 2;
attribute C_BID_WIDTH : integer;
attribute C_BID_WIDTH of inst : label is 1;
attribute C_BRESP_RIGHT : integer;
attribute C_BRESP_RIGHT of inst : label is 0;
attribute C_BRESP_WIDTH : integer;
attribute C_BRESP_WIDTH of inst : label is 2;
attribute C_BUSER_RIGHT : integer;
attribute C_BUSER_RIGHT of inst : label is 0;
attribute C_BUSER_WIDTH : integer;
attribute C_BUSER_WIDTH of inst : label is 0;
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of inst : label is 3;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "artix7";
attribute C_FIFO_AR_WIDTH : integer;
attribute C_FIFO_AR_WIDTH of inst : label is 58;
attribute C_FIFO_AW_WIDTH : integer;
attribute C_FIFO_AW_WIDTH of inst : label is 58;
attribute C_FIFO_B_WIDTH : integer;
attribute C_FIFO_B_WIDTH of inst : label is 3;
attribute C_FIFO_R_WIDTH : integer;
attribute C_FIFO_R_WIDTH of inst : label is 132;
attribute C_FIFO_W_WIDTH : integer;
attribute C_FIFO_W_WIDTH of inst : label is 145;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of inst : label is 2;
attribute C_RDATA_RIGHT : integer;
attribute C_RDATA_RIGHT of inst : label is 3;
attribute C_RDATA_WIDTH : integer;
attribute C_RDATA_WIDTH of inst : label is 128;
attribute C_RID_RIGHT : integer;
attribute C_RID_RIGHT of inst : label is 131;
attribute C_RID_WIDTH : integer;
attribute C_RID_WIDTH of inst : label is 1;
attribute C_RLAST_RIGHT : integer;
attribute C_RLAST_RIGHT of inst : label is 0;
attribute C_RLAST_WIDTH : integer;
attribute C_RLAST_WIDTH of inst : label is 1;
attribute C_RRESP_RIGHT : integer;
attribute C_RRESP_RIGHT of inst : label is 1;
attribute C_RRESP_WIDTH : integer;
attribute C_RRESP_WIDTH of inst : label is 2;
attribute C_RUSER_RIGHT : integer;
attribute C_RUSER_RIGHT of inst : label is 0;
attribute C_RUSER_WIDTH : integer;
attribute C_RUSER_WIDTH of inst : label is 0;
attribute C_R_WIDTH : integer;
attribute C_R_WIDTH of inst : label is 132;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of inst : label is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of inst : label is 1;
attribute C_WDATA_RIGHT : integer;
attribute C_WDATA_RIGHT of inst : label is 17;
attribute C_WDATA_WIDTH : integer;
attribute C_WDATA_WIDTH of inst : label is 128;
attribute C_WID_RIGHT : integer;
attribute C_WID_RIGHT of inst : label is 145;
attribute C_WID_WIDTH : integer;
attribute C_WID_WIDTH of inst : label is 0;
attribute C_WLAST_RIGHT : integer;
attribute C_WLAST_RIGHT of inst : label is 0;
attribute C_WLAST_WIDTH : integer;
attribute C_WLAST_WIDTH of inst : label is 1;
attribute C_WSTRB_RIGHT : integer;
attribute C_WSTRB_RIGHT of inst : label is 1;
attribute C_WSTRB_WIDTH : integer;
attribute C_WSTRB_WIDTH of inst : label is 16;
attribute C_WUSER_RIGHT : integer;
attribute C_WUSER_RIGHT of inst : label is 0;
attribute C_WUSER_WIDTH : integer;
attribute C_WUSER_WIDTH of inst : label is 0;
attribute C_W_WIDTH : integer;
attribute C_W_WIDTH of inst : label is 145;
attribute P_ACLK_RATIO : integer;
attribute P_ACLK_RATIO of inst : label is 2;
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_FULLY_REG : integer;
attribute P_FULLY_REG of inst : label is 1;
attribute P_LIGHT_WT : integer;
attribute P_LIGHT_WT of inst : label is 0;
attribute P_LUTRAM_ASYNC : integer;
attribute P_LUTRAM_ASYNC of inst : label is 12;
attribute P_ROUNDING_OFFSET : integer;
attribute P_ROUNDING_OFFSET of inst : label is 0;
attribute P_SI_LT_MI : string;
attribute P_SI_LT_MI of inst : label is "1'b1";
attribute downgradeipidentifiedwarnings of inst : label is "yes";
begin
inst: entity work.system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter
port map (
m_axi_aclk => m_axi_aclk,
m_axi_araddr(27 downto 0) => m_axi_araddr(27 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_aresetn => m_axi_aresetn,
m_axi_arid(0) => m_axi_arid(0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(27 downto 0) => m_axi_awaddr(27 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awid(0) => m_axi_awid(0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awlock(0) => m_axi_awlock(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => m_axi_awregion(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(0) => m_axi_bid(0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rid(0) => m_axi_rid(0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(127 downto 0) => m_axi_wdata(127 downto 0),
m_axi_wid(0) => NLW_inst_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(15 downto 0) => m_axi_wstrb(15 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(27 downto 0) => s_axi_araddr(27 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => s_axi_arid(0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(27 downto 0) => s_axi_awaddr(27 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(0) => s_axi_awid(0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(127 downto 0) => s_axi_rdata(127 downto 0),
s_axi_rid(0) => s_axi_rid(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(127 downto 0) => s_axi_wdata(127 downto 0),
s_axi_wid(0) => '0',
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(15 downto 0) => s_axi_wstrb(15 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
apache-2.0
|
259043862bccea03ab608e0e1a4d164b
| 0.566406 | 2.690228 | false | false | false | false |
daniw/add
|
edk/IVK_HW/t01_hello/hdl/elaborate/clock_generator_0_v4_03_a/hdl/vhdl/clock_generator.vhd
| 1 | 36,357 |
------------------------------------------------------------------------------
-- /home/daniw/data/studium/sem6/add/edk/IVK_HW/t01_hello/hdl/elaborate/clock_generator_0_v4_03_a/hdl/vhdl/clock_generator.vhd
------------------------------------------------------------------------------
-- ClkGen Wrapper HDL file generated by ClkGen's TCL generator
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
library Unisim;
use Unisim.vcomponents.all;
library clock_generator_v4_03_a;
use clock_generator_v4_03_a.all;
entity clock_generator is
generic (
C_FAMILY : string := "spartan6" ;
C_DEVICE : string := "6slx150t";
C_PACKAGE : string := "fgg676";
C_SPEEDGRADE : string := "-3";
C_CLK_GEN : string := "PASSED"
);
port (
-- clock generation
CLKIN : in std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUT6 : out std_logic;
CLKOUT7 : out std_logic;
CLKOUT8 : out std_logic;
CLKOUT9 : out std_logic;
CLKOUT10 : out std_logic;
CLKOUT11 : out std_logic;
CLKOUT12 : out std_logic;
CLKOUT13 : out std_logic;
CLKOUT14 : out std_logic;
CLKOUT15 : out std_logic;
-- external feedback
CLKFBIN : in std_logic;
CLKFBOUT : out std_logic;
-- variable phase shift
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSDONE : out std_logic;
-- reset
RST : in std_logic;
LOCKED : out std_logic
);
end clock_generator;
architecture STRUCTURE of clock_generator is
----------------------------------------------------------------------------
-- Components ( copy from entity, exact the same in low level parameters )
----------------------------------------------------------------------------
component pll_module is
generic (
C_BANDWIDTH : string := "OPTIMIZED";
C_CLKFBOUT_MULT : integer := 1;
C_CLKFBOUT_PHASE : real := 0.0;
C_CLKIN1_PERIOD : real := 0.000;
-- C_CLKIN2_PERIOD : real := 0.000;
C_CLKOUT0_DIVIDE : integer := 1;
C_CLKOUT0_DUTY_CYCLE : real := 0.5;
C_CLKOUT0_PHASE : real := 0.0;
C_CLKOUT1_DIVIDE : integer := 1;
C_CLKOUT1_DUTY_CYCLE : real := 0.5;
C_CLKOUT1_PHASE : real := 0.0;
C_CLKOUT2_DIVIDE : integer := 1;
C_CLKOUT2_DUTY_CYCLE : real := 0.5;
C_CLKOUT2_PHASE : real := 0.0;
C_CLKOUT3_DIVIDE : integer := 1;
C_CLKOUT3_DUTY_CYCLE : real := 0.5;
C_CLKOUT3_PHASE : real := 0.0;
C_CLKOUT4_DIVIDE : integer := 1;
C_CLKOUT4_DUTY_CYCLE : real := 0.5;
C_CLKOUT4_PHASE : real := 0.0;
C_CLKOUT5_DIVIDE : integer := 1;
C_CLKOUT5_DUTY_CYCLE : real := 0.5;
C_CLKOUT5_PHASE : real := 0.0;
C_COMPENSATION : string := "SYSTEM_SYNCHRONOUS";
C_DIVCLK_DIVIDE : integer := 1;
-- C_EN_REL : boolean := false;
-- C_PLL_PMCD_MODE : boolean := false;
C_REF_JITTER : real := 0.100;
C_RESET_ON_LOSS_OF_LOCK : boolean := false;
C_RST_DEASSERT_CLK : string := "CLKIN1";
C_CLKOUT0_DESKEW_ADJUST : string := "NONE";
C_CLKOUT1_DESKEW_ADJUST : string := "NONE";
C_CLKOUT2_DESKEW_ADJUST : string := "PPC";
C_CLKOUT3_DESKEW_ADJUST : string := "PPC";
C_CLKOUT4_DESKEW_ADJUST : string := "PPC";
C_CLKOUT5_DESKEW_ADJUST : string := "PPC";
C_CLKFBOUT_DESKEW_ADJUST : string := "PPC";
C_CLKIN1_BUF : boolean := false;
-- C_CLKIN2_BUF : boolean := false;
C_CLKFBOUT_BUF : boolean := false;
C_CLKOUT0_BUF : boolean := false;
C_CLKOUT1_BUF : boolean := false;
C_CLKOUT2_BUF : boolean := false;
C_CLKOUT3_BUF : boolean := false;
C_CLKOUT4_BUF : boolean := false;
C_CLKOUT5_BUF : boolean := false;
C_EXT_RESET_HIGH : integer := 1;
C_FAMILY : string := "spartan6"
);
port (
CLKFBDCM : out std_logic;
CLKFBOUT : out std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUTDCM0 : out std_logic;
CLKOUTDCM1 : out std_logic;
CLKOUTDCM2 : out std_logic;
CLKOUTDCM3 : out std_logic;
CLKOUTDCM4 : out std_logic;
CLKOUTDCM5 : out std_logic;
-- DO : out std_logic_vector (15 downto 0);
-- DRDY : out std_logic;
LOCKED : out std_logic;
CLKFBIN : in std_logic;
CLKIN1 : in std_logic;
-- CLKIN2 : in std_logic;
-- CLKINSEL : in std_logic;
-- DADDR : in std_logic_vector (4 downto 0);
-- DCLK : in std_logic;
-- DEN : in std_logic;
-- DI : in std_logic_vector (15 downto 0);
-- DWE : in std_logic;
-- REL : in std_logic;
RST : in std_logic
);
end component;
----------------------------------------------------------------------------
-- Functions
----------------------------------------------------------------------------
-- Note : The string functions are put here to remove dependency to other pcore level libraries
function UpperCase_Char(char : character) return character is
begin
-- If char is not an upper case letter then return char
if char < 'a' or char > 'z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'a' => return 'A'; when 'b' => return 'B'; when 'c' => return 'C'; when 'd' => return 'D';
when 'e' => return 'E'; when 'f' => return 'F'; when 'g' => return 'G'; when 'h' => return 'H';
when 'i' => return 'I'; when 'j' => return 'J'; when 'k' => return 'K'; when 'l' => return 'L';
when 'm' => return 'M'; when 'n' => return 'N'; when 'o' => return 'O'; when 'p' => return 'P';
when 'q' => return 'Q'; when 'r' => return 'R'; when 's' => return 'S'; when 't' => return 'T';
when 'u' => return 'U'; when 'v' => return 'V'; when 'w' => return 'W'; when 'x' => return 'X';
when 'y' => return 'Y'; when 'z' => return 'Z';
when others => return char;
end case;
end UpperCase_Char;
function UpperCase_String (s : string) return string is
variable res : string(s'range);
begin -- function LoweerCase_String
for I in s'range loop
res(I) := UpperCase_Char(s(I));
end loop; -- I
return res;
end function UpperCase_String;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function equalString( str1, str2 : string ) return boolean is
constant len1 : integer := str1'length;
constant len2 : integer := str2'length;
variable equal : boolean := true;
begin
if not (len1 = len2) then
equal := false;
else
for i in str1'range loop
if not (UpperCase_Char(str1(i)) = UpperCase_Char(str2(i))) then
equal := false;
end if;
end loop;
end if;
return equal;
end equalString;
----------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------
-- signals: gnd
signal net_gnd0 : std_logic;
signal net_gnd1 : std_logic_vector(0 to 0);
signal net_gnd16 : std_logic_vector(0 to 15);
-- signals: vdd
signal net_vdd0 : std_logic;
-- signals : PLL0 wrapper
signal SIG_PLL0_CLKFBDCM : std_logic;
signal SIG_PLL0_CLKFBOUT : std_logic;
signal SIG_PLL0_CLKOUT0 : std_logic;
signal SIG_PLL0_CLKOUT1 : std_logic;
signal SIG_PLL0_CLKOUT2 : std_logic;
signal SIG_PLL0_CLKOUT3 : std_logic;
signal SIG_PLL0_CLKOUT4 : std_logic;
signal SIG_PLL0_CLKOUT5 : std_logic;
signal SIG_PLL0_CLKOUTDCM0 : std_logic;
signal SIG_PLL0_CLKOUTDCM1 : std_logic;
signal SIG_PLL0_CLKOUTDCM2 : std_logic;
signal SIG_PLL0_CLKOUTDCM3 : std_logic;
signal SIG_PLL0_CLKOUTDCM4 : std_logic;
signal SIG_PLL0_CLKOUTDCM5 : std_logic;
signal SIG_PLL0_LOCKED : std_logic;
signal SIG_PLL0_CLKFBIN : std_logic;
signal SIG_PLL0_CLKIN1 : std_logic;
signal SIG_PLL0_RST : std_logic;
signal SIG_PLL0_CLKFBOUT_BUF : std_logic;
signal SIG_PLL0_CLKOUT0_BUF : std_logic;
signal SIG_PLL0_CLKOUT1_BUF : std_logic;
signal SIG_PLL0_CLKOUT2_BUF : std_logic;
signal SIG_PLL0_CLKOUT3_BUF : std_logic;
signal SIG_PLL0_CLKOUT4_BUF : std_logic;
signal SIG_PLL0_CLKOUT5_BUF : std_logic;
begin
----------------------------------------------------------------------------
-- GND and VCC signals
----------------------------------------------------------------------------
net_gnd0 <= '0';
net_gnd1(0 to 0) <= B"0";
net_gnd16(0 to 15) <= B"0000000000000000";
net_vdd0 <= '1';
----------------------------------------------------------------------------
-- DCM wrappers
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLL wrappers
----------------------------------------------------------------------------
-- PLL0 wrapper
PLL0_INST : pll_module
generic map (
C_BANDWIDTH => "OPTIMIZED",
C_CLKFBOUT_MULT => 10,
C_CLKFBOUT_PHASE => 0.0,
C_CLKIN1_PERIOD => 10.000000,
C_CLKOUT0_DIVIDE => 20,
C_CLKOUT0_DUTY_CYCLE => 0.5,
C_CLKOUT0_PHASE => 0.0000,
C_CLKOUT1_DIVIDE => 1,
C_CLKOUT1_DUTY_CYCLE => 0.5,
C_CLKOUT1_PHASE => 0.0,
C_CLKOUT2_DIVIDE => 1,
C_CLKOUT2_DUTY_CYCLE => 0.5,
C_CLKOUT2_PHASE => 0.0,
C_CLKOUT3_DIVIDE => 1,
C_CLKOUT3_DUTY_CYCLE => 0.5,
C_CLKOUT3_PHASE => 0.0,
C_CLKOUT4_DIVIDE => 1,
C_CLKOUT4_DUTY_CYCLE => 0.5,
C_CLKOUT4_PHASE => 0.0,
C_CLKOUT5_DIVIDE => 1,
C_CLKOUT5_DUTY_CYCLE => 0.5,
C_CLKOUT5_PHASE => 0.0,
C_COMPENSATION => "SYSTEM_SYNCHRONOUS",
C_DIVCLK_DIVIDE => 1,
C_REF_JITTER => 0.100,
C_RESET_ON_LOSS_OF_LOCK => false,
C_RST_DEASSERT_CLK => "CLKIN1",
C_CLKOUT0_DESKEW_ADJUST => "NONE",
C_CLKOUT1_DESKEW_ADJUST => "NONE",
C_CLKOUT2_DESKEW_ADJUST => "PPC",
C_CLKOUT3_DESKEW_ADJUST => "PPC",
C_CLKOUT4_DESKEW_ADJUST => "PPC",
C_CLKOUT5_DESKEW_ADJUST => "PPC",
C_CLKFBOUT_DESKEW_ADJUST => "PPC",
C_CLKIN1_BUF => false,
C_CLKFBOUT_BUF => false,
C_CLKOUT0_BUF => false,
C_CLKOUT1_BUF => false,
C_CLKOUT2_BUF => false,
C_CLKOUT3_BUF => false,
C_CLKOUT4_BUF => false,
C_CLKOUT5_BUF => false,
C_EXT_RESET_HIGH => 1,
C_FAMILY => "spartan6"
)
port map (
CLKFBDCM => SIG_PLL0_CLKFBDCM,
CLKFBOUT => SIG_PLL0_CLKFBOUT,
CLKOUT0 => SIG_PLL0_CLKOUT0,
CLKOUT1 => SIG_PLL0_CLKOUT1,
CLKOUT2 => SIG_PLL0_CLKOUT2,
CLKOUT3 => SIG_PLL0_CLKOUT3,
CLKOUT4 => SIG_PLL0_CLKOUT4,
CLKOUT5 => SIG_PLL0_CLKOUT5,
CLKOUTDCM0 => SIG_PLL0_CLKOUTDCM0,
CLKOUTDCM1 => SIG_PLL0_CLKOUTDCM1,
CLKOUTDCM2 => SIG_PLL0_CLKOUTDCM2,
CLKOUTDCM3 => SIG_PLL0_CLKOUTDCM3,
CLKOUTDCM4 => SIG_PLL0_CLKOUTDCM4,
CLKOUTDCM5 => SIG_PLL0_CLKOUTDCM5,
-- DO
-- DRDY
LOCKED => SIG_PLL0_LOCKED,
CLKFBIN => SIG_PLL0_CLKFBIN,
CLKIN1 => SIG_PLL0_CLKIN1,
-- CLKIN2
-- CLKINSEL
-- DADDR
-- DCLK
-- DEN
-- DI
-- DWE
-- REL
RST => SIG_PLL0_RST
);
-- wrapper of clkout : CLKOUT0
PLL0_CLKOUT0_BUFG_INST : BUFG
port map (
I => SIG_PLL0_CLKOUT0,
O => SIG_PLL0_CLKOUT0_BUF
);
-- wrapper of clkout : CLKOUT1
SIG_PLL0_CLKOUT1_BUF <= SIG_PLL0_CLKOUT1;
-- wrapper of clkout : CLKOUT2
SIG_PLL0_CLKOUT2_BUF <= SIG_PLL0_CLKOUT2;
-- wrapper of clkout : CLKOUT3
SIG_PLL0_CLKOUT3_BUF <= SIG_PLL0_CLKOUT3;
-- wrapper of clkout : CLKOUT4
SIG_PLL0_CLKOUT4_BUF <= SIG_PLL0_CLKOUT4;
-- wrapper of clkout : CLKOUT5
SIG_PLL0_CLKOUT5_BUF <= SIG_PLL0_CLKOUT5;
-- wrapper of clkout : CLKFBOUT
PLL0_CLKFBOUT_BUFG_INST : BUFG
port map (
I => SIG_PLL0_CLKFBOUT,
O => SIG_PLL0_CLKFBOUT_BUF
);
----------------------------------------------------------------------------
-- MMCM wrappers
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLLE wrappers
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- DCMs CLKIN, CLKFB and RST signal connection
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLLs CLKIN1, CLKFBIN and RST signal connection
----------------------------------------------------------------------------
-- PLL0 CLKIN1
SIG_PLL0_CLKIN1 <= CLKIN;
-- PLL0 CLKFBIN
SIG_PLL0_CLKFBIN <= SIG_PLL0_CLKFBOUT;
-- PLL0 RST
SIG_PLL0_RST <= RST;
----------------------------------------------------------------------------
-- MMCMs CLKIN1, CLKFBIN, RST and Variable_Phase_Control signal connection
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- PLLEs CLKIN1, CLKFBIN, RST and Variable_Phase_Control signal connection
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- CLKGEN CLKOUT, CLKFBOUT and LOCKED signal connection
----------------------------------------------------------------------------
-- CLKGEN CLKOUT
CLKOUT0 <= SIG_PLL0_CLKOUT0_BUF;
CLKOUT1 <= '0';
CLKOUT2 <= '0';
CLKOUT3 <= '0';
CLKOUT4 <= '0';
CLKOUT5 <= '0';
CLKOUT6 <= '0';
CLKOUT7 <= '0';
CLKOUT8 <= '0';
CLKOUT9 <= '0';
CLKOUT10 <= '0';
CLKOUT11 <= '0';
CLKOUT12 <= '0';
CLKOUT13 <= '0';
CLKOUT14 <= '0';
CLKOUT15 <= '0';
-- CLKGEN CLKFBOUT
-- CLKGEN LOCKED
LOCKED <= SIG_PLL0_LOCKED;
end architecture STRUCTURE;
------------------------------------------------------------------------------
-- High level parameters
------------------------------------------------------------------------------
-- C_CLK_GEN = PASSED
-- C_ELABORATE_DIR =
-- C_ELABORATE_RES = NOT_SET
-- C_FAMILY = spartan6
-- C_DEVICE = 6slx150t
-- C_PACKAGE = fgg676
-- C_SPEEDGRADE = -3
----------------------------------------
-- C_CLKIN_FREQ = 100000000
-- C_CLKOUT0_FREQ = 50000000
-- C_CLKOUT0_PHASE = 0
-- C_CLKOUT0_GROUP = NONE
-- C_CLKOUT0_BUF = TRUE
-- C_CLKOUT0_VARIABLE_PHASE = FALSE
-- C_CLKOUT1_FREQ = 0
-- C_CLKOUT1_PHASE = 0
-- C_CLKOUT1_GROUP = NONE
-- C_CLKOUT1_BUF = TRUE
-- C_CLKOUT1_VARIABLE_PHASE = FALSE
-- C_CLKOUT2_FREQ = 0
-- C_CLKOUT2_PHASE = 0
-- C_CLKOUT2_GROUP = NONE
-- C_CLKOUT2_BUF = TRUE
-- C_CLKOUT2_VARIABLE_PHASE = FALSE
-- C_CLKOUT3_FREQ = 0
-- C_CLKOUT3_PHASE = 0
-- C_CLKOUT3_GROUP = NONE
-- C_CLKOUT3_BUF = TRUE
-- C_CLKOUT3_VARIABLE_PHASE = FALSE
-- C_CLKOUT4_FREQ = 0
-- C_CLKOUT4_PHASE = 0
-- C_CLKOUT4_GROUP = NONE
-- C_CLKOUT4_BUF = TRUE
-- C_CLKOUT4_VARIABLE_PHASE = FALSE
-- C_CLKOUT5_FREQ = 0
-- C_CLKOUT5_PHASE = 0
-- C_CLKOUT5_GROUP = NONE
-- C_CLKOUT5_BUF = TRUE
-- C_CLKOUT5_VARIABLE_PHASE = FALSE
-- C_CLKOUT6_FREQ = 0
-- C_CLKOUT6_PHASE = 0
-- C_CLKOUT6_GROUP = NONE
-- C_CLKOUT6_BUF = TRUE
-- C_CLKOUT6_VARIABLE_PHASE = FALSE
-- C_CLKOUT7_FREQ = 0
-- C_CLKOUT7_PHASE = 0
-- C_CLKOUT7_GROUP = NONE
-- C_CLKOUT7_BUF = TRUE
-- C_CLKOUT7_VARIABLE_PHASE = FALSE
-- C_CLKOUT8_FREQ = 0
-- C_CLKOUT8_PHASE = 0
-- C_CLKOUT8_GROUP = NONE
-- C_CLKOUT8_BUF = TRUE
-- C_CLKOUT8_VARIABLE_PHASE = FALSE
-- C_CLKOUT9_FREQ = 0
-- C_CLKOUT9_PHASE = 0
-- C_CLKOUT9_GROUP = NONE
-- C_CLKOUT9_BUF = TRUE
-- C_CLKOUT9_VARIABLE_PHASE = FALSE
-- C_CLKOUT10_FREQ = 0
-- C_CLKOUT10_PHASE = 0
-- C_CLKOUT10_GROUP = NONE
-- C_CLKOUT10_BUF = TRUE
-- C_CLKOUT10_VARIABLE_PHASE = FALSE
-- C_CLKOUT11_FREQ = 0
-- C_CLKOUT11_PHASE = 0
-- C_CLKOUT11_GROUP = NONE
-- C_CLKOUT11_BUF = TRUE
-- C_CLKOUT11_VARIABLE_PHASE = FALSE
-- C_CLKOUT12_FREQ = 0
-- C_CLKOUT12_PHASE = 0
-- C_CLKOUT12_GROUP = NONE
-- C_CLKOUT12_BUF = TRUE
-- C_CLKOUT12_VARIABLE_PHASE = FALSE
-- C_CLKOUT13_FREQ = 0
-- C_CLKOUT13_PHASE = 0
-- C_CLKOUT13_GROUP = NONE
-- C_CLKOUT13_BUF = TRUE
-- C_CLKOUT13_VARIABLE_PHASE = FALSE
-- C_CLKOUT14_FREQ = 0
-- C_CLKOUT14_PHASE = 0
-- C_CLKOUT14_GROUP = NONE
-- C_CLKOUT14_BUF = TRUE
-- C_CLKOUT14_VARIABLE_PHASE = FALSE
-- C_CLKOUT15_FREQ = 0
-- C_CLKOUT15_PHASE = 0
-- C_CLKOUT15_GROUP = NONE
-- C_CLKOUT15_BUF = TRUE
-- C_CLKOUT15_VARIABLE_PHASE = FALSE
----------------------------------------
-- C_CLKFBIN_FREQ = 0
-- C_CLKFBIN_DESKEW = NONE
-- C_CLKFBOUT_FREQ = 0
-- C_CLKFBOUT_GROUP = NONE
-- C_CLKFBOUT_BUF = TRUE
----------------------------------------
-- C_PSDONE_GROUP = NONE
------------------------------------------------------------------------------
-- Low level parameters
------------------------------------------------------------------------------
-- C_CLKOUT0_MODULE = PLL0
-- C_CLKOUT0_PORT = CLKOUT0B
-- C_CLKOUT1_MODULE = NONE
-- C_CLKOUT1_PORT = NONE
-- C_CLKOUT2_MODULE = NONE
-- C_CLKOUT2_PORT = NONE
-- C_CLKOUT3_MODULE = NONE
-- C_CLKOUT3_PORT = NONE
-- C_CLKOUT4_MODULE = NONE
-- C_CLKOUT4_PORT = NONE
-- C_CLKOUT5_MODULE = NONE
-- C_CLKOUT5_PORT = NONE
-- C_CLKOUT6_MODULE = NONE
-- C_CLKOUT6_PORT = NONE
-- C_CLKOUT7_MODULE = NONE
-- C_CLKOUT7_PORT = NONE
-- C_CLKOUT8_MODULE = NONE
-- C_CLKOUT8_PORT = NONE
-- C_CLKOUT9_MODULE = NONE
-- C_CLKOUT9_PORT = NONE
-- C_CLKOUT10_MODULE = NONE
-- C_CLKOUT10_PORT = NONE
-- C_CLKOUT11_MODULE = NONE
-- C_CLKOUT11_PORT = NONE
-- C_CLKOUT12_MODULE = NONE
-- C_CLKOUT12_PORT = NONE
-- C_CLKOUT13_MODULE = NONE
-- C_CLKOUT13_PORT = NONE
-- C_CLKOUT14_MODULE = NONE
-- C_CLKOUT14_PORT = NONE
-- C_CLKOUT15_MODULE = NONE
-- C_CLKOUT15_PORT = NONE
----------------------------------------
-- C_CLKFBOUT_MODULE = NONE
-- C_CLKFBOUT_PORT = NONE
-- C_CLKFBOUT_get_clkgen_dcm_default_params = NONE
----------------------------------------
-- C_PSDONE_MODULE = NONE
----------------------------------------
-- C_DCM0_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM0_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM0_DUTY_CYCLE_CORRECTION = true
-- C_DCM0_CLKIN_DIVIDE_BY_2 = false
-- C_DCM0_CLK_FEEDBACK = "1X"
-- C_DCM0_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM0_DSS_MODE = "NONE"
-- C_DCM0_STARTUP_WAIT = false
-- C_DCM0_PHASE_SHIFT = 0
-- C_DCM0_CLKFX_MULTIPLY = 4
-- C_DCM0_CLKFX_DIVIDE = 1
-- C_DCM0_CLKDV_DIVIDE = 2.0
-- C_DCM0_CLKIN_PERIOD = 41.6666666
-- C_DCM0_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM0_CLKIN_BUF = false
-- C_DCM0_CLKFB_BUF = false
-- C_DCM0_CLK0_BUF = false
-- C_DCM0_CLK90_BUF = false
-- C_DCM0_CLK180_BUF = false
-- C_DCM0_CLK270_BUF = false
-- C_DCM0_CLKDV_BUF = false
-- C_DCM0_CLK2X_BUF = false
-- C_DCM0_CLK2X180_BUF = false
-- C_DCM0_CLKFX_BUF = false
-- C_DCM0_CLKFX180_BUF = false
-- C_DCM0_EXT_RESET_HIGH = 1
-- C_DCM0_FAMILY = "spartan6"
-- C_DCM0_CLKIN_MODULE = NONE
-- C_DCM0_CLKIN_PORT = NONE
-- C_DCM0_CLKFB_MODULE = NONE
-- C_DCM0_CLKFB_PORT = NONE
-- C_DCM0_RST_MODULE = NONE
-- C_DCM1_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM1_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM1_DUTY_CYCLE_CORRECTION = true
-- C_DCM1_CLKIN_DIVIDE_BY_2 = false
-- C_DCM1_CLK_FEEDBACK = "1X"
-- C_DCM1_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM1_DSS_MODE = "NONE"
-- C_DCM1_STARTUP_WAIT = false
-- C_DCM1_PHASE_SHIFT = 0
-- C_DCM1_CLKFX_MULTIPLY = 4
-- C_DCM1_CLKFX_DIVIDE = 1
-- C_DCM1_CLKDV_DIVIDE = 2.0
-- C_DCM1_CLKIN_PERIOD = 41.6666666
-- C_DCM1_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM1_CLKIN_BUF = false
-- C_DCM1_CLKFB_BUF = false
-- C_DCM1_CLK0_BUF = false
-- C_DCM1_CLK90_BUF = false
-- C_DCM1_CLK180_BUF = false
-- C_DCM1_CLK270_BUF = false
-- C_DCM1_CLKDV_BUF = false
-- C_DCM1_CLK2X_BUF = false
-- C_DCM1_CLK2X180_BUF = false
-- C_DCM1_CLKFX_BUF = false
-- C_DCM1_CLKFX180_BUF = false
-- C_DCM1_EXT_RESET_HIGH = 1
-- C_DCM1_FAMILY = "spartan6"
-- C_DCM1_CLKIN_MODULE = NONE
-- C_DCM1_CLKIN_PORT = NONE
-- C_DCM1_CLKFB_MODULE = NONE
-- C_DCM1_CLKFB_PORT = NONE
-- C_DCM1_RST_MODULE = NONE
-- C_DCM2_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM2_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM2_DUTY_CYCLE_CORRECTION = true
-- C_DCM2_CLKIN_DIVIDE_BY_2 = false
-- C_DCM2_CLK_FEEDBACK = "1X"
-- C_DCM2_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM2_DSS_MODE = "NONE"
-- C_DCM2_STARTUP_WAIT = false
-- C_DCM2_PHASE_SHIFT = 0
-- C_DCM2_CLKFX_MULTIPLY = 4
-- C_DCM2_CLKFX_DIVIDE = 1
-- C_DCM2_CLKDV_DIVIDE = 2.0
-- C_DCM2_CLKIN_PERIOD = 41.6666666
-- C_DCM2_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM2_CLKIN_BUF = false
-- C_DCM2_CLKFB_BUF = false
-- C_DCM2_CLK0_BUF = false
-- C_DCM2_CLK90_BUF = false
-- C_DCM2_CLK180_BUF = false
-- C_DCM2_CLK270_BUF = false
-- C_DCM2_CLKDV_BUF = false
-- C_DCM2_CLK2X_BUF = false
-- C_DCM2_CLK2X180_BUF = false
-- C_DCM2_CLKFX_BUF = false
-- C_DCM2_CLKFX180_BUF = false
-- C_DCM2_EXT_RESET_HIGH = 1
-- C_DCM2_FAMILY = "spartan6"
-- C_DCM2_CLKIN_MODULE = NONE
-- C_DCM2_CLKIN_PORT = NONE
-- C_DCM2_CLKFB_MODULE = NONE
-- C_DCM2_CLKFB_PORT = NONE
-- C_DCM2_RST_MODULE = NONE
-- C_DCM3_DFS_FREQUENCY_MODE = "LOW"
-- C_DCM3_DLL_FREQUENCY_MODE = "LOW"
-- C_DCM3_DUTY_CYCLE_CORRECTION = true
-- C_DCM3_CLKIN_DIVIDE_BY_2 = false
-- C_DCM3_CLK_FEEDBACK = "1X"
-- C_DCM3_CLKOUT_PHASE_SHIFT = "NONE"
-- C_DCM3_DSS_MODE = "NONE"
-- C_DCM3_STARTUP_WAIT = false
-- C_DCM3_PHASE_SHIFT = 0
-- C_DCM3_CLKFX_MULTIPLY = 4
-- C_DCM3_CLKFX_DIVIDE = 1
-- C_DCM3_CLKDV_DIVIDE = 2.0
-- C_DCM3_CLKIN_PERIOD = 41.6666666
-- C_DCM3_DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"
-- C_DCM3_CLKIN_BUF = false
-- C_DCM3_CLKFB_BUF = false
-- C_DCM3_CLK0_BUF = false
-- C_DCM3_CLK90_BUF = false
-- C_DCM3_CLK180_BUF = false
-- C_DCM3_CLK270_BUF = false
-- C_DCM3_CLKDV_BUF = false
-- C_DCM3_CLK2X_BUF = false
-- C_DCM3_CLK2X180_BUF = false
-- C_DCM3_CLKFX_BUF = false
-- C_DCM3_CLKFX180_BUF = false
-- C_DCM3_EXT_RESET_HIGH = 1
-- C_DCM3_FAMILY = "spartan6"
-- C_DCM3_CLKIN_MODULE = NONE
-- C_DCM3_CLKIN_PORT = NONE
-- C_DCM3_CLKFB_MODULE = NONE
-- C_DCM3_CLKFB_PORT = NONE
-- C_DCM3_RST_MODULE = NONE
----------------------------------------
-- C_PLL0_BANDWIDTH = "OPTIMIZED"
-- C_PLL0_CLKFBOUT_MULT = 10
-- C_PLL0_CLKFBOUT_PHASE = 0.0
-- C_PLL0_CLKIN1_PERIOD = 10.000000
-- C_PLL0_CLKOUT0_DIVIDE = 20
-- C_PLL0_CLKOUT0_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT0_PHASE = 0.0000
-- C_PLL0_CLKOUT1_DIVIDE = 1
-- C_PLL0_CLKOUT1_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT1_PHASE = 0.0
-- C_PLL0_CLKOUT2_DIVIDE = 1
-- C_PLL0_CLKOUT2_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT2_PHASE = 0.0
-- C_PLL0_CLKOUT3_DIVIDE = 1
-- C_PLL0_CLKOUT3_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT3_PHASE = 0.0
-- C_PLL0_CLKOUT4_DIVIDE = 1
-- C_PLL0_CLKOUT4_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT4_PHASE = 0.0
-- C_PLL0_CLKOUT5_DIVIDE = 1
-- C_PLL0_CLKOUT5_DUTY_CYCLE = 0.5
-- C_PLL0_CLKOUT5_PHASE = 0.0
-- C_PLL0_COMPENSATION = "SYSTEM_SYNCHRONOUS"
-- C_PLL0_DIVCLK_DIVIDE = 1
-- C_PLL0_REF_JITTER = 0.100
-- C_PLL0_RESET_ON_LOSS_OF_LOCK = false
-- C_PLL0_RST_DEASSERT_CLK = "CLKIN1"
-- C_PLL0_CLKOUT0_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT1_DESKEW_ADJUST = "NONE"
-- C_PLL0_CLKOUT2_DESKEW_ADJUST = "PPC"
-- C_PLL0_CLKOUT3_DESKEW_ADJUST = "PPC"
-- C_PLL0_CLKOUT4_DESKEW_ADJUST = "PPC"
-- C_PLL0_CLKOUT5_DESKEW_ADJUST = "PPC"
-- C_PLL0_CLKFBOUT_DESKEW_ADJUST = "PPC"
-- C_PLL0_CLKIN1_BUF = false
-- C_PLL0_CLKFBOUT_BUF = TRUE
-- C_PLL0_CLKOUT0_BUF = TRUE
-- C_PLL0_CLKOUT1_BUF = false
-- C_PLL0_CLKOUT2_BUF = false
-- C_PLL0_CLKOUT3_BUF = false
-- C_PLL0_CLKOUT4_BUF = false
-- C_PLL0_CLKOUT5_BUF = false
-- C_PLL0_EXT_RESET_HIGH = 1
-- C_PLL0_FAMILY = "spartan6"
-- C_PLL0_CLKIN1_MODULE = CLKGEN
-- C_PLL0_CLKIN1_PORT = CLKIN
-- C_PLL0_CLKFBIN_MODULE = PLL0
-- C_PLL0_CLKFBIN_PORT = CLKFBOUT
-- C_PLL0_RST_MODULE = CLKGEN
-- C_PLL1_BANDWIDTH = "OPTIMIZED"
-- C_PLL1_CLKFBOUT_MULT = 1
-- C_PLL1_CLKFBOUT_PHASE = 0.0
-- C_PLL1_CLKIN1_PERIOD = 0.000
-- C_PLL1_CLKOUT0_DIVIDE = 1
-- C_PLL1_CLKOUT0_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT0_PHASE = 0.0
-- C_PLL1_CLKOUT1_DIVIDE = 1
-- C_PLL1_CLKOUT1_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT1_PHASE = 0.0
-- C_PLL1_CLKOUT2_DIVIDE = 1
-- C_PLL1_CLKOUT2_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT2_PHASE = 0.0
-- C_PLL1_CLKOUT3_DIVIDE = 1
-- C_PLL1_CLKOUT3_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT3_PHASE = 0.0
-- C_PLL1_CLKOUT4_DIVIDE = 1
-- C_PLL1_CLKOUT4_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT4_PHASE = 0.0
-- C_PLL1_CLKOUT5_DIVIDE = 1
-- C_PLL1_CLKOUT5_DUTY_CYCLE = 0.5
-- C_PLL1_CLKOUT5_PHASE = 0.0
-- C_PLL1_COMPENSATION = "SYSTEM_SYNCHRONOUS"
-- C_PLL1_DIVCLK_DIVIDE = 1
-- C_PLL1_REF_JITTER = 0.100
-- C_PLL1_RESET_ON_LOSS_OF_LOCK = false
-- C_PLL1_RST_DEASSERT_CLK = "CLKIN1"
-- C_PLL1_CLKOUT0_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT1_DESKEW_ADJUST = "NONE"
-- C_PLL1_CLKOUT2_DESKEW_ADJUST = "PPC"
-- C_PLL1_CLKOUT3_DESKEW_ADJUST = "PPC"
-- C_PLL1_CLKOUT4_DESKEW_ADJUST = "PPC"
-- C_PLL1_CLKOUT5_DESKEW_ADJUST = "PPC"
-- C_PLL1_CLKFBOUT_DESKEW_ADJUST = "PPC"
-- C_PLL1_CLKIN1_BUF = false
-- C_PLL1_CLKFBOUT_BUF = false
-- C_PLL1_CLKOUT0_BUF = false
-- C_PLL1_CLKOUT1_BUF = false
-- C_PLL1_CLKOUT2_BUF = false
-- C_PLL1_CLKOUT3_BUF = false
-- C_PLL1_CLKOUT4_BUF = false
-- C_PLL1_CLKOUT5_BUF = false
-- C_PLL1_EXT_RESET_HIGH = 1
-- C_PLL1_FAMILY = "spartan6"
-- C_PLL1_CLKIN1_MODULE = NONE
-- C_PLL1_CLKIN1_PORT = NONE
-- C_PLL1_CLKFBIN_MODULE = NONE
-- C_PLL1_CLKFBIN_PORT = NONE
-- C_PLL1_RST_MODULE = NONE
----------------------------------------
-- C_MMCM0_BANDWIDTH = "OPTIMIZED"
-- C_MMCM0_CLKFBOUT_MULT_F = 1.0
-- C_MMCM0_CLKFBOUT_PHASE = 0.0
-- C_MMCM0_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM0_CLKIN1_PERIOD = 0.000
-- C_MMCM0_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM0_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT0_PHASE = 0.0
-- C_MMCM0_CLKOUT1_DIVIDE = 1
-- C_MMCM0_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT1_PHASE = 0.0
-- C_MMCM0_CLKOUT2_DIVIDE = 1
-- C_MMCM0_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT2_PHASE = 0.0
-- C_MMCM0_CLKOUT3_DIVIDE = 1
-- C_MMCM0_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT3_PHASE = 0.0
-- C_MMCM0_CLKOUT4_DIVIDE = 1
-- C_MMCM0_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT4_PHASE = 0.0
-- C_MMCM0_CLKOUT4_CASCADE = false
-- C_MMCM0_CLKOUT5_DIVIDE = 1
-- C_MMCM0_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT5_PHASE = 0.0
-- C_MMCM0_CLKOUT6_DIVIDE = 1
-- C_MMCM0_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM0_CLKOUT6_PHASE = 0.0
-- C_MMCM0_CLKOUT0_USE_FINE_PS = false
-- C_MMCM0_CLKOUT1_USE_FINE_PS = false
-- C_MMCM0_CLKOUT2_USE_FINE_PS = false
-- C_MMCM0_CLKOUT3_USE_FINE_PS = false
-- C_MMCM0_CLKOUT4_USE_FINE_PS = false
-- C_MMCM0_CLKOUT5_USE_FINE_PS = false
-- C_MMCM0_CLKOUT6_USE_FINE_PS = false
-- C_MMCM0_COMPENSATION = "ZHOLD"
-- C_MMCM0_DIVCLK_DIVIDE = 1
-- C_MMCM0_REF_JITTER1 = 0.010
-- C_MMCM0_CLKIN1_BUF = false
-- C_MMCM0_CLKFBOUT_BUF = false
-- C_MMCM0_CLKOUT0_BUF = false
-- C_MMCM0_CLKOUT1_BUF = false
-- C_MMCM0_CLKOUT2_BUF = false
-- C_MMCM0_CLKOUT3_BUF = false
-- C_MMCM0_CLKOUT4_BUF = false
-- C_MMCM0_CLKOUT5_BUF = false
-- C_MMCM0_CLKOUT6_BUF = false
-- C_MMCM0_CLOCK_HOLD = false
-- C_MMCM0_STARTUP_WAIT = false
-- C_MMCM0_EXT_RESET_HIGH = 1
-- C_MMCM0_FAMILY = "spartan6"
-- C_MMCM0_CLKIN1_MODULE = NONE
-- C_MMCM0_CLKIN1_PORT = NONE
-- C_MMCM0_CLKFBIN_MODULE = NONE
-- C_MMCM0_CLKFBIN_PORT = NONE
-- C_MMCM0_RST_MODULE = NONE
-- C_MMCM1_BANDWIDTH = "OPTIMIZED"
-- C_MMCM1_CLKFBOUT_MULT_F = 1.0
-- C_MMCM1_CLKFBOUT_PHASE = 0.0
-- C_MMCM1_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM1_CLKIN1_PERIOD = 0.000
-- C_MMCM1_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM1_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT0_PHASE = 0.0
-- C_MMCM1_CLKOUT1_DIVIDE = 1
-- C_MMCM1_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT1_PHASE = 0.0
-- C_MMCM1_CLKOUT2_DIVIDE = 1
-- C_MMCM1_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT2_PHASE = 0.0
-- C_MMCM1_CLKOUT3_DIVIDE = 1
-- C_MMCM1_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT3_PHASE = 0.0
-- C_MMCM1_CLKOUT4_DIVIDE = 1
-- C_MMCM1_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT4_PHASE = 0.0
-- C_MMCM1_CLKOUT4_CASCADE = false
-- C_MMCM1_CLKOUT5_DIVIDE = 1
-- C_MMCM1_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT5_PHASE = 0.0
-- C_MMCM1_CLKOUT6_DIVIDE = 1
-- C_MMCM1_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM1_CLKOUT6_PHASE = 0.0
-- C_MMCM1_CLKOUT0_USE_FINE_PS = false
-- C_MMCM1_CLKOUT1_USE_FINE_PS = false
-- C_MMCM1_CLKOUT2_USE_FINE_PS = false
-- C_MMCM1_CLKOUT3_USE_FINE_PS = false
-- C_MMCM1_CLKOUT4_USE_FINE_PS = false
-- C_MMCM1_CLKOUT5_USE_FINE_PS = false
-- C_MMCM1_CLKOUT6_USE_FINE_PS = false
-- C_MMCM1_COMPENSATION = "ZHOLD"
-- C_MMCM1_DIVCLK_DIVIDE = 1
-- C_MMCM1_REF_JITTER1 = 0.010
-- C_MMCM1_CLKIN1_BUF = false
-- C_MMCM1_CLKFBOUT_BUF = false
-- C_MMCM1_CLKOUT0_BUF = false
-- C_MMCM1_CLKOUT1_BUF = false
-- C_MMCM1_CLKOUT2_BUF = false
-- C_MMCM1_CLKOUT3_BUF = false
-- C_MMCM1_CLKOUT4_BUF = false
-- C_MMCM1_CLKOUT5_BUF = false
-- C_MMCM1_CLKOUT6_BUF = false
-- C_MMCM1_CLOCK_HOLD = false
-- C_MMCM1_STARTUP_WAIT = false
-- C_MMCM1_EXT_RESET_HIGH = 1
-- C_MMCM1_FAMILY = "spartan6"
-- C_MMCM1_CLKIN1_MODULE = NONE
-- C_MMCM1_CLKIN1_PORT = NONE
-- C_MMCM1_CLKFBIN_MODULE = NONE
-- C_MMCM1_CLKFBIN_PORT = NONE
-- C_MMCM1_RST_MODULE = NONE
-- C_MMCM2_BANDWIDTH = "OPTIMIZED"
-- C_MMCM2_CLKFBOUT_MULT_F = 1.0
-- C_MMCM2_CLKFBOUT_PHASE = 0.0
-- C_MMCM2_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM2_CLKIN1_PERIOD = 0.000
-- C_MMCM2_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM2_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT0_PHASE = 0.0
-- C_MMCM2_CLKOUT1_DIVIDE = 1
-- C_MMCM2_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT1_PHASE = 0.0
-- C_MMCM2_CLKOUT2_DIVIDE = 1
-- C_MMCM2_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT2_PHASE = 0.0
-- C_MMCM2_CLKOUT3_DIVIDE = 1
-- C_MMCM2_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT3_PHASE = 0.0
-- C_MMCM2_CLKOUT4_DIVIDE = 1
-- C_MMCM2_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT4_PHASE = 0.0
-- C_MMCM2_CLKOUT4_CASCADE = false
-- C_MMCM2_CLKOUT5_DIVIDE = 1
-- C_MMCM2_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT5_PHASE = 0.0
-- C_MMCM2_CLKOUT6_DIVIDE = 1
-- C_MMCM2_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM2_CLKOUT6_PHASE = 0.0
-- C_MMCM2_CLKOUT0_USE_FINE_PS = false
-- C_MMCM2_CLKOUT1_USE_FINE_PS = false
-- C_MMCM2_CLKOUT2_USE_FINE_PS = false
-- C_MMCM2_CLKOUT3_USE_FINE_PS = false
-- C_MMCM2_CLKOUT4_USE_FINE_PS = false
-- C_MMCM2_CLKOUT5_USE_FINE_PS = false
-- C_MMCM2_CLKOUT6_USE_FINE_PS = false
-- C_MMCM2_COMPENSATION = "ZHOLD"
-- C_MMCM2_DIVCLK_DIVIDE = 1
-- C_MMCM2_REF_JITTER1 = 0.010
-- C_MMCM2_CLKIN1_BUF = false
-- C_MMCM2_CLKFBOUT_BUF = false
-- C_MMCM2_CLKOUT0_BUF = false
-- C_MMCM2_CLKOUT1_BUF = false
-- C_MMCM2_CLKOUT2_BUF = false
-- C_MMCM2_CLKOUT3_BUF = false
-- C_MMCM2_CLKOUT4_BUF = false
-- C_MMCM2_CLKOUT5_BUF = false
-- C_MMCM2_CLKOUT6_BUF = false
-- C_MMCM2_CLOCK_HOLD = false
-- C_MMCM2_STARTUP_WAIT = false
-- C_MMCM2_EXT_RESET_HIGH = 1
-- C_MMCM2_FAMILY = "spartan6"
-- C_MMCM2_CLKIN1_MODULE = NONE
-- C_MMCM2_CLKIN1_PORT = NONE
-- C_MMCM2_CLKFBIN_MODULE = NONE
-- C_MMCM2_CLKFBIN_PORT = NONE
-- C_MMCM2_RST_MODULE = NONE
-- C_MMCM3_BANDWIDTH = "OPTIMIZED"
-- C_MMCM3_CLKFBOUT_MULT_F = 1.0
-- C_MMCM3_CLKFBOUT_PHASE = 0.0
-- C_MMCM3_CLKFBOUT_USE_FINE_PS = false
-- C_MMCM3_CLKIN1_PERIOD = 0.000
-- C_MMCM3_CLKOUT0_DIVIDE_F = 1.0
-- C_MMCM3_CLKOUT0_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT0_PHASE = 0.0
-- C_MMCM3_CLKOUT1_DIVIDE = 1
-- C_MMCM3_CLKOUT1_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT1_PHASE = 0.0
-- C_MMCM3_CLKOUT2_DIVIDE = 1
-- C_MMCM3_CLKOUT2_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT2_PHASE = 0.0
-- C_MMCM3_CLKOUT3_DIVIDE = 1
-- C_MMCM3_CLKOUT3_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT3_PHASE = 0.0
-- C_MMCM3_CLKOUT4_DIVIDE = 1
-- C_MMCM3_CLKOUT4_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT4_PHASE = 0.0
-- C_MMCM3_CLKOUT4_CASCADE = false
-- C_MMCM3_CLKOUT5_DIVIDE = 1
-- C_MMCM3_CLKOUT5_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT5_PHASE = 0.0
-- C_MMCM3_CLKOUT6_DIVIDE = 1
-- C_MMCM3_CLKOUT6_DUTY_CYCLE = 0.5
-- C_MMCM3_CLKOUT6_PHASE = 0.0
-- C_MMCM3_CLKOUT0_USE_FINE_PS = false
-- C_MMCM3_CLKOUT1_USE_FINE_PS = false
-- C_MMCM3_CLKOUT2_USE_FINE_PS = false
-- C_MMCM3_CLKOUT3_USE_FINE_PS = false
-- C_MMCM3_CLKOUT4_USE_FINE_PS = false
-- C_MMCM3_CLKOUT5_USE_FINE_PS = false
-- C_MMCM3_CLKOUT6_USE_FINE_PS = false
-- C_MMCM3_COMPENSATION = "ZHOLD"
-- C_MMCM3_DIVCLK_DIVIDE = 1
-- C_MMCM3_REF_JITTER1 = 0.010
-- C_MMCM3_CLKIN1_BUF = false
-- C_MMCM3_CLKFBOUT_BUF = false
-- C_MMCM3_CLKOUT0_BUF = false
-- C_MMCM3_CLKOUT1_BUF = false
-- C_MMCM3_CLKOUT2_BUF = false
-- C_MMCM3_CLKOUT3_BUF = false
-- C_MMCM3_CLKOUT4_BUF = false
-- C_MMCM3_CLKOUT5_BUF = false
-- C_MMCM3_CLKOUT6_BUF = false
-- C_MMCM3_CLOCK_HOLD = false
-- C_MMCM3_STARTUP_WAIT = false
-- C_MMCM3_EXT_RESET_HIGH = 1
-- C_MMCM3_FAMILY = "spartan6"
-- C_MMCM3_CLKIN1_MODULE = NONE
-- C_MMCM3_CLKIN1_PORT = NONE
-- C_MMCM3_CLKFBIN_MODULE = NONE
-- C_MMCM3_CLKFBIN_PORT = NONE
-- C_MMCM3_RST_MODULE = NONE
----------------------------------------
-- C_PLLE0_BANDWIDTH = "OPTIMIZED"
-- C_PLLE0_CLKFBOUT_MULT = 1
-- C_PLLE0_CLKFBOUT_PHASE = 0.0
-- C_PLLE0_CLKIN1_PERIOD = 0.000
-- C_PLLE0_CLKOUT0_DIVIDE = 1
-- C_PLLE0_CLKOUT0_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT0_PHASE = 0.0
-- C_PLLE0_CLKOUT1_DIVIDE = 1
-- C_PLLE0_CLKOUT1_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT1_PHASE = 0.0
-- C_PLLE0_CLKOUT2_DIVIDE = 1
-- C_PLLE0_CLKOUT2_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT2_PHASE = 0.0
-- C_PLLE0_CLKOUT3_DIVIDE = 1
-- C_PLLE0_CLKOUT3_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT3_PHASE = 0.0
-- C_PLLE0_CLKOUT4_DIVIDE = 1
-- C_PLLE0_CLKOUT4_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT4_PHASE = 0.0
-- C_PLLE0_CLKOUT5_DIVIDE = 1
-- C_PLLE0_CLKOUT5_DUTY_CYCLE = 0.5
-- C_PLLE0_CLKOUT5_PHASE = 0.0
-- C_PLLE0_COMPENSATION = "ZHOLD"
-- C_PLLE0_DIVCLK_DIVIDE = 1
-- C_PLLE0_REF_JITTER1 = 0.010
-- C_PLLE0_CLKIN1_BUF = false
-- C_PLLE0_CLKFBOUT_BUF = false
-- C_PLLE0_CLKOUT0_BUF = false
-- C_PLLE0_CLKOUT1_BUF = false
-- C_PLLE0_CLKOUT2_BUF = false
-- C_PLLE0_CLKOUT3_BUF = false
-- C_PLLE0_CLKOUT4_BUF = false
-- C_PLLE0_CLKOUT5_BUF = false
-- C_PLLE0_STARTUP_WAIT = "false"
-- C_PLLE0_EXT_RESET_HIGH = 1
-- C_PLLE0_FAMILY = "virtex7"
-- C_PLLE0_CLKIN1_MODULE = NONE
-- C_PLLE0_CLKIN1_PORT = NONE
-- C_PLLE0_CLKFBIN_MODULE = NONE
-- C_PLLE0_CLKFBIN_PORT = NONE
-- C_PLLE0_RST_MODULE = NONE
----------------------------------------
|
gpl-2.0
|
313564296a8ae5966ddfe23f1aa9d2c7
| 0.548175 | 2.951774 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_gpio_sw_0/sim/system_axi_gpio_sw_0.vhd
| 1 | 9,059 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_13;
USE axi_gpio_v2_0_13.axi_gpio;
ENTITY system_axi_gpio_sw_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END system_axi_gpio_sw_0;
ARCHITECTURE system_axi_gpio_sw_0_arch OF system_axi_gpio_sw_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_gpio_sw_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 4,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 1,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 1,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 1,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
ip2intc_irpt => ip2intc_irpt,
gpio_io_i => gpio_io_i,
gpio2_io_i => gpio2_io_i
);
END system_axi_gpio_sw_0_arch;
|
apache-2.0
|
c0330eeb61ffb6819058eaab717cf034
| 0.681311 | 3.235357 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_microblaze_0_xlconcat_0/synth/system_microblaze_0_xlconcat_0.vhd
| 1 | 9,009 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlconcat:2.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlconcat;
ENTITY system_microblaze_0_xlconcat_0 IS
PORT (
In0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END system_microblaze_0_xlconcat_0;
ARCHITECTURE system_microblaze_0_xlconcat_0_arch OF system_microblaze_0_xlconcat_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_microblaze_0_xlconcat_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlconcat IS
GENERIC (
IN0_WIDTH : INTEGER;
IN1_WIDTH : INTEGER;
IN2_WIDTH : INTEGER;
IN3_WIDTH : INTEGER;
IN4_WIDTH : INTEGER;
IN5_WIDTH : INTEGER;
IN6_WIDTH : INTEGER;
IN7_WIDTH : INTEGER;
IN8_WIDTH : INTEGER;
IN9_WIDTH : INTEGER;
IN10_WIDTH : INTEGER;
IN11_WIDTH : INTEGER;
IN12_WIDTH : INTEGER;
IN13_WIDTH : INTEGER;
IN14_WIDTH : INTEGER;
IN15_WIDTH : INTEGER;
IN16_WIDTH : INTEGER;
IN17_WIDTH : INTEGER;
IN18_WIDTH : INTEGER;
IN19_WIDTH : INTEGER;
IN20_WIDTH : INTEGER;
IN21_WIDTH : INTEGER;
IN22_WIDTH : INTEGER;
IN23_WIDTH : INTEGER;
IN24_WIDTH : INTEGER;
IN25_WIDTH : INTEGER;
IN26_WIDTH : INTEGER;
IN27_WIDTH : INTEGER;
IN28_WIDTH : INTEGER;
IN29_WIDTH : INTEGER;
IN30_WIDTH : INTEGER;
IN31_WIDTH : INTEGER;
dout_width : INTEGER;
NUM_PORTS : INTEGER
);
PORT (
In0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In21 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In22 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In25 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In26 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In27 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In28 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In29 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In30 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In31 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END COMPONENT xlconcat;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_microblaze_0_xlconcat_0_arch: ARCHITECTURE IS "xlconcat,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_microblaze_0_xlconcat_0_arch : ARCHITECTURE IS "system_microblaze_0_xlconcat_0,xlconcat,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_microblaze_0_xlconcat_0_arch: ARCHITECTURE IS "system_microblaze_0_xlconcat_0,xlconcat,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH=1,I" &
"N24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=7,NUM_PORTS=7}";
BEGIN
U0 : xlconcat
GENERIC MAP (
IN0_WIDTH => 1,
IN1_WIDTH => 1,
IN2_WIDTH => 1,
IN3_WIDTH => 1,
IN4_WIDTH => 1,
IN5_WIDTH => 1,
IN6_WIDTH => 1,
IN7_WIDTH => 1,
IN8_WIDTH => 1,
IN9_WIDTH => 1,
IN10_WIDTH => 1,
IN11_WIDTH => 1,
IN12_WIDTH => 1,
IN13_WIDTH => 1,
IN14_WIDTH => 1,
IN15_WIDTH => 1,
IN16_WIDTH => 1,
IN17_WIDTH => 1,
IN18_WIDTH => 1,
IN19_WIDTH => 1,
IN20_WIDTH => 1,
IN21_WIDTH => 1,
IN22_WIDTH => 1,
IN23_WIDTH => 1,
IN24_WIDTH => 1,
IN25_WIDTH => 1,
IN26_WIDTH => 1,
IN27_WIDTH => 1,
IN28_WIDTH => 1,
IN29_WIDTH => 1,
IN30_WIDTH => 1,
IN31_WIDTH => 1,
dout_width => 7,
NUM_PORTS => 7
)
PORT MAP (
In0 => In0,
In1 => In1,
In2 => In2,
In3 => In3,
In4 => In4,
In5 => In5,
In6 => In6,
In7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
dout => dout
);
END system_microblaze_0_xlconcat_0_arch;
|
apache-2.0
|
93d1ec9ef115f2606e3a291f4e459061
| 0.648796 | 3.254697 | false | false | false | false |
jeffmagina/ECE368
|
Lab1/CounterTest/clk4Hz.vhd
| 1 | 1,421 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: CLK4Hz
-- Project Name: CLOCK COUNTER
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Clock Divider
-- Lower the Clock frequency from
-- 50 Mhz to 4 hz
-- 50Mhz = 50,000,000/12,500,000 = 2 Hz
-- 4Hz ~= 1/2 second
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk4Hz is
Port ( CLK_IN : in STD_LOGIC;
RST : in STD_LOGIC;
CLK_OUT : out STD_LOGIC);
end clk4Hz;
architecture Behavioral of clk4Hz is
signal clkdv: STD_LOGIC:='0';
signal counter : integer range 0 to 12500000 := 0;
begin
frequency_divider: process (RST, CLK_IN) begin
if (RST = '1') then
clkdv <= '0';
counter <= 0;
elsif rising_edge(CLK_IN) then
if (counter = 12500000) then
if(clkdv='0') then
clkdv <= '1';
else
clkdv <= '0';
end if;
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;
CLK_OUT <= clkdv;
end Behavioral;
|
mit
|
a5bd2618ff4f7187f9f0db8adc18f81f
| 0.498241 | 4.118841 | false | false | false | false |
jeffmagina/ECE368
|
Project1/EXECUTE/ALU/alu_arithmetic_unit.vhd
| 1 | 1,610 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Arithmetic_Unit
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Artithmetic Unit
-- Operations - Add, Sub, Addi
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arith_Unit is
Port ( A : in STD_LOGIC_VECTOR (15 downto 0);
B : in STD_LOGIC_VECTOR (15 downto 0);
OP : in STD_LOGIC_VECTOR (2 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
RESULT : out STD_LOGIC_VECTOR (15 downto 0));
end Arith_Unit;
architecture Combinational of Arith_Unit is
signal a1, b1 : STD_LOGIC_VECTOR (16 downto 0) := (OTHERS => '0');
signal arith : STD_LOGIC_VECTOR (16 downto 0) := (OTHERS => '0');
begin
-- Give extra bit to accound for carry,overflow,negative
a1 <= '0' & A;
b1 <= '0' & B;
with OP select
arith <=
a1 + b1 when "000", -- ADD
a1 - b1 when "001", -- SUB
a1 + b1 when "101", -- ADDI
a1 + b1 when OTHERS;
CCR(3) <= arith(15); -- Negative
CCR(2) <= '1' when arith(15 downto 0) = x"0000" else '0'; -- Zero
CCR(1) <= arith(16) xor arith(15); -- Overflow
CCR(0) <= arith(16); --Carry
RESULT <= arith(15 downto 0);
end Combinational;
|
mit
|
981a0978d370c857512282debb91bb38
| 0.555901 | 3.546256 | false | false | false | false |
kaott/16-bit-risc
|
vhdl/add4.vhd
| 4 | 817 |
-- ADD4
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity add4 is
port( A, B : in std_logic_vector(3 downto 0);
CIN : in std_logic;
D : out std_logic_vector(3 downto 0);
COUT : out std_logic
);
end add4;
architecture logic of add4 is
signal sum : std_logic_vector(3 downto 0);
signal cG : std_logic_vector(3 downto 0);
signal cP : std_logic_vector(3 downto 0);
signal cI : std_logic_vector(3 downto 1);
begin
sum <= A xor B;
cG <= A and B;
cP <= A or B;
process(cG, cP, cI)
begin
cI(1) <= cG(0) or (cP(0) and CIN);
for i in 1 to 2 LOOP
cI(i+1) <= cG(i) or (cP(i) and cI(i));
end loop;
COUT <= cG(3) or (cP(3) and cI(3));
end process;
D(0) <= sum(0) xor CIN;
D(3 downto 1) <= sum(3 downto 1) xor cI(3 downto 1);
end logic;
|
mit
|
198f217d2a3098804549ce4a480fff36
| 0.587515 | 2.424332 | false | false | false | false |
alextrem/red-diamond
|
fpga/vhdl/i2s.vhd
| 1 | 1,303 |
---------------------------------------
-- Company:
-- Engineer: Alexander Geißler
--
-- Create Date: 16:00:00 07/04/2015
-- Design Name:
-- Project Name: red-diamond
-- Target Device: EP4CE22C8N
-- Tool Versions: 14.0
-- Description: Audio interface of
-- ADV7612
--
-- Dependencies:
--
-- Revision:
-- Revision 0.1 - File created
--------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity i2s is
port (
-- Synchrounous reset
reset : in std_logic;
-- I2S interface
-- Data output for left and right channel
sd : inout std_logic;
-- Bit clock
sck : inout std_logic;
-- Audio master clock output
ws : inout std_logic;
-- left channel data
left_channel : inout std_logic_vector(31 downto 0);
-- right channel data
right_channel : inout std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of i2s is
signal sv_sr : std_logic_vector(31 downto 0);
begin
SHIFT_REGISTER: process(reset, sck)
begin
if rising_edge(sck) then
if reset = '1' then
left_channel <= (others=>'0');
right_channel <= (others=>'0');
sck <= '0';
sd <= '0';
else
sv_sr <= sd & sv_sr(31 downto 1);
end if;
end if;
end process;
end rtl;
|
gpl-3.0
|
6c11c042bb947c519be33774b642f23b
| 0.563748 | 3.381818 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_wiz_0_0_proc_common_pkg.vhd
| 1 | 18,688 |
-------------------------------------------------------------------------------
-- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: system_xadc_wiz_0_0_proc_common_pkg.vhd
-- Version: v1.21b
-- Description: This file contains the constants and functions used in the
-- processor common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 09/12/01 -- Created from opb_arb_pkg.vhd
--
-- ALS 09/21/01
-- ^^^^^^
-- Added pwr function. Replaced log2 function with one that works for XST.
-- ~~~~~~
--
-- ALS 12/07/01
-- ^^^^^^
-- Added Addr_bits function.
-- ~~~~~~
-- ALS 01/31/02
-- ^^^^^^
-- Added max2 function.
-- ~~~~~~
-- FLO 02/22/02
-- ^^^^^^
-- Extended input argument range of log2 function to 2^30. Also, added
-- a check that the argument does not exceed this value; a failure
-- assertion violation is generated if it does not.
-- ~~~~~~
-- FLO 08/31/06
-- ^^^^^^
-- Removed type TARGET_FAMILY_TYPE and functions Get_Reg_File_Area and
-- Get_RLOC_Name. These objects are not used. Further, the functions
-- produced misleading warnings (CR419886, CR419898).
-- ~~~~~~
-- FLO 05/25/07
-- ^^^^^^
-- -Reimplemented function pad_power2 to correct error when the input
-- argument is 1. (fixes CR 303469)
-- -Added function clog2(x), which returns the integer ceiling of the
-- base 2 logarithm of x. This function can be used in place of log2
-- when wishing to avoid the XST warning, "VHDL Assertion Statement
-- with non constant condition is ignored".
-- ~~~~~~
--
-- DET 1/17/2008 v3_30_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-- DET 5/8/2009 v3_30_a for EDK L.SP2
-- ~~~~~~
-- - Per CR520627
-- - Added synthesis translate_off/on constructs to the log2 function
-- around the assertion statement. This removes a repetative XST Warning
-- in SRP files about a non-constant assertion check.
-- ^^^^^^
-- FL0 20/27/2010
-- ^^^^^^
-- Removed 42 TBD comment, again. (CR 568493)
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package system_xadc_wiz_0_0_proc_common_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
-- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63);
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer;
function min2 (num1, num2 : integer) return integer;
function Addr_Bits(x,y : std_logic_vector) return integer;
function clog2(x : positive) return natural;
function pad_power2 ( in_num : integer ) return integer;
function pad_4 ( in_num : integer ) return integer;
function log2(x : natural) return integer;
function pwr(x: integer; y: integer) return integer;
function String_To_Int(S : string) return integer;
function itoa (int : integer) return string;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- the RESET_ACTIVE constant should denote the logic level of an active reset
constant RESET_ACTIVE : std_logic := '1';
-- table containing strings representing hex characters for conversion to
-- integers
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
end system_xadc_wiz_0_0_proc_common_pkg;
package body system_xadc_wiz_0_0_proc_common_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function min2
--
-- This function returns the lesser of two numbers.
-------------------------------------------------------------------------------
function min2 (num1, num2 : integer) return integer is
begin
if num1 <= num2 then
return num1;
else
return num2;
end if;
end function min2;
-------------------------------------------------------------------------------
-- Function Addr_bits
--
-- function to convert an address range (base address and an upper address)
-- into the number of upper address bits needed for decoding a device
-- select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits(x,y : std_logic_vector) return integer is
variable addr_xor : std_logic_vector(x'range);
variable count : integer := 0;
begin
assert x'length = y'length and (x'ascending xnor y'ascending)
report "Addr_Bits: arguments are not the same type"
severity ERROR;
addr_xor := x xor y;
for i in x'range
loop
if addr_xor(i) = '1' then return count;
end if;
count := count + 1;
end loop;
return x'length;
end Addr_Bits;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function pad_power2
--
-- This function returns the next power of 2 from the input number. If the
-- input number is a power of 2, this function returns the input number.
--
-- This function is used to round up the number of masters to the next power
-- of 2 if the number of masters is not already a power of 2.
--
-- Input argument 0, which is not a power of two, is accepted and returns 0.
-- Input arguments less than 0 are not allowed.
-------------------------------------------------------------------------------
--
function pad_power2 (in_num : integer ) return integer is
begin
if in_num = 0 then
return 0;
else
return 2**(clog2(in_num));
end if;
end pad_power2;
-------------------------------------------------------------------------------
-- Function pad_4
--
-- This function returns the next multiple of 4 from the input number. If the
-- input number is a multiple of 4, this function returns the input number.
--
-------------------------------------------------------------------------------
--
function pad_4 (in_num : integer ) return integer is
variable out_num : integer;
begin
out_num := (((in_num-1)/4) + 1)*4;
return out_num;
end pad_4;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- x**y
-- negative numbers not allowed for y
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
-------------------------------------------------------------------------------
-- Function itoa
--
-- The itoa function converts an integer to a text string.
-- This function is required since `image doesn't work in Synplicity
-- Valid input range is -9999 to 9999
-------------------------------------------------------------------------------
--
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end itoa;
-----------------------------------------------------------------------------
-- Function String_To_Int
--
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end String_To_Int;
end package body system_xadc_wiz_0_0_proc_common_pkg;
|
apache-2.0
|
a4eb3c55d18c80787d7e27d6560c22e4
| 0.469606 | 4.612043 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_ethernetlite_0_0/sim/system_axi_ethernetlite_0_0.vhd
| 1 | 12,419 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_ethernetlite:3.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_ethernetlite_v3_0_9;
USE axi_ethernetlite_v3_0_9.axi_ethernetlite;
ENTITY system_axi_ethernetlite_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
phy_tx_clk : IN STD_LOGIC;
phy_rx_clk : IN STD_LOGIC;
phy_crs : IN STD_LOGIC;
phy_dv : IN STD_LOGIC;
phy_rx_data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_col : IN STD_LOGIC;
phy_rx_er : IN STD_LOGIC;
phy_rst_n : OUT STD_LOGIC;
phy_tx_en : OUT STD_LOGIC;
phy_tx_data : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_mdio_i : IN STD_LOGIC;
phy_mdio_o : OUT STD_LOGIC;
phy_mdio_t : OUT STD_LOGIC;
phy_mdc : OUT STD_LOGIC
);
END system_axi_ethernetlite_0_0;
ARCHITECTURE system_axi_ethernetlite_0_0_arch OF system_axi_ethernetlite_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_ethernetlite_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_ethernetlite IS
GENERIC (
C_FAMILY : STRING;
C_SELECT_XPM : INTEGER;
C_INSTANCE : STRING;
C_S_AXI_ACLK_PERIOD_PS : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_INCLUDE_MDIO : INTEGER;
C_INCLUDE_INTERNAL_LOOPBACK : INTEGER;
C_INCLUDE_GLOBAL_BUFFERS : INTEGER;
C_DUPLEX : INTEGER;
C_TX_PING_PONG : INTEGER;
C_RX_PING_PONG : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
phy_tx_clk : IN STD_LOGIC;
phy_rx_clk : IN STD_LOGIC;
phy_crs : IN STD_LOGIC;
phy_dv : IN STD_LOGIC;
phy_rx_data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_col : IN STD_LOGIC;
phy_rx_er : IN STD_LOGIC;
phy_rst_n : OUT STD_LOGIC;
phy_tx_en : OUT STD_LOGIC;
phy_tx_data : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_mdio_i : IN STD_LOGIC;
phy_mdio_o : OUT STD_LOGIC;
phy_mdio_t : OUT STD_LOGIC;
phy_mdc : OUT STD_LOGIC
);
END COMPONENT axi_ethernetlite;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF phy_tx_clk: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TX_CLK";
ATTRIBUTE X_INTERFACE_INFO OF phy_rx_clk: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_CLK";
ATTRIBUTE X_INTERFACE_INFO OF phy_crs: SIGNAL IS "xilinx.com:interface:mii:1.0 MII CRS";
ATTRIBUTE X_INTERFACE_INFO OF phy_dv: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_DV";
ATTRIBUTE X_INTERFACE_INFO OF phy_rx_data: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RXD";
ATTRIBUTE X_INTERFACE_INFO OF phy_col: SIGNAL IS "xilinx.com:interface:mii:1.0 MII COL";
ATTRIBUTE X_INTERFACE_INFO OF phy_rx_er: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_ER";
ATTRIBUTE X_INTERFACE_INFO OF phy_rst_n: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RST_N";
ATTRIBUTE X_INTERFACE_INFO OF phy_tx_en: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TX_EN";
ATTRIBUTE X_INTERFACE_INFO OF phy_tx_data: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TXD";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdio_i: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDIO_I";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdio_o: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDIO_O";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdio_t: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDIO_T";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdc: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDC";
BEGIN
U0 : axi_ethernetlite
GENERIC MAP (
C_FAMILY => "artix7",
C_SELECT_XPM => 1,
C_INSTANCE => "axi_ethernetlite_inst",
C_S_AXI_ACLK_PERIOD_PS => 10000,
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 1,
C_S_AXI_PROTOCOL => "AXI4LITE",
C_INCLUDE_MDIO => 1,
C_INCLUDE_INTERNAL_LOOPBACK => 0,
C_INCLUDE_GLOBAL_BUFFERS => 1,
C_DUPLEX => 1,
C_TX_PING_PONG => 1,
C_RX_PING_PONG => 1
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
ip2intc_irpt => ip2intc_irpt,
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => '1',
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => s_axi_araddr,
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
phy_tx_clk => phy_tx_clk,
phy_rx_clk => phy_rx_clk,
phy_crs => phy_crs,
phy_dv => phy_dv,
phy_rx_data => phy_rx_data,
phy_col => phy_col,
phy_rx_er => phy_rx_er,
phy_rst_n => phy_rst_n,
phy_tx_en => phy_tx_en,
phy_tx_data => phy_tx_data,
phy_mdio_i => phy_mdio_i,
phy_mdio_o => phy_mdio_o,
phy_mdio_t => phy_mdio_t,
phy_mdc => phy_mdc
);
END system_axi_ethernetlite_0_0_arch;
|
apache-2.0
|
8c96be160c50082013becf30e41a2fab
| 0.671471 | 3.163271 | false | false | false | false |
KPU-RISC/KPU
|
VHDL/SRAM256Bytes.vhd
| 1 | 8,099 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/22/2015 09:57:12 AM
-- Design Name:
-- Module Name: SRAM256Bytes - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SRAM256Bytes is
Port
(
Load : in BIT;
Sel : in BIT;
Address : in BIT_VECTOR(7 downto 0);
InData : in BIT_VECTOR(7 downto 0);
OutData : out BIT_VECTOR(7 downto 0)
);
end SRAM256Bytes;
architecture Behavioral of SRAM256Bytes is
component SRAM16Bytes is
Port
(
Load : in BIT;
Sel : in BIT;
Address : in BIT_VECTOR(3 downto 0);
InData : in BIT_VECTOR(7 downto 0);
OutData : out BIT_VECTOR(7 downto 0)
);
end component SRAM16Bytes;
component Decoder2to4 is
Port
(
A : in BIT_VECTOR(1 downto 0); -- 2-Bit Memory Address (Input)
X : out BIT_VECTOR(3 downto 0) -- 4-Bit Address Lines (Output)
);
end component Decoder2to4;
signal AccessLines1: BIT_VECTOR(3 downto 0);
signal AccessLines2: BIT_VECTOR(3 downto 0);
signal OutData1 : BIT_VECTOR(7 downto 0);
signal OutData2 : BIT_VECTOR(7 downto 0);
signal OutData3 : BIT_VECTOR(7 downto 0);
signal OutData4 : BIT_VECTOR(7 downto 0);
signal OutData5 : BIT_VECTOR(7 downto 0);
signal OutData6 : BIT_VECTOR(7 downto 0);
signal OutData7 : BIT_VECTOR(7 downto 0);
signal OutData8 : BIT_VECTOR(7 downto 0);
signal OutData9 : BIT_VECTOR(7 downto 0);
signal OutData10 : BIT_VECTOR(7 downto 0);
signal OutData11 : BIT_VECTOR(7 downto 0);
signal OutData12 : BIT_VECTOR(7 downto 0);
signal OutData13 : BIT_VECTOR(7 downto 0);
signal OutData14 : BIT_VECTOR(7 downto 0);
signal OutData15 : BIT_VECTOR(7 downto 0);
signal OutData16 : BIT_VECTOR(7 downto 0);
signal LoadLine1: BIT;
signal LoadLine2: BIT;
signal LoadLine3: BIT;
signal LoadLine4: BIT;
signal LoadLine5: BIT;
signal LoadLine6: BIT;
signal LoadLine7: BIT;
signal LoadLine8: BIT;
signal LoadLine9: BIT;
signal LoadLine10: BIT;
signal LoadLine11: BIT;
signal LoadLine12: BIT;
signal LoadLine13: BIT;
signal LoadLine14: BIT;
signal LoadLine15: BIT;
signal LoadLine16: BIT;
signal SelectLine1: BIT;
signal SelectLine2: BIT;
signal SelectLine3: BIT;
signal SelectLine4: BIT;
signal SelectLine5: BIT;
signal SelectLine6: BIT;
signal SelectLine7: BIT;
signal SelectLine8: BIT;
signal SelectLine9: BIT;
signal SelectLine10: BIT;
signal SelectLine11: BIT;
signal SelectLine12: BIT;
signal SelectLine13: BIT;
signal SelectLine14: BIT;
signal SelectLine15: BIT;
signal SelectLine16: BIT;
begin
-- The 16 16-byte SRAM memory cells are logically arranged in a 4x4 matrix
-- 1 2 3 4
-- 5 6 7 8
-- 9 10 11 12
-- 13 14 14 16
-- The 1st decoder takes the lower 2 bits of the address and provides the row offset into the 4x4 matrix
Decoder1: Decoder2to4 port map(Address(5 downto 4), AccessLines1);
-- The 2nd decoder takes the upper 2 bits of the address and provides the column offset into the 4x4 matrix
Decoder2: Decoder2to4 port map(Address(7 downto 6), AccessLines2);
-- Create a dedicate Load-Line for every 16-byte SRAM memory cell
LoadLine1 <= Load and AccessLines1(0) and AccessLines2(0);
LoadLine2 <= Load and AccessLines1(1) and AccessLines2(0);
LoadLine3 <= Load and AccessLines1(2) and AccessLines2(0);
LoadLine4 <= Load and AccessLines1(3) and AccessLines2(0);
LoadLine5 <= Load and AccessLines1(0) and AccessLines2(1);
LoadLine6 <= Load and AccessLines1(1) and AccessLines2(1);
LoadLine7 <= Load and AccessLines1(2) and AccessLines2(1);
LoadLine8 <= Load and AccessLines1(3) and AccessLines2(1);
LoadLine9 <= Load and AccessLines1(0) and AccessLines2(2);
LoadLine10 <= Load and AccessLines1(1) and AccessLines2(2);
LoadLine11 <= Load and AccessLines1(2) and AccessLines2(2);
LoadLine12 <= Load and AccessLines1(3) and AccessLines2(2);
LoadLine13 <= Load and AccessLines1(0) and AccessLines2(3);
LoadLine14 <= Load and AccessLines1(1) and AccessLines2(3);
LoadLine15 <= Load and AccessLines1(2) and AccessLines2(3);
LoadLine16 <= Load and AccessLines1(3) and AccessLines2(3);
-- Create a dedicate Select-Line for every 16-byte SRAM memory cell
SelectLine1 <= Sel and AccessLines1(0) and AccessLines2(0);
SelectLine2 <= Sel and AccessLines1(1) and AccessLines2(0);
SelectLine3 <= Sel and AccessLines1(2) and AccessLines2(0);
SelectLine4 <= Sel and AccessLines1(3) and AccessLines2(0);
SelectLine5 <= Sel and AccessLines1(0) and AccessLines2(1);
SelectLine6 <= Sel and AccessLines1(1) and AccessLines2(1);
SelectLine7 <= Sel and AccessLines1(2) and AccessLines2(1);
SelectLine8 <= Sel and AccessLines1(3) and AccessLines2(1);
SelectLine9 <= Sel and AccessLines1(0) and AccessLines2(2);
SelectLine10 <= Sel and AccessLines1(1) and AccessLines2(2);
SelectLine11 <= Sel and AccessLines1(2) and AccessLines2(2);
SelectLine12 <= Sel and AccessLines1(3) and AccessLines2(2);
SelectLine13 <= Sel and AccessLines1(0) and AccessLines2(3);
SelectLine14 <= Sel and AccessLines1(1) and AccessLines2(3);
SelectLine15 <= Sel and AccessLines1(2) and AccessLines2(3);
SelectLine16 <= Sel and AccessLines1(3) and AccessLines2(3);
-- Instantiate the 16 individual 8-bit SRAM memory cells
ram1: SRAM16Bytes port map (LoadLine1, SelectLine1, Address(3 downto 0), InData, OutData1);
ram2: SRAM16Bytes port map (LoadLine2, SelectLine2, Address(3 downto 0), InData, OutData2);
ram3: SRAM16Bytes port map (LoadLine3, SelectLine3, Address(3 downto 0), InData, OutData3);
ram4: SRAM16Bytes port map (LoadLine4, SelectLine4, Address(3 downto 0), InData, OutData4);
ram5: SRAM16Bytes port map (LoadLine5, SelectLine5, Address(3 downto 0), InData, OutData5);
ram6: SRAM16Bytes port map (LoadLine6, SelectLine6, Address(3 downto 0), InData, OutData6);
ram7: SRAM16Bytes port map (LoadLine7, SelectLine7, Address(3 downto 0), InData, OutData7);
ram8: SRAM16Bytes port map (LoadLine8, SelectLine8, Address(3 downto 0), InData, OutData8);
ram9: SRAM16Bytes port map (LoadLine9, SelectLine9, Address(3 downto 0), InData, OutData9);
ram10: SRAM16Bytes port map (LoadLine10, SelectLine10, Address(3 downto 0), InData, OutData10);
ram11: SRAM16Bytes port map (LoadLine11, SelectLine11, Address(3 downto 0), InData, OutData11);
ram12: SRAM16Bytes port map (LoadLine12, SelectLine12, Address(3 downto 0), InData, OutData12);
ram13: SRAM16Bytes port map (LoadLine13, SelectLine13, Address(3 downto 0), InData, OutData13);
ram14: SRAM16Bytes port map (LoadLine14, SelectLine14, Address(3 downto 0), InData, OutData14);
ram15: SRAM16Bytes port map (LoadLine15, SelectLine15, Address(3 downto 0), InData, OutData15);
ram16: SRAM16Bytes port map (LoadLine16, SelectLine16, Address(3 downto 0), InData, OutData16);
-- Return the read data
OutData <= OutData1 or
OutData2 or
OutData3 or
OutData4 or
OutData5 or
OutData6 or
OutData7 or
OutData8 or
OutData9 or
OutData10 or
OutData11 or
OutData12 or
OutData13 or
OutData14 or
OutData15 or
OutData16;
end Behavioral;
|
mit
|
d55bf70410eef9321c65dfe56fe73cfd
| 0.671811 | 3.78812 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_microblaze_0_axi_intc_0/sim/system_microblaze_0_axi_intc_0.vhd
| 1 | 10,463 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_intc:4.1
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_intc_v4_1_9;
USE axi_intc_v4_1_9.axi_intc;
ENTITY system_microblaze_0_axi_intc_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
intr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
processor_clk : IN STD_LOGIC;
processor_rst : IN STD_LOGIC;
irq : OUT STD_LOGIC;
processor_ack : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
interrupt_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_microblaze_0_axi_intc_0;
ARCHITECTURE system_microblaze_0_axi_intc_0_arch OF system_microblaze_0_axi_intc_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_microblaze_0_axi_intc_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_intc IS
GENERIC (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_NUM_INTR_INPUTS : INTEGER;
C_NUM_SW_INTR : INTEGER;
C_KIND_OF_INTR : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_KIND_OF_EDGE : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_KIND_OF_LVL : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_ASYNC_INTR : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_NUM_SYNC_FF : INTEGER;
C_IVAR_RESET_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_ENABLE_ASYNC : INTEGER;
C_HAS_IPR : INTEGER;
C_HAS_SIE : INTEGER;
C_HAS_CIE : INTEGER;
C_HAS_IVR : INTEGER;
C_HAS_ILR : INTEGER;
C_IRQ_IS_LEVEL : INTEGER;
C_IRQ_ACTIVE : STD_LOGIC;
C_DISABLE_SYNCHRONIZERS : INTEGER;
C_MB_CLK_NOT_CONNECTED : INTEGER;
C_HAS_FAST : INTEGER;
C_EN_CASCADE_MODE : INTEGER;
C_CASCADE_MASTER : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
intr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
processor_clk : IN STD_LOGIC;
processor_rst : IN STD_LOGIC;
irq : OUT STD_LOGIC;
processor_ack : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
interrupt_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
irq_in : IN STD_LOGIC;
interrupt_address_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
processor_ack_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT axi_intc;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_resetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RREADY";
ATTRIBUTE X_INTERFACE_INFO OF intr: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt_input INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF processor_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 proc_clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF processor_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 proc_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF irq: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 interrupt INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF processor_ack: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 interrupt ACK";
ATTRIBUTE X_INTERFACE_INFO OF interrupt_address: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 interrupt ADDRESS";
BEGIN
U0 : axi_intc
GENERIC MAP (
C_FAMILY => "artix7",
C_INSTANCE => "system_microblaze_0_axi_intc_0",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_NUM_INTR_INPUTS => 7,
C_NUM_SW_INTR => 0,
C_KIND_OF_INTR => X"ffffffb2",
C_KIND_OF_EDGE => X"FFFFFFFF",
C_KIND_OF_LVL => X"FFFFFFFF",
C_ASYNC_INTR => X"FFFFFFC2",
C_NUM_SYNC_FF => 2,
C_IVAR_RESET_VALUE => X"00000010",
C_ENABLE_ASYNC => 0,
C_HAS_IPR => 1,
C_HAS_SIE => 1,
C_HAS_CIE => 1,
C_HAS_IVR => 1,
C_HAS_ILR => 0,
C_IRQ_IS_LEVEL => 1,
C_IRQ_ACTIVE => '1',
C_DISABLE_SYNCHRONIZERS => 0,
C_MB_CLK_NOT_CONNECTED => 1,
C_HAS_FAST => 1,
C_EN_CASCADE_MODE => 0,
C_CASCADE_MASTER => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
intr => intr,
processor_clk => processor_clk,
processor_rst => processor_rst,
irq => irq,
processor_ack => processor_ack,
interrupt_address => interrupt_address,
irq_in => '0',
interrupt_address_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END system_microblaze_0_axi_intc_0_arch;
|
apache-2.0
|
837bbcadeb8c8216cacff559c7b863cf
| 0.67667 | 3.303757 | false | false | false | false |
daniw/add
|
floppy/mcu/cpu_prc.vhd
| 1 | 2,603 |
-------------------------------------------------------------------------------
-- Entity: cpu_prc
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- Program Counter unit for the RISC-CPU of the von-Neuman MCU.
-------------------------------------------------------------------------------
-- Total # of FFs: 8 + 2
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity cpu_prc is
port(rst : in std_logic;
clk : in std_logic;
-- CPU internal interfaces
ctr_in : in t_ctr2prc;
ctr_out : out t_prc2ctr
);
end cpu_prc;
architecture rtl of cpu_prc is
-- program counter and exception signals
signal pc : std_logic_vector(AW-1 downto 0);
signal exc : t_addr_exc;
begin
-- assign outputs
ctr_out.pc <= pc;
ctr_out.exc <= exc;
-----------------------------------------------------------------------------
-- Program Counter
-----------------------------------------------------------------------------
P_pc: process(clk, rst)
variable v_pc : std_logic_vector(AW-1 downto 0);
variable v_addr : std_logic_vector(AW downto 0);
begin
if rst = '1' then
pc <= (others => '0');
exc <= no_err;
elsif rising_edge(clk) then
if ctr_in.enb = '1' then
exc <= no_err; -- default assignment
case ctr_in.mode is
when linear =>
-- PC := PC + 1
v_pc := std_logic_vector(unsigned(pc) + 1);
if unsigned(v_pc) >= unsigned(BA(RAM)) then
-- PC would leave ROM address space
-- do not increment and issue error
exc <= lin_err;
else
pc <= v_pc;
end if;
when abs_jump =>
-- PC := addr
pc <= ctr_in.addr;
when rel_offset =>
-- PC := PC + addr
v_addr := std_logic_vector(unsigned('0' & pc) + unsigned(ctr_in.addr));
pc <= v_addr(AW-1 downto 0);
if v_addr(AW) = '1' and ctr_in.addr(AW-1) = '0' then
-- overflow with addition of positive relative offset
exc <= rel_err;
elsif v_addr(AW) = '0' and ctr_in.addr(AW-1) = '1' then
-- underflow with addition of negative relative offset
exc <= rel_err;
end if;
when others => null;
end case;
end if;
end if;
end process;
end rtl;
|
gpl-2.0
|
719009f10b6a42fcb0e68433e9ab6624
| 0.426047 | 4.225649 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 2/WindowsManager.vhd
| 1 | 1,820 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity WindowsManager is
Port ( rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
op : in STD_LOGIC_VECTOR (1 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
CWP : in STD_LOGIC:='0';
nRs1 : out STD_LOGIC_VECTOR (5 downto 0);
nRs2 : out STD_LOGIC_VECTOR (5 downto 0);
nRd : out STD_LOGIC_VECTOR (5 downto 0);
nCWP : out STD_LOGIC:='0');
end WindowsManager;
architecture Behavioral of WindowsManager is
begin
process(rs1,rs2,rd,op,op3,CWP)
begin
if(CWP='0') then
nRs1<='0'&rs1;
nRs2<='0'&rs2;
nRd<='0'&rd;
else
------------------rs1------------------
if(rs1>=24 and rs1<=31) then
nRs1<=rs1-"010000";
elsif((rs1>=16 and rs1<=23) or (rs1>=8 and rs1<=15)) then
nRs1<=rs1+"010000";
else
nRs1<='0'&rs1;
end if;
-----------------rs2----------------------
if(rs2>=24 and rs2<=31) then
nRs2<=rs2-"010000";
elsif((rs2>=16 and rs2<=23) or (rs2>=8 and rs2<=15)) then
nRs2<=rs2+"010000";
else
nRs2<='0'&rs2;
end if;
-----------------rd-------------------------
if(rd>=24 and rd<=31) then
nRd<=rd-"010000";
elsif((rd>=16 and rd<=23)or(rd>=8 and rd<=15)) then
nRd<=rd+"010000";
else
nRd<='0'&rd;
end if;
end if;
if((op="10") and (op3="111100" or op3="111101")) then --SAVE or Restore
nCWP<=not(CWP);
if (CWP='1') then
nRd<='0'&rd;
else
if(rd>=24 and rd<=31) then
nRd<=rd-"010000";
elsif((rd>=16 and rd<=23) or (rd>=8 and rd<=15)) then
nRd<=rd+"010000";
else
nRd<='0'&rd;
end if;
end if;
else
nCWP<=CWP;
end if;
end process;
end Behavioral;
|
mit
|
5b206053e2cffd70a67080c5741a7e3f
| 0.528022 | 2.745098 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_gpio_led_0/synth/system_axi_gpio_led_0.vhd
| 1 | 10,508 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_13;
USE axi_gpio_v2_0_13.axi_gpio;
ENTITY system_axi_gpio_led_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END system_axi_gpio_led_0;
ARCHITECTURE system_axi_gpio_led_0_arch OF system_axi_gpio_led_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_gpio_led_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_axi_gpio_led_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_axi_gpio_led_0_arch : ARCHITECTURE IS "system_axi_gpio_led_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_axi_gpio_led_0_arch: ARCHITECTURE IS "system_axi_gpio_led_0,axi_gpio,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=13,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=4,C_GPIO2_WIDTH=12,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=1,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 12,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 1,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => gpio2_io_i,
gpio2_io_o => gpio2_io_o,
gpio2_io_t => gpio2_io_t
);
END system_axi_gpio_led_0_arch;
|
apache-2.0
|
905ac0297123a48ee676c3d728bbe404
| 0.687762 | 3.145166 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_xadc_wiz_0_0/system_xadc_wiz_0_0_sim_netlist.vhdl
| 1 | 304,475 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:44:11 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_xadc_wiz_0_0/system_xadc_wiz_0_0_sim_netlist.vhdl
-- Design : system_xadc_wiz_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xadc_wiz_0_0_drp_arbiter is
port (
den_C : out STD_LOGIC;
dwe_C : out STD_LOGIC;
overlap_A_reg_0 : out STD_LOGIC;
overlap_B_reg_0 : out STD_LOGIC;
drdy_i : out STD_LOGIC;
\state_reg[1]_0\ : out STD_LOGIC;
den_reg_reg_0 : out STD_LOGIC;
drdy_wr_ack_i_reg : out STD_LOGIC;
drdy_rd_ack_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
\status_reg_reg[7]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\status_reg_reg[7]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
\do_reg_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_aclk : in STD_LOGIC;
reset : in STD_LOGIC;
dwe_d1 : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]\ : in STD_LOGIC;
den_C_reg_reg_0 : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]_0\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
den_A : in STD_LOGIC;
bbusy_A : in STD_LOGIC;
drdy_C : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
den_o_reg : in STD_LOGIC;
drdy_wr_ack_i_d2 : in STD_LOGIC;
drdy_wr_ack_i_d1 : in STD_LOGIC;
drdy_rd_ack_i_d2 : in STD_LOGIC;
drdy_rd_ack_i_d1 : in STD_LOGIC;
DO : in STD_LOGIC_VECTOR ( 15 downto 0 );
den_d1 : in STD_LOGIC;
den_o_reg_0 : in STD_LOGIC;
den_o_reg_1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xadc_wiz_0_0_drp_arbiter : entity is "drp_arbiter";
end system_xadc_wiz_0_0_drp_arbiter;
architecture STRUCTURE of system_xadc_wiz_0_0_drp_arbiter is
signal \daddr_C_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \daddr_C_reg[1]_i_1_n_0\ : STD_LOGIC;
signal \daddr_C_reg[2]_i_1_n_0\ : STD_LOGIC;
signal \daddr_C_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \daddr_C_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \daddr_C_reg[5]_i_1_n_0\ : STD_LOGIC;
signal \daddr_C_reg[6]_i_1_n_0\ : STD_LOGIC;
signal \daddr_C_reg[6]_i_2_n_0\ : STD_LOGIC;
signal \daddr_C_reg[6]_i_3_n_0\ : STD_LOGIC;
signal \daddr_C_reg[6]_i_4_n_0\ : STD_LOGIC;
signal \daddr_C_reg[6]_i_5_n_0\ : STD_LOGIC;
signal \daddr_C_reg[6]_i_6_n_0\ : STD_LOGIC;
signal \daddr_C_reg[6]_i_7_n_0\ : STD_LOGIC;
signal \daddr_C_reg[6]_i_8_n_0\ : STD_LOGIC;
signal \daddr_C_reg[6]_i_9_n_0\ : STD_LOGIC;
signal daddr_reg : STD_LOGIC_VECTOR ( 6 downto 0 );
signal \daddr_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \daddr_reg[1]_i_1_n_0\ : STD_LOGIC;
signal \daddr_reg[2]_i_1_n_0\ : STD_LOGIC;
signal \daddr_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \daddr_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \daddr_reg[5]_i_1_n_0\ : STD_LOGIC;
signal \daddr_reg[6]_i_1_n_0\ : STD_LOGIC;
signal \daddr_reg[6]_i_2_n_0\ : STD_LOGIC;
signal \daddr_reg[6]_i_3_n_0\ : STD_LOGIC;
signal den_C_reg_i_1_n_0 : STD_LOGIC;
signal den_C_reg_i_2_n_0 : STD_LOGIC;
signal den_C_reg_i_3_n_0 : STD_LOGIC;
signal den_reg_i_1_n_0 : STD_LOGIC;
signal \^den_reg_reg_0\ : STD_LOGIC;
signal den_reg_reg_n_0 : STD_LOGIC;
signal \di_C_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \di_C_reg[10]_i_1_n_0\ : STD_LOGIC;
signal \di_C_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \di_C_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \di_C_reg[13]_i_1_n_0\ : STD_LOGIC;
signal \di_C_reg[14]_i_1_n_0\ : STD_LOGIC;
signal \di_C_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \di_C_reg[1]_i_1_n_0\ : STD_LOGIC;
signal \di_C_reg[2]_i_1_n_0\ : STD_LOGIC;
signal \di_C_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \di_C_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \di_C_reg[5]_i_1_n_0\ : STD_LOGIC;
signal \di_C_reg[6]_i_1_n_0\ : STD_LOGIC;
signal \di_C_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \di_C_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \di_C_reg[9]_i_1_n_0\ : STD_LOGIC;
signal di_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \di_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \di_reg[10]_i_1_n_0\ : STD_LOGIC;
signal \di_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \di_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \di_reg[13]_i_1_n_0\ : STD_LOGIC;
signal \di_reg[14]_i_1_n_0\ : STD_LOGIC;
signal \di_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \di_reg[1]_i_1_n_0\ : STD_LOGIC;
signal \di_reg[2]_i_1_n_0\ : STD_LOGIC;
signal \di_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \di_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \di_reg[5]_i_1_n_0\ : STD_LOGIC;
signal \di_reg[6]_i_1_n_0\ : STD_LOGIC;
signal \di_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \di_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \di_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \do_A_reg[10]_i_1_n_0\ : STD_LOGIC;
signal \do_A_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \do_A_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \do_A_reg[13]_i_1_n_0\ : STD_LOGIC;
signal \do_A_reg[14]_i_1_n_0\ : STD_LOGIC;
signal \do_A_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \do_A_reg[15]_i_2_n_0\ : STD_LOGIC;
signal \do_A_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \do_A_reg[5]_i_1_n_0\ : STD_LOGIC;
signal \do_A_reg[6]_i_1_n_0\ : STD_LOGIC;
signal \do_A_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \do_A_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \do_A_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \do_B_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \do_B_reg[10]_i_1_n_0\ : STD_LOGIC;
signal \do_B_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \do_B_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \do_B_reg[13]_i_1_n_0\ : STD_LOGIC;
signal \do_B_reg[14]_i_1_n_0\ : STD_LOGIC;
signal \do_B_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \do_B_reg[15]_i_2_n_0\ : STD_LOGIC;
signal \do_B_reg[1]_i_1_n_0\ : STD_LOGIC;
signal \do_B_reg[2]_i_1_n_0\ : STD_LOGIC;
signal \do_B_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \do_B_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \do_B_reg[5]_i_1_n_0\ : STD_LOGIC;
signal \do_B_reg[6]_i_1_n_0\ : STD_LOGIC;
signal \do_B_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \do_B_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \do_B_reg[9]_i_1_n_0\ : STD_LOGIC;
signal drdy_A_reg_i_1_n_0 : STD_LOGIC;
signal drdy_B : STD_LOGIC;
signal drdy_B_reg_i_1_n_0 : STD_LOGIC;
signal \^drdy_i\ : STD_LOGIC;
signal dwe_C_reg_i_1_n_0 : STD_LOGIC;
signal dwe_reg_i_1_n_0 : STD_LOGIC;
signal dwe_reg_reg_n_0 : STD_LOGIC;
signal overlap_A_i_1_n_0 : STD_LOGIC;
signal overlap_A_i_2_n_0 : STD_LOGIC;
signal overlap_A_i_3_n_0 : STD_LOGIC;
signal \^overlap_a_reg_0\ : STD_LOGIC;
signal overlap_B_i_1_n_0 : STD_LOGIC;
signal overlap_B_i_4_n_0 : STD_LOGIC;
signal \^overlap_b_reg_0\ : STD_LOGIC;
signal \state[0]_i_1_n_0\ : STD_LOGIC;
signal \state[0]_i_2__0_n_0\ : STD_LOGIC;
signal \state[0]_i_3__0_n_0\ : STD_LOGIC;
signal \state[0]_i_4__0_n_0\ : STD_LOGIC;
signal \state[1]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_2__0_n_0\ : STD_LOGIC;
signal \state[1]_i_3__0_n_0\ : STD_LOGIC;
signal \state[1]_i_4_n_0\ : STD_LOGIC;
signal \state[1]_i_5_n_0\ : STD_LOGIC;
signal \^state_reg[1]_0\ : STD_LOGIC;
signal \state_reg_n_0_[1]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \daddr_C_reg[6]_i_3\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \daddr_C_reg[6]_i_4\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \daddr_C_reg[6]_i_5\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \daddr_C_reg[6]_i_6\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of den_reg_i_1 : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \di_reg[0]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \di_reg[10]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \di_reg[11]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \di_reg[12]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \di_reg[13]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \di_reg[14]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \di_reg[15]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \di_reg[1]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \di_reg[2]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \di_reg[3]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \di_reg[4]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \di_reg[5]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \di_reg[6]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \di_reg[7]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \di_reg[8]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \di_reg[9]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \do_A_reg[10]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \do_A_reg[11]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \do_A_reg[12]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \do_A_reg[13]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \do_A_reg[14]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \do_A_reg[15]_i_2\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \do_A_reg[4]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \do_A_reg[5]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \do_A_reg[6]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \do_A_reg[7]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \do_A_reg[8]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \do_A_reg[9]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \do_B_reg[10]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \do_B_reg[11]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \do_B_reg[12]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \do_B_reg[13]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \do_B_reg[14]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \do_B_reg[15]_i_2\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \do_B_reg[1]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \do_B_reg[2]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \do_B_reg[3]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \do_B_reg[4]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \do_B_reg[5]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \do_B_reg[6]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \do_B_reg[7]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \do_B_reg[8]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \do_B_reg[9]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of drdy_A_reg_i_1 : label is "soft_lutpair36";
attribute SOFT_HLUTNM of drdy_B_reg_i_1 : label is "soft_lutpair36";
attribute SOFT_HLUTNM of overlap_A_i_3 : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \state[0]_i_3__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \state[0]_i_4__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \state[1]_i_5\ : label is "soft_lutpair32";
begin
den_reg_reg_0 <= \^den_reg_reg_0\;
drdy_i <= \^drdy_i\;
overlap_A_reg_0 <= \^overlap_a_reg_0\;
overlap_B_reg_0 <= \^overlap_b_reg_0\;
\state_reg[1]_0\ <= \^state_reg[1]_0\;
\daddr_C_reg[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4540FFFF45404540"
)
port map (
I0 => \daddr_C_reg[6]_i_7_n_0\,
I1 => s_axi_araddr(0),
I2 => s_axi_arvalid,
I3 => s_axi_awaddr(0),
I4 => \daddr_C_reg[6]_i_8_n_0\,
I5 => daddr_reg(0),
O => \daddr_C_reg[0]_i_1_n_0\
);
\daddr_C_reg[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4540FFFF45404540"
)
port map (
I0 => \daddr_C_reg[6]_i_7_n_0\,
I1 => s_axi_araddr(1),
I2 => s_axi_arvalid,
I3 => s_axi_awaddr(1),
I4 => \daddr_C_reg[6]_i_8_n_0\,
I5 => daddr_reg(1),
O => \daddr_C_reg[1]_i_1_n_0\
);
\daddr_C_reg[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4540FFFF45404540"
)
port map (
I0 => \daddr_C_reg[6]_i_7_n_0\,
I1 => s_axi_araddr(2),
I2 => s_axi_arvalid,
I3 => s_axi_awaddr(2),
I4 => \daddr_C_reg[6]_i_8_n_0\,
I5 => daddr_reg(2),
O => \daddr_C_reg[2]_i_1_n_0\
);
\daddr_C_reg[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4540FFFF45404540"
)
port map (
I0 => \daddr_C_reg[6]_i_7_n_0\,
I1 => s_axi_araddr(3),
I2 => s_axi_arvalid,
I3 => s_axi_awaddr(3),
I4 => \daddr_C_reg[6]_i_8_n_0\,
I5 => daddr_reg(3),
O => \daddr_C_reg[3]_i_1_n_0\
);
\daddr_C_reg[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4540FFFF45404540"
)
port map (
I0 => \daddr_C_reg[6]_i_7_n_0\,
I1 => s_axi_araddr(4),
I2 => s_axi_arvalid,
I3 => s_axi_awaddr(4),
I4 => \daddr_C_reg[6]_i_8_n_0\,
I5 => daddr_reg(4),
O => \daddr_C_reg[4]_i_1_n_0\
);
\daddr_C_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4540FFFF45404540"
)
port map (
I0 => \daddr_C_reg[6]_i_7_n_0\,
I1 => s_axi_araddr(5),
I2 => s_axi_arvalid,
I3 => s_axi_awaddr(5),
I4 => \daddr_C_reg[6]_i_8_n_0\,
I5 => daddr_reg(5),
O => \daddr_C_reg[5]_i_1_n_0\
);
\daddr_C_reg[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEFEFEFEFFFE"
)
port map (
I0 => \state[1]_i_3__0_n_0\,
I1 => \daddr_C_reg[6]_i_3_n_0\,
I2 => \daddr_C_reg[6]_i_4_n_0\,
I3 => \daddr_C_reg[6]_i_5_n_0\,
I4 => \daddr_C_reg[6]_i_6_n_0\,
I5 => den_C_reg_reg_0,
O => \daddr_C_reg[6]_i_1_n_0\
);
\daddr_C_reg[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"4540FFFF45404540"
)
port map (
I0 => \daddr_C_reg[6]_i_7_n_0\,
I1 => s_axi_araddr(6),
I2 => s_axi_arvalid,
I3 => s_axi_awaddr(6),
I4 => \daddr_C_reg[6]_i_8_n_0\,
I5 => daddr_reg(6),
O => \daddr_C_reg[6]_i_2_n_0\
);
\daddr_C_reg[6]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"10101000"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => bbusy_A,
I2 => \^state_reg[1]_0\,
I3 => \^den_reg_reg_0\,
I4 => \^overlap_b_reg_0\,
O => \daddr_C_reg[6]_i_3_n_0\
);
\daddr_C_reg[6]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FD550000"
)
port map (
I0 => drdy_C,
I1 => den_A,
I2 => \^overlap_a_reg_0\,
I3 => \state_reg_n_0_[1]\,
I4 => \^state_reg[1]_0\,
O => \daddr_C_reg[6]_i_4_n_0\
);
\daddr_C_reg[6]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF1"
)
port map (
I0 => \^den_reg_reg_0\,
I1 => den_A,
I2 => \^overlap_b_reg_0\,
I3 => \^overlap_a_reg_0\,
O => \daddr_C_reg[6]_i_5_n_0\
);
\daddr_C_reg[6]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \^state_reg[1]_0\,
I1 => bbusy_A,
I2 => \state_reg_n_0_[1]\,
O => \daddr_C_reg[6]_i_6_n_0\
);
\daddr_C_reg[6]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAA8AA"
)
port map (
I0 => \daddr_C_reg[6]_i_9_n_0\,
I1 => den_A,
I2 => \daddr_C_reg[6]_i_6_n_0\,
I3 => \^den_reg_reg_0\,
I4 => \^overlap_b_reg_0\,
I5 => \^overlap_a_reg_0\,
O => \daddr_C_reg[6]_i_7_n_0\
);
\daddr_C_reg[6]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F7F2F7F7F7F2A3B"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => \^overlap_a_reg_0\,
I2 => drdy_C,
I3 => \^overlap_b_reg_0\,
I4 => bbusy_A,
I5 => \^state_reg[1]_0\,
O => \daddr_C_reg[6]_i_8_n_0\
);
\daddr_C_reg[6]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF0075FF"
)
port map (
I0 => \^state_reg[1]_0\,
I1 => bbusy_A,
I2 => \^overlap_b_reg_0\,
I3 => drdy_C,
I4 => \state_reg_n_0_[1]\,
O => \daddr_C_reg[6]_i_9_n_0\
);
\daddr_C_reg_reg[0]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_C_reg[6]_i_1_n_0\,
CLR => reset,
D => \daddr_C_reg[0]_i_1_n_0\,
Q => \status_reg_reg[7]\(0)
);
\daddr_C_reg_reg[1]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_C_reg[6]_i_1_n_0\,
CLR => reset,
D => \daddr_C_reg[1]_i_1_n_0\,
Q => \status_reg_reg[7]\(1)
);
\daddr_C_reg_reg[2]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_C_reg[6]_i_1_n_0\,
CLR => reset,
D => \daddr_C_reg[2]_i_1_n_0\,
Q => \status_reg_reg[7]\(2)
);
\daddr_C_reg_reg[3]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_C_reg[6]_i_1_n_0\,
CLR => reset,
D => \daddr_C_reg[3]_i_1_n_0\,
Q => \status_reg_reg[7]\(3)
);
\daddr_C_reg_reg[4]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_C_reg[6]_i_1_n_0\,
CLR => reset,
D => \daddr_C_reg[4]_i_1_n_0\,
Q => \status_reg_reg[7]\(4)
);
\daddr_C_reg_reg[5]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_C_reg[6]_i_1_n_0\,
CLR => reset,
D => \daddr_C_reg[5]_i_1_n_0\,
Q => \status_reg_reg[7]\(5)
);
\daddr_C_reg_reg[6]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_C_reg[6]_i_1_n_0\,
CLR => reset,
D => \daddr_C_reg[6]_i_2_n_0\,
Q => \status_reg_reg[7]\(6)
);
\daddr_reg[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00E2E2E2"
)
port map (
I0 => s_axi_awaddr(0),
I1 => s_axi_arvalid,
I2 => s_axi_araddr(0),
I3 => \^state_reg[1]_0\,
I4 => \state_reg_n_0_[1]\,
O => \daddr_reg[0]_i_1_n_0\
);
\daddr_reg[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00E2E2E2"
)
port map (
I0 => s_axi_awaddr(1),
I1 => s_axi_arvalid,
I2 => s_axi_araddr(1),
I3 => \^state_reg[1]_0\,
I4 => \state_reg_n_0_[1]\,
O => \daddr_reg[1]_i_1_n_0\
);
\daddr_reg[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00E2E2E2"
)
port map (
I0 => s_axi_awaddr(2),
I1 => s_axi_arvalid,
I2 => s_axi_araddr(2),
I3 => \^state_reg[1]_0\,
I4 => \state_reg_n_0_[1]\,
O => \daddr_reg[2]_i_1_n_0\
);
\daddr_reg[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00E2E2E2"
)
port map (
I0 => s_axi_awaddr(3),
I1 => s_axi_arvalid,
I2 => s_axi_araddr(3),
I3 => \^state_reg[1]_0\,
I4 => \state_reg_n_0_[1]\,
O => \daddr_reg[3]_i_1_n_0\
);
\daddr_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00E2E2E2"
)
port map (
I0 => s_axi_awaddr(4),
I1 => s_axi_arvalid,
I2 => s_axi_araddr(4),
I3 => \^state_reg[1]_0\,
I4 => \state_reg_n_0_[1]\,
O => \daddr_reg[4]_i_1_n_0\
);
\daddr_reg[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00E2E2E2"
)
port map (
I0 => s_axi_awaddr(5),
I1 => s_axi_arvalid,
I2 => s_axi_araddr(5),
I3 => \^state_reg[1]_0\,
I4 => \state_reg_n_0_[1]\,
O => \daddr_reg[5]_i_1_n_0\
);
\daddr_reg[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0CCF0CC80CC8080"
)
port map (
I0 => \daddr_reg[6]_i_3_n_0\,
I1 => \^den_reg_reg_0\,
I2 => den_A,
I3 => \state_reg_n_0_[1]\,
I4 => bbusy_A,
I5 => \^state_reg[1]_0\,
O => \daddr_reg[6]_i_1_n_0\
);
\daddr_reg[6]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00E2E2E2"
)
port map (
I0 => s_axi_awaddr(6),
I1 => s_axi_arvalid,
I2 => s_axi_araddr(6),
I3 => \^state_reg[1]_0\,
I4 => \state_reg_n_0_[1]\,
O => \daddr_reg[6]_i_2_n_0\
);
\daddr_reg[6]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \^overlap_b_reg_0\,
I1 => \^overlap_a_reg_0\,
I2 => \^state_reg[1]_0\,
I3 => bbusy_A,
I4 => \state_reg_n_0_[1]\,
I5 => den_C_reg_reg_0,
O => \daddr_reg[6]_i_3_n_0\
);
\daddr_reg[6]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => den_d1,
I1 => den_C_reg_reg_0,
I2 => \GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]_0\,
O => \^den_reg_reg_0\
);
\daddr_reg_reg[0]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_reg[6]_i_1_n_0\,
CLR => reset,
D => \daddr_reg[0]_i_1_n_0\,
Q => daddr_reg(0)
);
\daddr_reg_reg[1]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_reg[6]_i_1_n_0\,
CLR => reset,
D => \daddr_reg[1]_i_1_n_0\,
Q => daddr_reg(1)
);
\daddr_reg_reg[2]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_reg[6]_i_1_n_0\,
CLR => reset,
D => \daddr_reg[2]_i_1_n_0\,
Q => daddr_reg(2)
);
\daddr_reg_reg[3]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_reg[6]_i_1_n_0\,
CLR => reset,
D => \daddr_reg[3]_i_1_n_0\,
Q => daddr_reg(3)
);
\daddr_reg_reg[4]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_reg[6]_i_1_n_0\,
CLR => reset,
D => \daddr_reg[4]_i_1_n_0\,
Q => daddr_reg(4)
);
\daddr_reg_reg[5]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_reg[6]_i_1_n_0\,
CLR => reset,
D => \daddr_reg[5]_i_1_n_0\,
Q => daddr_reg(5)
);
\daddr_reg_reg[6]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_reg[6]_i_1_n_0\,
CLR => reset,
D => \daddr_reg[6]_i_2_n_0\,
Q => daddr_reg(6)
);
den_C_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF1FFF1FFFFFFF1"
)
port map (
I0 => \daddr_C_reg[6]_i_5_n_0\,
I1 => \daddr_C_reg[6]_i_6_n_0\,
I2 => den_C_reg_i_2_n_0,
I3 => den_C_reg_i_3_n_0,
I4 => den_reg_reg_n_0,
I5 => \daddr_C_reg[6]_i_8_n_0\,
O => den_C_reg_i_1_n_0
);
den_C_reg_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000AAAA00080000"
)
port map (
I0 => \^den_reg_reg_0\,
I1 => \^state_reg[1]_0\,
I2 => bbusy_A,
I3 => \^overlap_b_reg_0\,
I4 => drdy_C,
I5 => \state_reg_n_0_[1]\,
O => den_C_reg_i_2_n_0
);
den_C_reg_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"03000A00C300CA00"
)
port map (
I0 => bbusy_A,
I1 => drdy_C,
I2 => \state_reg_n_0_[1]\,
I3 => den_A,
I4 => \^state_reg[1]_0\,
I5 => \^overlap_a_reg_0\,
O => den_C_reg_i_3_n_0
);
den_C_reg_reg: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_C_reg[6]_i_1_n_0\,
CLR => reset,
D => den_C_reg_i_1_n_0,
Q => den_C
);
den_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"D8D8D8C8"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => den_A,
I2 => \^den_reg_reg_0\,
I3 => bbusy_A,
I4 => \^state_reg[1]_0\,
O => den_reg_i_1_n_0
);
den_reg_reg: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_reg[6]_i_1_n_0\,
CLR => reset,
D => den_reg_i_1_n_0,
Q => den_reg_reg_n_0
);
\di_C_reg[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \daddr_C_reg[6]_i_7_n_0\,
I1 => s_axi_wdata(0),
I2 => \daddr_C_reg[6]_i_8_n_0\,
I3 => di_reg(0),
O => \di_C_reg[0]_i_1_n_0\
);
\di_C_reg[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \daddr_C_reg[6]_i_7_n_0\,
I1 => s_axi_wdata(10),
I2 => \daddr_C_reg[6]_i_8_n_0\,
I3 => di_reg(10),
O => \di_C_reg[10]_i_1_n_0\
);
\di_C_reg[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \daddr_C_reg[6]_i_7_n_0\,
I1 => s_axi_wdata(11),
I2 => \daddr_C_reg[6]_i_8_n_0\,
I3 => di_reg(11),
O => \di_C_reg[11]_i_1_n_0\
);
\di_C_reg[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \daddr_C_reg[6]_i_7_n_0\,
I1 => s_axi_wdata(12),
I2 => \daddr_C_reg[6]_i_8_n_0\,
I3 => di_reg(12),
O => \di_C_reg[12]_i_1_n_0\
);
\di_C_reg[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \daddr_C_reg[6]_i_7_n_0\,
I1 => s_axi_wdata(13),
I2 => \daddr_C_reg[6]_i_8_n_0\,
I3 => di_reg(13),
O => \di_C_reg[13]_i_1_n_0\
);
\di_C_reg[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \daddr_C_reg[6]_i_7_n_0\,
I1 => s_axi_wdata(14),
I2 => \daddr_C_reg[6]_i_8_n_0\,
I3 => di_reg(14),
O => \di_C_reg[14]_i_1_n_0\
);
\di_C_reg[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \daddr_C_reg[6]_i_7_n_0\,
I1 => s_axi_wdata(15),
I2 => \daddr_C_reg[6]_i_8_n_0\,
I3 => di_reg(15),
O => \di_C_reg[15]_i_1_n_0\
);
\di_C_reg[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \daddr_C_reg[6]_i_7_n_0\,
I1 => s_axi_wdata(1),
I2 => \daddr_C_reg[6]_i_8_n_0\,
I3 => di_reg(1),
O => \di_C_reg[1]_i_1_n_0\
);
\di_C_reg[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \daddr_C_reg[6]_i_7_n_0\,
I1 => s_axi_wdata(2),
I2 => \daddr_C_reg[6]_i_8_n_0\,
I3 => di_reg(2),
O => \di_C_reg[2]_i_1_n_0\
);
\di_C_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \daddr_C_reg[6]_i_7_n_0\,
I1 => s_axi_wdata(3),
I2 => \daddr_C_reg[6]_i_8_n_0\,
I3 => di_reg(3),
O => \di_C_reg[3]_i_1_n_0\
);
\di_C_reg[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \daddr_C_reg[6]_i_7_n_0\,
I1 => s_axi_wdata(4),
I2 => \daddr_C_reg[6]_i_8_n_0\,
I3 => di_reg(4),
O => \di_C_reg[4]_i_1_n_0\
);
\di_C_reg[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \daddr_C_reg[6]_i_7_n_0\,
I1 => s_axi_wdata(5),
I2 => \daddr_C_reg[6]_i_8_n_0\,
I3 => di_reg(5),
O => \di_C_reg[5]_i_1_n_0\
);
\di_C_reg[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \daddr_C_reg[6]_i_7_n_0\,
I1 => s_axi_wdata(6),
I2 => \daddr_C_reg[6]_i_8_n_0\,
I3 => di_reg(6),
O => \di_C_reg[6]_i_1_n_0\
);
\di_C_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \daddr_C_reg[6]_i_7_n_0\,
I1 => s_axi_wdata(7),
I2 => \daddr_C_reg[6]_i_8_n_0\,
I3 => di_reg(7),
O => \di_C_reg[7]_i_1_n_0\
);
\di_C_reg[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \daddr_C_reg[6]_i_7_n_0\,
I1 => s_axi_wdata(8),
I2 => \daddr_C_reg[6]_i_8_n_0\,
I3 => di_reg(8),
O => \di_C_reg[8]_i_1_n_0\
);
\di_C_reg[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \daddr_C_reg[6]_i_7_n_0\,
I1 => s_axi_wdata(9),
I2 => \daddr_C_reg[6]_i_8_n_0\,
I3 => di_reg(9),
O => \di_C_reg[9]_i_1_n_0\
);
\di_C_reg_reg[0]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_C_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_C_reg[0]_i_1_n_0\,
Q => \status_reg_reg[7]_0\(0)
);
\di_C_reg_reg[10]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_C_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_C_reg[10]_i_1_n_0\,
Q => \status_reg_reg[7]_0\(10)
);
\di_C_reg_reg[11]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_C_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_C_reg[11]_i_1_n_0\,
Q => \status_reg_reg[7]_0\(11)
);
\di_C_reg_reg[12]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_C_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_C_reg[12]_i_1_n_0\,
Q => \status_reg_reg[7]_0\(12)
);
\di_C_reg_reg[13]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_C_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_C_reg[13]_i_1_n_0\,
Q => \status_reg_reg[7]_0\(13)
);
\di_C_reg_reg[14]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_C_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_C_reg[14]_i_1_n_0\,
Q => \status_reg_reg[7]_0\(14)
);
\di_C_reg_reg[15]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_C_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_C_reg[15]_i_1_n_0\,
Q => \status_reg_reg[7]_0\(15)
);
\di_C_reg_reg[1]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_C_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_C_reg[1]_i_1_n_0\,
Q => \status_reg_reg[7]_0\(1)
);
\di_C_reg_reg[2]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_C_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_C_reg[2]_i_1_n_0\,
Q => \status_reg_reg[7]_0\(2)
);
\di_C_reg_reg[3]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_C_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_C_reg[3]_i_1_n_0\,
Q => \status_reg_reg[7]_0\(3)
);
\di_C_reg_reg[4]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_C_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_C_reg[4]_i_1_n_0\,
Q => \status_reg_reg[7]_0\(4)
);
\di_C_reg_reg[5]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_C_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_C_reg[5]_i_1_n_0\,
Q => \status_reg_reg[7]_0\(5)
);
\di_C_reg_reg[6]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_C_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_C_reg[6]_i_1_n_0\,
Q => \status_reg_reg[7]_0\(6)
);
\di_C_reg_reg[7]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_C_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_C_reg[7]_i_1_n_0\,
Q => \status_reg_reg[7]_0\(7)
);
\di_C_reg_reg[8]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_C_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_C_reg[8]_i_1_n_0\,
Q => \status_reg_reg[7]_0\(8)
);
\di_C_reg_reg[9]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_C_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_C_reg[9]_i_1_n_0\,
Q => \status_reg_reg[7]_0\(9)
);
\di_reg[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(0),
I1 => \state_reg_n_0_[1]\,
O => \di_reg[0]_i_1_n_0\
);
\di_reg[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(10),
I1 => \state_reg_n_0_[1]\,
O => \di_reg[10]_i_1_n_0\
);
\di_reg[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(11),
I1 => \state_reg_n_0_[1]\,
O => \di_reg[11]_i_1_n_0\
);
\di_reg[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(12),
I1 => \state_reg_n_0_[1]\,
O => \di_reg[12]_i_1_n_0\
);
\di_reg[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(13),
I1 => \state_reg_n_0_[1]\,
O => \di_reg[13]_i_1_n_0\
);
\di_reg[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(14),
I1 => \state_reg_n_0_[1]\,
O => \di_reg[14]_i_1_n_0\
);
\di_reg[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(15),
I1 => \state_reg_n_0_[1]\,
O => \di_reg[15]_i_1_n_0\
);
\di_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(1),
I1 => \state_reg_n_0_[1]\,
O => \di_reg[1]_i_1_n_0\
);
\di_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(2),
I1 => \state_reg_n_0_[1]\,
O => \di_reg[2]_i_1_n_0\
);
\di_reg[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(3),
I1 => \state_reg_n_0_[1]\,
O => \di_reg[3]_i_1_n_0\
);
\di_reg[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(4),
I1 => \state_reg_n_0_[1]\,
O => \di_reg[4]_i_1_n_0\
);
\di_reg[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(5),
I1 => \state_reg_n_0_[1]\,
O => \di_reg[5]_i_1_n_0\
);
\di_reg[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(6),
I1 => \state_reg_n_0_[1]\,
O => \di_reg[6]_i_1_n_0\
);
\di_reg[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(7),
I1 => \state_reg_n_0_[1]\,
O => \di_reg[7]_i_1_n_0\
);
\di_reg[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(8),
I1 => \state_reg_n_0_[1]\,
O => \di_reg[8]_i_1_n_0\
);
\di_reg[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(9),
I1 => \state_reg_n_0_[1]\,
O => \di_reg[9]_i_1_n_0\
);
\di_reg_reg[0]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_reg[0]_i_1_n_0\,
Q => di_reg(0)
);
\di_reg_reg[10]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_reg[10]_i_1_n_0\,
Q => di_reg(10)
);
\di_reg_reg[11]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_reg[11]_i_1_n_0\,
Q => di_reg(11)
);
\di_reg_reg[12]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_reg[12]_i_1_n_0\,
Q => di_reg(12)
);
\di_reg_reg[13]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_reg[13]_i_1_n_0\,
Q => di_reg(13)
);
\di_reg_reg[14]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_reg[14]_i_1_n_0\,
Q => di_reg(14)
);
\di_reg_reg[15]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_reg[15]_i_1_n_0\,
Q => di_reg(15)
);
\di_reg_reg[1]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_reg[1]_i_1_n_0\,
Q => di_reg(1)
);
\di_reg_reg[2]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_reg[2]_i_1_n_0\,
Q => di_reg(2)
);
\di_reg_reg[3]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_reg[3]_i_1_n_0\,
Q => di_reg(3)
);
\di_reg_reg[4]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_reg[4]_i_1_n_0\,
Q => di_reg(4)
);
\di_reg_reg[5]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_reg[5]_i_1_n_0\,
Q => di_reg(5)
);
\di_reg_reg[6]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_reg[6]_i_1_n_0\,
Q => di_reg(6)
);
\di_reg_reg[7]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_reg[7]_i_1_n_0\,
Q => di_reg(7)
);
\di_reg_reg[8]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_reg[8]_i_1_n_0\,
Q => di_reg(8)
);
\di_reg_reg[9]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_reg[6]_i_1_n_0\,
CLR => reset,
D => \di_reg[9]_i_1_n_0\,
Q => di_reg(9)
);
\do_A_reg[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^state_reg[1]_0\,
I1 => DO(10),
O => \do_A_reg[10]_i_1_n_0\
);
\do_A_reg[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^state_reg[1]_0\,
I1 => DO(11),
O => \do_A_reg[11]_i_1_n_0\
);
\do_A_reg[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^state_reg[1]_0\,
I1 => DO(12),
O => \do_A_reg[12]_i_1_n_0\
);
\do_A_reg[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^state_reg[1]_0\,
I1 => DO(13),
O => \do_A_reg[13]_i_1_n_0\
);
\do_A_reg[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^state_reg[1]_0\,
I1 => DO(14),
O => \do_A_reg[14]_i_1_n_0\
);
\do_A_reg[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"45"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => drdy_C,
I2 => \^state_reg[1]_0\,
O => \do_A_reg[15]_i_1_n_0\
);
\do_A_reg[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^state_reg[1]_0\,
I1 => DO(15),
O => \do_A_reg[15]_i_2_n_0\
);
\do_A_reg[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^state_reg[1]_0\,
I1 => DO(4),
O => \do_A_reg[4]_i_1_n_0\
);
\do_A_reg[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^state_reg[1]_0\,
I1 => DO(5),
O => \do_A_reg[5]_i_1_n_0\
);
\do_A_reg[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^state_reg[1]_0\,
I1 => DO(6),
O => \do_A_reg[6]_i_1_n_0\
);
\do_A_reg[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^state_reg[1]_0\,
I1 => DO(7),
O => \do_A_reg[7]_i_1_n_0\
);
\do_A_reg[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^state_reg[1]_0\,
I1 => DO(8),
O => \do_A_reg[8]_i_1_n_0\
);
\do_A_reg[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^state_reg[1]_0\,
I1 => DO(9),
O => \do_A_reg[9]_i_1_n_0\
);
\do_A_reg_reg[10]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_A_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_A_reg[10]_i_1_n_0\,
Q => Q(6)
);
\do_A_reg_reg[11]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_A_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_A_reg[11]_i_1_n_0\,
Q => Q(7)
);
\do_A_reg_reg[12]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_A_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_A_reg[12]_i_1_n_0\,
Q => Q(8)
);
\do_A_reg_reg[13]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_A_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_A_reg[13]_i_1_n_0\,
Q => Q(9)
);
\do_A_reg_reg[14]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_A_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_A_reg[14]_i_1_n_0\,
Q => Q(10)
);
\do_A_reg_reg[15]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_A_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_A_reg[15]_i_2_n_0\,
Q => Q(11)
);
\do_A_reg_reg[4]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_A_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_A_reg[4]_i_1_n_0\,
Q => Q(0)
);
\do_A_reg_reg[5]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_A_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_A_reg[5]_i_1_n_0\,
Q => Q(1)
);
\do_A_reg_reg[6]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_A_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_A_reg[6]_i_1_n_0\,
Q => Q(2)
);
\do_A_reg_reg[7]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_A_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_A_reg[7]_i_1_n_0\,
Q => Q(3)
);
\do_A_reg_reg[8]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_A_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_A_reg[8]_i_1_n_0\,
Q => Q(4)
);
\do_A_reg_reg[9]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_A_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_A_reg[9]_i_1_n_0\,
Q => Q(5)
);
\do_B_reg[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => DO(0),
O => \do_B_reg[0]_i_1_n_0\
);
\do_B_reg[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => DO(10),
O => \do_B_reg[10]_i_1_n_0\
);
\do_B_reg[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => DO(11),
O => \do_B_reg[11]_i_1_n_0\
);
\do_B_reg[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => DO(12),
O => \do_B_reg[12]_i_1_n_0\
);
\do_B_reg[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => DO(13),
O => \do_B_reg[13]_i_1_n_0\
);
\do_B_reg[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => DO(14),
O => \do_B_reg[14]_i_1_n_0\
);
\do_B_reg[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"83"
)
port map (
I0 => drdy_C,
I1 => \^state_reg[1]_0\,
I2 => \state_reg_n_0_[1]\,
O => \do_B_reg[15]_i_1_n_0\
);
\do_B_reg[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => DO(15),
O => \do_B_reg[15]_i_2_n_0\
);
\do_B_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => DO(1),
O => \do_B_reg[1]_i_1_n_0\
);
\do_B_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => DO(2),
O => \do_B_reg[2]_i_1_n_0\
);
\do_B_reg[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => DO(3),
O => \do_B_reg[3]_i_1_n_0\
);
\do_B_reg[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => DO(4),
O => \do_B_reg[4]_i_1_n_0\
);
\do_B_reg[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => DO(5),
O => \do_B_reg[5]_i_1_n_0\
);
\do_B_reg[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => DO(6),
O => \do_B_reg[6]_i_1_n_0\
);
\do_B_reg[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => DO(7),
O => \do_B_reg[7]_i_1_n_0\
);
\do_B_reg[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => DO(8),
O => \do_B_reg[8]_i_1_n_0\
);
\do_B_reg[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => DO(9),
O => \do_B_reg[9]_i_1_n_0\
);
\do_B_reg_reg[0]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_B_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_B_reg[0]_i_1_n_0\,
Q => \do_reg_reg[15]\(0)
);
\do_B_reg_reg[10]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_B_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_B_reg[10]_i_1_n_0\,
Q => \do_reg_reg[15]\(10)
);
\do_B_reg_reg[11]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_B_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_B_reg[11]_i_1_n_0\,
Q => \do_reg_reg[15]\(11)
);
\do_B_reg_reg[12]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_B_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_B_reg[12]_i_1_n_0\,
Q => \do_reg_reg[15]\(12)
);
\do_B_reg_reg[13]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_B_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_B_reg[13]_i_1_n_0\,
Q => \do_reg_reg[15]\(13)
);
\do_B_reg_reg[14]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_B_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_B_reg[14]_i_1_n_0\,
Q => \do_reg_reg[15]\(14)
);
\do_B_reg_reg[15]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_B_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_B_reg[15]_i_2_n_0\,
Q => \do_reg_reg[15]\(15)
);
\do_B_reg_reg[1]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_B_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_B_reg[1]_i_1_n_0\,
Q => \do_reg_reg[15]\(1)
);
\do_B_reg_reg[2]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_B_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_B_reg[2]_i_1_n_0\,
Q => \do_reg_reg[15]\(2)
);
\do_B_reg_reg[3]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_B_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_B_reg[3]_i_1_n_0\,
Q => \do_reg_reg[15]\(3)
);
\do_B_reg_reg[4]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_B_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_B_reg[4]_i_1_n_0\,
Q => \do_reg_reg[15]\(4)
);
\do_B_reg_reg[5]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_B_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_B_reg[5]_i_1_n_0\,
Q => \do_reg_reg[15]\(5)
);
\do_B_reg_reg[6]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_B_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_B_reg[6]_i_1_n_0\,
Q => \do_reg_reg[15]\(6)
);
\do_B_reg_reg[7]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_B_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_B_reg[7]_i_1_n_0\,
Q => \do_reg_reg[15]\(7)
);
\do_B_reg_reg[8]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_B_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_B_reg[8]_i_1_n_0\,
Q => \do_reg_reg[15]\(8)
);
\do_B_reg_reg[9]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \do_B_reg[15]_i_1_n_0\,
CLR => reset,
D => \do_B_reg[9]_i_1_n_0\,
Q => \do_reg_reg[15]\(9)
);
drdy_A_reg_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"3808"
)
port map (
I0 => drdy_C,
I1 => \^state_reg[1]_0\,
I2 => \state_reg_n_0_[1]\,
I3 => \^drdy_i\,
O => drdy_A_reg_i_1_n_0
);
drdy_A_reg_reg: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => '1',
CLR => reset,
D => drdy_A_reg_i_1_n_0,
Q => \^drdy_i\
);
drdy_B_reg_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"B080"
)
port map (
I0 => drdy_C,
I1 => \^state_reg[1]_0\,
I2 => \state_reg_n_0_[1]\,
I3 => drdy_B,
O => drdy_B_reg_i_1_n_0
);
drdy_B_reg_reg: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => '1',
CLR => reset,
D => drdy_B_reg_i_1_n_0,
Q => drdy_B
);
drdy_rd_ack_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00FF808000008080"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]_0\,
I1 => Bus_RNW_reg,
I2 => drdy_B,
I3 => drdy_rd_ack_i_d2,
I4 => den_C_reg_reg_0,
I5 => drdy_rd_ack_i_d1,
O => drdy_rd_ack_i_reg
);
drdy_wr_ack_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00FF202000002020"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]_0\,
I1 => Bus_RNW_reg,
I2 => drdy_B,
I3 => drdy_wr_ack_i_d2,
I4 => den_C_reg_reg_0,
I5 => drdy_wr_ack_i_d1,
O => drdy_wr_ack_i_reg
);
dwe_C_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"4444444F"
)
port map (
I0 => \daddr_C_reg[6]_i_8_n_0\,
I1 => dwe_reg_reg_n_0,
I2 => \daddr_C_reg[6]_i_7_n_0\,
I3 => dwe_d1,
I4 => \GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]\,
O => dwe_C_reg_i_1_n_0
);
dwe_C_reg_reg: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_C_reg[6]_i_1_n_0\,
CLR => reset,
D => dwe_C_reg_i_1_n_0,
Q => dwe_C
);
dwe_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000400040004"
)
port map (
I0 => den_C_reg_reg_0,
I1 => \GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]_0\,
I2 => Bus_RNW_reg,
I3 => dwe_d1,
I4 => \^state_reg[1]_0\,
I5 => \state_reg_n_0_[1]\,
O => dwe_reg_i_1_n_0
);
dwe_reg_reg: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \daddr_reg[6]_i_1_n_0\,
CLR => reset,
D => dwe_reg_i_1_n_0,
Q => dwe_reg_reg_n_0
);
overlap_A_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"E0E0E0FFE0E0E000"
)
port map (
I0 => bbusy_A,
I1 => \state_reg_n_0_[1]\,
I2 => den_A,
I3 => overlap_A_i_2_n_0,
I4 => overlap_A_i_3_n_0,
I5 => \^overlap_a_reg_0\,
O => overlap_A_i_1_n_0
);
overlap_A_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000000FE"
)
port map (
I0 => den_A,
I1 => \^overlap_a_reg_0\,
I2 => \^den_reg_reg_0\,
I3 => den_C_reg_reg_0,
I4 => \daddr_C_reg[6]_i_6_n_0\,
I5 => \^overlap_b_reg_0\,
O => overlap_A_i_2_n_0
);
overlap_A_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"EA000000"
)
port map (
I0 => den_A,
I1 => drdy_C,
I2 => \^overlap_a_reg_0\,
I3 => \state_reg_n_0_[1]\,
I4 => \^state_reg[1]_0\,
O => overlap_A_i_3_n_0
);
overlap_A_reg: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => '1',
CLR => reset,
D => overlap_A_i_1_n_0,
Q => \^overlap_a_reg_0\
);
overlap_B_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCC888AAAAAAAAA"
)
port map (
I0 => den_o_reg_0,
I1 => \^overlap_b_reg_0\,
I2 => den_o_reg_1,
I3 => \^overlap_a_reg_0\,
I4 => \state[0]_i_4__0_n_0\,
I5 => overlap_B_i_4_n_0,
O => overlap_B_i_1_n_0
);
overlap_B_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF000FFF7F"
)
port map (
I0 => \^overlap_b_reg_0\,
I1 => drdy_C,
I2 => \^state_reg[1]_0\,
I3 => bbusy_A,
I4 => \^den_reg_reg_0\,
I5 => \state_reg_n_0_[1]\,
O => overlap_B_i_4_n_0
);
overlap_B_reg: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => '1',
CLR => reset,
D => overlap_B_i_1_n_0,
Q => \^overlap_b_reg_0\
);
\state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAABBBA888A888A"
)
port map (
I0 => \state[0]_i_2__0_n_0\,
I1 => \state[1]_i_3__0_n_0\,
I2 => \state[0]_i_3__0_n_0\,
I3 => \state[0]_i_4__0_n_0\,
I4 => drdy_C,
I5 => \^state_reg[1]_0\,
O => \state[0]_i_1_n_0\
);
\state[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F333FF3FF333FB3B"
)
port map (
I0 => \^den_reg_reg_0\,
I1 => \^state_reg[1]_0\,
I2 => \state_reg_n_0_[1]\,
I3 => den_o_reg,
I4 => bbusy_A,
I5 => \^overlap_b_reg_0\,
O => \state[0]_i_2__0_n_0\
);
\state[0]_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^overlap_a_reg_0\,
I1 => \^overlap_b_reg_0\,
O => \state[0]_i_3__0_n_0\
);
\state[0]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => den_C_reg_reg_0,
I1 => \state_reg_n_0_[1]\,
I2 => bbusy_A,
I3 => \^state_reg[1]_0\,
O => \state[0]_i_4__0_n_0\
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABABABAAA8A8A8"
)
port map (
I0 => \state[1]_i_2__0_n_0\,
I1 => \state[1]_i_3__0_n_0\,
I2 => \state[1]_i_4_n_0\,
I3 => drdy_C,
I4 => \^state_reg[1]_0\,
I5 => \state_reg_n_0_[1]\,
O => \state[1]_i_1_n_0\
);
\state[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFAAABAA"
)
port map (
I0 => \^overlap_b_reg_0\,
I1 => den_A,
I2 => \^overlap_a_reg_0\,
I3 => \^den_reg_reg_0\,
I4 => \^state_reg[1]_0\,
I5 => \state[1]_i_5_n_0\,
O => \state[1]_i_2__0_n_0\
);
\state[1]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000110100001100"
)
port map (
I0 => den_C_reg_reg_0,
I1 => \state_reg_n_0_[1]\,
I2 => bbusy_A,
I3 => den_A,
I4 => \^state_reg[1]_0\,
I5 => \^den_reg_reg_0\,
O => \state[1]_i_3__0_n_0\
);
\state[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000000E"
)
port map (
I0 => \^overlap_b_reg_0\,
I1 => \^overlap_a_reg_0\,
I2 => \^state_reg[1]_0\,
I3 => bbusy_A,
I4 => \state_reg_n_0_[1]\,
I5 => den_C_reg_reg_0,
O => \state[1]_i_4_n_0\
);
\state[1]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => bbusy_A,
O => \state[1]_i_5_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => '1',
CLR => reset,
D => \state[0]_i_1_n_0\,
Q => \^state_reg[1]_0\
);
\state_reg[1]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => '1',
CLR => reset,
D => \state[1]_i_1_n_0\,
Q => \state_reg_n_0_[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xadc_wiz_0_0_system_xadc_wiz_0_0_address_decoder is
port (
dwe_d1_reg : out STD_LOGIC;
hard_macro_rst_reg_reg : out STD_LOGIC;
dwe_d1_reg_0 : out STD_LOGIC;
dwe_C_reg_reg : out STD_LOGIC;
bus2ip_wrce : out STD_LOGIC_VECTOR ( 0 to 0 );
rst_ip2bus_rdack0 : out STD_LOGIC;
bus2ip_rdce : out STD_LOGIC_VECTOR ( 2 downto 0 );
D : out STD_LOGIC_VECTOR ( 18 downto 0 );
status_reg_rdack0 : out STD_LOGIC;
Intr2Bus_RdAck0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[16].GEN_REG_STATUS.ip_irpt_status_reg_reg[16]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
local_reg_wrack0 : out STD_LOGIC;
local_reg_rdack0 : out STD_LOGIC;
local_rdce_or_reduce : out STD_LOGIC;
ip2bus_wrack_int1 : out STD_LOGIC;
\INTR_CTRLR_GEN_I.ip2bus_wrack_reg\ : out STD_LOGIC;
reset_trig0 : out STD_LOGIC;
sw_rst_cond : out STD_LOGIC;
p_3_out : out STD_LOGIC;
p_5_out : out STD_LOGIC;
dummy_bus2ip_rdce_intr : out STD_LOGIC;
dummy_local_reg_wrack0 : out STD_LOGIC;
dummy_local_reg_rdack0 : out STD_LOGIC;
dummy_local_reg_rdack_d10 : out STD_LOGIC;
hard_macro_rst_reg_reg_0 : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
local_reg_wrack_d1_reg : out STD_LOGIC;
\temp_rd_wait_cycle_reg_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_d1_reg\ : out STD_LOGIC;
dummy_local_reg_wrack_d1_reg : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
ip2bus_wrack : in STD_LOGIC;
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[6]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn : in STD_LOGIC;
ip2bus_rdack : in STD_LOGIC;
jtaglocked_i : in STD_LOGIC;
rst_ip2bus_rdack_d1 : in STD_LOGIC;
\ip_irpt_enable_reg_reg[16]\ : in STD_LOGIC_VECTOR ( 16 downto 0 );
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ : in STD_LOGIC;
\status_reg_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
\alarm_reg_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\do_reg_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
p_1_in44_in : in STD_LOGIC;
p_1_in41_in : in STD_LOGIC;
p_1_in38_in : in STD_LOGIC;
p_1_in35_in : in STD_LOGIC;
p_1_in32_in : in STD_LOGIC;
p_1_in29_in : in STD_LOGIC;
p_1_in26_in : in STD_LOGIC;
p_1_in23_in : in STD_LOGIC;
p_1_in20_in : in STD_LOGIC;
p_1_in17_in : in STD_LOGIC;
status_reg_rdack_d1 : in STD_LOGIC;
p_1_in14_in : in STD_LOGIC;
p_1_in11_in : in STD_LOGIC;
p_1_in8_in : in STD_LOGIC;
p_1_in5_in : in STD_LOGIC;
p_1_in2_in : in STD_LOGIC;
p_1_in : in STD_LOGIC;
jtagmodified_i : in STD_LOGIC;
jtagmodified_d1 : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
ipif_glbl_irpt_enable_reg : in STD_LOGIC;
irpt_rdack_d1 : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
local_reg_wrack_d1 : in STD_LOGIC;
local_reg_rdack_d1 : in STD_LOGIC;
intr_ip2bus_wrack : in STD_LOGIC;
wrack : in STD_LOGIC;
dummy_local_reg_wrack : in STD_LOGIC;
dummy_intr_reg_wrack : in STD_LOGIC;
local_reg_wrack_reg : in STD_LOGIC;
\s_axi_wdata_1__s_port_]\ : in STD_LOGIC;
sw_rst_cond_d1 : in STD_LOGIC;
dummy_intr_reg_wrack_d1 : in STD_LOGIC;
dummy_intr_reg_rdack_d1 : in STD_LOGIC;
dummy_local_reg_wrack_d1 : in STD_LOGIC;
dummy_local_reg_rdack_d1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 1 downto 0 );
hard_macro_rst_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xadc_wiz_0_0_system_xadc_wiz_0_0_address_decoder : entity is "system_xadc_wiz_0_0_address_decoder";
end system_xadc_wiz_0_0_system_xadc_wiz_0_0_address_decoder;
architecture STRUCTURE of system_xadc_wiz_0_0_system_xadc_wiz_0_0_address_decoder is
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[22].ce_out_i[22]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_3_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_4_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_3_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_4_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_5_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_6_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_7_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_8_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_d1_i_2_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_d1_i_3_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_d1_i_4_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN_I.ip2bus_data_int[0]_i_2_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_2_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_3_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_4_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN_I.ip2bus_data_int[21]_i_2_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN_I.ip2bus_data_int[22]_i_2_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_2_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_3_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_4_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN_I.ip2bus_data_int[24]_i_2_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN_I.ip2bus_data_int[25]_i_2_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN_I.ip2bus_data_int[26]_i_2_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN_I.ip2bus_data_int[27]_i_2_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN_I.ip2bus_data_int[28]_i_2_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN_I.ip2bus_data_int[29]_i_2_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN_I.ip2bus_data_int[30]_i_2_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN_I.ip2bus_data_int[31]_i_2_n_0\ : STD_LOGIC;
signal \^intr_ctrlr_gen_i.ip2bus_wrack_reg\ : STD_LOGIC;
signal Intr2Bus_WrAck_i_2_n_0 : STD_LOGIC;
signal cs_ce_clr : STD_LOGIC;
signal \^dwe_d1_reg\ : STD_LOGIC;
signal \^hard_macro_rst_reg_reg\ : STD_LOGIC;
signal p_10_in : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_11_in : STD_LOGIC;
signal p_11_out : STD_LOGIC;
signal p_12_in : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_13_in : STD_LOGIC;
signal p_13_out : STD_LOGIC;
signal p_14_in : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal p_15_out : STD_LOGIC;
signal p_16_in : STD_LOGIC;
signal p_17_in : STD_LOGIC;
signal p_18_in : STD_LOGIC;
signal p_19_in : STD_LOGIC;
signal p_20_in : STD_LOGIC;
signal p_21_in : STD_LOGIC;
signal p_22_in : STD_LOGIC;
signal p_23_in : STD_LOGIC;
signal p_24_in : STD_LOGIC;
signal p_25_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_5_in : STD_LOGIC;
signal p_5_out_0 : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_in : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_in : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_9_in : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal pselect_hit_i_0 : STD_LOGIC;
signal \s_axi_wdata_1__s_net_1\ : STD_LOGIC;
signal start : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_3\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_4\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_3\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_2\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_4\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_5\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_7\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_8\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN_I.dummy_intr_reg_rdack_d1_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN_I.dummy_intr_reg_rdack_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_d1_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN_I.ip2bus_data_int[0]_i_2\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_4\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_3\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_4\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN_I.ip2bus_error_i_2\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of Intr2Bus_WrAck_i_2 : label is "soft_lutpair20";
attribute SOFT_HLUTNM of drdy_rd_ack_i_d1_i_1 : label is "soft_lutpair25";
attribute SOFT_HLUTNM of drdy_wr_ack_i_d1_i_1 : label is "soft_lutpair25";
attribute SOFT_HLUTNM of dummy_local_reg_rdack_d1_i_1 : label is "soft_lutpair11";
attribute SOFT_HLUTNM of dummy_local_reg_rdack_i_1 : label is "soft_lutpair12";
attribute SOFT_HLUTNM of dummy_local_reg_wrack_d1_i_1 : label is "soft_lutpair12";
attribute SOFT_HLUTNM of dummy_local_reg_wrack_i_1 : label is "soft_lutpair11";
attribute SOFT_HLUTNM of dwe_C_reg_i_2 : label is "soft_lutpair18";
attribute SOFT_HLUTNM of dwe_d1_i_1 : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \ip_irpt_enable_reg[16]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of local_reg_rdack_d1_i_1 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of local_reg_rdack_i_1 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of local_reg_wrack_d1_i_1 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of reset_trig_i_1 : label is "soft_lutpair16";
attribute SOFT_HLUTNM of rst_ip2bus_rdack_d1_i_1 : label is "soft_lutpair17";
attribute SOFT_HLUTNM of rst_ip2bus_rdack_i_1 : label is "soft_lutpair17";
attribute SOFT_HLUTNM of status_reg_rdack_d1_i_1 : label is "soft_lutpair24";
attribute SOFT_HLUTNM of status_reg_rdack_i_1 : label is "soft_lutpair15";
attribute SOFT_HLUTNM of sw_rst_cond_d1_i_1 : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \temp_rd_wait_cycle_reg[15]_i_1\ : label is "soft_lutpair10";
begin
\INTR_CTRLR_GEN_I.ip2bus_wrack_reg\ <= \^intr_ctrlr_gen_i.ip2bus_wrack_reg\;
dwe_d1_reg <= \^dwe_d1_reg\;
hard_macro_rst_reg_reg <= \^hard_macro_rst_reg_reg\;
\s_axi_wdata_1__s_net_1\ <= \s_axi_wdata_1__s_port_]\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF7000000F0"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
I3 => Q(0),
I4 => Q(1),
I5 => \^hard_macro_rst_reg_reg\,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => \^hard_macro_rst_reg_reg\,
R => '0'
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000020"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_2_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_2_n_0\,
I2 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_3_n_0\,
I3 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_4_n_0\,
I4 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_5_n_0\,
O => p_7_out
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start,
D => p_7_out,
Q => p_25_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000440347"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_arvalid,
I2 => s_axi_awaddr(2),
I3 => s_axi_araddr(0),
I4 => s_axi_awaddr(0),
I5 => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\,
O => p_13_out
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start,
D => p_13_out,
Q => p_15_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000047034400"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_arvalid,
I2 => s_axi_awaddr(2),
I3 => s_axi_araddr(0),
I4 => s_axi_awaddr(0),
I5 => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\,
O => p_12_out
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start,
D => p_12_out,
Q => p_14_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000047034400"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_arvalid,
I2 => s_axi_awaddr(0),
I3 => s_axi_araddr(2),
I4 => s_axi_awaddr(2),
I5 => \GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_2_n_0\,
O => p_11_out
);
\GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start,
D => p_11_out,
Q => p_13_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000B8308800"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_arvalid,
I2 => s_axi_awaddr(2),
I3 => s_axi_araddr(0),
I4 => s_axi_awaddr(0),
I5 => \GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_2_n_0\,
O => p_10_out
);
\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFFFFFFFFFF"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_4_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_2_n_0\,
I2 => \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_3_n_0\,
I3 => \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_4_n_0\,
I4 => start,
I5 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_5_n_0\,
O => \GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start,
D => p_10_out,
Q => p_12_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000047034400"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_arvalid,
I2 => s_axi_awaddr(0),
I3 => s_axi_araddr(2),
I4 => s_axi_awaddr(2),
I5 => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\,
O => p_9_out
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start,
D => p_9_out,
Q => p_11_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000B8308800"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_arvalid,
I2 => s_axi_awaddr(2),
I3 => s_axi_araddr(0),
I4 => s_axi_awaddr(0),
I5 => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\,
O => p_8_out
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFFFFFFFFFFFFFF"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_4_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_3_n_0\,
I2 => \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_4_n_0\,
I3 => start,
I4 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_5_n_0\,
I5 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_2_n_0\,
O => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start,
D => p_8_out,
Q => p_10_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000440347"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_arvalid,
I2 => s_axi_awaddr(2),
I3 => s_axi_araddr(0),
I4 => s_axi_awaddr(0),
I5 => \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_2_n_0\,
O => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start,
D => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\,
Q => p_9_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000047034400"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_arvalid,
I2 => s_axi_awaddr(2),
I3 => s_axi_araddr(0),
I4 => s_axi_awaddr(0),
I5 => \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_2_n_0\,
O => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start,
D => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\,
Q => p_8_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000440347"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_arvalid,
I2 => s_axi_awaddr(2),
I3 => s_axi_araddr(0),
I4 => s_axi_awaddr(0),
I5 => \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_2_n_0\,
O => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start,
D => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\,
Q => p_7_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000047034400"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_arvalid,
I2 => s_axi_awaddr(2),
I3 => s_axi_araddr(0),
I4 => s_axi_awaddr(0),
I5 => \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_2_n_0\,
O => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start,
D => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\,
Q => p_6_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00040000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_2_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_3_n_0\,
I2 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_4_n_0\,
I3 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_5_n_0\,
I4 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\,
O => p_6_out
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start,
D => p_6_out,
Q => p_24_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000047034400"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_arvalid,
I2 => s_axi_awaddr(0),
I3 => s_axi_araddr(2),
I4 => s_axi_awaddr(2),
I5 => \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_2_n_0\,
O => \GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[20].ce_out_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start,
D => \GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1_n_0\,
Q => p_5_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000B8308800"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_arvalid,
I2 => s_axi_awaddr(2),
I3 => s_axi_araddr(0),
I4 => s_axi_awaddr(0),
I5 => \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_2_n_0\,
O => \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFDFFFFFFFFFFFF"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_4_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_2_n_0\,
I2 => \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_3_n_0\,
I3 => \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_4_n_0\,
I4 => start,
I5 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_5_n_0\,
O => \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[21].ce_out_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start,
D => \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1_n_0\,
Q => p_4_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[22].ce_out_i[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000047034400"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_arvalid,
I2 => s_axi_awaddr(0),
I3 => s_axi_araddr(2),
I4 => s_axi_awaddr(2),
I5 => \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_2_n_0\,
O => \GEN_BKEND_CE_REGISTERS[22].ce_out_i[22]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[22].ce_out_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start,
D => \GEN_BKEND_CE_REGISTERS[22].ce_out_i[22]_i_1_n_0\,
Q => p_3_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000B8308800"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_arvalid,
I2 => s_axi_awaddr(2),
I3 => s_axi_araddr(0),
I4 => s_axi_awaddr(0),
I5 => \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_2_n_0\,
O => p_15_out
);
\GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FDFFFFFFFFFFFFFF"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_4_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_3_n_0\,
I2 => \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_4_n_0\,
I3 => start,
I4 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_5_n_0\,
I5 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_2_n_0\,
O => \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(7),
I1 => s_axi_arvalid,
I2 => s_axi_awaddr(7),
O => \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_3_n_0\
);
\GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => s_axi_awaddr(5),
I1 => s_axi_araddr(5),
I2 => s_axi_awaddr(6),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(6),
O => \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_4_n_0\
);
\GEN_BKEND_CE_REGISTERS[23].ce_out_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start,
D => p_15_out,
Q => p_2_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => ip2bus_wrack,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[6]\(0),
I2 => s_axi_aresetn,
I3 => ip2bus_rdack,
O => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
I3 => Q(0),
I4 => Q(1),
O => start
);
\GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"A808"
)
port map (
I0 => start,
I1 => s_axi_awaddr(7),
I2 => s_axi_arvalid,
I3 => s_axi_araddr(7),
O => pselect_hit_i_0
);
\GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start,
D => pselect_hit_i_0,
Q => \^dwe_d1_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000080"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_2_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_2_n_0\,
I2 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_3_n_0\,
I3 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_4_n_0\,
I4 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_5_n_0\,
O => p_5_out_0
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_awaddr(0),
I1 => s_axi_araddr(0),
I2 => s_axi_awaddr(2),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(2),
O => \GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start,
D => p_5_out_0,
Q => p_23_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000080"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_2_n_0\,
I2 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_3_n_0\,
I3 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_4_n_0\,
I4 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_5_n_0\,
O => p_4_out
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_awaddr(0),
I1 => s_axi_araddr(0),
I2 => s_axi_awaddr(2),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(2),
O => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start,
D => p_4_out,
Q => p_22_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00040000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_2_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_3_n_0\,
I2 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_4_n_0\,
I3 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_5_n_0\,
I4 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_2_n_0\,
O => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start,
D => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\,
Q => p_21_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00040000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_2_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_3_n_0\,
I2 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_4_n_0\,
I3 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_5_n_0\,
I4 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_6_n_0\,
O => \GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1_n_0\,
Q => p_20_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00080000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_2_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_3_n_0\,
I2 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_4_n_0\,
I3 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_5_n_0\,
I4 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_2_n_0\,
O => \GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_awaddr(2),
I1 => s_axi_araddr(2),
I2 => s_axi_awaddr(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(0),
O => \GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start,
D => \GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1_n_0\,
Q => p_19_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00080000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_2_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_3_n_0\,
I2 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_4_n_0\,
I3 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_5_n_0\,
I4 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_6_n_0\,
O => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_arvalid,
I2 => s_axi_awaddr(1),
O => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000020202"
)
port map (
I0 => start,
I1 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_7_n_0\,
I2 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_8_n_0\,
I3 => s_axi_araddr(7),
I4 => s_axi_arvalid,
I5 => s_axi_awaddr(7),
O => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_3_n_0\
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(3),
I1 => s_axi_arvalid,
I2 => s_axi_awaddr(3),
O => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_4_n_0\
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(4),
I1 => s_axi_arvalid,
I2 => s_axi_awaddr(4),
O => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_5_n_0\
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCA000A0"
)
port map (
I0 => s_axi_awaddr(0),
I1 => s_axi_araddr(0),
I2 => s_axi_awaddr(2),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(2),
O => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_6_n_0\
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(5),
I1 => s_axi_arvalid,
I2 => s_axi_awaddr(5),
O => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_7_n_0\
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(6),
I1 => s_axi_arvalid,
I2 => s_axi_awaddr(6),
O => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_8_n_0\
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start,
D => \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1_n_0\,
Q => p_18_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000440347"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_arvalid,
I2 => s_axi_awaddr(2),
I3 => s_axi_araddr(0),
I4 => s_axi_awaddr(0),
I5 => \GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_2_n_0\,
O => \GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start,
D => \GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1_n_0\,
Q => p_17_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000047034400"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_arvalid,
I2 => s_axi_awaddr(2),
I3 => s_axi_araddr(0),
I4 => s_axi_awaddr(0),
I5 => \GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_2_n_0\,
O => p_14_out
);
\GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start,
D => p_14_out,
Q => p_16_in,
R => cs_ce_clr
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF1FF"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_wstrb(0),
I2 => \^hard_macro_rst_reg_reg\,
I3 => p_9_in,
I4 => irpt_wrack_d1,
O => \GEN_IP_IRPT_STATUS_REG[16].GEN_REG_STATUS.ip_irpt_status_reg_reg[16]\
);
\INTR_CTRLR_GEN_I.dummy_intr_reg_rdack_d1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^hard_macro_rst_reg_reg\,
I1 => \INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_d1_i_2_n_0\,
O => dummy_bus2ip_rdce_intr
);
\INTR_CTRLR_GEN_I.dummy_intr_reg_rdack_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_d1_i_2_n_0\,
I1 => \^hard_macro_rst_reg_reg\,
I2 => dummy_intr_reg_rdack_d1,
O => p_5_out
);
\INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_d1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^hard_macro_rst_reg_reg\,
I1 => \INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_d1_i_2_n_0\,
O => \INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_d1_reg\
);
\INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_d1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => \INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_d1_i_3_n_0\,
I1 => \INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_d1_i_4_n_0\,
I2 => p_12_in,
I3 => p_8_in,
I4 => p_11_in,
O => \INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_d1_i_2_n_0\
);
\INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_d1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => p_14_in,
I1 => p_17_in,
I2 => p_16_in,
I3 => p_6_in,
I4 => p_3_in,
I5 => p_5_in,
O => \INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_d1_i_3_n_0\
);
\INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_d1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_13_in,
I1 => p_2_in,
I2 => p_4_in,
I3 => p_15_in,
O => \INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_d1_i_4_n_0\
);
\INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_d1_i_2_n_0\,
I1 => \^hard_macro_rst_reg_reg\,
I2 => dummy_intr_reg_wrack_d1,
O => p_3_out
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00100000"
)
port map (
I0 => p_9_in,
I1 => p_7_in,
I2 => ipif_glbl_irpt_enable_reg,
I3 => \INTR_CTRLR_GEN_I.ip2bus_data_int[0]_i_2_n_0\,
I4 => p_10_in,
O => D(18)
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => s_axi_wstrb(0),
I1 => s_axi_arvalid,
I2 => \^hard_macro_rst_reg_reg\,
O => \INTR_CTRLR_GEN_I.ip2bus_data_int[0]_i_2_n_0\
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000E000000000000"
)
port map (
I0 => jtagmodified_i,
I1 => jtagmodified_d1,
I2 => p_24_in,
I3 => p_23_in,
I4 => \^hard_macro_rst_reg_reg\,
I5 => \^dwe_d1_reg\,
O => D(17)
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_2_n_0\,
I1 => \ip_irpt_enable_reg_reg[16]\(16),
I2 => p_1_in,
I3 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_3_n_0\,
I4 => jtaglocked_i,
I5 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_4_n_0\,
O => D(16)
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"BBBFFFFF"
)
port map (
I0 => p_9_in,
I1 => p_7_in,
I2 => s_axi_wstrb(0),
I3 => s_axi_arvalid,
I4 => \^hard_macro_rst_reg_reg\,
O => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_2_n_0\
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"57FF"
)
port map (
I0 => \^hard_macro_rst_reg_reg\,
I1 => s_axi_arvalid,
I2 => s_axi_wstrb(0),
I3 => p_9_in,
O => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_3_n_0\
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => \^dwe_d1_reg\,
I1 => \^hard_macro_rst_reg_reg\,
I2 => p_23_in,
I3 => p_24_in,
O => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_4_n_0\
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_2_n_0\,
I1 => \ip_irpt_enable_reg_reg[16]\(15),
I2 => p_1_in2_in,
I3 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_3_n_0\,
I4 => \do_reg_reg[15]\(15),
I5 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_4_n_0\,
O => D(15)
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_2_n_0\,
I1 => \ip_irpt_enable_reg_reg[16]\(14),
I2 => p_1_in5_in,
I3 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_3_n_0\,
I4 => \do_reg_reg[15]\(14),
I5 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_4_n_0\,
O => D(14)
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_2_n_0\,
I1 => \ip_irpt_enable_reg_reg[16]\(13),
I2 => p_1_in8_in,
I3 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_3_n_0\,
I4 => \do_reg_reg[15]\(13),
I5 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_4_n_0\,
O => D(13)
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_2_n_0\,
I1 => \ip_irpt_enable_reg_reg[16]\(12),
I2 => p_1_in11_in,
I3 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_3_n_0\,
I4 => \do_reg_reg[15]\(12),
I5 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_4_n_0\,
O => D(12)
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_2_n_0\,
I1 => \ip_irpt_enable_reg_reg[16]\(11),
I2 => p_1_in14_in,
I3 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_3_n_0\,
I4 => \do_reg_reg[15]\(11),
I5 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_4_n_0\,
O => D(11)
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4F4FFF4"
)
port map (
I0 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_2_n_0\,
I1 => \ip_irpt_enable_reg_reg[16]\(10),
I2 => \INTR_CTRLR_GEN_I.ip2bus_data_int[21]_i_2_n_0\,
I3 => p_1_in17_in,
I4 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_3_n_0\,
O => D(10)
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[21]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"002000C000200000"
)
port map (
I0 => \status_reg_reg[10]\(10),
I1 => \^dwe_d1_reg\,
I2 => \^hard_macro_rst_reg_reg\,
I3 => p_23_in,
I4 => p_24_in,
I5 => \do_reg_reg[15]\(10),
O => \INTR_CTRLR_GEN_I.ip2bus_data_int[21]_i_2_n_0\
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4F4FFF4"
)
port map (
I0 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_2_n_0\,
I1 => \ip_irpt_enable_reg_reg[16]\(9),
I2 => \INTR_CTRLR_GEN_I.ip2bus_data_int[22]_i_2_n_0\,
I3 => p_1_in20_in,
I4 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_3_n_0\,
O => D(9)
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[22]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"002000C000200000"
)
port map (
I0 => \do_reg_reg[15]\(9),
I1 => p_24_in,
I2 => \^hard_macro_rst_reg_reg\,
I3 => p_23_in,
I4 => \^dwe_d1_reg\,
I5 => \status_reg_reg[10]\(9),
O => \INTR_CTRLR_GEN_I.ip2bus_data_int[22]_i_2_n_0\
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF44F4"
)
port map (
I0 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_2_n_0\,
I1 => \ip_irpt_enable_reg_reg[16]\(8),
I2 => p_1_in23_in,
I3 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_3_n_0\,
I4 => \INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_2_n_0\,
O => D(8)
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_3_n_0\,
I1 => \status_reg_reg[10]\(8),
I2 => \alarm_reg_reg[8]\(8),
I3 => \INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_4_n_0\,
I4 => \do_reg_reg[15]\(8),
I5 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_4_n_0\,
O => \INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_2_n_0\
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => p_24_in,
I1 => \^hard_macro_rst_reg_reg\,
I2 => p_23_in,
I3 => \^dwe_d1_reg\,
O => \INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_3_n_0\
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => p_23_in,
I1 => p_24_in,
I2 => \^hard_macro_rst_reg_reg\,
I3 => \^dwe_d1_reg\,
O => \INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_4_n_0\
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF44F4"
)
port map (
I0 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_2_n_0\,
I1 => \ip_irpt_enable_reg_reg[16]\(7),
I2 => p_1_in26_in,
I3 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_3_n_0\,
I4 => \INTR_CTRLR_GEN_I.ip2bus_data_int[24]_i_2_n_0\,
O => D(7)
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[24]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_3_n_0\,
I1 => \status_reg_reg[10]\(7),
I2 => \alarm_reg_reg[8]\(7),
I3 => \INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_4_n_0\,
I4 => \do_reg_reg[15]\(7),
I5 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_4_n_0\,
O => \INTR_CTRLR_GEN_I.ip2bus_data_int[24]_i_2_n_0\
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF44F4"
)
port map (
I0 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_2_n_0\,
I1 => \ip_irpt_enable_reg_reg[16]\(6),
I2 => p_1_in29_in,
I3 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_3_n_0\,
I4 => \INTR_CTRLR_GEN_I.ip2bus_data_int[25]_i_2_n_0\,
O => D(6)
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[25]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_3_n_0\,
I1 => \status_reg_reg[10]\(6),
I2 => \alarm_reg_reg[8]\(6),
I3 => \INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_4_n_0\,
I4 => \do_reg_reg[15]\(6),
I5 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_4_n_0\,
O => \INTR_CTRLR_GEN_I.ip2bus_data_int[25]_i_2_n_0\
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF44F4"
)
port map (
I0 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_2_n_0\,
I1 => \ip_irpt_enable_reg_reg[16]\(5),
I2 => p_1_in32_in,
I3 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_3_n_0\,
I4 => \INTR_CTRLR_GEN_I.ip2bus_data_int[26]_i_2_n_0\,
O => D(5)
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[26]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_3_n_0\,
I1 => \status_reg_reg[10]\(5),
I2 => \alarm_reg_reg[8]\(5),
I3 => \INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_4_n_0\,
I4 => \do_reg_reg[15]\(5),
I5 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_4_n_0\,
O => \INTR_CTRLR_GEN_I.ip2bus_data_int[26]_i_2_n_0\
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF44F4"
)
port map (
I0 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_2_n_0\,
I1 => \ip_irpt_enable_reg_reg[16]\(4),
I2 => p_1_in35_in,
I3 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_3_n_0\,
I4 => \INTR_CTRLR_GEN_I.ip2bus_data_int[27]_i_2_n_0\,
O => D(4)
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[27]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_3_n_0\,
I1 => \status_reg_reg[10]\(4),
I2 => \alarm_reg_reg[8]\(4),
I3 => \INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_4_n_0\,
I4 => \do_reg_reg[15]\(4),
I5 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_4_n_0\,
O => \INTR_CTRLR_GEN_I.ip2bus_data_int[27]_i_2_n_0\
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF44F4"
)
port map (
I0 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_2_n_0\,
I1 => \ip_irpt_enable_reg_reg[16]\(3),
I2 => p_1_in38_in,
I3 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_3_n_0\,
I4 => \INTR_CTRLR_GEN_I.ip2bus_data_int[28]_i_2_n_0\,
O => D(3)
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[28]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_3_n_0\,
I1 => \status_reg_reg[10]\(3),
I2 => \alarm_reg_reg[8]\(3),
I3 => \INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_4_n_0\,
I4 => \do_reg_reg[15]\(3),
I5 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_4_n_0\,
O => \INTR_CTRLR_GEN_I.ip2bus_data_int[28]_i_2_n_0\
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[29]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF44F4"
)
port map (
I0 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_2_n_0\,
I1 => \ip_irpt_enable_reg_reg[16]\(2),
I2 => p_1_in41_in,
I3 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_3_n_0\,
I4 => \INTR_CTRLR_GEN_I.ip2bus_data_int[29]_i_2_n_0\,
O => D(2)
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[29]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_3_n_0\,
I1 => \status_reg_reg[10]\(2),
I2 => \alarm_reg_reg[8]\(2),
I3 => \INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_4_n_0\,
I4 => \do_reg_reg[15]\(2),
I5 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_4_n_0\,
O => \INTR_CTRLR_GEN_I.ip2bus_data_int[29]_i_2_n_0\
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[30]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF44F4"
)
port map (
I0 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_2_n_0\,
I1 => \ip_irpt_enable_reg_reg[16]\(1),
I2 => p_1_in44_in,
I3 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_3_n_0\,
I4 => \INTR_CTRLR_GEN_I.ip2bus_data_int[30]_i_2_n_0\,
O => D(1)
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[30]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_3_n_0\,
I1 => \status_reg_reg[10]\(1),
I2 => \alarm_reg_reg[8]\(1),
I3 => \INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_4_n_0\,
I4 => \do_reg_reg[15]\(1),
I5 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_4_n_0\,
O => \INTR_CTRLR_GEN_I.ip2bus_data_int[30]_i_2_n_0\
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[31]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF44F4"
)
port map (
I0 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_2_n_0\,
I1 => \ip_irpt_enable_reg_reg[16]\(0),
I2 => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\,
I3 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_3_n_0\,
I4 => \INTR_CTRLR_GEN_I.ip2bus_data_int[31]_i_2_n_0\,
O => D(0)
);
\INTR_CTRLR_GEN_I.ip2bus_data_int[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_3_n_0\,
I1 => \status_reg_reg[10]\(0),
I2 => \alarm_reg_reg[8]\(0),
I3 => \INTR_CTRLR_GEN_I.ip2bus_data_int[23]_i_4_n_0\,
I4 => \do_reg_reg[15]\(0),
I5 => \INTR_CTRLR_GEN_I.ip2bus_data_int[15]_i_4_n_0\,
O => \INTR_CTRLR_GEN_I.ip2bus_data_int[31]_i_2_n_0\
);
\INTR_CTRLR_GEN_I.ip2bus_error_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \s_axi_wdata_1__s_net_1\,
I1 => p_25_in,
I2 => \^hard_macro_rst_reg_reg\,
O => \^intr_ctrlr_gen_i.ip2bus_wrack_reg\
);
\INTR_CTRLR_GEN_I.ip2bus_wrack_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \^intr_ctrlr_gen_i.ip2bus_wrack_reg\,
I1 => intr_ip2bus_wrack,
I2 => wrack,
I3 => dummy_local_reg_wrack,
I4 => dummy_intr_reg_wrack,
I5 => local_reg_wrack_reg,
O => ip2bus_wrack_int1
);
Intr2Bus_RdAck_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00000F0E"
)
port map (
I0 => p_7_in,
I1 => p_9_in,
I2 => \INTR_CTRLR_GEN_I.ip2bus_data_int[0]_i_2_n_0\,
I3 => p_10_in,
I4 => irpt_rdack_d1,
O => Intr2Bus_RdAck0
);
Intr2Bus_WrAck_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00005554"
)
port map (
I0 => Intr2Bus_WrAck_i_2_n_0,
I1 => p_9_in,
I2 => p_7_in,
I3 => p_10_in,
I4 => irpt_wrack_d1,
O => interrupt_wrce_strb
);
Intr2Bus_WrAck_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"AB"
)
port map (
I0 => \^hard_macro_rst_reg_reg\,
I1 => s_axi_wstrb(0),
I2 => s_axi_arvalid,
O => Intr2Bus_WrAck_i_2_n_0
);
drdy_rd_ack_i_d1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^dwe_d1_reg\,
I1 => \^hard_macro_rst_reg_reg\,
O => bus2ip_rdce(0)
);
drdy_wr_ack_i_d1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^dwe_d1_reg\,
I1 => \^hard_macro_rst_reg_reg\,
O => bus2ip_wrce(0)
);
dummy_local_reg_rdack_d1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"AAA8"
)
port map (
I0 => \^hard_macro_rst_reg_reg\,
I1 => p_18_in,
I2 => p_19_in,
I3 => p_20_in,
O => dummy_local_reg_rdack_d10
);
dummy_local_reg_rdack_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FE00"
)
port map (
I0 => p_20_in,
I1 => p_19_in,
I2 => p_18_in,
I3 => \^hard_macro_rst_reg_reg\,
I4 => dummy_local_reg_rdack_d1,
O => dummy_local_reg_rdack0
);
dummy_local_reg_wrack_d1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"5554"
)
port map (
I0 => \^hard_macro_rst_reg_reg\,
I1 => p_18_in,
I2 => p_19_in,
I3 => p_20_in,
O => dummy_local_reg_wrack_d1_reg
);
dummy_local_reg_wrack_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000FE"
)
port map (
I0 => p_20_in,
I1 => p_19_in,
I2 => p_18_in,
I3 => \^hard_macro_rst_reg_reg\,
I4 => dummy_local_reg_wrack_d1,
O => dummy_local_reg_wrack0
);
dwe_C_reg_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => jtaglocked_i,
I1 => \^dwe_d1_reg\,
I2 => \^hard_macro_rst_reg_reg\,
O => dwe_C_reg_reg
);
dwe_d1_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^hard_macro_rst_reg_reg\,
I1 => \^dwe_d1_reg\,
I2 => jtaglocked_i,
O => dwe_d1_reg_0
);
hard_macro_rst_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEF0020"
)
port map (
I0 => s_axi_wdata(0),
I1 => \^hard_macro_rst_reg_reg\,
I2 => p_21_in,
I3 => p_22_in,
I4 => hard_macro_rst_reg,
O => hard_macro_rst_reg_reg_0
);
\ip_irpt_enable_reg[16]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00A8"
)
port map (
I0 => p_7_in,
I1 => s_axi_arvalid,
I2 => s_axi_wstrb(0),
I3 => \^hard_macro_rst_reg_reg\,
O => E(0)
);
ipif_glbl_irpt_enable_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBBBF00008880"
)
port map (
I0 => s_axi_wdata(1),
I1 => p_10_in,
I2 => s_axi_arvalid,
I3 => s_axi_wstrb(0),
I4 => \^hard_macro_rst_reg_reg\,
I5 => ipif_glbl_irpt_enable_reg,
O => ipif_glbl_irpt_enable_reg_reg
);
irpt_rdack_d1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CCC0CCC0CCC08880"
)
port map (
I0 => p_10_in,
I1 => \^hard_macro_rst_reg_reg\,
I2 => s_axi_arvalid,
I3 => s_axi_wstrb(0),
I4 => p_9_in,
I5 => p_7_in,
O => irpt_rdack
);
irpt_wrack_d1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00FE00FE00FE0000"
)
port map (
I0 => p_10_in,
I1 => p_7_in,
I2 => p_9_in,
I3 => \^hard_macro_rst_reg_reg\,
I4 => s_axi_wstrb(0),
I5 => s_axi_arvalid,
O => irpt_wrack
);
local_reg_rdack_d1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"AAA8"
)
port map (
I0 => \^hard_macro_rst_reg_reg\,
I1 => p_21_in,
I2 => p_22_in,
I3 => p_23_in,
O => local_rdce_or_reduce
);
local_reg_rdack_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FE00"
)
port map (
I0 => p_23_in,
I1 => p_22_in,
I2 => p_21_in,
I3 => \^hard_macro_rst_reg_reg\,
I4 => local_reg_rdack_d1,
O => local_reg_rdack0
);
local_reg_wrack_d1_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"55555554"
)
port map (
I0 => \^hard_macro_rst_reg_reg\,
I1 => p_24_in,
I2 => p_23_in,
I3 => p_21_in,
I4 => p_22_in,
O => local_reg_wrack_d1_reg
);
local_reg_wrack_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000FFFE"
)
port map (
I0 => p_22_in,
I1 => p_21_in,
I2 => p_23_in,
I3 => p_24_in,
I4 => \^hard_macro_rst_reg_reg\,
I5 => local_reg_wrack_d1,
O => local_reg_wrack0
);
reset_trig_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => \^hard_macro_rst_reg_reg\,
I1 => p_25_in,
I2 => \s_axi_wdata_1__s_net_1\,
I3 => sw_rst_cond_d1,
O => reset_trig0
);
rst_ip2bus_rdack_d1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^hard_macro_rst_reg_reg\,
I1 => p_25_in,
O => bus2ip_rdce(2)
);
rst_ip2bus_rdack_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => p_25_in,
I1 => \^hard_macro_rst_reg_reg\,
I2 => rst_ip2bus_rdack_d1,
O => rst_ip2bus_rdack0
);
status_reg_rdack_d1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_24_in,
I1 => \^hard_macro_rst_reg_reg\,
O => bus2ip_rdce(1)
);
status_reg_rdack_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => status_reg_rdack_d1,
I1 => p_24_in,
I2 => \^hard_macro_rst_reg_reg\,
O => status_reg_rdack0
);
sw_rst_cond_d1_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \s_axi_wdata_1__s_net_1\,
I1 => p_25_in,
I2 => \^hard_macro_rst_reg_reg\,
O => sw_rst_cond
);
\temp_rd_wait_cycle_reg[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^hard_macro_rst_reg_reg\,
I1 => p_22_in,
I2 => p_21_in,
O => \temp_rd_wait_cycle_reg_reg[0]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xadc_wiz_0_0_system_xadc_wiz_0_0_interrupt_control is
port (
irpt_wrack_d1 : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ : out STD_LOGIC;
p_1_in44_in : out STD_LOGIC;
p_1_in41_in : out STD_LOGIC;
p_1_in38_in : out STD_LOGIC;
p_1_in35_in : out STD_LOGIC;
p_1_in32_in : out STD_LOGIC;
p_1_in29_in : out STD_LOGIC;
p_1_in26_in : out STD_LOGIC;
p_1_in23_in : out STD_LOGIC;
p_1_in20_in : out STD_LOGIC;
p_1_in17_in : out STD_LOGIC;
p_1_in14_in : out STD_LOGIC;
p_1_in11_in : out STD_LOGIC;
p_1_in8_in : out STD_LOGIC;
p_1_in5_in : out STD_LOGIC;
p_1_in2_in : out STD_LOGIC;
p_1_in : out STD_LOGIC;
intr_ip2bus_wrack : out STD_LOGIC;
irpt_rdack_d1 : out STD_LOGIC;
intr_ip2bus_rdack : out STD_LOGIC;
ipif_glbl_irpt_enable_reg : out STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 16 downto 0 );
reset2ip_reset : in STD_LOGIC;
irpt_wrack : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
den_C_reg_reg : in STD_LOGIC_VECTOR ( 7 downto 0 );
eos_out : in STD_LOGIC;
eoc_out : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
jtagmodified_i : in STD_LOGIC;
ot_d1_reg : in STD_LOGIC;
alarm_0_d1_reg : in STD_LOGIC;
interrupt_wrce_strb : in STD_LOGIC;
irpt_rdack : in STD_LOGIC;
Intr2Bus_RdAck0 : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]\ : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 16 downto 0 );
Bus_RNW_reg_reg : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xadc_wiz_0_0_system_xadc_wiz_0_0_interrupt_control : entity is "system_xadc_wiz_0_0_interrupt_control";
end system_xadc_wiz_0_0_system_xadc_wiz_0_0_interrupt_control;
architecture STRUCTURE of system_xadc_wiz_0_0_system_xadc_wiz_0_0_interrupt_control is
signal \DO_IRPT_INPUT[10].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[10].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[11].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[11].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[12].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[12].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[13].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[13].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[14].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[14].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[2].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[2].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[3].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[3].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[4].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[4].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[5].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[5].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[6].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[6].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[7].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[7].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[8].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[8].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[9].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[9].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[10].GEN_REG_STATUS.ip_irpt_status_reg[10]_i_1_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[11].GEN_REG_STATUS.ip_irpt_status_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[12].GEN_REG_STATUS.ip_irpt_status_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[13].GEN_REG_STATUS.ip_irpt_status_reg[13]_i_1_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[14].GEN_REG_STATUS.ip_irpt_status_reg[14]_i_1_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[15].GEN_REG_STATUS.ip_irpt_status_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[16].GEN_REG_STATUS.ip_irpt_status_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg[5]_i_1_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg[6]_i_1_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[9].GEN_REG_STATUS.ip_irpt_status_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 16 downto 0 );
signal ip2intc_irpt_INST_0_i_1_n_0 : STD_LOGIC;
signal ip2intc_irpt_INST_0_i_2_n_0 : STD_LOGIC;
signal ip2intc_irpt_INST_0_i_3_n_0 : STD_LOGIC;
signal ip2intc_irpt_INST_0_i_4_n_0 : STD_LOGIC;
signal ip2intc_irpt_INST_0_i_5_n_0 : STD_LOGIC;
signal ip2intc_irpt_INST_0_i_6_n_0 : STD_LOGIC;
signal ip2intc_irpt_INST_0_i_7_n_0 : STD_LOGIC;
signal ip2intc_irpt_INST_0_i_8_n_0 : STD_LOGIC;
signal \^ipif_glbl_irpt_enable_reg\ : STD_LOGIC;
signal irpt_dly1 : STD_LOGIC;
signal irpt_dly2 : STD_LOGIC;
signal \^p_1_in\ : STD_LOGIC;
signal \^p_1_in11_in\ : STD_LOGIC;
signal \^p_1_in14_in\ : STD_LOGIC;
signal \^p_1_in17_in\ : STD_LOGIC;
signal \^p_1_in20_in\ : STD_LOGIC;
signal \^p_1_in23_in\ : STD_LOGIC;
signal \^p_1_in26_in\ : STD_LOGIC;
signal \^p_1_in29_in\ : STD_LOGIC;
signal \^p_1_in2_in\ : STD_LOGIC;
signal \^p_1_in32_in\ : STD_LOGIC;
signal \^p_1_in35_in\ : STD_LOGIC;
signal \^p_1_in38_in\ : STD_LOGIC;
signal \^p_1_in41_in\ : STD_LOGIC;
signal \^p_1_in44_in\ : STD_LOGIC;
signal \^p_1_in5_in\ : STD_LOGIC;
signal \^p_1_in8_in\ : STD_LOGIC;
begin
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ <= \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\;
Q(16 downto 0) <= \^q\(16 downto 0);
ipif_glbl_irpt_enable_reg <= \^ipif_glbl_irpt_enable_reg\;
p_1_in <= \^p_1_in\;
p_1_in11_in <= \^p_1_in11_in\;
p_1_in14_in <= \^p_1_in14_in\;
p_1_in17_in <= \^p_1_in17_in\;
p_1_in20_in <= \^p_1_in20_in\;
p_1_in23_in <= \^p_1_in23_in\;
p_1_in26_in <= \^p_1_in26_in\;
p_1_in29_in <= \^p_1_in29_in\;
p_1_in2_in <= \^p_1_in2_in\;
p_1_in32_in <= \^p_1_in32_in\;
p_1_in35_in <= \^p_1_in35_in\;
p_1_in38_in <= \^p_1_in38_in\;
p_1_in41_in <= \^p_1_in41_in\;
p_1_in44_in <= \^p_1_in44_in\;
p_1_in5_in <= \^p_1_in5_in\;
p_1_in8_in <= \^p_1_in8_in\;
\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => den_C_reg_reg(0),
Q => irpt_dly1,
S => reset2ip_reset
);
\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_dly1,
Q => irpt_dly2,
S => reset2ip_reset
);
\DO_IRPT_INPUT[10].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => den_C_reg_reg(4),
Q => \DO_IRPT_INPUT[10].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
S => reset2ip_reset
);
\DO_IRPT_INPUT[10].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \DO_IRPT_INPUT[10].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
Q => \DO_IRPT_INPUT[10].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
S => reset2ip_reset
);
\DO_IRPT_INPUT[11].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => den_C_reg_reg(5),
Q => \DO_IRPT_INPUT[11].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
S => reset2ip_reset
);
\DO_IRPT_INPUT[11].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \DO_IRPT_INPUT[11].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
Q => \DO_IRPT_INPUT[11].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
S => reset2ip_reset
);
\DO_IRPT_INPUT[12].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => den_C_reg_reg(6),
Q => \DO_IRPT_INPUT[12].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
S => reset2ip_reset
);
\DO_IRPT_INPUT[12].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \DO_IRPT_INPUT[12].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
Q => \DO_IRPT_INPUT[12].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
S => reset2ip_reset
);
\DO_IRPT_INPUT[13].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => den_C_reg_reg(7),
Q => \DO_IRPT_INPUT[13].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
S => reset2ip_reset
);
\DO_IRPT_INPUT[13].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \DO_IRPT_INPUT[13].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
Q => \DO_IRPT_INPUT[13].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
S => reset2ip_reset
);
\DO_IRPT_INPUT[14].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
Q => \DO_IRPT_INPUT[14].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
S => reset2ip_reset
);
\DO_IRPT_INPUT[14].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \DO_IRPT_INPUT[14].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
Q => \DO_IRPT_INPUT[14].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
S => reset2ip_reset
);
\DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => den_C_reg_reg(1),
Q => \DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
S => reset2ip_reset
);
\DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
Q => \DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
S => reset2ip_reset
);
\DO_IRPT_INPUT[2].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => den_C_reg_reg(2),
Q => \DO_IRPT_INPUT[2].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
S => reset2ip_reset
);
\DO_IRPT_INPUT[2].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \DO_IRPT_INPUT[2].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
Q => \DO_IRPT_INPUT[2].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
S => reset2ip_reset
);
\DO_IRPT_INPUT[3].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => den_C_reg_reg(3),
Q => \DO_IRPT_INPUT[3].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
S => reset2ip_reset
);
\DO_IRPT_INPUT[3].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \DO_IRPT_INPUT[3].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
Q => \DO_IRPT_INPUT[3].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
S => reset2ip_reset
);
\DO_IRPT_INPUT[4].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => eos_out,
Q => \DO_IRPT_INPUT[4].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
S => reset2ip_reset
);
\DO_IRPT_INPUT[4].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \DO_IRPT_INPUT[4].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
Q => \DO_IRPT_INPUT[4].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
S => reset2ip_reset
);
\DO_IRPT_INPUT[5].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => eoc_out,
Q => \DO_IRPT_INPUT[5].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
S => reset2ip_reset
);
\DO_IRPT_INPUT[5].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \DO_IRPT_INPUT[5].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
Q => \DO_IRPT_INPUT[5].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
S => reset2ip_reset
);
\DO_IRPT_INPUT[6].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => D(0),
Q => \DO_IRPT_INPUT[6].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
S => reset2ip_reset
);
\DO_IRPT_INPUT[6].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \DO_IRPT_INPUT[6].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
Q => \DO_IRPT_INPUT[6].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
S => reset2ip_reset
);
\DO_IRPT_INPUT[7].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => jtagmodified_i,
Q => \DO_IRPT_INPUT[7].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
S => reset2ip_reset
);
\DO_IRPT_INPUT[7].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \DO_IRPT_INPUT[7].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
Q => \DO_IRPT_INPUT[7].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
S => reset2ip_reset
);
\DO_IRPT_INPUT[8].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => ot_d1_reg,
Q => \DO_IRPT_INPUT[8].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
S => reset2ip_reset
);
\DO_IRPT_INPUT[8].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \DO_IRPT_INPUT[8].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
Q => \DO_IRPT_INPUT[8].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
S => reset2ip_reset
);
\DO_IRPT_INPUT[9].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => alarm_0_d1_reg,
Q => \DO_IRPT_INPUT[9].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
S => reset2ip_reset
);
\DO_IRPT_INPUT[9].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \DO_IRPT_INPUT[9].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
Q => \DO_IRPT_INPUT[9].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
S => reset2ip_reset
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4F44F4"
)
port map (
I0 => irpt_dly2,
I1 => irpt_dly1,
I2 => s_axi_wdata(0),
I3 => Bus_RNW_reg_reg,
I4 => \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\,
O => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\,
Q => \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\,
R => reset2ip_reset
);
\GEN_IP_IRPT_STATUS_REG[10].GEN_REG_STATUS.ip_irpt_status_reg[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4F44F4"
)
port map (
I0 => \DO_IRPT_INPUT[10].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
I1 => \DO_IRPT_INPUT[10].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
I2 => s_axi_wdata(10),
I3 => Bus_RNW_reg_reg,
I4 => \^p_1_in17_in\,
O => \GEN_IP_IRPT_STATUS_REG[10].GEN_REG_STATUS.ip_irpt_status_reg[10]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[10].GEN_REG_STATUS.ip_irpt_status_reg_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[10].GEN_REG_STATUS.ip_irpt_status_reg[10]_i_1_n_0\,
Q => \^p_1_in17_in\,
R => reset2ip_reset
);
\GEN_IP_IRPT_STATUS_REG[11].GEN_REG_STATUS.ip_irpt_status_reg[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4F44F4"
)
port map (
I0 => \DO_IRPT_INPUT[11].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
I1 => \DO_IRPT_INPUT[11].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
I2 => s_axi_wdata(11),
I3 => Bus_RNW_reg_reg,
I4 => \^p_1_in14_in\,
O => \GEN_IP_IRPT_STATUS_REG[11].GEN_REG_STATUS.ip_irpt_status_reg[11]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[11].GEN_REG_STATUS.ip_irpt_status_reg_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[11].GEN_REG_STATUS.ip_irpt_status_reg[11]_i_1_n_0\,
Q => \^p_1_in14_in\,
R => reset2ip_reset
);
\GEN_IP_IRPT_STATUS_REG[12].GEN_REG_STATUS.ip_irpt_status_reg[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4F44F4"
)
port map (
I0 => \DO_IRPT_INPUT[12].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
I1 => \DO_IRPT_INPUT[12].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
I2 => s_axi_wdata(12),
I3 => Bus_RNW_reg_reg,
I4 => \^p_1_in11_in\,
O => \GEN_IP_IRPT_STATUS_REG[12].GEN_REG_STATUS.ip_irpt_status_reg[12]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[12].GEN_REG_STATUS.ip_irpt_status_reg_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[12].GEN_REG_STATUS.ip_irpt_status_reg[12]_i_1_n_0\,
Q => \^p_1_in11_in\,
R => reset2ip_reset
);
\GEN_IP_IRPT_STATUS_REG[13].GEN_REG_STATUS.ip_irpt_status_reg[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4F44F4"
)
port map (
I0 => \DO_IRPT_INPUT[13].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
I1 => \DO_IRPT_INPUT[13].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
I2 => s_axi_wdata(13),
I3 => Bus_RNW_reg_reg,
I4 => \^p_1_in8_in\,
O => \GEN_IP_IRPT_STATUS_REG[13].GEN_REG_STATUS.ip_irpt_status_reg[13]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[13].GEN_REG_STATUS.ip_irpt_status_reg_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[13].GEN_REG_STATUS.ip_irpt_status_reg[13]_i_1_n_0\,
Q => \^p_1_in8_in\,
R => reset2ip_reset
);
\GEN_IP_IRPT_STATUS_REG[14].GEN_REG_STATUS.ip_irpt_status_reg[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4F44F4"
)
port map (
I0 => \DO_IRPT_INPUT[14].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
I1 => \DO_IRPT_INPUT[14].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
I2 => s_axi_wdata(14),
I3 => Bus_RNW_reg_reg,
I4 => \^p_1_in5_in\,
O => \GEN_IP_IRPT_STATUS_REG[14].GEN_REG_STATUS.ip_irpt_status_reg[14]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[14].GEN_REG_STATUS.ip_irpt_status_reg_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[14].GEN_REG_STATUS.ip_irpt_status_reg[14]_i_1_n_0\,
Q => \^p_1_in5_in\,
R => reset2ip_reset
);
\GEN_IP_IRPT_STATUS_REG[15].GEN_REG_STATUS.ip_irpt_status_reg[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4F44F4"
)
port map (
I0 => \DO_IRPT_INPUT[14].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
I1 => \DO_IRPT_INPUT[14].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
I2 => s_axi_wdata(15),
I3 => Bus_RNW_reg_reg,
I4 => \^p_1_in2_in\,
O => \GEN_IP_IRPT_STATUS_REG[15].GEN_REG_STATUS.ip_irpt_status_reg[15]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[15].GEN_REG_STATUS.ip_irpt_status_reg_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[15].GEN_REG_STATUS.ip_irpt_status_reg[15]_i_1_n_0\,
Q => \^p_1_in2_in\,
R => reset2ip_reset
);
\GEN_IP_IRPT_STATUS_REG[16].GEN_REG_STATUS.ip_irpt_status_reg[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4F44F4"
)
port map (
I0 => \DO_IRPT_INPUT[14].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
I1 => \DO_IRPT_INPUT[14].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
I2 => s_axi_wdata(16),
I3 => Bus_RNW_reg_reg,
I4 => \^p_1_in\,
O => \GEN_IP_IRPT_STATUS_REG[16].GEN_REG_STATUS.ip_irpt_status_reg[16]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[16].GEN_REG_STATUS.ip_irpt_status_reg_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[16].GEN_REG_STATUS.ip_irpt_status_reg[16]_i_1_n_0\,
Q => \^p_1_in\,
R => reset2ip_reset
);
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4F44F4"
)
port map (
I0 => \DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
I1 => \DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
I2 => s_axi_wdata(1),
I3 => Bus_RNW_reg_reg,
I4 => \^p_1_in44_in\,
O => \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1_n_0\,
Q => \^p_1_in44_in\,
R => reset2ip_reset
);
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4F44F4"
)
port map (
I0 => \DO_IRPT_INPUT[2].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
I1 => \DO_IRPT_INPUT[2].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
I2 => s_axi_wdata(2),
I3 => Bus_RNW_reg_reg,
I4 => \^p_1_in41_in\,
O => \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_1_n_0\,
Q => \^p_1_in41_in\,
R => reset2ip_reset
);
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4F44F4"
)
port map (
I0 => \DO_IRPT_INPUT[3].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
I1 => \DO_IRPT_INPUT[3].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
I2 => s_axi_wdata(3),
I3 => Bus_RNW_reg_reg,
I4 => \^p_1_in38_in\,
O => \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg[3]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg[3]_i_1_n_0\,
Q => \^p_1_in38_in\,
R => reset2ip_reset
);
\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4F44F4"
)
port map (
I0 => \DO_IRPT_INPUT[4].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
I1 => \DO_IRPT_INPUT[4].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
I2 => s_axi_wdata(4),
I3 => Bus_RNW_reg_reg,
I4 => \^p_1_in35_in\,
O => \GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg[4]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg[4]_i_1_n_0\,
Q => \^p_1_in35_in\,
R => reset2ip_reset
);
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4F44F4"
)
port map (
I0 => \DO_IRPT_INPUT[5].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
I1 => \DO_IRPT_INPUT[5].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
I2 => s_axi_wdata(5),
I3 => Bus_RNW_reg_reg,
I4 => \^p_1_in32_in\,
O => \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg[5]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg[5]_i_1_n_0\,
Q => \^p_1_in32_in\,
R => reset2ip_reset
);
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4F44F4"
)
port map (
I0 => \DO_IRPT_INPUT[6].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
I1 => \DO_IRPT_INPUT[6].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
I2 => s_axi_wdata(6),
I3 => Bus_RNW_reg_reg,
I4 => \^p_1_in29_in\,
O => \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg[6]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg[6]_i_1_n_0\,
Q => \^p_1_in29_in\,
R => reset2ip_reset
);
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4F44F4"
)
port map (
I0 => \DO_IRPT_INPUT[7].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
I1 => \DO_IRPT_INPUT[7].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
I2 => s_axi_wdata(7),
I3 => Bus_RNW_reg_reg,
I4 => \^p_1_in26_in\,
O => \GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg[7]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg[7]_i_1_n_0\,
Q => \^p_1_in26_in\,
R => reset2ip_reset
);
\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4F44F4"
)
port map (
I0 => \DO_IRPT_INPUT[8].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
I1 => \DO_IRPT_INPUT[8].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
I2 => s_axi_wdata(8),
I3 => Bus_RNW_reg_reg,
I4 => \^p_1_in23_in\,
O => \GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg[8]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg[8]_i_1_n_0\,
Q => \^p_1_in23_in\,
R => reset2ip_reset
);
\GEN_IP_IRPT_STATUS_REG[9].GEN_REG_STATUS.ip_irpt_status_reg[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF4F44F4"
)
port map (
I0 => \DO_IRPT_INPUT[9].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
I1 => \DO_IRPT_INPUT[9].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
I2 => s_axi_wdata(9),
I3 => Bus_RNW_reg_reg,
I4 => \^p_1_in20_in\,
O => \GEN_IP_IRPT_STATUS_REG[9].GEN_REG_STATUS.ip_irpt_status_reg[9]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[9].GEN_REG_STATUS.ip_irpt_status_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[9].GEN_REG_STATUS.ip_irpt_status_reg[9]_i_1_n_0\,
Q => \^p_1_in20_in\,
R => reset2ip_reset
);
Intr2Bus_RdAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Intr2Bus_RdAck0,
Q => intr_ip2bus_rdack,
R => reset2ip_reset
);
Intr2Bus_WrAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => interrupt_wrce_strb,
Q => intr_ip2bus_wrack,
R => reset2ip_reset
);
ip2intc_irpt_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA8AAAA"
)
port map (
I0 => \^ipif_glbl_irpt_enable_reg\,
I1 => ip2intc_irpt_INST_0_i_1_n_0,
I2 => ip2intc_irpt_INST_0_i_2_n_0,
I3 => ip2intc_irpt_INST_0_i_3_n_0,
I4 => ip2intc_irpt_INST_0_i_4_n_0,
O => ip2intc_irpt
);
ip2intc_irpt_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => \^q\(1),
I1 => \^p_1_in44_in\,
I2 => \^p_1_in26_in\,
I3 => \^q\(7),
I4 => \^p_1_in38_in\,
I5 => \^q\(3),
O => ip2intc_irpt_INST_0_i_1_n_0
);
ip2intc_irpt_INST_0_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \^p_1_in17_in\,
I1 => \^q\(10),
I2 => \^p_1_in41_in\,
I3 => \^q\(2),
I4 => ip2intc_irpt_INST_0_i_5_n_0,
O => ip2intc_irpt_INST_0_i_2_n_0
);
ip2intc_irpt_INST_0_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \^p_1_in8_in\,
I1 => \^q\(13),
I2 => \^p_1_in29_in\,
I3 => \^q\(6),
I4 => ip2intc_irpt_INST_0_i_6_n_0,
O => ip2intc_irpt_INST_0_i_3_n_0
);
ip2intc_irpt_INST_0_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000777"
)
port map (
I0 => \^p_1_in14_in\,
I1 => \^q\(11),
I2 => \^p_1_in5_in\,
I3 => \^q\(14),
I4 => ip2intc_irpt_INST_0_i_7_n_0,
I5 => ip2intc_irpt_INST_0_i_8_n_0,
O => ip2intc_irpt_INST_0_i_4_n_0
);
ip2intc_irpt_INST_0_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^q\(8),
I1 => \^p_1_in23_in\,
I2 => \^q\(0),
I3 => \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\,
O => ip2intc_irpt_INST_0_i_5_n_0
);
ip2intc_irpt_INST_0_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^q\(4),
I1 => \^p_1_in35_in\,
I2 => \^q\(15),
I3 => \^p_1_in2_in\,
O => ip2intc_irpt_INST_0_i_6_n_0
);
ip2intc_irpt_INST_0_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^q\(16),
I1 => \^p_1_in\,
I2 => \^q\(12),
I3 => \^p_1_in11_in\,
O => ip2intc_irpt_INST_0_i_7_n_0
);
ip2intc_irpt_INST_0_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^q\(5),
I1 => \^p_1_in32_in\,
I2 => \^q\(9),
I3 => \^p_1_in20_in\,
O => ip2intc_irpt_INST_0_i_8_n_0
);
\ip_irpt_enable_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(0),
Q => \^q\(0),
R => reset2ip_reset
);
\ip_irpt_enable_reg_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(10),
Q => \^q\(10),
R => reset2ip_reset
);
\ip_irpt_enable_reg_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(11),
Q => \^q\(11),
R => reset2ip_reset
);
\ip_irpt_enable_reg_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(12),
Q => \^q\(12),
R => reset2ip_reset
);
\ip_irpt_enable_reg_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(13),
Q => \^q\(13),
R => reset2ip_reset
);
\ip_irpt_enable_reg_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(14),
Q => \^q\(14),
R => reset2ip_reset
);
\ip_irpt_enable_reg_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(15),
Q => \^q\(15),
R => reset2ip_reset
);
\ip_irpt_enable_reg_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(16),
Q => \^q\(16),
R => reset2ip_reset
);
\ip_irpt_enable_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(1),
Q => \^q\(1),
R => reset2ip_reset
);
\ip_irpt_enable_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(2),
Q => \^q\(2),
R => reset2ip_reset
);
\ip_irpt_enable_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(3),
Q => \^q\(3),
R => reset2ip_reset
);
\ip_irpt_enable_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(4),
Q => \^q\(4),
R => reset2ip_reset
);
\ip_irpt_enable_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(5),
Q => \^q\(5),
R => reset2ip_reset
);
\ip_irpt_enable_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(6),
Q => \^q\(6),
R => reset2ip_reset
);
\ip_irpt_enable_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(7),
Q => \^q\(7),
R => reset2ip_reset
);
\ip_irpt_enable_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(8),
Q => \^q\(8),
R => reset2ip_reset
);
\ip_irpt_enable_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(9),
Q => \^q\(9),
R => reset2ip_reset
);
ipif_glbl_irpt_enable_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]\,
Q => \^ipif_glbl_irpt_enable_reg\,
R => reset2ip_reset
);
irpt_rdack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_rdack,
Q => irpt_rdack_d1,
R => reset2ip_reset
);
irpt_wrack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_wrack,
Q => irpt_wrack_d1,
R => reset2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xadc_wiz_0_0_system_xadc_wiz_0_0_soft_reset is
port (
sw_rst_cond_d1 : out STD_LOGIC;
wrack : out STD_LOGIC;
\ip_irpt_enable_reg_reg[16]\ : out STD_LOGIC;
reset2ip_reset : out STD_LOGIC;
reset_trig_reg_0 : out STD_LOGIC;
reset : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_reset_active_high : in STD_LOGIC;
sw_rst_cond : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
reset_trig0 : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 3 downto 0 );
hard_macro_rst_reg : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xadc_wiz_0_0_system_xadc_wiz_0_0_soft_reset : entity is "system_xadc_wiz_0_0_soft_reset";
end system_xadc_wiz_0_0_system_xadc_wiz_0_0_soft_reset;
architecture STRUCTURE of system_xadc_wiz_0_0_system_xadc_wiz_0_0_soft_reset is
signal FF_WRACK_i_1_n_0 : STD_LOGIC;
signal \RESET_FLOPS[10].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[11].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[12].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[13].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[14].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[15].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[1].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[2].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[3].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[4].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[5].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[6].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[7].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[8].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[9].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal S : STD_LOGIC;
signal flop_q_chain : STD_LOGIC_VECTOR ( 1 to 15 );
signal \^ip_irpt_enable_reg_reg[16]\ : STD_LOGIC;
attribute IS_CE_INVERTED : string;
attribute IS_CE_INVERTED of FF_WRACK : label is "1'b0";
attribute IS_S_INVERTED : string;
attribute IS_S_INVERTED of FF_WRACK : label is "1'b0";
attribute box_type : string;
attribute box_type of FF_WRACK : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of FF_WRACK_i_1 : label is "soft_lutpair64";
attribute IS_CE_INVERTED of \RESET_FLOPS[0].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[0].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[0].RST_FLOPS\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \RESET_FLOPS[10].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[10].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[10].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[10].RST_FLOPS_i_1\ : label is "soft_lutpair69";
attribute IS_CE_INVERTED of \RESET_FLOPS[11].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[11].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[11].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[11].RST_FLOPS_i_1\ : label is "soft_lutpair70";
attribute IS_CE_INVERTED of \RESET_FLOPS[12].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[12].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[12].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[12].RST_FLOPS_i_1\ : label is "soft_lutpair70";
attribute IS_CE_INVERTED of \RESET_FLOPS[13].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[13].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[13].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[13].RST_FLOPS_i_1\ : label is "soft_lutpair71";
attribute IS_CE_INVERTED of \RESET_FLOPS[14].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[14].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[14].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[14].RST_FLOPS_i_1\ : label is "soft_lutpair71";
attribute IS_CE_INVERTED of \RESET_FLOPS[15].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[15].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[15].RST_FLOPS\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \RESET_FLOPS[1].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[1].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[1].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[1].RST_FLOPS_i_1\ : label is "soft_lutpair65";
attribute IS_CE_INVERTED of \RESET_FLOPS[2].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[2].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[2].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[2].RST_FLOPS_i_1\ : label is "soft_lutpair65";
attribute IS_CE_INVERTED of \RESET_FLOPS[3].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[3].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[3].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[3].RST_FLOPS_i_1\ : label is "soft_lutpair66";
attribute IS_CE_INVERTED of \RESET_FLOPS[4].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[4].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[4].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[4].RST_FLOPS_i_1\ : label is "soft_lutpair66";
attribute IS_CE_INVERTED of \RESET_FLOPS[5].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[5].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[5].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[5].RST_FLOPS_i_1\ : label is "soft_lutpair67";
attribute IS_CE_INVERTED of \RESET_FLOPS[6].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[6].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[6].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[6].RST_FLOPS_i_1\ : label is "soft_lutpair67";
attribute IS_CE_INVERTED of \RESET_FLOPS[7].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[7].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[7].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[7].RST_FLOPS_i_1\ : label is "soft_lutpair68";
attribute IS_CE_INVERTED of \RESET_FLOPS[8].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[8].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[8].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[8].RST_FLOPS_i_1\ : label is "soft_lutpair68";
attribute IS_CE_INVERTED of \RESET_FLOPS[9].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[9].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[9].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[9].RST_FLOPS_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of XADC_INST_i_1 : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \alarm_reg[8]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \do_reg[15]_i_1\ : label is "soft_lutpair63";
begin
\ip_irpt_enable_reg_reg[16]\ <= \^ip_irpt_enable_reg_reg[16]\;
FF_WRACK: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => FF_WRACK_i_1_n_0,
Q => wrack,
R => bus2ip_reset_active_high
);
FF_WRACK_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^ip_irpt_enable_reg_reg[16]\,
I1 => flop_q_chain(15),
O => FF_WRACK_i_1_n_0
);
\RESET_FLOPS[0].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => S,
Q => flop_q_chain(1),
R => bus2ip_reset_active_high
);
\RESET_FLOPS[10].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[10].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(11),
R => bus2ip_reset_active_high
);
\RESET_FLOPS[10].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(10),
O => \RESET_FLOPS[10].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[11].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[11].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(12),
R => bus2ip_reset_active_high
);
\RESET_FLOPS[11].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(11),
O => \RESET_FLOPS[11].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[12].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[12].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(13),
R => bus2ip_reset_active_high
);
\RESET_FLOPS[12].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(12),
O => \RESET_FLOPS[12].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[13].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[13].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(14),
R => bus2ip_reset_active_high
);
\RESET_FLOPS[13].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(13),
O => \RESET_FLOPS[13].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[14].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[14].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(15),
R => bus2ip_reset_active_high
);
\RESET_FLOPS[14].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(14),
O => \RESET_FLOPS[14].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[15].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[15].RST_FLOPS_i_1_n_0\,
Q => \^ip_irpt_enable_reg_reg[16]\,
R => bus2ip_reset_active_high
);
\RESET_FLOPS[15].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(15),
O => \RESET_FLOPS[15].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[1].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[1].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(2),
R => bus2ip_reset_active_high
);
\RESET_FLOPS[1].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(1),
O => \RESET_FLOPS[1].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[2].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[2].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(3),
R => bus2ip_reset_active_high
);
\RESET_FLOPS[2].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(2),
O => \RESET_FLOPS[2].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[3].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[3].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(4),
R => bus2ip_reset_active_high
);
\RESET_FLOPS[3].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(3),
O => \RESET_FLOPS[3].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[4].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[4].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(5),
R => bus2ip_reset_active_high
);
\RESET_FLOPS[4].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(4),
O => \RESET_FLOPS[4].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[5].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[5].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(6),
R => bus2ip_reset_active_high
);
\RESET_FLOPS[5].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(5),
O => \RESET_FLOPS[5].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[6].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[6].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(7),
R => bus2ip_reset_active_high
);
\RESET_FLOPS[6].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(6),
O => \RESET_FLOPS[6].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[7].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[7].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(8),
R => bus2ip_reset_active_high
);
\RESET_FLOPS[7].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(7),
O => \RESET_FLOPS[7].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[8].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[8].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(9),
R => bus2ip_reset_active_high
);
\RESET_FLOPS[8].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(8),
O => \RESET_FLOPS[8].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[9].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[9].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(10),
R => bus2ip_reset_active_high
);
\RESET_FLOPS[9].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(9),
O => \RESET_FLOPS[9].RST_FLOPS_i_1_n_0\
);
XADC_INST_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \^ip_irpt_enable_reg_reg[16]\,
I1 => bus2ip_reset_active_high,
I2 => hard_macro_rst_reg,
O => reset
);
\alarm_reg[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^ip_irpt_enable_reg_reg[16]\,
I1 => bus2ip_reset_active_high,
O => reset2ip_reset
);
\do_reg[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \^ip_irpt_enable_reg_reg[16]\,
I1 => bus2ip_reset_active_high,
I2 => D(0),
O => SR(0)
);
reset_trig_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => reset_trig0,
Q => S,
R => bus2ip_reset_active_high
);
sw_rst_cond_d1_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"00000E0000000000"
)
port map (
I0 => s_axi_wstrb(0),
I1 => s_axi_arvalid,
I2 => s_axi_wdata(2),
I3 => s_axi_wdata(3),
I4 => s_axi_wdata(0),
I5 => s_axi_wdata(1),
O => reset_trig_reg_0
);
sw_rst_cond_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => sw_rst_cond,
Q => sw_rst_cond_d1,
R => bus2ip_reset_active_high
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xadc_wiz_0_0_temperature_update is
port (
den_A : out STD_LOGIC;
bbusy_A : out STD_LOGIC;
overlap_B_reg : out STD_LOGIC;
\state_reg[0]_0\ : out STD_LOGIC;
overlap_B_reg_0 : out STD_LOGIC;
temp_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_aclk : in STD_LOGIC;
reset : in STD_LOGIC;
den_d1_reg : in STD_LOGIC;
overlap_B_reg_1 : in STD_LOGIC;
\state_reg[0]_1\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
overlap_A_reg : in STD_LOGIC;
drdy_i : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]\ : in STD_LOGIC;
den_C_reg_reg : in STD_LOGIC;
den_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xadc_wiz_0_0_temperature_update : entity is "temperature_update";
end system_xadc_wiz_0_0_temperature_update;
architecture STRUCTURE of system_xadc_wiz_0_0_temperature_update is
signal \^bbusy_a\ : STD_LOGIC;
signal busy_o_i_1_n_0 : STD_LOGIC;
signal \^den_a\ : STD_LOGIC;
signal den_o_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state[0]_i_1_n_0\ : STD_LOGIC;
signal \state[0]_i_2__1_n_0\ : STD_LOGIC;
signal \state[0]_i_3_n_0\ : STD_LOGIC;
signal \state[0]_i_4_n_0\ : STD_LOGIC;
signal \state[0]_i_5_n_0\ : STD_LOGIC;
signal \state[1]_i_1_n_0\ : STD_LOGIC;
signal \temp_out[11]_i_1_n_0\ : STD_LOGIC;
signal \timer_cntr[0]_i_10_n_0\ : STD_LOGIC;
signal \timer_cntr[0]_i_2_n_0\ : STD_LOGIC;
signal \timer_cntr[0]_i_3_n_0\ : STD_LOGIC;
signal \timer_cntr[0]_i_4_n_0\ : STD_LOGIC;
signal \timer_cntr[0]_i_5_n_0\ : STD_LOGIC;
signal \timer_cntr[0]_i_6_n_0\ : STD_LOGIC;
signal \timer_cntr[0]_i_7_n_0\ : STD_LOGIC;
signal \timer_cntr[0]_i_8_n_0\ : STD_LOGIC;
signal \timer_cntr[0]_i_9_n_0\ : STD_LOGIC;
signal \timer_cntr[12]_i_2_n_0\ : STD_LOGIC;
signal \timer_cntr[12]_i_3_n_0\ : STD_LOGIC;
signal \timer_cntr[12]_i_4_n_0\ : STD_LOGIC;
signal \timer_cntr[12]_i_5_n_0\ : STD_LOGIC;
signal \timer_cntr[12]_i_6_n_0\ : STD_LOGIC;
signal \timer_cntr[12]_i_7_n_0\ : STD_LOGIC;
signal \timer_cntr[12]_i_8_n_0\ : STD_LOGIC;
signal \timer_cntr[4]_i_2_n_0\ : STD_LOGIC;
signal \timer_cntr[4]_i_3_n_0\ : STD_LOGIC;
signal \timer_cntr[4]_i_4_n_0\ : STD_LOGIC;
signal \timer_cntr[4]_i_5_n_0\ : STD_LOGIC;
signal \timer_cntr[4]_i_6_n_0\ : STD_LOGIC;
signal \timer_cntr[4]_i_7_n_0\ : STD_LOGIC;
signal \timer_cntr[4]_i_8_n_0\ : STD_LOGIC;
signal \timer_cntr[4]_i_9_n_0\ : STD_LOGIC;
signal \timer_cntr[8]_i_2_n_0\ : STD_LOGIC;
signal \timer_cntr[8]_i_3_n_0\ : STD_LOGIC;
signal \timer_cntr[8]_i_4_n_0\ : STD_LOGIC;
signal \timer_cntr[8]_i_5_n_0\ : STD_LOGIC;
signal \timer_cntr[8]_i_6_n_0\ : STD_LOGIC;
signal \timer_cntr[8]_i_7_n_0\ : STD_LOGIC;
signal \timer_cntr[8]_i_8_n_0\ : STD_LOGIC;
signal \timer_cntr[8]_i_9_n_0\ : STD_LOGIC;
signal timer_cntr_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \timer_cntr_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \timer_cntr_reg[0]_i_1_n_1\ : STD_LOGIC;
signal \timer_cntr_reg[0]_i_1_n_2\ : STD_LOGIC;
signal \timer_cntr_reg[0]_i_1_n_3\ : STD_LOGIC;
signal \timer_cntr_reg[0]_i_1_n_4\ : STD_LOGIC;
signal \timer_cntr_reg[0]_i_1_n_5\ : STD_LOGIC;
signal \timer_cntr_reg[0]_i_1_n_6\ : STD_LOGIC;
signal \timer_cntr_reg[0]_i_1_n_7\ : STD_LOGIC;
signal \timer_cntr_reg[12]_i_1_n_1\ : STD_LOGIC;
signal \timer_cntr_reg[12]_i_1_n_2\ : STD_LOGIC;
signal \timer_cntr_reg[12]_i_1_n_3\ : STD_LOGIC;
signal \timer_cntr_reg[12]_i_1_n_4\ : STD_LOGIC;
signal \timer_cntr_reg[12]_i_1_n_5\ : STD_LOGIC;
signal \timer_cntr_reg[12]_i_1_n_6\ : STD_LOGIC;
signal \timer_cntr_reg[12]_i_1_n_7\ : STD_LOGIC;
signal \timer_cntr_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \timer_cntr_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \timer_cntr_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \timer_cntr_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \timer_cntr_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \timer_cntr_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \timer_cntr_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \timer_cntr_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \timer_cntr_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \timer_cntr_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \timer_cntr_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \timer_cntr_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \timer_cntr_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \timer_cntr_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \timer_cntr_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \timer_cntr_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \NLW_timer_cntr_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of busy_o_i_1 : label is "soft_lutpair59";
attribute SOFT_HLUTNM of overlap_B_i_3 : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \state[0]_i_5__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \state[1]_i_1\ : label is "soft_lutpair59";
begin
bbusy_A <= \^bbusy_a\;
den_A <= \^den_a\;
busy_o_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7F50"
)
port map (
I0 => state(1),
I1 => drdy_i,
I2 => state(0),
I3 => \^bbusy_a\,
O => busy_o_i_1_n_0
);
busy_o_reg: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => '1',
CLR => reset,
D => busy_o_i_1_n_0,
Q => \^bbusy_a\
);
den_o_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"32"
)
port map (
I0 => state(1),
I1 => state(0),
I2 => \^den_a\,
O => den_o_i_1_n_0
);
den_o_reg: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => '1',
CLR => reset,
D => den_o_i_1_n_0,
Q => \^den_a\
);
overlap_B_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAA08"
)
port map (
I0 => den_d1_reg,
I1 => \^den_a\,
I2 => overlap_B_reg_1,
I3 => \state_reg[0]_1\,
I4 => \^bbusy_a\,
O => overlap_B_reg
);
overlap_B_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"5551"
)
port map (
I0 => \^den_a\,
I1 => \GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]\,
I2 => den_C_reg_reg,
I3 => den_d1,
O => overlap_B_reg_0
);
\state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"22222222AAAAAAFA"
)
port map (
I0 => state(1),
I1 => drdy_i,
I2 => \state[0]_i_2__1_n_0\,
I3 => \state[0]_i_3_n_0\,
I4 => \state[0]_i_4_n_0\,
I5 => state(0),
O => \state[0]_i_1_n_0\
);
\state[0]_i_2__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"01FF"
)
port map (
I0 => timer_cntr_reg(2),
I1 => timer_cntr_reg(1),
I2 => timer_cntr_reg(0),
I3 => timer_cntr_reg(3),
O => \state[0]_i_2__1_n_0\
);
\state[0]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => timer_cntr_reg(5),
I1 => timer_cntr_reg(4),
I2 => timer_cntr_reg(7),
I3 => timer_cntr_reg(6),
O => \state[0]_i_3_n_0\
);
\state[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => timer_cntr_reg(10),
I1 => timer_cntr_reg(11),
I2 => timer_cntr_reg(8),
I3 => timer_cntr_reg(9),
I4 => \state[0]_i_5_n_0\,
O => \state[0]_i_4_n_0\
);
\state[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => timer_cntr_reg(15),
I1 => timer_cntr_reg(14),
I2 => timer_cntr_reg(13),
I3 => timer_cntr_reg(12),
O => \state[0]_i_5_n_0\
);
\state[0]_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^den_a\,
I1 => overlap_A_reg,
O => \state_reg[0]_0\
);
\state[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7A"
)
port map (
I0 => state(0),
I1 => drdy_i,
I2 => state(1),
O => \state[1]_i_1_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDPE
port map (
C => s_axi_aclk,
CE => '1',
D => \state[0]_i_1_n_0\,
PRE => reset,
Q => state(0)
);
\state_reg[1]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => '1',
CLR => reset,
D => \state[1]_i_1_n_0\,
Q => state(1)
);
\temp_out[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => drdy_i,
I1 => state(0),
I2 => state(1),
O => \temp_out[11]_i_1_n_0\
);
\temp_out_reg[0]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \temp_out[11]_i_1_n_0\,
CLR => reset,
D => D(0),
Q => temp_out(0)
);
\temp_out_reg[10]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \temp_out[11]_i_1_n_0\,
CLR => reset,
D => D(10),
Q => temp_out(10)
);
\temp_out_reg[11]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \temp_out[11]_i_1_n_0\,
CLR => reset,
D => D(11),
Q => temp_out(11)
);
\temp_out_reg[1]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \temp_out[11]_i_1_n_0\,
CLR => reset,
D => D(1),
Q => temp_out(1)
);
\temp_out_reg[2]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \temp_out[11]_i_1_n_0\,
CLR => reset,
D => D(2),
Q => temp_out(2)
);
\temp_out_reg[3]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \temp_out[11]_i_1_n_0\,
CLR => reset,
D => D(3),
Q => temp_out(3)
);
\temp_out_reg[4]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \temp_out[11]_i_1_n_0\,
CLR => reset,
D => D(4),
Q => temp_out(4)
);
\temp_out_reg[5]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \temp_out[11]_i_1_n_0\,
CLR => reset,
D => D(5),
Q => temp_out(5)
);
\temp_out_reg[6]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \temp_out[11]_i_1_n_0\,
CLR => reset,
D => D(6),
Q => temp_out(6)
);
\temp_out_reg[7]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \temp_out[11]_i_1_n_0\,
CLR => reset,
D => D(7),
Q => temp_out(7)
);
\temp_out_reg[8]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \temp_out[11]_i_1_n_0\,
CLR => reset,
D => D(8),
Q => temp_out(8)
);
\temp_out_reg[9]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => \temp_out[11]_i_1_n_0\,
CLR => reset,
D => D(9),
Q => temp_out(9)
);
\timer_cntr[0]_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => timer_cntr_reg(0),
I1 => timer_cntr_reg(1),
I2 => timer_cntr_reg(2),
O => \timer_cntr[0]_i_10_n_0\
);
\timer_cntr[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCDCCCCC"
)
port map (
I0 => \state[0]_i_4_n_0\,
I1 => timer_cntr_reg(3),
I2 => \timer_cntr[0]_i_10_n_0\,
I3 => \state[0]_i_3_n_0\,
I4 => Q(3),
O => \timer_cntr[0]_i_2_n_0\
);
\timer_cntr[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAABAAAAAAA8AA"
)
port map (
I0 => timer_cntr_reg(2),
I1 => \state[0]_i_4_n_0\,
I2 => timer_cntr_reg(3),
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => \state[0]_i_3_n_0\,
I5 => Q(2),
O => \timer_cntr[0]_i_3_n_0\
);
\timer_cntr[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAABAAAAAAA8AA"
)
port map (
I0 => timer_cntr_reg(1),
I1 => \state[0]_i_4_n_0\,
I2 => timer_cntr_reg(3),
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => \state[0]_i_3_n_0\,
I5 => Q(1),
O => \timer_cntr[0]_i_4_n_0\
);
\timer_cntr[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAABAAAAAAA8AA"
)
port map (
I0 => timer_cntr_reg(0),
I1 => \state[0]_i_4_n_0\,
I2 => timer_cntr_reg(3),
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => \state[0]_i_3_n_0\,
I5 => Q(0),
O => \timer_cntr[0]_i_5_n_0\
);
\timer_cntr[0]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"00FF00EF"
)
port map (
I0 => Q(3),
I1 => \state[0]_i_3_n_0\,
I2 => \timer_cntr[0]_i_10_n_0\,
I3 => timer_cntr_reg(3),
I4 => \state[0]_i_4_n_0\,
O => \timer_cntr[0]_i_6_n_0\
);
\timer_cntr[0]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"3333333333333A33"
)
port map (
I0 => Q(2),
I1 => timer_cntr_reg(2),
I2 => \state[0]_i_3_n_0\,
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => timer_cntr_reg(3),
I5 => \state[0]_i_4_n_0\,
O => \timer_cntr[0]_i_7_n_0\
);
\timer_cntr[0]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"3333333333333A33"
)
port map (
I0 => Q(1),
I1 => timer_cntr_reg(1),
I2 => \state[0]_i_3_n_0\,
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => timer_cntr_reg(3),
I5 => \state[0]_i_4_n_0\,
O => \timer_cntr[0]_i_8_n_0\
);
\timer_cntr[0]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"3333333333333A33"
)
port map (
I0 => Q(0),
I1 => timer_cntr_reg(0),
I2 => \state[0]_i_3_n_0\,
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => timer_cntr_reg(3),
I5 => \state[0]_i_4_n_0\,
O => \timer_cntr[0]_i_9_n_0\
);
\timer_cntr[12]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAABAAAAAAA8AA"
)
port map (
I0 => timer_cntr_reg(14),
I1 => \state[0]_i_4_n_0\,
I2 => timer_cntr_reg(3),
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => \state[0]_i_3_n_0\,
I5 => Q(14),
O => \timer_cntr[12]_i_2_n_0\
);
\timer_cntr[12]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAABAAAAAAAAAA"
)
port map (
I0 => timer_cntr_reg(13),
I1 => \state[0]_i_4_n_0\,
I2 => timer_cntr_reg(3),
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => \state[0]_i_3_n_0\,
I5 => Q(13),
O => \timer_cntr[12]_i_3_n_0\
);
\timer_cntr[12]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAABAAAAAAA8AA"
)
port map (
I0 => timer_cntr_reg(12),
I1 => \state[0]_i_4_n_0\,
I2 => timer_cntr_reg(3),
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => \state[0]_i_3_n_0\,
I5 => Q(12),
O => \timer_cntr[12]_i_4_n_0\
);
\timer_cntr[12]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFFFEF"
)
port map (
I0 => \state[0]_i_4_n_0\,
I1 => timer_cntr_reg(3),
I2 => \timer_cntr[0]_i_10_n_0\,
I3 => \state[0]_i_3_n_0\,
I4 => Q(15),
I5 => timer_cntr_reg(15),
O => \timer_cntr[12]_i_5_n_0\
);
\timer_cntr[12]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"3333333333333A33"
)
port map (
I0 => Q(14),
I1 => timer_cntr_reg(14),
I2 => \state[0]_i_3_n_0\,
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => timer_cntr_reg(3),
I5 => \state[0]_i_4_n_0\,
O => \timer_cntr[12]_i_6_n_0\
);
\timer_cntr[12]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"3333333333333E33"
)
port map (
I0 => Q(13),
I1 => timer_cntr_reg(13),
I2 => \state[0]_i_3_n_0\,
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => timer_cntr_reg(3),
I5 => \state[0]_i_4_n_0\,
O => \timer_cntr[12]_i_7_n_0\
);
\timer_cntr[12]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"3333333333333A33"
)
port map (
I0 => Q(12),
I1 => timer_cntr_reg(12),
I2 => \state[0]_i_3_n_0\,
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => timer_cntr_reg(3),
I5 => \state[0]_i_4_n_0\,
O => \timer_cntr[12]_i_8_n_0\
);
\timer_cntr[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAABAAAAAAA8AA"
)
port map (
I0 => timer_cntr_reg(7),
I1 => \state[0]_i_4_n_0\,
I2 => timer_cntr_reg(3),
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => \state[0]_i_3_n_0\,
I5 => Q(7),
O => \timer_cntr[4]_i_2_n_0\
);
\timer_cntr[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAABAAAAAAA8AA"
)
port map (
I0 => timer_cntr_reg(6),
I1 => \state[0]_i_4_n_0\,
I2 => timer_cntr_reg(3),
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => \state[0]_i_3_n_0\,
I5 => Q(6),
O => \timer_cntr[4]_i_3_n_0\
);
\timer_cntr[4]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAABAAAAAAA8AA"
)
port map (
I0 => timer_cntr_reg(5),
I1 => \state[0]_i_4_n_0\,
I2 => timer_cntr_reg(3),
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => \state[0]_i_3_n_0\,
I5 => Q(5),
O => \timer_cntr[4]_i_4_n_0\
);
\timer_cntr[4]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAABAAAAAAA8AA"
)
port map (
I0 => timer_cntr_reg(4),
I1 => \state[0]_i_4_n_0\,
I2 => timer_cntr_reg(3),
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => \state[0]_i_3_n_0\,
I5 => Q(4),
O => \timer_cntr[4]_i_5_n_0\
);
\timer_cntr[4]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"3333333333333A33"
)
port map (
I0 => Q(7),
I1 => timer_cntr_reg(7),
I2 => \state[0]_i_3_n_0\,
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => timer_cntr_reg(3),
I5 => \state[0]_i_4_n_0\,
O => \timer_cntr[4]_i_6_n_0\
);
\timer_cntr[4]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"3333333333333A33"
)
port map (
I0 => Q(6),
I1 => timer_cntr_reg(6),
I2 => \state[0]_i_3_n_0\,
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => timer_cntr_reg(3),
I5 => \state[0]_i_4_n_0\,
O => \timer_cntr[4]_i_7_n_0\
);
\timer_cntr[4]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"3333333333333A33"
)
port map (
I0 => Q(5),
I1 => timer_cntr_reg(5),
I2 => \state[0]_i_3_n_0\,
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => timer_cntr_reg(3),
I5 => \state[0]_i_4_n_0\,
O => \timer_cntr[4]_i_8_n_0\
);
\timer_cntr[4]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"3333333333333A33"
)
port map (
I0 => Q(4),
I1 => timer_cntr_reg(4),
I2 => \state[0]_i_3_n_0\,
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => timer_cntr_reg(3),
I5 => \state[0]_i_4_n_0\,
O => \timer_cntr[4]_i_9_n_0\
);
\timer_cntr[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAABAAAAAAA8AA"
)
port map (
I0 => timer_cntr_reg(11),
I1 => \state[0]_i_4_n_0\,
I2 => timer_cntr_reg(3),
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => \state[0]_i_3_n_0\,
I5 => Q(11),
O => \timer_cntr[8]_i_2_n_0\
);
\timer_cntr[8]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAABAAAAAAA8AA"
)
port map (
I0 => timer_cntr_reg(10),
I1 => \state[0]_i_4_n_0\,
I2 => timer_cntr_reg(3),
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => \state[0]_i_3_n_0\,
I5 => Q(10),
O => \timer_cntr[8]_i_3_n_0\
);
\timer_cntr[8]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAABAAAAAAAAAA"
)
port map (
I0 => timer_cntr_reg(9),
I1 => \state[0]_i_4_n_0\,
I2 => timer_cntr_reg(3),
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => \state[0]_i_3_n_0\,
I5 => Q(9),
O => \timer_cntr[8]_i_4_n_0\
);
\timer_cntr[8]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAABAAAAAAAAAA"
)
port map (
I0 => timer_cntr_reg(8),
I1 => \state[0]_i_4_n_0\,
I2 => timer_cntr_reg(3),
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => \state[0]_i_3_n_0\,
I5 => Q(8),
O => \timer_cntr[8]_i_5_n_0\
);
\timer_cntr[8]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"3333333333333A33"
)
port map (
I0 => Q(11),
I1 => timer_cntr_reg(11),
I2 => \state[0]_i_3_n_0\,
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => timer_cntr_reg(3),
I5 => \state[0]_i_4_n_0\,
O => \timer_cntr[8]_i_6_n_0\
);
\timer_cntr[8]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"3333333333333A33"
)
port map (
I0 => Q(10),
I1 => timer_cntr_reg(10),
I2 => \state[0]_i_3_n_0\,
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => timer_cntr_reg(3),
I5 => \state[0]_i_4_n_0\,
O => \timer_cntr[8]_i_7_n_0\
);
\timer_cntr[8]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"3333333333333E33"
)
port map (
I0 => Q(9),
I1 => timer_cntr_reg(9),
I2 => \state[0]_i_3_n_0\,
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => timer_cntr_reg(3),
I5 => \state[0]_i_4_n_0\,
O => \timer_cntr[8]_i_8_n_0\
);
\timer_cntr[8]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"3333333333333E33"
)
port map (
I0 => Q(8),
I1 => timer_cntr_reg(8),
I2 => \state[0]_i_3_n_0\,
I3 => \timer_cntr[0]_i_10_n_0\,
I4 => timer_cntr_reg(3),
I5 => \state[0]_i_4_n_0\,
O => \timer_cntr[8]_i_9_n_0\
);
\timer_cntr_reg[0]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => '1',
CLR => reset,
D => \timer_cntr_reg[0]_i_1_n_7\,
Q => timer_cntr_reg(0)
);
\timer_cntr_reg[0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \timer_cntr_reg[0]_i_1_n_0\,
CO(2) => \timer_cntr_reg[0]_i_1_n_1\,
CO(1) => \timer_cntr_reg[0]_i_1_n_2\,
CO(0) => \timer_cntr_reg[0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \timer_cntr[0]_i_2_n_0\,
DI(2) => \timer_cntr[0]_i_3_n_0\,
DI(1) => \timer_cntr[0]_i_4_n_0\,
DI(0) => \timer_cntr[0]_i_5_n_0\,
O(3) => \timer_cntr_reg[0]_i_1_n_4\,
O(2) => \timer_cntr_reg[0]_i_1_n_5\,
O(1) => \timer_cntr_reg[0]_i_1_n_6\,
O(0) => \timer_cntr_reg[0]_i_1_n_7\,
S(3) => \timer_cntr[0]_i_6_n_0\,
S(2) => \timer_cntr[0]_i_7_n_0\,
S(1) => \timer_cntr[0]_i_8_n_0\,
S(0) => \timer_cntr[0]_i_9_n_0\
);
\timer_cntr_reg[10]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => '1',
CLR => reset,
D => \timer_cntr_reg[8]_i_1_n_5\,
Q => timer_cntr_reg(10)
);
\timer_cntr_reg[11]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => '1',
CLR => reset,
D => \timer_cntr_reg[8]_i_1_n_4\,
Q => timer_cntr_reg(11)
);
\timer_cntr_reg[12]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => '1',
CLR => reset,
D => \timer_cntr_reg[12]_i_1_n_7\,
Q => timer_cntr_reg(12)
);
\timer_cntr_reg[12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \timer_cntr_reg[8]_i_1_n_0\,
CO(3) => \NLW_timer_cntr_reg[12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \timer_cntr_reg[12]_i_1_n_1\,
CO(1) => \timer_cntr_reg[12]_i_1_n_2\,
CO(0) => \timer_cntr_reg[12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \timer_cntr[12]_i_2_n_0\,
DI(1) => \timer_cntr[12]_i_3_n_0\,
DI(0) => \timer_cntr[12]_i_4_n_0\,
O(3) => \timer_cntr_reg[12]_i_1_n_4\,
O(2) => \timer_cntr_reg[12]_i_1_n_5\,
O(1) => \timer_cntr_reg[12]_i_1_n_6\,
O(0) => \timer_cntr_reg[12]_i_1_n_7\,
S(3) => \timer_cntr[12]_i_5_n_0\,
S(2) => \timer_cntr[12]_i_6_n_0\,
S(1) => \timer_cntr[12]_i_7_n_0\,
S(0) => \timer_cntr[12]_i_8_n_0\
);
\timer_cntr_reg[13]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => '1',
CLR => reset,
D => \timer_cntr_reg[12]_i_1_n_6\,
Q => timer_cntr_reg(13)
);
\timer_cntr_reg[14]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => '1',
CLR => reset,
D => \timer_cntr_reg[12]_i_1_n_5\,
Q => timer_cntr_reg(14)
);
\timer_cntr_reg[15]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => '1',
CLR => reset,
D => \timer_cntr_reg[12]_i_1_n_4\,
Q => timer_cntr_reg(15)
);
\timer_cntr_reg[1]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => '1',
CLR => reset,
D => \timer_cntr_reg[0]_i_1_n_6\,
Q => timer_cntr_reg(1)
);
\timer_cntr_reg[2]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => '1',
CLR => reset,
D => \timer_cntr_reg[0]_i_1_n_5\,
Q => timer_cntr_reg(2)
);
\timer_cntr_reg[3]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => '1',
CLR => reset,
D => \timer_cntr_reg[0]_i_1_n_4\,
Q => timer_cntr_reg(3)
);
\timer_cntr_reg[4]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => '1',
CLR => reset,
D => \timer_cntr_reg[4]_i_1_n_7\,
Q => timer_cntr_reg(4)
);
\timer_cntr_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \timer_cntr_reg[0]_i_1_n_0\,
CO(3) => \timer_cntr_reg[4]_i_1_n_0\,
CO(2) => \timer_cntr_reg[4]_i_1_n_1\,
CO(1) => \timer_cntr_reg[4]_i_1_n_2\,
CO(0) => \timer_cntr_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \timer_cntr[4]_i_2_n_0\,
DI(2) => \timer_cntr[4]_i_3_n_0\,
DI(1) => \timer_cntr[4]_i_4_n_0\,
DI(0) => \timer_cntr[4]_i_5_n_0\,
O(3) => \timer_cntr_reg[4]_i_1_n_4\,
O(2) => \timer_cntr_reg[4]_i_1_n_5\,
O(1) => \timer_cntr_reg[4]_i_1_n_6\,
O(0) => \timer_cntr_reg[4]_i_1_n_7\,
S(3) => \timer_cntr[4]_i_6_n_0\,
S(2) => \timer_cntr[4]_i_7_n_0\,
S(1) => \timer_cntr[4]_i_8_n_0\,
S(0) => \timer_cntr[4]_i_9_n_0\
);
\timer_cntr_reg[5]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => '1',
CLR => reset,
D => \timer_cntr_reg[4]_i_1_n_6\,
Q => timer_cntr_reg(5)
);
\timer_cntr_reg[6]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => '1',
CLR => reset,
D => \timer_cntr_reg[4]_i_1_n_5\,
Q => timer_cntr_reg(6)
);
\timer_cntr_reg[7]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => '1',
CLR => reset,
D => \timer_cntr_reg[4]_i_1_n_4\,
Q => timer_cntr_reg(7)
);
\timer_cntr_reg[8]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => '1',
CLR => reset,
D => \timer_cntr_reg[8]_i_1_n_7\,
Q => timer_cntr_reg(8)
);
\timer_cntr_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \timer_cntr_reg[4]_i_1_n_0\,
CO(3) => \timer_cntr_reg[8]_i_1_n_0\,
CO(2) => \timer_cntr_reg[8]_i_1_n_1\,
CO(1) => \timer_cntr_reg[8]_i_1_n_2\,
CO(0) => \timer_cntr_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \timer_cntr[8]_i_2_n_0\,
DI(2) => \timer_cntr[8]_i_3_n_0\,
DI(1) => \timer_cntr[8]_i_4_n_0\,
DI(0) => \timer_cntr[8]_i_5_n_0\,
O(3) => \timer_cntr_reg[8]_i_1_n_4\,
O(2) => \timer_cntr_reg[8]_i_1_n_5\,
O(1) => \timer_cntr_reg[8]_i_1_n_6\,
O(0) => \timer_cntr_reg[8]_i_1_n_7\,
S(3) => \timer_cntr[8]_i_6_n_0\,
S(2) => \timer_cntr[8]_i_7_n_0\,
S(1) => \timer_cntr[8]_i_8_n_0\,
S(0) => \timer_cntr[8]_i_9_n_0\
);
\timer_cntr_reg[9]\: unisim.vcomponents.FDCE
port map (
C => s_axi_aclk,
CE => '1',
CLR => reset,
D => \timer_cntr_reg[8]_i_1_n_6\,
Q => timer_cntr_reg(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xadc_wiz_0_0_system_xadc_wiz_0_0_slave_attachment is
port (
dwe_d1_reg : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
hard_macro_rst_reg_reg : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
dwe_d1_reg_0 : out STD_LOGIC;
dwe_C_reg_reg : out STD_LOGIC;
bus2ip_wrce : out STD_LOGIC_VECTOR ( 0 to 0 );
rst_ip2bus_rdack0 : out STD_LOGIC;
bus2ip_rdce : out STD_LOGIC_VECTOR ( 2 downto 0 );
D : out STD_LOGIC_VECTOR ( 18 downto 0 );
status_reg_rdack0 : out STD_LOGIC;
Intr2Bus_RdAck0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[16].GEN_REG_STATUS.ip_irpt_status_reg_reg[16]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
local_reg_wrack0 : out STD_LOGIC;
local_reg_rdack0 : out STD_LOGIC;
local_rdce_or_reduce : out STD_LOGIC;
ip2bus_wrack_int1 : out STD_LOGIC;
\INTR_CTRLR_GEN_I.ip2bus_wrack_reg\ : out STD_LOGIC;
reset_trig0 : out STD_LOGIC;
sw_rst_cond : out STD_LOGIC;
p_3_out : out STD_LOGIC;
p_5_out : out STD_LOGIC;
dummy_bus2ip_rdce_intr : out STD_LOGIC;
dummy_local_reg_wrack0 : out STD_LOGIC;
dummy_local_reg_rdack0 : out STD_LOGIC;
dummy_local_reg_rdack_d10 : out STD_LOGIC;
hard_macro_rst_reg_reg_0 : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
local_reg_wrack_d1_reg : out STD_LOGIC;
\temp_rd_wait_cycle_reg_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_d1_reg\ : out STD_LOGIC;
dummy_local_reg_wrack_d1_reg : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 18 downto 0 );
s_axi_aclk : in STD_LOGIC;
ip2bus_error : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack : in STD_LOGIC;
ip2bus_wrack : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
jtaglocked_i : in STD_LOGIC;
rst_ip2bus_rdack_d1 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 16 downto 0 );
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ : in STD_LOGIC;
\status_reg_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
\alarm_reg_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\do_reg_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
p_1_in44_in : in STD_LOGIC;
p_1_in41_in : in STD_LOGIC;
p_1_in38_in : in STD_LOGIC;
p_1_in35_in : in STD_LOGIC;
p_1_in32_in : in STD_LOGIC;
p_1_in29_in : in STD_LOGIC;
p_1_in26_in : in STD_LOGIC;
p_1_in23_in : in STD_LOGIC;
p_1_in20_in : in STD_LOGIC;
p_1_in17_in : in STD_LOGIC;
status_reg_rdack_d1 : in STD_LOGIC;
p_1_in14_in : in STD_LOGIC;
p_1_in11_in : in STD_LOGIC;
p_1_in8_in : in STD_LOGIC;
p_1_in5_in : in STD_LOGIC;
p_1_in2_in : in STD_LOGIC;
p_1_in : in STD_LOGIC;
jtagmodified_i : in STD_LOGIC;
jtagmodified_d1 : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
ipif_glbl_irpt_enable_reg : in STD_LOGIC;
irpt_rdack_d1 : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
local_reg_wrack_d1 : in STD_LOGIC;
local_reg_rdack_d1 : in STD_LOGIC;
intr_ip2bus_wrack : in STD_LOGIC;
wrack : in STD_LOGIC;
dummy_local_reg_wrack : in STD_LOGIC;
dummy_intr_reg_wrack : in STD_LOGIC;
local_reg_wrack_reg : in STD_LOGIC;
\s_axi_wdata_1__s_port_]\ : in STD_LOGIC;
sw_rst_cond_d1 : in STD_LOGIC;
dummy_intr_reg_wrack_d1 : in STD_LOGIC;
dummy_intr_reg_rdack_d1 : in STD_LOGIC;
dummy_local_reg_wrack_d1 : in STD_LOGIC;
dummy_local_reg_rdack_d1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 1 downto 0 );
hard_macro_rst_reg : in STD_LOGIC;
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[0]\ : in STD_LOGIC_VECTOR ( 18 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xadc_wiz_0_0_system_xadc_wiz_0_0_slave_attachment : entity is "system_xadc_wiz_0_0_slave_attachment";
end system_xadc_wiz_0_0_system_xadc_wiz_0_0_slave_attachment;
architecture STRUCTURE of system_xadc_wiz_0_0_system_xadc_wiz_0_0_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt[6]_i_3_n_0\ : STD_LOGIC;
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_2_out : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 6 downto 0 );
signal rst_i_1_n_0 : STD_LOGIC;
signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \s_axi_bresp_i[1]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal s_axi_rdata_i : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i0 : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \s_axi_wdata_1__s_net_1\ : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state[0]_i_1_n_0\ : STD_LOGIC;
signal \state[0]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal timeout : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[4]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[6]_i_3\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of s_axi_arready_INST_0 : label is "soft_lutpair29";
attribute SOFT_HLUTNM of s_axi_wready_INST_0 : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \state[0]_i_2\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair29";
begin
SR(0) <= \^sr\(0);
s_axi_bresp(0) <= \^s_axi_bresp\(0);
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
\s_axi_wdata_1__s_net_1\ <= \s_axi_wdata_1__s_port_]\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\,
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2]\,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\,
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[3]\,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2]\,
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2]\,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\,
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[3]\,
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[4]\,
O => plusOp(4)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[5]\,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2]\,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\,
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[3]\,
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[4]\,
O => plusOp(5)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(0),
I1 => state(1),
O => p_2_out
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[6]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => timeout,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt[6]_i_3_n_0\,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[5]\,
O => plusOp(6)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[6]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[4]\,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[3]\,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\,
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2]\,
O => \INCLUDE_DPHASE_TIMER.dpto_cnt[6]_i_3_n_0\
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
R => p_2_out
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\,
R => p_2_out
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2]\,
R => p_2_out
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[3]\,
R => p_2_out
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(4),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[4]\,
R => p_2_out
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(5),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[5]\,
R => p_2_out
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(6),
Q => timeout,
R => p_2_out
);
I_DECODER: entity work.system_xadc_wiz_0_0_system_xadc_wiz_0_0_address_decoder
port map (
D(18 downto 0) => D(18 downto 0),
E(0) => E(0),
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\,
\GEN_IP_IRPT_STATUS_REG[16].GEN_REG_STATUS.ip_irpt_status_reg_reg[16]\ => \GEN_IP_IRPT_STATUS_REG[16].GEN_REG_STATUS.ip_irpt_status_reg_reg[16]\,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[6]\(0) => timeout,
\INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_d1_reg\ => \INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_d1_reg\,
\INTR_CTRLR_GEN_I.ip2bus_wrack_reg\ => \INTR_CTRLR_GEN_I.ip2bus_wrack_reg\,
Intr2Bus_RdAck0 => Intr2Bus_RdAck0,
Q(1 downto 0) => state(1 downto 0),
\alarm_reg_reg[8]\(8 downto 0) => \alarm_reg_reg[8]\(8 downto 0),
bus2ip_rdce(2 downto 0) => bus2ip_rdce(2 downto 0),
bus2ip_wrce(0) => bus2ip_wrce(0),
\do_reg_reg[15]\(15 downto 0) => \do_reg_reg[15]\(15 downto 0),
dummy_bus2ip_rdce_intr => dummy_bus2ip_rdce_intr,
dummy_intr_reg_rdack_d1 => dummy_intr_reg_rdack_d1,
dummy_intr_reg_wrack => dummy_intr_reg_wrack,
dummy_intr_reg_wrack_d1 => dummy_intr_reg_wrack_d1,
dummy_local_reg_rdack0 => dummy_local_reg_rdack0,
dummy_local_reg_rdack_d1 => dummy_local_reg_rdack_d1,
dummy_local_reg_rdack_d10 => dummy_local_reg_rdack_d10,
dummy_local_reg_wrack => dummy_local_reg_wrack,
dummy_local_reg_wrack0 => dummy_local_reg_wrack0,
dummy_local_reg_wrack_d1 => dummy_local_reg_wrack_d1,
dummy_local_reg_wrack_d1_reg => dummy_local_reg_wrack_d1_reg,
dwe_C_reg_reg => dwe_C_reg_reg,
dwe_d1_reg => dwe_d1_reg,
dwe_d1_reg_0 => dwe_d1_reg_0,
hard_macro_rst_reg => hard_macro_rst_reg,
hard_macro_rst_reg_reg => hard_macro_rst_reg_reg,
hard_macro_rst_reg_reg_0 => hard_macro_rst_reg_reg_0,
interrupt_wrce_strb => interrupt_wrce_strb,
intr_ip2bus_wrack => intr_ip2bus_wrack,
ip2bus_rdack => ip2bus_rdack,
ip2bus_wrack => ip2bus_wrack,
ip2bus_wrack_int1 => ip2bus_wrack_int1,
\ip_irpt_enable_reg_reg[16]\(16 downto 0) => Q(16 downto 0),
ipif_glbl_irpt_enable_reg => ipif_glbl_irpt_enable_reg,
ipif_glbl_irpt_enable_reg_reg => ipif_glbl_irpt_enable_reg_reg,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
jtaglocked_i => jtaglocked_i,
jtagmodified_d1 => jtagmodified_d1,
jtagmodified_i => jtagmodified_i,
local_rdce_or_reduce => local_rdce_or_reduce,
local_reg_rdack0 => local_reg_rdack0,
local_reg_rdack_d1 => local_reg_rdack_d1,
local_reg_wrack0 => local_reg_wrack0,
local_reg_wrack_d1 => local_reg_wrack_d1,
local_reg_wrack_d1_reg => local_reg_wrack_d1_reg,
local_reg_wrack_reg => local_reg_wrack_reg,
p_1_in => p_1_in,
p_1_in11_in => p_1_in11_in,
p_1_in14_in => p_1_in14_in,
p_1_in17_in => p_1_in17_in,
p_1_in20_in => p_1_in20_in,
p_1_in23_in => p_1_in23_in,
p_1_in26_in => p_1_in26_in,
p_1_in29_in => p_1_in29_in,
p_1_in2_in => p_1_in2_in,
p_1_in32_in => p_1_in32_in,
p_1_in35_in => p_1_in35_in,
p_1_in38_in => p_1_in38_in,
p_1_in41_in => p_1_in41_in,
p_1_in44_in => p_1_in44_in,
p_1_in5_in => p_1_in5_in,
p_1_in8_in => p_1_in8_in,
p_3_out => p_3_out,
p_5_out => p_5_out,
reset_trig0 => reset_trig0,
rst_ip2bus_rdack0 => rst_ip2bus_rdack0,
rst_ip2bus_rdack_d1 => rst_ip2bus_rdack_d1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(7 downto 0) => s_axi_araddr(7 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(7 downto 0) => s_axi_awaddr(7 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_wdata(1 downto 0) => s_axi_wdata(1 downto 0),
\s_axi_wdata_1__s_port_]\ => \s_axi_wdata_1__s_net_1\,
s_axi_wstrb(0) => s_axi_wstrb(0),
s_axi_wvalid => s_axi_wvalid,
status_reg_rdack0 => status_reg_rdack0,
status_reg_rdack_d1 => status_reg_rdack_d1,
\status_reg_reg[10]\(10 downto 0) => \status_reg_reg[10]\(10 downto 0),
sw_rst_cond => sw_rst_cond,
sw_rst_cond_d1 => sw_rst_cond_d1,
\temp_rd_wait_cycle_reg_reg[0]\(0) => \temp_rd_wait_cycle_reg_reg[0]\(0),
wrack => wrack
);
rst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => rst_i_1_n_0
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rst_i_1_n_0,
Q => \^sr\(0),
R => '0'
);
s_axi_arready_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => timeout,
I1 => ip2bus_rdack,
O => s_axi_arready
);
\s_axi_bresp_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => ip2bus_error,
I1 => state(1),
I2 => state(0),
I3 => \^s_axi_bresp\(0),
O => \s_axi_bresp_i[1]_i_1_n_0\
);
\s_axi_bresp_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \s_axi_bresp_i[1]_i_1_n_0\,
Q => \^s_axi_bresp\(0),
R => \^sr\(0)
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"5D5D5D550C0C0C00"
)
port map (
I0 => s_axi_bready,
I1 => state(1),
I2 => state(0),
I3 => timeout,
I4 => ip2bus_wrack,
I5 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => \^sr\(0)
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => s_axi_rdata_i
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[0]\(0),
Q => s_axi_rdata(0),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[0]\(10),
Q => s_axi_rdata(10),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[0]\(11),
Q => s_axi_rdata(11),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[0]\(12),
Q => s_axi_rdata(12),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[0]\(13),
Q => s_axi_rdata(13),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[0]\(14),
Q => s_axi_rdata(14),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[0]\(15),
Q => s_axi_rdata(15),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[0]\(16),
Q => s_axi_rdata(16),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[0]\(17),
Q => s_axi_rdata(17),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[0]\(1),
Q => s_axi_rdata(1),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[0]\(2),
Q => s_axi_rdata(2),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[0]\(18),
Q => s_axi_rdata(18),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[0]\(3),
Q => s_axi_rdata(3),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[0]\(4),
Q => s_axi_rdata(4),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[0]\(5),
Q => s_axi_rdata(5),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[0]\(6),
Q => s_axi_rdata(6),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[0]\(7),
Q => s_axi_rdata(7),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[0]\(8),
Q => s_axi_rdata(8),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[0]\(9),
Q => s_axi_rdata(9),
R => \^sr\(0)
);
\s_axi_rresp_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => ip2bus_error,
Q => s_axi_rresp(0),
R => \^sr\(0)
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"5D5D5D550C0C0C00"
)
port map (
I0 => s_axi_rready,
I1 => state(0),
I2 => state(1),
I3 => timeout,
I4 => ip2bus_rdack,
I5 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => \^sr\(0)
);
s_axi_wready_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => timeout,
I1 => ip2bus_wrack,
O => s_axi_wready
);
\state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00707070"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => state(0),
I3 => \^s_axi_rvalid\,
I4 => s_axi_rready,
I5 => \state[0]_i_2_n_0\,
O => \state[0]_i_1_n_0\
);
\state[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0F0FEFE0"
)
port map (
I0 => timeout,
I1 => ip2bus_wrack,
I2 => state(1),
I3 => s_axi_arvalid,
I4 => state(0),
O => \state[0]_i_2_n_0\
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00707070"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => state(1),
I3 => \^s_axi_bvalid\,
I4 => s_axi_bready,
I5 => \state[1]_i_2_n_0\,
O => \state[1]_i_1_n_0\
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAFFAAFFAAAAAAEA"
)
port map (
I0 => s_axi_rvalid_i0,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(0),
I4 => s_axi_arvalid,
I5 => state(1),
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0E00"
)
port map (
I0 => ip2bus_rdack,
I1 => timeout,
I2 => state(1),
I3 => state(0),
O => s_axi_rvalid_i0
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \state[0]_i_1_n_0\,
Q => state(0),
R => \^sr\(0)
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \state[1]_i_1_n_0\,
Q => state(1),
R => \^sr\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xadc_wiz_0_0_system_xadc_wiz_0_0_xadc_core_drp is
port (
D : out STD_LOGIC_VECTOR ( 6 downto 0 );
eoc_out : out STD_LOGIC;
eos_out : out STD_LOGIC;
jtagmodified_i : out STD_LOGIC;
\alarm_reg_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
local_reg_wrack_d1 : out STD_LOGIC;
local_reg_rdack_d1 : out STD_LOGIC;
status_reg_rdack_d1 : out STD_LOGIC;
jtagmodified_d1 : out STD_LOGIC;
hard_macro_rst_reg : out STD_LOGIC;
ip2bus_error_int1 : out STD_LOGIC;
\INTR_CTRLR_GEN_I.ip2bus_wrack_reg\ : out STD_LOGIC;
ip2bus_rdack_int1 : out STD_LOGIC;
\DO_IRPT_INPUT[9].GEN_POS_EDGE_DETECT.irpt_dly1_reg\ : out STD_LOGIC;
\DO_IRPT_INPUT[8].GEN_POS_EDGE_DETECT.irpt_dly1_reg\ : out STD_LOGIC;
temp_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
Q : out STD_LOGIC_VECTOR ( 8 downto 0 );
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[16]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[21]\ : out STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_aclk : in STD_LOGIC;
reset : in STD_LOGIC;
vn_in : in STD_LOGIC;
vp_in : in STD_LOGIC;
VAUXN : in STD_LOGIC_VECTOR ( 12 downto 0 );
VAUXP : in STD_LOGIC_VECTOR ( 12 downto 0 );
reset2ip_reset : in STD_LOGIC;
Bus_RNW_reg_reg : in STD_LOGIC;
local_reg_wrack0 : in STD_LOGIC;
bus2ip_wrce : in STD_LOGIC_VECTOR ( 0 to 0 );
local_rdce_or_reduce : in STD_LOGIC;
local_reg_rdack0 : in STD_LOGIC;
bus2ip_rdce : in STD_LOGIC_VECTOR ( 1 downto 0 );
status_reg_rdack0 : in STD_LOGIC;
Bus_RNW_reg_reg_0 : in STD_LOGIC;
Bus_RNW_reg_reg_1 : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]_0\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 17 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
\s_axi_wstrb[2]\ : in STD_LOGIC;
dummy_intr_reg_rdack : in STD_LOGIC;
dummy_local_reg_rdack : in STD_LOGIC;
intr_ip2bus_rdack : in STD_LOGIC;
rst_ip2bus_rdack : in STD_LOGIC;
\RESET_FLOPS[15].RST_FLOPS\ : in STD_LOGIC;
bus2ip_reset_active_high : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xadc_wiz_0_0_system_xadc_wiz_0_0_xadc_core_drp : entity is "system_xadc_wiz_0_0_xadc_core_drp";
end system_xadc_wiz_0_0_system_xadc_wiz_0_0_xadc_core_drp;
architecture STRUCTURE of system_xadc_wiz_0_0_system_xadc_wiz_0_0_xadc_core_drp is
signal \^d\ : STD_LOGIC_VECTOR ( 6 downto 0 );
signal \INTR_CTRLR_GEN_I.ip2bus_error_i_4_n_0\ : STD_LOGIC;
signal Inst_drp_arbiter_n_2 : STD_LOGIC;
signal Inst_drp_arbiter_n_3 : STD_LOGIC;
signal Inst_drp_arbiter_n_5 : STD_LOGIC;
signal Inst_drp_arbiter_n_6 : STD_LOGIC;
signal Inst_drp_arbiter_n_7 : STD_LOGIC;
signal Inst_drp_arbiter_n_8 : STD_LOGIC;
signal XADC_INST_n_34 : STD_LOGIC;
signal alarm_0_d1 : STD_LOGIC;
signal \^alarm_reg_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal bbusy_A : STD_LOGIC;
signal daddr_C : STD_LOGIC_VECTOR ( 6 downto 0 );
signal den_A : STD_LOGIC;
signal den_C : STD_LOGIC;
signal den_d1 : STD_LOGIC;
signal den_d1_i_1_n_0 : STD_LOGIC;
signal di_C : STD_LOGIC_VECTOR ( 15 downto 0 );
signal do_A_reg : STD_LOGIC_VECTOR ( 15 downto 4 );
signal do_B_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
signal do_C : STD_LOGIC_VECTOR ( 15 downto 0 );
signal drdy_C : STD_LOGIC;
signal drdy_i : STD_LOGIC;
signal drdy_rd_ack_i : STD_LOGIC;
signal drdy_rd_ack_i_d1 : STD_LOGIC;
signal drdy_rd_ack_i_d2 : STD_LOGIC;
signal drdy_wr_ack_i : STD_LOGIC;
signal drdy_wr_ack_i_d1 : STD_LOGIC;
signal drdy_wr_ack_i_d2 : STD_LOGIC;
signal dwe_C : STD_LOGIC;
signal dwe_d1 : STD_LOGIC;
signal eoc_d1 : STD_LOGIC;
signal eoc_d1_i_1_n_0 : STD_LOGIC;
signal \^eoc_out\ : STD_LOGIC;
signal eos_d1 : STD_LOGIC;
signal eos_d1_i_1_n_0 : STD_LOGIC;
signal \^eos_out\ : STD_LOGIC;
signal jtag_modified_info : STD_LOGIC;
signal jtagbusy_i : STD_LOGIC;
signal \^jtagmodified_d1\ : STD_LOGIC;
signal jtagmodified_d1_i_1_n_0 : STD_LOGIC;
signal \^jtagmodified_i\ : STD_LOGIC;
signal local_reg_rdack : STD_LOGIC;
signal local_reg_wrack : STD_LOGIC;
signal ot_d1 : STD_LOGIC;
signal p_4_out : STD_LOGIC_VECTOR ( 6 downto 5 );
signal status_reg_rdack : STD_LOGIC;
signal temperature_update_inst_n_2 : STD_LOGIC;
signal temperature_update_inst_n_3 : STD_LOGIC;
signal temperature_update_inst_n_4 : STD_LOGIC;
signal wait_cycle : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_XADC_INST_MUXADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN_I.ip2bus_error_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN_I.ip2bus_wrack_i_2\ : label is "soft_lutpair60";
attribute box_type : string;
attribute box_type of XADC_INST : label is "PRIMITIVE";
attribute SOFT_HLUTNM of eoc_d1_i_1 : label is "soft_lutpair61";
attribute SOFT_HLUTNM of eos_d1_i_1 : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \status_reg[5]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \status_reg[6]_i_1\ : label is "soft_lutpair62";
begin
D(6 downto 0) <= \^d\(6 downto 0);
\alarm_reg_reg[7]_0\(7 downto 0) <= \^alarm_reg_reg[7]_0\(7 downto 0);
eoc_out <= \^eoc_out\;
eos_out <= \^eos_out\;
jtagmodified_d1 <= \^jtagmodified_d1\;
jtagmodified_i <= \^jtagmodified_i\;
\DO_IRPT_INPUT[8].GEN_POS_EDGE_DETECT.irpt_dly1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => ot_d1,
I1 => \^alarm_reg_reg[7]_0\(0),
O => \DO_IRPT_INPUT[8].GEN_POS_EDGE_DETECT.irpt_dly1_reg\
);
\DO_IRPT_INPUT[9].GEN_POS_EDGE_DETECT.irpt_dly1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => alarm_0_d1,
I1 => \^alarm_reg_reg[7]_0\(1),
O => \DO_IRPT_INPUT[9].GEN_POS_EDGE_DETECT.irpt_dly1_reg\
);
\INTR_CTRLR_GEN_I.ip2bus_error_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BBBBBBBA"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
I1 => \s_axi_wstrb[2]\,
I2 => drdy_wr_ack_i,
I3 => local_reg_wrack,
I4 => \INTR_CTRLR_GEN_I.ip2bus_error_i_4_n_0\,
O => ip2bus_error_int1
);
\INTR_CTRLR_GEN_I.ip2bus_error_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => status_reg_rdack,
I1 => local_reg_rdack,
I2 => drdy_rd_ack_i,
O => \INTR_CTRLR_GEN_I.ip2bus_error_i_4_n_0\
);
\INTR_CTRLR_GEN_I.ip2bus_rdack_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \INTR_CTRLR_GEN_I.ip2bus_error_i_4_n_0\,
I1 => dummy_intr_reg_rdack,
I2 => dummy_local_reg_rdack,
I3 => intr_ip2bus_rdack,
I4 => rst_ip2bus_rdack,
O => ip2bus_rdack_int1
);
\INTR_CTRLR_GEN_I.ip2bus_wrack_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => local_reg_wrack,
I1 => drdy_wr_ack_i,
O => \INTR_CTRLR_GEN_I.ip2bus_wrack_reg\
);
Inst_drp_arbiter: entity work.system_xadc_wiz_0_0_drp_arbiter
port map (
Bus_RNW_reg => Bus_RNW_reg,
DO(15 downto 0) => do_C(15 downto 0),
\GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]\ => \GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]\,
\GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]_0\ => \GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]_0\,
Q(11 downto 0) => do_A_reg(15 downto 4),
bbusy_A => bbusy_A,
den_A => den_A,
den_C => den_C,
den_C_reg_reg_0 => \^d\(6),
den_d1 => den_d1,
den_o_reg => temperature_update_inst_n_3,
den_o_reg_0 => temperature_update_inst_n_2,
den_o_reg_1 => temperature_update_inst_n_4,
den_reg_reg_0 => Inst_drp_arbiter_n_6,
\do_reg_reg[15]\(15 downto 0) => do_B_reg(15 downto 0),
drdy_C => drdy_C,
drdy_i => drdy_i,
drdy_rd_ack_i_d1 => drdy_rd_ack_i_d1,
drdy_rd_ack_i_d2 => drdy_rd_ack_i_d2,
drdy_rd_ack_i_reg => Inst_drp_arbiter_n_8,
drdy_wr_ack_i_d1 => drdy_wr_ack_i_d1,
drdy_wr_ack_i_d2 => drdy_wr_ack_i_d2,
drdy_wr_ack_i_reg => Inst_drp_arbiter_n_7,
dwe_C => dwe_C,
dwe_d1 => dwe_d1,
overlap_A_reg_0 => Inst_drp_arbiter_n_2,
overlap_B_reg_0 => Inst_drp_arbiter_n_3,
reset => reset,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(6 downto 0) => s_axi_araddr(6 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(6 downto 0) => s_axi_awaddr(6 downto 0),
s_axi_wdata(15 downto 0) => s_axi_wdata(15 downto 0),
\state_reg[1]_0\ => Inst_drp_arbiter_n_5,
\status_reg_reg[7]\(6 downto 0) => daddr_C(6 downto 0),
\status_reg_reg[7]_0\(15 downto 0) => di_C(15 downto 0)
);
XADC_INST: unisim.vcomponents.XADC
generic map(
INIT_40 => X"0000",
INIT_41 => X"21A1",
INIT_42 => X"0400",
INIT_43 => X"0000",
INIT_44 => X"0000",
INIT_45 => X"0000",
INIT_46 => X"0000",
INIT_47 => X"0000",
INIT_48 => X"0900",
INIT_49 => X"F6F7",
INIT_4A => X"0000",
INIT_4B => X"0000",
INIT_4C => X"0000",
INIT_4D => X"0000",
INIT_4E => X"0000",
INIT_4F => X"0000",
INIT_50 => X"B5ED",
INIT_51 => X"53A0",
INIT_52 => X"A147",
INIT_53 => X"CA33",
INIT_54 => X"A93A",
INIT_55 => X"5111",
INIT_56 => X"9555",
INIT_57 => X"AE4E",
INIT_58 => X"5999",
INIT_59 => X"0000",
INIT_5A => X"0000",
INIT_5B => X"0000",
INIT_5C => X"5111",
INIT_5D => X"0000",
INIT_5E => X"0000",
INIT_5F => X"0000",
IS_CONVSTCLK_INVERTED => '0',
IS_DCLK_INVERTED => '0',
SIM_DEVICE => "7SERIES",
SIM_MONITOR_FILE => "design.txt"
)
port map (
ALM(7) => XADC_INST_n_34,
ALM(6 downto 0) => \^alarm_reg_reg[7]_0\(7 downto 1),
BUSY => \^d\(5),
CHANNEL(4 downto 0) => \^d\(4 downto 0),
CONVST => '0',
CONVSTCLK => '0',
DADDR(6 downto 0) => daddr_C(6 downto 0),
DCLK => s_axi_aclk,
DEN => den_C,
DI(15 downto 0) => di_C(15 downto 0),
DO(15 downto 0) => do_C(15 downto 0),
DRDY => drdy_C,
DWE => dwe_C,
EOC => \^eoc_out\,
EOS => \^eos_out\,
JTAGBUSY => jtagbusy_i,
JTAGLOCKED => \^d\(6),
JTAGMODIFIED => \^jtagmodified_i\,
MUXADDR(4 downto 0) => NLW_XADC_INST_MUXADDR_UNCONNECTED(4 downto 0),
OT => \^alarm_reg_reg[7]_0\(0),
RESET => reset,
VAUXN(15 downto 12) => VAUXN(12 downto 9),
VAUXN(11) => '0',
VAUXN(10 downto 9) => VAUXN(8 downto 7),
VAUXN(8) => '0',
VAUXN(7 downto 4) => VAUXN(6 downto 3),
VAUXN(3) => '0',
VAUXN(2 downto 0) => VAUXN(2 downto 0),
VAUXP(15 downto 12) => VAUXP(12 downto 9),
VAUXP(11) => '0',
VAUXP(10 downto 9) => VAUXP(8 downto 7),
VAUXP(8) => '0',
VAUXP(7 downto 4) => VAUXP(6 downto 3),
VAUXP(3) => '0',
VAUXP(2 downto 0) => VAUXP(2 downto 0),
VN => vn_in,
VP => vp_in
);
alarm_0_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^alarm_reg_reg[7]_0\(1),
Q => alarm_0_d1,
R => '0'
);
\alarm_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^alarm_reg_reg[7]_0\(0),
Q => Q(0),
R => reset2ip_reset
);
\alarm_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^alarm_reg_reg[7]_0\(1),
Q => Q(1),
R => reset2ip_reset
);
\alarm_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^alarm_reg_reg[7]_0\(2),
Q => Q(2),
R => reset2ip_reset
);
\alarm_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^alarm_reg_reg[7]_0\(3),
Q => Q(3),
R => reset2ip_reset
);
\alarm_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^alarm_reg_reg[7]_0\(4),
Q => Q(4),
R => reset2ip_reset
);
\alarm_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^alarm_reg_reg[7]_0\(5),
Q => Q(5),
R => reset2ip_reset
);
\alarm_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^alarm_reg_reg[7]_0\(6),
Q => Q(6),
R => reset2ip_reset
);
\alarm_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^alarm_reg_reg[7]_0\(7),
Q => Q(7),
R => reset2ip_reset
);
\alarm_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => XADC_INST_n_34,
Q => Q(8),
R => reset2ip_reset
);
den_d1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"4"
)
port map (
I0 => \^d\(6),
I1 => \GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]_0\,
O => den_d1_i_1_n_0
);
den_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => den_d1_i_1_n_0,
Q => den_d1,
R => '0'
);
\do_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => do_B_reg(0),
Q => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[16]\(0),
R => SR(0)
);
\do_reg_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => do_B_reg(10),
Q => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[16]\(10),
R => SR(0)
);
\do_reg_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => do_B_reg(11),
Q => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[16]\(11),
R => SR(0)
);
\do_reg_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => do_B_reg(12),
Q => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[16]\(12),
R => SR(0)
);
\do_reg_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => do_B_reg(13),
Q => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[16]\(13),
R => SR(0)
);
\do_reg_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => do_B_reg(14),
Q => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[16]\(14),
R => SR(0)
);
\do_reg_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => do_B_reg(15),
Q => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[16]\(15),
R => SR(0)
);
\do_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => do_B_reg(1),
Q => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[16]\(1),
R => SR(0)
);
\do_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => do_B_reg(2),
Q => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[16]\(2),
R => SR(0)
);
\do_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => do_B_reg(3),
Q => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[16]\(3),
R => SR(0)
);
\do_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => do_B_reg(4),
Q => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[16]\(4),
R => SR(0)
);
\do_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => do_B_reg(5),
Q => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[16]\(5),
R => SR(0)
);
\do_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => do_B_reg(6),
Q => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[16]\(6),
R => SR(0)
);
\do_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => do_B_reg(7),
Q => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[16]\(7),
R => SR(0)
);
\do_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => do_B_reg(8),
Q => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[16]\(8),
R => SR(0)
);
\do_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => do_B_reg(9),
Q => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[16]\(9),
R => SR(0)
);
drdy_rd_ack_i_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^d\(6),
D => bus2ip_rdce(0),
Q => drdy_rd_ack_i_d1,
R => reset2ip_reset
);
drdy_rd_ack_i_d2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^d\(6),
D => drdy_rd_ack_i_d1,
Q => drdy_rd_ack_i_d2,
R => reset2ip_reset
);
drdy_rd_ack_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Inst_drp_arbiter_n_8,
Q => drdy_rd_ack_i,
R => reset2ip_reset
);
drdy_wr_ack_i_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^d\(6),
D => bus2ip_wrce(0),
Q => drdy_wr_ack_i_d1,
R => reset2ip_reset
);
drdy_wr_ack_i_d2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \^d\(6),
D => drdy_wr_ack_i_d1,
Q => drdy_wr_ack_i_d2,
R => reset2ip_reset
);
drdy_wr_ack_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Inst_drp_arbiter_n_7,
Q => drdy_wr_ack_i,
R => reset2ip_reset
);
dwe_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg_0,
Q => dwe_d1,
R => '0'
);
eoc_d1_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \^eoc_out\,
I1 => status_reg_rdack,
I2 => eoc_d1,
O => eoc_d1_i_1_n_0
);
eoc_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => eoc_d1_i_1_n_0,
Q => eoc_d1,
R => reset2ip_reset
);
eos_d1_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \^eos_out\,
I1 => status_reg_rdack,
I2 => eos_d1,
O => eos_d1_i_1_n_0
);
eos_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => eos_d1_i_1_n_0,
Q => eos_d1,
R => reset2ip_reset
);
hard_macro_rst_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg_1,
Q => hard_macro_rst_reg,
R => reset2ip_reset
);
jtagmodified_d1_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00001110"
)
port map (
I0 => \RESET_FLOPS[15].RST_FLOPS\,
I1 => bus2ip_reset_active_high,
I2 => \^jtagmodified_d1\,
I3 => \^jtagmodified_i\,
I4 => drdy_rd_ack_i,
O => jtagmodified_d1_i_1_n_0
);
jtagmodified_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => jtagmodified_d1_i_1_n_0,
Q => \^jtagmodified_d1\,
R => '0'
);
local_reg_rdack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => local_rdce_or_reduce,
Q => local_reg_rdack_d1,
R => reset2ip_reset
);
local_reg_rdack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => local_reg_rdack0,
Q => local_reg_rdack,
R => reset2ip_reset
);
local_reg_wrack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg,
Q => local_reg_wrack_d1,
R => reset2ip_reset
);
local_reg_wrack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => local_reg_wrack0,
Q => local_reg_wrack,
R => reset2ip_reset
);
ot_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^alarm_reg_reg[7]_0\(0),
Q => ot_d1,
R => '0'
);
\status_reg[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^eoc_out\,
I1 => eoc_d1,
O => p_4_out(5)
);
\status_reg[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^eos_out\,
I1 => eos_d1,
O => p_4_out(6)
);
\status_reg[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^jtagmodified_d1\,
I1 => \^jtagmodified_i\,
O => jtag_modified_info
);
status_reg_rdack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => bus2ip_rdce(1),
Q => status_reg_rdack_d1,
R => reset2ip_reset
);
status_reg_rdack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => status_reg_rdack0,
Q => status_reg_rdack,
R => reset2ip_reset
);
\status_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^d\(0),
Q => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[21]\(0),
R => reset2ip_reset
);
\status_reg_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => jtagbusy_i,
Q => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[21]\(10),
R => reset2ip_reset
);
\status_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^d\(1),
Q => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[21]\(1),
R => reset2ip_reset
);
\status_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^d\(2),
Q => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[21]\(2),
R => reset2ip_reset
);
\status_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^d\(3),
Q => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[21]\(3),
R => reset2ip_reset
);
\status_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^d\(4),
Q => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[21]\(4),
R => reset2ip_reset
);
\status_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_4_out(5),
Q => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[21]\(5),
R => reset2ip_reset
);
\status_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_4_out(6),
Q => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[21]\(6),
R => reset2ip_reset
);
\status_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^d\(5),
Q => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[21]\(7),
R => reset2ip_reset
);
\status_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^d\(6),
Q => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[21]\(8),
R => reset2ip_reset
);
\status_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => jtag_modified_info,
Q => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[21]\(9),
R => reset2ip_reset
);
\temp_rd_wait_cycle_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(2),
Q => wait_cycle(0),
R => reset2ip_reset
);
\temp_rd_wait_cycle_reg_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(12),
Q => wait_cycle(10),
R => reset2ip_reset
);
\temp_rd_wait_cycle_reg_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(13),
Q => wait_cycle(11),
R => reset2ip_reset
);
\temp_rd_wait_cycle_reg_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(14),
Q => wait_cycle(12),
R => reset2ip_reset
);
\temp_rd_wait_cycle_reg_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(15),
Q => wait_cycle(13),
R => reset2ip_reset
);
\temp_rd_wait_cycle_reg_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(16),
Q => wait_cycle(14),
R => reset2ip_reset
);
\temp_rd_wait_cycle_reg_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(17),
Q => wait_cycle(15),
R => reset2ip_reset
);
\temp_rd_wait_cycle_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(3),
Q => wait_cycle(1),
R => reset2ip_reset
);
\temp_rd_wait_cycle_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(4),
Q => wait_cycle(2),
R => reset2ip_reset
);
\temp_rd_wait_cycle_reg_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(5),
Q => wait_cycle(3),
S => reset2ip_reset
);
\temp_rd_wait_cycle_reg_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(6),
Q => wait_cycle(4),
R => reset2ip_reset
);
\temp_rd_wait_cycle_reg_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(7),
Q => wait_cycle(5),
S => reset2ip_reset
);
\temp_rd_wait_cycle_reg_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(8),
Q => wait_cycle(6),
S => reset2ip_reset
);
\temp_rd_wait_cycle_reg_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(9),
Q => wait_cycle(7),
S => reset2ip_reset
);
\temp_rd_wait_cycle_reg_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(10),
Q => wait_cycle(8),
S => reset2ip_reset
);
\temp_rd_wait_cycle_reg_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(11),
Q => wait_cycle(9),
S => reset2ip_reset
);
temperature_update_inst: entity work.system_xadc_wiz_0_0_temperature_update
port map (
D(11 downto 0) => do_A_reg(15 downto 4),
\GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]\ => \GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]_0\,
Q(15 downto 0) => wait_cycle(15 downto 0),
bbusy_A => bbusy_A,
den_A => den_A,
den_C_reg_reg => \^d\(6),
den_d1 => den_d1,
den_d1_reg => Inst_drp_arbiter_n_6,
drdy_i => drdy_i,
overlap_A_reg => Inst_drp_arbiter_n_2,
overlap_B_reg => temperature_update_inst_n_2,
overlap_B_reg_0 => temperature_update_inst_n_4,
overlap_B_reg_1 => Inst_drp_arbiter_n_3,
reset => reset,
s_axi_aclk => s_axi_aclk,
\state_reg[0]_0\ => temperature_update_inst_n_3,
\state_reg[0]_1\ => Inst_drp_arbiter_n_5,
temp_out(11 downto 0) => temp_out(11 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xadc_wiz_0_0_system_xadc_wiz_0_0_axi_lite_ipif is
port (
dwe_d1_reg : out STD_LOGIC;
bus2ip_reset_active_high : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
Bus_RNW_reg : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
dwe_d1_reg_0 : out STD_LOGIC;
dwe_C_reg_reg : out STD_LOGIC;
bus2ip_wrce : out STD_LOGIC_VECTOR ( 0 to 0 );
rst_ip2bus_rdack0 : out STD_LOGIC;
bus2ip_rdce : out STD_LOGIC_VECTOR ( 2 downto 0 );
D : out STD_LOGIC_VECTOR ( 18 downto 0 );
status_reg_rdack0 : out STD_LOGIC;
Intr2Bus_RdAck0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[16].GEN_REG_STATUS.ip_irpt_status_reg_reg[16]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
local_reg_wrack0 : out STD_LOGIC;
local_reg_rdack0 : out STD_LOGIC;
local_rdce_or_reduce : out STD_LOGIC;
ip2bus_wrack_int1 : out STD_LOGIC;
\INTR_CTRLR_GEN_I.ip2bus_wrack_reg\ : out STD_LOGIC;
reset_trig0 : out STD_LOGIC;
sw_rst_cond : out STD_LOGIC;
p_3_out : out STD_LOGIC;
p_5_out : out STD_LOGIC;
dummy_bus2ip_rdce_intr : out STD_LOGIC;
dummy_local_reg_wrack0 : out STD_LOGIC;
dummy_local_reg_rdack0 : out STD_LOGIC;
dummy_local_reg_rdack_d10 : out STD_LOGIC;
hard_macro_rst_reg_reg : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
local_reg_wrack_d1_reg : out STD_LOGIC;
\temp_rd_wait_cycle_reg_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_d1_reg\ : out STD_LOGIC;
dummy_local_reg_wrack_d1_reg : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 18 downto 0 );
s_axi_aclk : in STD_LOGIC;
ip2bus_error : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack : in STD_LOGIC;
ip2bus_wrack : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
jtaglocked_i : in STD_LOGIC;
rst_ip2bus_rdack_d1 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 16 downto 0 );
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ : in STD_LOGIC;
\status_reg_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
\alarm_reg_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\do_reg_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
p_1_in44_in : in STD_LOGIC;
p_1_in41_in : in STD_LOGIC;
p_1_in38_in : in STD_LOGIC;
p_1_in35_in : in STD_LOGIC;
p_1_in32_in : in STD_LOGIC;
p_1_in29_in : in STD_LOGIC;
p_1_in26_in : in STD_LOGIC;
p_1_in23_in : in STD_LOGIC;
p_1_in20_in : in STD_LOGIC;
p_1_in17_in : in STD_LOGIC;
status_reg_rdack_d1 : in STD_LOGIC;
p_1_in14_in : in STD_LOGIC;
p_1_in11_in : in STD_LOGIC;
p_1_in8_in : in STD_LOGIC;
p_1_in5_in : in STD_LOGIC;
p_1_in2_in : in STD_LOGIC;
p_1_in : in STD_LOGIC;
jtagmodified_i : in STD_LOGIC;
jtagmodified_d1 : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
ipif_glbl_irpt_enable_reg : in STD_LOGIC;
irpt_rdack_d1 : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
local_reg_wrack_d1 : in STD_LOGIC;
local_reg_rdack_d1 : in STD_LOGIC;
intr_ip2bus_wrack : in STD_LOGIC;
wrack : in STD_LOGIC;
dummy_local_reg_wrack : in STD_LOGIC;
dummy_intr_reg_wrack : in STD_LOGIC;
local_reg_wrack_reg : in STD_LOGIC;
\s_axi_wdata_1__s_port_]\ : in STD_LOGIC;
sw_rst_cond_d1 : in STD_LOGIC;
dummy_intr_reg_wrack_d1 : in STD_LOGIC;
dummy_intr_reg_rdack_d1 : in STD_LOGIC;
dummy_local_reg_wrack_d1 : in STD_LOGIC;
dummy_local_reg_rdack_d1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 1 downto 0 );
hard_macro_rst_reg : in STD_LOGIC;
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[0]\ : in STD_LOGIC_VECTOR ( 18 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xadc_wiz_0_0_system_xadc_wiz_0_0_axi_lite_ipif : entity is "system_xadc_wiz_0_0_axi_lite_ipif";
end system_xadc_wiz_0_0_system_xadc_wiz_0_0_axi_lite_ipif;
architecture STRUCTURE of system_xadc_wiz_0_0_system_xadc_wiz_0_0_axi_lite_ipif is
signal \s_axi_wdata_1__s_net_1\ : STD_LOGIC;
begin
\s_axi_wdata_1__s_net_1\ <= \s_axi_wdata_1__s_port_]\;
I_SLAVE_ATTACHMENT: entity work.system_xadc_wiz_0_0_system_xadc_wiz_0_0_slave_attachment
port map (
D(18 downto 0) => D(18 downto 0),
E(0) => E(0),
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\,
\GEN_IP_IRPT_STATUS_REG[16].GEN_REG_STATUS.ip_irpt_status_reg_reg[16]\ => \GEN_IP_IRPT_STATUS_REG[16].GEN_REG_STATUS.ip_irpt_status_reg_reg[16]\,
\INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_d1_reg\ => \INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_d1_reg\,
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[0]\(18 downto 0) => \INTR_CTRLR_GEN_I.ip2bus_data_int_reg[0]\(18 downto 0),
\INTR_CTRLR_GEN_I.ip2bus_wrack_reg\ => \INTR_CTRLR_GEN_I.ip2bus_wrack_reg\,
Intr2Bus_RdAck0 => Intr2Bus_RdAck0,
Q(16 downto 0) => Q(16 downto 0),
SR(0) => bus2ip_reset_active_high,
\alarm_reg_reg[8]\(8 downto 0) => \alarm_reg_reg[8]\(8 downto 0),
bus2ip_rdce(2 downto 0) => bus2ip_rdce(2 downto 0),
bus2ip_wrce(0) => bus2ip_wrce(0),
\do_reg_reg[15]\(15 downto 0) => \do_reg_reg[15]\(15 downto 0),
dummy_bus2ip_rdce_intr => dummy_bus2ip_rdce_intr,
dummy_intr_reg_rdack_d1 => dummy_intr_reg_rdack_d1,
dummy_intr_reg_wrack => dummy_intr_reg_wrack,
dummy_intr_reg_wrack_d1 => dummy_intr_reg_wrack_d1,
dummy_local_reg_rdack0 => dummy_local_reg_rdack0,
dummy_local_reg_rdack_d1 => dummy_local_reg_rdack_d1,
dummy_local_reg_rdack_d10 => dummy_local_reg_rdack_d10,
dummy_local_reg_wrack => dummy_local_reg_wrack,
dummy_local_reg_wrack0 => dummy_local_reg_wrack0,
dummy_local_reg_wrack_d1 => dummy_local_reg_wrack_d1,
dummy_local_reg_wrack_d1_reg => dummy_local_reg_wrack_d1_reg,
dwe_C_reg_reg => dwe_C_reg_reg,
dwe_d1_reg => dwe_d1_reg,
dwe_d1_reg_0 => dwe_d1_reg_0,
hard_macro_rst_reg => hard_macro_rst_reg,
hard_macro_rst_reg_reg => Bus_RNW_reg,
hard_macro_rst_reg_reg_0 => hard_macro_rst_reg_reg,
interrupt_wrce_strb => interrupt_wrce_strb,
intr_ip2bus_wrack => intr_ip2bus_wrack,
ip2bus_error => ip2bus_error,
ip2bus_rdack => ip2bus_rdack,
ip2bus_wrack => ip2bus_wrack,
ip2bus_wrack_int1 => ip2bus_wrack_int1,
ipif_glbl_irpt_enable_reg => ipif_glbl_irpt_enable_reg,
ipif_glbl_irpt_enable_reg_reg => ipif_glbl_irpt_enable_reg_reg,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
jtaglocked_i => jtaglocked_i,
jtagmodified_d1 => jtagmodified_d1,
jtagmodified_i => jtagmodified_i,
local_rdce_or_reduce => local_rdce_or_reduce,
local_reg_rdack0 => local_reg_rdack0,
local_reg_rdack_d1 => local_reg_rdack_d1,
local_reg_wrack0 => local_reg_wrack0,
local_reg_wrack_d1 => local_reg_wrack_d1,
local_reg_wrack_d1_reg => local_reg_wrack_d1_reg,
local_reg_wrack_reg => local_reg_wrack_reg,
p_1_in => p_1_in,
p_1_in11_in => p_1_in11_in,
p_1_in14_in => p_1_in14_in,
p_1_in17_in => p_1_in17_in,
p_1_in20_in => p_1_in20_in,
p_1_in23_in => p_1_in23_in,
p_1_in26_in => p_1_in26_in,
p_1_in29_in => p_1_in29_in,
p_1_in2_in => p_1_in2_in,
p_1_in32_in => p_1_in32_in,
p_1_in35_in => p_1_in35_in,
p_1_in38_in => p_1_in38_in,
p_1_in41_in => p_1_in41_in,
p_1_in44_in => p_1_in44_in,
p_1_in5_in => p_1_in5_in,
p_1_in8_in => p_1_in8_in,
p_3_out => p_3_out,
p_5_out => p_5_out,
reset_trig0 => reset_trig0,
rst_ip2bus_rdack0 => rst_ip2bus_rdack0,
rst_ip2bus_rdack_d1 => rst_ip2bus_rdack_d1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(7 downto 0) => s_axi_araddr(7 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(7 downto 0) => s_axi_awaddr(7 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(0) => s_axi_bresp(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(18 downto 0) => s_axi_rdata(18 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(0) => s_axi_rresp(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(1 downto 0) => s_axi_wdata(1 downto 0),
\s_axi_wdata_1__s_port_]\ => \s_axi_wdata_1__s_net_1\,
s_axi_wready => s_axi_wready,
s_axi_wstrb(0) => s_axi_wstrb(0),
s_axi_wvalid => s_axi_wvalid,
status_reg_rdack0 => status_reg_rdack0,
status_reg_rdack_d1 => status_reg_rdack_d1,
\status_reg_reg[10]\(10 downto 0) => \status_reg_reg[10]\(10 downto 0),
sw_rst_cond => sw_rst_cond,
sw_rst_cond_d1 => sw_rst_cond_d1,
\temp_rd_wait_cycle_reg_reg[0]\(0) => \temp_rd_wait_cycle_reg_reg[0]\(0),
wrack => wrack
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xadc_wiz_0_0_system_xadc_wiz_0_0_axi_xadc is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
vauxp0 : in STD_LOGIC;
vauxn0 : in STD_LOGIC;
vauxp1 : in STD_LOGIC;
vauxn1 : in STD_LOGIC;
vauxp2 : in STD_LOGIC;
vauxn2 : in STD_LOGIC;
vauxp4 : in STD_LOGIC;
vauxn4 : in STD_LOGIC;
vauxp5 : in STD_LOGIC;
vauxn5 : in STD_LOGIC;
vauxp6 : in STD_LOGIC;
vauxn6 : in STD_LOGIC;
vauxp7 : in STD_LOGIC;
vauxn7 : in STD_LOGIC;
vauxp9 : in STD_LOGIC;
vauxn9 : in STD_LOGIC;
vauxp10 : in STD_LOGIC;
vauxn10 : in STD_LOGIC;
vauxp12 : in STD_LOGIC;
vauxn12 : in STD_LOGIC;
vauxp13 : in STD_LOGIC;
vauxn13 : in STD_LOGIC;
vauxp14 : in STD_LOGIC;
vauxn14 : in STD_LOGIC;
vauxp15 : in STD_LOGIC;
vauxn15 : in STD_LOGIC;
busy_out : out STD_LOGIC;
channel_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
eoc_out : out STD_LOGIC;
eos_out : out STD_LOGIC;
alarm_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
temp_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
vp_in : in STD_LOGIC;
vn_in : in STD_LOGIC
);
attribute C_FAMILY : string;
attribute C_FAMILY of system_xadc_wiz_0_0_system_xadc_wiz_0_0_axi_xadc : entity is "virtex7";
attribute C_INCLUDE_INTR : integer;
attribute C_INCLUDE_INTR of system_xadc_wiz_0_0_system_xadc_wiz_0_0_axi_xadc : entity is 1;
attribute C_INSTANCE : string;
attribute C_INSTANCE of system_xadc_wiz_0_0_system_xadc_wiz_0_0_axi_xadc : entity is "system_xadc_wiz_0_0_axi_xadc";
attribute C_SIM_MONITOR_FILE : string;
attribute C_SIM_MONITOR_FILE of system_xadc_wiz_0_0_system_xadc_wiz_0_0_axi_xadc : entity is "design.txt";
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of system_xadc_wiz_0_0_system_xadc_wiz_0_0_axi_xadc : entity is 11;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_xadc_wiz_0_0_system_xadc_wiz_0_0_axi_xadc : entity is 32;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xadc_wiz_0_0_system_xadc_wiz_0_0_axi_xadc : entity is "system_xadc_wiz_0_0_axi_xadc";
attribute hdl : string;
attribute hdl of system_xadc_wiz_0_0_system_xadc_wiz_0_0_axi_xadc : entity is "VHDL";
attribute ip_group : string;
attribute ip_group of system_xadc_wiz_0_0_system_xadc_wiz_0_0_axi_xadc : entity is "LOGICORE";
attribute iptype : string;
attribute iptype of system_xadc_wiz_0_0_system_xadc_wiz_0_0_axi_xadc : entity is "PERIPHERAL";
end system_xadc_wiz_0_0_system_xadc_wiz_0_0_axi_xadc;
architecture STRUCTURE of system_xadc_wiz_0_0_system_xadc_wiz_0_0_axi_xadc is
signal \<const0>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_0 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_10 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_40 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_46 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_55 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_56 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_57 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_58 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_59 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_60 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_9 : STD_LOGIC;
signal AXI_XADC_CORE_I_n_16 : STD_LOGIC;
signal AXI_XADC_CORE_I_n_24 : STD_LOGIC;
signal AXI_XADC_CORE_I_n_26 : STD_LOGIC;
signal AXI_XADC_CORE_I_n_27 : STD_LOGIC;
signal \INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I_n_1\ : STD_LOGIC;
signal \INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I_n_26\ : STD_LOGIC;
signal \INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I_n_31\ : STD_LOGIC;
signal \INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I_n_36\ : STD_LOGIC;
signal \INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I_n_38\ : STD_LOGIC;
signal \INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I_n_39\ : STD_LOGIC;
signal \INTR_CTRLR_GEN_I.ip2bus_error_i_3_n_0\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
signal Intr2Bus_RdAck0 : STD_LOGIC;
signal SOFT_RESET_I_n_2 : STD_LOGIC;
signal SOFT_RESET_I_n_4 : STD_LOGIC;
signal SOFT_RESET_I_n_6 : STD_LOGIC;
signal Sysmon_IP2Bus_Data : STD_LOGIC_VECTOR ( 14 to 14 );
signal \^alarm_out\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal alarm_reg : STD_LOGIC_VECTOR ( 0 to 0 );
signal bus2ip_rdce : STD_LOGIC_VECTOR ( 24 downto 0 );
signal bus2ip_reset_active_high : STD_LOGIC;
signal bus2ip_wrce : STD_LOGIC_VECTOR ( 0 to 0 );
signal do_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
signal dummy_bus2ip_rdce_intr : STD_LOGIC;
signal dummy_intr_reg_rdack : STD_LOGIC;
signal dummy_intr_reg_rdack_d1 : STD_LOGIC;
signal dummy_intr_reg_wrack : STD_LOGIC;
signal dummy_intr_reg_wrack_d1 : STD_LOGIC;
signal dummy_local_reg_rdack : STD_LOGIC;
signal dummy_local_reg_rdack0 : STD_LOGIC;
signal dummy_local_reg_rdack_d1 : STD_LOGIC;
signal dummy_local_reg_rdack_d10 : STD_LOGIC;
signal dummy_local_reg_wrack : STD_LOGIC;
signal dummy_local_reg_wrack0 : STD_LOGIC;
signal dummy_local_reg_wrack_d1 : STD_LOGIC;
signal \^eoc_out\ : STD_LOGIC;
signal \^eos_out\ : STD_LOGIC;
signal hard_macro_rst_reg : STD_LOGIC;
signal interrupt_wrce_strb : STD_LOGIC;
signal intr_ip2bus_data : STD_LOGIC_VECTOR ( 0 to 0 );
signal intr_ip2bus_rdack : STD_LOGIC;
signal intr_ip2bus_wrack : STD_LOGIC;
signal ip2bus_data : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ip2bus_data_int1 : STD_LOGIC_VECTOR ( 15 to 31 );
signal ip2bus_error : STD_LOGIC;
signal ip2bus_error_int1 : STD_LOGIC;
signal ip2bus_rdack : STD_LOGIC;
signal ip2bus_rdack_int1 : STD_LOGIC;
signal ip2bus_wrack : STD_LOGIC;
signal ip2bus_wrack_int1 : STD_LOGIC;
signal ipif_glbl_irpt_enable_reg : STD_LOGIC;
signal irpt_rdack : STD_LOGIC;
signal irpt_rdack_d1 : STD_LOGIC;
signal irpt_wrack : STD_LOGIC;
signal irpt_wrack_d1 : STD_LOGIC;
signal irpt_wrack_d11 : STD_LOGIC;
signal jtaglocked_i : STD_LOGIC;
signal jtagmodified_d1 : STD_LOGIC;
signal jtagmodified_i : STD_LOGIC;
signal local_rdce_or_reduce : STD_LOGIC;
signal local_reg_rdack0 : STD_LOGIC;
signal local_reg_rdack_d1 : STD_LOGIC;
signal local_reg_wrack0 : STD_LOGIC;
signal local_reg_wrack_d1 : STD_LOGIC;
signal ot_i : STD_LOGIC;
signal p_0_in10_in : STD_LOGIC;
signal p_0_in13_in : STD_LOGIC;
signal p_0_in16_in : STD_LOGIC;
signal p_0_in1_in : STD_LOGIC;
signal p_0_in22_in : STD_LOGIC;
signal p_0_in25_in : STD_LOGIC;
signal p_0_in28_in : STD_LOGIC;
signal p_0_in31_in : STD_LOGIC;
signal p_0_in37_in : STD_LOGIC;
signal p_0_in40_in : STD_LOGIC;
signal p_0_in43_in : STD_LOGIC;
signal p_0_in7_in : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_1_in11_in : STD_LOGIC;
signal p_1_in14_in : STD_LOGIC;
signal p_1_in17_in : STD_LOGIC;
signal p_1_in20_in : STD_LOGIC;
signal p_1_in23_in : STD_LOGIC;
signal p_1_in26_in : STD_LOGIC;
signal p_1_in29_in : STD_LOGIC;
signal p_1_in2_in : STD_LOGIC;
signal p_1_in32_in : STD_LOGIC;
signal p_1_in35_in : STD_LOGIC;
signal p_1_in38_in : STD_LOGIC;
signal p_1_in41_in : STD_LOGIC;
signal p_1_in44_in : STD_LOGIC;
signal p_1_in5_in : STD_LOGIC;
signal p_1_in8_in : STD_LOGIC;
signal p_1_in_0 : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in : STD_LOGIC;
signal p_3_out : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal p_5_in : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal reset : STD_LOGIC;
signal reset2ip_reset : STD_LOGIC;
signal reset_trig0 : STD_LOGIC;
signal rst_ip2bus_rdack : STD_LOGIC;
signal rst_ip2bus_rdack0 : STD_LOGIC;
signal rst_ip2bus_rdack_d1 : STD_LOGIC;
signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_rresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^s_axi_wready\ : STD_LOGIC;
signal status_reg : STD_LOGIC_VECTOR ( 10 downto 0 );
signal status_reg_rdack0 : STD_LOGIC;
signal status_reg_rdack_d1 : STD_LOGIC;
signal sw_rst_cond : STD_LOGIC;
signal sw_rst_cond_d1 : STD_LOGIC;
signal wrack : STD_LOGIC;
begin
alarm_out(7 downto 0) <= \^alarm_out\(7 downto 0);
eoc_out <= \^eoc_out\;
eos_out <= \^eos_out\;
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \^s_axi_bresp\(1);
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \^s_axi_rdata\(31);
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17 downto 0) <= \^s_axi_rdata\(17 downto 0);
s_axi_rresp(1) <= \^s_axi_rresp\(1);
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI_LITE_IPIF_I: entity work.system_xadc_wiz_0_0_system_xadc_wiz_0_0_axi_lite_ipif
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
D(18) => intr_ip2bus_data(0),
D(17) => Sysmon_IP2Bus_Data(14),
D(16) => ip2bus_data_int1(15),
D(15) => ip2bus_data_int1(16),
D(14) => ip2bus_data_int1(17),
D(13) => ip2bus_data_int1(18),
D(12) => ip2bus_data_int1(19),
D(11) => ip2bus_data_int1(20),
D(10) => ip2bus_data_int1(21),
D(9) => ip2bus_data_int1(22),
D(8) => ip2bus_data_int1(23),
D(7) => ip2bus_data_int1(24),
D(6) => ip2bus_data_int1(25),
D(5) => ip2bus_data_int1(26),
D(4) => ip2bus_data_int1(27),
D(3) => ip2bus_data_int1(28),
D(2) => ip2bus_data_int1(29),
D(1) => ip2bus_data_int1(30),
D(0) => ip2bus_data_int1(31),
E(0) => irpt_wrack_d11,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ => \INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I_n_1\,
\GEN_IP_IRPT_STATUS_REG[16].GEN_REG_STATUS.ip_irpt_status_reg_reg[16]\ => AXI_LITE_IPIF_I_n_40,
\INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_d1_reg\ => AXI_LITE_IPIF_I_n_59,
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[0]\(18) => ip2bus_data(31),
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[0]\(17 downto 0) => ip2bus_data(17 downto 0),
\INTR_CTRLR_GEN_I.ip2bus_wrack_reg\ => AXI_LITE_IPIF_I_n_46,
Intr2Bus_RdAck0 => Intr2Bus_RdAck0,
Q(16) => p_0_in43_in,
Q(15) => p_0_in40_in,
Q(14) => p_0_in37_in,
Q(13) => \INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I_n_26\,
Q(12) => p_0_in31_in,
Q(11) => p_0_in28_in,
Q(10) => p_0_in25_in,
Q(9) => p_0_in22_in,
Q(8) => \INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I_n_31\,
Q(7) => p_0_in16_in,
Q(6) => p_0_in13_in,
Q(5) => p_0_in10_in,
Q(4) => p_0_in7_in,
Q(3) => \INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I_n_36\,
Q(2) => p_0_in1_in,
Q(1) => \INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I_n_38\,
Q(0) => \INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I_n_39\,
\alarm_reg_reg[8]\(8 downto 1) => \^alarm_out\(7 downto 0),
\alarm_reg_reg[8]\(0) => alarm_reg(0),
bus2ip_rdce(2 downto 1) => bus2ip_rdce(24 downto 23),
bus2ip_rdce(0) => bus2ip_rdce(0),
bus2ip_reset_active_high => bus2ip_reset_active_high,
bus2ip_wrce(0) => bus2ip_wrce(0),
\do_reg_reg[15]\(15 downto 0) => do_reg(15 downto 0),
dummy_bus2ip_rdce_intr => dummy_bus2ip_rdce_intr,
dummy_intr_reg_rdack_d1 => dummy_intr_reg_rdack_d1,
dummy_intr_reg_wrack => dummy_intr_reg_wrack,
dummy_intr_reg_wrack_d1 => dummy_intr_reg_wrack_d1,
dummy_local_reg_rdack0 => dummy_local_reg_rdack0,
dummy_local_reg_rdack_d1 => dummy_local_reg_rdack_d1,
dummy_local_reg_rdack_d10 => dummy_local_reg_rdack_d10,
dummy_local_reg_wrack => dummy_local_reg_wrack,
dummy_local_reg_wrack0 => dummy_local_reg_wrack0,
dummy_local_reg_wrack_d1 => dummy_local_reg_wrack_d1,
dummy_local_reg_wrack_d1_reg => AXI_LITE_IPIF_I_n_60,
dwe_C_reg_reg => AXI_LITE_IPIF_I_n_10,
dwe_d1_reg => AXI_LITE_IPIF_I_n_0,
dwe_d1_reg_0 => AXI_LITE_IPIF_I_n_9,
hard_macro_rst_reg => hard_macro_rst_reg,
hard_macro_rst_reg_reg => AXI_LITE_IPIF_I_n_55,
interrupt_wrce_strb => interrupt_wrce_strb,
intr_ip2bus_wrack => intr_ip2bus_wrack,
ip2bus_error => ip2bus_error,
ip2bus_rdack => ip2bus_rdack,
ip2bus_wrack => ip2bus_wrack,
ip2bus_wrack_int1 => ip2bus_wrack_int1,
ipif_glbl_irpt_enable_reg => ipif_glbl_irpt_enable_reg,
ipif_glbl_irpt_enable_reg_reg => AXI_LITE_IPIF_I_n_56,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
jtaglocked_i => jtaglocked_i,
jtagmodified_d1 => jtagmodified_d1,
jtagmodified_i => jtagmodified_i,
local_rdce_or_reduce => local_rdce_or_reduce,
local_reg_rdack0 => local_reg_rdack0,
local_reg_rdack_d1 => local_reg_rdack_d1,
local_reg_wrack0 => local_reg_wrack0,
local_reg_wrack_d1 => local_reg_wrack_d1,
local_reg_wrack_d1_reg => AXI_LITE_IPIF_I_n_57,
local_reg_wrack_reg => AXI_XADC_CORE_I_n_24,
p_1_in => p_1_in_0,
p_1_in11_in => p_1_in11_in,
p_1_in14_in => p_1_in14_in,
p_1_in17_in => p_1_in17_in,
p_1_in20_in => p_1_in20_in,
p_1_in23_in => p_1_in23_in,
p_1_in26_in => p_1_in26_in,
p_1_in29_in => p_1_in29_in,
p_1_in2_in => p_1_in2_in,
p_1_in32_in => p_1_in32_in,
p_1_in35_in => p_1_in35_in,
p_1_in38_in => p_1_in38_in,
p_1_in41_in => p_1_in41_in,
p_1_in44_in => p_1_in44_in,
p_1_in5_in => p_1_in5_in,
p_1_in8_in => p_1_in8_in,
p_3_out => p_3_out,
p_5_out => p_5_out,
reset_trig0 => reset_trig0,
rst_ip2bus_rdack0 => rst_ip2bus_rdack0,
rst_ip2bus_rdack_d1 => rst_ip2bus_rdack_d1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(7 downto 0) => s_axi_araddr(9 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(7 downto 0) => s_axi_awaddr(9 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(0) => \^s_axi_bresp\(1),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(18) => \^s_axi_rdata\(31),
s_axi_rdata(17 downto 0) => \^s_axi_rdata\(17 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(0) => \^s_axi_rresp\(1),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(1) => s_axi_wdata(31),
s_axi_wdata(0) => s_axi_wdata(0),
\s_axi_wdata_1__s_port_]\ => SOFT_RESET_I_n_4,
s_axi_wready => \^s_axi_wready\,
s_axi_wstrb(0) => s_axi_wstrb(3),
s_axi_wvalid => s_axi_wvalid,
status_reg_rdack0 => status_reg_rdack0,
status_reg_rdack_d1 => status_reg_rdack_d1,
\status_reg_reg[10]\(10 downto 0) => status_reg(10 downto 0),
sw_rst_cond => sw_rst_cond,
sw_rst_cond_d1 => sw_rst_cond_d1,
\temp_rd_wait_cycle_reg_reg[0]\(0) => AXI_LITE_IPIF_I_n_58,
wrack => wrack
);
AXI_XADC_CORE_I: entity work.system_xadc_wiz_0_0_system_xadc_wiz_0_0_xadc_core_drp
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
Bus_RNW_reg_reg => AXI_LITE_IPIF_I_n_57,
Bus_RNW_reg_reg_0 => AXI_LITE_IPIF_I_n_9,
Bus_RNW_reg_reg_1 => AXI_LITE_IPIF_I_n_55,
D(6) => jtaglocked_i,
D(5) => busy_out,
D(4 downto 0) => channel_out(4 downto 0),
\DO_IRPT_INPUT[8].GEN_POS_EDGE_DETECT.irpt_dly1_reg\ => AXI_XADC_CORE_I_n_27,
\DO_IRPT_INPUT[9].GEN_POS_EDGE_DETECT.irpt_dly1_reg\ => AXI_XADC_CORE_I_n_26,
E(0) => AXI_LITE_IPIF_I_n_58,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => AXI_LITE_IPIF_I_n_46,
\GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]\ => AXI_LITE_IPIF_I_n_10,
\GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]_0\ => AXI_LITE_IPIF_I_n_0,
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[16]\(15 downto 0) => do_reg(15 downto 0),
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[21]\(10 downto 0) => status_reg(10 downto 0),
\INTR_CTRLR_GEN_I.ip2bus_wrack_reg\ => AXI_XADC_CORE_I_n_24,
Q(8 downto 1) => \^alarm_out\(7 downto 0),
Q(0) => alarm_reg(0),
\RESET_FLOPS[15].RST_FLOPS\ => SOFT_RESET_I_n_2,
SR(0) => SOFT_RESET_I_n_6,
VAUXN(12) => vauxn15,
VAUXN(11) => vauxn14,
VAUXN(10) => vauxn13,
VAUXN(9) => vauxn12,
VAUXN(8) => vauxn10,
VAUXN(7) => vauxn9,
VAUXN(6) => vauxn7,
VAUXN(5) => vauxn6,
VAUXN(4) => vauxn5,
VAUXN(3) => vauxn4,
VAUXN(2) => vauxn2,
VAUXN(1) => vauxn1,
VAUXN(0) => vauxn0,
VAUXP(12) => vauxp15,
VAUXP(11) => vauxp14,
VAUXP(10) => vauxp13,
VAUXP(9) => vauxp12,
VAUXP(8) => vauxp10,
VAUXP(7) => vauxp9,
VAUXP(6) => vauxp7,
VAUXP(5) => vauxp6,
VAUXP(4) => vauxp5,
VAUXP(3) => vauxp4,
VAUXP(2) => vauxp2,
VAUXP(1) => vauxp1,
VAUXP(0) => vauxp0,
\alarm_reg_reg[7]_0\(7) => p_1_in,
\alarm_reg_reg[7]_0\(6) => p_2_in,
\alarm_reg_reg[7]_0\(5) => p_3_in,
\alarm_reg_reg[7]_0\(4) => p_4_in,
\alarm_reg_reg[7]_0\(3) => p_5_in,
\alarm_reg_reg[7]_0\(2) => p_6_in,
\alarm_reg_reg[7]_0\(1) => AXI_XADC_CORE_I_n_16,
\alarm_reg_reg[7]_0\(0) => ot_i,
bus2ip_rdce(1) => bus2ip_rdce(23),
bus2ip_rdce(0) => bus2ip_rdce(0),
bus2ip_reset_active_high => bus2ip_reset_active_high,
bus2ip_wrce(0) => bus2ip_wrce(0),
dummy_intr_reg_rdack => dummy_intr_reg_rdack,
dummy_local_reg_rdack => dummy_local_reg_rdack,
eoc_out => \^eoc_out\,
eos_out => \^eos_out\,
hard_macro_rst_reg => hard_macro_rst_reg,
intr_ip2bus_rdack => intr_ip2bus_rdack,
ip2bus_error_int1 => ip2bus_error_int1,
ip2bus_rdack_int1 => ip2bus_rdack_int1,
jtagmodified_d1 => jtagmodified_d1,
jtagmodified_i => jtagmodified_i,
local_rdce_or_reduce => local_rdce_or_reduce,
local_reg_rdack0 => local_reg_rdack0,
local_reg_rdack_d1 => local_reg_rdack_d1,
local_reg_wrack0 => local_reg_wrack0,
local_reg_wrack_d1 => local_reg_wrack_d1,
reset => reset,
reset2ip_reset => reset2ip_reset,
rst_ip2bus_rdack => rst_ip2bus_rdack,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(6 downto 0) => s_axi_araddr(8 downto 2),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(6 downto 0) => s_axi_awaddr(8 downto 2),
s_axi_wdata(17 downto 0) => s_axi_wdata(17 downto 0),
\s_axi_wstrb[2]\ => \INTR_CTRLR_GEN_I.ip2bus_error_i_3_n_0\,
status_reg_rdack0 => status_reg_rdack0,
status_reg_rdack_d1 => status_reg_rdack_d1,
temp_out(11 downto 0) => temp_out(11 downto 0),
vn_in => vn_in,
vp_in => vp_in
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I\: entity work.system_xadc_wiz_0_0_system_xadc_wiz_0_0_interrupt_control
port map (
Bus_RNW_reg_reg => AXI_LITE_IPIF_I_n_40,
D(0) => jtaglocked_i,
E(0) => irpt_wrack_d11,
\GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]\ => AXI_LITE_IPIF_I_n_56,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ => \INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I_n_1\,
Intr2Bus_RdAck0 => Intr2Bus_RdAck0,
Q(16) => p_0_in43_in,
Q(15) => p_0_in40_in,
Q(14) => p_0_in37_in,
Q(13) => \INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I_n_26\,
Q(12) => p_0_in31_in,
Q(11) => p_0_in28_in,
Q(10) => p_0_in25_in,
Q(9) => p_0_in22_in,
Q(8) => \INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I_n_31\,
Q(7) => p_0_in16_in,
Q(6) => p_0_in13_in,
Q(5) => p_0_in10_in,
Q(4) => p_0_in7_in,
Q(3) => \INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I_n_36\,
Q(2) => p_0_in1_in,
Q(1) => \INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I_n_38\,
Q(0) => \INTR_CTRLR_GEN_I.INTERRUPT_CONTROL_I_n_39\,
alarm_0_d1_reg => AXI_XADC_CORE_I_n_26,
den_C_reg_reg(7) => p_1_in,
den_C_reg_reg(6) => p_2_in,
den_C_reg_reg(5) => p_3_in,
den_C_reg_reg(4) => p_4_in,
den_C_reg_reg(3) => p_5_in,
den_C_reg_reg(2) => p_6_in,
den_C_reg_reg(1) => AXI_XADC_CORE_I_n_16,
den_C_reg_reg(0) => ot_i,
eoc_out => \^eoc_out\,
eos_out => \^eos_out\,
interrupt_wrce_strb => interrupt_wrce_strb,
intr_ip2bus_rdack => intr_ip2bus_rdack,
intr_ip2bus_wrack => intr_ip2bus_wrack,
ip2intc_irpt => ip2intc_irpt,
ipif_glbl_irpt_enable_reg => ipif_glbl_irpt_enable_reg,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
jtagmodified_i => jtagmodified_i,
ot_d1_reg => AXI_XADC_CORE_I_n_27,
p_1_in => p_1_in_0,
p_1_in11_in => p_1_in11_in,
p_1_in14_in => p_1_in14_in,
p_1_in17_in => p_1_in17_in,
p_1_in20_in => p_1_in20_in,
p_1_in23_in => p_1_in23_in,
p_1_in26_in => p_1_in26_in,
p_1_in29_in => p_1_in29_in,
p_1_in2_in => p_1_in2_in,
p_1_in32_in => p_1_in32_in,
p_1_in35_in => p_1_in35_in,
p_1_in38_in => p_1_in38_in,
p_1_in41_in => p_1_in41_in,
p_1_in44_in => p_1_in44_in,
p_1_in5_in => p_1_in5_in,
p_1_in8_in => p_1_in8_in,
reset2ip_reset => reset2ip_reset,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(16 downto 0) => s_axi_wdata(16 downto 0)
);
\INTR_CTRLR_GEN_I.dummy_intr_reg_rdack_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => dummy_bus2ip_rdce_intr,
Q => dummy_intr_reg_rdack_d1,
R => reset2ip_reset
);
\INTR_CTRLR_GEN_I.dummy_intr_reg_rdack_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_5_out,
Q => dummy_intr_reg_rdack,
R => reset2ip_reset
);
\INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => AXI_LITE_IPIF_I_n_59,
Q => dummy_intr_reg_wrack_d1,
R => reset2ip_reset
);
\INTR_CTRLR_GEN_I.dummy_intr_reg_wrack_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_3_out,
Q => dummy_intr_reg_wrack,
R => reset2ip_reset
);
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => intr_ip2bus_data(0),
Q => ip2bus_data(31),
R => reset2ip_reset
);
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => Sysmon_IP2Bus_Data(14),
Q => ip2bus_data(17),
R => reset2ip_reset
);
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data_int1(15),
Q => ip2bus_data(16),
R => reset2ip_reset
);
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data_int1(16),
Q => ip2bus_data(15),
R => reset2ip_reset
);
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data_int1(17),
Q => ip2bus_data(14),
R => reset2ip_reset
);
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data_int1(18),
Q => ip2bus_data(13),
R => reset2ip_reset
);
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data_int1(19),
Q => ip2bus_data(12),
R => reset2ip_reset
);
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data_int1(20),
Q => ip2bus_data(11),
R => reset2ip_reset
);
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data_int1(21),
Q => ip2bus_data(10),
R => reset2ip_reset
);
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data_int1(22),
Q => ip2bus_data(9),
R => reset2ip_reset
);
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data_int1(23),
Q => ip2bus_data(8),
R => reset2ip_reset
);
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data_int1(24),
Q => ip2bus_data(7),
R => reset2ip_reset
);
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data_int1(25),
Q => ip2bus_data(6),
R => reset2ip_reset
);
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data_int1(26),
Q => ip2bus_data(5),
R => reset2ip_reset
);
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data_int1(27),
Q => ip2bus_data(4),
R => reset2ip_reset
);
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data_int1(28),
Q => ip2bus_data(3),
R => reset2ip_reset
);
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data_int1(29),
Q => ip2bus_data(2),
R => reset2ip_reset
);
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data_int1(30),
Q => ip2bus_data(1),
R => reset2ip_reset
);
\INTR_CTRLR_GEN_I.ip2bus_data_int_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data_int1(31),
Q => ip2bus_data(0),
R => reset2ip_reset
);
\INTR_CTRLR_GEN_I.ip2bus_error_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAAA"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_wstrb(3),
I2 => s_axi_wstrb(1),
I3 => s_axi_wstrb(0),
I4 => s_axi_wstrb(2),
O => \INTR_CTRLR_GEN_I.ip2bus_error_i_3_n_0\
);
\INTR_CTRLR_GEN_I.ip2bus_error_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_error_int1,
Q => ip2bus_error,
R => reset2ip_reset
);
\INTR_CTRLR_GEN_I.ip2bus_rdack_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_int1,
Q => ip2bus_rdack,
R => reset2ip_reset
);
\INTR_CTRLR_GEN_I.ip2bus_wrack_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_wrack_int1,
Q => ip2bus_wrack,
R => reset2ip_reset
);
SOFT_RESET_I: entity work.system_xadc_wiz_0_0_system_xadc_wiz_0_0_soft_reset
port map (
D(0) => jtaglocked_i,
SR(0) => SOFT_RESET_I_n_6,
bus2ip_reset_active_high => bus2ip_reset_active_high,
hard_macro_rst_reg => hard_macro_rst_reg,
\ip_irpt_enable_reg_reg[16]\ => SOFT_RESET_I_n_2,
reset => reset,
reset2ip_reset => reset2ip_reset,
reset_trig0 => reset_trig0,
reset_trig_reg_0 => SOFT_RESET_I_n_4,
s_axi_aclk => s_axi_aclk,
s_axi_arvalid => s_axi_arvalid,
s_axi_wdata(3 downto 0) => s_axi_wdata(3 downto 0),
s_axi_wstrb(0) => s_axi_wstrb(0),
sw_rst_cond => sw_rst_cond,
sw_rst_cond_d1 => sw_rst_cond_d1,
wrack => wrack
);
dummy_local_reg_rdack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => dummy_local_reg_rdack_d10,
Q => dummy_local_reg_rdack_d1,
R => reset2ip_reset
);
dummy_local_reg_rdack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => dummy_local_reg_rdack0,
Q => dummy_local_reg_rdack,
R => reset2ip_reset
);
dummy_local_reg_wrack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => AXI_LITE_IPIF_I_n_60,
Q => dummy_local_reg_wrack_d1,
R => reset2ip_reset
);
dummy_local_reg_wrack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => dummy_local_reg_wrack0,
Q => dummy_local_reg_wrack,
R => reset2ip_reset
);
rst_ip2bus_rdack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => bus2ip_rdce(24),
Q => rst_ip2bus_rdack_d1,
R => reset2ip_reset
);
rst_ip2bus_rdack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rst_ip2bus_rdack0,
Q => rst_ip2bus_rdack,
R => reset2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xadc_wiz_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
vauxp0 : in STD_LOGIC;
vauxn0 : in STD_LOGIC;
vauxp1 : in STD_LOGIC;
vauxn1 : in STD_LOGIC;
vauxp2 : in STD_LOGIC;
vauxn2 : in STD_LOGIC;
vauxp4 : in STD_LOGIC;
vauxn4 : in STD_LOGIC;
vauxp5 : in STD_LOGIC;
vauxn5 : in STD_LOGIC;
vauxp6 : in STD_LOGIC;
vauxn6 : in STD_LOGIC;
vauxp7 : in STD_LOGIC;
vauxn7 : in STD_LOGIC;
vauxp9 : in STD_LOGIC;
vauxn9 : in STD_LOGIC;
vauxp10 : in STD_LOGIC;
vauxn10 : in STD_LOGIC;
vauxp12 : in STD_LOGIC;
vauxn12 : in STD_LOGIC;
vauxp13 : in STD_LOGIC;
vauxn13 : in STD_LOGIC;
vauxp14 : in STD_LOGIC;
vauxn14 : in STD_LOGIC;
vauxp15 : in STD_LOGIC;
vauxn15 : in STD_LOGIC;
busy_out : out STD_LOGIC;
channel_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
eoc_out : out STD_LOGIC;
eos_out : out STD_LOGIC;
vccaux_alarm_out : out STD_LOGIC;
vccint_alarm_out : out STD_LOGIC;
user_temp_alarm_out : out STD_LOGIC;
alarm_out : out STD_LOGIC;
temp_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
vp_in : in STD_LOGIC;
vn_in : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_xadc_wiz_0_0 : entity is true;
end system_xadc_wiz_0_0;
architecture STRUCTURE of system_xadc_wiz_0_0 is
signal NLW_U0_alarm_out_UNCONNECTED : STD_LOGIC_VECTOR ( 6 downto 3 );
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "virtex7";
attribute C_INCLUDE_INTR : integer;
attribute C_INCLUDE_INTR of U0 : label is 1;
attribute C_INSTANCE : string;
attribute C_INSTANCE of U0 : label is "system_xadc_wiz_0_0_axi_xadc";
attribute C_SIM_MONITOR_FILE : string;
attribute C_SIM_MONITOR_FILE of U0 : label is "design.txt";
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 11;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute hdl : string;
attribute hdl of U0 : label is "VHDL";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
attribute iptype : string;
attribute iptype of U0 : label is "PERIPHERAL";
begin
U0: entity work.system_xadc_wiz_0_0_system_xadc_wiz_0_0_axi_xadc
port map (
alarm_out(7) => alarm_out,
alarm_out(6 downto 3) => NLW_U0_alarm_out_UNCONNECTED(6 downto 3),
alarm_out(2) => vccaux_alarm_out,
alarm_out(1) => vccint_alarm_out,
alarm_out(0) => user_temp_alarm_out,
busy_out => busy_out,
channel_out(4 downto 0) => channel_out(4 downto 0),
eoc_out => eoc_out,
eos_out => eos_out,
ip2intc_irpt => ip2intc_irpt,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(10 downto 0) => s_axi_araddr(10 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(10 downto 0) => s_axi_awaddr(10 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid,
temp_out(11 downto 0) => temp_out(11 downto 0),
vauxn0 => vauxn0,
vauxn1 => vauxn1,
vauxn10 => vauxn10,
vauxn12 => vauxn12,
vauxn13 => vauxn13,
vauxn14 => vauxn14,
vauxn15 => vauxn15,
vauxn2 => vauxn2,
vauxn4 => vauxn4,
vauxn5 => vauxn5,
vauxn6 => vauxn6,
vauxn7 => vauxn7,
vauxn9 => vauxn9,
vauxp0 => vauxp0,
vauxp1 => vauxp1,
vauxp10 => vauxp10,
vauxp12 => vauxp12,
vauxp13 => vauxp13,
vauxp14 => vauxp14,
vauxp15 => vauxp15,
vauxp2 => vauxp2,
vauxp4 => vauxp4,
vauxp5 => vauxp5,
vauxp6 => vauxp6,
vauxp7 => vauxp7,
vauxp9 => vauxp9,
vn_in => vn_in,
vp_in => vp_in
);
end STRUCTURE;
|
apache-2.0
|
1fe3a1cf4336cbd6b34a260a26ebc5e4
| 0.541194 | 2.51705 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_dlmb_bram_if_cntlr_0/synth/system_dlmb_bram_if_cntlr_0.vhd
| 1 | 13,435 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:lmb_bram_if_cntlr:4.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY lmb_bram_if_cntlr_v4_0_10;
USE lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_cntlr;
ENTITY system_dlmb_bram_if_cntlr_0 IS
PORT (
LMB_Clk : IN STD_LOGIC;
LMB_Rst : IN STD_LOGIC;
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_AddrStrobe : IN STD_LOGIC;
LMB_ReadStrobe : IN STD_LOGIC;
LMB_WriteStrobe : IN STD_LOGIC;
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : OUT STD_LOGIC;
Sl_Wait : OUT STD_LOGIC;
Sl_UE : OUT STD_LOGIC;
Sl_CE : OUT STD_LOGIC;
BRAM_Rst_A : OUT STD_LOGIC;
BRAM_Clk_A : OUT STD_LOGIC;
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_EN_A : OUT STD_LOGIC;
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31)
);
END system_dlmb_bram_if_cntlr_0;
ARCHITECTURE system_dlmb_bram_if_cntlr_0_arch OF system_dlmb_bram_if_cntlr_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_dlmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "yes";
COMPONENT lmb_bram_if_cntlr IS
GENERIC (
C_FAMILY : STRING;
C_HIGHADDR : STD_LOGIC_VECTOR;
C_BASEADDR : STD_LOGIC_VECTOR;
C_NUM_LMB : INTEGER;
C_MASK : STD_LOGIC_VECTOR;
C_MASK1 : STD_LOGIC_VECTOR;
C_MASK2 : STD_LOGIC_VECTOR;
C_MASK3 : STD_LOGIC_VECTOR;
C_LMB_AWIDTH : INTEGER;
C_LMB_DWIDTH : INTEGER;
C_ECC : INTEGER;
C_INTERCONNECT : INTEGER;
C_FAULT_INJECT : INTEGER;
C_CE_FAILING_REGISTERS : INTEGER;
C_UE_FAILING_REGISTERS : INTEGER;
C_ECC_STATUS_REGISTERS : INTEGER;
C_ECC_ONOFF_REGISTER : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER;
C_CE_COUNTER_WIDTH : INTEGER;
C_WRITE_ACCESS : INTEGER;
C_BRAM_AWIDTH : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
PORT (
LMB_Clk : IN STD_LOGIC;
LMB_Rst : IN STD_LOGIC;
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_AddrStrobe : IN STD_LOGIC;
LMB_ReadStrobe : IN STD_LOGIC;
LMB_WriteStrobe : IN STD_LOGIC;
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : OUT STD_LOGIC;
Sl_Wait : OUT STD_LOGIC;
Sl_UE : OUT STD_LOGIC;
Sl_CE : OUT STD_LOGIC;
LMB1_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB1_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB1_AddrStrobe : IN STD_LOGIC;
LMB1_ReadStrobe : IN STD_LOGIC;
LMB1_WriteStrobe : IN STD_LOGIC;
LMB1_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl1_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl1_Ready : OUT STD_LOGIC;
Sl1_Wait : OUT STD_LOGIC;
Sl1_UE : OUT STD_LOGIC;
Sl1_CE : OUT STD_LOGIC;
LMB2_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB2_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB2_AddrStrobe : IN STD_LOGIC;
LMB2_ReadStrobe : IN STD_LOGIC;
LMB2_WriteStrobe : IN STD_LOGIC;
LMB2_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl2_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl2_Ready : OUT STD_LOGIC;
Sl2_Wait : OUT STD_LOGIC;
Sl2_UE : OUT STD_LOGIC;
Sl2_CE : OUT STD_LOGIC;
LMB3_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB3_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB3_AddrStrobe : IN STD_LOGIC;
LMB3_ReadStrobe : IN STD_LOGIC;
LMB3_WriteStrobe : IN STD_LOGIC;
LMB3_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl3_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl3_Ready : OUT STD_LOGIC;
Sl3_Wait : OUT STD_LOGIC;
Sl3_UE : OUT STD_LOGIC;
Sl3_CE : OUT STD_LOGIC;
BRAM_Rst_A : OUT STD_LOGIC;
BRAM_Clk_A : OUT STD_LOGIC;
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_EN_A : OUT STD_LOGIC;
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31);
S_AXI_CTRL_ACLK : IN STD_LOGIC;
S_AXI_CTRL_ARESETN : IN STD_LOGIC;
S_AXI_CTRL_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_AWVALID : IN STD_LOGIC;
S_AXI_CTRL_AWREADY : OUT STD_LOGIC;
S_AXI_CTRL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_CTRL_WVALID : IN STD_LOGIC;
S_AXI_CTRL_WREADY : OUT STD_LOGIC;
S_AXI_CTRL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_CTRL_BVALID : OUT STD_LOGIC;
S_AXI_CTRL_BREADY : IN STD_LOGIC;
S_AXI_CTRL_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_ARVALID : IN STD_LOGIC;
S_AXI_CTRL_ARREADY : OUT STD_LOGIC;
S_AXI_CTRL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_CTRL_RVALID : OUT STD_LOGIC;
S_AXI_CTRL_RREADY : IN STD_LOGIC;
UE : OUT STD_LOGIC;
CE : OUT STD_LOGIC;
Interrupt : OUT STD_LOGIC
);
END COMPONENT lmb_bram_if_cntlr;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_dlmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "lmb_bram_if_cntlr,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_dlmb_bram_if_cntlr_0_arch : ARCHITECTURE IS "system_dlmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_dlmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "system_dlmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_bram_if_cntlr,x_ipVersion=4.0,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_HIGHADDR=0x0000000000007FFF,C_BASEADDR=0x0000000000000000,C_NUM_LMB=1,C_MASK=0x00000000c0000000,C_MASK1=0x0000000000800000,C_MASK2=0x0000000000800000,C_MASK3=0x0000000000800000,C_LMB_AWIDTH=32,C_LMB_DWIDTH=32,C_ECC=0,C_INTERCONNECT=0,C_FAULT_INJECT=0,C_CE_FAILING_REGIS" &
"TERS=0,C_UE_FAILING_REGISTERS=0,C_ECC_STATUS_REGISTERS=0,C_ECC_ONOFF_REGISTER=0,C_ECC_ONOFF_RESET_VALUE=1,C_CE_COUNTER_WIDTH=0,C_WRITE_ACCESS=2,C_BRAM_AWIDTH=32,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB BE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READY";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB CE";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Rst_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT RST";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Clk_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT CLK";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Addr_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_EN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT EN";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_WEN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT WE";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Dout_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DIN";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Din_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT";
BEGIN
U0 : lmb_bram_if_cntlr
GENERIC MAP (
C_FAMILY => "artix7",
C_HIGHADDR => X"0000000000007FFF",
C_BASEADDR => X"0000000000000000",
C_NUM_LMB => 1,
C_MASK => X"00000000c0000000",
C_MASK1 => X"0000000000800000",
C_MASK2 => X"0000000000800000",
C_MASK3 => X"0000000000800000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_BRAM_AWIDTH => 32,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
PORT MAP (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB1_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB1_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB1_AddrStrobe => '0',
LMB1_ReadStrobe => '0',
LMB1_WriteStrobe => '0',
LMB1_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
LMB2_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB2_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB2_AddrStrobe => '0',
LMB2_ReadStrobe => '0',
LMB2_WriteStrobe => '0',
LMB2_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
LMB3_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB3_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB3_AddrStrobe => '0',
LMB3_ReadStrobe => '0',
LMB3_WriteStrobe => '0',
LMB3_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Dout_A => BRAM_Dout_A,
BRAM_Din_A => BRAM_Din_A,
S_AXI_CTRL_ACLK => '0',
S_AXI_CTRL_ARESETN => '0',
S_AXI_CTRL_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_AWVALID => '0',
S_AXI_CTRL_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_CTRL_WVALID => '0',
S_AXI_CTRL_BREADY => '0',
S_AXI_CTRL_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_ARVALID => '0',
S_AXI_CTRL_RREADY => '0'
);
END system_dlmb_bram_if_cntlr_0_arch;
|
apache-2.0
|
2c543041fde58a37f6a0dd16d85f659a
| 0.664012 | 3.176874 | false | false | false | false |
jeffmagina/ECE368
|
Lab2/RISC Machine SSEG_for lab/alu_arithmetic_unit.vhd
| 3 | 1,602 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Arithmetic_Unit
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Artithmetic Unit
-- Operations - Add, Sub, Addi
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arith_Unit is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC_VECTOR (2 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
RESULT : out STD_LOGIC_VECTOR (7 downto 0));
end Arith_Unit;
architecture Combinational of Arith_Unit is
signal a1, b1 : STD_LOGIC_VECTOR (8 downto 0) := (OTHERS => '0');
signal arith : STD_LOGIC_VECTOR (8 downto 0) := (OTHERS => '0');
begin
-- Give extra bit to accound for carry,overflow,negative
a1 <= '0' & A;
b1 <= '0' & B;
with OP select
arith <=
a1 + b1 when "000", -- ADD
a1 - b1 when "001", -- SUB
a1 + b1 when "101", -- ADDI
a1 + b1 when OTHERS;
CCR(3) <= arith(7); -- Negative
CCR(2) <= '1' when arith(7 downto 0) = x"0000" else '0'; -- Zero
CCR(1) <= arith(8) xor arith(7); -- Overflow
CCR(0) <= arith(8); --Carry
RESULT <= arith(7 downto 0);
end Combinational;
|
mit
|
0f88d7bc39cbb51b31597ab239eb63ae
| 0.553683 | 3.520879 | false | false | false | false |
jeffmagina/ECE368
|
Project1/FORWARDING_UNIT/Forwarding_unit.vhd
| 1 | 1,229 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:42:15 04/07/2015
-- Design Name:
-- Module Name: Forwarding_unit - Dataflow
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Forwarding_unit is
Port( OPA_REG : IN STD_LOGIC_VECTOR(3 downto 0);
EX_FWD_REG : IN STD_LOGIC_VECTOR(3 downto 0);
WB_FWD_REG : IN STD_LOGIC_VECTOR(3 downto 0);
FWD_SEL : IN STD_LOGIC_VECTOR(1 downto 0);
FWD_MUX_SEL : OUT STD_LOGIC_VECTOR(1 downto 0));
end Forwarding_unit;
architecture Dataflow of Forwarding_unit is
signal PRIORITY : STD_LOGIC_VECTOR(1 downto 0);
begin
PRIORITY <= "10" when FWD_SEL = "00" AND OPA_REG = WB_FWD_REG ELSE
"00";
FWD_MUX_SEL <= "01" when FWD_SEL = "01" ELSE
"10" when PRIORITY = "10" AND OPA_REG /= EX_FWD_REG ELSE
"11" when OPA_REG = EX_FWD_REG ELSE
"00";
end Dataflow;
|
mit
|
b9645b6e1c673a2c32b00c1d6ad4bf21
| 0.526444 | 3.511429 | false | false | false | false |
jeffmagina/ECE368
|
Lab2/RISC Machine SSEG_for lab/DEBUG_CONTROLLER.vhd
| 2 | 2,079 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:26:35 02/25/2015
-- Design Name:
-- Module Name: DEBUG_CONTROLLER - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DEBUG_CONTROLLER is
Port( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
PS2_CLK : inout STD_LOGIC;
PS2_DATA : inout STD_LOGIC;
SEG : out STD_LOGIC_VECTOR (6 downto 0);
DP : out STD_LOGIC;
AN : out STD_LOGIC_VECTOR (3 downto 0));
end DEBUG_CONTROLLER;
architecture Structural of DEBUG_CONTROLLER is
signal RD : STD_LOGIC := '0';
signal WE : STD_LOGIC := '0';
signal KEY_DATA : STD_LOGIC_VECTOR (7 downto 0);
signal TO_SEG : STD_LOGIC_VECTOR(15 downto 0);
signal cen : STD_LOGIC := '0';
signal enl : STD_LOGIC := '1';
signal dpc : STD_LOGIC_VECTOR (3 downto 0) := "1111";
begin
U1: entity work.KEYBOARD_CONTROLLER
Port MAP ( CLK => CLK,
RST => RST,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
ASCII_OUT => KEY_DATA,
ASCII_RD => RD,
ASCII_WE => WE);
U2: entity work.ASCII_BUFFER
port MAP(
ASCII_DATA => KEY_DATA,
ASCII_RD => RD,
ASCII_WE => WE,
CLK => CLK,
RST => RST,
ASCII_BUFF => TO_SEG);
SSeg: entity work.SSegDriver
port map( CLK => CLK,
RST => '0',
EN => enl,
SEG_0 => TO_SEG(15 downto 12),
SEG_1 => TO_SEG(11 downto 8),
SEG_2 => TO_SEG(7 downto 4),
SEG_3 => TO_SEG(3 downto 0),
DP_CTRL => dpc,
COL_EN => cen,
SEG_OUT => SEG,
DP_OUT => DP,
AN_OUT => AN);
end Structural;
|
mit
|
b3ba4d9c24212a4c7cb8803c4c9cd1dd
| 0.499759 | 3.342444 | false | false | false | false |
KPU-RISC/KPU
|
VHDL/SAR8Bit.vhd
| 1 | 1,353 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07/17/2015 02:58:32 PM
-- Design Name:
-- Module Name: SAR8Bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SAR8Bit is
Port
(
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
Cout : out BIT -- Carry-out flag
);
end SAR8Bit;
architecture Behavioral of SAR8Bit is
begin
Cout <= Input(0);
Output(0) <= Input(1);
Output(1) <= Input(2);
Output(2) <= Input(3);
Output(3) <= Input(4);
Output(4) <= Input(5);
Output(5) <= Input(6);
Output(6) <= Input(7);
Output(7) <= Input(7);
end Behavioral;
|
mit
|
16b054ce25c9064bac6d2f57b334f81c
| 0.548411 | 3.768802 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 3/RF_tb.vhd
| 1 | 2,182 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY RF_tb IS
END RF_tb;
ARCHITECTURE behavior OF RF_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RF
PORT(
rs1 : IN std_logic_vector(5 downto 0);
rs2 : IN std_logic_vector(5 downto 0);
rd : IN std_logic_vector(5 downto 0);
DWR : IN std_logic_vector(31 downto 0);
rst : IN std_logic;
Crs1 : OUT std_logic_vector(31 downto 0);
Crs2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal rs1 : std_logic_vector(5 downto 0) := (others => '0');
signal rs2 : std_logic_vector(5 downto 0) := (others => '0');
signal rd : std_logic_vector(5 downto 0) := (others => '0');
signal DWR : std_logic_vector(31 downto 0) := (others => '0');
signal rst : std_logic := '0';
--Outputs
signal Crs1 : std_logic_vector(31 downto 0);
signal Crs2 : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RF PORT MAP (
rs1 => rs1,
rs2 => rs2,
rd => rd,
DWR => DWR,
rst => rst,
Crs1 => Crs1,
Crs2 => Crs2
);
-- Stimulus process
stim_proc: process
begin
rst<='1';
wait for 20 ns;
rst<='0';
rs1<=(others=>'0');
rs2<="001000";
rd<="000001";
DWR<="00000000000000000000000000001000";
wait for 40 ns;
rs1<=(others=>'0');
rs2<="011001";
rd<="000010";
DWR<="11111111111111111111111111111001";
wait for 40 ns;
rs1<="000001";
rs2<="000010";
rd<="001000";
DWR<="00000000000001000101111011111111";
wait for 40 ns;
rd<="001001";
DWR<="00000000000000000000000000001000";
wait for 40 ns;
rd<="001010";
DWR<="00000000000000000000000000001001";
wait for 40 ns;
rd<="001011";
DWR<="00000000000000000000000000001010";
wait for 40 ns;
rd<="001100";
DWR<="00000000000000000000000000001011";
wait for 40 ns;
rst<='1';
rs1<="000001";
rs2<="000010";
rd<="001101";
DWR<="00000000000000000000000000001100";
wait;
end process;
END;
|
mit
|
3a0b4d932f969ed3b7db887e495c8b59
| 0.568286 | 3.496795 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_microblaze_0_axi_intc_0/synth/system_microblaze_0_axi_intc_0.vhd
| 1 | 11,615 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_intc:4.1
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_intc_v4_1_9;
USE axi_intc_v4_1_9.axi_intc;
ENTITY system_microblaze_0_axi_intc_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
intr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
processor_clk : IN STD_LOGIC;
processor_rst : IN STD_LOGIC;
irq : OUT STD_LOGIC;
processor_ack : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
interrupt_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_microblaze_0_axi_intc_0;
ARCHITECTURE system_microblaze_0_axi_intc_0_arch OF system_microblaze_0_axi_intc_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_microblaze_0_axi_intc_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_intc IS
GENERIC (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_NUM_INTR_INPUTS : INTEGER;
C_NUM_SW_INTR : INTEGER;
C_KIND_OF_INTR : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_KIND_OF_EDGE : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_KIND_OF_LVL : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_ASYNC_INTR : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_NUM_SYNC_FF : INTEGER;
C_IVAR_RESET_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_ENABLE_ASYNC : INTEGER;
C_HAS_IPR : INTEGER;
C_HAS_SIE : INTEGER;
C_HAS_CIE : INTEGER;
C_HAS_IVR : INTEGER;
C_HAS_ILR : INTEGER;
C_IRQ_IS_LEVEL : INTEGER;
C_IRQ_ACTIVE : STD_LOGIC;
C_DISABLE_SYNCHRONIZERS : INTEGER;
C_MB_CLK_NOT_CONNECTED : INTEGER;
C_HAS_FAST : INTEGER;
C_EN_CASCADE_MODE : INTEGER;
C_CASCADE_MASTER : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
intr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
processor_clk : IN STD_LOGIC;
processor_rst : IN STD_LOGIC;
irq : OUT STD_LOGIC;
processor_ack : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
interrupt_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
irq_in : IN STD_LOGIC;
interrupt_address_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
processor_ack_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT axi_intc;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_microblaze_0_axi_intc_0_arch: ARCHITECTURE IS "axi_intc,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_microblaze_0_axi_intc_0_arch : ARCHITECTURE IS "system_microblaze_0_axi_intc_0,axi_intc,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_microblaze_0_axi_intc_0_arch: ARCHITECTURE IS "system_microblaze_0_axi_intc_0,axi_intc,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_intc,x_ipVersion=4.1,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_INSTANCE=system_microblaze_0_axi_intc_0,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_NUM_INTR_INPUTS=7,C_NUM_SW_INTR=0,C_KIND_OF_INTR=0xffffffb2,C_KIND_OF_EDGE=0xFFFFFFFF,C_KIND_OF_LVL=0xFFFFFFFF,C_ASYNC_INTR=0xFFFFFFC2,C_NUM_SYNC_FF=2,C_IVAR_RESET_VALUE=0x00000010,C_ENABLE_ASYNC=0,C_" &
"HAS_IPR=1,C_HAS_SIE=1,C_HAS_CIE=1,C_HAS_IVR=1,C_HAS_ILR=0,C_IRQ_IS_LEVEL=1,C_IRQ_ACTIVE=0x1,C_DISABLE_SYNCHRONIZERS=0,C_MB_CLK_NOT_CONNECTED=1,C_HAS_FAST=1,C_EN_CASCADE_MODE=0,C_CASCADE_MASTER=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_resetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RREADY";
ATTRIBUTE X_INTERFACE_INFO OF intr: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt_input INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF processor_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 proc_clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF processor_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 proc_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF irq: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 interrupt INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF processor_ack: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 interrupt ACK";
ATTRIBUTE X_INTERFACE_INFO OF interrupt_address: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 interrupt ADDRESS";
BEGIN
U0 : axi_intc
GENERIC MAP (
C_FAMILY => "artix7",
C_INSTANCE => "system_microblaze_0_axi_intc_0",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_NUM_INTR_INPUTS => 7,
C_NUM_SW_INTR => 0,
C_KIND_OF_INTR => X"ffffffb2",
C_KIND_OF_EDGE => X"FFFFFFFF",
C_KIND_OF_LVL => X"FFFFFFFF",
C_ASYNC_INTR => X"FFFFFFC2",
C_NUM_SYNC_FF => 2,
C_IVAR_RESET_VALUE => X"00000010",
C_ENABLE_ASYNC => 0,
C_HAS_IPR => 1,
C_HAS_SIE => 1,
C_HAS_CIE => 1,
C_HAS_IVR => 1,
C_HAS_ILR => 0,
C_IRQ_IS_LEVEL => 1,
C_IRQ_ACTIVE => '1',
C_DISABLE_SYNCHRONIZERS => 0,
C_MB_CLK_NOT_CONNECTED => 1,
C_HAS_FAST => 1,
C_EN_CASCADE_MODE => 0,
C_CASCADE_MASTER => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
intr => intr,
processor_clk => processor_clk,
processor_rst => processor_rst,
irq => irq,
processor_ack => processor_ack,
interrupt_address => interrupt_address,
irq_in => '0',
interrupt_address_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END system_microblaze_0_axi_intc_0_arch;
|
apache-2.0
|
c37054896ea614f99eb164ddae1ff58c
| 0.685493 | 3.205907 | false | false | false | false |
alextrem/red-diamond
|
fpga/vhdl/ahb_slave.vhd
| 1 | 2,011 |
------------------------------------------------------------------------------
-- Company: Red Diamond
-- Engineer: Alexander Geissler
--
-- Create Date: 23:40:00 11/19/2016
-- Design Name:
-- Project Name: red-diamond
-- Target Device: EP4CE22C8N
-- Tool Versions: 17.0
-- Description: AHB slave interface
--
-- Dependencies:
--
-- Revision:
-- Revision 0.1 - File created
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.amba.all;
entity ahb_slave is
port(
hclk : in std_ulogic;
hreset_n : in std_ulogic;
ahb_in : in t_ahb_slave_in;
ahb_out : out t_ahb_slave_out
);
end entity;
architecture rtl of ahb_slave is
type t_ahb_state is (ADDRESS, DATA, FINISH);
signal AHBSTATE : t_ahb_state;
type t_register is record
hwrite : std_ulogic;
haddr : std_logic_vector(31 downto 0);
hsize : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
hreadyout : std_ulogic;
state : t_ahb_state;
end record;
--
signal r, r_next : t_register;
begin
-- Cominatorical process
comb_proc : process(ahb_in, r, hreset_n)
variable v : t_register;
begin
v := r;
case AHBSTATE is
when ADDRESS => -- Address state
if ahb_in.hready = '1' and ahb_in.hsel = '1' and ahb_in.htrans(1)= '1' then
v.haddr := ahb_in.haddr; -- store address
v.hwrite := ahb_in.hwrite; -- store write
v.hreadyout := '0';
v.state := DATA;
end if;
when DATA => -- Data state
if r.hwrite = '1' then
--ahb_write_data();
else
--ahb_read_word();
v.hreadyout := '1';
end if;
when FINISH =>
when others =>
null;
end case;
if (hreset_n = '0') then
v.state := ADDRESS;
end if;
r <= v;
ahb_out.hreadyout <= v.hreadyout;
end process comb_proc;
end rtl;
|
gpl-3.0
|
c36f2681b5fa86ff9103ded1dcde45e7
| 0.519642 | 3.503484 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_rst_mig_7series_0_83M_0/synth/system_rst_mig_7series_0_83M_0.vhd
| 1 | 6,653 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rst_mig_7series_0_83M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_rst_mig_7series_0_83M_0;
ARCHITECTURE system_rst_mig_7series_0_83M_0_arch OF system_rst_mig_7series_0_83M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rst_mig_7series_0_83M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_rst_mig_7series_0_83M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_rst_mig_7series_0_83M_0_arch : ARCHITECTURE IS "system_rst_mig_7series_0_83M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_rst_mig_7series_0_83M_0_arch: ARCHITECTURE IS "system_rst_mig_7series_0_83M_0,proc_sys_reset,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=1,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "artix7",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '1',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END system_rst_mig_7series_0_83M_0_arch;
|
apache-2.0
|
361f6d61492405dbd8f9833666c5732e
| 0.714415 | 3.440021 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_gpio_sw_0/synth/system_axi_gpio_sw_0.vhd
| 1 | 9,954 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_13;
USE axi_gpio_v2_0_13.axi_gpio;
ENTITY system_axi_gpio_sw_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END system_axi_gpio_sw_0;
ARCHITECTURE system_axi_gpio_sw_0_arch OF system_axi_gpio_sw_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_gpio_sw_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_axi_gpio_sw_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_axi_gpio_sw_0_arch : ARCHITECTURE IS "system_axi_gpio_sw_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_axi_gpio_sw_0_arch: ARCHITECTURE IS "system_axi_gpio_sw_0,axi_gpio,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=13,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=4,C_GPIO2_WIDTH=4,C_ALL_INPUTS=1,C_ALL_INPUTS_2=1,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=1,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=1,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 4,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 1,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 1,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 1,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
ip2intc_irpt => ip2intc_irpt,
gpio_io_i => gpio_io_i,
gpio2_io_i => gpio2_io_i
);
END system_axi_gpio_sw_0_arch;
|
apache-2.0
|
014eab8c532d6fc48c0a210c2b461bdf
| 0.68907 | 3.17512 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_xadc_wiz_0_0/system_xadc_wiz_0_0_axi_xadc.vhd
| 1 | 50,598 |
-------------------------------------------------------------------------------
-- system_xadc_wiz_0_0_axi_xadc.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
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-- ** Copyright 2010, 2013 Xilinx, Inc. **
-- ** All rights reserved. **
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-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
-------------------------------------------------------------------------------
-- File : system_xadc_wiz_0_0_axi_xadc.vhd
-- Version : v3.0
-- Description : XADC macro with AXI bus interface
-- Standard : VHDL-93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Structure:
-- axi_xadc.vhd
-- -system_xadc_wiz_0_0_xadc_core_drp.vhd
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.conv_std_logic_vector;
use IEEE.std_logic_arith.unsigned;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_misc.and_reduce;
use IEEE.std_logic_misc.or_reduce;
library work;
use work.system_xadc_wiz_0_0_ipif_pkg.all;
use work.system_xadc_wiz_0_0_soft_reset;
use work.system_xadc_wiz_0_0_ipif_pkg.calc_num_ce;
use work.system_xadc_wiz_0_0_ipif_pkg.INTEGER_ARRAY_TYPE;
use work.system_xadc_wiz_0_0_ipif_pkg.SLV64_ARRAY_TYPE;
use work.system_xadc_wiz_0_0_ipif_pkg.INTR_POS_EDGE_DETECT;
use work.system_xadc_wiz_0_0_proc_common_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
--------------------
-- AXI LITE Generics
--------------------
-- C_BASEADDR -- Base Address
-- C_HIGHADDR -- high address
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_FAMILY -- Target FPGA family, Virtex 6 only
-- C_INCLUDE_INTR -- inclusion of interrupt
-- C_SIM_MONITOR_FILE -- simulation file
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-------------------------------------------------------------------------------
-- Note: the unused signals in the port name lists are not listed here.
-------------------------------------------------------------------------------
-- SYSMON EXTERNAL INTERFACE -- INPUT Signals
-------------------------------------------------------------------------------
-- VAUXN -- Sixteen auxiliary analog input pairs
-- VAUXP -- low bandwidth differential analog inputs
-- CONVST -- Conversion start signal for event-driven sampling mode
-------------------------------------------------------------------------------
-- SYSMON EXTERNAL INTERFACE -- OUTPUT Signals
-------------------------------------------------------------------------------
-- ip2intc_irpt -- Interrupt to processor
-- alarm_out -- SYSMON alarm output signals of the hard macro
-------------------------------------------------------------------------------
entity system_xadc_wiz_0_0_axi_xadc is
generic
(
-----------------------------------------
-- C_BASEADDR : std_logic_vector := X"FFFF_FFFF";
-- C_HIGHADDR : std_logic_vector := X"0000_0000";
-----------------------------------------
-- AXI slave single block generics
C_INSTANCE : string := "system_xadc_wiz_0_0_axi_xadc";
C_FAMILY : string := "virtex7";
C_S_AXI_ADDR_WIDTH : integer range 2 to 32 := 11;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
-----------------------------------------
-- SYSMON Generics
C_INCLUDE_INTR : integer range 0 to 1 := 1;
C_SIM_MONITOR_FILE : string := "design.txt"
);
port
(
-- System interface
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
-- AXI Write address channel signals
s_axi_awaddr : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
-- AXI Write data channel signals
s_axi_wdata : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_wstrb : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
-- AXI Write response channel signals
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
-- AXI Read address channel signals
s_axi_araddr : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
-- AXI Read address channel signals
s_axi_rdata : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Input to the system from the axi_xadc core
ip2intc_irpt : out std_logic;
-- XADC External interface signals
-- Conversion start control signal for Event driven mode
vauxp0 : in STD_LOGIC; -- Auxiliary Channel 0
vauxn0 : in STD_LOGIC;
vauxp1 : in STD_LOGIC; -- Auxiliary Channel 1
vauxn1 : in STD_LOGIC;
vauxp2 : in STD_LOGIC; -- Auxiliary Channel 2
vauxn2 : in STD_LOGIC;
vauxp4 : in STD_LOGIC; -- Auxiliary Channel 4
vauxn4 : in STD_LOGIC;
vauxp5 : in STD_LOGIC; -- Auxiliary Channel 5
vauxn5 : in STD_LOGIC;
vauxp6 : in STD_LOGIC; -- Auxiliary Channel 6
vauxn6 : in STD_LOGIC;
vauxp7 : in STD_LOGIC; -- Auxiliary Channel 7
vauxn7 : in STD_LOGIC;
vauxp9 : in STD_LOGIC; -- Auxiliary Channel 9
vauxn9 : in STD_LOGIC;
vauxp10 : in STD_LOGIC; -- Auxiliary Channel 10
vauxn10 : in STD_LOGIC;
vauxp12 : in STD_LOGIC; -- Auxiliary Channel 12
vauxn12 : in STD_LOGIC;
vauxp13 : in STD_LOGIC; -- Auxiliary Channel 13
vauxn13 : in STD_LOGIC;
vauxp14 : in STD_LOGIC; -- Auxiliary Channel 14
vauxn14 : in STD_LOGIC;
vauxp15 : in STD_LOGIC; -- Auxiliary Channel 15
vauxn15 : in STD_LOGIC;
busy_out : out STD_LOGIC; -- ADC Busy signal
channel_out : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs
eoc_out : out STD_LOGIC; -- End of Conversion Signal
eos_out : out STD_LOGIC; -- End of Sequence Signal
alarm_out : out STD_LOGIC_VECTOR (7 downto 0); -- OR'ed output of all the Alarms
temp_out : out std_logic_vector(11 downto 0);
vp_in : in STD_LOGIC; -- Dedicated Analog Input Pair
vn_in : in STD_LOGIC
);
-------------------------------------------------------------------------------
-- Attributes
-------------------------------------------------------------------------------
-- Fan-Out attributes for XST
ATTRIBUTE MAX_FANOUT : string;
ATTRIBUTE MAX_FANOUT of s_axi_aclk : signal is "10000";
ATTRIBUTE MAX_FANOUT of s_axi_aresetn : signal is "10000";
-----------------------------------------------------------------
-- Start of PSFUtil MPD attributes
-----------------------------------------------------------------
ATTRIBUTE HDL : string;
ATTRIBUTE HDL of system_xadc_wiz_0_0_axi_xadc : entity is "VHDL";
ATTRIBUTE IPTYPE : string;
ATTRIBUTE IPTYPE of system_xadc_wiz_0_0_axi_xadc : entity is "PERIPHERAL";
ATTRIBUTE IP_GROUP : string;
ATTRIBUTE IP_GROUP of system_xadc_wiz_0_0_axi_xadc : entity is "LOGICORE";
ATTRIBUTE SIGIS : string;
ATTRIBUTE SIGIS of s_axi_aclk : signal is "Clk";
ATTRIBUTE SIGIS of s_axi_aresetn : signal is "Rst";
ATTRIBUTE SIGIS of ip2intc_irpt : signal is "INTR_LEVEL_HIGH";
-----------------------------------------------------------------
-- end of PSFUtil MPD attributes
-----------------------------------------------------------------
end entity system_xadc_wiz_0_0_axi_xadc;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture imp of system_xadc_wiz_0_0_axi_xadc is
component system_xadc_wiz_0_0_xadc_core_drp
generic
(
----------------
C_S_AXI_ADDR_WIDTH : integer;
C_S_AXI_DATA_WIDTH : integer;
C_FAMILY : string;
----------------
CE_NUMBERS : integer;
IP_INTR_NUM : integer;
C_SIM_MONITOR_FILE : string ;
----------------
MUX_ADDR_NO : integer
);
port
(
-- IP Interconnect (IPIC) port signals ---------
Bus2IP_Clk : in std_logic;
Bus2IP_Rst : in std_logic;
-- Bus 2 IP IPIC interface
Bus2IP_RdCE : in std_logic_vector(0 to CE_NUMBERS-1);
Bus2IP_WrCE : in std_logic_vector(0 to CE_NUMBERS-1);
Bus2IP_Addr : in std_logic_vector(0 to (C_S_AXI_ADDR_WIDTH-1));
Bus2IP_Data : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
-- IP 2 Bus IPIC interface
Sysmon_IP2Bus_Data : out std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
Sysmon_IP2Bus_WrAck : out std_logic;
Sysmon_IP2Bus_RdAck : out std_logic;
---------------- interrupt interface with the system -----------
Interrupt_status : out std_logic_vector(0 to IP_INTR_NUM-1);
---------------- sysmon macro interface -------------------
vauxp0 : in STD_LOGIC; -- Auxiliary Channel 0
vauxn0 : in STD_LOGIC;
vauxp1 : in STD_LOGIC; -- Auxiliary Channel 1
vauxn1 : in STD_LOGIC;
vauxp2 : in STD_LOGIC; -- Auxiliary Channel 2
vauxn2 : in STD_LOGIC;
vauxp4 : in STD_LOGIC; -- Auxiliary Channel 4
vauxn4 : in STD_LOGIC;
vauxp5 : in STD_LOGIC; -- Auxiliary Channel 5
vauxn5 : in STD_LOGIC;
vauxp6 : in STD_LOGIC; -- Auxiliary Channel 6
vauxn6 : in STD_LOGIC;
vauxp7 : in STD_LOGIC; -- Auxiliary Channel 7
vauxn7 : in STD_LOGIC;
vauxp9 : in STD_LOGIC; -- Auxiliary Channel 9
vauxn9 : in STD_LOGIC;
vauxp10 : in STD_LOGIC; -- Auxiliary Channel 10
vauxn10 : in STD_LOGIC;
vauxp12 : in STD_LOGIC; -- Auxiliary Channel 12
vauxn12 : in STD_LOGIC;
vauxp13 : in STD_LOGIC; -- Auxiliary Channel 13
vauxn13 : in STD_LOGIC;
vauxp14 : in STD_LOGIC; -- Auxiliary Channel 14
vauxn14 : in STD_LOGIC;
vauxp15 : in STD_LOGIC; -- Auxiliary Channel 15
vauxn15 : in STD_LOGIC;
busy_out : out STD_LOGIC; -- ADC Busy signal
channel_out : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs
eoc_out : out STD_LOGIC; -- End of Conversion Signal
eos_out : out STD_LOGIC; -- End of Sequence Signal
alarm_out : out STD_LOGIC_VECTOR (7 downto 0);
temp_out : out std_logic_vector(11 downto 0);
vp_in : in STD_LOGIC; -- Dedicated Analog Input Pair
vn_in : in STD_LOGIC
);
end component;
-------------------------------------------------------------------------------
-- Function Declarations starts
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function: add_intr_ard_addr_range_array
-------------------------------------------------------------------------------
-- Add the interrupt base and high address to ARD_ADDR_RANGE_ARRAY, if
-- C_INCLUDE_INTR is = 1
-------------------------------------------------------------------------------
function add_intr_ard_addr_range_array
(include_intr : integer;
USER_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE;
INTR_USER_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE
)
return SLV64_ARRAY_TYPE is
begin
if include_intr = 1 then
return INTR_USER_ARD_ADDR_RANGE_ARRAY;
else
return USER_ARD_ADDR_RANGE_ARRAY;
end if;
end function add_intr_ard_addr_range_array;
-------------------------------------------------------------------------------
-- Function: add_intr_ce_range_array
-------------------------------------------------------------------------------
-- This function is used to add the 16 interrupts in the NUM_CE range array, if
-- C_INCLUDE_INTR is = 1
-------------------------------------------------------------------------------
function add_intr_ce_range_array
(include_intr : integer;
USER_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE;
INTR_USER_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
)
return INTEGER_ARRAY_TYPE is
begin
if include_intr = 1 then
return INTR_USER_ARD_NUM_CE_ARRAY;
else
return USER_ARD_NUM_CE_ARRAY;
end if;
end function add_intr_ce_range_array;
-------------------------------------------------------------------------------
-- Function Declaration ends
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declaration Starts
-------------------------------------------------------------------------------
-- AXI lite parameters
constant C_BASEADDR : std_logic_vector := X"0000_0000";
--constant C_BASEADDR : std_logic_vector := X"FFFF_FFFF";
constant C_HIGHADDR : std_logic_vector := X"0000_0000";
constant C_S_AXI_SYSMON_MIN_SIZE : std_logic_vector(31 downto 0):= X"000003FF";
constant C_USE_WSTRB : integer := 1;
constant C_DPHASE_TIMEOUT : integer := 64;
--constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_S_AXI_ADDR_WIDTH-1)
-- := (others => '0');
constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-32-1) := (others => '0');
constant INTERRUPT_NO : natural := 17; -- changed from 10 to 17 for adding
-- falling edge interrupts
constant C_INTR_CE_NUM : integer := 16; -- this is fixed for interrupt controller
constant MUX_ADDR_NO : integer := 5; -- added for XADC
-------------------------------------------------------------------------------
-- The local register array contains
-- 1. Software Reset Register (SRR), -- address C_BASEADDR + 0x00
-- 2. Status Register (SR), -- address C_BASEADDR + 0x04
-- 3. Alarm Output Status Register (AOSR), -- address C_BASEADDR + 0x08
-- 4. CONVST Register (CONVSTR), -- address C_BASEADDR + 0x0C
-- 5. SYSMON Reset Register (SYSMONRR). -- address C_BASEADDR + 0x10
-- All registers are 32 bit width and their addresses are at word boundry.
-------------------------------------------------------------------------------
constant LOCAL_REG_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant LOCAL_REG_HIGHADDR : std_logic_vector := C_BASEADDR or X"0000001F";
-------------------------------------------------------------------------------
-- The interrupt registers to be added if C_INCLUDE_INTR = 1
-------------------------------------------------------------------------------
constant INTR_BASEADDR : std_logic_vector := C_BASEADDR or X"00000040";
constant INTR_HIGHADDR : std_logic_vector := C_BASEADDR or x"0000007F";
-------------------------------------------------------------------------------
-- The address range is devided in the range of Status & Control registers
-- there are total 128 registers. First 64 are the status and remaning 64 are
-- control registers
-------------------------------------------------------------------------------
constant REG_FILE_BASEADDR : std_logic_vector := C_BASEADDR or X"00000200";
constant REG_FILE_HIGHADDR : std_logic_vector := C_BASEADDR or X"000003FF";
-------------------------------------------------------------------------------
--The address ranges for the registers are defined in USER_ARD_ADDR_RANGE_ARRAY
-------------------------------------------------------------------------------
constant USER_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & LOCAL_REG_BASEADDR,
ZERO_ADDR_PAD & LOCAL_REG_HIGHADDR,
ZERO_ADDR_PAD & REG_FILE_BASEADDR,
ZERO_ADDR_PAD & REG_FILE_HIGHADDR
);
constant INTR_USER_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & LOCAL_REG_BASEADDR,
ZERO_ADDR_PAD & LOCAL_REG_HIGHADDR,
ZERO_ADDR_PAD & INTR_BASEADDR,
ZERO_ADDR_PAD & INTR_HIGHADDR,
ZERO_ADDR_PAD & REG_FILE_BASEADDR,
ZERO_ADDR_PAD & REG_FILE_HIGHADDR
);
-------------------------------------------------------------------------------
-- The USER_ARD_ADDR_RANGE_ARRAY is subset of ARD_ADDR_RANGE_ARRAY based on the
-- C_INCLUDE_INTR parameter value.
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
add_intr_ard_addr_range_array(
C_INCLUDE_INTR,
USER_ARD_ADDR_RANGE_ARRAY,
INTR_USER_ARD_ADDR_RANGE_ARRAY
);
-------------------------------------------------------------------------------
--The total 128 DRP register address space is divided in two 64 register arrays
--The status and control registers are equally divided in the range to generate
--the chip enable signals.
--There are some local alarm registers, conversion start registers, ip reset
--registers present in the design.
--the no. of CE's required is defined in USER_ARD_NUM_CE_ARRAY array
-------------------------------------------------------------------------------
constant USER_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 8, -- 5 chip enable + 3 dummy
-- CS_0 & CE_0 => SRR -- Addr = 00
-- CS_0 & CE_1 => SR -- Addr = 04
-- CS_0 & CE_2 => AOSR -- Addr = 08
-- CS_0 & CE_3 => CONVSTR -- Addr = 0C
-- CS_0 & CE_4 => SYSMONRR -- Addr = 10
-- CS_0 & CE_5 => dummy -- Addr = 14
-- CS_0 & CE_6 => dummy -- Addr = 18
-- CS_0 & CE_7 => dummy -- Addr = 1C
1 => 1--, -- 1 chip enable
-- CS_1 & CE_8 => 1 CE required to access DRP
);
constant INTR_USER_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 8, -- 5 chip enable + 3 dummy
-- CS_0 & CE_0 => SRR -- Addr = 00
-- CS_0 & CE_1 => SR -- Addr = 04
-- CS_0 & CE_2 => AOSR -- Addr = 08
-- CS_0 & CE_3 => CONVSTR -- Addr = 0C
-- CS_0 & CE_4 => SYSMONRR -- Addr = 10
-- CS_0 & CE_5 => dummy -- Addr = 14
-- CS_0 & CE_6 => dummy -- Addr = 18
-- CS_0 & CE_7 => dummy -- Addr = 1C
1 => 16, -- 16 chip enable
-- CS_1 & CE_15 => GIER -- Addr = 5C
-- CS_1 & CE_16 => IPISR -- Addr = 60
-- CS_1 & CE_18 => IPIER -- Addr = 68
-- Following commented code is for reference with execution of above function
2 => 1 -- 1 chip enable -- addr = 200 to 3FF
-- CS_2 & CE_24 => 1 CE required to access DRP
);
-------------------------------------------------------------------------------
-- The USER_ARD_NUM_CE_ARRAY is subset of ARD_NUM_CE_ARRAY based on the
-- C_INCLUDE_INTR parameter value.
-------------------------------------------------------------------------------
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
add_intr_ce_range_array(
C_INCLUDE_INTR,
USER_ARD_NUM_CE_ARRAY,
INTR_USER_ARD_NUM_CE_ARRAY
);
-------------------------------------------------------------------------------
-- Eight interrupts
-------------------------------------------------------------------------------
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to INTERRUPT_NO-1):=
(
others => INTR_POS_EDGE_DETECT
);
-------------------------------------------------------------------------------
-- Calculating index for interrupt logic
-------------------------------------------------------------------------------
constant SWRESET : natural := 0;
constant INTR_LO : natural := 0;
constant INTR_HI : natural := 15;
constant CS_NUMBERS : integer :=((ARD_ADDR_RANGE_ARRAY'LENGTH/2));
constant RD_CE_NUMBERS : integer :=(calc_num_ce(ARD_NUM_CE_ARRAY));
constant WR_CE_NUMBERS : integer :=(calc_num_ce(ARD_NUM_CE_ARRAY));
constant IP_INTR_MODE_ARRAY_NUM : integer := IP_INTR_MODE_ARRAY'length;
constant RDCE_WRCE_SYSMON_CORE : integer := 9;
--------------------------------------------------------------------------------
-- Constant Declaration Ends
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Signal and Type Declarations
--------------------------------------------------------------------------------
--bus2ip signals
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
---
signal bus2ip_rdce : std_logic_vector((RD_CE_NUMBERS-1)downto 0);
signal bus2ip_rdce_int : std_logic_vector(0 to (RD_CE_NUMBERS-1));
signal bus2ip_rdce_xadc_core : std_logic_vector(0 to (RDCE_WRCE_SYSMON_CORE-1));
---
signal bus2ip_wrce : std_logic_vector((WR_CE_NUMBERS-1)downto 0);
signal bus2ip_wrce_int : std_logic_vector(0 to (WR_CE_NUMBERS-1));
signal bus2ip_wrce_xadc_core : std_logic_vector(0 to (RDCE_WRCE_SYSMON_CORE-1));
---
signal bus2ip_addr : std_logic_vector((C_S_AXI_ADDR_WIDTH-1)downto 0);
signal bus2ip_addr_int : std_logic_vector(0 to (C_S_AXI_ADDR_WIDTH-1));
---
signal bus2ip_be : std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1)downto 0);
signal bus2ip_be_int : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH/8)-1);
---
signal bus2ip_data : std_logic_vector(((C_S_AXI_DATA_WIDTH)-1)downto 0);
signal bus2ip_data_int : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
-- ip2bus signals
signal ip2bus_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1)downto 0)
:= (others => '0');
signal ip2bus_data_int : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
signal ip2bus_data_int1 : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
---
signal ip2bus_wrack : std_logic;
signal ip2bus_rdack : std_logic;
signal ip2bus_error : std_logic;
signal ip2bus_wrack_int1 : std_logic;
signal ip2bus_rdack_int1 : std_logic;
signal ip2bus_error_int1 : std_logic;
signal xadc_ip2bus_data : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
signal xadc_ip2bus_wrack : std_logic;
signal xadc_ip2bus_rdack : std_logic;
-- signal xadc_ip2bus_error : std_logic;
signal interrupt_status_i : std_logic_vector(0 to (IP_INTR_MODE_ARRAY_NUM-1));
signal intr_ip2bus_data : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
signal intr_ip2bus_wrack : std_logic;
signal intr_ip2bus_rdack : std_logic;
signal intr_ip2bus_error : std_logic;
-- Software Reset Signals
signal reset2ip_reset : std_logic := '0';
signal rst_ip2bus_wrack : std_logic;
signal rst_ip2bus_error : std_logic;
signal rst_ip2bus_rdack : std_logic;
signal rst_ip2bus_rdack_d1 : std_logic;
-- following signals are used to impleemnt the register access rule
signal and_reduce_be : std_logic;
signal partial_reg_access_error : std_logic;
signal bus2ip_reset_active_low : std_logic;
signal bus2ip_reset_active_high: std_logic;
--------------------------------------------
signal dummy_local_reg_rdack_d1 : std_logic;
signal dummy_local_reg_rdack : std_logic;
signal dummy_local_reg_wrack_d1 : std_logic;
signal dummy_local_reg_wrack : std_logic;
signal bus2ip_rdce_intr : std_logic_vector(INTR_LO to INTR_HI);
signal bus2ip_wrce_intr : std_logic_vector(INTR_LO to INTR_HI);
-------------------------------------------------------------------------------
-- Architecture begins
-------------------------------------------------------------------------------
begin
--------------------------------------------
-- INSTANTIATE AXI SLAVE SINGLE
--------------------------------------------
AXI_LITE_IPIF_I : entity work.system_xadc_wiz_0_0_axi_lite_ipif
generic map
(
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_SYSMON_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
s_axi_aclk => s_axi_aclk, -- in
s_axi_aresetn => s_axi_aresetn, -- in
s_axi_awaddr => s_axi_awaddr, -- in
s_axi_awvalid => s_axi_awvalid, -- in
s_axi_awready => s_axi_awready, -- out
s_axi_wdata => s_axi_wdata, -- in
s_axi_wstrb => s_axi_wstrb, -- in
s_axi_wvalid => s_axi_wvalid, -- in
s_axi_wready => s_axi_wready, -- out
s_axi_bresp => s_axi_bresp, -- out
s_axi_bvalid => s_axi_bvalid, -- out
s_axi_bready => s_axi_bready, -- in
s_axi_araddr => s_axi_araddr, -- in
s_axi_arvalid => s_axi_arvalid, -- in
s_axi_arready => s_axi_arready, -- out
s_axi_rdata => s_axi_rdata, -- out
s_axi_rresp => s_axi_rresp, -- out
s_axi_rvalid => s_axi_rvalid, -- out
s_axi_rready => s_axi_rready, -- in
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk, -- out
Bus2IP_Resetn => bus2ip_reset_active_low, -- out
Bus2IP_Addr => bus2ip_addr, -- out
Bus2IP_RNW => open, -- out
Bus2IP_BE => bus2ip_be, -- out
Bus2IP_CS => open, -- out
Bus2IP_RdCE => bus2ip_rdce, -- out
Bus2IP_WrCE => bus2ip_wrce, -- out
Bus2IP_Data => bus2ip_data, -- out
IP2Bus_Data => ip2bus_data, -- in
IP2Bus_WrAck => ip2bus_wrack, -- in
IP2Bus_RdAck => ip2bus_rdack, -- in
IP2Bus_Error => ip2bus_error -- in
);
-------------------------------------------------------------------------------
-------------------------------
bus2ip_rdce_int <= bus2ip_rdce;
-------------------------------
bus2ip_wrce_int <= bus2ip_wrce;
-------------------------------
ip2bus_data <= ip2bus_data_int;
-------------------------------
----------------------
--REG_RESET_FROM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RESET_FROM_IPIF: process (s_axi_aclk) is
begin
if(s_axi_aclk'event and s_axi_aclk = '1') then
bus2ip_reset_active_high <= not(bus2ip_reset_active_low);
end if;
end process REG_RESET_FROM_IPIF;
----------------------
-------------------------------------------------------------------------------
-------------------- when interrupt is used.
RDCE_WRCE_GEN_I: if (C_INCLUDE_INTR = 1) generate
-----------------
--------
begin
--------
bus2ip_rdce_intr <= bus2ip_rdce_int -- (25-16=8) to (25-2=23)
(((RD_CE_NUMBERS-C_INTR_CE_NUM)-1)to (RD_CE_NUMBERS-2));
bus2ip_wrce_intr <= bus2ip_wrce_int -- (25-16=8) to (25-2=23)
(((WR_CE_NUMBERS-C_INTR_CE_NUM)-1)to (WR_CE_NUMBERS-2));
bus2ip_rdce_xadc_core <= bus2ip_rdce_int -- 0 to ((25-16=8)-2)=7
((RD_CE_NUMBERS-RD_CE_NUMBERS)to
((RD_CE_NUMBERS-C_INTR_CE_NUM)-2)
)
& -- 24 = last rdce
bus2ip_rdce_int(RD_CE_NUMBERS-1);
bus2ip_wrce_xadc_core <= bus2ip_wrce_int -- 0 to ((25-16=8)-1)=7
((WR_CE_NUMBERS-WR_CE_NUMBERS)to
((WR_CE_NUMBERS-C_INTR_CE_NUM)-2)
)
& -- 24 = last wrce
bus2ip_wrce_int(WR_CE_NUMBERS-1);
end generate RDCE_WRCE_GEN_I;
-----------------------------
-------------------------------------------------------------------------------
-------------------- when interrupt is NOT used.
RDCE_WRCE_NOT_GEN_I: if (C_INCLUDE_INTR = 0) generate
-----------------
--------
begin
--------
bus2ip_rdce_xadc_core <= bus2ip_rdce_int;
bus2ip_wrce_xadc_core <= bus2ip_wrce_int;
end generate RDCE_WRCE_NOT_GEN_I;
---------------------------------
-------------------------------------------------------------------------------
--------------------------------------------
-- XADC_CORE_I: INSTANTIATE XADC CORE
--------------------------------------------
AXI_XADC_CORE_I : system_xadc_wiz_0_0_xadc_core_drp
generic map
(
---------------- -------------------------
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_FAMILY => C_FAMILY,
---------------- -------------------------
CE_NUMBERS => RDCE_WRCE_SYSMON_CORE,
IP_INTR_NUM => IP_INTR_MODE_ARRAY_NUM,
C_SIM_MONITOR_FILE => C_SIM_MONITOR_FILE,
------------------ -------------------------
MUX_ADDR_NO => MUX_ADDR_NO
)
port map
(
-- IP Interconnect (IPIC) port signals ---------
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Rst => reset2ip_reset,
Bus2IP_RdCE => bus2ip_rdce_xadc_core,
Bus2IP_WrCE => bus2ip_wrce_xadc_core,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_Data => bus2ip_data,
-- ip2bus signals ------------------------------
Sysmon_IP2Bus_Data => xadc_ip2bus_data,
Sysmon_IP2Bus_WrAck => xadc_ip2bus_wrack,
Sysmon_IP2Bus_RdAck => xadc_ip2bus_rdack,
Interrupt_status => interrupt_status_i,
--- external interface signals ------------------
vauxp0 => vauxp0,
vauxn0 => vauxn0,
vauxp1 => vauxp1,
vauxn1 => vauxn1,
vauxp2 => vauxp2,
vauxn2 => vauxn2,
vauxp4 => vauxp4,
vauxn4 => vauxn4,
vauxp5 => vauxp5,
vauxn5 => vauxn5,
vauxp6 => vauxp6,
vauxn6 => vauxn6,
vauxp7 => vauxp7,
vauxn7 => vauxn7,
vauxp9 => vauxp9,
vauxn9 => vauxn9,
vauxp10 => vauxp10,
vauxn10 => vauxn10,
vauxp12 => vauxp12,
vauxn12 => vauxn12,
vauxp13 => vauxp13,
vauxn13 => vauxn13,
vauxp14 => vauxp14,
vauxn14 => vauxn14,
vauxp15 => vauxp15,
vauxn15 => vauxn15,
busy_out => busy_out,
channel_out => channel_out,
eoc_out => eoc_out,
eos_out => eos_out,
alarm_out => alarm_out,
temp_out => temp_out,
vp_in => vp_in,
vn_in => vn_in
);
----------------------------------------------------------
-- SOFT_RESET_I: INSTANTIATE SOFTWARE RESET REGISTER (SRR)
----------------------------------------------------------
SOFT_RESET_I: entity work.system_xadc_wiz_0_0_soft_reset
generic map
(
C_SIPIF_DWIDTH => C_S_AXI_DATA_WIDTH,
-- Width of triggered reset in Bus Clocks
C_RESET_WIDTH => 16
)
port map
(
-- Inputs From the AXI Slave Single Bus
Bus2IP_Reset => bus2ip_reset_active_high, -- in
Bus2IP_Clk => bus2ip_clk, -- in
Bus2IP_WrCE => bus2ip_wrce_int(SWRESET), -- in
Bus2IP_Data => bus2ip_data, -- in
Bus2IP_BE => bus2ip_be, -- in
-- Final Device Reset Output
Reset2IP_Reset => reset2ip_reset, -- out
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck => rst_ip2bus_wrack, -- out
Reset2Bus_Error => rst_ip2bus_error, -- out
Reset2Bus_ToutSup => open -- out
);
------------------------------------------------------------
-- INSTANTIATE INTERRUPT CONTROLLER MODULE (IPISR,IPIER,GIER)
------------------------------------------------------------
-- INTR_CTRLR_GEN_I: Generate logic to be used to pass signals,
-------------------- when interrupt is used.
INTR_CTRLR_GEN_I: if (C_INCLUDE_INTR = 1) generate
-----------------
--------
signal bus2ip_rdce_intr_int : std_logic_vector(INTR_LO to INTR_HI);
signal bus2ip_wrce_intr_int : std_logic_vector(INTR_LO to INTR_HI);
signal dummy_bus2ip_rdce_intr : std_logic;
signal dummy_bus2ip_wrce_intr : std_logic;
signal dummy_intr_reg_rdack_d1: std_logic;
signal dummy_intr_reg_rdack : std_logic;
signal dummy_intr_reg_wrack_d1: std_logic;
signal dummy_intr_reg_wrack : std_logic;
--------
begin
--------
bus2ip_rdce_intr_int <= "0000000" &
bus2ip_rdce_intr(7 to 8) &
"0" &
bus2ip_rdce_intr(10) &
"00000";
bus2ip_wrce_intr_int <= "0000000" &
bus2ip_wrce_intr(7 to 8) &
"0" &
bus2ip_wrce_intr(10) &
"00000";
dummy_bus2ip_rdce_intr <= or_reduce(bus2ip_rdce_intr(0 to 6)) or
bus2ip_rdce_intr(9) or
or_reduce(bus2ip_rdce_intr(11 to 15));
dummy_bus2ip_wrce_intr <= or_reduce(bus2ip_wrce_intr(0 to 6)) or
bus2ip_wrce_intr(9) or
or_reduce(bus2ip_wrce_intr(11 to 15));
---------------------------------------------
DUMMY_INTR_RD_WR_ACK_GEN_PROCESS:process(Bus2IP_Clk) is
begin
if (bus2ip_clk'event and bus2ip_clk = '1') then
if (reset2ip_reset = RESET_ACTIVE) then
dummy_intr_reg_rdack_d1 <= '0';
dummy_intr_reg_rdack <= '0';
dummy_intr_reg_wrack_d1 <= '0';
dummy_intr_reg_wrack <= '0';
else
dummy_intr_reg_rdack_d1 <= dummy_bus2ip_rdce_intr;
dummy_intr_reg_rdack <= dummy_bus2ip_rdce_intr and
(not dummy_intr_reg_rdack_d1);
dummy_intr_reg_wrack_d1 <= dummy_bus2ip_wrce_intr;
dummy_intr_reg_wrack <= dummy_bus2ip_wrce_intr and
(not dummy_intr_reg_wrack_d1);
end if;
end if;
end process DUMMY_INTR_RD_WR_ACK_GEN_PROCESS;
---------------------------------------------
INTERRUPT_CONTROL_I: entity work.system_xadc_wiz_0_0_interrupt_control
generic map
(
C_NUM_CE => C_INTR_CE_NUM,
C_NUM_IPIF_IRPT_SRC => 1, -- Set to 1 to avoid null array
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_PENCODER => FALSE,
-- Specifies device ISC hierarchy
C_INCLUDE_DEV_ISC => FALSE,
C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH
)
port map
(
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => reset2ip_reset,
Bus2IP_Data => bus2ip_data,
Bus2IP_BE => bus2ip_be,
Interrupt_RdCE => bus2ip_rdce_intr_int,
Interrupt_WrCE => bus2ip_wrce_intr_int,
IPIF_Reg_Interrupts => "00", -- Tie off the unused reg intr's
IPIF_Lvl_Interrupts => "0", -- Tie off the dummy lvl intr
IP2Bus_IntrEvent => interrupt_status_i,
Intr2Bus_DevIntr => ip2intc_irpt,
Intr2Bus_DBus => intr_ip2bus_data,
Intr2Bus_WrAck => intr_ip2bus_wrack,
Intr2Bus_RdAck => intr_ip2bus_rdack,
Intr2Bus_Error => intr_ip2bus_error,
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
ip2bus_wrack_int1 <= xadc_ip2bus_wrack or
rst_ip2bus_wrack or
intr_ip2bus_wrack or
dummy_intr_reg_wrack or
dummy_local_reg_wrack;
ip2bus_rdack_int1 <= xadc_ip2bus_rdack or
rst_ip2bus_rdack or
intr_ip2bus_rdack or
dummy_intr_reg_rdack or
dummy_local_reg_rdack;
ip2bus_error_int1 <= rst_ip2bus_error or
intr_ip2bus_error or
partial_reg_access_error;
ip2bus_data_int1 <= xadc_ip2bus_data or
intr_ip2bus_data;
process (Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset = '1') then
ip2bus_wrack <= '0';
ip2bus_rdack <= '0';
ip2bus_error <= '0';
ip2bus_data_int <= (others => '0');
else
ip2bus_wrack <= ip2bus_wrack_int1;
ip2bus_rdack <= ip2bus_rdack_int1;
ip2bus_error <= ip2bus_error_int1;
ip2bus_data_int <= ip2bus_data_int1;
end if;
end if;
end process;
end generate INTR_CTRLR_GEN_I;
------------------------------
-------------------------------------------------------------------------------
-- NO_INTR_CTRLR_GEN_I: Generate logic to be used to pass signals,
----------------------- when interrupt is not used.
NO_INTR_CTRLR_GEN_I : if (C_INCLUDE_INTR = 0) generate
-----
begin
-----
ip2bus_wrack_int1 <= xadc_ip2bus_wrack or
rst_ip2bus_wrack or
dummy_local_reg_wrack;
ip2bus_rdack_int1 <= xadc_ip2bus_rdack or
rst_ip2bus_rdack or
dummy_local_reg_rdack;
ip2bus_error_int1 <= rst_ip2bus_error or
partial_reg_access_error;
ip2bus_data_int1 <= xadc_ip2bus_data;
ip2intc_irpt <= '0';
process (Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset = '1') then
ip2bus_wrack <= '0';
ip2bus_rdack <= '0';
ip2bus_error <= '0';
ip2bus_data_int <= (others => '0');
else
ip2bus_wrack <= ip2bus_wrack_int1;
ip2bus_rdack <= ip2bus_rdack_int1;
ip2bus_error <= ip2bus_error_int1;
ip2bus_data_int <= ip2bus_data_int1;
end if;
end if;
end process;
end generate NO_INTR_CTRLR_GEN_I;
---------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- SW_RESET_REG_READ_ACK_GEN_PROCESS:IMPLEMENT READ ACK LOGIC FOR SOFTWARE
-- RESET MODULE. This is dummy read as read is
-- not allowed on reset core.
------------------------------------------------------------
SW_RESET_REG_READ_ACK_GEN_PROCESS:process(Bus2IP_Clk) is
begin
if (bus2ip_clk'event and bus2ip_clk = '1') then
if (reset2ip_reset = RESET_ACTIVE) then
rst_ip2bus_rdack_d1 <= '0';
rst_ip2bus_rdack <= '0';
else
rst_ip2bus_rdack_d1 <= bus2ip_rdce_int(SWRESET);
rst_ip2bus_rdack <= bus2ip_rdce_int(SWRESET) and
(not rst_ip2bus_rdack_d1);
end if;
end if;
end process SW_RESET_REG_READ_ACK_GEN_PROCESS;
---------------------------------------------
-------------------------------------------------------------------------------
-- Logic for generation of error signal for partial word access byte enables
and_reduce_be <= and_reduce(bus2ip_be);
partial_reg_access_error <= (not and_reduce_be) and
(xadc_ip2bus_rdack or
xadc_ip2bus_wrack);
-------------------------------------------------------------------------------
--------------------------------------------------------------
---- SW_RESET_REG_READ_ACK_GEN_PROCESS:Implement read ack logic for dummy register
---- holes. This is dummy read as read/write is
---- not returning any value. In local registers.
--------------------------------------------------------------
DUMMY_REG_READ_WRITE_ACK_GEN_PROCESS:process(Bus2IP_Clk) is
begin
if (bus2ip_clk'event and bus2ip_clk = '1') then
if (reset2ip_reset = RESET_ACTIVE) then
dummy_local_reg_rdack_d1 <= '0';
dummy_local_reg_rdack <= '0';
dummy_local_reg_wrack_d1 <= '0';
dummy_local_reg_wrack <= '0';
else
dummy_local_reg_rdack_d1 <= or_reduce(bus2ip_rdce_int(5 to 7));
dummy_local_reg_rdack <= or_reduce(bus2ip_rdce_int(5 to 7)) and
(not dummy_local_reg_rdack_d1);
dummy_local_reg_wrack_d1 <= or_reduce(bus2ip_wrce_int(5 to 7));
dummy_local_reg_wrack <= or_reduce(bus2ip_wrce_int(5 to 7)) and
(not dummy_local_reg_wrack_d1);
end if;
end if;
end process DUMMY_REG_READ_WRITE_ACK_GEN_PROCESS;
-----------------------------------------------
end architecture imp;
|
apache-2.0
|
59ddbfe1282f8135fba1b9f1a9e91bb7
| 0.433021 | 4.255509 | false | false | false | false |
daniw/add
|
edk/IVK_HW/t01_hello/hdl/dlmb_cntlr_wrapper.vhd
| 1 | 14,262 |
-------------------------------------------------------------------------------
-- dlmb_cntlr_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_if_cntlr_v3_00_b;
use lmb_bram_if_cntlr_v3_00_b.all;
entity dlmb_cntlr_wrapper is
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to 31);
LMB_WriteDBus : in std_logic_vector(0 to 31);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to 3);
Sl_DBus : out std_logic_vector(0 to 31);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to 3);
BRAM_Addr_A : out std_logic_vector(0 to 31);
BRAM_Din_A : in std_logic_vector(0 to 31);
BRAM_Dout_A : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0);
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31);
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31);
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0);
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of dlmb_cntlr_wrapper : entity is "lmb_bram_if_cntlr_v3_00_b";
end dlmb_cntlr_wrapper;
architecture STRUCTURE of dlmb_cntlr_wrapper is
component lmb_bram_if_cntlr is
generic (
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_FAMILY : string;
C_MASK : std_logic_vector(0 to 31);
C_LMB_AWIDTH : integer;
C_LMB_DWIDTH : integer;
C_ECC : integer;
C_INTERCONNECT : integer;
C_FAULT_INJECT : integer;
C_CE_FAILING_REGISTERS : integer;
C_UE_FAILING_REGISTERS : integer;
C_ECC_STATUS_REGISTERS : integer;
C_ECC_ONOFF_REGISTER : integer;
C_ECC_ONOFF_RESET_VALUE : integer;
C_CE_COUNTER_WIDTH : integer;
C_WRITE_ACCESS : integer;
C_SPLB_CTRL_BASEADDR : std_logic_vector;
C_SPLB_CTRL_HIGHADDR : std_logic_vector;
C_SPLB_CTRL_AWIDTH : INTEGER;
C_SPLB_CTRL_DWIDTH : INTEGER;
C_SPLB_CTRL_P2P : INTEGER;
C_SPLB_CTRL_MID_WIDTH : INTEGER;
C_SPLB_CTRL_NUM_MASTERS : INTEGER;
C_SPLB_CTRL_SUPPORT_BURSTS : INTEGER;
C_SPLB_CTRL_NATIVE_DWIDTH : INTEGER;
C_S_AXI_CTRL_BASEADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_HIGHADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to ((C_LMB_DWIDTH+8*C_ECC)/8)-1);
BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1);
BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
Interrupt : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to (C_SPLB_CTRL_MID_WIDTH-1));
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to ((C_SPLB_CTRL_DWIDTH/8)-1));
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(((C_S_AXI_CTRL_DATA_WIDTH/8)-1) downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end component;
begin
dlmb_cntlr : lmb_bram_if_cntlr
generic map (
C_BASEADDR => X"00000000",
C_HIGHADDR => X"00007fff",
C_FAMILY => "spartan6",
C_MASK => X"80000000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_SPLB_CTRL_BASEADDR => X"FFFFFFFF",
C_SPLB_CTRL_HIGHADDR => X"00000000",
C_SPLB_CTRL_AWIDTH => 32,
C_SPLB_CTRL_DWIDTH => 32,
C_SPLB_CTRL_P2P => 0,
C_SPLB_CTRL_MID_WIDTH => 1,
C_SPLB_CTRL_NUM_MASTERS => 1,
C_SPLB_CTRL_SUPPORT_BURSTS => 0,
C_SPLB_CTRL_NATIVE_DWIDTH => 32,
C_S_AXI_CTRL_BASEADDR => X"FFFFFFFF",
C_S_AXI_CTRL_HIGHADDR => X"00000000",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
Interrupt => Interrupt,
SPLB_CTRL_PLB_ABus => SPLB_CTRL_PLB_ABus,
SPLB_CTRL_PLB_PAValid => SPLB_CTRL_PLB_PAValid,
SPLB_CTRL_PLB_masterID => SPLB_CTRL_PLB_masterID,
SPLB_CTRL_PLB_RNW => SPLB_CTRL_PLB_RNW,
SPLB_CTRL_PLB_BE => SPLB_CTRL_PLB_BE,
SPLB_CTRL_PLB_size => SPLB_CTRL_PLB_size,
SPLB_CTRL_PLB_type => SPLB_CTRL_PLB_type,
SPLB_CTRL_PLB_wrDBus => SPLB_CTRL_PLB_wrDBus,
SPLB_CTRL_Sl_addrAck => SPLB_CTRL_Sl_addrAck,
SPLB_CTRL_Sl_SSize => SPLB_CTRL_Sl_SSize,
SPLB_CTRL_Sl_wait => SPLB_CTRL_Sl_wait,
SPLB_CTRL_Sl_rearbitrate => SPLB_CTRL_Sl_rearbitrate,
SPLB_CTRL_Sl_wrDAck => SPLB_CTRL_Sl_wrDAck,
SPLB_CTRL_Sl_wrComp => SPLB_CTRL_Sl_wrComp,
SPLB_CTRL_Sl_rdDBus => SPLB_CTRL_Sl_rdDBus,
SPLB_CTRL_Sl_rdDAck => SPLB_CTRL_Sl_rdDAck,
SPLB_CTRL_Sl_rdComp => SPLB_CTRL_Sl_rdComp,
SPLB_CTRL_Sl_MBusy => SPLB_CTRL_Sl_MBusy,
SPLB_CTRL_Sl_MWrErr => SPLB_CTRL_Sl_MWrErr,
SPLB_CTRL_Sl_MRdErr => SPLB_CTRL_Sl_MRdErr,
SPLB_CTRL_PLB_UABus => SPLB_CTRL_PLB_UABus,
SPLB_CTRL_PLB_SAValid => SPLB_CTRL_PLB_SAValid,
SPLB_CTRL_PLB_rdPrim => SPLB_CTRL_PLB_rdPrim,
SPLB_CTRL_PLB_wrPrim => SPLB_CTRL_PLB_wrPrim,
SPLB_CTRL_PLB_abort => SPLB_CTRL_PLB_abort,
SPLB_CTRL_PLB_busLock => SPLB_CTRL_PLB_busLock,
SPLB_CTRL_PLB_MSize => SPLB_CTRL_PLB_MSize,
SPLB_CTRL_PLB_lockErr => SPLB_CTRL_PLB_lockErr,
SPLB_CTRL_PLB_wrBurst => SPLB_CTRL_PLB_wrBurst,
SPLB_CTRL_PLB_rdBurst => SPLB_CTRL_PLB_rdBurst,
SPLB_CTRL_PLB_wrPendReq => SPLB_CTRL_PLB_wrPendReq,
SPLB_CTRL_PLB_rdPendReq => SPLB_CTRL_PLB_rdPendReq,
SPLB_CTRL_PLB_wrPendPri => SPLB_CTRL_PLB_wrPendPri,
SPLB_CTRL_PLB_rdPendPri => SPLB_CTRL_PLB_rdPendPri,
SPLB_CTRL_PLB_reqPri => SPLB_CTRL_PLB_reqPri,
SPLB_CTRL_PLB_TAttribute => SPLB_CTRL_PLB_TAttribute,
SPLB_CTRL_Sl_wrBTerm => SPLB_CTRL_Sl_wrBTerm,
SPLB_CTRL_Sl_rdWdAddr => SPLB_CTRL_Sl_rdWdAddr,
SPLB_CTRL_Sl_rdBTerm => SPLB_CTRL_Sl_rdBTerm,
SPLB_CTRL_Sl_MIRQ => SPLB_CTRL_Sl_MIRQ,
S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK,
S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN,
S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR,
S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID,
S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY,
S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA,
S_AXI_CTRL_WSTRB => S_AXI_CTRL_WSTRB,
S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID,
S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY,
S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP,
S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID,
S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY,
S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR,
S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID,
S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY,
S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA,
S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP,
S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID,
S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY
);
end architecture STRUCTURE;
|
gpl-2.0
|
93f41aae891b632aa1ebff1be47af17a
| 0.6206 | 2.949132 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 3/principal_tb.vhd
| 1 | 1,156 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY principal_tb IS
END principal_tb;
ARCHITECTURE behavior OF principal_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MODULOPRINCIPAL
PORT(
rst : IN std_logic;
CLK : IN std_logic;
ALURESULT : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal rst : std_logic := '0';
signal CLK : std_logic := '0';
--Outputs
signal ALURESULT : std_logic_vector(31 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MODULOPRINCIPAL PORT MAP (
rst => rst,
CLK => CLK,
ALURESULT => ALURESULT
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for 20 ns;
CLK <= '1';
wait for 20 ns;
end process;
-- Stimulus process
stim_proc: process
begin
rst<='1';
wait for 20 ns;
rst<='0';
--wait for 200 ns;
--rst<='1';
wait;
end process;
END;
|
mit
|
61e3916e09b0bcb90e20270ae290d506
| 0.553633 | 3.918644 | false | false | false | false |
daniw/add
|
rot_enc/bus.vhd
| 1 | 4,767 |
-------------------------------------------------------------------------------
-- Entity: ram
-- Author: Waj
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- Data/address/control bus for simple von-Neumann MCU.
-- The bus master (CPU) can read/write in every cycle. The bus slaves are
-- assumed to have registerd read data output with an address-in to data-out
-- latency of 1 cc. The read data muxing from bus slaves to the bus master is
-- done combinationally. Thus, at the bus master interface, there results a
-- read data latency of 1 cc.
-------------------------------------------------------------------------------
-- Note on code portability:
-------------------------------------------------------------------------------
-- The address decoding logic as implemented in process P_dec below, shows how
-- to write portable code by means of a user-defined enumaration type which is
-- used as the index range for a constant array, see mcu_pkg. This allows to
-- leave the local code (in process P_dec) unchanged when the number and/or
-- base addresses of the bus slaves in the system change. Such changes then
-- need only to be made in the global definition package.
-- To generate such portable code for the rest of the functionality (e.g. for
-- the read data mux) would require to organize all data input vectors in a
-- signal array first. This would destroy the portability of the code, since it
-- requires manual code adaption when design parameter change.
-------------------------------------------------------------------------------
-- Total # of FFs: 3
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity buss is
port(rst : in std_logic;
clk : in std_logic;
-- CPU bus signals
cpu_in : in t_cpu2bus;
cpu_out : out t_bus2cpu;
-- ROM bus signals
rom_in : in t_ros2bus;
rom_out : out t_bus2ros;
-- RAM bus signals
ram_in : in t_rws2bus;
ram_out : out t_bus2rws;
-- GPIO bus signals
gpio_in : in t_rws2bus;
gpio_out : out t_bus2rws
);
end buss;
architecture rtl of buss is
-- currently addressed bus slave
signal bus_slave, bus_slave_reg : t_bus_slave;
begin
-----------------------------------------------------------------------------
-- address decoding
-----------------------------------------------------------------------------
-- convey lower address bist from CPU to all bus slaves
rom_out.addr <= cpu_in.addr(AWL-1 downto 0);
ram_out.addr <= cpu_in.addr(AWL-1 downto 0);
gpio_out.addr <= cpu_in.addr(AWL-1 downto 0);
-- combinational process:
-- determine addressed slave by decoding higher address bits
-----------------------------------------------------------------------------
P_dec: process(cpu_in)
begin
bus_slave <= ROM; -- default assignment
for k in t_bus_slave loop
if cpu_in.addr(AW-1 downto AW-AWH) = HBA(k) then
bus_slave <= k;
end if;
end loop;
end process;
-----------------------------------------------------------------------------
-- write transfer logic
-----------------------------------------------------------------------------
-- convey write data from CPU to all bus slaves
-- rom is read-only slave
ram_out.data <= cpu_in.data;
gpio_out.data <= cpu_in.data;
-- convey write enable from CPU to addressed slave only
ram_out.wr_enb <= cpu_in.wr_enb when bus_slave = RAM else '0';
gpio_out.wr_enb <= cpu_in.wr_enb when bus_slave = GPIO else '0';
-----------------------------------------------------------------------------
-- read transfer logic
-----------------------------------------------------------------------------
-- read data mux
with bus_slave_reg select cpu_out.data <= rom_in.data when ROM,
ram_in.data when RAM,
gpio_in.data when GPIO,
(others => '-') when others;
-- convey read enable from CPU to addressed slave only
ram_out.rd_enb <= cpu_in.rd_enb when bus_slave = RAM else '0';
gpio_out.rd_enb <= cpu_in.rd_enb when bus_slave = GPIO else '0';
-- sequential process:
-- register decode information to compensate read-latency of slaves
-----------------------------------------------------------------------------
P_reg: process(rst, clk)
begin
if rst = '1' then
bus_slave_reg <= ROM;
elsif rising_edge(clk) then
bus_slave_reg <= bus_slave;
end if;
end process;
end rtl;
|
gpl-2.0
|
d943fcb59eead7bc1d366d91fd974e7a
| 0.492553 | 4.561722 | false | false | false | false |
daniw/add
|
rot_enc/lcd.vhd
| 3 | 1,542 |
-------------------------------------------------------------------------------
-- Entity: lcd
-- Author: Waj
-- Date : 11-May-13
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- LCD controller with bus interface and 4-bit data interface.
-------------------------------------------------------------------------------
-- Total # of FFs: ... tbd ...
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity lcd is
port(rst : in std_logic;
clk : in std_logic;
-- LCD bus signals
bus_in : in t_bus2rws;
bus_out : out t_rws2bus;
-- LCD control/data interface
lcd_out : out std_logic_vector(LCD_PW-1 downto 0)
);
end lcd;
architecture rtl of lcd is
begin
-----------------------------------------------------------------------------
-- sequential process: DUMMY to avoid logic optimization
-- To be replaced.....
-- # of FFs: ......
-----------------------------------------------------------------------------
P_dummy: process(rst, clk)
begin
if rst = '1' then
lcd_out <= (others => '0');
elsif rising_edge(clk) then
if bus_in.wr_enb = '1' then
if unsigned(bus_in.addr) > 0 then
bus_out.data <= bus_in.data;
lcd_out <= bus_in.addr & bus_in.data(3);
end if;
end if;
end if;
end process;
end rtl;
|
gpl-2.0
|
03016f5d3b8bc270d90d2a052f4a7d5a
| 0.393645 | 4.443804 | false | false | false | false |
daniw/add
|
lab1/Ex3/FIR_5x5_load_coeff/vhd/fir_2d_modules.vhd
| 1 | 6,366 |
-------------------------------------------------------------------------------
-- Company : HSLU
-- Engineer : Gai, Waj
--
-- Create Date: 26-May-11
-- Project : RT Video Lab 1: Exercise 3
-- Description: Components for 2D 5x5-FIR filter
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Multiplier
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity MULT is
generic(
DW_IN_1 : integer;
DW_IN_2 : integer;
DELAY : integer
);
port(
ce_1 : in std_logic;
clk_1 : in std_logic;
FACTOR_IN_1 : in std_logic_vector(DW_IN_1-1 downto 0);
FACTOR_IN_2 : in std_logic_vector(DW_IN_2-1 downto 0);
PRODUCT_OUT : out std_logic_vector((DW_IN_1 + DW_IN_2 - 1) downto 0)
);
end MULT;
architecture structural of MULT is
type DELAY_TYPE is array(DELAY-1 downto 0) of std_logic_vector((DW_IN_1 + DW_IN_2 - 1) downto 0);
signal FACTOR_1_BUF : unsigned(DW_IN_1-1 downto 0);
signal FACTOR_2_BUF : unsigned(DW_IN_2-1 downto 0);
signal DelayLine : DELAY_TYPE := (others => (others => '0'));
begin
FACTOR_1_BUF <= unsigned(FACTOR_IN_1);
FACTOR_2_BUF <= unsigned(FACTOR_IN_2);
x0_multiply : process(clk_1)
begin
if clk_1'event and clk_1 = '1' then
if ce_1 = '1' then
DelayLine(DELAY-1) <= std_logic_vector(FACTOR_1_BUF * FACTOR_2_BUF);
DelayLine(DELAY-2 downto 0) <= DelayLine(DELAY-1 downto 1);
PRODUCT_OUT <= DelayLine(0);
end if;
end if;
end process x0_multiply;
end structural;
-------------------------------------------------------------------------------
-- Adder
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity ADDER is
generic(
DW_IN : integer
);
port(
ce_1 : in std_logic;
clk_1 : in std_logic;
S_IN_1 : in std_logic_vector(DW_IN-1 downto 0);
S_IN_2 : in std_logic_vector(DW_IN-1 downto 0);
SUM_OUT : out std_logic_vector(DW_IN downto 0)
);
end ADDER;
architecture structural of ADDER is
signal IN_Sign1 : signed(DW_IN downto 0);
signal IN_Sign2 : signed(DW_IN downto 0);
begin
-- sign-extension of inputs
IN_Sign1 <= signed(S_IN_1(DW_IN-1) & '1' & S_IN_1(DW_IN-2 downto 0)) when S_IN_1(DW_IN-1) = '1' else
signed(S_IN_1(DW_IN-1) & '0' & S_IN_1(DW_IN-2 downto 0));
IN_Sign2 <= signed(S_IN_2(DW_IN-1) & '1' & S_IN_2(DW_IN-2 downto 0)) when S_IN_2(DW_IN-1) = '1' else
signed(S_IN_2(DW_IN-1) & '0' & S_IN_2(DW_IN-2 downto 0));
x0_ADD : process(clk_1)
begin
if clk_1'event and clk_1 = '1' then
if ce_1 = '1' then
SUM_OUT <= std_logic_vector(signed(IN_Sign1 + IN_Sign2));
end if;
end if;
end process x0_ADD;
end structural;
-------------------------------------------------------------------------------
-- absolute Value
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity ABS_VAL is
generic(
DW: integer
);
port(
ce_1 : in std_logic;
clk_1 : in std_logic;
VAL_IN : in std_logic_vector(DW-1 downto 0);
VAL_OUT : out std_logic_vector(DW-1 downto 0)
);
end ABS_VAL;
architecture structural of ABS_VAL is
signal OutReg : std_logic_vector(DW-1 downto 0);
begin
x0_abs : process(clk_1)
begin
if clk_1'event and clk_1 = '1' then
if ce_1 = '1' then
-- :ToDo: ------------------------------------------------------------
-- Implement logic to generate absolute value of VAL_IN
-----------------------------------------------------------------------
OutReg <= .....
-- additional output register
VAL_OUT <= OutReg;
end if;
end if;
end process x0_abs;
end structural;
-------------------------------------------------------------------------------
-- Pipeline register
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity Pipeline_Reg is
generic(
DW_IN : integer
);
port(
clk_1 : in std_logic;
en : in std_logic;
D : in std_logic_vector(DW_IN-1 downto 0);
Q : out std_logic_vector(DW_IN-1 downto 0)
);
end Pipeline_Reg;
architecture structural of Pipeline_Reg is
begin
p_reg : process(clk_1)
begin
if clk_1'event and clk_1 = '1' then
if en = '1' then
Q <= D;
end if;
end if;
end process p_reg;
end structural;
-------------------------------------------------------------------------------
-- Truncation/Saturation unit
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity CONVERT is
generic(
DW_IN : integer;
DW_OUT : integer;
BIN_PNT : integer
);
port(
clk_1 : in std_logic;
ce_1 : in std_logic;
din : in std_logic_vector(DW_IN-1 downto 0);
dout : out std_logic_vector(DW_OUT-1 downto 0)
);
end CONVERT;
architecture structural of CONVERT is
begin
x0_CONV : process(clk_1)
begin
if clk_1'event and clk_1 = '1' then
if ce_1 = '1' then
-- :ToDo: ------------------------------------------------------------
-- Implement logic to scale the unsigned value din, which has a total
-- number of DW_IN bits and BIN_PNT fractional bits, such that
-- a) dout has a total number of DW_OUT bits and zero fractional bits
-- b) saturation is applied if the value of din exceeds the maximum
-- unsigned value of dout
-----------------------------------------------------------------------
dout <= .....
end if;
end if;
end process;
end structural;
|
gpl-2.0
|
6ec34c7fbe0d35a3497a1ff5074063ef
| 0.457901 | 3.660725 | false | false | false | false |
jeffmagina/ECE368
|
Lab2/RISC Machine SSEG/RISC_MACHINE.vhd
| 1 | 2,576 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Jeffrey Magina and Jon Leidhold
--
-- Create Date: SPRING 2015
-- Module Name: RISC_MACHINE
-- Project Name: RISC_MACHINE
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: RISC Machine possibly for future
-- design of UMD RISC Machine. Takes in a 0 - F
-- on the ASCII_DATA line outputs, it to the BUFFER
-- concatenated together to form the Instruction
-- which is sent to the ALU to perform a function and
-- outputs it to the seven segment display
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.all;
entity RISC_MACHINE is
Port( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
PS2_CLK : inout STD_LOGIC;
PS2_DATA : inout STD_LOGIC;
SEG : out STD_LOGIC_VECTOR (6 downto 0);
DP : out STD_LOGIC;
AN : out STD_LOGIC_VECTOR (3 downto 0);
LED : out STD_LOGIC_VECTOR (3 downto 0));
end RISC_MACHINE;
architecture Structural of RISC_MACHINE is
signal RD,WE :STD_LOGIC;
signal KEY_DATA : STD_LOGIC_VECTOR (7 downto 0);
signal TO_SEG : STD_LOGIC_VECTOR(7 downto 0);
signal TO_ALU : STD_LOGIC_VECTOR(15 downto 0);
signal RegA : STD_LOGIC_VECTOR(7 downto 0);
signal cen : STD_LOGIC := '0';
signal enl : STD_LOGIC := '1';
signal dpc : STD_LOGIC_VECTOR (3 downto 0) := "1111";
begin
Keyboard: entity work.KEYBOARD_CONTROLLER
Port MAP ( CLK => CLK,
RST => RST,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
ASCII_OUT => KEY_DATA,
ASCII_RD => RD,
ASCII_WE => WE);
Debug_Unit: entity work.ASCII_BUFFER
port MAP(
ASCII_DATA => KEY_DATA,
ASCII_RD => RD,
ASCII_WE => WE,
CLK => CLK,
RST => RST,
ASCII_BUFF => TO_ALU);
SSeg: entity work.SSegDriver
port map( CLK => CLK,
RST => '0',
EN => enl,
SEG_0 => "0000",
SEG_1 => "0000",
SEG_2 => TO_SEG(7 downto 4),
SEG_3 => TO_SEG(3 downto 0),
DP_CTRL => dpc,
COL_EN => cen,
SEG_OUT => SEG,
DP_OUT => DP,
AN_OUT => AN);
RegA <= ("0000" & TO_ALU(11 downto 8));
ALU: entity work.ALU
Port map ( CLK => CLK,
RA => RegA,
RB => TO_ALU(7 downto 0),
OPCODE => TO_ALU(15 downto 12),
CCR => LED(3 downto 0),
ALU_OUT => TO_SEG(7 downto 0));
end Structural;
|
mit
|
0ac6e98efda65e5d04930eaaaa0b5765
| 0.559006 | 3.362924 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_gpio_0_0/sim/system_axi_gpio_0_0.vhd
| 1 | 9,295 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_13;
USE axi_gpio_v2_0_13.axi_gpio;
ENTITY system_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END system_axi_gpio_0_0;
ARCHITECTURE system_axi_gpio_0_0_arch OF system_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 20,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 1,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
ip2intc_irpt => ip2intc_irpt,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END system_axi_gpio_0_0_arch;
|
apache-2.0
|
2c7dd4e5415c6fd44b38086530996cba
| 0.680581 | 3.225191 | false | false | false | false |
xcthulhu/lambda-geda
|
blink.vhdl
| 1 | 821 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
library unisim;
use unisim.Vcomponents.all;
entity Clk_div_led is
generic (max_count : natural := 48000000);
port (CLK : in std_logic;
led : out std_logic);
end Clk_div_led;
architecture RTL of Clk_div_led is
signal x : std_logic;
begin
IO_L24P_1 : OBUF
port map (I => x,
O => led);
-- compteur de 0 à max_count
compteur : process(Clk)
variable count : natural range 0 to max_count;
begin
if rising_edge(Clk) then
if count < max_count/2 then
x <= '1';
count := count + 1;
elsif count < max_count then
x <= '0';
count := count + 1;
else
x <= '1';
count := 0;
end if;
end if;
end process compteur;
end RTL;
|
gpl-3.0
|
8df6ba82b2d67d1251b41453c79192d2
| 0.564634 | 3.319838 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_xadc_wiz_0_0/interrupt_control_v2_01_a/hdl/src/vhdl/system_xadc_wiz_0_0_interrupt_control.vhd
| 1 | 56,977 |
-------------------------------------------------------------------------------
--system_xadc_wiz_0_0_interrupt_control.vhd version v2.01.a
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright(C) 2005 by Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This text contains proprietary, confidential **
-- ** information of Xilinx, Inc. , is distributed by **
-- ** under license from Xilinx, Inc., and may be used, **
-- ** copied and/or disclosed only pursuant to the terms **
-- ** of a valid license agreement with Xilinx, Inc. **
-- ** **
-- ** Unmodified source code is guaranteed to place and route, **
-- ** function and run at speed according to the datasheet **
-- ** specification. Source code is provided "as-is", with no **
-- ** obligation on the part of Xilinx to provide support. **
-- ** **
-- ** Xilinx Hotline support of source code IP shall only include **
-- ** standard level Xilinx Hotline support, and will only address **
-- ** issues and questions related to the standard released Netlist **
-- ** version of the core (and thus indirectly, the original core source). **
-- ** **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Support Hotline will only be able **
-- ** to confirm the problem in the Netlist version of the core. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: system_xadc_wiz_0_0_interrupt_control.vhd
--
-- Description: This VHDL design file is the parameterized interrupt control
-- module for the ipif which permits parameterizing 1 or 2 levels
-- of interrupt registers. This module has been optimized
-- for the 64 bit wide PLB bus.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- system_xadc_wiz_0_0_interrupt_control.vhd
--
--
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_I_SP2
--
-- Initial Release
--
-- END_CHANGELOG
-------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_K_SP3
--
-- Updated to use work library
--
-- @END_CHANGELOG
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe Aug 16, 2001 -- V1.00a (initial release)
-- Mike Lovejoy Oct 9, 2001 -- V1.01a
-- Added parameter C_INCLUDE_DEV_ISC to remove Device ISC.
-- When one source of interrupts Device ISC is redundant and
-- can be eliminated to reduce LUT count. When 7 interrupts
-- are included, the LUT count is reduced from 49 to 17.
-- Also removed the "wrapper" which required redefining
-- ports and generics herein.
--
-- det Feb-19-02
-- - Added additional selections of input processing on the IP
-- interrupt inputs. This was done by replacing the
-- C_IP_IRPT_NUM Generic with an unconstrained input array
-- of integers selecting the type of input processing for each
-- bit.
--
-- det Mar-22-02
-- - Corrected a reset problem with pos edge detect interrupt
-- input processing (a high on the input when recovering from
-- reset caused an eroneous interrupt to be latched in the IP_
-- ISR reg.
--
-- blt Nov-18-02 -- V1.01b
-- - Updated library and use statements to use ipif_common_v1_00_b
--
-- DET 11/5/2003 v1_00_e
-- ~~~~~~
-- - Revamped register topology to take advantage of 64 bit wide data bus
-- interface. This required adding the Bus2IP_BE_sa input port to
-- provide byte lane qualifiers for write operations.
-- ^^^^^^
--
--
-- DET 3/25/2004 ipif to v1_00_f
-- ~~~~~~
-- - Changed proc_common library reference to v2_00_a
-- - Removed ipif_common library reference
-- ^^^^^^
-- GAB 06/29/2005 v2_00_a
-- ~~~~~~
-- - Modified plb_system_xadc_wiz_0_0_interrupt_control of plb_ipif_v1_00_f to make
-- a common version that supports 32,64, and 128-Bit Data Bus Widths.
-- - Changed to use ieee.numeric_std library and removed
-- ieee.std_logic_arith.all
-- ^^^^^^
-- GAB 09/01/2006 v2_00_a
-- ~~~~~~
-- - Modified wrack and strobe for toggling set interrupt bits to reduce LUTs
-- - Removed strobe from interrupt enable registers where it was not needed
-- ^^^^^^
-- GAB 07/02/2008 v2_01_a
-- ~~~~~~
-- - Modified to used proc_common_v3_30_a library
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--
--
-------------------------------------------------------------------------------
-- Special information
--
-- The input Generic C_IP_INTR_MODE_ARRAY is an unconstrained array
-- of integers. The number of entries specifies how many IP interrupts
-- are to be processed. Each entry in the array specifies the type of input
-- processing for each IP interrupt input. The following table
-- lists the defined values for entries in the array:
--
-- 1 = Level Pass through (non-inverted input)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Level (non-inverted input)
-- 4 = Registered Level (inverted input)
-- 5 = Rising Edge Detect (non-inverted input)
-- 6 = Falling Edge Detect (non-inverted input)
--
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library work;
Use work.system_xadc_wiz_0_0_proc_common_pkg.all;
use work.system_xadc_wiz_0_0_ipif_pkg.all;
----------------------------------------------------------------------
entity system_xadc_wiz_0_0_interrupt_control is
Generic(
C_NUM_CE : integer range 4 to 16 := 4;
-- Number of register chip enables required
-- For C_IPIF_DWIDTH=32 Set C_NUM_CE = 16
-- For C_IPIF_DWIDTH=64 Set C_NUM_CE = 8
-- For C_IPIF_DWIDTH=128 Set C_NUM_CE = 4
C_NUM_IPIF_IRPT_SRC : integer range 1 to 29 := 4;
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- pass through (non-inverting)
2 -- pass through (inverting)
);
-- Interrupt Modes
--1, -- pass through (non-inverting)
--2, -- pass through (inverting)
--3, -- registered level (non-inverting)
--4, -- registered level (inverting)
--5, -- positive edge detect
--6 -- negative edge detect
C_INCLUDE_DEV_PENCODER : boolean := false;
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_ISC : boolean := false;
-- Specifies device ISC hierarchy
-- Exclusion of Device ISC requires
-- exclusion of Priority encoder
C_IPIF_DWIDTH : integer range 32 to 128 := 128
);
port(
-- Inputs From the IPIF Bus
Bus2IP_Clk : In std_logic;
Bus2IP_Reset : In std_logic;
Bus2IP_Data : In std_logic_vector(0 to C_IPIF_DWIDTH-1);
Bus2IP_BE : In std_logic_vector(0 to (C_IPIF_DWIDTH/8)-1);
Interrupt_RdCE : In std_logic_vector(0 to C_NUM_CE-1);
Interrupt_WrCE : In std_logic_vector(0 to C_NUM_CE-1);
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
IPIF_Reg_Interrupts : In std_logic_vector(0 to 1);
-- Level Interrupt inputs from the IPIF sources
IPIF_Lvl_Interrupts : In std_logic_vector
(0 to C_NUM_IPIF_IRPT_SRC-1);
-- Inputs from the IP Interface
IP2Bus_IntrEvent : In std_logic_vector
(0 to C_IP_INTR_MODE_ARRAY'length-1);
-- Final Device Interrupt Output
Intr2Bus_DevIntr : Out std_logic;
-- Status Reply Outputs to the Bus
Intr2Bus_DBus : Out std_logic_vector(0 to C_IPIF_DWIDTH-1);
Intr2Bus_WrAck : Out std_logic;
Intr2Bus_RdAck : Out std_logic;
Intr2Bus_Error : Out std_logic;
Intr2Bus_Retry : Out std_logic;
Intr2Bus_ToutSup : Out std_logic
);
end system_xadc_wiz_0_0_interrupt_control;
-------------------------------------------------------------------------------
architecture implementation of system_xadc_wiz_0_0_interrupt_control is
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_max_allowed_irpt_width
--
-- Function Description:
-- This function determines the maximum number of interrupts that
-- can be processed from the User IP based on the IPIF data bus width
-- and the number of interrupt entries desired.
--
-------------------------------------------------------------------
function get_max_allowed_irpt_width(data_bus_width : integer;
num_intrpts_entered : integer)
return integer is
Variable temp_max : Integer;
begin
If (data_bus_width >= num_intrpts_entered) Then
temp_max := num_intrpts_entered;
else
temp_max := data_bus_width;
End if;
return(temp_max);
end function get_max_allowed_irpt_width;
-------------------------------------------------------------------------------
-- Function data_port_map
-- This function will return an index within a 'reg_width' divided port
-- having a width of 'port_width' based on an address 'offset'.
-- For instance if the port_width is 128-bits and the register width
-- reg_width = 32 bits and the register address offset=16 (0x10), this
-- function will return a index of 0.
--
-- Address Offset Returned Index Return Index Returned Index
-- (128 Bit Bus) (64 Bit Bus) (32 Bit Bus)
-- 0x00 0 0 0
-- 0x04 1 1 0
-- 0x08 2 0 0
-- 0x0C 3 1 0
-- 0x10 0 0 0
-- 0x14 1 1 0
-- 0x18 2 0 0
-- 0x1C 3 1 0
-------------------------------------------------------------------------------
function data_port_map(offset : integer;
reg_width : integer;
port_width : integer)
return integer is
variable upper_index : integer;
variable vector_range : integer;
variable reg_offset : std_logic_vector(0 to 7);
variable word_offset_i : integer;
begin
-- Calculate index position to start decoding the address offset
upper_index := log2(port_width/8);
-- Calculate the number of bits to look at in decoding
-- the address offset
vector_range := max2(1,log2(port_width/reg_width));
-- Convert address offset into a std_logic_vector in order to
-- strip out a set of bits for decoding
reg_offset := std_logic_vector(to_unsigned(offset,8));
-- Calculate an index representing the word position of
-- a register with respect to the port width.
word_offset_i := to_integer(unsigned(reg_offset(reg_offset'length
- upper_index to (reg_offset'length
- upper_index) + vector_range - 1)));
return word_offset_i;
end data_port_map;
-------------------------------------------------------------------------------
-- Type declarations
-------------------------------------------------------------------------------
-- no Types
-------------------------------------------------------------------------------
-- Constant declarations
-------------------------------------------------------------------------------
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
-- figure out if 32 bits wide or 64 bits wide
Constant LSB_BYTLE_LANE_COL_OFFSET : integer := (C_IPIF_DWIDTH/32)-1;
Constant CHIP_SEL_SCALE_FACTOR : integer := (C_IPIF_DWIDTH/32);
constant BITS_PER_REG : integer := 32;
constant BYTES_PER_REG : integer := BITS_PER_REG/8;
-- Register Index
Constant DEVICE_ISR_INDEX : integer := 0;
Constant DEVICE_IPR_INDEX : integer := 1;
Constant DEVICE_IER_INDEX : integer := 2;
Constant DEVICE_IAR_INDEX : integer := 3; --NOT USED RSVD
Constant DEVICE_SIE_INDEX : integer := 4; --NOT USED RSVD
Constant DEVICE_CIE_INDEX : integer := 5; --NOT USED RSVD
Constant DEVICE_IIR_INDEX : integer := 6;
Constant DEVICE_GIE_INDEX : integer := 7;
Constant IP_ISR_INDEX : integer := 8;
Constant IP_IPR_INDEX : integer := 9; --NOT USED RSVD
Constant IP_IER_INDEX : integer := 10;
Constant IP_IAR_INDEX : integer := 11; --NOT USED RSVD
Constant IP_SIE_INDEX : integer := 12; --NOT USED RSVD
Constant IP_CIE_INDEX : integer := 13; --NOT USED RSVD
Constant IP_IIR_INDEX : integer := 14; --NOT USED RSVD
Constant IP_GIE_INDEX : integer := 15; --NOT USED RSVD
-- Chip Enable Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR : integer := DEVICE_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IPR : integer := DEVICE_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IER : integer := DEVICE_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_IAR : integer := DEVICE_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_SIE : integer := DEVICE_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_CIE : integer := DEVICE_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_IIR : integer := DEVICE_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant DEVICE_GIE : integer := DEVICE_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant IP_ISR : integer := IP_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IPR : integer := IP_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IER : integer := IP_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_IAR : integer := IP_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_SIE : integer := IP_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_CIE : integer := IP_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_IIR : integer := IP_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
Constant IP_GIE : integer := IP_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
-- Register Address Offset
Constant DEVICE_ISR_OFFSET : integer := DEVICE_ISR_INDEX * BYTES_PER_REG;
Constant DEVICE_IPR_OFFSET : integer := DEVICE_IPR_INDEX * BYTES_PER_REG;
Constant DEVICE_IER_OFFSET : integer := DEVICE_IER_INDEX * BYTES_PER_REG;
Constant DEVICE_IAR_OFFSET : integer := DEVICE_IAR_INDEX * BYTES_PER_REG;
Constant DEVICE_SIE_OFFSET : integer := DEVICE_SIE_INDEX * BYTES_PER_REG;
Constant DEVICE_CIE_OFFSET : integer := DEVICE_CIE_INDEX * BYTES_PER_REG;
Constant DEVICE_IIR_OFFSET : integer := DEVICE_IIR_INDEX * BYTES_PER_REG;
Constant DEVICE_GIE_OFFSET : integer := DEVICE_GIE_INDEX * BYTES_PER_REG;
Constant IP_ISR_OFFSET : integer := IP_ISR_INDEX * BYTES_PER_REG;
Constant IP_IPR_OFFSET : integer := IP_IPR_INDEX * BYTES_PER_REG;
Constant IP_IER_OFFSET : integer := IP_IER_INDEX * BYTES_PER_REG;
Constant IP_IAR_OFFSET : integer := IP_IAR_INDEX * BYTES_PER_REG;
Constant IP_SIE_OFFSET : integer := IP_SIE_INDEX * BYTES_PER_REG;
Constant IP_CIE_OFFSET : integer := IP_CIE_INDEX * BYTES_PER_REG;
Constant IP_IIR_OFFSET : integer := IP_IIR_INDEX * BYTES_PER_REG;
Constant IP_GIE_OFFSET : integer := IP_GIE_INDEX * BYTES_PER_REG;
-- Column Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR_COL : integer := data_port_map(DEVICE_ISR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IPR_COL : integer := data_port_map(DEVICE_IPR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IER_COL : integer := data_port_map(DEVICE_IER_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IAR_COL : integer := data_port_map(DEVICE_IAR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_SIE_COL : integer := data_port_map(DEVICE_SIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_CIE_COL : integer := data_port_map(DEVICE_CIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IIR_COL : integer := data_port_map(DEVICE_IIR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_GIE_COL : integer := data_port_map(DEVICE_GIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_ISR_COL : integer := data_port_map(IP_ISR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IPR_COL : integer := data_port_map(IP_IPR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IER_COL : integer := data_port_map(IP_IER_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IAR_COL : integer := data_port_map(IP_IAR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_SIE_COL : integer := data_port_map(IP_SIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_CIE_COL : integer := data_port_map(IP_CIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IIR_COL : integer := data_port_map(IP_IIR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_GIE_COL : integer := data_port_map(IP_GIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
-- Generic to constant mapping
Constant DBUS_WIDTH_MINUS1 : Integer := C_IPIF_DWIDTH - 1;
Constant NUM_USER_DESIRED_IRPTS : Integer := C_IP_INTR_MODE_ARRAY'length;
-- Constant IP_IRPT_HIGH_INDEX : Integer := C_IP_INTR_MODE_ARRAY'length - 1;
Constant IP_IRPT_HIGH_INDEX : Integer :=
get_max_allowed_irpt_width(C_IPIF_DWIDTH,
NUM_USER_DESIRED_IRPTS)
-1;
Constant IPIF_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC + 2;
-- (2 level + 1 IP + Number of latched inputs) - 1
Constant IPIF_LVL_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC - 1;
-- Priority encoder support constants
Constant PRIORITY_ENC_WIDTH : Integer := 8; -- bits
Constant NO_INTR_VALUE : Integer := 128;
-- no interrupt pending code = "10000000"
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
Signal trans_reg_irpts : std_logic_vector(1 downto 0);
Signal trans_lvl_irpts : std_logic_vector
(IPIF_LVL_IRPT_HIGH_INDEX downto 0);
Signal trans_ip_irpts : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal edgedtct_ip_irpts : std_logic_vector
(0 to IP_IRPT_HIGH_INDEX);
signal irpt_read_data : std_logic_vector
(DBUS_WIDTH_MINUS1 downto 0);
Signal irpt_rdack : std_logic;
Signal irpt_wrack : std_logic;
signal ip_irpt_status_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_enable_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_pending_value : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal ip_interrupt_or : std_logic;
signal ipif_irpt_status_reg : std_logic_vector(1 downto 0);
signal ipif_irpt_status_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_enable_reg : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_pending_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
Signal ipif_glbl_irpt_enable_reg : std_logic;
Signal ipif_interrupt : std_logic;
Signal ipif_interrupt_or : std_logic;
Signal ipif_pri_encode_present : std_logic;
Signal ipif_priority_encode_value : std_logic_vector
(PRIORITY_ENC_WIDTH-1 downto 0);
Signal column_sel : std_logic_vector
(0 to LSB_BYTLE_LANE_COL_OFFSET);
signal interrupt_wrce_strb : std_logic;
signal irpt_wrack_d1 : std_logic;
signal irpt_rdack_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc I/O and Signal assignments
Intr2Bus_DevIntr <= ipif_interrupt;
Intr2Bus_Error <= LOGIC_LOW;
Intr2Bus_Retry <= LOGIC_LOW;
Intr2Bus_ToutSup <= LOGIC_LOW;
REG_WRACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_wrack_d1 <= '0';
Intr2Bus_WrAck <= '0';
else
irpt_wrack_d1 <= irpt_wrack;
Intr2Bus_WrAck <= interrupt_wrce_strb;
end if;
end if;
end process REG_WRACK_PROCESS;
interrupt_wrce_strb <= irpt_wrack and not irpt_wrack_d1;
REG_RDACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_rdack_d1 <= '0';
Intr2Bus_RdAck <= '0';
else
irpt_rdack_d1 <= irpt_rdack;
Intr2Bus_RdAck <= irpt_rdack and not irpt_rdack_d1;
end if;
end if;
end process REG_RDACK_PROCESS;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: ASSIGN_COL
--
-- Process Description:
--
--
-------------------------------------------------------------
ASSIGN_COL : process (Bus2IP_BE)
begin
-- Assign the 32-bit column selects from BE inputs
for i in 0 to LSB_BYTLE_LANE_COL_OFFSET loop
column_sel(i) <= Bus2IP_BE(i*4);
end loop;
end process ASSIGN_COL;
----------------------------------------------------------------------------------------------------------------
--- IP Interrupt processing start
------------------------------------------------------------------------------------------
-- Convert Little endian register to big endian data bus
------------------------------------------------------------------------------------------
LITTLE_TO_BIG : process (irpt_read_data)
Begin
for k in 0 to DBUS_WIDTH_MINUS1 loop
Intr2Bus_DBus(DBUS_WIDTH_MINUS1-k) <= irpt_read_data(k); -- Convert to Big-Endian Data Bus
End loop;
End process; -- LITTLE_TO_BIG
------------------------------------------------------------------------------------------
-- Convert big endian interrupt inputs to Little endian registers
------------------------------------------------------------------------------------------
BIG_TO_LITTLE : process (IPIF_Reg_Interrupts, IPIF_Lvl_Interrupts, edgedtct_ip_irpts)
Begin
for i in 0 to 1 loop
trans_reg_irpts(i) <= IPIF_Reg_Interrupts(i); -- Convert to Little-Endian format
End loop;
for j in 0 to IPIF_LVL_IRPT_HIGH_INDEX loop
trans_lvl_irpts(j) <= IPIF_Lvl_Interrupts(j); -- Convert to Little-Endian format
End loop;
for k in 0 to IP_IRPT_HIGH_INDEX loop
trans_ip_irpts(k) <= edgedtct_ip_irpts(k); -- Convert to Little-Endian format
End loop;
End process; -- BIG_TO_LITTLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Input Processing
------------------------------------------------------------------------------------------
DO_IRPT_INPUT: for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_NON_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 3) generate
edgedtct_ip_irpts(irpt_index) <= IP2Bus_IntrEvent(irpt_index);
end generate GEN_NON_INVERT_PASS_THROUGH;
GEN_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 2 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 4) generate
edgedtct_ip_irpts(irpt_index) <= not(IP2Bus_IntrEvent(irpt_index));
end generate GEN_INVERT_PASS_THROUGH;
GEN_POS_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 5) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '1'; -- setting to '1' protects reset transition
irpt_dly2 <= '1'; -- where interrupt inputs are preset high
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
-- now detect rising edge
edgedtct_ip_irpts(irpt_index) <= irpt_dly1 and not(irpt_dly2);
end generate GEN_POS_EDGE_DETECT;
GEN_NEG_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 6) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '0';
irpt_dly2 <= '0';
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
edgedtct_ip_irpts(irpt_index) <= not(irpt_dly1) and irpt_dly2;
end generate GEN_NEG_EDGE_DETECT;
GEN_INVALID_TYPE : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 6 ) generate
edgedtct_ip_irpts(irpt_index) <= '0'; -- Don't use input
end generate GEN_INVALID_TYPE;
End generate DO_IRPT_INPUT;
-- Generate the IP Interrupt Status register
GEN_IP_IRPT_STATUS_REG : for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_REG_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 2) generate
DO_STATUS_BIT : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_status_reg(irpt_index) <= '0';
elsif (Interrupt_WrCE(IP_ISR) = '1' and
column_sel(IP_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then -- toggle selected ISR bits from the DBus inputs
-- (GAB)
ip_irpt_status_reg(irpt_index) <=
(Bus2IP_Data((BITS_PER_REG * IP_ISR_COL)
+(BITS_PER_REG - 1)
- irpt_index) xor -- toggle bits on write of '1'
ip_irpt_status_reg(irpt_index)) or -- but don't miss interrupts coming
trans_ip_irpts(irpt_index); -- in on non-cleared interrupt bits
else
ip_irpt_status_reg(irpt_index) <=
ip_irpt_status_reg(irpt_index) or
trans_ip_irpts(irpt_index); -- latch and hold input interrupt bits
End if;
Else
null;
End if;
End process; -- DO_STATUS_BIT
End generate GEN_REG_STATUS;
GEN_PASS_THROUGH_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 2) generate
ip_irpt_status_reg(irpt_index) <= trans_ip_irpts(irpt_index);
End generate GEN_PASS_THROUGH_STATUS;
End generate GEN_IP_IRPT_STATUS_REG;
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IP_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(IP_IER) = '1' and
column_sel(IP_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ip_irpt_enable_reg <= Bus2IP_Data
( (BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
- IP_IRPT_HIGH_INDEX to
(BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IP_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IP_INTR_ENABLE : process (ip_irpt_status_reg, ip_irpt_enable_reg)
Begin
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_irpt_pending_value(i) <= ip_irpt_status_reg(i) and
ip_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IP_INTR_ENABLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt 'OR' Functions
------------------------------------------------------------------------------------------
DO_IP_INTR_OR : process (ip_irpt_pending_value)
Variable ip_loop_or : std_logic;
Begin
ip_loop_or := '0';
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_loop_or := ip_loop_or or ip_irpt_pending_value(i);
End loop;
ip_interrupt_or <= ip_loop_or;
End process; -- DO_IP_INTR_OR
--------------------------------------------------------------------------------------------
--- IP Interrupt processing end
--------------------------------------------------------------------------------------------
--==========================================================================================
Include_Device_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
--------------------------------------------------------------------------------------------
--- IPIF Interrupt processing Start
--------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Status Register Write and Clear Functions
-- This is only 2 bits wide (the only inputs latched at this level...the others just flow
-- through)
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_STATUS_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_status_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_ISR) = '1' and
column_sel(DEVICE_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then
for i in 0 to 1 loop
-- (GAB)
ipif_irpt_status_reg(i) <= (Bus2IP_Data
( (BITS_PER_REG * DEVICE_ISR_COL)
+(BITS_PER_REG - 1)
- i) xor -- toggle bits on write of '1'
ipif_irpt_status_reg(i)) or -- but don't miss interrupts coming
trans_reg_irpts(i); -- in on non-cleared interrupt bits
End loop;
else
for i in 0 to 1 loop
ipif_irpt_status_reg(i) <= ipif_irpt_status_reg(i) or trans_reg_irpts(i);
-- latch and hold asserted interrupts
End loop;
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_STATUS_REG
DO_IPIF_IRPT_STATUS_VALUE : process (ipif_irpt_status_reg, trans_lvl_irpts, ip_interrupt_or)
Begin
ipif_irpt_status_value(1 downto 0) <= ipif_irpt_status_reg;
ipif_irpt_status_value(2) <= ip_interrupt_or;
for i in 3 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_status_value(i) <= trans_lvl_irpts(i-3);
End loop;
End process; -- DO_IPIF_IRPT_STATUS_VALUE
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_IER) = '1' and
column_sel(DEVICE_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ipif_irpt_enable_reg <= Bus2IP_Data
(
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
- IPIF_IRPT_HIGH_INDEX to
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IPIF_INTR_ENABLE : process (ipif_irpt_status_value, ipif_irpt_enable_reg)
Begin
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_pending_value(i) <= ipif_irpt_status_value(i) and ipif_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IPIF_INTR_ENABLE
end generate Include_Device_ISC_generate;
Initialize_when_not_include_Device_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_irpt_status_reg <= (others => '0');
ipif_irpt_status_value <= (others => '0');
ipif_irpt_enable_reg <= (others => '0');
ipif_irpt_pending_value <= (others => '0');
end generate Initialize_when_not_include_Device_ISC_generate;
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Master Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_MASTER_ENABLE : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_glbl_irpt_enable_reg <= '0';
elsif (Interrupt_WrCE(DEVICE_GIE) = '1' and
column_sel(DEVICE_GIE_COL) = '1' )then
--interrupt_wrce_strb = '1') Then -- load input data from the DBus inputs
-- (GAB)
ipif_glbl_irpt_enable_reg <= Bus2IP_Data(BITS_PER_REG * DEVICE_GIE_COL);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_MASTER_ENABLE
INCLUDE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = True) generate
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Priority Encoder Function on the Interrupt Pending Value
-- Loop from Interrupt LSB to MSB, retaining the position of the last interrupt detected.
-- This method implies a positional priority of MSB to LSB.
------------------------------------------------------------------------------------------
ipif_pri_encode_present <= '1';
DO_PRIORITY_ENCODER : process (ipif_irpt_pending_value)
Variable irpt_position : Integer;
Variable irpt_detected : Boolean;
Variable loop_count : integer;
Begin
loop_count := IPIF_IRPT_HIGH_INDEX + 1;
irpt_position := 0;
irpt_detected := FALSE;
-- Search through the pending interrupt values starting with the MSB
while (loop_count > 0) loop
If (ipif_irpt_pending_value(loop_count-1) = '1') Then
irpt_detected := TRUE;
irpt_position := loop_count-1;
else
null; -- do nothing
End if;
loop_count := loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last interrupt encountered
If (irpt_detected) Then
ipif_priority_encode_value <= std_logic_vector(to_unsigned(irpt_position, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '1'; -- piggy-back off of this function for the "OR" function
else
ipif_priority_encode_value <= std_logic_vector(to_unsigned(NO_INTR_VALUE, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '0';
End if;
End process; -- DO_PRIORITY_ENCODER
end generate INCLUDE_DEV_PRIORITY_ENCODER;
DELETE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = False) generate
ipif_pri_encode_present <= '0';
ipif_priority_encode_value <= (others => '0');
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt 'OR' Functions (used if priority encoder removed)
------------------------------------------------------------------------------------------
DO_IPIF_INTR_OR : process (ipif_irpt_pending_value)
Variable ipif_loop_or : std_logic;
Begin
ipif_loop_or := '0';
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_loop_or := ipif_loop_or or ipif_irpt_pending_value(i);
End loop;
ipif_interrupt_or <= ipif_loop_or;
End process; -- DO_IPIF_INTR_OR
end generate DELETE_DEV_PRIORITY_ENCODER;
-------------------------------------------------------------------------------------------
-- Perform the final Master enable function on the 'ORed' interrupts
OR_operation_with_Dev_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
ipif_interrupt_PROCESS: process(ipif_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ipif_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_with_Dev_ISC_generate;
OR_operation_withOUT_Dev_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_interrupt_PROCESS: process(ip_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ip_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_withOUT_Dev_ISC_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Interrupt processing end
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_WrAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <= (
Interrupt_WrCE(DEVICE_ISR) and
column_sel(DEVICE_ISR_COL)
)
or
(
Interrupt_WrCE(DEVICE_IER) and
column_sel(DEVICE_IER_COL)
)
or
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Include_Dev_ISC_WrAck_OR_generate;
Exclude_Dev_ISC_WrAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <=
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Exclude_Dev_ISC_WrAck_OR_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Bus Data Read Mux and Read Acknowledge generation
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_RdAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, column_sel,
ip_irpt_status_reg,
ip_irpt_enable_reg,
ipif_irpt_pending_value,
ipif_irpt_enable_reg,
ipif_pri_encode_present,
ipif_priority_encode_value,
ipif_irpt_status_value,
ipif_glbl_irpt_enable_reg)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_ISR) = '1'
and column_sel(DEVICE_ISR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_ISR_COL)
- BITS_PER_REG)) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IPR) = '1'
and column_sel(DEVICE_IPR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_pending_value(i+32); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IPR_COL)
- BITS_PER_REG)) <= ipif_irpt_pending_value(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IER) = '1'
and column_sel(DEVICE_IER_COL) = '1') Then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IER_COL)
- BITS_PER_REG)) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IIR) = '1'
and column_sel(DEVICE_IIR_COL) = '1') Then
-- irpt_read_data(32+PRIORITY_ENC_WIDTH-1 downto 32) <= ipif_priority_encode_value; -- output IPIF pending interrupt values
irpt_read_data( (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG) + PRIORITY_ENC_WIDTH-1
downto (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG)) <= ipif_priority_encode_value;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(DBUS_WIDTH_MINUS1) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Include_Dev_ISC_RdAck_OR_generate;
Exclude_Dev_ISC_RdAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, ip_irpt_status_reg, ip_irpt_enable_reg,
ipif_glbl_irpt_enable_reg,column_sel)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(31) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Exclude_Dev_ISC_RdAck_OR_generate;
end implementation;
|
apache-2.0
|
0186319ed6dcdca68ae02bfe42d99e14
| 0.451568 | 4.583461 | false | false | false | false |
aggroskater/ee4321-vhdl-digital-design
|
Project-2-4bit-RCA/rca_4_bit.vhd
| 1 | 1,605 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:15:26 02/12/2014
-- Design Name:
-- Module Name: rca_4_bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rca_4_bit is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
Sum : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end rca_4_bit;
architecture Behavioral of rca_4_bit is
signal c0, c1, c2 : std_logic:='0';
signal b0, b1, b2, b3 : std_logic:='0';
begin
--add/sub control; this flips B if necessary.
b0 <= B(0) XOR Cin;
b1 <= B(1) XOR Cin;
b2 <= B(2) XOR Cin;
b3 <= B(3) XOR Cin;
FA0: entity work.full_adder_1_bit port map (A(0),b0,Cin,c0,Sum(0));
FA1: entity work.full_adder_1_bit port map (A(1),b1,c0,c1,Sum(1));
FA2: entity work.full_adder_1_bit port map (A(2),b2,c1,c2,Sum(2));
FA3: entity work.full_adder_1_bit port map (A(3),b3,c2,Cout,Sum(3));
end Behavioral;
|
agpl-3.0
|
c2cb2987031f0ddc85d350064cadd418
| 0.581308 | 3.074713 | false | false | false | false |
KPU-RISC/KPU
|
VHDL/ALU8Bit.vhd
| 1 | 13,412 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/20/2015 06:10:42 PM
-- Design Name:
-- Module Name: ALU8Bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU8Bit is
Port
(
InputA : in BIT_VECTOR(7 downto 0); -- 1st 8-bit input value
InputB : in BIT_VECTOR(7 downto 0); -- 2nd 8-bit input value
FunctionCode: in BIT_VECTOR(3 downto 0); -- 4-bit function code
CarryIn: in BIT; -- Carry-Bit
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
Sign : out BIT; -- Do we have a negative number? FLAGS(0)
Zero : out BIT; -- Do we have a zero value? FLAGS(1)
Carry : out BIT; -- Do we have a carry? FLAGS(2)
Overflow: out BIT -- Do we have an overflow? FLAGS(3)
);
end ALU8Bit;
architecture Behavioral of ALU8Bit is
component RippleCarryAdder8Bit is
Port
(
InputA : in BIT_VECTOR(7 downto 0); -- 1st 8-bit input value
InputB : in BIT_VECTOR(7 downto 0); -- 2nd 8-bit input value
Cin : in BIT; -- Carry-in flag
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
Cout : out BIT -- Carry-out flag
);
end component RippleCarryAdder8Bit;
component And8Bit is
Port
(
InputA : in BIT_VECTOR(7 downto 0); -- 1st 8-bit input value
InputB : in BIT_VECTOR(7 downto 0); -- 2nd 8-bit input value
Output : out BIT_VECTOR(7 downto 0) -- 8-bit output value
);
end component And8Bit;
component Or8Bit is
Port
(
InputA : in BIT_VECTOR(7 downto 0); -- 1st 8-bit input value
InputB : in BIT_VECTOR(7 downto 0); -- 2nd 8-bit input value
Output : out BIT_VECTOR(7 downto 0) -- 8-bit output value
);
end component Or8Bit;
component Xor8Bit is
Port
(
InputA : in BIT_VECTOR(7 downto 0); -- 1st 8-bit input value
InputB : in BIT_VECTOR(7 downto 0); -- 2nd 8-bit input value
Output : out BIT_VECTOR(7 downto 0) -- 8-bit output value
);
end component Xor8Bit;
component Not8Bit is
Port
(
Input : in BIT_VECTOR(7 downto 0); -- 1st 8-bit input value
Output : out BIT_VECTOR(7 downto 0) -- 8-bit output value
);
end component Not8Bit;
component SHL8Bit is
Port
(
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
Cout : out BIT -- Carry-out flag
);
end component SHL8Bit;
component RCL8Bit is
Port
(
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Cin : in BIT; -- Carry-in flag
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
Cout : out BIT -- Carry-out flag
);
end component RCL8Bit;
component SHR8Bit is
Port
(
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
Cout : out BIT -- Carry-out flag
);
end component SHR8Bit;
component SAR8Bit is
Port
(
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
Cout : out BIT -- Carry-out flag
);
end component SAR8Bit;
component RCR8Bit is
Port
(
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Cin : in BIT; -- Carry-in flag
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
Cout : out BIT -- Carry-out flag
);
end component RCR8Bit;
component Neg8Bit is
Port
(
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Output : out BIT_VECTOR(7 downto 0) -- 8-bit output value
);
end component Neg8Bit;
component MOV8 is
Port
(
InputA : in BIT_VECTOR(7 downto 0); -- 1st 8-bit input value
InputB : in BIT_VECTOR(7 downto 0); -- 2nd 8-bit input value
Output : out BIT_VECTOR(7 downto 0) -- 8-bit output value
);
end component MOV8;
component EnableCircuit is
Port
(
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Enable : in BIT; -- Should be input value returned?
Output : out BIT_VECTOR(7 downto 0) -- 8-bit output value
);
end component EnableCircuit;
component Decoder4To16 is
Port
(
F : in BIT_VECTOR(3 downto 0); -- 4-Bit Function Code (Input)
X : out BIT_VECTOR(15 downto 0) -- 16-Bit State (Output)
);
end component Decoder4To16;
signal OutputADD : BIT_VECTOR(7 downto 0);
signal OutputAND : BIT_VECTOR(7 downto 0);
signal OutputOR : BIT_VECTOR(7 downto 0);
signal OutputXOR : BIT_VECTOR(7 downto 0);
signal OutputNOT : BIT_VECTOR(7 downto 0);
signal OutputSHL : BIT_VECTOR(7 downto 0);
signal OutputADC : BIT_VECTOR(7 downto 0);
signal OutputSUB : BIT_VECTOR(7 downto 0);
signal OutputNEG : BIT_VECTOR(7 downto 0);
signal OutputSBB : BIT_VECTOR(7 downto 0);
signal OutputRCL : BIT_VECTOR(7 downto 0);
signal OutputSHR : BIT_VECTOR(7 downto 0);
signal OutputSAR : BIT_VECTOR(7 downto 0);
signal OutputRCR : BIT_VECTOR(7 downto 0);
signal OutputMOV8 : BIT_VECTOR(7 downto 0);
signal OutputEnabledADD : BIT_VECTOR(7 downto 0);
signal OutputEnabledAND : BIT_VECTOR(7 downto 0);
signal OutputEnabledOR : BIT_VECTOR(7 downto 0);
signal OutputEnabledXOR : BIT_VECTOR(7 downto 0);
signal OutputEnabledNOT : BIT_VECTOR(7 downto 0);
signal OutputEnabledSHL : BIT_VECTOR(7 downto 0);
signal OutputEnabledADC : BIT_VECTOR(7 downto 0);
signal OutputEnabledSUB : BIT_VECTOR(7 downto 0);
signal OutputEnabledNEG : BIT_VECTOR(7 downto 0);
signal OutputEnabledSBB : BIT_VECTOR(7 downto 0);
signal OutputEnabledRCL : BIT_VECTOR(7 downto 0);
signal OutputEnabledSHR : BIT_VECTOR(7 downto 0);
signal OutputEnabledSAR : BIT_VECTOR(7 downto 0);
signal OutputEnabledRCR : BIT_VECTOR(7 downto 0);
signal OutputEnabledMOV8 : BIT_VECTOR(7 downto 0);
signal OutputLocal: BIT_VECTOR(7 downto 0);
signal ControlLines: BIT_VECTOR(15 downto 0);
signal CarryLocalADD: BIT;
signal CarryLocalADC: BIT;
signal CarryLocalSUB: BIT;
signal CarryLocalSBB: BIT;
signal CarryLocalSHL: BIT;
signal CarryLocalRCL: BIT;
signal CarryLocalSHR: BIT;
signal CarryLocalSAR: BIT;
signal CarryLocalRCR: BIT;
signal CarrySUB: BIT;
signal Overflow_ADD: BIT;
signal Overflow_ADC: BIT;
signal Overflow_SUB: BIT;
signal Overflow_SBB: BIT;
signal TwoComplementForSBB : BIT_VECTOR(7 downto 0);
signal InputBPlusCarryForSBB : BIT_VECTOR(7 downto 0);
signal CarryForSBB : BIT_VECTOR(7 downto 0);
begin
-- Decide which ALU operation is currently running
Decoder: Decoder4to16 port map(FunctionCode, ControlLines);
-- Perform the individual ALU operations concurrently
XOR_Impl: Xor8Bit port map(InputA, InputB, OutputXOR);
OR_Impl: Or8Bit port map(InputA, InputB, OutputOR);
AND_Impl: And8Bit port map(InputA, InputB, OutputAND);
ADD_Impl: RippleCarryAdder8Bit port map (InputA, InputB, '0', OutputADD, CarryLocalADD);
NOT_Impl: Not8Bit port map(InputA, OutputNOT);
SHL_Impl: SHL8Bit port map(InputA, OutputSHL, CarryLocalSHL);
ADC_Impl: RippleCarryAdder8Bit port map (InputA, InputB, CarryIn, OutputADC, CarryLocalADC);
SUB_Impl: RippleCarryAdder8Bit port map (InputA, not(InputB), '1', OutputSUB, CarryLocalSUB);
NEG_Impl: Neg8Bit port map(InputA, OutputNEG);
RCL_Impl: RCL8Bit port map(InputA, CarryIn, OutputRCL, CarryLocalRCL);
SHR_Impl: SHR8Bit port map(InputA, OutputSHR, CarryLocalSHR);
SAR_Impl: SAR8Bit port map(InputA, OutputSAR, CarryLocalSAR);
RCR_Impl: RCR8Bit port map(InputA, CarryIn, OutputRCR, CarryLocalRCR);
MOV8_Impl: MOV8 port map(InputA, InputB, OutputMOV8);
-- SBB implementation:
-- => In the 1st step the Carry flag is added to InputB
-- => In the 2nd step the RippleCarryAdder performs the SUB operation by converting InputB to the Two-Complement (NOT + 1)
CarryForSBB(0) <= CarryIn;
CarryForSBB(7 downto 1) <= "0000000";
ADD_For_SBB_Impl: RippleCarryAdder8Bit port map (InputB, CarryForSBB, '0', InputBPlusCarryForSBB);
SBB_Impl: RippleCarryAdder8Bit port map (InputA, not(InputBPlusCarryForSBB), '1', OutputSBB, CarryLocalSBB);
-- Output only the ALU operation that is currently running
EnableXOR: EnableCircuit port map(OutputXOR, ControlLines(1), OutputEnabledXOR);
EnableOR: EnableCircuit port map(OutputOR, ControlLines(2), OutputEnabledOR);
EnableAND: EnableCircuit port map(OutputAND, ControlLines(3), OutputEnabledAND);
EnableADD: EnableCircuit port map(OutputADD, ControlLines(4), OutputEnabledADD);
EnableNOT: EnableCircuit port map(OutputNOT, ControlLines(5), OutputEnabledNOT);
EnableSHL: EnableCircuit port map(OutputSHL, ControlLines(6), OutputEnabledSHL);
EnableADC: EnableCircuit port map(OutputADC, ControlLines(7), OutputEnabledADC);
EnableSUB: EnableCircuit port map(OutputSUB, ControlLines(8), OutputEnabledSUB);
EnableNEG: EnableCircuit port map(OutputNEG, ControlLines(9), OutputEnabledNEG);
EnableSBB: EnableCircuit port map(OutputSBB, ControlLines(10), OutputEnabledSBB);
EnableRCL: EnableCircuit port map(OutputRCL, ControlLines(11), OutputEnabledRCL);
EnableSHR: EnableCircuit port map(OutputSHR, ControlLines(12), OutputEnabledSHR);
EnableSAR: EnableCircuit port map(OutputSAR, ControlLines(13), OutputEnabledSAR);
EnableRCR: EnableCircuit port map(OutputRCR, ControlLines(14), OutputEnabledRCR);
EnableMOV8: EnableCircuit port map(OutputMOV8, ControlLines(15), OutputEnabledMOV8);
-- Returns the final output of the ALU
OutputLocal <= OutputEnabledXOR or
OutputEnabledOR or
OutputEnabledAND or
OutputEnabledADD or
OutputEnabledNOT or
OutputEnabledSHL or
OutputEnabledADC or
OutputEnabledSUB or
OutputEnabledNEG or
OutputEnabledSBB or
OutputEnabledRCL or
OutputEnabledSHR or
OutputEnabledSAR or
OutputEnabledRCR or
OutputEnabledMOV8;
Output <= OutputLocal;
-- Returns the Sign flag
Sign <= OutputLocal(7) and not(ControlLines(0));
-- Returns the Zero flag
Zero <= not(
OutputLocal(0) or
OutputLocal(1) or
OutputLocal(2) or
OutputLocal(3) or
OutputLocal(4) or
OutputLocal(5) or
OutputLocal(6) or
OutputLocal(7)
) and not(ControlLines(0));
-- Returns the Carry flag
Carry <= (CarryLocalADD and ControlLines(4)) or -- ADD
(CarryLocalADC and ControlLines(7)) or -- ADC
(not(CarryLocalSUB) and ControlLines(8)) or -- SUB
(not(CarryLocalSBB) and ControlLines(10))or -- SBB
(CarryLocalSHL and ControlLines(6)) or -- SHL
(CarryLocalRCL and ControlLines(11)) or -- RCL
(CarryLocalSHR and ControlLines(12)) or -- SHR
(CarryLocalSAR and ControlLines(13)) or -- SAR
(CarryLocalRCR and ControlLines(14)); -- RCR
-- Calculates the overflow flag for the ADD operation
Overflow_ADD <= (Not(InputA(7)) and not(InputB(7)) and OutputADD(7)) or
(InputA(7) and InputB(7) and not(OutputADD(7)));
-- Calculates the overflow flag for the ADC operation
Overflow_ADC <= (Not(InputA(7)) and not(InputB(7)) and OutputADC(7)) or
(InputA(7) and InputB(7) and not(OutputADC(7)));
-- Calculates the overflow flag for the SUB operation
Overflow_SUB <= (Not(InputA(7)) and InputB(7) and OutputSUB(7)) or
(InputA(7) and not(InputB(7)) and not(OutputSUB(7)));
-- Calculates the overflow flag for the SBB operation
Overflow_SBB <= (Not(InputA(7)) and InputB(7) and OutputSBB(7)) or
(InputA(7) and not(InputB(7)) and not(OutputSBB(7)));
-- Returns the Overflow flag
Overflow <= (Overflow_ADD and ControlLines(4)) or
(Overflow_ADC and ControlLines(7)) or
(Overflow_SUB and ControlLines(8)) or
(Overflow_SBB and ControlLines(10));
end Behavioral;
|
mit
|
49dabbb201c3ca9660eb5b9a7b72983c
| 0.624217 | 4.036112 | false | false | false | false |
KPU-RISC/KPU
|
VHDL/Or8Bit.vhd
| 1 | 1,447 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/18/2015 11:10:22 PM
-- Design Name:
-- Module Name: Or8Bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Or8Bit is
Port
(
InputA : in BIT_VECTOR(7 downto 0); -- 1st 8-bit input value
InputB : in BIT_VECTOR(7 downto 0); -- 2nd 8-bit input value
Output : out BIT_VECTOR(7 downto 0) -- 8-bit output value
);
end Or8Bit;
architecture Behavioral of Or8Bit is
begin
Output(0) <= InputA(0) or InputB(0);
Output(1) <= InputA(1) or InputB(1);
Output(2) <= InputA(2) or InputB(2);
Output(3) <= InputA(3) or InputB(3);
Output(4) <= InputA(4) or InputB(4);
Output(5) <= InputA(5) or InputB(5);
Output(6) <= InputA(6) or InputB(6);
Output(7) <= InputA(7) or InputB(7);
end Behavioral;
|
mit
|
6b14971e83b5bca90504b354d7569793
| 0.574983 | 3.608479 | false | false | false | false |
daniw/add
|
edk/IVK_HW/t01_hello/hdl/proc_sys_reset_0_wrapper.vhd
| 2 | 4,179 |
-------------------------------------------------------------------------------
-- proc_sys_reset_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library proc_sys_reset_v3_00_a;
use proc_sys_reset_v3_00_a.all;
entity proc_sys_reset_0_wrapper is
port (
Slowest_sync_clk : in std_logic;
Ext_Reset_In : in std_logic;
Aux_Reset_In : in std_logic;
MB_Debug_Sys_Rst : in std_logic;
Core_Reset_Req_0 : in std_logic;
Chip_Reset_Req_0 : in std_logic;
System_Reset_Req_0 : in std_logic;
Core_Reset_Req_1 : in std_logic;
Chip_Reset_Req_1 : in std_logic;
System_Reset_Req_1 : in std_logic;
Dcm_locked : in std_logic;
RstcPPCresetcore_0 : out std_logic;
RstcPPCresetchip_0 : out std_logic;
RstcPPCresetsys_0 : out std_logic;
RstcPPCresetcore_1 : out std_logic;
RstcPPCresetchip_1 : out std_logic;
RstcPPCresetsys_1 : out std_logic;
MB_Reset : out std_logic;
Bus_Struct_Reset : out std_logic_vector(0 to 0);
Peripheral_Reset : out std_logic_vector(0 to 0);
Interconnect_aresetn : out std_logic_vector(0 to 0);
Peripheral_aresetn : out std_logic_vector(0 to 0)
);
attribute x_core_info : STRING;
attribute x_core_info of proc_sys_reset_0_wrapper : entity is "proc_sys_reset_v3_00_a";
end proc_sys_reset_0_wrapper;
architecture STRUCTURE of proc_sys_reset_0_wrapper is
component proc_sys_reset is
generic (
C_EXT_RST_WIDTH : integer;
C_AUX_RST_WIDTH : integer;
C_EXT_RESET_HIGH : std_logic;
C_AUX_RESET_HIGH : std_logic;
C_NUM_BUS_RST : integer;
C_NUM_PERP_RST : integer;
C_NUM_INTERCONNECT_ARESETN : integer;
C_NUM_PERP_ARESETN : integer
);
port (
Slowest_sync_clk : in std_logic;
Ext_Reset_In : in std_logic;
Aux_Reset_In : in std_logic;
MB_Debug_Sys_Rst : in std_logic;
Core_Reset_Req_0 : in std_logic;
Chip_Reset_Req_0 : in std_logic;
System_Reset_Req_0 : in std_logic;
Core_Reset_Req_1 : in std_logic;
Chip_Reset_Req_1 : in std_logic;
System_Reset_Req_1 : in std_logic;
Dcm_locked : in std_logic;
RstcPPCresetcore_0 : out std_logic;
RstcPPCresetchip_0 : out std_logic;
RstcPPCresetsys_0 : out std_logic;
RstcPPCresetcore_1 : out std_logic;
RstcPPCresetchip_1 : out std_logic;
RstcPPCresetsys_1 : out std_logic;
MB_Reset : out std_logic;
Bus_Struct_Reset : out std_logic_vector(0 to C_NUM_BUS_RST-1);
Peripheral_Reset : out std_logic_vector(0 to C_NUM_PERP_RST-1);
Interconnect_aresetn : out std_logic_vector(0 to C_NUM_INTERCONNECT_ARESETN-1);
Peripheral_aresetn : out std_logic_vector(0 to C_NUM_PERP_ARESETN-1)
);
end component;
begin
proc_sys_reset_0 : proc_sys_reset
generic map (
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '1',
C_AUX_RESET_HIGH => '1',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
port map (
Slowest_sync_clk => Slowest_sync_clk,
Ext_Reset_In => Ext_Reset_In,
Aux_Reset_In => Aux_Reset_In,
MB_Debug_Sys_Rst => MB_Debug_Sys_Rst,
Core_Reset_Req_0 => Core_Reset_Req_0,
Chip_Reset_Req_0 => Chip_Reset_Req_0,
System_Reset_Req_0 => System_Reset_Req_0,
Core_Reset_Req_1 => Core_Reset_Req_1,
Chip_Reset_Req_1 => Chip_Reset_Req_1,
System_Reset_Req_1 => System_Reset_Req_1,
Dcm_locked => Dcm_locked,
RstcPPCresetcore_0 => RstcPPCresetcore_0,
RstcPPCresetchip_0 => RstcPPCresetchip_0,
RstcPPCresetsys_0 => RstcPPCresetsys_0,
RstcPPCresetcore_1 => RstcPPCresetcore_1,
RstcPPCresetchip_1 => RstcPPCresetchip_1,
RstcPPCresetsys_1 => RstcPPCresetsys_1,
MB_Reset => MB_Reset,
Bus_Struct_Reset => Bus_Struct_Reset,
Peripheral_Reset => Peripheral_Reset,
Interconnect_aresetn => Interconnect_aresetn,
Peripheral_aresetn => Peripheral_aresetn
);
end architecture STRUCTURE;
|
gpl-2.0
|
02466a5aba74abd6930735b3cdbbedca
| 0.61498 | 3.298343 | false | false | false | false |
daniw/add
|
cpu/rom.vhd
| 1 | 3,141 |
-------------------------------------------------------------------------------
-- Entity: rom
-- Author: Waj
-- Date : 11-May-13, 26-May-13
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- Program memory for simple von-Neumann MCU with registerd read data output.
-------------------------------------------------------------------------------
-- Total # of FFs: DW
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity rom is
port(clk : in std_logic;
-- ROM bus signals
bus_in : in t_bus2ros;
bus_out : out t_ros2bus
);
end rom;
architecture rtl of rom is
type t_rom is array (0 to 2**AWL-1) of std_logic_vector(DW-1 downto 0);
constant rom_table : t_rom := (
---------------------------------------------------------------------------
-- program code -----------------------------------------------------------
---------------------------------------------------------------------------
-- addr Opcode Rdest Rsrc1 Rsrc2 description
---------------------------------------------------------------------------
0 => OPC(setil) & reg(0) & "01000000", -- r0 = r0 + "01000000"
1 => OPC(setil) & reg(1) & "01000001", -- r1 = r1 + "01000001"
2 => OPC(setil) & reg(2) & "01000010", -- r2 = r2 + "01000010"
3 => OPC(setil) & reg(6) & "00000001", -- r6 = r6 + "00000001"
4 => OPC(setih) & reg(6) & "11110000", -- r6 = r6 + "11110000"
5 => OPC(setil) & reg(7) & "00000000", -- r7 = r7 + "00000000"
6 => OPC(setih) & reg(7) & "11110000", -- r7 = r7 + "11110000"
7 => OPC(ld) & reg(3) & reg(0) & "---" & "--", -- r3 = *r0
8 => OPC(add) & reg(3) & reg(3) & reg(6) & "--", -- r3 = r3 + r6
9 => OPC(st) & reg(3) & reg(0) & "---" & "--", -- *r0 = r3
10 => OPC(ld) & reg(4) & reg(1) & "---" & "--", -- r4 = *r1
11 => OPC(add) & reg(4) & reg(4) & reg(7) & "--", -- r4 = r4 + r7
12 => OPC(st) & reg(4) & reg(1) & "---" & "--", -- *r1 = r4
13 => OPC(add) & reg(5) & reg(3) & reg(4) & "--", -- r5 = r3 + r4
14 => OPC(st) & reg(5) & reg(2) & "---" & "--", -- *r2 = r5
15 => OPC(bov) & "---" & "00000010", -- bov "00000010"
16 => OPC(jmp) & "---" & "00000111", -- jmp "00000111"
others => (others => '1')
);
begin
-----------------------------------------------------------------------------
-- sequential process: ROM table with registerd output
-----------------------------------------------------------------------------
P_rom: process(clk)
begin
if rising_edge(clk) then
bus_out.data <= rom_table(to_integer(unsigned(bus_in.addr)));
end if;
end process;
end rtl;
|
gpl-2.0
|
691be18f93f338da4747e9d88683da71
| 0.33015 | 3.802663 | false | false | false | false |
kaott/16-bit-risc
|
vhdl/fts.vhd
| 4 | 1,348 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.lib.all;
ENTITY fts IS
PORT( hexin :IN STD_LOGIC_VECTOR(0 TO 3);
dispout :OUT STD_LOGIC_VECTOR(0 TO 6));
END fts;
ARCHITECTURE Structure OF fts IS
BEGIN
PROCESS(hexin)
BEGIN
IF hexin = "0000" THEN --0
dispout <= "0000001";
END IF;
IF hexin = "0001" THEN --1
dispout <= "1001111";
END IF;
IF hexin = "0010" THEN --2
dispout <= "0010010";
END IF;
IF hexin = "0011" THEN --3
dispout <= "0000110";
END IF;
IF hexin = "0100" THEN --4
dispout <= "1001100";
END IF;
IF hexin = "0101" THEN --5
dispout <= "0100100";
END IF;
IF hexin = "0110" THEN --6
dispout <= "0100000";
END IF;
IF hexin = "0111" THEN --7
dispout <= "0001111";
END IF;
IF hexin = "1000" THEN --8
dispout <= "0000000";
END IF;
IF hexin = "1001" THEN --9
dispout <= "0001100";
END IF;
IF hexin = "1010" THEN --A
dispout <= "0001000";
END IF;
IF hexin = "1011" THEN --B
dispout <= "1100000";
END IF;
IF hexin = "1100" THEN --C
dispout <= "0110001";
END IF;
IF hexin = "1101" THEN --D
dispout <= "1000010";
END IF;
IF hexin = "1110" THEN --E
dispout <= "0110000";
END IF;
IF hexin = "1111" THEN --F
dispout <= "0111000";
END IF;
END PROCESS;
END Structure;
|
mit
|
383fac5b01bb35037596400e8efe2cea
| 0.557864 | 2.880342 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/hdl/system.vhd
| 1 | 506,764 |
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
--Date : Mon Mar 20 20:54:09 2017
--Host : N73-PC running 64-bit major release (build 9200)
--Command : generate_target system.bd
--Design : system
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_1RZ0IW6 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m00_couplers_imp_1RZ0IW6;
architecture STRUCTURE of m00_couplers_imp_1RZ0IW6 is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m00_couplers_to_m00_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m00_couplers_to_m00_couplers_AWVALID(0);
M_AXI_bready(0) <= m00_couplers_to_m00_couplers_BREADY(0);
M_AXI_rready(0) <= m00_couplers_to_m00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m00_couplers_to_m00_couplers_WVALID(0);
S_AXI_arready(0) <= m00_couplers_to_m00_couplers_ARREADY(0);
S_AXI_awready(0) <= m00_couplers_to_m00_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m00_couplers_to_m00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m00_couplers_to_m00_couplers_RVALID(0);
S_AXI_wready(0) <= m00_couplers_to_m00_couplers_WREADY(0);
m00_couplers_to_m00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_m00_couplers_ARREADY(0) <= M_AXI_arready(0);
m00_couplers_to_m00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m00_couplers_to_m00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_m00_couplers_AWREADY(0) <= M_AXI_awready(0);
m00_couplers_to_m00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m00_couplers_to_m00_couplers_BREADY(0) <= S_AXI_bready(0);
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID(0) <= M_AXI_bvalid(0);
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RREADY(0) <= S_AXI_rready(0);
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID(0) <= M_AXI_rvalid(0);
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WREADY(0) <= M_AXI_wready(0);
m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_m00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_1TEAG88 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 27 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC;
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 27 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC;
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m00_couplers_imp_1TEAG88;
architecture STRUCTURE of m00_couplers_imp_1TEAG88 is
component system_auto_cc_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 27 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 27 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component system_auto_cc_0;
signal M_ACLK_1 : STD_LOGIC;
signal M_ARESETN_1 : STD_LOGIC;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_cc_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 27 downto 0 );
signal auto_cc_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_cc_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_cc_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_cc_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_cc_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_cc_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_m00_couplers_ARREADY : STD_LOGIC;
signal auto_cc_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_cc_to_m00_couplers_ARVALID : STD_LOGIC;
signal auto_cc_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 27 downto 0 );
signal auto_cc_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_cc_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_cc_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_cc_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_cc_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_cc_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_m00_couplers_AWREADY : STD_LOGIC;
signal auto_cc_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_cc_to_m00_couplers_AWVALID : STD_LOGIC;
signal auto_cc_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_cc_to_m00_couplers_BREADY : STD_LOGIC;
signal auto_cc_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_cc_to_m00_couplers_BVALID : STD_LOGIC;
signal auto_cc_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal auto_cc_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_cc_to_m00_couplers_RLAST : STD_LOGIC;
signal auto_cc_to_m00_couplers_RREADY : STD_LOGIC;
signal auto_cc_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_cc_to_m00_couplers_RVALID : STD_LOGIC;
signal auto_cc_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal auto_cc_to_m00_couplers_WLAST : STD_LOGIC;
signal auto_cc_to_m00_couplers_WREADY : STD_LOGIC;
signal auto_cc_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 0 );
signal auto_cc_to_m00_couplers_WVALID : STD_LOGIC;
signal m00_couplers_to_auto_cc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_cc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_cc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_cc_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_cc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_cc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_cc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_cc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_cc_ARREADY : STD_LOGIC;
signal m00_couplers_to_auto_cc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_cc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_cc_ARVALID : STD_LOGIC;
signal m00_couplers_to_auto_cc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_cc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_cc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_cc_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_cc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_cc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_cc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_cc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_cc_AWREADY : STD_LOGIC;
signal m00_couplers_to_auto_cc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_cc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_cc_AWVALID : STD_LOGIC;
signal m00_couplers_to_auto_cc_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_cc_BREADY : STD_LOGIC;
signal m00_couplers_to_auto_cc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_cc_BVALID : STD_LOGIC;
signal m00_couplers_to_auto_cc_RDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal m00_couplers_to_auto_cc_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_cc_RLAST : STD_LOGIC;
signal m00_couplers_to_auto_cc_RREADY : STD_LOGIC;
signal m00_couplers_to_auto_cc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_cc_RVALID : STD_LOGIC;
signal m00_couplers_to_auto_cc_WDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal m00_couplers_to_auto_cc_WLAST : STD_LOGIC;
signal m00_couplers_to_auto_cc_WREADY : STD_LOGIC;
signal m00_couplers_to_auto_cc_WSTRB : STD_LOGIC_VECTOR ( 15 downto 0 );
signal m00_couplers_to_auto_cc_WVALID : STD_LOGIC;
signal NLW_auto_cc_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_auto_cc_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_ACLK_1 <= M_ACLK;
M_ARESETN_1 <= M_ARESETN;
M_AXI_araddr(27 downto 0) <= auto_cc_to_m00_couplers_ARADDR(27 downto 0);
M_AXI_arburst(1 downto 0) <= auto_cc_to_m00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_cc_to_m00_couplers_ARCACHE(3 downto 0);
M_AXI_arid(0) <= auto_cc_to_m00_couplers_ARID(0);
M_AXI_arlen(7 downto 0) <= auto_cc_to_m00_couplers_ARLEN(7 downto 0);
M_AXI_arlock <= auto_cc_to_m00_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= auto_cc_to_m00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_cc_to_m00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_cc_to_m00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_cc_to_m00_couplers_ARVALID;
M_AXI_awaddr(27 downto 0) <= auto_cc_to_m00_couplers_AWADDR(27 downto 0);
M_AXI_awburst(1 downto 0) <= auto_cc_to_m00_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_cc_to_m00_couplers_AWCACHE(3 downto 0);
M_AXI_awid(0) <= auto_cc_to_m00_couplers_AWID(0);
M_AXI_awlen(7 downto 0) <= auto_cc_to_m00_couplers_AWLEN(7 downto 0);
M_AXI_awlock <= auto_cc_to_m00_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= auto_cc_to_m00_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_cc_to_m00_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_cc_to_m00_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_cc_to_m00_couplers_AWVALID;
M_AXI_bready <= auto_cc_to_m00_couplers_BREADY;
M_AXI_rready <= auto_cc_to_m00_couplers_RREADY;
M_AXI_wdata(127 downto 0) <= auto_cc_to_m00_couplers_WDATA(127 downto 0);
M_AXI_wlast <= auto_cc_to_m00_couplers_WLAST;
M_AXI_wstrb(15 downto 0) <= auto_cc_to_m00_couplers_WSTRB(15 downto 0);
M_AXI_wvalid <= auto_cc_to_m00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= m00_couplers_to_auto_cc_ARREADY;
S_AXI_awready <= m00_couplers_to_auto_cc_AWREADY;
S_AXI_bid(0) <= m00_couplers_to_auto_cc_BID(0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_auto_cc_BRESP(1 downto 0);
S_AXI_bvalid <= m00_couplers_to_auto_cc_BVALID;
S_AXI_rdata(127 downto 0) <= m00_couplers_to_auto_cc_RDATA(127 downto 0);
S_AXI_rid(0) <= m00_couplers_to_auto_cc_RID(0);
S_AXI_rlast <= m00_couplers_to_auto_cc_RLAST;
S_AXI_rresp(1 downto 0) <= m00_couplers_to_auto_cc_RRESP(1 downto 0);
S_AXI_rvalid <= m00_couplers_to_auto_cc_RVALID;
S_AXI_wready <= m00_couplers_to_auto_cc_WREADY;
auto_cc_to_m00_couplers_ARREADY <= M_AXI_arready;
auto_cc_to_m00_couplers_AWREADY <= M_AXI_awready;
auto_cc_to_m00_couplers_BID(0) <= M_AXI_bid(0);
auto_cc_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_cc_to_m00_couplers_BVALID <= M_AXI_bvalid;
auto_cc_to_m00_couplers_RDATA(127 downto 0) <= M_AXI_rdata(127 downto 0);
auto_cc_to_m00_couplers_RID(0) <= M_AXI_rid(0);
auto_cc_to_m00_couplers_RLAST <= M_AXI_rlast;
auto_cc_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_cc_to_m00_couplers_RVALID <= M_AXI_rvalid;
auto_cc_to_m00_couplers_WREADY <= M_AXI_wready;
m00_couplers_to_auto_cc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_auto_cc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
m00_couplers_to_auto_cc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
m00_couplers_to_auto_cc_ARID(0) <= S_AXI_arid(0);
m00_couplers_to_auto_cc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
m00_couplers_to_auto_cc_ARLOCK(0) <= S_AXI_arlock(0);
m00_couplers_to_auto_cc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_auto_cc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
m00_couplers_to_auto_cc_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0);
m00_couplers_to_auto_cc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
m00_couplers_to_auto_cc_ARVALID <= S_AXI_arvalid;
m00_couplers_to_auto_cc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_auto_cc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
m00_couplers_to_auto_cc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
m00_couplers_to_auto_cc_AWID(0) <= S_AXI_awid(0);
m00_couplers_to_auto_cc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
m00_couplers_to_auto_cc_AWLOCK(0) <= S_AXI_awlock(0);
m00_couplers_to_auto_cc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_auto_cc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
m00_couplers_to_auto_cc_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0);
m00_couplers_to_auto_cc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
m00_couplers_to_auto_cc_AWVALID <= S_AXI_awvalid;
m00_couplers_to_auto_cc_BREADY <= S_AXI_bready;
m00_couplers_to_auto_cc_RREADY <= S_AXI_rready;
m00_couplers_to_auto_cc_WDATA(127 downto 0) <= S_AXI_wdata(127 downto 0);
m00_couplers_to_auto_cc_WLAST <= S_AXI_wlast;
m00_couplers_to_auto_cc_WSTRB(15 downto 0) <= S_AXI_wstrb(15 downto 0);
m00_couplers_to_auto_cc_WVALID <= S_AXI_wvalid;
auto_cc: component system_auto_cc_0
port map (
m_axi_aclk => M_ACLK_1,
m_axi_araddr(27 downto 0) => auto_cc_to_m00_couplers_ARADDR(27 downto 0),
m_axi_arburst(1 downto 0) => auto_cc_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_cc_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_aresetn => M_ARESETN_1,
m_axi_arid(0) => auto_cc_to_m00_couplers_ARID(0),
m_axi_arlen(7 downto 0) => auto_cc_to_m00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => auto_cc_to_m00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => auto_cc_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_cc_to_m00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_cc_to_m00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => NLW_auto_cc_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => auto_cc_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_cc_to_m00_couplers_ARVALID,
m_axi_awaddr(27 downto 0) => auto_cc_to_m00_couplers_AWADDR(27 downto 0),
m_axi_awburst(1 downto 0) => auto_cc_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_cc_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awid(0) => auto_cc_to_m00_couplers_AWID(0),
m_axi_awlen(7 downto 0) => auto_cc_to_m00_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => auto_cc_to_m00_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => auto_cc_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_cc_to_m00_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_cc_to_m00_couplers_AWREADY,
m_axi_awregion(3 downto 0) => NLW_auto_cc_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => auto_cc_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_cc_to_m00_couplers_AWVALID,
m_axi_bid(0) => auto_cc_to_m00_couplers_BID(0),
m_axi_bready => auto_cc_to_m00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_cc_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_cc_to_m00_couplers_BVALID,
m_axi_rdata(127 downto 0) => auto_cc_to_m00_couplers_RDATA(127 downto 0),
m_axi_rid(0) => auto_cc_to_m00_couplers_RID(0),
m_axi_rlast => auto_cc_to_m00_couplers_RLAST,
m_axi_rready => auto_cc_to_m00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_cc_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_cc_to_m00_couplers_RVALID,
m_axi_wdata(127 downto 0) => auto_cc_to_m00_couplers_WDATA(127 downto 0),
m_axi_wlast => auto_cc_to_m00_couplers_WLAST,
m_axi_wready => auto_cc_to_m00_couplers_WREADY,
m_axi_wstrb(15 downto 0) => auto_cc_to_m00_couplers_WSTRB(15 downto 0),
m_axi_wvalid => auto_cc_to_m00_couplers_WVALID,
s_axi_aclk => S_ACLK_1,
s_axi_araddr(27 downto 0) => m00_couplers_to_auto_cc_ARADDR(27 downto 0),
s_axi_arburst(1 downto 0) => m00_couplers_to_auto_cc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => m00_couplers_to_auto_cc_ARCACHE(3 downto 0),
s_axi_aresetn => S_ARESETN_1,
s_axi_arid(0) => m00_couplers_to_auto_cc_ARID(0),
s_axi_arlen(7 downto 0) => m00_couplers_to_auto_cc_ARLEN(7 downto 0),
s_axi_arlock(0) => m00_couplers_to_auto_cc_ARLOCK(0),
s_axi_arprot(2 downto 0) => m00_couplers_to_auto_cc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => m00_couplers_to_auto_cc_ARQOS(3 downto 0),
s_axi_arready => m00_couplers_to_auto_cc_ARREADY,
s_axi_arregion(3 downto 0) => m00_couplers_to_auto_cc_ARREGION(3 downto 0),
s_axi_arsize(2 downto 0) => m00_couplers_to_auto_cc_ARSIZE(2 downto 0),
s_axi_arvalid => m00_couplers_to_auto_cc_ARVALID,
s_axi_awaddr(27 downto 0) => m00_couplers_to_auto_cc_AWADDR(27 downto 0),
s_axi_awburst(1 downto 0) => m00_couplers_to_auto_cc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => m00_couplers_to_auto_cc_AWCACHE(3 downto 0),
s_axi_awid(0) => m00_couplers_to_auto_cc_AWID(0),
s_axi_awlen(7 downto 0) => m00_couplers_to_auto_cc_AWLEN(7 downto 0),
s_axi_awlock(0) => m00_couplers_to_auto_cc_AWLOCK(0),
s_axi_awprot(2 downto 0) => m00_couplers_to_auto_cc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => m00_couplers_to_auto_cc_AWQOS(3 downto 0),
s_axi_awready => m00_couplers_to_auto_cc_AWREADY,
s_axi_awregion(3 downto 0) => m00_couplers_to_auto_cc_AWREGION(3 downto 0),
s_axi_awsize(2 downto 0) => m00_couplers_to_auto_cc_AWSIZE(2 downto 0),
s_axi_awvalid => m00_couplers_to_auto_cc_AWVALID,
s_axi_bid(0) => m00_couplers_to_auto_cc_BID(0),
s_axi_bready => m00_couplers_to_auto_cc_BREADY,
s_axi_bresp(1 downto 0) => m00_couplers_to_auto_cc_BRESP(1 downto 0),
s_axi_bvalid => m00_couplers_to_auto_cc_BVALID,
s_axi_rdata(127 downto 0) => m00_couplers_to_auto_cc_RDATA(127 downto 0),
s_axi_rid(0) => m00_couplers_to_auto_cc_RID(0),
s_axi_rlast => m00_couplers_to_auto_cc_RLAST,
s_axi_rready => m00_couplers_to_auto_cc_RREADY,
s_axi_rresp(1 downto 0) => m00_couplers_to_auto_cc_RRESP(1 downto 0),
s_axi_rvalid => m00_couplers_to_auto_cc_RVALID,
s_axi_wdata(127 downto 0) => m00_couplers_to_auto_cc_WDATA(127 downto 0),
s_axi_wlast => m00_couplers_to_auto_cc_WLAST,
s_axi_wready => m00_couplers_to_auto_cc_WREADY,
s_axi_wstrb(15 downto 0) => m00_couplers_to_auto_cc_WSTRB(15 downto 0),
s_axi_wvalid => m00_couplers_to_auto_cc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_K87I2F is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m01_couplers_imp_K87I2F;
architecture STRUCTURE of m01_couplers_imp_K87I2F is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m01_couplers_to_m01_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m01_couplers_to_m01_couplers_AWVALID(0);
M_AXI_bready(0) <= m01_couplers_to_m01_couplers_BREADY(0);
M_AXI_rready(0) <= m01_couplers_to_m01_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m01_couplers_to_m01_couplers_WVALID(0);
S_AXI_arready(0) <= m01_couplers_to_m01_couplers_ARREADY(0);
S_AXI_awready(0) <= m01_couplers_to_m01_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m01_couplers_to_m01_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m01_couplers_to_m01_couplers_RVALID(0);
S_AXI_wready(0) <= m01_couplers_to_m01_couplers_WREADY(0);
m01_couplers_to_m01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m01_couplers_to_m01_couplers_ARREADY(0) <= M_AXI_arready(0);
m01_couplers_to_m01_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m01_couplers_to_m01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m01_couplers_to_m01_couplers_AWREADY(0) <= M_AXI_awready(0);
m01_couplers_to_m01_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m01_couplers_to_m01_couplers_BREADY(0) <= S_AXI_bready(0);
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID(0) <= M_AXI_bvalid(0);
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RREADY(0) <= S_AXI_rready(0);
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID(0) <= M_AXI_rvalid(0);
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WREADY(0) <= M_AXI_wready(0);
m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m02_couplers_imp_QYRHL1 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m02_couplers_imp_QYRHL1;
architecture STRUCTURE of m02_couplers_imp_QYRHL1 is
signal m02_couplers_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m02_couplers_to_m02_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m02_couplers_to_m02_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m02_couplers_to_m02_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m02_couplers_to_m02_couplers_AWVALID(0);
M_AXI_bready(0) <= m02_couplers_to_m02_couplers_BREADY(0);
M_AXI_rready(0) <= m02_couplers_to_m02_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m02_couplers_to_m02_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m02_couplers_to_m02_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m02_couplers_to_m02_couplers_WVALID(0);
S_AXI_arready(0) <= m02_couplers_to_m02_couplers_ARREADY(0);
S_AXI_awready(0) <= m02_couplers_to_m02_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m02_couplers_to_m02_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m02_couplers_to_m02_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m02_couplers_to_m02_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m02_couplers_to_m02_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m02_couplers_to_m02_couplers_RVALID(0);
S_AXI_wready(0) <= m02_couplers_to_m02_couplers_WREADY(0);
m02_couplers_to_m02_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m02_couplers_to_m02_couplers_ARREADY(0) <= M_AXI_arready(0);
m02_couplers_to_m02_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m02_couplers_to_m02_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m02_couplers_to_m02_couplers_AWREADY(0) <= M_AXI_awready(0);
m02_couplers_to_m02_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m02_couplers_to_m02_couplers_BREADY(0) <= S_AXI_bready(0);
m02_couplers_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m02_couplers_to_m02_couplers_BVALID(0) <= M_AXI_bvalid(0);
m02_couplers_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m02_couplers_to_m02_couplers_RREADY(0) <= S_AXI_rready(0);
m02_couplers_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m02_couplers_to_m02_couplers_RVALID(0) <= M_AXI_rvalid(0);
m02_couplers_to_m02_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m02_couplers_to_m02_couplers_WREADY(0) <= M_AXI_wready(0);
m02_couplers_to_m02_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m02_couplers_to_m02_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m03_couplers_imp_1LIFQL0 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m03_couplers_imp_1LIFQL0;
architecture STRUCTURE of m03_couplers_imp_1LIFQL0 is
signal m03_couplers_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m03_couplers_to_m03_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m03_couplers_to_m03_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m03_couplers_to_m03_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m03_couplers_to_m03_couplers_AWVALID(0);
M_AXI_bready(0) <= m03_couplers_to_m03_couplers_BREADY(0);
M_AXI_rready(0) <= m03_couplers_to_m03_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m03_couplers_to_m03_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m03_couplers_to_m03_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m03_couplers_to_m03_couplers_WVALID(0);
S_AXI_arready(0) <= m03_couplers_to_m03_couplers_ARREADY(0);
S_AXI_awready(0) <= m03_couplers_to_m03_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m03_couplers_to_m03_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m03_couplers_to_m03_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m03_couplers_to_m03_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m03_couplers_to_m03_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m03_couplers_to_m03_couplers_RVALID(0);
S_AXI_wready(0) <= m03_couplers_to_m03_couplers_WREADY(0);
m03_couplers_to_m03_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m03_couplers_to_m03_couplers_ARREADY(0) <= M_AXI_arready(0);
m03_couplers_to_m03_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m03_couplers_to_m03_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m03_couplers_to_m03_couplers_AWREADY(0) <= M_AXI_awready(0);
m03_couplers_to_m03_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m03_couplers_to_m03_couplers_BREADY(0) <= S_AXI_bready(0);
m03_couplers_to_m03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m03_couplers_to_m03_couplers_BVALID(0) <= M_AXI_bvalid(0);
m03_couplers_to_m03_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m03_couplers_to_m03_couplers_RREADY(0) <= S_AXI_rready(0);
m03_couplers_to_m03_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m03_couplers_to_m03_couplers_RVALID(0) <= M_AXI_rvalid(0);
m03_couplers_to_m03_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m03_couplers_to_m03_couplers_WREADY(0) <= M_AXI_wready(0);
m03_couplers_to_m03_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m03_couplers_to_m03_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m04_couplers_imp_E2VWV5 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m04_couplers_imp_E2VWV5;
architecture STRUCTURE of m04_couplers_imp_E2VWV5 is
signal m04_couplers_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_m04_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_m04_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_m04_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_m04_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m04_couplers_to_m04_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m04_couplers_to_m04_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m04_couplers_to_m04_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m04_couplers_to_m04_couplers_AWVALID(0);
M_AXI_bready(0) <= m04_couplers_to_m04_couplers_BREADY(0);
M_AXI_rready(0) <= m04_couplers_to_m04_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m04_couplers_to_m04_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m04_couplers_to_m04_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m04_couplers_to_m04_couplers_WVALID(0);
S_AXI_arready(0) <= m04_couplers_to_m04_couplers_ARREADY(0);
S_AXI_awready(0) <= m04_couplers_to_m04_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m04_couplers_to_m04_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m04_couplers_to_m04_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m04_couplers_to_m04_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m04_couplers_to_m04_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m04_couplers_to_m04_couplers_RVALID(0);
S_AXI_wready(0) <= m04_couplers_to_m04_couplers_WREADY(0);
m04_couplers_to_m04_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m04_couplers_to_m04_couplers_ARREADY(0) <= M_AXI_arready(0);
m04_couplers_to_m04_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m04_couplers_to_m04_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m04_couplers_to_m04_couplers_AWREADY(0) <= M_AXI_awready(0);
m04_couplers_to_m04_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m04_couplers_to_m04_couplers_BREADY(0) <= S_AXI_bready(0);
m04_couplers_to_m04_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m04_couplers_to_m04_couplers_BVALID(0) <= M_AXI_bvalid(0);
m04_couplers_to_m04_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m04_couplers_to_m04_couplers_RREADY(0) <= S_AXI_rready(0);
m04_couplers_to_m04_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m04_couplers_to_m04_couplers_RVALID(0) <= M_AXI_rvalid(0);
m04_couplers_to_m04_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m04_couplers_to_m04_couplers_WREADY(0) <= M_AXI_wready(0);
m04_couplers_to_m04_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m04_couplers_to_m04_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m05_couplers_imp_17ILSXC is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m05_couplers_imp_17ILSXC;
architecture STRUCTURE of m05_couplers_imp_17ILSXC is
signal m05_couplers_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_m05_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_m05_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_m05_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_m05_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m05_couplers_to_m05_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m05_couplers_to_m05_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m05_couplers_to_m05_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m05_couplers_to_m05_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m05_couplers_to_m05_couplers_AWVALID(0);
M_AXI_bready(0) <= m05_couplers_to_m05_couplers_BREADY(0);
M_AXI_rready(0) <= m05_couplers_to_m05_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m05_couplers_to_m05_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m05_couplers_to_m05_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m05_couplers_to_m05_couplers_WVALID(0);
S_AXI_arready(0) <= m05_couplers_to_m05_couplers_ARREADY(0);
S_AXI_awready(0) <= m05_couplers_to_m05_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m05_couplers_to_m05_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m05_couplers_to_m05_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m05_couplers_to_m05_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m05_couplers_to_m05_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m05_couplers_to_m05_couplers_RVALID(0);
S_AXI_wready(0) <= m05_couplers_to_m05_couplers_WREADY(0);
m05_couplers_to_m05_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m05_couplers_to_m05_couplers_ARREADY(0) <= M_AXI_arready(0);
m05_couplers_to_m05_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m05_couplers_to_m05_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m05_couplers_to_m05_couplers_AWREADY(0) <= M_AXI_awready(0);
m05_couplers_to_m05_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m05_couplers_to_m05_couplers_BREADY(0) <= S_AXI_bready(0);
m05_couplers_to_m05_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m05_couplers_to_m05_couplers_BVALID(0) <= M_AXI_bvalid(0);
m05_couplers_to_m05_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m05_couplers_to_m05_couplers_RREADY(0) <= S_AXI_rready(0);
m05_couplers_to_m05_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m05_couplers_to_m05_couplers_RVALID(0) <= M_AXI_rvalid(0);
m05_couplers_to_m05_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m05_couplers_to_m05_couplers_WREADY(0) <= M_AXI_wready(0);
m05_couplers_to_m05_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m05_couplers_to_m05_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m06_couplers_imp_1E95TTU is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m06_couplers_imp_1E95TTU;
architecture STRUCTURE of m06_couplers_imp_1E95TTU is
signal m06_couplers_to_m06_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_m06_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_m06_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_m06_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_m06_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_m06_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_m06_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_m06_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_m06_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_m06_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_m06_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_m06_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_m06_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m06_couplers_to_m06_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m06_couplers_to_m06_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m06_couplers_to_m06_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m06_couplers_to_m06_couplers_AWVALID(0);
M_AXI_bready(0) <= m06_couplers_to_m06_couplers_BREADY(0);
M_AXI_rready(0) <= m06_couplers_to_m06_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m06_couplers_to_m06_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m06_couplers_to_m06_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m06_couplers_to_m06_couplers_WVALID(0);
S_AXI_arready(0) <= m06_couplers_to_m06_couplers_ARREADY(0);
S_AXI_awready(0) <= m06_couplers_to_m06_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m06_couplers_to_m06_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m06_couplers_to_m06_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m06_couplers_to_m06_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m06_couplers_to_m06_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m06_couplers_to_m06_couplers_RVALID(0);
S_AXI_wready(0) <= m06_couplers_to_m06_couplers_WREADY(0);
m06_couplers_to_m06_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m06_couplers_to_m06_couplers_ARREADY(0) <= M_AXI_arready(0);
m06_couplers_to_m06_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m06_couplers_to_m06_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m06_couplers_to_m06_couplers_AWREADY(0) <= M_AXI_awready(0);
m06_couplers_to_m06_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m06_couplers_to_m06_couplers_BREADY(0) <= S_AXI_bready(0);
m06_couplers_to_m06_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m06_couplers_to_m06_couplers_BVALID(0) <= M_AXI_bvalid(0);
m06_couplers_to_m06_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m06_couplers_to_m06_couplers_RREADY(0) <= S_AXI_rready(0);
m06_couplers_to_m06_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m06_couplers_to_m06_couplers_RVALID(0) <= M_AXI_rvalid(0);
m06_couplers_to_m06_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m06_couplers_to_m06_couplers_WREADY(0) <= M_AXI_wready(0);
m06_couplers_to_m06_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m06_couplers_to_m06_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m07_couplers_imp_7MB6C3 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m07_couplers_imp_7MB6C3;
architecture STRUCTURE of m07_couplers_imp_7MB6C3 is
signal m07_couplers_to_m07_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m07_couplers_to_m07_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_m07_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_m07_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m07_couplers_to_m07_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_m07_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_m07_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_m07_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m07_couplers_to_m07_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_m07_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m07_couplers_to_m07_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_m07_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m07_couplers_to_m07_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_m07_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m07_couplers_to_m07_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_m07_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m07_couplers_to_m07_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m07_couplers_to_m07_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m07_couplers_to_m07_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m07_couplers_to_m07_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m07_couplers_to_m07_couplers_AWVALID(0);
M_AXI_bready(0) <= m07_couplers_to_m07_couplers_BREADY(0);
M_AXI_rready(0) <= m07_couplers_to_m07_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m07_couplers_to_m07_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m07_couplers_to_m07_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m07_couplers_to_m07_couplers_WVALID(0);
S_AXI_arready(0) <= m07_couplers_to_m07_couplers_ARREADY(0);
S_AXI_awready(0) <= m07_couplers_to_m07_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m07_couplers_to_m07_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m07_couplers_to_m07_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m07_couplers_to_m07_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m07_couplers_to_m07_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m07_couplers_to_m07_couplers_RVALID(0);
S_AXI_wready(0) <= m07_couplers_to_m07_couplers_WREADY(0);
m07_couplers_to_m07_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m07_couplers_to_m07_couplers_ARREADY(0) <= M_AXI_arready(0);
m07_couplers_to_m07_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m07_couplers_to_m07_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m07_couplers_to_m07_couplers_AWREADY(0) <= M_AXI_awready(0);
m07_couplers_to_m07_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m07_couplers_to_m07_couplers_BREADY(0) <= S_AXI_bready(0);
m07_couplers_to_m07_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m07_couplers_to_m07_couplers_BVALID(0) <= M_AXI_bvalid(0);
m07_couplers_to_m07_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m07_couplers_to_m07_couplers_RREADY(0) <= S_AXI_rready(0);
m07_couplers_to_m07_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m07_couplers_to_m07_couplers_RVALID(0) <= M_AXI_rvalid(0);
m07_couplers_to_m07_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m07_couplers_to_m07_couplers_WREADY(0) <= M_AXI_wready(0);
m07_couplers_to_m07_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m07_couplers_to_m07_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m08_couplers_imp_15IETBD is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m08_couplers_imp_15IETBD;
architecture STRUCTURE of m08_couplers_imp_15IETBD is
signal m08_couplers_to_m08_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m08_couplers_to_m08_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_m08_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_m08_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m08_couplers_to_m08_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_m08_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_m08_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_m08_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m08_couplers_to_m08_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_m08_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m08_couplers_to_m08_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_m08_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m08_couplers_to_m08_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_m08_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m08_couplers_to_m08_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_m08_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m08_couplers_to_m08_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m08_couplers_to_m08_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m08_couplers_to_m08_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m08_couplers_to_m08_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m08_couplers_to_m08_couplers_AWVALID(0);
M_AXI_bready(0) <= m08_couplers_to_m08_couplers_BREADY(0);
M_AXI_rready(0) <= m08_couplers_to_m08_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m08_couplers_to_m08_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m08_couplers_to_m08_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m08_couplers_to_m08_couplers_WVALID(0);
S_AXI_arready(0) <= m08_couplers_to_m08_couplers_ARREADY(0);
S_AXI_awready(0) <= m08_couplers_to_m08_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m08_couplers_to_m08_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m08_couplers_to_m08_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m08_couplers_to_m08_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m08_couplers_to_m08_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m08_couplers_to_m08_couplers_RVALID(0);
S_AXI_wready(0) <= m08_couplers_to_m08_couplers_WREADY(0);
m08_couplers_to_m08_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m08_couplers_to_m08_couplers_ARREADY(0) <= M_AXI_arready(0);
m08_couplers_to_m08_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m08_couplers_to_m08_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m08_couplers_to_m08_couplers_AWREADY(0) <= M_AXI_awready(0);
m08_couplers_to_m08_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m08_couplers_to_m08_couplers_BREADY(0) <= S_AXI_bready(0);
m08_couplers_to_m08_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m08_couplers_to_m08_couplers_BVALID(0) <= M_AXI_bvalid(0);
m08_couplers_to_m08_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m08_couplers_to_m08_couplers_RREADY(0) <= S_AXI_rready(0);
m08_couplers_to_m08_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m08_couplers_to_m08_couplers_RVALID(0) <= M_AXI_rvalid(0);
m08_couplers_to_m08_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m08_couplers_to_m08_couplers_WREADY(0) <= M_AXI_wready(0);
m08_couplers_to_m08_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m08_couplers_to_m08_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m09_couplers_imp_GMVR08 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m09_couplers_imp_GMVR08;
architecture STRUCTURE of m09_couplers_imp_GMVR08 is
signal m09_couplers_to_m09_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m09_couplers_to_m09_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_m09_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_m09_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m09_couplers_to_m09_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_m09_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_m09_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_m09_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m09_couplers_to_m09_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_m09_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m09_couplers_to_m09_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_m09_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m09_couplers_to_m09_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_m09_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m09_couplers_to_m09_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_m09_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m09_couplers_to_m09_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m09_couplers_to_m09_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m09_couplers_to_m09_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m09_couplers_to_m09_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m09_couplers_to_m09_couplers_AWVALID(0);
M_AXI_bready(0) <= m09_couplers_to_m09_couplers_BREADY(0);
M_AXI_rready(0) <= m09_couplers_to_m09_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m09_couplers_to_m09_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m09_couplers_to_m09_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m09_couplers_to_m09_couplers_WVALID(0);
S_AXI_arready(0) <= m09_couplers_to_m09_couplers_ARREADY(0);
S_AXI_awready(0) <= m09_couplers_to_m09_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m09_couplers_to_m09_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m09_couplers_to_m09_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m09_couplers_to_m09_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m09_couplers_to_m09_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m09_couplers_to_m09_couplers_RVALID(0);
S_AXI_wready(0) <= m09_couplers_to_m09_couplers_WREADY(0);
m09_couplers_to_m09_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m09_couplers_to_m09_couplers_ARREADY(0) <= M_AXI_arready(0);
m09_couplers_to_m09_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m09_couplers_to_m09_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m09_couplers_to_m09_couplers_AWREADY(0) <= M_AXI_awready(0);
m09_couplers_to_m09_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m09_couplers_to_m09_couplers_BREADY(0) <= S_AXI_bready(0);
m09_couplers_to_m09_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m09_couplers_to_m09_couplers_BVALID(0) <= M_AXI_bvalid(0);
m09_couplers_to_m09_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m09_couplers_to_m09_couplers_RREADY(0) <= S_AXI_rready(0);
m09_couplers_to_m09_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m09_couplers_to_m09_couplers_RVALID(0) <= M_AXI_rvalid(0);
m09_couplers_to_m09_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m09_couplers_to_m09_couplers_WREADY(0) <= M_AXI_wready(0);
m09_couplers_to_m09_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m09_couplers_to_m09_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m10_couplers_imp_QYIUP1 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC;
M_AXI_arprot : out STD_LOGIC;
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC;
M_AXI_awprot : out STD_LOGIC;
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC;
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC;
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC;
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC;
S_AXI_arprot : in STD_LOGIC;
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC;
S_AXI_awprot : in STD_LOGIC;
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC;
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC;
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC;
S_AXI_wvalid : in STD_LOGIC
);
end m10_couplers_imp_QYIUP1;
architecture STRUCTURE of m10_couplers_imp_QYIUP1 is
signal m10_couplers_to_m10_couplers_ARADDR : STD_LOGIC;
signal m10_couplers_to_m10_couplers_ARPROT : STD_LOGIC;
signal m10_couplers_to_m10_couplers_ARREADY : STD_LOGIC;
signal m10_couplers_to_m10_couplers_ARVALID : STD_LOGIC;
signal m10_couplers_to_m10_couplers_AWADDR : STD_LOGIC;
signal m10_couplers_to_m10_couplers_AWPROT : STD_LOGIC;
signal m10_couplers_to_m10_couplers_AWREADY : STD_LOGIC;
signal m10_couplers_to_m10_couplers_AWVALID : STD_LOGIC;
signal m10_couplers_to_m10_couplers_BREADY : STD_LOGIC;
signal m10_couplers_to_m10_couplers_BRESP : STD_LOGIC;
signal m10_couplers_to_m10_couplers_BVALID : STD_LOGIC;
signal m10_couplers_to_m10_couplers_RDATA : STD_LOGIC;
signal m10_couplers_to_m10_couplers_RREADY : STD_LOGIC;
signal m10_couplers_to_m10_couplers_RRESP : STD_LOGIC;
signal m10_couplers_to_m10_couplers_RVALID : STD_LOGIC;
signal m10_couplers_to_m10_couplers_WDATA : STD_LOGIC;
signal m10_couplers_to_m10_couplers_WREADY : STD_LOGIC;
signal m10_couplers_to_m10_couplers_WSTRB : STD_LOGIC;
signal m10_couplers_to_m10_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr <= m10_couplers_to_m10_couplers_ARADDR;
M_AXI_arprot <= m10_couplers_to_m10_couplers_ARPROT;
M_AXI_arvalid <= m10_couplers_to_m10_couplers_ARVALID;
M_AXI_awaddr <= m10_couplers_to_m10_couplers_AWADDR;
M_AXI_awprot <= m10_couplers_to_m10_couplers_AWPROT;
M_AXI_awvalid <= m10_couplers_to_m10_couplers_AWVALID;
M_AXI_bready <= m10_couplers_to_m10_couplers_BREADY;
M_AXI_rready <= m10_couplers_to_m10_couplers_RREADY;
M_AXI_wdata <= m10_couplers_to_m10_couplers_WDATA;
M_AXI_wstrb <= m10_couplers_to_m10_couplers_WSTRB;
M_AXI_wvalid <= m10_couplers_to_m10_couplers_WVALID;
S_AXI_arready <= m10_couplers_to_m10_couplers_ARREADY;
S_AXI_awready <= m10_couplers_to_m10_couplers_AWREADY;
S_AXI_bresp <= m10_couplers_to_m10_couplers_BRESP;
S_AXI_bvalid <= m10_couplers_to_m10_couplers_BVALID;
S_AXI_rdata <= m10_couplers_to_m10_couplers_RDATA;
S_AXI_rresp <= m10_couplers_to_m10_couplers_RRESP;
S_AXI_rvalid <= m10_couplers_to_m10_couplers_RVALID;
S_AXI_wready <= m10_couplers_to_m10_couplers_WREADY;
m10_couplers_to_m10_couplers_ARADDR <= S_AXI_araddr;
m10_couplers_to_m10_couplers_ARPROT <= S_AXI_arprot;
m10_couplers_to_m10_couplers_ARREADY <= M_AXI_arready;
m10_couplers_to_m10_couplers_ARVALID <= S_AXI_arvalid;
m10_couplers_to_m10_couplers_AWADDR <= S_AXI_awaddr;
m10_couplers_to_m10_couplers_AWPROT <= S_AXI_awprot;
m10_couplers_to_m10_couplers_AWREADY <= M_AXI_awready;
m10_couplers_to_m10_couplers_AWVALID <= S_AXI_awvalid;
m10_couplers_to_m10_couplers_BREADY <= S_AXI_bready;
m10_couplers_to_m10_couplers_BRESP <= M_AXI_bresp;
m10_couplers_to_m10_couplers_BVALID <= M_AXI_bvalid;
m10_couplers_to_m10_couplers_RDATA <= M_AXI_rdata;
m10_couplers_to_m10_couplers_RREADY <= S_AXI_rready;
m10_couplers_to_m10_couplers_RRESP <= M_AXI_rresp;
m10_couplers_to_m10_couplers_RVALID <= M_AXI_rvalid;
m10_couplers_to_m10_couplers_WDATA <= S_AXI_wdata;
m10_couplers_to_m10_couplers_WREADY <= M_AXI_wready;
m10_couplers_to_m10_couplers_WSTRB <= S_AXI_wstrb;
m10_couplers_to_m10_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m11_couplers_imp_1LI8I9G is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m11_couplers_imp_1LI8I9G;
architecture STRUCTURE of m11_couplers_imp_1LI8I9G is
signal m11_couplers_to_m11_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m11_couplers_to_m11_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_m11_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_m11_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m11_couplers_to_m11_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_m11_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_m11_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_m11_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m11_couplers_to_m11_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_m11_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m11_couplers_to_m11_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_m11_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m11_couplers_to_m11_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_m11_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m11_couplers_to_m11_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_m11_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m11_couplers_to_m11_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m11_couplers_to_m11_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m11_couplers_to_m11_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m11_couplers_to_m11_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m11_couplers_to_m11_couplers_AWVALID(0);
M_AXI_bready(0) <= m11_couplers_to_m11_couplers_BREADY(0);
M_AXI_rready(0) <= m11_couplers_to_m11_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m11_couplers_to_m11_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m11_couplers_to_m11_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m11_couplers_to_m11_couplers_WVALID(0);
S_AXI_arready(0) <= m11_couplers_to_m11_couplers_ARREADY(0);
S_AXI_awready(0) <= m11_couplers_to_m11_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m11_couplers_to_m11_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m11_couplers_to_m11_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m11_couplers_to_m11_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m11_couplers_to_m11_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m11_couplers_to_m11_couplers_RVALID(0);
S_AXI_wready(0) <= m11_couplers_to_m11_couplers_WREADY(0);
m11_couplers_to_m11_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m11_couplers_to_m11_couplers_ARREADY(0) <= M_AXI_arready(0);
m11_couplers_to_m11_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m11_couplers_to_m11_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m11_couplers_to_m11_couplers_AWREADY(0) <= M_AXI_awready(0);
m11_couplers_to_m11_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m11_couplers_to_m11_couplers_BREADY(0) <= S_AXI_bready(0);
m11_couplers_to_m11_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m11_couplers_to_m11_couplers_BVALID(0) <= M_AXI_bvalid(0);
m11_couplers_to_m11_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m11_couplers_to_m11_couplers_RREADY(0) <= S_AXI_rready(0);
m11_couplers_to_m11_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m11_couplers_to_m11_couplers_RVALID(0) <= M_AXI_rvalid(0);
m11_couplers_to_m11_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m11_couplers_to_m11_couplers_WREADY(0) <= M_AXI_wready(0);
m11_couplers_to_m11_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m11_couplers_to_m11_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m12_couplers_imp_1RYRHQE is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m12_couplers_imp_1RYRHQE;
architecture STRUCTURE of m12_couplers_imp_1RYRHQE is
signal m12_couplers_to_m12_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m12_couplers_to_m12_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_m12_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_m12_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m12_couplers_to_m12_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_m12_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_m12_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_m12_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m12_couplers_to_m12_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_m12_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m12_couplers_to_m12_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_m12_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m12_couplers_to_m12_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_m12_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m12_couplers_to_m12_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_m12_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m12_couplers_to_m12_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m12_couplers_to_m12_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m12_couplers_to_m12_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m12_couplers_to_m12_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m12_couplers_to_m12_couplers_AWVALID(0);
M_AXI_bready(0) <= m12_couplers_to_m12_couplers_BREADY(0);
M_AXI_rready(0) <= m12_couplers_to_m12_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m12_couplers_to_m12_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m12_couplers_to_m12_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m12_couplers_to_m12_couplers_WVALID(0);
S_AXI_arready(0) <= m12_couplers_to_m12_couplers_ARREADY(0);
S_AXI_awready(0) <= m12_couplers_to_m12_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m12_couplers_to_m12_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m12_couplers_to_m12_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m12_couplers_to_m12_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m12_couplers_to_m12_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m12_couplers_to_m12_couplers_RVALID(0);
S_AXI_wready(0) <= m12_couplers_to_m12_couplers_WREADY(0);
m12_couplers_to_m12_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m12_couplers_to_m12_couplers_ARREADY(0) <= M_AXI_arready(0);
m12_couplers_to_m12_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m12_couplers_to_m12_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m12_couplers_to_m12_couplers_AWREADY(0) <= M_AXI_awready(0);
m12_couplers_to_m12_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m12_couplers_to_m12_couplers_BREADY(0) <= S_AXI_bready(0);
m12_couplers_to_m12_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m12_couplers_to_m12_couplers_BVALID(0) <= M_AXI_bvalid(0);
m12_couplers_to_m12_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m12_couplers_to_m12_couplers_RREADY(0) <= S_AXI_rready(0);
m12_couplers_to_m12_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m12_couplers_to_m12_couplers_RVALID(0) <= M_AXI_rvalid(0);
m12_couplers_to_m12_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m12_couplers_to_m12_couplers_WREADY(0) <= M_AXI_wready(0);
m12_couplers_to_m12_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m12_couplers_to_m12_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m13_couplers_imp_K7ZVH3 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m13_couplers_imp_K7ZVH3;
architecture STRUCTURE of m13_couplers_imp_K7ZVH3 is
component system_auto_cc_1 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component system_auto_cc_1;
signal M_ACLK_1 : STD_LOGIC;
signal M_ARESETN_1 : STD_LOGIC;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_cc_to_m13_couplers_ARADDR : STD_LOGIC_VECTOR ( 10 downto 0 );
signal auto_cc_to_m13_couplers_ARREADY : STD_LOGIC;
signal auto_cc_to_m13_couplers_ARVALID : STD_LOGIC;
signal auto_cc_to_m13_couplers_AWADDR : STD_LOGIC_VECTOR ( 10 downto 0 );
signal auto_cc_to_m13_couplers_AWREADY : STD_LOGIC;
signal auto_cc_to_m13_couplers_AWVALID : STD_LOGIC;
signal auto_cc_to_m13_couplers_BREADY : STD_LOGIC;
signal auto_cc_to_m13_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_cc_to_m13_couplers_BVALID : STD_LOGIC;
signal auto_cc_to_m13_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_cc_to_m13_couplers_RREADY : STD_LOGIC;
signal auto_cc_to_m13_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_cc_to_m13_couplers_RVALID : STD_LOGIC;
signal auto_cc_to_m13_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_cc_to_m13_couplers_WREADY : STD_LOGIC;
signal auto_cc_to_m13_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_cc_to_m13_couplers_WVALID : STD_LOGIC;
signal m13_couplers_to_auto_cc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m13_couplers_to_auto_cc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m13_couplers_to_auto_cc_ARREADY : STD_LOGIC;
signal m13_couplers_to_auto_cc_ARVALID : STD_LOGIC;
signal m13_couplers_to_auto_cc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m13_couplers_to_auto_cc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m13_couplers_to_auto_cc_AWREADY : STD_LOGIC;
signal m13_couplers_to_auto_cc_AWVALID : STD_LOGIC;
signal m13_couplers_to_auto_cc_BREADY : STD_LOGIC;
signal m13_couplers_to_auto_cc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m13_couplers_to_auto_cc_BVALID : STD_LOGIC;
signal m13_couplers_to_auto_cc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m13_couplers_to_auto_cc_RREADY : STD_LOGIC;
signal m13_couplers_to_auto_cc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m13_couplers_to_auto_cc_RVALID : STD_LOGIC;
signal m13_couplers_to_auto_cc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m13_couplers_to_auto_cc_WREADY : STD_LOGIC;
signal m13_couplers_to_auto_cc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m13_couplers_to_auto_cc_WVALID : STD_LOGIC;
signal NLW_auto_cc_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_auto_cc_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
M_ACLK_1 <= M_ACLK;
M_ARESETN_1 <= M_ARESETN;
M_AXI_araddr(10 downto 0) <= auto_cc_to_m13_couplers_ARADDR(10 downto 0);
M_AXI_arvalid <= auto_cc_to_m13_couplers_ARVALID;
M_AXI_awaddr(10 downto 0) <= auto_cc_to_m13_couplers_AWADDR(10 downto 0);
M_AXI_awvalid <= auto_cc_to_m13_couplers_AWVALID;
M_AXI_bready <= auto_cc_to_m13_couplers_BREADY;
M_AXI_rready <= auto_cc_to_m13_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_cc_to_m13_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_cc_to_m13_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_cc_to_m13_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= m13_couplers_to_auto_cc_ARREADY;
S_AXI_awready <= m13_couplers_to_auto_cc_AWREADY;
S_AXI_bresp(1 downto 0) <= m13_couplers_to_auto_cc_BRESP(1 downto 0);
S_AXI_bvalid <= m13_couplers_to_auto_cc_BVALID;
S_AXI_rdata(31 downto 0) <= m13_couplers_to_auto_cc_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m13_couplers_to_auto_cc_RRESP(1 downto 0);
S_AXI_rvalid <= m13_couplers_to_auto_cc_RVALID;
S_AXI_wready <= m13_couplers_to_auto_cc_WREADY;
auto_cc_to_m13_couplers_ARREADY <= M_AXI_arready;
auto_cc_to_m13_couplers_AWREADY <= M_AXI_awready;
auto_cc_to_m13_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_cc_to_m13_couplers_BVALID <= M_AXI_bvalid;
auto_cc_to_m13_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_cc_to_m13_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_cc_to_m13_couplers_RVALID <= M_AXI_rvalid;
auto_cc_to_m13_couplers_WREADY <= M_AXI_wready;
m13_couplers_to_auto_cc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m13_couplers_to_auto_cc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m13_couplers_to_auto_cc_ARVALID <= S_AXI_arvalid;
m13_couplers_to_auto_cc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m13_couplers_to_auto_cc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m13_couplers_to_auto_cc_AWVALID <= S_AXI_awvalid;
m13_couplers_to_auto_cc_BREADY <= S_AXI_bready;
m13_couplers_to_auto_cc_RREADY <= S_AXI_rready;
m13_couplers_to_auto_cc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m13_couplers_to_auto_cc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m13_couplers_to_auto_cc_WVALID <= S_AXI_wvalid;
auto_cc: component system_auto_cc_1
port map (
m_axi_aclk => M_ACLK_1,
m_axi_araddr(10 downto 0) => auto_cc_to_m13_couplers_ARADDR(10 downto 0),
m_axi_aresetn => M_ARESETN_1,
m_axi_arprot(2 downto 0) => NLW_auto_cc_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arready => auto_cc_to_m13_couplers_ARREADY,
m_axi_arvalid => auto_cc_to_m13_couplers_ARVALID,
m_axi_awaddr(10 downto 0) => auto_cc_to_m13_couplers_AWADDR(10 downto 0),
m_axi_awprot(2 downto 0) => NLW_auto_cc_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awready => auto_cc_to_m13_couplers_AWREADY,
m_axi_awvalid => auto_cc_to_m13_couplers_AWVALID,
m_axi_bready => auto_cc_to_m13_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_cc_to_m13_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_cc_to_m13_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_cc_to_m13_couplers_RDATA(31 downto 0),
m_axi_rready => auto_cc_to_m13_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_cc_to_m13_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_cc_to_m13_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_cc_to_m13_couplers_WDATA(31 downto 0),
m_axi_wready => auto_cc_to_m13_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_cc_to_m13_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_cc_to_m13_couplers_WVALID,
s_axi_aclk => S_ACLK_1,
s_axi_araddr(10 downto 0) => m13_couplers_to_auto_cc_ARADDR(10 downto 0),
s_axi_aresetn => S_ARESETN_1,
s_axi_arprot(2 downto 0) => m13_couplers_to_auto_cc_ARPROT(2 downto 0),
s_axi_arready => m13_couplers_to_auto_cc_ARREADY,
s_axi_arvalid => m13_couplers_to_auto_cc_ARVALID,
s_axi_awaddr(10 downto 0) => m13_couplers_to_auto_cc_AWADDR(10 downto 0),
s_axi_awprot(2 downto 0) => m13_couplers_to_auto_cc_AWPROT(2 downto 0),
s_axi_awready => m13_couplers_to_auto_cc_AWREADY,
s_axi_awvalid => m13_couplers_to_auto_cc_AWVALID,
s_axi_bready => m13_couplers_to_auto_cc_BREADY,
s_axi_bresp(1 downto 0) => m13_couplers_to_auto_cc_BRESP(1 downto 0),
s_axi_bvalid => m13_couplers_to_auto_cc_BVALID,
s_axi_rdata(31 downto 0) => m13_couplers_to_auto_cc_RDATA(31 downto 0),
s_axi_rready => m13_couplers_to_auto_cc_RREADY,
s_axi_rresp(1 downto 0) => m13_couplers_to_auto_cc_RRESP(1 downto 0),
s_axi_rvalid => m13_couplers_to_auto_cc_RVALID,
s_axi_wdata(31 downto 0) => m13_couplers_to_auto_cc_WDATA(31 downto 0),
s_axi_wready => m13_couplers_to_auto_cc_WREADY,
s_axi_wstrb(3 downto 0) => m13_couplers_to_auto_cc_WSTRB(3 downto 0),
s_axi_wvalid => m13_couplers_to_auto_cc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity microblaze_0_local_memory_imp_OGE0N8 is
port (
DLMB_abus : in STD_LOGIC_VECTOR ( 0 to 31 );
DLMB_addrstrobe : in STD_LOGIC;
DLMB_be : in STD_LOGIC_VECTOR ( 0 to 3 );
DLMB_ce : out STD_LOGIC;
DLMB_readdbus : out STD_LOGIC_VECTOR ( 0 to 31 );
DLMB_readstrobe : in STD_LOGIC;
DLMB_ready : out STD_LOGIC;
DLMB_ue : out STD_LOGIC;
DLMB_wait : out STD_LOGIC;
DLMB_writedbus : in STD_LOGIC_VECTOR ( 0 to 31 );
DLMB_writestrobe : in STD_LOGIC;
ILMB_abus : in STD_LOGIC_VECTOR ( 0 to 31 );
ILMB_addrstrobe : in STD_LOGIC;
ILMB_ce : out STD_LOGIC;
ILMB_readdbus : out STD_LOGIC_VECTOR ( 0 to 31 );
ILMB_readstrobe : in STD_LOGIC;
ILMB_ready : out STD_LOGIC;
ILMB_ue : out STD_LOGIC;
ILMB_wait : out STD_LOGIC;
LMB_Clk : in STD_LOGIC;
SYS_Rst : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end microblaze_0_local_memory_imp_OGE0N8;
architecture STRUCTURE of microblaze_0_local_memory_imp_OGE0N8 is
component system_dlmb_bram_if_cntlr_0 is
port (
LMB_Clk : in STD_LOGIC;
LMB_Rst : in STD_LOGIC;
LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_AddrStrobe : in STD_LOGIC;
LMB_ReadStrobe : in STD_LOGIC;
LMB_WriteStrobe : in STD_LOGIC;
LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : out STD_LOGIC;
Sl_Wait : out STD_LOGIC;
Sl_UE : out STD_LOGIC;
Sl_CE : out STD_LOGIC;
BRAM_Rst_A : out STD_LOGIC;
BRAM_Clk_A : out STD_LOGIC;
BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_EN_A : out STD_LOGIC;
BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 )
);
end component system_dlmb_bram_if_cntlr_0;
component system_dlmb_v10_0 is
port (
LMB_Clk : in STD_LOGIC;
SYS_Rst : in STD_LOGIC;
LMB_Rst : out STD_LOGIC;
M_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_ReadStrobe : in STD_LOGIC;
M_WriteStrobe : in STD_LOGIC;
M_AddrStrobe : in STD_LOGIC;
M_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_Wait : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_UE : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
LMB_ABus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_ReadStrobe : out STD_LOGIC;
LMB_WriteStrobe : out STD_LOGIC;
LMB_AddrStrobe : out STD_LOGIC;
LMB_ReadDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Ready : out STD_LOGIC;
LMB_Wait : out STD_LOGIC;
LMB_UE : out STD_LOGIC;
LMB_CE : out STD_LOGIC;
LMB_BE : out STD_LOGIC_VECTOR ( 0 to 3 )
);
end component system_dlmb_v10_0;
component system_ilmb_bram_if_cntlr_0 is
port (
LMB_Clk : in STD_LOGIC;
LMB_Rst : in STD_LOGIC;
LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_AddrStrobe : in STD_LOGIC;
LMB_ReadStrobe : in STD_LOGIC;
LMB_WriteStrobe : in STD_LOGIC;
LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : out STD_LOGIC;
Sl_Wait : out STD_LOGIC;
Sl_UE : out STD_LOGIC;
Sl_CE : out STD_LOGIC;
BRAM_Rst_A : out STD_LOGIC;
BRAM_Clk_A : out STD_LOGIC;
BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_EN_A : out STD_LOGIC;
BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 )
);
end component system_ilmb_bram_if_cntlr_0;
component system_ilmb_v10_0 is
port (
LMB_Clk : in STD_LOGIC;
SYS_Rst : in STD_LOGIC;
LMB_Rst : out STD_LOGIC;
M_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_ReadStrobe : in STD_LOGIC;
M_WriteStrobe : in STD_LOGIC;
M_AddrStrobe : in STD_LOGIC;
M_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_Wait : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_UE : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
LMB_ABus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_ReadStrobe : out STD_LOGIC;
LMB_WriteStrobe : out STD_LOGIC;
LMB_AddrStrobe : out STD_LOGIC;
LMB_ReadDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Ready : out STD_LOGIC;
LMB_Wait : out STD_LOGIC;
LMB_UE : out STD_LOGIC;
LMB_CE : out STD_LOGIC;
LMB_BE : out STD_LOGIC_VECTOR ( 0 to 3 )
);
end component system_ilmb_v10_0;
component system_lmb_bram_0 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_lmb_bram_0;
signal SYS_Rst_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_Clk : STD_LOGIC;
signal microblaze_0_dlmb_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal microblaze_0_dlmb_CE : STD_LOGIC;
signal microblaze_0_dlmb_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_READSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_READY : STD_LOGIC;
signal microblaze_0_dlmb_UE : STD_LOGIC;
signal microblaze_0_dlmb_WAIT : STD_LOGIC;
signal microblaze_0_dlmb_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_WRITESTROBE : STD_LOGIC;
signal microblaze_0_dlmb_bus_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_bus_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_bus_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal microblaze_0_dlmb_bus_CE : STD_LOGIC;
signal microblaze_0_dlmb_bus_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_bus_READSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_bus_READY : STD_LOGIC;
signal microblaze_0_dlmb_bus_UE : STD_LOGIC;
signal microblaze_0_dlmb_bus_WAIT : STD_LOGIC;
signal microblaze_0_dlmb_bus_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_bus_WRITESTROBE : STD_LOGIC;
signal microblaze_0_dlmb_cntlr_ADDR : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_cntlr_CLK : STD_LOGIC;
signal microblaze_0_dlmb_cntlr_DIN : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_cntlr_DOUT : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_dlmb_cntlr_EN : STD_LOGIC;
signal microblaze_0_dlmb_cntlr_RST : STD_LOGIC;
signal microblaze_0_dlmb_cntlr_WE : STD_LOGIC_VECTOR ( 0 to 3 );
signal microblaze_0_ilmb_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_CE : STD_LOGIC;
signal microblaze_0_ilmb_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_READSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_READY : STD_LOGIC;
signal microblaze_0_ilmb_UE : STD_LOGIC;
signal microblaze_0_ilmb_WAIT : STD_LOGIC;
signal microblaze_0_ilmb_bus_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_bus_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_bus_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal microblaze_0_ilmb_bus_CE : STD_LOGIC;
signal microblaze_0_ilmb_bus_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_bus_READSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_bus_READY : STD_LOGIC;
signal microblaze_0_ilmb_bus_UE : STD_LOGIC;
signal microblaze_0_ilmb_bus_WAIT : STD_LOGIC;
signal microblaze_0_ilmb_bus_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_bus_WRITESTROBE : STD_LOGIC;
signal microblaze_0_ilmb_cntlr_ADDR : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_cntlr_CLK : STD_LOGIC;
signal microblaze_0_ilmb_cntlr_DIN : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_cntlr_DOUT : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_ilmb_cntlr_EN : STD_LOGIC;
signal microblaze_0_ilmb_cntlr_RST : STD_LOGIC;
signal microblaze_0_ilmb_cntlr_WE : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_dlmb_v10_LMB_Rst_UNCONNECTED : STD_LOGIC;
signal NLW_ilmb_v10_LMB_Rst_UNCONNECTED : STD_LOGIC;
attribute BMM_INFO_ADDRESS_SPACE : string;
attribute BMM_INFO_ADDRESS_SPACE of dlmb_bram_if_cntlr : label is "byte 0x00000000 32 > system microblaze_0_local_memory/lmb_bram";
attribute KEEP_HIERARCHY : string;
attribute KEEP_HIERARCHY of dlmb_bram_if_cntlr : label is "yes";
begin
DLMB_ce <= microblaze_0_dlmb_CE;
DLMB_readdbus(0 to 31) <= microblaze_0_dlmb_READDBUS(0 to 31);
DLMB_ready <= microblaze_0_dlmb_READY;
DLMB_ue <= microblaze_0_dlmb_UE;
DLMB_wait <= microblaze_0_dlmb_WAIT;
ILMB_ce <= microblaze_0_ilmb_CE;
ILMB_readdbus(0 to 31) <= microblaze_0_ilmb_READDBUS(0 to 31);
ILMB_ready <= microblaze_0_ilmb_READY;
ILMB_ue <= microblaze_0_ilmb_UE;
ILMB_wait <= microblaze_0_ilmb_WAIT;
SYS_Rst_1(0) <= SYS_Rst(0);
microblaze_0_Clk <= LMB_Clk;
microblaze_0_dlmb_ABUS(0 to 31) <= DLMB_abus(0 to 31);
microblaze_0_dlmb_ADDRSTROBE <= DLMB_addrstrobe;
microblaze_0_dlmb_BE(0 to 3) <= DLMB_be(0 to 3);
microblaze_0_dlmb_READSTROBE <= DLMB_readstrobe;
microblaze_0_dlmb_WRITEDBUS(0 to 31) <= DLMB_writedbus(0 to 31);
microblaze_0_dlmb_WRITESTROBE <= DLMB_writestrobe;
microblaze_0_ilmb_ABUS(0 to 31) <= ILMB_abus(0 to 31);
microblaze_0_ilmb_ADDRSTROBE <= ILMB_addrstrobe;
microblaze_0_ilmb_READSTROBE <= ILMB_readstrobe;
dlmb_bram_if_cntlr: component system_dlmb_bram_if_cntlr_0
port map (
BRAM_Addr_A(0 to 31) => microblaze_0_dlmb_cntlr_ADDR(0 to 31),
BRAM_Clk_A => microblaze_0_dlmb_cntlr_CLK,
BRAM_Din_A(0) => microblaze_0_dlmb_cntlr_DOUT(31),
BRAM_Din_A(1) => microblaze_0_dlmb_cntlr_DOUT(30),
BRAM_Din_A(2) => microblaze_0_dlmb_cntlr_DOUT(29),
BRAM_Din_A(3) => microblaze_0_dlmb_cntlr_DOUT(28),
BRAM_Din_A(4) => microblaze_0_dlmb_cntlr_DOUT(27),
BRAM_Din_A(5) => microblaze_0_dlmb_cntlr_DOUT(26),
BRAM_Din_A(6) => microblaze_0_dlmb_cntlr_DOUT(25),
BRAM_Din_A(7) => microblaze_0_dlmb_cntlr_DOUT(24),
BRAM_Din_A(8) => microblaze_0_dlmb_cntlr_DOUT(23),
BRAM_Din_A(9) => microblaze_0_dlmb_cntlr_DOUT(22),
BRAM_Din_A(10) => microblaze_0_dlmb_cntlr_DOUT(21),
BRAM_Din_A(11) => microblaze_0_dlmb_cntlr_DOUT(20),
BRAM_Din_A(12) => microblaze_0_dlmb_cntlr_DOUT(19),
BRAM_Din_A(13) => microblaze_0_dlmb_cntlr_DOUT(18),
BRAM_Din_A(14) => microblaze_0_dlmb_cntlr_DOUT(17),
BRAM_Din_A(15) => microblaze_0_dlmb_cntlr_DOUT(16),
BRAM_Din_A(16) => microblaze_0_dlmb_cntlr_DOUT(15),
BRAM_Din_A(17) => microblaze_0_dlmb_cntlr_DOUT(14),
BRAM_Din_A(18) => microblaze_0_dlmb_cntlr_DOUT(13),
BRAM_Din_A(19) => microblaze_0_dlmb_cntlr_DOUT(12),
BRAM_Din_A(20) => microblaze_0_dlmb_cntlr_DOUT(11),
BRAM_Din_A(21) => microblaze_0_dlmb_cntlr_DOUT(10),
BRAM_Din_A(22) => microblaze_0_dlmb_cntlr_DOUT(9),
BRAM_Din_A(23) => microblaze_0_dlmb_cntlr_DOUT(8),
BRAM_Din_A(24) => microblaze_0_dlmb_cntlr_DOUT(7),
BRAM_Din_A(25) => microblaze_0_dlmb_cntlr_DOUT(6),
BRAM_Din_A(26) => microblaze_0_dlmb_cntlr_DOUT(5),
BRAM_Din_A(27) => microblaze_0_dlmb_cntlr_DOUT(4),
BRAM_Din_A(28) => microblaze_0_dlmb_cntlr_DOUT(3),
BRAM_Din_A(29) => microblaze_0_dlmb_cntlr_DOUT(2),
BRAM_Din_A(30) => microblaze_0_dlmb_cntlr_DOUT(1),
BRAM_Din_A(31) => microblaze_0_dlmb_cntlr_DOUT(0),
BRAM_Dout_A(0 to 31) => microblaze_0_dlmb_cntlr_DIN(0 to 31),
BRAM_EN_A => microblaze_0_dlmb_cntlr_EN,
BRAM_Rst_A => microblaze_0_dlmb_cntlr_RST,
BRAM_WEN_A(0 to 3) => microblaze_0_dlmb_cntlr_WE(0 to 3),
LMB_ABus(0 to 31) => microblaze_0_dlmb_bus_ABUS(0 to 31),
LMB_AddrStrobe => microblaze_0_dlmb_bus_ADDRSTROBE,
LMB_BE(0 to 3) => microblaze_0_dlmb_bus_BE(0 to 3),
LMB_Clk => microblaze_0_Clk,
LMB_ReadStrobe => microblaze_0_dlmb_bus_READSTROBE,
LMB_Rst => SYS_Rst_1(0),
LMB_WriteDBus(0 to 31) => microblaze_0_dlmb_bus_WRITEDBUS(0 to 31),
LMB_WriteStrobe => microblaze_0_dlmb_bus_WRITESTROBE,
Sl_CE => microblaze_0_dlmb_bus_CE,
Sl_DBus(0 to 31) => microblaze_0_dlmb_bus_READDBUS(0 to 31),
Sl_Ready => microblaze_0_dlmb_bus_READY,
Sl_UE => microblaze_0_dlmb_bus_UE,
Sl_Wait => microblaze_0_dlmb_bus_WAIT
);
dlmb_v10: component system_dlmb_v10_0
port map (
LMB_ABus(0 to 31) => microblaze_0_dlmb_bus_ABUS(0 to 31),
LMB_AddrStrobe => microblaze_0_dlmb_bus_ADDRSTROBE,
LMB_BE(0 to 3) => microblaze_0_dlmb_bus_BE(0 to 3),
LMB_CE => microblaze_0_dlmb_CE,
LMB_Clk => microblaze_0_Clk,
LMB_ReadDBus(0 to 31) => microblaze_0_dlmb_READDBUS(0 to 31),
LMB_ReadStrobe => microblaze_0_dlmb_bus_READSTROBE,
LMB_Ready => microblaze_0_dlmb_READY,
LMB_Rst => NLW_dlmb_v10_LMB_Rst_UNCONNECTED,
LMB_UE => microblaze_0_dlmb_UE,
LMB_Wait => microblaze_0_dlmb_WAIT,
LMB_WriteDBus(0 to 31) => microblaze_0_dlmb_bus_WRITEDBUS(0 to 31),
LMB_WriteStrobe => microblaze_0_dlmb_bus_WRITESTROBE,
M_ABus(0 to 31) => microblaze_0_dlmb_ABUS(0 to 31),
M_AddrStrobe => microblaze_0_dlmb_ADDRSTROBE,
M_BE(0 to 3) => microblaze_0_dlmb_BE(0 to 3),
M_DBus(0 to 31) => microblaze_0_dlmb_WRITEDBUS(0 to 31),
M_ReadStrobe => microblaze_0_dlmb_READSTROBE,
M_WriteStrobe => microblaze_0_dlmb_WRITESTROBE,
SYS_Rst => SYS_Rst_1(0),
Sl_CE(0) => microblaze_0_dlmb_bus_CE,
Sl_DBus(0 to 31) => microblaze_0_dlmb_bus_READDBUS(0 to 31),
Sl_Ready(0) => microblaze_0_dlmb_bus_READY,
Sl_UE(0) => microblaze_0_dlmb_bus_UE,
Sl_Wait(0) => microblaze_0_dlmb_bus_WAIT
);
ilmb_bram_if_cntlr: component system_ilmb_bram_if_cntlr_0
port map (
BRAM_Addr_A(0 to 31) => microblaze_0_ilmb_cntlr_ADDR(0 to 31),
BRAM_Clk_A => microblaze_0_ilmb_cntlr_CLK,
BRAM_Din_A(0) => microblaze_0_ilmb_cntlr_DOUT(31),
BRAM_Din_A(1) => microblaze_0_ilmb_cntlr_DOUT(30),
BRAM_Din_A(2) => microblaze_0_ilmb_cntlr_DOUT(29),
BRAM_Din_A(3) => microblaze_0_ilmb_cntlr_DOUT(28),
BRAM_Din_A(4) => microblaze_0_ilmb_cntlr_DOUT(27),
BRAM_Din_A(5) => microblaze_0_ilmb_cntlr_DOUT(26),
BRAM_Din_A(6) => microblaze_0_ilmb_cntlr_DOUT(25),
BRAM_Din_A(7) => microblaze_0_ilmb_cntlr_DOUT(24),
BRAM_Din_A(8) => microblaze_0_ilmb_cntlr_DOUT(23),
BRAM_Din_A(9) => microblaze_0_ilmb_cntlr_DOUT(22),
BRAM_Din_A(10) => microblaze_0_ilmb_cntlr_DOUT(21),
BRAM_Din_A(11) => microblaze_0_ilmb_cntlr_DOUT(20),
BRAM_Din_A(12) => microblaze_0_ilmb_cntlr_DOUT(19),
BRAM_Din_A(13) => microblaze_0_ilmb_cntlr_DOUT(18),
BRAM_Din_A(14) => microblaze_0_ilmb_cntlr_DOUT(17),
BRAM_Din_A(15) => microblaze_0_ilmb_cntlr_DOUT(16),
BRAM_Din_A(16) => microblaze_0_ilmb_cntlr_DOUT(15),
BRAM_Din_A(17) => microblaze_0_ilmb_cntlr_DOUT(14),
BRAM_Din_A(18) => microblaze_0_ilmb_cntlr_DOUT(13),
BRAM_Din_A(19) => microblaze_0_ilmb_cntlr_DOUT(12),
BRAM_Din_A(20) => microblaze_0_ilmb_cntlr_DOUT(11),
BRAM_Din_A(21) => microblaze_0_ilmb_cntlr_DOUT(10),
BRAM_Din_A(22) => microblaze_0_ilmb_cntlr_DOUT(9),
BRAM_Din_A(23) => microblaze_0_ilmb_cntlr_DOUT(8),
BRAM_Din_A(24) => microblaze_0_ilmb_cntlr_DOUT(7),
BRAM_Din_A(25) => microblaze_0_ilmb_cntlr_DOUT(6),
BRAM_Din_A(26) => microblaze_0_ilmb_cntlr_DOUT(5),
BRAM_Din_A(27) => microblaze_0_ilmb_cntlr_DOUT(4),
BRAM_Din_A(28) => microblaze_0_ilmb_cntlr_DOUT(3),
BRAM_Din_A(29) => microblaze_0_ilmb_cntlr_DOUT(2),
BRAM_Din_A(30) => microblaze_0_ilmb_cntlr_DOUT(1),
BRAM_Din_A(31) => microblaze_0_ilmb_cntlr_DOUT(0),
BRAM_Dout_A(0 to 31) => microblaze_0_ilmb_cntlr_DIN(0 to 31),
BRAM_EN_A => microblaze_0_ilmb_cntlr_EN,
BRAM_Rst_A => microblaze_0_ilmb_cntlr_RST,
BRAM_WEN_A(0 to 3) => microblaze_0_ilmb_cntlr_WE(0 to 3),
LMB_ABus(0 to 31) => microblaze_0_ilmb_bus_ABUS(0 to 31),
LMB_AddrStrobe => microblaze_0_ilmb_bus_ADDRSTROBE,
LMB_BE(0 to 3) => microblaze_0_ilmb_bus_BE(0 to 3),
LMB_Clk => microblaze_0_Clk,
LMB_ReadStrobe => microblaze_0_ilmb_bus_READSTROBE,
LMB_Rst => SYS_Rst_1(0),
LMB_WriteDBus(0 to 31) => microblaze_0_ilmb_bus_WRITEDBUS(0 to 31),
LMB_WriteStrobe => microblaze_0_ilmb_bus_WRITESTROBE,
Sl_CE => microblaze_0_ilmb_bus_CE,
Sl_DBus(0 to 31) => microblaze_0_ilmb_bus_READDBUS(0 to 31),
Sl_Ready => microblaze_0_ilmb_bus_READY,
Sl_UE => microblaze_0_ilmb_bus_UE,
Sl_Wait => microblaze_0_ilmb_bus_WAIT
);
ilmb_v10: component system_ilmb_v10_0
port map (
LMB_ABus(0 to 31) => microblaze_0_ilmb_bus_ABUS(0 to 31),
LMB_AddrStrobe => microblaze_0_ilmb_bus_ADDRSTROBE,
LMB_BE(0 to 3) => microblaze_0_ilmb_bus_BE(0 to 3),
LMB_CE => microblaze_0_ilmb_CE,
LMB_Clk => microblaze_0_Clk,
LMB_ReadDBus(0 to 31) => microblaze_0_ilmb_READDBUS(0 to 31),
LMB_ReadStrobe => microblaze_0_ilmb_bus_READSTROBE,
LMB_Ready => microblaze_0_ilmb_READY,
LMB_Rst => NLW_ilmb_v10_LMB_Rst_UNCONNECTED,
LMB_UE => microblaze_0_ilmb_UE,
LMB_Wait => microblaze_0_ilmb_WAIT,
LMB_WriteDBus(0 to 31) => microblaze_0_ilmb_bus_WRITEDBUS(0 to 31),
LMB_WriteStrobe => microblaze_0_ilmb_bus_WRITESTROBE,
M_ABus(0 to 31) => microblaze_0_ilmb_ABUS(0 to 31),
M_AddrStrobe => microblaze_0_ilmb_ADDRSTROBE,
M_BE(0 to 3) => B"0000",
M_DBus(0 to 31) => B"00000000000000000000000000000000",
M_ReadStrobe => microblaze_0_ilmb_READSTROBE,
M_WriteStrobe => '0',
SYS_Rst => SYS_Rst_1(0),
Sl_CE(0) => microblaze_0_ilmb_bus_CE,
Sl_DBus(0 to 31) => microblaze_0_ilmb_bus_READDBUS(0 to 31),
Sl_Ready(0) => microblaze_0_ilmb_bus_READY,
Sl_UE(0) => microblaze_0_ilmb_bus_UE,
Sl_Wait(0) => microblaze_0_ilmb_bus_WAIT
);
lmb_bram: component system_lmb_bram_0
port map (
addra(31) => microblaze_0_dlmb_cntlr_ADDR(0),
addra(30) => microblaze_0_dlmb_cntlr_ADDR(1),
addra(29) => microblaze_0_dlmb_cntlr_ADDR(2),
addra(28) => microblaze_0_dlmb_cntlr_ADDR(3),
addra(27) => microblaze_0_dlmb_cntlr_ADDR(4),
addra(26) => microblaze_0_dlmb_cntlr_ADDR(5),
addra(25) => microblaze_0_dlmb_cntlr_ADDR(6),
addra(24) => microblaze_0_dlmb_cntlr_ADDR(7),
addra(23) => microblaze_0_dlmb_cntlr_ADDR(8),
addra(22) => microblaze_0_dlmb_cntlr_ADDR(9),
addra(21) => microblaze_0_dlmb_cntlr_ADDR(10),
addra(20) => microblaze_0_dlmb_cntlr_ADDR(11),
addra(19) => microblaze_0_dlmb_cntlr_ADDR(12),
addra(18) => microblaze_0_dlmb_cntlr_ADDR(13),
addra(17) => microblaze_0_dlmb_cntlr_ADDR(14),
addra(16) => microblaze_0_dlmb_cntlr_ADDR(15),
addra(15) => microblaze_0_dlmb_cntlr_ADDR(16),
addra(14) => microblaze_0_dlmb_cntlr_ADDR(17),
addra(13) => microblaze_0_dlmb_cntlr_ADDR(18),
addra(12) => microblaze_0_dlmb_cntlr_ADDR(19),
addra(11) => microblaze_0_dlmb_cntlr_ADDR(20),
addra(10) => microblaze_0_dlmb_cntlr_ADDR(21),
addra(9) => microblaze_0_dlmb_cntlr_ADDR(22),
addra(8) => microblaze_0_dlmb_cntlr_ADDR(23),
addra(7) => microblaze_0_dlmb_cntlr_ADDR(24),
addra(6) => microblaze_0_dlmb_cntlr_ADDR(25),
addra(5) => microblaze_0_dlmb_cntlr_ADDR(26),
addra(4) => microblaze_0_dlmb_cntlr_ADDR(27),
addra(3) => microblaze_0_dlmb_cntlr_ADDR(28),
addra(2) => microblaze_0_dlmb_cntlr_ADDR(29),
addra(1) => microblaze_0_dlmb_cntlr_ADDR(30),
addra(0) => microblaze_0_dlmb_cntlr_ADDR(31),
addrb(31) => microblaze_0_ilmb_cntlr_ADDR(0),
addrb(30) => microblaze_0_ilmb_cntlr_ADDR(1),
addrb(29) => microblaze_0_ilmb_cntlr_ADDR(2),
addrb(28) => microblaze_0_ilmb_cntlr_ADDR(3),
addrb(27) => microblaze_0_ilmb_cntlr_ADDR(4),
addrb(26) => microblaze_0_ilmb_cntlr_ADDR(5),
addrb(25) => microblaze_0_ilmb_cntlr_ADDR(6),
addrb(24) => microblaze_0_ilmb_cntlr_ADDR(7),
addrb(23) => microblaze_0_ilmb_cntlr_ADDR(8),
addrb(22) => microblaze_0_ilmb_cntlr_ADDR(9),
addrb(21) => microblaze_0_ilmb_cntlr_ADDR(10),
addrb(20) => microblaze_0_ilmb_cntlr_ADDR(11),
addrb(19) => microblaze_0_ilmb_cntlr_ADDR(12),
addrb(18) => microblaze_0_ilmb_cntlr_ADDR(13),
addrb(17) => microblaze_0_ilmb_cntlr_ADDR(14),
addrb(16) => microblaze_0_ilmb_cntlr_ADDR(15),
addrb(15) => microblaze_0_ilmb_cntlr_ADDR(16),
addrb(14) => microblaze_0_ilmb_cntlr_ADDR(17),
addrb(13) => microblaze_0_ilmb_cntlr_ADDR(18),
addrb(12) => microblaze_0_ilmb_cntlr_ADDR(19),
addrb(11) => microblaze_0_ilmb_cntlr_ADDR(20),
addrb(10) => microblaze_0_ilmb_cntlr_ADDR(21),
addrb(9) => microblaze_0_ilmb_cntlr_ADDR(22),
addrb(8) => microblaze_0_ilmb_cntlr_ADDR(23),
addrb(7) => microblaze_0_ilmb_cntlr_ADDR(24),
addrb(6) => microblaze_0_ilmb_cntlr_ADDR(25),
addrb(5) => microblaze_0_ilmb_cntlr_ADDR(26),
addrb(4) => microblaze_0_ilmb_cntlr_ADDR(27),
addrb(3) => microblaze_0_ilmb_cntlr_ADDR(28),
addrb(2) => microblaze_0_ilmb_cntlr_ADDR(29),
addrb(1) => microblaze_0_ilmb_cntlr_ADDR(30),
addrb(0) => microblaze_0_ilmb_cntlr_ADDR(31),
clka => microblaze_0_dlmb_cntlr_CLK,
clkb => microblaze_0_ilmb_cntlr_CLK,
dina(31) => microblaze_0_dlmb_cntlr_DIN(0),
dina(30) => microblaze_0_dlmb_cntlr_DIN(1),
dina(29) => microblaze_0_dlmb_cntlr_DIN(2),
dina(28) => microblaze_0_dlmb_cntlr_DIN(3),
dina(27) => microblaze_0_dlmb_cntlr_DIN(4),
dina(26) => microblaze_0_dlmb_cntlr_DIN(5),
dina(25) => microblaze_0_dlmb_cntlr_DIN(6),
dina(24) => microblaze_0_dlmb_cntlr_DIN(7),
dina(23) => microblaze_0_dlmb_cntlr_DIN(8),
dina(22) => microblaze_0_dlmb_cntlr_DIN(9),
dina(21) => microblaze_0_dlmb_cntlr_DIN(10),
dina(20) => microblaze_0_dlmb_cntlr_DIN(11),
dina(19) => microblaze_0_dlmb_cntlr_DIN(12),
dina(18) => microblaze_0_dlmb_cntlr_DIN(13),
dina(17) => microblaze_0_dlmb_cntlr_DIN(14),
dina(16) => microblaze_0_dlmb_cntlr_DIN(15),
dina(15) => microblaze_0_dlmb_cntlr_DIN(16),
dina(14) => microblaze_0_dlmb_cntlr_DIN(17),
dina(13) => microblaze_0_dlmb_cntlr_DIN(18),
dina(12) => microblaze_0_dlmb_cntlr_DIN(19),
dina(11) => microblaze_0_dlmb_cntlr_DIN(20),
dina(10) => microblaze_0_dlmb_cntlr_DIN(21),
dina(9) => microblaze_0_dlmb_cntlr_DIN(22),
dina(8) => microblaze_0_dlmb_cntlr_DIN(23),
dina(7) => microblaze_0_dlmb_cntlr_DIN(24),
dina(6) => microblaze_0_dlmb_cntlr_DIN(25),
dina(5) => microblaze_0_dlmb_cntlr_DIN(26),
dina(4) => microblaze_0_dlmb_cntlr_DIN(27),
dina(3) => microblaze_0_dlmb_cntlr_DIN(28),
dina(2) => microblaze_0_dlmb_cntlr_DIN(29),
dina(1) => microblaze_0_dlmb_cntlr_DIN(30),
dina(0) => microblaze_0_dlmb_cntlr_DIN(31),
dinb(31) => microblaze_0_ilmb_cntlr_DIN(0),
dinb(30) => microblaze_0_ilmb_cntlr_DIN(1),
dinb(29) => microblaze_0_ilmb_cntlr_DIN(2),
dinb(28) => microblaze_0_ilmb_cntlr_DIN(3),
dinb(27) => microblaze_0_ilmb_cntlr_DIN(4),
dinb(26) => microblaze_0_ilmb_cntlr_DIN(5),
dinb(25) => microblaze_0_ilmb_cntlr_DIN(6),
dinb(24) => microblaze_0_ilmb_cntlr_DIN(7),
dinb(23) => microblaze_0_ilmb_cntlr_DIN(8),
dinb(22) => microblaze_0_ilmb_cntlr_DIN(9),
dinb(21) => microblaze_0_ilmb_cntlr_DIN(10),
dinb(20) => microblaze_0_ilmb_cntlr_DIN(11),
dinb(19) => microblaze_0_ilmb_cntlr_DIN(12),
dinb(18) => microblaze_0_ilmb_cntlr_DIN(13),
dinb(17) => microblaze_0_ilmb_cntlr_DIN(14),
dinb(16) => microblaze_0_ilmb_cntlr_DIN(15),
dinb(15) => microblaze_0_ilmb_cntlr_DIN(16),
dinb(14) => microblaze_0_ilmb_cntlr_DIN(17),
dinb(13) => microblaze_0_ilmb_cntlr_DIN(18),
dinb(12) => microblaze_0_ilmb_cntlr_DIN(19),
dinb(11) => microblaze_0_ilmb_cntlr_DIN(20),
dinb(10) => microblaze_0_ilmb_cntlr_DIN(21),
dinb(9) => microblaze_0_ilmb_cntlr_DIN(22),
dinb(8) => microblaze_0_ilmb_cntlr_DIN(23),
dinb(7) => microblaze_0_ilmb_cntlr_DIN(24),
dinb(6) => microblaze_0_ilmb_cntlr_DIN(25),
dinb(5) => microblaze_0_ilmb_cntlr_DIN(26),
dinb(4) => microblaze_0_ilmb_cntlr_DIN(27),
dinb(3) => microblaze_0_ilmb_cntlr_DIN(28),
dinb(2) => microblaze_0_ilmb_cntlr_DIN(29),
dinb(1) => microblaze_0_ilmb_cntlr_DIN(30),
dinb(0) => microblaze_0_ilmb_cntlr_DIN(31),
douta(31 downto 0) => microblaze_0_dlmb_cntlr_DOUT(31 downto 0),
doutb(31 downto 0) => microblaze_0_ilmb_cntlr_DOUT(31 downto 0),
ena => microblaze_0_dlmb_cntlr_EN,
enb => microblaze_0_ilmb_cntlr_EN,
rsta => microblaze_0_dlmb_cntlr_RST,
rstb => microblaze_0_ilmb_cntlr_RST,
wea(3) => microblaze_0_dlmb_cntlr_WE(0),
wea(2) => microblaze_0_dlmb_cntlr_WE(1),
wea(1) => microblaze_0_dlmb_cntlr_WE(2),
wea(0) => microblaze_0_dlmb_cntlr_WE(3),
web(3) => microblaze_0_ilmb_cntlr_WE(0),
web(2) => microblaze_0_ilmb_cntlr_WE(1),
web(1) => microblaze_0_ilmb_cntlr_WE(2),
web(0) => microblaze_0_ilmb_cntlr_WE(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1LZPV07 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end s00_couplers_imp_1LZPV07;
architecture STRUCTURE of s00_couplers_imp_1LZPV07 is
signal s00_couplers_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= s00_couplers_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= s00_couplers_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid(0) <= s00_couplers_to_s00_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= s00_couplers_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= s00_couplers_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid(0) <= s00_couplers_to_s00_couplers_AWVALID(0);
M_AXI_bready(0) <= s00_couplers_to_s00_couplers_BREADY(0);
M_AXI_rready(0) <= s00_couplers_to_s00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= s00_couplers_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= s00_couplers_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= s00_couplers_to_s00_couplers_WVALID(0);
S_AXI_arready(0) <= s00_couplers_to_s00_couplers_ARREADY(0);
S_AXI_awready(0) <= s00_couplers_to_s00_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_s00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= s00_couplers_to_s00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= s00_couplers_to_s00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= s00_couplers_to_s00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= s00_couplers_to_s00_couplers_RVALID(0);
S_AXI_wready(0) <= s00_couplers_to_s00_couplers_WREADY(0);
s00_couplers_to_s00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_s00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_s00_couplers_ARREADY(0) <= M_AXI_arready(0);
s00_couplers_to_s00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
s00_couplers_to_s00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_s00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_s00_couplers_AWREADY(0) <= M_AXI_awready(0);
s00_couplers_to_s00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
s00_couplers_to_s00_couplers_BREADY(0) <= S_AXI_bready(0);
s00_couplers_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
s00_couplers_to_s00_couplers_BVALID(0) <= M_AXI_bvalid(0);
s00_couplers_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s00_couplers_to_s00_couplers_RREADY(0) <= S_AXI_rready(0);
s00_couplers_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s00_couplers_to_s00_couplers_RVALID(0) <= M_AXI_rvalid(0);
s00_couplers_to_s00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_s00_couplers_WREADY(0) <= M_AXI_wready(0);
s00_couplers_to_s00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_s00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1P403ZT is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC;
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC;
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_1P403ZT;
architecture STRUCTURE of s00_couplers_imp_1P403ZT is
component system_auto_us_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component system_auto_us_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_us_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_us_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_us_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_us_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_us_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_us_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_us_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_us_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_us_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal auto_us_to_s00_couplers_RLAST : STD_LOGIC;
signal auto_us_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_us_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_us_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal auto_us_to_s00_couplers_WLAST : STD_LOGIC;
signal auto_us_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_us_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 0 );
signal auto_us_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_us_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_us_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_us_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_us_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_auto_us_ARLOCK : STD_LOGIC;
signal s00_couplers_to_auto_us_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_us_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_us_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_us_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_us_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_us_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_us_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_us_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_us_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_auto_us_AWLOCK : STD_LOGIC;
signal s00_couplers_to_auto_us_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_us_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_us_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_us_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_us_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_us_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_us_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_us_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_us_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_us_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_us_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_us_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_us_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_us_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_us_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_us_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_us_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_us_WVALID : STD_LOGIC;
signal NLW_auto_us_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_auto_us_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_AXI_araddr(31 downto 0) <= auto_us_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_us_to_s00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_us_to_s00_couplers_ARCACHE(3 downto 0);
M_AXI_arlen(7 downto 0) <= auto_us_to_s00_couplers_ARLEN(7 downto 0);
M_AXI_arlock(0) <= auto_us_to_s00_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= auto_us_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_us_to_s00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_us_to_s00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_us_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_us_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= auto_us_to_s00_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_us_to_s00_couplers_AWCACHE(3 downto 0);
M_AXI_awlen(7 downto 0) <= auto_us_to_s00_couplers_AWLEN(7 downto 0);
M_AXI_awlock(0) <= auto_us_to_s00_couplers_AWLOCK(0);
M_AXI_awprot(2 downto 0) <= auto_us_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_us_to_s00_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_us_to_s00_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_us_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_us_to_s00_couplers_BREADY;
M_AXI_rready <= auto_us_to_s00_couplers_RREADY;
M_AXI_wdata(127 downto 0) <= auto_us_to_s00_couplers_WDATA(127 downto 0);
M_AXI_wlast <= auto_us_to_s00_couplers_WLAST;
M_AXI_wstrb(15 downto 0) <= auto_us_to_s00_couplers_WSTRB(15 downto 0);
M_AXI_wvalid <= auto_us_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= s00_couplers_to_auto_us_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_us_AWREADY;
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_us_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_us_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_us_RDATA(31 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_us_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_us_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_us_RVALID;
S_AXI_wready <= s00_couplers_to_auto_us_WREADY;
auto_us_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_us_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_us_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_us_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_us_to_s00_couplers_RDATA(127 downto 0) <= M_AXI_rdata(127 downto 0);
auto_us_to_s00_couplers_RLAST <= M_AXI_rlast;
auto_us_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_us_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_us_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_us_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_us_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_us_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_us_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s00_couplers_to_auto_us_ARLOCK <= S_AXI_arlock;
s00_couplers_to_auto_us_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_us_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_us_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_us_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_us_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_us_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_us_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_us_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s00_couplers_to_auto_us_AWLOCK <= S_AXI_awlock;
s00_couplers_to_auto_us_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_us_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_us_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_us_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_us_BREADY <= S_AXI_bready;
s00_couplers_to_auto_us_RREADY <= S_AXI_rready;
s00_couplers_to_auto_us_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_us_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_us_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_us_WVALID <= S_AXI_wvalid;
auto_us: component system_auto_us_0
port map (
m_axi_araddr(31 downto 0) => auto_us_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_us_to_s00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_us_to_s00_couplers_ARCACHE(3 downto 0),
m_axi_arlen(7 downto 0) => auto_us_to_s00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => auto_us_to_s00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => auto_us_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_us_to_s00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_us_to_s00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => NLW_auto_us_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => auto_us_to_s00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_us_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_us_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_us_to_s00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_us_to_s00_couplers_AWCACHE(3 downto 0),
m_axi_awlen(7 downto 0) => auto_us_to_s00_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => auto_us_to_s00_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => auto_us_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_us_to_s00_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_us_to_s00_couplers_AWREADY,
m_axi_awregion(3 downto 0) => NLW_auto_us_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => auto_us_to_s00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_us_to_s00_couplers_AWVALID,
m_axi_bready => auto_us_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_us_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_us_to_s00_couplers_BVALID,
m_axi_rdata(127 downto 0) => auto_us_to_s00_couplers_RDATA(127 downto 0),
m_axi_rlast => auto_us_to_s00_couplers_RLAST,
m_axi_rready => auto_us_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_us_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_us_to_s00_couplers_RVALID,
m_axi_wdata(127 downto 0) => auto_us_to_s00_couplers_WDATA(127 downto 0),
m_axi_wlast => auto_us_to_s00_couplers_WLAST,
m_axi_wready => auto_us_to_s00_couplers_WREADY,
m_axi_wstrb(15 downto 0) => auto_us_to_s00_couplers_WSTRB(15 downto 0),
m_axi_wvalid => auto_us_to_s00_couplers_WVALID,
s_axi_aclk => S_ACLK_1,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_us_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_us_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_us_ARCACHE(3 downto 0),
s_axi_aresetn => S_ARESETN_1,
s_axi_arlen(7 downto 0) => s00_couplers_to_auto_us_ARLEN(7 downto 0),
s_axi_arlock(0) => s00_couplers_to_auto_us_ARLOCK,
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_us_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_us_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_us_ARREADY,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_us_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_us_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_us_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_us_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_us_AWCACHE(3 downto 0),
s_axi_awlen(7 downto 0) => s00_couplers_to_auto_us_AWLEN(7 downto 0),
s_axi_awlock(0) => s00_couplers_to_auto_us_AWLOCK,
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_us_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_us_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_us_AWREADY,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_us_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_us_AWVALID,
s_axi_bready => s00_couplers_to_auto_us_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_us_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_us_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_us_RDATA(31 downto 0),
s_axi_rlast => s00_couplers_to_auto_us_RLAST,
s_axi_rready => s00_couplers_to_auto_us_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_us_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_us_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_us_WDATA(31 downto 0),
s_axi_wlast => s00_couplers_to_auto_us_WLAST,
s_axi_wready => s00_couplers_to_auto_us_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_us_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_us_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s01_couplers_imp_VQ497S is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC;
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC
);
end s01_couplers_imp_VQ497S;
architecture STRUCTURE of s01_couplers_imp_VQ497S is
component system_auto_us_1 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component system_auto_us_1;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_us_to_s01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_us_to_s01_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s01_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s01_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal auto_us_to_s01_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_us_to_s01_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s01_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_us_to_s01_couplers_ARREADY : STD_LOGIC;
signal auto_us_to_s01_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_us_to_s01_couplers_ARVALID : STD_LOGIC;
signal auto_us_to_s01_couplers_RDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal auto_us_to_s01_couplers_RLAST : STD_LOGIC;
signal auto_us_to_s01_couplers_RREADY : STD_LOGIC;
signal auto_us_to_s01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_us_to_s01_couplers_RVALID : STD_LOGIC;
signal s01_couplers_to_auto_us_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_auto_us_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_auto_us_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_auto_us_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_auto_us_ARLOCK : STD_LOGIC;
signal s01_couplers_to_auto_us_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_auto_us_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_auto_us_ARREADY : STD_LOGIC;
signal s01_couplers_to_auto_us_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_auto_us_ARVALID : STD_LOGIC;
signal s01_couplers_to_auto_us_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_auto_us_RLAST : STD_LOGIC;
signal s01_couplers_to_auto_us_RREADY : STD_LOGIC;
signal s01_couplers_to_auto_us_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_auto_us_RVALID : STD_LOGIC;
signal NLW_auto_us_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_AXI_araddr(31 downto 0) <= auto_us_to_s01_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_us_to_s01_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_us_to_s01_couplers_ARCACHE(3 downto 0);
M_AXI_arlen(7 downto 0) <= auto_us_to_s01_couplers_ARLEN(7 downto 0);
M_AXI_arlock(0) <= auto_us_to_s01_couplers_ARLOCK(0);
M_AXI_arprot(2 downto 0) <= auto_us_to_s01_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_us_to_s01_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_us_to_s01_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_us_to_s01_couplers_ARVALID;
M_AXI_rready <= auto_us_to_s01_couplers_RREADY;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= s01_couplers_to_auto_us_ARREADY;
S_AXI_rdata(31 downto 0) <= s01_couplers_to_auto_us_RDATA(31 downto 0);
S_AXI_rlast <= s01_couplers_to_auto_us_RLAST;
S_AXI_rresp(1 downto 0) <= s01_couplers_to_auto_us_RRESP(1 downto 0);
S_AXI_rvalid <= s01_couplers_to_auto_us_RVALID;
auto_us_to_s01_couplers_ARREADY <= M_AXI_arready;
auto_us_to_s01_couplers_RDATA(127 downto 0) <= M_AXI_rdata(127 downto 0);
auto_us_to_s01_couplers_RLAST <= M_AXI_rlast;
auto_us_to_s01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_us_to_s01_couplers_RVALID <= M_AXI_rvalid;
s01_couplers_to_auto_us_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s01_couplers_to_auto_us_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s01_couplers_to_auto_us_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s01_couplers_to_auto_us_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s01_couplers_to_auto_us_ARLOCK <= S_AXI_arlock;
s01_couplers_to_auto_us_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s01_couplers_to_auto_us_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s01_couplers_to_auto_us_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s01_couplers_to_auto_us_ARVALID <= S_AXI_arvalid;
s01_couplers_to_auto_us_RREADY <= S_AXI_rready;
auto_us: component system_auto_us_1
port map (
m_axi_araddr(31 downto 0) => auto_us_to_s01_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_us_to_s01_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_us_to_s01_couplers_ARCACHE(3 downto 0),
m_axi_arlen(7 downto 0) => auto_us_to_s01_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => auto_us_to_s01_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => auto_us_to_s01_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_us_to_s01_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_us_to_s01_couplers_ARREADY,
m_axi_arregion(3 downto 0) => NLW_auto_us_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => auto_us_to_s01_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_us_to_s01_couplers_ARVALID,
m_axi_rdata(127 downto 0) => auto_us_to_s01_couplers_RDATA(127 downto 0),
m_axi_rlast => auto_us_to_s01_couplers_RLAST,
m_axi_rready => auto_us_to_s01_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_us_to_s01_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_us_to_s01_couplers_RVALID,
s_axi_aclk => S_ACLK_1,
s_axi_araddr(31 downto 0) => s01_couplers_to_auto_us_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s01_couplers_to_auto_us_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s01_couplers_to_auto_us_ARCACHE(3 downto 0),
s_axi_aresetn => S_ARESETN_1,
s_axi_arlen(7 downto 0) => s01_couplers_to_auto_us_ARLEN(7 downto 0),
s_axi_arlock(0) => s01_couplers_to_auto_us_ARLOCK,
s_axi_arprot(2 downto 0) => s01_couplers_to_auto_us_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s01_couplers_to_auto_us_ARQOS(3 downto 0),
s_axi_arready => s01_couplers_to_auto_us_ARREADY,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s01_couplers_to_auto_us_ARSIZE(2 downto 0),
s_axi_arvalid => s01_couplers_to_auto_us_ARVALID,
s_axi_rdata(31 downto 0) => s01_couplers_to_auto_us_RDATA(31 downto 0),
s_axi_rlast => s01_couplers_to_auto_us_RLAST,
s_axi_rready => s01_couplers_to_auto_us_RREADY,
s_axi_rresp(1 downto 0) => s01_couplers_to_auto_us_RRESP(1 downto 0),
s_axi_rvalid => s01_couplers_to_auto_us_RVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_mem_intercon_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 27 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_arlock : out STD_LOGIC;
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 27 downto 0 );
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_awlock : out STD_LOGIC;
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
M00_AXI_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rlast : in STD_LOGIC;
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
M00_AXI_wlast : out STD_LOGIC;
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arlock : in STD_LOGIC;
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_awlock : in STD_LOGIC;
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC;
S01_ACLK : in STD_LOGIC;
S01_ARESETN : in STD_LOGIC;
S01_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_arlock : in STD_LOGIC;
S01_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_arready : out STD_LOGIC;
S01_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_arvalid : in STD_LOGIC;
S01_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_rlast : out STD_LOGIC;
S01_AXI_rready : in STD_LOGIC;
S01_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_rvalid : out STD_LOGIC
);
end system_axi_mem_intercon_0;
architecture STRUCTURE of system_axi_mem_intercon_0 is
component system_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 255 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC;
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC;
signal S01_ACLK_1 : STD_LOGIC;
signal S01_ARESETN_1 : STD_LOGIC;
signal axi_mem_intercon_ACLK_net : STD_LOGIC;
signal axi_mem_intercon_ARESETN_net : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARLOCK : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARVALID : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWLOCK : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWVALID : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_BREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_BVALID : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RLAST : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_RREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RVALID : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_WLAST : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_WREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_WVALID : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARLOCK : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARREADY : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_ARVALID : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_RLAST : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_RREADY : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_RVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_ARADDR : STD_LOGIC_VECTOR ( 27 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARLOCK : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_AWADDR : STD_LOGIC_VECTOR ( 27 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWLOCK : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_BREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_BVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_axi_mem_intercon_RLAST : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WLAST : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WSTRB : STD_LOGIC_VECTOR ( 15 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_xbar_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_xbar_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal s00_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal s00_couplers_to_xbar_WLAST : STD_LOGIC;
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 15 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal s01_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_xbar_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s01_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 255 downto 128 );
signal s01_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_RREADY : STD_LOGIC;
signal s01_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 3 downto 2 );
signal s01_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m00_couplers_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m00_couplers_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal xbar_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RLAST : STD_LOGIC;
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal xbar_to_m00_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xbar_s_axi_awready_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_xbar_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_xbar_s_axi_bvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_xbar_s_axi_wready_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1 <= M00_ARESETN;
M00_AXI_araddr(27 downto 0) <= m00_couplers_to_axi_mem_intercon_ARADDR(27 downto 0);
M00_AXI_arburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0);
M00_AXI_arcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0);
M00_AXI_arid(0) <= m00_couplers_to_axi_mem_intercon_ARID(0);
M00_AXI_arlen(7 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLEN(7 downto 0);
M00_AXI_arlock <= m00_couplers_to_axi_mem_intercon_ARLOCK;
M00_AXI_arprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0);
M00_AXI_arqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0);
M00_AXI_arsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0);
M00_AXI_arvalid <= m00_couplers_to_axi_mem_intercon_ARVALID;
M00_AXI_awaddr(27 downto 0) <= m00_couplers_to_axi_mem_intercon_AWADDR(27 downto 0);
M00_AXI_awburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0);
M00_AXI_awcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0);
M00_AXI_awid(0) <= m00_couplers_to_axi_mem_intercon_AWID(0);
M00_AXI_awlen(7 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLEN(7 downto 0);
M00_AXI_awlock <= m00_couplers_to_axi_mem_intercon_AWLOCK;
M00_AXI_awprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0);
M00_AXI_awqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0);
M00_AXI_awsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0);
M00_AXI_awvalid <= m00_couplers_to_axi_mem_intercon_AWVALID;
M00_AXI_bready <= m00_couplers_to_axi_mem_intercon_BREADY;
M00_AXI_rready <= m00_couplers_to_axi_mem_intercon_RREADY;
M00_AXI_wdata(127 downto 0) <= m00_couplers_to_axi_mem_intercon_WDATA(127 downto 0);
M00_AXI_wlast <= m00_couplers_to_axi_mem_intercon_WLAST;
M00_AXI_wstrb(15 downto 0) <= m00_couplers_to_axi_mem_intercon_WSTRB(15 downto 0);
M00_AXI_wvalid <= m00_couplers_to_axi_mem_intercon_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1 <= S00_ARESETN;
S00_AXI_arready <= axi_mem_intercon_to_s00_couplers_ARREADY;
S00_AXI_awready <= axi_mem_intercon_to_s00_couplers_AWREADY;
S00_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= axi_mem_intercon_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rlast <= axi_mem_intercon_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= axi_mem_intercon_to_s00_couplers_RVALID;
S00_AXI_wready <= axi_mem_intercon_to_s00_couplers_WREADY;
S01_ACLK_1 <= S01_ACLK;
S01_ARESETN_1 <= S01_ARESETN;
S01_AXI_arready <= axi_mem_intercon_to_s01_couplers_ARREADY;
S01_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s01_couplers_RDATA(31 downto 0);
S01_AXI_rlast <= axi_mem_intercon_to_s01_couplers_RLAST;
S01_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s01_couplers_RRESP(1 downto 0);
S01_AXI_rvalid <= axi_mem_intercon_to_s01_couplers_RVALID;
axi_mem_intercon_ACLK_net <= ACLK;
axi_mem_intercon_ARESETN_net <= ARESETN;
axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0) <= S00_AXI_arlen(7 downto 0);
axi_mem_intercon_to_s00_couplers_ARLOCK <= S00_AXI_arlock;
axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
axi_mem_intercon_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
axi_mem_intercon_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
axi_mem_intercon_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
axi_mem_intercon_to_s00_couplers_AWLEN(7 downto 0) <= S00_AXI_awlen(7 downto 0);
axi_mem_intercon_to_s00_couplers_AWLOCK <= S00_AXI_awlock;
axi_mem_intercon_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
axi_mem_intercon_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
axi_mem_intercon_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
axi_mem_intercon_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
axi_mem_intercon_to_s00_couplers_BREADY <= S00_AXI_bready;
axi_mem_intercon_to_s00_couplers_RREADY <= S00_AXI_rready;
axi_mem_intercon_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
axi_mem_intercon_to_s00_couplers_WLAST <= S00_AXI_wlast;
axi_mem_intercon_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
axi_mem_intercon_to_s00_couplers_WVALID <= S00_AXI_wvalid;
axi_mem_intercon_to_s01_couplers_ARADDR(31 downto 0) <= S01_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s01_couplers_ARBURST(1 downto 0) <= S01_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s01_couplers_ARCACHE(3 downto 0) <= S01_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s01_couplers_ARLEN(7 downto 0) <= S01_AXI_arlen(7 downto 0);
axi_mem_intercon_to_s01_couplers_ARLOCK <= S01_AXI_arlock;
axi_mem_intercon_to_s01_couplers_ARPROT(2 downto 0) <= S01_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s01_couplers_ARQOS(3 downto 0) <= S01_AXI_arqos(3 downto 0);
axi_mem_intercon_to_s01_couplers_ARSIZE(2 downto 0) <= S01_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s01_couplers_ARVALID <= S01_AXI_arvalid;
axi_mem_intercon_to_s01_couplers_RREADY <= S01_AXI_rready;
m00_couplers_to_axi_mem_intercon_ARREADY <= M00_AXI_arready;
m00_couplers_to_axi_mem_intercon_AWREADY <= M00_AXI_awready;
m00_couplers_to_axi_mem_intercon_BID(0) <= M00_AXI_bid(0);
m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_BVALID <= M00_AXI_bvalid;
m00_couplers_to_axi_mem_intercon_RDATA(127 downto 0) <= M00_AXI_rdata(127 downto 0);
m00_couplers_to_axi_mem_intercon_RID(0) <= M00_AXI_rid(0);
m00_couplers_to_axi_mem_intercon_RLAST <= M00_AXI_rlast;
m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_RVALID <= M00_AXI_rvalid;
m00_couplers_to_axi_mem_intercon_WREADY <= M00_AXI_wready;
m00_couplers: entity work.m00_couplers_imp_1TEAG88
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN => M00_ARESETN_1,
M_AXI_araddr(27 downto 0) => m00_couplers_to_axi_mem_intercon_ARADDR(27 downto 0),
M_AXI_arburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0),
M_AXI_arid(0) => m00_couplers_to_axi_mem_intercon_ARID(0),
M_AXI_arlen(7 downto 0) => m00_couplers_to_axi_mem_intercon_ARLEN(7 downto 0),
M_AXI_arlock => m00_couplers_to_axi_mem_intercon_ARLOCK,
M_AXI_arprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0),
M_AXI_arready => m00_couplers_to_axi_mem_intercon_ARREADY,
M_AXI_arsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0),
M_AXI_arvalid => m00_couplers_to_axi_mem_intercon_ARVALID,
M_AXI_awaddr(27 downto 0) => m00_couplers_to_axi_mem_intercon_AWADDR(27 downto 0),
M_AXI_awburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0),
M_AXI_awid(0) => m00_couplers_to_axi_mem_intercon_AWID(0),
M_AXI_awlen(7 downto 0) => m00_couplers_to_axi_mem_intercon_AWLEN(7 downto 0),
M_AXI_awlock => m00_couplers_to_axi_mem_intercon_AWLOCK,
M_AXI_awprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0),
M_AXI_awready => m00_couplers_to_axi_mem_intercon_AWREADY,
M_AXI_awsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0),
M_AXI_awvalid => m00_couplers_to_axi_mem_intercon_AWVALID,
M_AXI_bid(0) => m00_couplers_to_axi_mem_intercon_BID(0),
M_AXI_bready => m00_couplers_to_axi_mem_intercon_BREADY,
M_AXI_bresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0),
M_AXI_bvalid => m00_couplers_to_axi_mem_intercon_BVALID,
M_AXI_rdata(127 downto 0) => m00_couplers_to_axi_mem_intercon_RDATA(127 downto 0),
M_AXI_rid(0) => m00_couplers_to_axi_mem_intercon_RID(0),
M_AXI_rlast => m00_couplers_to_axi_mem_intercon_RLAST,
M_AXI_rready => m00_couplers_to_axi_mem_intercon_RREADY,
M_AXI_rresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0),
M_AXI_rvalid => m00_couplers_to_axi_mem_intercon_RVALID,
M_AXI_wdata(127 downto 0) => m00_couplers_to_axi_mem_intercon_WDATA(127 downto 0),
M_AXI_wlast => m00_couplers_to_axi_mem_intercon_WLAST,
M_AXI_wready => m00_couplers_to_axi_mem_intercon_WREADY,
M_AXI_wstrb(15 downto 0) => m00_couplers_to_axi_mem_intercon_WSTRB(15 downto 0),
M_AXI_wvalid => m00_couplers_to_axi_mem_intercon_WVALID,
S_ACLK => axi_mem_intercon_ACLK_net,
S_ARESETN => axi_mem_intercon_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(0) => xbar_to_m00_couplers_ARID(0),
S_AXI_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
S_AXI_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
S_AXI_arready => xbar_to_m00_couplers_ARREADY,
S_AXI_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
S_AXI_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(0) => xbar_to_m00_couplers_AWID(0),
S_AXI_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
S_AXI_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
S_AXI_awready => xbar_to_m00_couplers_AWREADY,
S_AXI_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
S_AXI_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bid(0) => xbar_to_m00_couplers_BID(0),
S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
S_AXI_rdata(127 downto 0) => xbar_to_m00_couplers_RDATA(127 downto 0),
S_AXI_rid(0) => xbar_to_m00_couplers_RID(0),
S_AXI_rlast => xbar_to_m00_couplers_RLAST,
S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
S_AXI_wdata(127 downto 0) => xbar_to_m00_couplers_WDATA(127 downto 0),
S_AXI_wlast => xbar_to_m00_couplers_WLAST(0),
S_AXI_wready => xbar_to_m00_couplers_WREADY,
S_AXI_wstrb(15 downto 0) => xbar_to_m00_couplers_WSTRB(15 downto 0),
S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
);
s00_couplers: entity work.s00_couplers_imp_1P403ZT
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN => axi_mem_intercon_ARESETN_net,
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arlock(0) => s00_couplers_to_xbar_ARLOCK(0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s00_couplers_to_xbar_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s00_couplers_to_xbar_AWCACHE(3 downto 0),
M_AXI_awlen(7 downto 0) => s00_couplers_to_xbar_AWLEN(7 downto 0),
M_AXI_awlock(0) => s00_couplers_to_xbar_AWLOCK(0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => s00_couplers_to_xbar_AWQOS(3 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awsize(2 downto 0) => s00_couplers_to_xbar_AWSIZE(2 downto 0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(127 downto 0) => s00_couplers_to_xbar_RDATA(127 downto 0),
M_AXI_rlast => s00_couplers_to_xbar_RLAST(0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(127 downto 0) => s00_couplers_to_xbar_WDATA(127 downto 0),
M_AXI_wlast => s00_couplers_to_xbar_WLAST,
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(15 downto 0) => s00_couplers_to_xbar_WSTRB(15 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN => S00_ARESETN_1,
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0),
S_AXI_arlock => axi_mem_intercon_to_s00_couplers_ARLOCK,
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => axi_mem_intercon_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_mem_intercon_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awlen(7 downto 0) => axi_mem_intercon_to_s00_couplers_AWLEN(7 downto 0),
S_AXI_awlock => axi_mem_intercon_to_s00_couplers_AWLOCK,
S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => axi_mem_intercon_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => axi_mem_intercon_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => axi_mem_intercon_to_s00_couplers_AWVALID,
S_AXI_bready => axi_mem_intercon_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => axi_mem_intercon_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rlast => axi_mem_intercon_to_s00_couplers_RLAST,
S_AXI_rready => axi_mem_intercon_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_mem_intercon_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wlast => axi_mem_intercon_to_s00_couplers_WLAST,
S_AXI_wready => axi_mem_intercon_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => axi_mem_intercon_to_s00_couplers_WVALID
);
s01_couplers: entity work.s01_couplers_imp_VQ497S
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN => axi_mem_intercon_ARESETN_net,
M_AXI_araddr(31 downto 0) => s01_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s01_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s01_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arlen(7 downto 0) => s01_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arlock(0) => s01_couplers_to_xbar_ARLOCK(0),
M_AXI_arprot(2 downto 0) => s01_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => s01_couplers_to_xbar_ARQOS(3 downto 0),
M_AXI_arready => s01_couplers_to_xbar_ARREADY(1),
M_AXI_arsize(2 downto 0) => s01_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid => s01_couplers_to_xbar_ARVALID,
M_AXI_rdata(127 downto 0) => s01_couplers_to_xbar_RDATA(255 downto 128),
M_AXI_rlast => s01_couplers_to_xbar_RLAST(1),
M_AXI_rready => s01_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s01_couplers_to_xbar_RRESP(3 downto 2),
M_AXI_rvalid => s01_couplers_to_xbar_RVALID(1),
S_ACLK => S01_ACLK_1,
S_ARESETN => S01_ARESETN_1,
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s01_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s01_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s01_couplers_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s01_couplers_ARLEN(7 downto 0),
S_AXI_arlock => axi_mem_intercon_to_s01_couplers_ARLOCK,
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s01_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => axi_mem_intercon_to_s01_couplers_ARQOS(3 downto 0),
S_AXI_arready => axi_mem_intercon_to_s01_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s01_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_mem_intercon_to_s01_couplers_ARVALID,
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s01_couplers_RDATA(31 downto 0),
S_AXI_rlast => axi_mem_intercon_to_s01_couplers_RLAST,
S_AXI_rready => axi_mem_intercon_to_s01_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s01_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_mem_intercon_to_s01_couplers_RVALID
);
xbar: component system_xbar_0
port map (
aclk => axi_mem_intercon_ACLK_net,
aresetn => axi_mem_intercon_ARESETN_net,
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_arid(0) => xbar_to_m00_couplers_ARID(0),
m_axi_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
m_axi_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awid(0) => xbar_to_m00_couplers_AWID(0),
m_axi_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
m_axi_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
m_axi_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bid(0) => xbar_to_m00_couplers_BID(0),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
m_axi_rdata(127 downto 0) => xbar_to_m00_couplers_RDATA(127 downto 0),
m_axi_rid(0) => xbar_to_m00_couplers_RID(0),
m_axi_rlast(0) => xbar_to_m00_couplers_RLAST,
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
m_axi_wdata(127 downto 0) => xbar_to_m00_couplers_WDATA(127 downto 0),
m_axi_wlast(0) => xbar_to_m00_couplers_WLAST(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
m_axi_wstrb(15 downto 0) => xbar_to_m00_couplers_WSTRB(15 downto 0),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(63 downto 32) => s01_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arburst(3 downto 2) => s01_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arcache(7 downto 4) => s01_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arid(1 downto 0) => B"00",
s_axi_arlen(15 downto 8) => s01_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlock(1) => s01_couplers_to_xbar_ARLOCK(0),
s_axi_arlock(0) => s00_couplers_to_xbar_ARLOCK(0),
s_axi_arprot(5 downto 3) => s01_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arqos(7 downto 4) => s01_couplers_to_xbar_ARQOS(3 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_xbar_ARQOS(3 downto 0),
s_axi_arready(1) => s01_couplers_to_xbar_ARREADY(1),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arsize(5 downto 3) => s01_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arvalid(1) => s01_couplers_to_xbar_ARVALID,
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(63 downto 32) => B"00000000000000000000000000000000",
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awburst(3 downto 2) => B"00",
s_axi_awburst(1 downto 0) => s00_couplers_to_xbar_AWBURST(1 downto 0),
s_axi_awcache(7 downto 4) => B"0000",
s_axi_awcache(3 downto 0) => s00_couplers_to_xbar_AWCACHE(3 downto 0),
s_axi_awid(1 downto 0) => B"00",
s_axi_awlen(15 downto 8) => B"00000000",
s_axi_awlen(7 downto 0) => s00_couplers_to_xbar_AWLEN(7 downto 0),
s_axi_awlock(1) => '0',
s_axi_awlock(0) => s00_couplers_to_xbar_AWLOCK(0),
s_axi_awprot(5 downto 3) => B"000",
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awqos(7 downto 4) => B"0000",
s_axi_awqos(3 downto 0) => s00_couplers_to_xbar_AWQOS(3 downto 0),
s_axi_awready(1) => NLW_xbar_s_axi_awready_UNCONNECTED(1),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awsize(5 downto 3) => B"000",
s_axi_awsize(2 downto 0) => s00_couplers_to_xbar_AWSIZE(2 downto 0),
s_axi_awvalid(1) => '0',
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bid(1 downto 0) => NLW_xbar_s_axi_bid_UNCONNECTED(1 downto 0),
s_axi_bready(1) => '0',
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(3 downto 2) => NLW_xbar_s_axi_bresp_UNCONNECTED(3 downto 2),
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(1) => NLW_xbar_s_axi_bvalid_UNCONNECTED(1),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(255 downto 128) => s01_couplers_to_xbar_RDATA(255 downto 128),
s_axi_rdata(127 downto 0) => s00_couplers_to_xbar_RDATA(127 downto 0),
s_axi_rid(1 downto 0) => NLW_xbar_s_axi_rid_UNCONNECTED(1 downto 0),
s_axi_rlast(1) => s01_couplers_to_xbar_RLAST(1),
s_axi_rlast(0) => s00_couplers_to_xbar_RLAST(0),
s_axi_rready(1) => s01_couplers_to_xbar_RREADY,
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(3 downto 2) => s01_couplers_to_xbar_RRESP(3 downto 2),
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(1) => s01_couplers_to_xbar_RVALID(1),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(255 downto 128) => B"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
s_axi_wdata(127 downto 0) => s00_couplers_to_xbar_WDATA(127 downto 0),
s_axi_wlast(1) => '1',
s_axi_wlast(0) => s00_couplers_to_xbar_WLAST,
s_axi_wready(1) => NLW_xbar_s_axi_wready_UNCONNECTED(1),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(31 downto 16) => B"1111111111111111",
s_axi_wstrb(15 downto 0) => s00_couplers_to_xbar_WSTRB(15 downto 0),
s_axi_wvalid(1) => '0',
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_microblaze_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC;
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_ACLK : in STD_LOGIC;
M02_ARESETN : in STD_LOGIC;
M02_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M02_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M03_ACLK : in STD_LOGIC;
M03_ARESETN : in STD_LOGIC;
M03_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M03_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M04_ACLK : in STD_LOGIC;
M04_ARESETN : in STD_LOGIC;
M04_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M04_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M05_ACLK : in STD_LOGIC;
M05_ARESETN : in STD_LOGIC;
M05_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M05_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M06_ACLK : in STD_LOGIC;
M06_ARESETN : in STD_LOGIC;
M06_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M06_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M06_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M06_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M07_ACLK : in STD_LOGIC;
M07_ARESETN : in STD_LOGIC;
M07_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M07_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M07_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M07_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M07_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M07_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M07_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M07_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M07_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M07_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M07_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M07_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M07_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M07_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M07_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M07_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M07_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M08_ACLK : in STD_LOGIC;
M08_ARESETN : in STD_LOGIC;
M08_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M08_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M08_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M08_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M08_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M08_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M08_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M08_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M08_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M08_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M08_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M08_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M08_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M08_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M08_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M08_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M08_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M09_ACLK : in STD_LOGIC;
M09_ARESETN : in STD_LOGIC;
M09_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M09_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M09_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M09_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M09_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M09_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M09_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M09_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M09_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M09_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M09_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M09_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M09_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M09_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M09_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M09_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M09_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M10_ACLK : in STD_LOGIC;
M10_ARESETN : in STD_LOGIC;
M10_AXI_araddr : out STD_LOGIC;
M10_AXI_arprot : out STD_LOGIC;
M10_AXI_arready : in STD_LOGIC;
M10_AXI_arvalid : out STD_LOGIC;
M10_AXI_awaddr : out STD_LOGIC;
M10_AXI_awprot : out STD_LOGIC;
M10_AXI_awready : in STD_LOGIC;
M10_AXI_awvalid : out STD_LOGIC;
M10_AXI_bready : out STD_LOGIC;
M10_AXI_bresp : in STD_LOGIC;
M10_AXI_bvalid : in STD_LOGIC;
M10_AXI_rdata : in STD_LOGIC;
M10_AXI_rready : out STD_LOGIC;
M10_AXI_rresp : in STD_LOGIC;
M10_AXI_rvalid : in STD_LOGIC;
M10_AXI_wdata : out STD_LOGIC;
M10_AXI_wready : in STD_LOGIC;
M10_AXI_wstrb : out STD_LOGIC;
M10_AXI_wvalid : out STD_LOGIC;
M11_ACLK : in STD_LOGIC;
M11_ARESETN : in STD_LOGIC;
M11_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M11_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M11_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M11_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M11_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M11_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M11_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M11_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M11_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M11_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M11_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M11_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M11_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M11_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M11_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M11_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M11_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M12_ACLK : in STD_LOGIC;
M12_ARESETN : in STD_LOGIC;
M12_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M12_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M12_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M12_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M12_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M12_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M12_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M12_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M12_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M12_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M12_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M12_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M12_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M12_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M12_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M12_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M12_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M13_ACLK : in STD_LOGIC;
M13_ARESETN : in STD_LOGIC;
M13_AXI_araddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
M13_AXI_arready : in STD_LOGIC;
M13_AXI_arvalid : out STD_LOGIC;
M13_AXI_awaddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
M13_AXI_awready : in STD_LOGIC;
M13_AXI_awvalid : out STD_LOGIC;
M13_AXI_bready : out STD_LOGIC;
M13_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M13_AXI_bvalid : in STD_LOGIC;
M13_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M13_AXI_rready : out STD_LOGIC;
M13_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M13_AXI_rvalid : in STD_LOGIC;
M13_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M13_AXI_wready : in STD_LOGIC;
M13_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M13_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_microblaze_0_axi_periph_0;
architecture STRUCTURE of system_microblaze_0_axi_periph_0 is
component system_xbar_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 447 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 41 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 447 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 55 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 447 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 41 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 447 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 13 downto 0 )
);
end component system_xbar_1;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC;
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC;
signal M02_ACLK_1 : STD_LOGIC;
signal M02_ARESETN_1 : STD_LOGIC;
signal M03_ACLK_1 : STD_LOGIC;
signal M03_ARESETN_1 : STD_LOGIC;
signal M04_ACLK_1 : STD_LOGIC;
signal M04_ARESETN_1 : STD_LOGIC;
signal M05_ACLK_1 : STD_LOGIC;
signal M05_ARESETN_1 : STD_LOGIC;
signal M06_ACLK_1 : STD_LOGIC;
signal M06_ARESETN_1 : STD_LOGIC;
signal M07_ACLK_1 : STD_LOGIC;
signal M07_ARESETN_1 : STD_LOGIC;
signal M08_ACLK_1 : STD_LOGIC;
signal M08_ARESETN_1 : STD_LOGIC;
signal M09_ACLK_1 : STD_LOGIC;
signal M09_ARESETN_1 : STD_LOGIC;
signal M10_ACLK_1 : STD_LOGIC;
signal M10_ARESETN_1 : STD_LOGIC;
signal M11_ACLK_1 : STD_LOGIC;
signal M11_ARESETN_1 : STD_LOGIC;
signal M12_ACLK_1 : STD_LOGIC;
signal M12_ARESETN_1 : STD_LOGIC;
signal M13_ACLK_1 : STD_LOGIC;
signal M13_ARESETN_1 : STD_LOGIC;
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m04_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m05_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m05_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m06_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m07_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m07_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m07_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m07_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m07_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m07_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m07_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m07_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m08_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m08_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m08_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m08_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m08_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m08_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m08_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m08_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m09_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m09_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m09_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m09_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m09_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m09_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m09_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m09_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m10_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_ARPROT : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_AWPROT : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC;
signal m10_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC;
signal m11_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m11_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m11_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m11_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m11_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m11_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m11_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m11_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m11_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m12_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m12_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m12_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m12_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m12_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m12_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m12_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m12_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m13_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 10 downto 0 );
signal m13_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC;
signal m13_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC;
signal m13_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 10 downto 0 );
signal m13_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC;
signal m13_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC;
signal m13_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC;
signal m13_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m13_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC;
signal m13_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m13_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC;
signal m13_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m13_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC;
signal m13_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m13_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC;
signal m13_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m13_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC;
signal microblaze_0_axi_periph_ACLK_net : STD_LOGIC;
signal microblaze_0_axi_periph_ARESETN_net : STD_LOGIC;
signal microblaze_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 12 );
signal xbar_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m04_couplers_ARVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m04_couplers_AWVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m04_couplers_RREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 19 downto 16 );
signal xbar_to_m04_couplers_WVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m05_couplers_ARVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m05_couplers_AWVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m05_couplers_RREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m05_couplers_WSTRB : STD_LOGIC_VECTOR ( 23 downto 20 );
signal xbar_to_m05_couplers_WVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m06_couplers_ARADDR : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m06_couplers_ARVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_AWADDR : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m06_couplers_AWVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_BREADY : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m06_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m06_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m06_couplers_RREADY : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m06_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m06_couplers_WDATA : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m06_couplers_WSTRB : STD_LOGIC_VECTOR ( 27 downto 24 );
signal xbar_to_m06_couplers_WVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m07_couplers_ARADDR : STD_LOGIC_VECTOR ( 255 downto 224 );
signal xbar_to_m07_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m07_couplers_ARVALID : STD_LOGIC_VECTOR ( 7 to 7 );
signal xbar_to_m07_couplers_AWADDR : STD_LOGIC_VECTOR ( 255 downto 224 );
signal xbar_to_m07_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m07_couplers_AWVALID : STD_LOGIC_VECTOR ( 7 to 7 );
signal xbar_to_m07_couplers_BREADY : STD_LOGIC_VECTOR ( 7 to 7 );
signal xbar_to_m07_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m07_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m07_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m07_couplers_RREADY : STD_LOGIC_VECTOR ( 7 to 7 );
signal xbar_to_m07_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m07_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m07_couplers_WDATA : STD_LOGIC_VECTOR ( 255 downto 224 );
signal xbar_to_m07_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m07_couplers_WSTRB : STD_LOGIC_VECTOR ( 31 downto 28 );
signal xbar_to_m07_couplers_WVALID : STD_LOGIC_VECTOR ( 7 to 7 );
signal xbar_to_m08_couplers_ARADDR : STD_LOGIC_VECTOR ( 287 downto 256 );
signal xbar_to_m08_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m08_couplers_ARVALID : STD_LOGIC_VECTOR ( 8 to 8 );
signal xbar_to_m08_couplers_AWADDR : STD_LOGIC_VECTOR ( 287 downto 256 );
signal xbar_to_m08_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m08_couplers_AWVALID : STD_LOGIC_VECTOR ( 8 to 8 );
signal xbar_to_m08_couplers_BREADY : STD_LOGIC_VECTOR ( 8 to 8 );
signal xbar_to_m08_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m08_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m08_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m08_couplers_RREADY : STD_LOGIC_VECTOR ( 8 to 8 );
signal xbar_to_m08_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m08_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m08_couplers_WDATA : STD_LOGIC_VECTOR ( 287 downto 256 );
signal xbar_to_m08_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m08_couplers_WSTRB : STD_LOGIC_VECTOR ( 35 downto 32 );
signal xbar_to_m08_couplers_WVALID : STD_LOGIC_VECTOR ( 8 to 8 );
signal xbar_to_m09_couplers_ARADDR : STD_LOGIC_VECTOR ( 319 downto 288 );
signal xbar_to_m09_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m09_couplers_ARVALID : STD_LOGIC_VECTOR ( 9 to 9 );
signal xbar_to_m09_couplers_AWADDR : STD_LOGIC_VECTOR ( 319 downto 288 );
signal xbar_to_m09_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m09_couplers_AWVALID : STD_LOGIC_VECTOR ( 9 to 9 );
signal xbar_to_m09_couplers_BREADY : STD_LOGIC_VECTOR ( 9 to 9 );
signal xbar_to_m09_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m09_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m09_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m09_couplers_RREADY : STD_LOGIC_VECTOR ( 9 to 9 );
signal xbar_to_m09_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m09_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m09_couplers_WDATA : STD_LOGIC_VECTOR ( 319 downto 288 );
signal xbar_to_m09_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m09_couplers_WSTRB : STD_LOGIC_VECTOR ( 39 downto 36 );
signal xbar_to_m09_couplers_WVALID : STD_LOGIC_VECTOR ( 9 to 9 );
signal xbar_to_m10_couplers_ARADDR : STD_LOGIC_VECTOR ( 351 downto 320 );
signal xbar_to_m10_couplers_ARPROT : STD_LOGIC_VECTOR ( 32 downto 30 );
signal xbar_to_m10_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m10_couplers_ARVALID : STD_LOGIC_VECTOR ( 10 to 10 );
signal xbar_to_m10_couplers_AWADDR : STD_LOGIC_VECTOR ( 351 downto 320 );
signal xbar_to_m10_couplers_AWPROT : STD_LOGIC_VECTOR ( 32 downto 30 );
signal xbar_to_m10_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m10_couplers_AWVALID : STD_LOGIC_VECTOR ( 10 to 10 );
signal xbar_to_m10_couplers_BREADY : STD_LOGIC_VECTOR ( 10 to 10 );
signal xbar_to_m10_couplers_BRESP : STD_LOGIC;
signal xbar_to_m10_couplers_BVALID : STD_LOGIC;
signal xbar_to_m10_couplers_RDATA : STD_LOGIC;
signal xbar_to_m10_couplers_RREADY : STD_LOGIC_VECTOR ( 10 to 10 );
signal xbar_to_m10_couplers_RRESP : STD_LOGIC;
signal xbar_to_m10_couplers_RVALID : STD_LOGIC;
signal xbar_to_m10_couplers_WDATA : STD_LOGIC_VECTOR ( 351 downto 320 );
signal xbar_to_m10_couplers_WREADY : STD_LOGIC;
signal xbar_to_m10_couplers_WSTRB : STD_LOGIC_VECTOR ( 43 downto 40 );
signal xbar_to_m10_couplers_WVALID : STD_LOGIC_VECTOR ( 10 to 10 );
signal xbar_to_m11_couplers_ARADDR : STD_LOGIC_VECTOR ( 383 downto 352 );
signal xbar_to_m11_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m11_couplers_ARVALID : STD_LOGIC_VECTOR ( 11 to 11 );
signal xbar_to_m11_couplers_AWADDR : STD_LOGIC_VECTOR ( 383 downto 352 );
signal xbar_to_m11_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m11_couplers_AWVALID : STD_LOGIC_VECTOR ( 11 to 11 );
signal xbar_to_m11_couplers_BREADY : STD_LOGIC_VECTOR ( 11 to 11 );
signal xbar_to_m11_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m11_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m11_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m11_couplers_RREADY : STD_LOGIC_VECTOR ( 11 to 11 );
signal xbar_to_m11_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m11_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m11_couplers_WDATA : STD_LOGIC_VECTOR ( 383 downto 352 );
signal xbar_to_m11_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m11_couplers_WSTRB : STD_LOGIC_VECTOR ( 47 downto 44 );
signal xbar_to_m11_couplers_WVALID : STD_LOGIC_VECTOR ( 11 to 11 );
signal xbar_to_m12_couplers_ARADDR : STD_LOGIC_VECTOR ( 415 downto 384 );
signal xbar_to_m12_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m12_couplers_ARVALID : STD_LOGIC_VECTOR ( 12 to 12 );
signal xbar_to_m12_couplers_AWADDR : STD_LOGIC_VECTOR ( 415 downto 384 );
signal xbar_to_m12_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m12_couplers_AWVALID : STD_LOGIC_VECTOR ( 12 to 12 );
signal xbar_to_m12_couplers_BREADY : STD_LOGIC_VECTOR ( 12 to 12 );
signal xbar_to_m12_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m12_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m12_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m12_couplers_RREADY : STD_LOGIC_VECTOR ( 12 to 12 );
signal xbar_to_m12_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m12_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m12_couplers_WDATA : STD_LOGIC_VECTOR ( 415 downto 384 );
signal xbar_to_m12_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m12_couplers_WSTRB : STD_LOGIC_VECTOR ( 51 downto 48 );
signal xbar_to_m12_couplers_WVALID : STD_LOGIC_VECTOR ( 12 to 12 );
signal xbar_to_m13_couplers_ARADDR : STD_LOGIC_VECTOR ( 447 downto 416 );
signal xbar_to_m13_couplers_ARPROT : STD_LOGIC_VECTOR ( 41 downto 39 );
signal xbar_to_m13_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m13_couplers_ARVALID : STD_LOGIC_VECTOR ( 13 to 13 );
signal xbar_to_m13_couplers_AWADDR : STD_LOGIC_VECTOR ( 447 downto 416 );
signal xbar_to_m13_couplers_AWPROT : STD_LOGIC_VECTOR ( 41 downto 39 );
signal xbar_to_m13_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m13_couplers_AWVALID : STD_LOGIC_VECTOR ( 13 to 13 );
signal xbar_to_m13_couplers_BREADY : STD_LOGIC_VECTOR ( 13 to 13 );
signal xbar_to_m13_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m13_couplers_BVALID : STD_LOGIC;
signal xbar_to_m13_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m13_couplers_RREADY : STD_LOGIC_VECTOR ( 13 to 13 );
signal xbar_to_m13_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m13_couplers_RVALID : STD_LOGIC;
signal xbar_to_m13_couplers_WDATA : STD_LOGIC_VECTOR ( 447 downto 416 );
signal xbar_to_m13_couplers_WREADY : STD_LOGIC;
signal xbar_to_m13_couplers_WSTRB : STD_LOGIC_VECTOR ( 55 downto 52 );
signal xbar_to_m13_couplers_WVALID : STD_LOGIC_VECTOR ( 13 to 13 );
signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 38 downto 0 );
signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 38 downto 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1 <= M00_ARESETN;
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M00_AXI_arvalid(0) <= m00_couplers_to_microblaze_0_axi_periph_ARVALID(0);
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M00_AXI_awvalid(0) <= m00_couplers_to_microblaze_0_axi_periph_AWVALID(0);
M00_AXI_bready(0) <= m00_couplers_to_microblaze_0_axi_periph_BREADY(0);
M00_AXI_rready(0) <= m00_couplers_to_microblaze_0_axi_periph_RREADY(0);
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M00_AXI_wvalid(0) <= m00_couplers_to_microblaze_0_axi_periph_WVALID(0);
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1 <= M01_ARESETN;
M01_AXI_araddr(31 downto 0) <= m01_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M01_AXI_arvalid(0) <= m01_couplers_to_microblaze_0_axi_periph_ARVALID(0);
M01_AXI_awaddr(31 downto 0) <= m01_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M01_AXI_awvalid(0) <= m01_couplers_to_microblaze_0_axi_periph_AWVALID(0);
M01_AXI_bready(0) <= m01_couplers_to_microblaze_0_axi_periph_BREADY(0);
M01_AXI_rready(0) <= m01_couplers_to_microblaze_0_axi_periph_RREADY(0);
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M01_AXI_wvalid(0) <= m01_couplers_to_microblaze_0_axi_periph_WVALID(0);
M02_ACLK_1 <= M02_ACLK;
M02_ARESETN_1 <= M02_ARESETN;
M02_AXI_araddr(31 downto 0) <= m02_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M02_AXI_arvalid(0) <= m02_couplers_to_microblaze_0_axi_periph_ARVALID(0);
M02_AXI_awaddr(31 downto 0) <= m02_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M02_AXI_awvalid(0) <= m02_couplers_to_microblaze_0_axi_periph_AWVALID(0);
M02_AXI_bready(0) <= m02_couplers_to_microblaze_0_axi_periph_BREADY(0);
M02_AXI_rready(0) <= m02_couplers_to_microblaze_0_axi_periph_RREADY(0);
M02_AXI_wdata(31 downto 0) <= m02_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M02_AXI_wstrb(3 downto 0) <= m02_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M02_AXI_wvalid(0) <= m02_couplers_to_microblaze_0_axi_periph_WVALID(0);
M03_ACLK_1 <= M03_ACLK;
M03_ARESETN_1 <= M03_ARESETN;
M03_AXI_araddr(31 downto 0) <= m03_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M03_AXI_arvalid(0) <= m03_couplers_to_microblaze_0_axi_periph_ARVALID(0);
M03_AXI_awaddr(31 downto 0) <= m03_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M03_AXI_awvalid(0) <= m03_couplers_to_microblaze_0_axi_periph_AWVALID(0);
M03_AXI_bready(0) <= m03_couplers_to_microblaze_0_axi_periph_BREADY(0);
M03_AXI_rready(0) <= m03_couplers_to_microblaze_0_axi_periph_RREADY(0);
M03_AXI_wdata(31 downto 0) <= m03_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M03_AXI_wstrb(3 downto 0) <= m03_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M03_AXI_wvalid(0) <= m03_couplers_to_microblaze_0_axi_periph_WVALID(0);
M04_ACLK_1 <= M04_ACLK;
M04_ARESETN_1 <= M04_ARESETN;
M04_AXI_araddr(31 downto 0) <= m04_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M04_AXI_arvalid(0) <= m04_couplers_to_microblaze_0_axi_periph_ARVALID(0);
M04_AXI_awaddr(31 downto 0) <= m04_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M04_AXI_awvalid(0) <= m04_couplers_to_microblaze_0_axi_periph_AWVALID(0);
M04_AXI_bready(0) <= m04_couplers_to_microblaze_0_axi_periph_BREADY(0);
M04_AXI_rready(0) <= m04_couplers_to_microblaze_0_axi_periph_RREADY(0);
M04_AXI_wdata(31 downto 0) <= m04_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M04_AXI_wstrb(3 downto 0) <= m04_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M04_AXI_wvalid(0) <= m04_couplers_to_microblaze_0_axi_periph_WVALID(0);
M05_ACLK_1 <= M05_ACLK;
M05_ARESETN_1 <= M05_ARESETN;
M05_AXI_araddr(31 downto 0) <= m05_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M05_AXI_arvalid(0) <= m05_couplers_to_microblaze_0_axi_periph_ARVALID(0);
M05_AXI_awaddr(31 downto 0) <= m05_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M05_AXI_awvalid(0) <= m05_couplers_to_microblaze_0_axi_periph_AWVALID(0);
M05_AXI_bready(0) <= m05_couplers_to_microblaze_0_axi_periph_BREADY(0);
M05_AXI_rready(0) <= m05_couplers_to_microblaze_0_axi_periph_RREADY(0);
M05_AXI_wdata(31 downto 0) <= m05_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M05_AXI_wstrb(3 downto 0) <= m05_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M05_AXI_wvalid(0) <= m05_couplers_to_microblaze_0_axi_periph_WVALID(0);
M06_ACLK_1 <= M06_ACLK;
M06_ARESETN_1 <= M06_ARESETN;
M06_AXI_araddr(31 downto 0) <= m06_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M06_AXI_arvalid(0) <= m06_couplers_to_microblaze_0_axi_periph_ARVALID(0);
M06_AXI_awaddr(31 downto 0) <= m06_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M06_AXI_awvalid(0) <= m06_couplers_to_microblaze_0_axi_periph_AWVALID(0);
M06_AXI_bready(0) <= m06_couplers_to_microblaze_0_axi_periph_BREADY(0);
M06_AXI_rready(0) <= m06_couplers_to_microblaze_0_axi_periph_RREADY(0);
M06_AXI_wdata(31 downto 0) <= m06_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M06_AXI_wstrb(3 downto 0) <= m06_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M06_AXI_wvalid(0) <= m06_couplers_to_microblaze_0_axi_periph_WVALID(0);
M07_ACLK_1 <= M07_ACLK;
M07_ARESETN_1 <= M07_ARESETN;
M07_AXI_araddr(31 downto 0) <= m07_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M07_AXI_arvalid(0) <= m07_couplers_to_microblaze_0_axi_periph_ARVALID(0);
M07_AXI_awaddr(31 downto 0) <= m07_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M07_AXI_awvalid(0) <= m07_couplers_to_microblaze_0_axi_periph_AWVALID(0);
M07_AXI_bready(0) <= m07_couplers_to_microblaze_0_axi_periph_BREADY(0);
M07_AXI_rready(0) <= m07_couplers_to_microblaze_0_axi_periph_RREADY(0);
M07_AXI_wdata(31 downto 0) <= m07_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M07_AXI_wstrb(3 downto 0) <= m07_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M07_AXI_wvalid(0) <= m07_couplers_to_microblaze_0_axi_periph_WVALID(0);
M08_ACLK_1 <= M08_ACLK;
M08_ARESETN_1 <= M08_ARESETN;
M08_AXI_araddr(31 downto 0) <= m08_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M08_AXI_arvalid(0) <= m08_couplers_to_microblaze_0_axi_periph_ARVALID(0);
M08_AXI_awaddr(31 downto 0) <= m08_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M08_AXI_awvalid(0) <= m08_couplers_to_microblaze_0_axi_periph_AWVALID(0);
M08_AXI_bready(0) <= m08_couplers_to_microblaze_0_axi_periph_BREADY(0);
M08_AXI_rready(0) <= m08_couplers_to_microblaze_0_axi_periph_RREADY(0);
M08_AXI_wdata(31 downto 0) <= m08_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M08_AXI_wstrb(3 downto 0) <= m08_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M08_AXI_wvalid(0) <= m08_couplers_to_microblaze_0_axi_periph_WVALID(0);
M09_ACLK_1 <= M09_ACLK;
M09_ARESETN_1 <= M09_ARESETN;
M09_AXI_araddr(31 downto 0) <= m09_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M09_AXI_arvalid(0) <= m09_couplers_to_microblaze_0_axi_periph_ARVALID(0);
M09_AXI_awaddr(31 downto 0) <= m09_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M09_AXI_awvalid(0) <= m09_couplers_to_microblaze_0_axi_periph_AWVALID(0);
M09_AXI_bready(0) <= m09_couplers_to_microblaze_0_axi_periph_BREADY(0);
M09_AXI_rready(0) <= m09_couplers_to_microblaze_0_axi_periph_RREADY(0);
M09_AXI_wdata(31 downto 0) <= m09_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M09_AXI_wstrb(3 downto 0) <= m09_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M09_AXI_wvalid(0) <= m09_couplers_to_microblaze_0_axi_periph_WVALID(0);
M10_ACLK_1 <= M10_ACLK;
M10_ARESETN_1 <= M10_ARESETN;
M10_AXI_araddr <= m10_couplers_to_microblaze_0_axi_periph_ARADDR;
M10_AXI_arprot <= m10_couplers_to_microblaze_0_axi_periph_ARPROT;
M10_AXI_arvalid <= m10_couplers_to_microblaze_0_axi_periph_ARVALID;
M10_AXI_awaddr <= m10_couplers_to_microblaze_0_axi_periph_AWADDR;
M10_AXI_awprot <= m10_couplers_to_microblaze_0_axi_periph_AWPROT;
M10_AXI_awvalid <= m10_couplers_to_microblaze_0_axi_periph_AWVALID;
M10_AXI_bready <= m10_couplers_to_microblaze_0_axi_periph_BREADY;
M10_AXI_rready <= m10_couplers_to_microblaze_0_axi_periph_RREADY;
M10_AXI_wdata <= m10_couplers_to_microblaze_0_axi_periph_WDATA;
M10_AXI_wstrb <= m10_couplers_to_microblaze_0_axi_periph_WSTRB;
M10_AXI_wvalid <= m10_couplers_to_microblaze_0_axi_periph_WVALID;
M11_ACLK_1 <= M11_ACLK;
M11_ARESETN_1 <= M11_ARESETN;
M11_AXI_araddr(31 downto 0) <= m11_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M11_AXI_arvalid(0) <= m11_couplers_to_microblaze_0_axi_periph_ARVALID(0);
M11_AXI_awaddr(31 downto 0) <= m11_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M11_AXI_awvalid(0) <= m11_couplers_to_microblaze_0_axi_periph_AWVALID(0);
M11_AXI_bready(0) <= m11_couplers_to_microblaze_0_axi_periph_BREADY(0);
M11_AXI_rready(0) <= m11_couplers_to_microblaze_0_axi_periph_RREADY(0);
M11_AXI_wdata(31 downto 0) <= m11_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M11_AXI_wstrb(3 downto 0) <= m11_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M11_AXI_wvalid(0) <= m11_couplers_to_microblaze_0_axi_periph_WVALID(0);
M12_ACLK_1 <= M12_ACLK;
M12_ARESETN_1 <= M12_ARESETN;
M12_AXI_araddr(31 downto 0) <= m12_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M12_AXI_arvalid(0) <= m12_couplers_to_microblaze_0_axi_periph_ARVALID(0);
M12_AXI_awaddr(31 downto 0) <= m12_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M12_AXI_awvalid(0) <= m12_couplers_to_microblaze_0_axi_periph_AWVALID(0);
M12_AXI_bready(0) <= m12_couplers_to_microblaze_0_axi_periph_BREADY(0);
M12_AXI_rready(0) <= m12_couplers_to_microblaze_0_axi_periph_RREADY(0);
M12_AXI_wdata(31 downto 0) <= m12_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M12_AXI_wstrb(3 downto 0) <= m12_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M12_AXI_wvalid(0) <= m12_couplers_to_microblaze_0_axi_periph_WVALID(0);
M13_ACLK_1 <= M13_ACLK;
M13_ARESETN_1 <= M13_ARESETN;
M13_AXI_araddr(10 downto 0) <= m13_couplers_to_microblaze_0_axi_periph_ARADDR(10 downto 0);
M13_AXI_arvalid <= m13_couplers_to_microblaze_0_axi_periph_ARVALID;
M13_AXI_awaddr(10 downto 0) <= m13_couplers_to_microblaze_0_axi_periph_AWADDR(10 downto 0);
M13_AXI_awvalid <= m13_couplers_to_microblaze_0_axi_periph_AWVALID;
M13_AXI_bready <= m13_couplers_to_microblaze_0_axi_periph_BREADY;
M13_AXI_rready <= m13_couplers_to_microblaze_0_axi_periph_RREADY;
M13_AXI_wdata(31 downto 0) <= m13_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M13_AXI_wstrb(3 downto 0) <= m13_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M13_AXI_wvalid <= m13_couplers_to_microblaze_0_axi_periph_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1 <= S00_ARESETN;
S00_AXI_arready(0) <= microblaze_0_axi_periph_to_s00_couplers_ARREADY(0);
S00_AXI_awready(0) <= microblaze_0_axi_periph_to_s00_couplers_AWREADY(0);
S00_AXI_bresp(1 downto 0) <= microblaze_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid(0) <= microblaze_0_axi_periph_to_s00_couplers_BVALID(0);
S00_AXI_rdata(31 downto 0) <= microblaze_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rresp(1 downto 0) <= microblaze_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid(0) <= microblaze_0_axi_periph_to_s00_couplers_RVALID(0);
S00_AXI_wready(0) <= microblaze_0_axi_periph_to_s00_couplers_WREADY(0);
m00_couplers_to_microblaze_0_axi_periph_ARREADY(0) <= M00_AXI_arready(0);
m00_couplers_to_microblaze_0_axi_periph_AWREADY(0) <= M00_AXI_awready(0);
m00_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_microblaze_0_axi_periph_BVALID(0) <= M00_AXI_bvalid(0);
m00_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_microblaze_0_axi_periph_RVALID(0) <= M00_AXI_rvalid(0);
m00_couplers_to_microblaze_0_axi_periph_WREADY(0) <= M00_AXI_wready(0);
m01_couplers_to_microblaze_0_axi_periph_ARREADY(0) <= M01_AXI_arready(0);
m01_couplers_to_microblaze_0_axi_periph_AWREADY(0) <= M01_AXI_awready(0);
m01_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_microblaze_0_axi_periph_BVALID(0) <= M01_AXI_bvalid(0);
m01_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_microblaze_0_axi_periph_RVALID(0) <= M01_AXI_rvalid(0);
m01_couplers_to_microblaze_0_axi_periph_WREADY(0) <= M01_AXI_wready(0);
m02_couplers_to_microblaze_0_axi_periph_ARREADY(0) <= M02_AXI_arready(0);
m02_couplers_to_microblaze_0_axi_periph_AWREADY(0) <= M02_AXI_awready(0);
m02_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0);
m02_couplers_to_microblaze_0_axi_periph_BVALID(0) <= M02_AXI_bvalid(0);
m02_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0);
m02_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0);
m02_couplers_to_microblaze_0_axi_periph_RVALID(0) <= M02_AXI_rvalid(0);
m02_couplers_to_microblaze_0_axi_periph_WREADY(0) <= M02_AXI_wready(0);
m03_couplers_to_microblaze_0_axi_periph_ARREADY(0) <= M03_AXI_arready(0);
m03_couplers_to_microblaze_0_axi_periph_AWREADY(0) <= M03_AXI_awready(0);
m03_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M03_AXI_bresp(1 downto 0);
m03_couplers_to_microblaze_0_axi_periph_BVALID(0) <= M03_AXI_bvalid(0);
m03_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M03_AXI_rdata(31 downto 0);
m03_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M03_AXI_rresp(1 downto 0);
m03_couplers_to_microblaze_0_axi_periph_RVALID(0) <= M03_AXI_rvalid(0);
m03_couplers_to_microblaze_0_axi_periph_WREADY(0) <= M03_AXI_wready(0);
m04_couplers_to_microblaze_0_axi_periph_ARREADY(0) <= M04_AXI_arready(0);
m04_couplers_to_microblaze_0_axi_periph_AWREADY(0) <= M04_AXI_awready(0);
m04_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M04_AXI_bresp(1 downto 0);
m04_couplers_to_microblaze_0_axi_periph_BVALID(0) <= M04_AXI_bvalid(0);
m04_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M04_AXI_rdata(31 downto 0);
m04_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M04_AXI_rresp(1 downto 0);
m04_couplers_to_microblaze_0_axi_periph_RVALID(0) <= M04_AXI_rvalid(0);
m04_couplers_to_microblaze_0_axi_periph_WREADY(0) <= M04_AXI_wready(0);
m05_couplers_to_microblaze_0_axi_periph_ARREADY(0) <= M05_AXI_arready(0);
m05_couplers_to_microblaze_0_axi_periph_AWREADY(0) <= M05_AXI_awready(0);
m05_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M05_AXI_bresp(1 downto 0);
m05_couplers_to_microblaze_0_axi_periph_BVALID(0) <= M05_AXI_bvalid(0);
m05_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M05_AXI_rdata(31 downto 0);
m05_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M05_AXI_rresp(1 downto 0);
m05_couplers_to_microblaze_0_axi_periph_RVALID(0) <= M05_AXI_rvalid(0);
m05_couplers_to_microblaze_0_axi_periph_WREADY(0) <= M05_AXI_wready(0);
m06_couplers_to_microblaze_0_axi_periph_ARREADY(0) <= M06_AXI_arready(0);
m06_couplers_to_microblaze_0_axi_periph_AWREADY(0) <= M06_AXI_awready(0);
m06_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M06_AXI_bresp(1 downto 0);
m06_couplers_to_microblaze_0_axi_periph_BVALID(0) <= M06_AXI_bvalid(0);
m06_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M06_AXI_rdata(31 downto 0);
m06_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M06_AXI_rresp(1 downto 0);
m06_couplers_to_microblaze_0_axi_periph_RVALID(0) <= M06_AXI_rvalid(0);
m06_couplers_to_microblaze_0_axi_periph_WREADY(0) <= M06_AXI_wready(0);
m07_couplers_to_microblaze_0_axi_periph_ARREADY(0) <= M07_AXI_arready(0);
m07_couplers_to_microblaze_0_axi_periph_AWREADY(0) <= M07_AXI_awready(0);
m07_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M07_AXI_bresp(1 downto 0);
m07_couplers_to_microblaze_0_axi_periph_BVALID(0) <= M07_AXI_bvalid(0);
m07_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M07_AXI_rdata(31 downto 0);
m07_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M07_AXI_rresp(1 downto 0);
m07_couplers_to_microblaze_0_axi_periph_RVALID(0) <= M07_AXI_rvalid(0);
m07_couplers_to_microblaze_0_axi_periph_WREADY(0) <= M07_AXI_wready(0);
m08_couplers_to_microblaze_0_axi_periph_ARREADY(0) <= M08_AXI_arready(0);
m08_couplers_to_microblaze_0_axi_periph_AWREADY(0) <= M08_AXI_awready(0);
m08_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M08_AXI_bresp(1 downto 0);
m08_couplers_to_microblaze_0_axi_periph_BVALID(0) <= M08_AXI_bvalid(0);
m08_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M08_AXI_rdata(31 downto 0);
m08_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M08_AXI_rresp(1 downto 0);
m08_couplers_to_microblaze_0_axi_periph_RVALID(0) <= M08_AXI_rvalid(0);
m08_couplers_to_microblaze_0_axi_periph_WREADY(0) <= M08_AXI_wready(0);
m09_couplers_to_microblaze_0_axi_periph_ARREADY(0) <= M09_AXI_arready(0);
m09_couplers_to_microblaze_0_axi_periph_AWREADY(0) <= M09_AXI_awready(0);
m09_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M09_AXI_bresp(1 downto 0);
m09_couplers_to_microblaze_0_axi_periph_BVALID(0) <= M09_AXI_bvalid(0);
m09_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M09_AXI_rdata(31 downto 0);
m09_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M09_AXI_rresp(1 downto 0);
m09_couplers_to_microblaze_0_axi_periph_RVALID(0) <= M09_AXI_rvalid(0);
m09_couplers_to_microblaze_0_axi_periph_WREADY(0) <= M09_AXI_wready(0);
m10_couplers_to_microblaze_0_axi_periph_ARREADY <= M10_AXI_arready;
m10_couplers_to_microblaze_0_axi_periph_AWREADY <= M10_AXI_awready;
m10_couplers_to_microblaze_0_axi_periph_BRESP <= M10_AXI_bresp;
m10_couplers_to_microblaze_0_axi_periph_BVALID <= M10_AXI_bvalid;
m10_couplers_to_microblaze_0_axi_periph_RDATA <= M10_AXI_rdata;
m10_couplers_to_microblaze_0_axi_periph_RRESP <= M10_AXI_rresp;
m10_couplers_to_microblaze_0_axi_periph_RVALID <= M10_AXI_rvalid;
m10_couplers_to_microblaze_0_axi_periph_WREADY <= M10_AXI_wready;
m11_couplers_to_microblaze_0_axi_periph_ARREADY(0) <= M11_AXI_arready(0);
m11_couplers_to_microblaze_0_axi_periph_AWREADY(0) <= M11_AXI_awready(0);
m11_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M11_AXI_bresp(1 downto 0);
m11_couplers_to_microblaze_0_axi_periph_BVALID(0) <= M11_AXI_bvalid(0);
m11_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M11_AXI_rdata(31 downto 0);
m11_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M11_AXI_rresp(1 downto 0);
m11_couplers_to_microblaze_0_axi_periph_RVALID(0) <= M11_AXI_rvalid(0);
m11_couplers_to_microblaze_0_axi_periph_WREADY(0) <= M11_AXI_wready(0);
m12_couplers_to_microblaze_0_axi_periph_ARREADY(0) <= M12_AXI_arready(0);
m12_couplers_to_microblaze_0_axi_periph_AWREADY(0) <= M12_AXI_awready(0);
m12_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M12_AXI_bresp(1 downto 0);
m12_couplers_to_microblaze_0_axi_periph_BVALID(0) <= M12_AXI_bvalid(0);
m12_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M12_AXI_rdata(31 downto 0);
m12_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M12_AXI_rresp(1 downto 0);
m12_couplers_to_microblaze_0_axi_periph_RVALID(0) <= M12_AXI_rvalid(0);
m12_couplers_to_microblaze_0_axi_periph_WREADY(0) <= M12_AXI_wready(0);
m13_couplers_to_microblaze_0_axi_periph_ARREADY <= M13_AXI_arready;
m13_couplers_to_microblaze_0_axi_periph_AWREADY <= M13_AXI_awready;
m13_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M13_AXI_bresp(1 downto 0);
m13_couplers_to_microblaze_0_axi_periph_BVALID <= M13_AXI_bvalid;
m13_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M13_AXI_rdata(31 downto 0);
m13_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M13_AXI_rresp(1 downto 0);
m13_couplers_to_microblaze_0_axi_periph_RVALID <= M13_AXI_rvalid;
m13_couplers_to_microblaze_0_axi_periph_WREADY <= M13_AXI_wready;
microblaze_0_axi_periph_ACLK_net <= ACLK;
microblaze_0_axi_periph_ARESETN_net <= ARESETN;
microblaze_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
microblaze_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
microblaze_0_axi_periph_to_s00_couplers_ARVALID(0) <= S00_AXI_arvalid(0);
microblaze_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
microblaze_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
microblaze_0_axi_periph_to_s00_couplers_AWVALID(0) <= S00_AXI_awvalid(0);
microblaze_0_axi_periph_to_s00_couplers_BREADY(0) <= S00_AXI_bready(0);
microblaze_0_axi_periph_to_s00_couplers_RREADY(0) <= S00_AXI_rready(0);
microblaze_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
microblaze_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
microblaze_0_axi_periph_to_s00_couplers_WVALID(0) <= S00_AXI_wvalid(0);
m00_couplers: entity work.m00_couplers_imp_1RZ0IW6
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN => M00_ARESETN_1,
M_AXI_araddr(31 downto 0) => m00_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m00_couplers_to_microblaze_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m00_couplers_to_microblaze_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m00_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m00_couplers_to_microblaze_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m00_couplers_to_microblaze_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m00_couplers_to_microblaze_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m00_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m00_couplers_to_microblaze_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m00_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m00_couplers_to_microblaze_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m00_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m00_couplers_to_microblaze_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m00_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m00_couplers_to_microblaze_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m00_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m00_couplers_to_microblaze_0_axi_periph_WVALID(0),
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arready(0) => xbar_to_m00_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awready(0) => xbar_to_m00_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready(0) => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready(0) => xbar_to_m00_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_K87I2F
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN => M01_ARESETN_1,
M_AXI_araddr(31 downto 0) => m01_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m01_couplers_to_microblaze_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m01_couplers_to_microblaze_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m01_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m01_couplers_to_microblaze_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m01_couplers_to_microblaze_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m01_couplers_to_microblaze_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m01_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m01_couplers_to_microblaze_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m01_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m01_couplers_to_microblaze_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m01_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m01_couplers_to_microblaze_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m01_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m01_couplers_to_microblaze_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m01_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m01_couplers_to_microblaze_0_axi_periph_WVALID(0),
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32),
S_AXI_arready(0) => xbar_to_m01_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32),
S_AXI_awready(0) => xbar_to_m01_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready(0) => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m01_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m01_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready(0) => xbar_to_m01_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid(0) => xbar_to_m01_couplers_WVALID(1)
);
m02_couplers: entity work.m02_couplers_imp_QYRHL1
port map (
M_ACLK => M02_ACLK_1,
M_ARESETN => M02_ARESETN_1,
M_AXI_araddr(31 downto 0) => m02_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m02_couplers_to_microblaze_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m02_couplers_to_microblaze_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m02_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m02_couplers_to_microblaze_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m02_couplers_to_microblaze_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m02_couplers_to_microblaze_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m02_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m02_couplers_to_microblaze_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m02_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m02_couplers_to_microblaze_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m02_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m02_couplers_to_microblaze_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m02_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m02_couplers_to_microblaze_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m02_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m02_couplers_to_microblaze_0_axi_periph_WVALID(0),
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m02_couplers_ARADDR(95 downto 64),
S_AXI_arready(0) => xbar_to_m02_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m02_couplers_ARVALID(2),
S_AXI_awaddr(31 downto 0) => xbar_to_m02_couplers_AWADDR(95 downto 64),
S_AXI_awready(0) => xbar_to_m02_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m02_couplers_AWVALID(2),
S_AXI_bready(0) => xbar_to_m02_couplers_BREADY(2),
S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m02_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m02_couplers_RREADY(2),
S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m02_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64),
S_AXI_wready(0) => xbar_to_m02_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m02_couplers_WSTRB(11 downto 8),
S_AXI_wvalid(0) => xbar_to_m02_couplers_WVALID(2)
);
m03_couplers: entity work.m03_couplers_imp_1LIFQL0
port map (
M_ACLK => M03_ACLK_1,
M_ARESETN => M03_ARESETN_1,
M_AXI_araddr(31 downto 0) => m03_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m03_couplers_to_microblaze_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m03_couplers_to_microblaze_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m03_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m03_couplers_to_microblaze_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m03_couplers_to_microblaze_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m03_couplers_to_microblaze_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m03_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m03_couplers_to_microblaze_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m03_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m03_couplers_to_microblaze_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m03_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m03_couplers_to_microblaze_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m03_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m03_couplers_to_microblaze_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m03_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m03_couplers_to_microblaze_0_axi_periph_WVALID(0),
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m03_couplers_ARADDR(127 downto 96),
S_AXI_arready(0) => xbar_to_m03_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m03_couplers_ARVALID(3),
S_AXI_awaddr(31 downto 0) => xbar_to_m03_couplers_AWADDR(127 downto 96),
S_AXI_awready(0) => xbar_to_m03_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m03_couplers_AWVALID(3),
S_AXI_bready(0) => xbar_to_m03_couplers_BREADY(3),
S_AXI_bresp(1 downto 0) => xbar_to_m03_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m03_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m03_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m03_couplers_RREADY(3),
S_AXI_rresp(1 downto 0) => xbar_to_m03_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m03_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m03_couplers_WDATA(127 downto 96),
S_AXI_wready(0) => xbar_to_m03_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m03_couplers_WSTRB(15 downto 12),
S_AXI_wvalid(0) => xbar_to_m03_couplers_WVALID(3)
);
m04_couplers: entity work.m04_couplers_imp_E2VWV5
port map (
M_ACLK => M04_ACLK_1,
M_ARESETN => M04_ARESETN_1,
M_AXI_araddr(31 downto 0) => m04_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m04_couplers_to_microblaze_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m04_couplers_to_microblaze_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m04_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m04_couplers_to_microblaze_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m04_couplers_to_microblaze_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m04_couplers_to_microblaze_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m04_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m04_couplers_to_microblaze_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m04_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m04_couplers_to_microblaze_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m04_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m04_couplers_to_microblaze_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m04_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m04_couplers_to_microblaze_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m04_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m04_couplers_to_microblaze_0_axi_periph_WVALID(0),
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m04_couplers_ARADDR(159 downto 128),
S_AXI_arready(0) => xbar_to_m04_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m04_couplers_ARVALID(4),
S_AXI_awaddr(31 downto 0) => xbar_to_m04_couplers_AWADDR(159 downto 128),
S_AXI_awready(0) => xbar_to_m04_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m04_couplers_AWVALID(4),
S_AXI_bready(0) => xbar_to_m04_couplers_BREADY(4),
S_AXI_bresp(1 downto 0) => xbar_to_m04_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m04_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m04_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m04_couplers_RREADY(4),
S_AXI_rresp(1 downto 0) => xbar_to_m04_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m04_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m04_couplers_WDATA(159 downto 128),
S_AXI_wready(0) => xbar_to_m04_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m04_couplers_WSTRB(19 downto 16),
S_AXI_wvalid(0) => xbar_to_m04_couplers_WVALID(4)
);
m05_couplers: entity work.m05_couplers_imp_17ILSXC
port map (
M_ACLK => M05_ACLK_1,
M_ARESETN => M05_ARESETN_1,
M_AXI_araddr(31 downto 0) => m05_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m05_couplers_to_microblaze_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m05_couplers_to_microblaze_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m05_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m05_couplers_to_microblaze_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m05_couplers_to_microblaze_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m05_couplers_to_microblaze_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m05_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m05_couplers_to_microblaze_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m05_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m05_couplers_to_microblaze_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m05_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m05_couplers_to_microblaze_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m05_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m05_couplers_to_microblaze_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m05_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m05_couplers_to_microblaze_0_axi_periph_WVALID(0),
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m05_couplers_ARADDR(191 downto 160),
S_AXI_arready(0) => xbar_to_m05_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m05_couplers_ARVALID(5),
S_AXI_awaddr(31 downto 0) => xbar_to_m05_couplers_AWADDR(191 downto 160),
S_AXI_awready(0) => xbar_to_m05_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m05_couplers_AWVALID(5),
S_AXI_bready(0) => xbar_to_m05_couplers_BREADY(5),
S_AXI_bresp(1 downto 0) => xbar_to_m05_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m05_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m05_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m05_couplers_RREADY(5),
S_AXI_rresp(1 downto 0) => xbar_to_m05_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m05_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m05_couplers_WDATA(191 downto 160),
S_AXI_wready(0) => xbar_to_m05_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m05_couplers_WSTRB(23 downto 20),
S_AXI_wvalid(0) => xbar_to_m05_couplers_WVALID(5)
);
m06_couplers: entity work.m06_couplers_imp_1E95TTU
port map (
M_ACLK => M06_ACLK_1,
M_ARESETN => M06_ARESETN_1,
M_AXI_araddr(31 downto 0) => m06_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m06_couplers_to_microblaze_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m06_couplers_to_microblaze_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m06_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m06_couplers_to_microblaze_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m06_couplers_to_microblaze_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m06_couplers_to_microblaze_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m06_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m06_couplers_to_microblaze_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m06_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m06_couplers_to_microblaze_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m06_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m06_couplers_to_microblaze_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m06_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m06_couplers_to_microblaze_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m06_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m06_couplers_to_microblaze_0_axi_periph_WVALID(0),
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m06_couplers_ARADDR(223 downto 192),
S_AXI_arready(0) => xbar_to_m06_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m06_couplers_ARVALID(6),
S_AXI_awaddr(31 downto 0) => xbar_to_m06_couplers_AWADDR(223 downto 192),
S_AXI_awready(0) => xbar_to_m06_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m06_couplers_AWVALID(6),
S_AXI_bready(0) => xbar_to_m06_couplers_BREADY(6),
S_AXI_bresp(1 downto 0) => xbar_to_m06_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m06_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m06_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m06_couplers_RREADY(6),
S_AXI_rresp(1 downto 0) => xbar_to_m06_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m06_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m06_couplers_WDATA(223 downto 192),
S_AXI_wready(0) => xbar_to_m06_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m06_couplers_WSTRB(27 downto 24),
S_AXI_wvalid(0) => xbar_to_m06_couplers_WVALID(6)
);
m07_couplers: entity work.m07_couplers_imp_7MB6C3
port map (
M_ACLK => M07_ACLK_1,
M_ARESETN => M07_ARESETN_1,
M_AXI_araddr(31 downto 0) => m07_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m07_couplers_to_microblaze_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m07_couplers_to_microblaze_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m07_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m07_couplers_to_microblaze_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m07_couplers_to_microblaze_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m07_couplers_to_microblaze_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m07_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m07_couplers_to_microblaze_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m07_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m07_couplers_to_microblaze_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m07_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m07_couplers_to_microblaze_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m07_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m07_couplers_to_microblaze_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m07_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m07_couplers_to_microblaze_0_axi_periph_WVALID(0),
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m07_couplers_ARADDR(255 downto 224),
S_AXI_arready(0) => xbar_to_m07_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m07_couplers_ARVALID(7),
S_AXI_awaddr(31 downto 0) => xbar_to_m07_couplers_AWADDR(255 downto 224),
S_AXI_awready(0) => xbar_to_m07_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m07_couplers_AWVALID(7),
S_AXI_bready(0) => xbar_to_m07_couplers_BREADY(7),
S_AXI_bresp(1 downto 0) => xbar_to_m07_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m07_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m07_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m07_couplers_RREADY(7),
S_AXI_rresp(1 downto 0) => xbar_to_m07_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m07_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m07_couplers_WDATA(255 downto 224),
S_AXI_wready(0) => xbar_to_m07_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m07_couplers_WSTRB(31 downto 28),
S_AXI_wvalid(0) => xbar_to_m07_couplers_WVALID(7)
);
m08_couplers: entity work.m08_couplers_imp_15IETBD
port map (
M_ACLK => M08_ACLK_1,
M_ARESETN => M08_ARESETN_1,
M_AXI_araddr(31 downto 0) => m08_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m08_couplers_to_microblaze_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m08_couplers_to_microblaze_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m08_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m08_couplers_to_microblaze_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m08_couplers_to_microblaze_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m08_couplers_to_microblaze_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m08_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m08_couplers_to_microblaze_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m08_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m08_couplers_to_microblaze_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m08_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m08_couplers_to_microblaze_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m08_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m08_couplers_to_microblaze_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m08_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m08_couplers_to_microblaze_0_axi_periph_WVALID(0),
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m08_couplers_ARADDR(287 downto 256),
S_AXI_arready(0) => xbar_to_m08_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m08_couplers_ARVALID(8),
S_AXI_awaddr(31 downto 0) => xbar_to_m08_couplers_AWADDR(287 downto 256),
S_AXI_awready(0) => xbar_to_m08_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m08_couplers_AWVALID(8),
S_AXI_bready(0) => xbar_to_m08_couplers_BREADY(8),
S_AXI_bresp(1 downto 0) => xbar_to_m08_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m08_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m08_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m08_couplers_RREADY(8),
S_AXI_rresp(1 downto 0) => xbar_to_m08_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m08_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m08_couplers_WDATA(287 downto 256),
S_AXI_wready(0) => xbar_to_m08_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m08_couplers_WSTRB(35 downto 32),
S_AXI_wvalid(0) => xbar_to_m08_couplers_WVALID(8)
);
m09_couplers: entity work.m09_couplers_imp_GMVR08
port map (
M_ACLK => M09_ACLK_1,
M_ARESETN => M09_ARESETN_1,
M_AXI_araddr(31 downto 0) => m09_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m09_couplers_to_microblaze_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m09_couplers_to_microblaze_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m09_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m09_couplers_to_microblaze_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m09_couplers_to_microblaze_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m09_couplers_to_microblaze_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m09_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m09_couplers_to_microblaze_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m09_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m09_couplers_to_microblaze_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m09_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m09_couplers_to_microblaze_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m09_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m09_couplers_to_microblaze_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m09_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m09_couplers_to_microblaze_0_axi_periph_WVALID(0),
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m09_couplers_ARADDR(319 downto 288),
S_AXI_arready(0) => xbar_to_m09_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m09_couplers_ARVALID(9),
S_AXI_awaddr(31 downto 0) => xbar_to_m09_couplers_AWADDR(319 downto 288),
S_AXI_awready(0) => xbar_to_m09_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m09_couplers_AWVALID(9),
S_AXI_bready(0) => xbar_to_m09_couplers_BREADY(9),
S_AXI_bresp(1 downto 0) => xbar_to_m09_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m09_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m09_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m09_couplers_RREADY(9),
S_AXI_rresp(1 downto 0) => xbar_to_m09_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m09_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m09_couplers_WDATA(319 downto 288),
S_AXI_wready(0) => xbar_to_m09_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m09_couplers_WSTRB(39 downto 36),
S_AXI_wvalid(0) => xbar_to_m09_couplers_WVALID(9)
);
m10_couplers: entity work.m10_couplers_imp_QYIUP1
port map (
M_ACLK => M10_ACLK_1,
M_ARESETN => M10_ARESETN_1,
M_AXI_araddr => m10_couplers_to_microblaze_0_axi_periph_ARADDR,
M_AXI_arprot => m10_couplers_to_microblaze_0_axi_periph_ARPROT,
M_AXI_arready => m10_couplers_to_microblaze_0_axi_periph_ARREADY,
M_AXI_arvalid => m10_couplers_to_microblaze_0_axi_periph_ARVALID,
M_AXI_awaddr => m10_couplers_to_microblaze_0_axi_periph_AWADDR,
M_AXI_awprot => m10_couplers_to_microblaze_0_axi_periph_AWPROT,
M_AXI_awready => m10_couplers_to_microblaze_0_axi_periph_AWREADY,
M_AXI_awvalid => m10_couplers_to_microblaze_0_axi_periph_AWVALID,
M_AXI_bready => m10_couplers_to_microblaze_0_axi_periph_BREADY,
M_AXI_bresp => m10_couplers_to_microblaze_0_axi_periph_BRESP,
M_AXI_bvalid => m10_couplers_to_microblaze_0_axi_periph_BVALID,
M_AXI_rdata => m10_couplers_to_microblaze_0_axi_periph_RDATA,
M_AXI_rready => m10_couplers_to_microblaze_0_axi_periph_RREADY,
M_AXI_rresp => m10_couplers_to_microblaze_0_axi_periph_RRESP,
M_AXI_rvalid => m10_couplers_to_microblaze_0_axi_periph_RVALID,
M_AXI_wdata => m10_couplers_to_microblaze_0_axi_periph_WDATA,
M_AXI_wready => m10_couplers_to_microblaze_0_axi_periph_WREADY,
M_AXI_wstrb => m10_couplers_to_microblaze_0_axi_periph_WSTRB,
M_AXI_wvalid => m10_couplers_to_microblaze_0_axi_periph_WVALID,
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr => xbar_to_m10_couplers_ARADDR(320),
S_AXI_arprot => xbar_to_m10_couplers_ARPROT(30),
S_AXI_arready => xbar_to_m10_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m10_couplers_ARVALID(10),
S_AXI_awaddr => xbar_to_m10_couplers_AWADDR(320),
S_AXI_awprot => xbar_to_m10_couplers_AWPROT(30),
S_AXI_awready => xbar_to_m10_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m10_couplers_AWVALID(10),
S_AXI_bready => xbar_to_m10_couplers_BREADY(10),
S_AXI_bresp => xbar_to_m10_couplers_BRESP,
S_AXI_bvalid => xbar_to_m10_couplers_BVALID,
S_AXI_rdata => xbar_to_m10_couplers_RDATA,
S_AXI_rready => xbar_to_m10_couplers_RREADY(10),
S_AXI_rresp => xbar_to_m10_couplers_RRESP,
S_AXI_rvalid => xbar_to_m10_couplers_RVALID,
S_AXI_wdata => xbar_to_m10_couplers_WDATA(320),
S_AXI_wready => xbar_to_m10_couplers_WREADY,
S_AXI_wstrb => xbar_to_m10_couplers_WSTRB(40),
S_AXI_wvalid => xbar_to_m10_couplers_WVALID(10)
);
m11_couplers: entity work.m11_couplers_imp_1LI8I9G
port map (
M_ACLK => M11_ACLK_1,
M_ARESETN => M11_ARESETN_1,
M_AXI_araddr(31 downto 0) => m11_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m11_couplers_to_microblaze_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m11_couplers_to_microblaze_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m11_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m11_couplers_to_microblaze_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m11_couplers_to_microblaze_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m11_couplers_to_microblaze_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m11_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m11_couplers_to_microblaze_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m11_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m11_couplers_to_microblaze_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m11_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m11_couplers_to_microblaze_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m11_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m11_couplers_to_microblaze_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m11_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m11_couplers_to_microblaze_0_axi_periph_WVALID(0),
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m11_couplers_ARADDR(383 downto 352),
S_AXI_arready(0) => xbar_to_m11_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m11_couplers_ARVALID(11),
S_AXI_awaddr(31 downto 0) => xbar_to_m11_couplers_AWADDR(383 downto 352),
S_AXI_awready(0) => xbar_to_m11_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m11_couplers_AWVALID(11),
S_AXI_bready(0) => xbar_to_m11_couplers_BREADY(11),
S_AXI_bresp(1 downto 0) => xbar_to_m11_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m11_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m11_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m11_couplers_RREADY(11),
S_AXI_rresp(1 downto 0) => xbar_to_m11_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m11_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m11_couplers_WDATA(383 downto 352),
S_AXI_wready(0) => xbar_to_m11_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m11_couplers_WSTRB(47 downto 44),
S_AXI_wvalid(0) => xbar_to_m11_couplers_WVALID(11)
);
m12_couplers: entity work.m12_couplers_imp_1RYRHQE
port map (
M_ACLK => M12_ACLK_1,
M_ARESETN => M12_ARESETN_1,
M_AXI_araddr(31 downto 0) => m12_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m12_couplers_to_microblaze_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m12_couplers_to_microblaze_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m12_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m12_couplers_to_microblaze_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m12_couplers_to_microblaze_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m12_couplers_to_microblaze_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m12_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m12_couplers_to_microblaze_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m12_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m12_couplers_to_microblaze_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m12_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m12_couplers_to_microblaze_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m12_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m12_couplers_to_microblaze_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m12_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m12_couplers_to_microblaze_0_axi_periph_WVALID(0),
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m12_couplers_ARADDR(415 downto 384),
S_AXI_arready(0) => xbar_to_m12_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m12_couplers_ARVALID(12),
S_AXI_awaddr(31 downto 0) => xbar_to_m12_couplers_AWADDR(415 downto 384),
S_AXI_awready(0) => xbar_to_m12_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m12_couplers_AWVALID(12),
S_AXI_bready(0) => xbar_to_m12_couplers_BREADY(12),
S_AXI_bresp(1 downto 0) => xbar_to_m12_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m12_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m12_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m12_couplers_RREADY(12),
S_AXI_rresp(1 downto 0) => xbar_to_m12_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m12_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m12_couplers_WDATA(415 downto 384),
S_AXI_wready(0) => xbar_to_m12_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m12_couplers_WSTRB(51 downto 48),
S_AXI_wvalid(0) => xbar_to_m12_couplers_WVALID(12)
);
m13_couplers: entity work.m13_couplers_imp_K7ZVH3
port map (
M_ACLK => M13_ACLK_1,
M_ARESETN => M13_ARESETN_1,
M_AXI_araddr(10 downto 0) => m13_couplers_to_microblaze_0_axi_periph_ARADDR(10 downto 0),
M_AXI_arready => m13_couplers_to_microblaze_0_axi_periph_ARREADY,
M_AXI_arvalid => m13_couplers_to_microblaze_0_axi_periph_ARVALID,
M_AXI_awaddr(10 downto 0) => m13_couplers_to_microblaze_0_axi_periph_AWADDR(10 downto 0),
M_AXI_awready => m13_couplers_to_microblaze_0_axi_periph_AWREADY,
M_AXI_awvalid => m13_couplers_to_microblaze_0_axi_periph_AWVALID,
M_AXI_bready => m13_couplers_to_microblaze_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m13_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m13_couplers_to_microblaze_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m13_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m13_couplers_to_microblaze_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m13_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m13_couplers_to_microblaze_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m13_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m13_couplers_to_microblaze_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m13_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m13_couplers_to_microblaze_0_axi_periph_WVALID,
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m13_couplers_ARADDR(447 downto 416),
S_AXI_arprot(2 downto 0) => xbar_to_m13_couplers_ARPROT(41 downto 39),
S_AXI_arready => xbar_to_m13_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m13_couplers_ARVALID(13),
S_AXI_awaddr(31 downto 0) => xbar_to_m13_couplers_AWADDR(447 downto 416),
S_AXI_awprot(2 downto 0) => xbar_to_m13_couplers_AWPROT(41 downto 39),
S_AXI_awready => xbar_to_m13_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m13_couplers_AWVALID(13),
S_AXI_bready => xbar_to_m13_couplers_BREADY(13),
S_AXI_bresp(1 downto 0) => xbar_to_m13_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m13_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m13_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m13_couplers_RREADY(13),
S_AXI_rresp(1 downto 0) => xbar_to_m13_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m13_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m13_couplers_WDATA(447 downto 416),
S_AXI_wready => xbar_to_m13_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m13_couplers_WSTRB(55 downto 52),
S_AXI_wvalid => xbar_to_m13_couplers_WVALID(13)
);
s00_couplers: entity work.s00_couplers_imp_1LZPV07
port map (
M_ACLK => microblaze_0_axi_periph_ACLK_net,
M_ARESETN => microblaze_0_axi_periph_ARESETN_net,
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready(0) => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready(0) => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid(0) => s00_couplers_to_xbar_AWVALID(0),
M_AXI_bready(0) => s00_couplers_to_xbar_BREADY(0),
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready(0) => s00_couplers_to_xbar_RREADY(0),
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready(0) => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid(0) => s00_couplers_to_xbar_WVALID(0),
S_ACLK => S00_ACLK_1,
S_ARESETN => S00_ARESETN_1,
S_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arprot(2 downto 0) => microblaze_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arready(0) => microblaze_0_axi_periph_to_s00_couplers_ARREADY(0),
S_AXI_arvalid(0) => microblaze_0_axi_periph_to_s00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awprot(2 downto 0) => microblaze_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awready(0) => microblaze_0_axi_periph_to_s00_couplers_AWREADY(0),
S_AXI_awvalid(0) => microblaze_0_axi_periph_to_s00_couplers_AWVALID(0),
S_AXI_bready(0) => microblaze_0_axi_periph_to_s00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => microblaze_0_axi_periph_to_s00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => microblaze_0_axi_periph_to_s00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => microblaze_0_axi_periph_to_s00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wready(0) => microblaze_0_axi_periph_to_s00_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => microblaze_0_axi_periph_to_s00_couplers_WVALID(0)
);
xbar: component system_xbar_1
port map (
aclk => microblaze_0_axi_periph_ACLK_net,
aresetn => microblaze_0_axi_periph_ARESETN_net,
m_axi_araddr(447 downto 416) => xbar_to_m13_couplers_ARADDR(447 downto 416),
m_axi_araddr(415 downto 384) => xbar_to_m12_couplers_ARADDR(415 downto 384),
m_axi_araddr(383 downto 352) => xbar_to_m11_couplers_ARADDR(383 downto 352),
m_axi_araddr(351 downto 320) => xbar_to_m10_couplers_ARADDR(351 downto 320),
m_axi_araddr(319 downto 288) => xbar_to_m09_couplers_ARADDR(319 downto 288),
m_axi_araddr(287 downto 256) => xbar_to_m08_couplers_ARADDR(287 downto 256),
m_axi_araddr(255 downto 224) => xbar_to_m07_couplers_ARADDR(255 downto 224),
m_axi_araddr(223 downto 192) => xbar_to_m06_couplers_ARADDR(223 downto 192),
m_axi_araddr(191 downto 160) => xbar_to_m05_couplers_ARADDR(191 downto 160),
m_axi_araddr(159 downto 128) => xbar_to_m04_couplers_ARADDR(159 downto 128),
m_axi_araddr(127 downto 96) => xbar_to_m03_couplers_ARADDR(127 downto 96),
m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(41 downto 39) => xbar_to_m13_couplers_ARPROT(41 downto 39),
m_axi_arprot(38 downto 33) => NLW_xbar_m_axi_arprot_UNCONNECTED(38 downto 33),
m_axi_arprot(32 downto 30) => xbar_to_m10_couplers_ARPROT(32 downto 30),
m_axi_arprot(29 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(29 downto 0),
m_axi_arready(13) => xbar_to_m13_couplers_ARREADY,
m_axi_arready(12) => xbar_to_m12_couplers_ARREADY(0),
m_axi_arready(11) => xbar_to_m11_couplers_ARREADY(0),
m_axi_arready(10) => xbar_to_m10_couplers_ARREADY,
m_axi_arready(9) => xbar_to_m09_couplers_ARREADY(0),
m_axi_arready(8) => xbar_to_m08_couplers_ARREADY(0),
m_axi_arready(7) => xbar_to_m07_couplers_ARREADY(0),
m_axi_arready(6) => xbar_to_m06_couplers_ARREADY(0),
m_axi_arready(5) => xbar_to_m05_couplers_ARREADY(0),
m_axi_arready(4) => xbar_to_m04_couplers_ARREADY(0),
m_axi_arready(3) => xbar_to_m03_couplers_ARREADY(0),
m_axi_arready(2) => xbar_to_m02_couplers_ARREADY(0),
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY(0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY(0),
m_axi_arvalid(13) => xbar_to_m13_couplers_ARVALID(13),
m_axi_arvalid(12) => xbar_to_m12_couplers_ARVALID(12),
m_axi_arvalid(11) => xbar_to_m11_couplers_ARVALID(11),
m_axi_arvalid(10) => xbar_to_m10_couplers_ARVALID(10),
m_axi_arvalid(9) => xbar_to_m09_couplers_ARVALID(9),
m_axi_arvalid(8) => xbar_to_m08_couplers_ARVALID(8),
m_axi_arvalid(7) => xbar_to_m07_couplers_ARVALID(7),
m_axi_arvalid(6) => xbar_to_m06_couplers_ARVALID(6),
m_axi_arvalid(5) => xbar_to_m05_couplers_ARVALID(5),
m_axi_arvalid(4) => xbar_to_m04_couplers_ARVALID(4),
m_axi_arvalid(3) => xbar_to_m03_couplers_ARVALID(3),
m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(447 downto 416) => xbar_to_m13_couplers_AWADDR(447 downto 416),
m_axi_awaddr(415 downto 384) => xbar_to_m12_couplers_AWADDR(415 downto 384),
m_axi_awaddr(383 downto 352) => xbar_to_m11_couplers_AWADDR(383 downto 352),
m_axi_awaddr(351 downto 320) => xbar_to_m10_couplers_AWADDR(351 downto 320),
m_axi_awaddr(319 downto 288) => xbar_to_m09_couplers_AWADDR(319 downto 288),
m_axi_awaddr(287 downto 256) => xbar_to_m08_couplers_AWADDR(287 downto 256),
m_axi_awaddr(255 downto 224) => xbar_to_m07_couplers_AWADDR(255 downto 224),
m_axi_awaddr(223 downto 192) => xbar_to_m06_couplers_AWADDR(223 downto 192),
m_axi_awaddr(191 downto 160) => xbar_to_m05_couplers_AWADDR(191 downto 160),
m_axi_awaddr(159 downto 128) => xbar_to_m04_couplers_AWADDR(159 downto 128),
m_axi_awaddr(127 downto 96) => xbar_to_m03_couplers_AWADDR(127 downto 96),
m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(41 downto 39) => xbar_to_m13_couplers_AWPROT(41 downto 39),
m_axi_awprot(38 downto 33) => NLW_xbar_m_axi_awprot_UNCONNECTED(38 downto 33),
m_axi_awprot(32 downto 30) => xbar_to_m10_couplers_AWPROT(32 downto 30),
m_axi_awprot(29 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(29 downto 0),
m_axi_awready(13) => xbar_to_m13_couplers_AWREADY,
m_axi_awready(12) => xbar_to_m12_couplers_AWREADY(0),
m_axi_awready(11) => xbar_to_m11_couplers_AWREADY(0),
m_axi_awready(10) => xbar_to_m10_couplers_AWREADY,
m_axi_awready(9) => xbar_to_m09_couplers_AWREADY(0),
m_axi_awready(8) => xbar_to_m08_couplers_AWREADY(0),
m_axi_awready(7) => xbar_to_m07_couplers_AWREADY(0),
m_axi_awready(6) => xbar_to_m06_couplers_AWREADY(0),
m_axi_awready(5) => xbar_to_m05_couplers_AWREADY(0),
m_axi_awready(4) => xbar_to_m04_couplers_AWREADY(0),
m_axi_awready(3) => xbar_to_m03_couplers_AWREADY(0),
m_axi_awready(2) => xbar_to_m02_couplers_AWREADY(0),
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY(0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY(0),
m_axi_awvalid(13) => xbar_to_m13_couplers_AWVALID(13),
m_axi_awvalid(12) => xbar_to_m12_couplers_AWVALID(12),
m_axi_awvalid(11) => xbar_to_m11_couplers_AWVALID(11),
m_axi_awvalid(10) => xbar_to_m10_couplers_AWVALID(10),
m_axi_awvalid(9) => xbar_to_m09_couplers_AWVALID(9),
m_axi_awvalid(8) => xbar_to_m08_couplers_AWVALID(8),
m_axi_awvalid(7) => xbar_to_m07_couplers_AWVALID(7),
m_axi_awvalid(6) => xbar_to_m06_couplers_AWVALID(6),
m_axi_awvalid(5) => xbar_to_m05_couplers_AWVALID(5),
m_axi_awvalid(4) => xbar_to_m04_couplers_AWVALID(4),
m_axi_awvalid(3) => xbar_to_m03_couplers_AWVALID(3),
m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(13) => xbar_to_m13_couplers_BREADY(13),
m_axi_bready(12) => xbar_to_m12_couplers_BREADY(12),
m_axi_bready(11) => xbar_to_m11_couplers_BREADY(11),
m_axi_bready(10) => xbar_to_m10_couplers_BREADY(10),
m_axi_bready(9) => xbar_to_m09_couplers_BREADY(9),
m_axi_bready(8) => xbar_to_m08_couplers_BREADY(8),
m_axi_bready(7) => xbar_to_m07_couplers_BREADY(7),
m_axi_bready(6) => xbar_to_m06_couplers_BREADY(6),
m_axi_bready(5) => xbar_to_m05_couplers_BREADY(5),
m_axi_bready(4) => xbar_to_m04_couplers_BREADY(4),
m_axi_bready(3) => xbar_to_m03_couplers_BREADY(3),
m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(27 downto 26) => xbar_to_m13_couplers_BRESP(1 downto 0),
m_axi_bresp(25 downto 24) => xbar_to_m12_couplers_BRESP(1 downto 0),
m_axi_bresp(23 downto 22) => xbar_to_m11_couplers_BRESP(1 downto 0),
m_axi_bresp(21) => xbar_to_m10_couplers_BRESP,
m_axi_bresp(20) => xbar_to_m10_couplers_BRESP,
m_axi_bresp(19 downto 18) => xbar_to_m09_couplers_BRESP(1 downto 0),
m_axi_bresp(17 downto 16) => xbar_to_m08_couplers_BRESP(1 downto 0),
m_axi_bresp(15 downto 14) => xbar_to_m07_couplers_BRESP(1 downto 0),
m_axi_bresp(13 downto 12) => xbar_to_m06_couplers_BRESP(1 downto 0),
m_axi_bresp(11 downto 10) => xbar_to_m05_couplers_BRESP(1 downto 0),
m_axi_bresp(9 downto 8) => xbar_to_m04_couplers_BRESP(1 downto 0),
m_axi_bresp(7 downto 6) => xbar_to_m03_couplers_BRESP(1 downto 0),
m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(13) => xbar_to_m13_couplers_BVALID,
m_axi_bvalid(12) => xbar_to_m12_couplers_BVALID(0),
m_axi_bvalid(11) => xbar_to_m11_couplers_BVALID(0),
m_axi_bvalid(10) => xbar_to_m10_couplers_BVALID,
m_axi_bvalid(9) => xbar_to_m09_couplers_BVALID(0),
m_axi_bvalid(8) => xbar_to_m08_couplers_BVALID(0),
m_axi_bvalid(7) => xbar_to_m07_couplers_BVALID(0),
m_axi_bvalid(6) => xbar_to_m06_couplers_BVALID(0),
m_axi_bvalid(5) => xbar_to_m05_couplers_BVALID(0),
m_axi_bvalid(4) => xbar_to_m04_couplers_BVALID(0),
m_axi_bvalid(3) => xbar_to_m03_couplers_BVALID(0),
m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID(0),
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID(0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
m_axi_rdata(447 downto 416) => xbar_to_m13_couplers_RDATA(31 downto 0),
m_axi_rdata(415 downto 384) => xbar_to_m12_couplers_RDATA(31 downto 0),
m_axi_rdata(383 downto 352) => xbar_to_m11_couplers_RDATA(31 downto 0),
m_axi_rdata(351) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(350) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(349) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(348) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(347) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(346) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(345) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(344) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(343) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(342) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(341) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(340) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(339) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(338) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(337) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(336) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(335) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(334) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(333) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(332) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(331) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(330) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(329) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(328) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(327) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(326) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(325) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(324) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(323) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(322) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(321) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(320) => xbar_to_m10_couplers_RDATA,
m_axi_rdata(319 downto 288) => xbar_to_m09_couplers_RDATA(31 downto 0),
m_axi_rdata(287 downto 256) => xbar_to_m08_couplers_RDATA(31 downto 0),
m_axi_rdata(255 downto 224) => xbar_to_m07_couplers_RDATA(31 downto 0),
m_axi_rdata(223 downto 192) => xbar_to_m06_couplers_RDATA(31 downto 0),
m_axi_rdata(191 downto 160) => xbar_to_m05_couplers_RDATA(31 downto 0),
m_axi_rdata(159 downto 128) => xbar_to_m04_couplers_RDATA(31 downto 0),
m_axi_rdata(127 downto 96) => xbar_to_m03_couplers_RDATA(31 downto 0),
m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(13) => xbar_to_m13_couplers_RREADY(13),
m_axi_rready(12) => xbar_to_m12_couplers_RREADY(12),
m_axi_rready(11) => xbar_to_m11_couplers_RREADY(11),
m_axi_rready(10) => xbar_to_m10_couplers_RREADY(10),
m_axi_rready(9) => xbar_to_m09_couplers_RREADY(9),
m_axi_rready(8) => xbar_to_m08_couplers_RREADY(8),
m_axi_rready(7) => xbar_to_m07_couplers_RREADY(7),
m_axi_rready(6) => xbar_to_m06_couplers_RREADY(6),
m_axi_rready(5) => xbar_to_m05_couplers_RREADY(5),
m_axi_rready(4) => xbar_to_m04_couplers_RREADY(4),
m_axi_rready(3) => xbar_to_m03_couplers_RREADY(3),
m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(27 downto 26) => xbar_to_m13_couplers_RRESP(1 downto 0),
m_axi_rresp(25 downto 24) => xbar_to_m12_couplers_RRESP(1 downto 0),
m_axi_rresp(23 downto 22) => xbar_to_m11_couplers_RRESP(1 downto 0),
m_axi_rresp(21) => xbar_to_m10_couplers_RRESP,
m_axi_rresp(20) => xbar_to_m10_couplers_RRESP,
m_axi_rresp(19 downto 18) => xbar_to_m09_couplers_RRESP(1 downto 0),
m_axi_rresp(17 downto 16) => xbar_to_m08_couplers_RRESP(1 downto 0),
m_axi_rresp(15 downto 14) => xbar_to_m07_couplers_RRESP(1 downto 0),
m_axi_rresp(13 downto 12) => xbar_to_m06_couplers_RRESP(1 downto 0),
m_axi_rresp(11 downto 10) => xbar_to_m05_couplers_RRESP(1 downto 0),
m_axi_rresp(9 downto 8) => xbar_to_m04_couplers_RRESP(1 downto 0),
m_axi_rresp(7 downto 6) => xbar_to_m03_couplers_RRESP(1 downto 0),
m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(13) => xbar_to_m13_couplers_RVALID,
m_axi_rvalid(12) => xbar_to_m12_couplers_RVALID(0),
m_axi_rvalid(11) => xbar_to_m11_couplers_RVALID(0),
m_axi_rvalid(10) => xbar_to_m10_couplers_RVALID,
m_axi_rvalid(9) => xbar_to_m09_couplers_RVALID(0),
m_axi_rvalid(8) => xbar_to_m08_couplers_RVALID(0),
m_axi_rvalid(7) => xbar_to_m07_couplers_RVALID(0),
m_axi_rvalid(6) => xbar_to_m06_couplers_RVALID(0),
m_axi_rvalid(5) => xbar_to_m05_couplers_RVALID(0),
m_axi_rvalid(4) => xbar_to_m04_couplers_RVALID(0),
m_axi_rvalid(3) => xbar_to_m03_couplers_RVALID(0),
m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID(0),
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID(0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
m_axi_wdata(447 downto 416) => xbar_to_m13_couplers_WDATA(447 downto 416),
m_axi_wdata(415 downto 384) => xbar_to_m12_couplers_WDATA(415 downto 384),
m_axi_wdata(383 downto 352) => xbar_to_m11_couplers_WDATA(383 downto 352),
m_axi_wdata(351 downto 320) => xbar_to_m10_couplers_WDATA(351 downto 320),
m_axi_wdata(319 downto 288) => xbar_to_m09_couplers_WDATA(319 downto 288),
m_axi_wdata(287 downto 256) => xbar_to_m08_couplers_WDATA(287 downto 256),
m_axi_wdata(255 downto 224) => xbar_to_m07_couplers_WDATA(255 downto 224),
m_axi_wdata(223 downto 192) => xbar_to_m06_couplers_WDATA(223 downto 192),
m_axi_wdata(191 downto 160) => xbar_to_m05_couplers_WDATA(191 downto 160),
m_axi_wdata(159 downto 128) => xbar_to_m04_couplers_WDATA(159 downto 128),
m_axi_wdata(127 downto 96) => xbar_to_m03_couplers_WDATA(127 downto 96),
m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(13) => xbar_to_m13_couplers_WREADY,
m_axi_wready(12) => xbar_to_m12_couplers_WREADY(0),
m_axi_wready(11) => xbar_to_m11_couplers_WREADY(0),
m_axi_wready(10) => xbar_to_m10_couplers_WREADY,
m_axi_wready(9) => xbar_to_m09_couplers_WREADY(0),
m_axi_wready(8) => xbar_to_m08_couplers_WREADY(0),
m_axi_wready(7) => xbar_to_m07_couplers_WREADY(0),
m_axi_wready(6) => xbar_to_m06_couplers_WREADY(0),
m_axi_wready(5) => xbar_to_m05_couplers_WREADY(0),
m_axi_wready(4) => xbar_to_m04_couplers_WREADY(0),
m_axi_wready(3) => xbar_to_m03_couplers_WREADY(0),
m_axi_wready(2) => xbar_to_m02_couplers_WREADY(0),
m_axi_wready(1) => xbar_to_m01_couplers_WREADY(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY(0),
m_axi_wstrb(55 downto 52) => xbar_to_m13_couplers_WSTRB(55 downto 52),
m_axi_wstrb(51 downto 48) => xbar_to_m12_couplers_WSTRB(51 downto 48),
m_axi_wstrb(47 downto 44) => xbar_to_m11_couplers_WSTRB(47 downto 44),
m_axi_wstrb(43 downto 40) => xbar_to_m10_couplers_WSTRB(43 downto 40),
m_axi_wstrb(39 downto 36) => xbar_to_m09_couplers_WSTRB(39 downto 36),
m_axi_wstrb(35 downto 32) => xbar_to_m08_couplers_WSTRB(35 downto 32),
m_axi_wstrb(31 downto 28) => xbar_to_m07_couplers_WSTRB(31 downto 28),
m_axi_wstrb(27 downto 24) => xbar_to_m06_couplers_WSTRB(27 downto 24),
m_axi_wstrb(23 downto 20) => xbar_to_m05_couplers_WSTRB(23 downto 20),
m_axi_wstrb(19 downto 16) => xbar_to_m04_couplers_WSTRB(19 downto 16),
m_axi_wstrb(15 downto 12) => xbar_to_m03_couplers_WSTRB(15 downto 12),
m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8),
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(13) => xbar_to_m13_couplers_WVALID(13),
m_axi_wvalid(12) => xbar_to_m12_couplers_WVALID(12),
m_axi_wvalid(11) => xbar_to_m11_couplers_WVALID(11),
m_axi_wvalid(10) => xbar_to_m10_couplers_WVALID(10),
m_axi_wvalid(9) => xbar_to_m09_couplers_WVALID(9),
m_axi_wvalid(8) => xbar_to_m08_couplers_WVALID(8),
m_axi_wvalid(7) => xbar_to_m07_couplers_WVALID(7),
m_axi_wvalid(6) => xbar_to_m06_couplers_WVALID(6),
m_axi_wvalid(5) => xbar_to_m05_couplers_WVALID(5),
m_axi_wvalid(4) => xbar_to_m04_couplers_WVALID(4),
m_axi_wvalid(3) => xbar_to_m03_couplers_WVALID(3),
m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID(0),
s_axi_bready(0) => s00_couplers_to_xbar_BREADY(0),
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY(0),
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
DDR3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
DDR3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
DDR3_cas_n : out STD_LOGIC;
DDR3_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR3_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
DDR3_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR3_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_ras_n : out STD_LOGIC;
DDR3_reset_n : out STD_LOGIC;
DDR3_we_n : out STD_LOGIC;
Vaux0_v_n : in STD_LOGIC;
Vaux0_v_p : in STD_LOGIC;
Vaux10_v_n : in STD_LOGIC;
Vaux10_v_p : in STD_LOGIC;
Vaux12_v_n : in STD_LOGIC;
Vaux12_v_p : in STD_LOGIC;
Vaux13_v_n : in STD_LOGIC;
Vaux13_v_p : in STD_LOGIC;
Vaux14_v_n : in STD_LOGIC;
Vaux14_v_p : in STD_LOGIC;
Vaux15_v_n : in STD_LOGIC;
Vaux15_v_p : in STD_LOGIC;
Vaux1_v_n : in STD_LOGIC;
Vaux1_v_p : in STD_LOGIC;
Vaux2_v_n : in STD_LOGIC;
Vaux2_v_p : in STD_LOGIC;
Vaux4_v_n : in STD_LOGIC;
Vaux4_v_p : in STD_LOGIC;
Vaux5_v_n : in STD_LOGIC;
Vaux5_v_p : in STD_LOGIC;
Vaux6_v_n : in STD_LOGIC;
Vaux6_v_p : in STD_LOGIC;
Vaux7_v_n : in STD_LOGIC;
Vaux7_v_p : in STD_LOGIC;
Vaux9_v_n : in STD_LOGIC;
Vaux9_v_p : in STD_LOGIC;
Vp_Vn_v_n : in STD_LOGIC;
Vp_Vn_v_p : in STD_LOGIC;
dip_switches_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
eth_mdio_mdc_mdc : out STD_LOGIC;
eth_mdio_mdc_mdio_i : in STD_LOGIC;
eth_mdio_mdc_mdio_o : out STD_LOGIC;
eth_mdio_mdc_mdio_t : out STD_LOGIC;
eth_mii_col : in STD_LOGIC;
eth_mii_crs : in STD_LOGIC;
eth_mii_rst_n : out STD_LOGIC;
eth_mii_rx_clk : in STD_LOGIC;
eth_mii_rx_dv : in STD_LOGIC;
eth_mii_rx_er : in STD_LOGIC;
eth_mii_rxd : in STD_LOGIC_VECTOR ( 3 downto 0 );
eth_mii_tx_clk : in STD_LOGIC;
eth_mii_tx_en : out STD_LOGIC;
eth_mii_txd : out STD_LOGIC_VECTOR ( 3 downto 0 );
eth_ref_clk : out STD_LOGIC;
i2c_pullups_tri_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
i2c_pullups_tri_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
i2c_pullups_tri_t : out STD_LOGIC_VECTOR ( 1 downto 0 );
i2c_scl_i : in STD_LOGIC;
i2c_scl_o : out STD_LOGIC;
i2c_scl_t : out STD_LOGIC;
i2c_sda_i : in STD_LOGIC;
i2c_sda_o : out STD_LOGIC;
i2c_sda_t : out STD_LOGIC;
led_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
led_4bits_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
led_4bits_tri_t : out STD_LOGIC_VECTOR ( 3 downto 0 );
push_buttons_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
qspi_flash_io0_i : in STD_LOGIC;
qspi_flash_io0_o : out STD_LOGIC;
qspi_flash_io0_t : out STD_LOGIC;
qspi_flash_io1_i : in STD_LOGIC;
qspi_flash_io1_o : out STD_LOGIC;
qspi_flash_io1_t : out STD_LOGIC;
qspi_flash_io2_i : in STD_LOGIC;
qspi_flash_io2_o : out STD_LOGIC;
qspi_flash_io2_t : out STD_LOGIC;
qspi_flash_io3_i : in STD_LOGIC;
qspi_flash_io3_o : out STD_LOGIC;
qspi_flash_io3_t : out STD_LOGIC;
qspi_flash_sck_i : in STD_LOGIC;
qspi_flash_sck_o : out STD_LOGIC;
qspi_flash_sck_t : out STD_LOGIC;
qspi_flash_ss_i : in STD_LOGIC;
qspi_flash_ss_o : out STD_LOGIC;
qspi_flash_ss_t : out STD_LOGIC;
reset : in STD_LOGIC;
rgb_led_tri_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
rgb_led_tri_o : out STD_LOGIC_VECTOR ( 11 downto 0 );
rgb_led_tri_t : out STD_LOGIC_VECTOR ( 11 downto 0 );
shield_dp0_dp19_tri_i : in STD_LOGIC_VECTOR ( 19 downto 0 );
shield_dp0_dp19_tri_o : out STD_LOGIC_VECTOR ( 19 downto 0 );
shield_dp0_dp19_tri_t : out STD_LOGIC_VECTOR ( 19 downto 0 );
shield_dp26_dp41_tri_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
shield_dp26_dp41_tri_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
shield_dp26_dp41_tri_t : out STD_LOGIC_VECTOR ( 15 downto 0 );
spi_io0_i : in STD_LOGIC;
spi_io0_o : out STD_LOGIC;
spi_io0_t : out STD_LOGIC;
spi_io1_i : in STD_LOGIC;
spi_io1_o : out STD_LOGIC;
spi_io1_t : out STD_LOGIC;
spi_sck_i : in STD_LOGIC;
spi_sck_o : out STD_LOGIC;
spi_sck_t : out STD_LOGIC;
spi_ss_i : in STD_LOGIC;
spi_ss_o : out STD_LOGIC;
spi_ss_t : out STD_LOGIC;
sys_clock : in STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of system : entity is "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=52,numReposBlks=31,numNonXlnxBlks=0,numHierBlks=21,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system : entity is "system.hwdef";
end system;
architecture STRUCTURE of system is
component system_microblaze_0_xlconcat_0 is
port (
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
In2 : in STD_LOGIC_VECTOR ( 0 to 0 );
In3 : in STD_LOGIC_VECTOR ( 0 to 0 );
In4 : in STD_LOGIC_VECTOR ( 0 to 0 );
In5 : in STD_LOGIC_VECTOR ( 0 to 0 );
In6 : in STD_LOGIC_VECTOR ( 0 to 0 );
dout : out STD_LOGIC_VECTOR ( 6 downto 0 )
);
end component system_microblaze_0_xlconcat_0;
component system_axi_ethernetlite_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
phy_tx_clk : in STD_LOGIC;
phy_rx_clk : in STD_LOGIC;
phy_crs : in STD_LOGIC;
phy_dv : in STD_LOGIC;
phy_rx_data : in STD_LOGIC_VECTOR ( 3 downto 0 );
phy_col : in STD_LOGIC;
phy_rx_er : in STD_LOGIC;
phy_rst_n : out STD_LOGIC;
phy_tx_en : out STD_LOGIC;
phy_tx_data : out STD_LOGIC_VECTOR ( 3 downto 0 );
phy_mdio_i : in STD_LOGIC;
phy_mdio_o : out STD_LOGIC;
phy_mdio_t : out STD_LOGIC;
phy_mdc : out STD_LOGIC
);
end component system_axi_ethernetlite_0_0;
component system_axi_gpio_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 19 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 19 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
end component system_axi_gpio_0_0;
component system_axi_gpio_1_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end component system_axi_gpio_1_0;
component system_axi_gpio_led_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 11 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end component system_axi_gpio_led_0;
component system_axi_gpio_pullup_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component system_axi_gpio_pullup_0;
component system_axi_gpio_sw_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end component system_axi_gpio_sw_0;
component system_axi_iic_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
iic2intc_irpt : out STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
sda_t : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
scl_t : out STD_LOGIC;
gpo : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_axi_iic_0_0;
component system_axi_quad_spi_flash_0 is
port (
ext_spi_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
io0_i : in STD_LOGIC;
io0_o : out STD_LOGIC;
io0_t : out STD_LOGIC;
io1_i : in STD_LOGIC;
io1_o : out STD_LOGIC;
io1_t : out STD_LOGIC;
io2_i : in STD_LOGIC;
io2_o : out STD_LOGIC;
io2_t : out STD_LOGIC;
io3_i : in STD_LOGIC;
io3_o : out STD_LOGIC;
io3_t : out STD_LOGIC;
sck_i : in STD_LOGIC;
sck_o : out STD_LOGIC;
sck_t : out STD_LOGIC;
ss_i : in STD_LOGIC_VECTOR ( 0 to 0 );
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
ss_t : out STD_LOGIC;
ip2intc_irpt : out STD_LOGIC
);
end component system_axi_quad_spi_flash_0;
component system_axi_quad_spi_shield_0 is
port (
ext_spi_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
io0_i : in STD_LOGIC;
io0_o : out STD_LOGIC;
io0_t : out STD_LOGIC;
io1_i : in STD_LOGIC;
io1_o : out STD_LOGIC;
io1_t : out STD_LOGIC;
sck_i : in STD_LOGIC;
sck_o : out STD_LOGIC;
sck_t : out STD_LOGIC;
ss_i : in STD_LOGIC_VECTOR ( 0 to 0 );
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
ss_t : out STD_LOGIC;
ip2intc_irpt : out STD_LOGIC
);
end component system_axi_quad_spi_shield_0;
component system_axi_timer_0_0 is
port (
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC;
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
pwm0 : out STD_LOGIC;
interrupt : out STD_LOGIC;
freeze : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC
);
end component system_axi_timer_0_0;
component system_axi_uartlite_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
interrupt : out STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
rx : in STD_LOGIC;
tx : out STD_LOGIC
);
end component system_axi_uartlite_0_0;
component system_clk_wiz_1_0 is
port (
resetn : in STD_LOGIC;
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC;
clk_out3 : out STD_LOGIC;
clk_out4 : out STD_LOGIC;
locked : out STD_LOGIC
);
end component system_clk_wiz_1_0;
component system_mdm_1_0 is
port (
Debug_SYS_Rst : out STD_LOGIC;
Dbg_Clk_0 : out STD_LOGIC;
Dbg_TDI_0 : out STD_LOGIC;
Dbg_TDO_0 : in STD_LOGIC;
Dbg_Reg_En_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_0 : out STD_LOGIC;
Dbg_Shift_0 : out STD_LOGIC;
Dbg_Update_0 : out STD_LOGIC;
Dbg_Rst_0 : out STD_LOGIC;
Dbg_Disable_0 : out STD_LOGIC
);
end component system_mdm_1_0;
component system_microblaze_0_0 is
port (
Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Interrupt : in STD_LOGIC;
Interrupt_Address : in STD_LOGIC_VECTOR ( 0 to 31 );
Interrupt_Ack : out STD_LOGIC_VECTOR ( 0 to 1 );
Instr_Addr : out STD_LOGIC_VECTOR ( 0 to 31 );
Instr : in STD_LOGIC_VECTOR ( 0 to 31 );
IFetch : out STD_LOGIC;
I_AS : out STD_LOGIC;
IReady : in STD_LOGIC;
IWAIT : in STD_LOGIC;
ICE : in STD_LOGIC;
IUE : in STD_LOGIC;
Data_Addr : out STD_LOGIC_VECTOR ( 0 to 31 );
Data_Read : in STD_LOGIC_VECTOR ( 0 to 31 );
Data_Write : out STD_LOGIC_VECTOR ( 0 to 31 );
D_AS : out STD_LOGIC;
Read_Strobe : out STD_LOGIC;
Write_Strobe : out STD_LOGIC;
DReady : in STD_LOGIC;
DWait : in STD_LOGIC;
DCE : in STD_LOGIC;
DUE : in STD_LOGIC;
Byte_Enable : out STD_LOGIC_VECTOR ( 0 to 3 );
M_AXI_DP_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DP_AWVALID : out STD_LOGIC;
M_AXI_DP_AWREADY : in STD_LOGIC;
M_AXI_DP_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DP_WVALID : out STD_LOGIC;
M_AXI_DP_WREADY : in STD_LOGIC;
M_AXI_DP_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DP_BVALID : in STD_LOGIC;
M_AXI_DP_BREADY : out STD_LOGIC;
M_AXI_DP_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DP_ARVALID : out STD_LOGIC;
M_AXI_DP_ARREADY : in STD_LOGIC;
M_AXI_DP_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DP_RVALID : in STD_LOGIC;
M_AXI_DP_RREADY : out STD_LOGIC;
Dbg_Clk : in STD_LOGIC;
Dbg_TDI : in STD_LOGIC;
Dbg_TDO : out STD_LOGIC;
Dbg_Reg_En : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Shift : in STD_LOGIC;
Dbg_Capture : in STD_LOGIC;
Dbg_Update : in STD_LOGIC;
Debug_Rst : in STD_LOGIC;
Dbg_Disable : in STD_LOGIC;
M_AXI_IC_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_IC_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_IC_AWLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_IC_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_IC_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_IC_AWLOCK : out STD_LOGIC;
M_AXI_IC_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_IC_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_AWVALID : out STD_LOGIC;
M_AXI_IC_AWREADY : in STD_LOGIC;
M_AXI_IC_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_IC_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_WLAST : out STD_LOGIC;
M_AXI_IC_WVALID : out STD_LOGIC;
M_AXI_IC_WREADY : in STD_LOGIC;
M_AXI_IC_BID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_IC_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_IC_BVALID : in STD_LOGIC;
M_AXI_IC_BREADY : out STD_LOGIC;
M_AXI_IC_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_IC_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_IC_ARLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_IC_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_IC_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_IC_ARLOCK : out STD_LOGIC;
M_AXI_IC_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_IC_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_IC_ARVALID : out STD_LOGIC;
M_AXI_IC_ARREADY : in STD_LOGIC;
M_AXI_IC_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_IC_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_IC_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_IC_RLAST : in STD_LOGIC;
M_AXI_IC_RVALID : in STD_LOGIC;
M_AXI_IC_RREADY : out STD_LOGIC;
M_AXI_DC_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_DC_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DC_AWLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_DC_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DC_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DC_AWLOCK : out STD_LOGIC;
M_AXI_DC_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DC_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_AWVALID : out STD_LOGIC;
M_AXI_DC_AWREADY : in STD_LOGIC;
M_AXI_DC_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DC_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_WLAST : out STD_LOGIC;
M_AXI_DC_WVALID : out STD_LOGIC;
M_AXI_DC_WREADY : in STD_LOGIC;
M_AXI_DC_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DC_BID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_DC_BVALID : in STD_LOGIC;
M_AXI_DC_BREADY : out STD_LOGIC;
M_AXI_DC_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_DC_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DC_ARLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_DC_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DC_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DC_ARLOCK : out STD_LOGIC;
M_AXI_DC_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DC_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DC_ARVALID : out STD_LOGIC;
M_AXI_DC_ARREADY : in STD_LOGIC;
M_AXI_DC_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_DC_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DC_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DC_RLAST : in STD_LOGIC;
M_AXI_DC_RVALID : in STD_LOGIC;
M_AXI_DC_RREADY : out STD_LOGIC
);
end component system_microblaze_0_0;
component system_microblaze_0_axi_intc_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
intr : in STD_LOGIC_VECTOR ( 6 downto 0 );
processor_clk : in STD_LOGIC;
processor_rst : in STD_LOGIC;
irq : out STD_LOGIC;
processor_ack : in STD_LOGIC_VECTOR ( 1 downto 0 );
interrupt_address : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_microblaze_0_axi_intc_0;
component system_mig_7series_0_0 is
port (
device_temp_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
sys_rst : in STD_LOGIC;
clk_ref_i : in STD_LOGIC;
ddr3_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
ddr3_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
ddr3_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
ddr3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
ddr3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
ddr3_ras_n : out STD_LOGIC;
ddr3_cas_n : out STD_LOGIC;
ddr3_we_n : out STD_LOGIC;
ddr3_reset_n : out STD_LOGIC;
ddr3_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr3_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr3_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
ddr3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
ui_clk_sync_rst : out STD_LOGIC;
ui_clk : out STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 27 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 27 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
mmcm_locked : out STD_LOGIC;
sys_clk_i : in STD_LOGIC;
init_calib_complete : out STD_LOGIC;
aresetn : in STD_LOGIC
);
end component system_mig_7series_0_0;
component system_rst_clk_wiz_1_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_rst_clk_wiz_1_100M_0;
component system_rst_mig_7series_0_83M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_rst_mig_7series_0_83M_0;
component system_xadc_wiz_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
vp_in : in STD_LOGIC;
vn_in : in STD_LOGIC;
vauxp0 : in STD_LOGIC;
vauxn0 : in STD_LOGIC;
vauxp1 : in STD_LOGIC;
vauxn1 : in STD_LOGIC;
vauxp2 : in STD_LOGIC;
vauxn2 : in STD_LOGIC;
vauxp4 : in STD_LOGIC;
vauxn4 : in STD_LOGIC;
vauxp5 : in STD_LOGIC;
vauxn5 : in STD_LOGIC;
vauxp6 : in STD_LOGIC;
vauxn6 : in STD_LOGIC;
vauxp7 : in STD_LOGIC;
vauxn7 : in STD_LOGIC;
vauxp9 : in STD_LOGIC;
vauxn9 : in STD_LOGIC;
vauxp10 : in STD_LOGIC;
vauxn10 : in STD_LOGIC;
vauxp12 : in STD_LOGIC;
vauxn12 : in STD_LOGIC;
vauxp13 : in STD_LOGIC;
vauxn13 : in STD_LOGIC;
vauxp14 : in STD_LOGIC;
vauxn14 : in STD_LOGIC;
vauxp15 : in STD_LOGIC;
vauxn15 : in STD_LOGIC;
user_temp_alarm_out : out STD_LOGIC;
vccint_alarm_out : out STD_LOGIC;
vccaux_alarm_out : out STD_LOGIC;
channel_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
eoc_out : out STD_LOGIC;
alarm_out : out STD_LOGIC;
eos_out : out STD_LOGIC;
busy_out : out STD_LOGIC;
temp_out : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end component system_xadc_wiz_0_0;
signal Vaux0_1_V_N : STD_LOGIC;
signal Vaux0_1_V_P : STD_LOGIC;
signal Vaux10_1_V_N : STD_LOGIC;
signal Vaux10_1_V_P : STD_LOGIC;
signal Vaux12_1_V_N : STD_LOGIC;
signal Vaux12_1_V_P : STD_LOGIC;
signal Vaux13_1_V_N : STD_LOGIC;
signal Vaux13_1_V_P : STD_LOGIC;
signal Vaux14_1_V_N : STD_LOGIC;
signal Vaux14_1_V_P : STD_LOGIC;
signal Vaux15_1_V_N : STD_LOGIC;
signal Vaux15_1_V_P : STD_LOGIC;
signal Vaux1_1_V_N : STD_LOGIC;
signal Vaux1_1_V_P : STD_LOGIC;
signal Vaux2_1_V_N : STD_LOGIC;
signal Vaux2_1_V_P : STD_LOGIC;
signal Vaux4_1_V_N : STD_LOGIC;
signal Vaux4_1_V_P : STD_LOGIC;
signal Vaux5_1_V_N : STD_LOGIC;
signal Vaux5_1_V_P : STD_LOGIC;
signal Vaux6_1_V_N : STD_LOGIC;
signal Vaux6_1_V_P : STD_LOGIC;
signal Vaux7_1_V_N : STD_LOGIC;
signal Vaux7_1_V_P : STD_LOGIC;
signal Vaux9_1_V_N : STD_LOGIC;
signal Vaux9_1_V_P : STD_LOGIC;
signal Vp_Vn_1_V_N : STD_LOGIC;
signal Vp_Vn_1_V_P : STD_LOGIC;
signal axi_ethernetlite_0_MDIO_MDC : STD_LOGIC;
signal axi_ethernetlite_0_MDIO_MDIO_I : STD_LOGIC;
signal axi_ethernetlite_0_MDIO_MDIO_O : STD_LOGIC;
signal axi_ethernetlite_0_MDIO_MDIO_T : STD_LOGIC;
signal axi_ethernetlite_0_MII_COL : STD_LOGIC;
signal axi_ethernetlite_0_MII_CRS : STD_LOGIC;
signal axi_ethernetlite_0_MII_RST_N : STD_LOGIC;
signal axi_ethernetlite_0_MII_RXD : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_ethernetlite_0_MII_RX_CLK : STD_LOGIC;
signal axi_ethernetlite_0_MII_RX_DV : STD_LOGIC;
signal axi_ethernetlite_0_MII_RX_ER : STD_LOGIC;
signal axi_ethernetlite_0_MII_TXD : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_ethernetlite_0_MII_TX_CLK : STD_LOGIC;
signal axi_ethernetlite_0_MII_TX_EN : STD_LOGIC;
signal axi_ethernetlite_0_ip2intc_irpt : STD_LOGIC;
signal axi_gpio_0_GPIO2_TRI_I : STD_LOGIC_VECTOR ( 19 downto 0 );
signal axi_gpio_0_GPIO2_TRI_O : STD_LOGIC_VECTOR ( 19 downto 0 );
signal axi_gpio_0_GPIO2_TRI_T : STD_LOGIC_VECTOR ( 19 downto 0 );
signal axi_gpio_1_GPIO1_TRI_I : STD_LOGIC_VECTOR ( 15 downto 0 );
signal axi_gpio_1_GPIO1_TRI_O : STD_LOGIC_VECTOR ( 15 downto 0 );
signal axi_gpio_1_GPIO1_TRI_T : STD_LOGIC_VECTOR ( 15 downto 0 );
signal axi_gpio_2_GPIO2_TRI_I : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_gpio_2_GPIO2_TRI_O : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_gpio_2_GPIO2_TRI_T : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_gpio_2_GPIO_TRI_I : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_gpio_2_GPIO_TRI_O : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_gpio_2_GPIO_TRI_T : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_gpio_pullup_GPIO_TRI_I : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_gpio_pullup_GPIO_TRI_O : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_gpio_pullup_GPIO_TRI_T : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_gpio_sw_GPIO2_TRI_I : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_gpio_sw_GPIO_TRI_I : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_gpio_sw_ip2intc_irpt : STD_LOGIC;
signal axi_iic_0_IIC_SCL_I : STD_LOGIC;
signal axi_iic_0_IIC_SCL_O : STD_LOGIC;
signal axi_iic_0_IIC_SCL_T : STD_LOGIC;
signal axi_iic_0_IIC_SDA_I : STD_LOGIC;
signal axi_iic_0_IIC_SDA_O : STD_LOGIC;
signal axi_iic_0_IIC_SDA_T : STD_LOGIC;
signal axi_iic_0_iic2intc_irpt : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 27 downto 0 );
signal axi_mem_intercon_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_M00_AXI_ARLOCK : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 27 downto 0 );
signal axi_mem_intercon_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_M00_AXI_AWLOCK : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_BREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_BVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal axi_mem_intercon_M00_AXI_RID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_M00_AXI_RLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_RVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 127 downto 0 );
signal axi_mem_intercon_M00_AXI_WLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 15 downto 0 );
signal axi_mem_intercon_M00_AXI_WVALID : STD_LOGIC;
signal axi_quad_spi_0_SPI_0_IO0_I : STD_LOGIC;
signal axi_quad_spi_0_SPI_0_IO0_O : STD_LOGIC;
signal axi_quad_spi_0_SPI_0_IO0_T : STD_LOGIC;
signal axi_quad_spi_0_SPI_0_IO1_I : STD_LOGIC;
signal axi_quad_spi_0_SPI_0_IO1_O : STD_LOGIC;
signal axi_quad_spi_0_SPI_0_IO1_T : STD_LOGIC;
signal axi_quad_spi_0_SPI_0_SCK_I : STD_LOGIC;
signal axi_quad_spi_0_SPI_0_SCK_O : STD_LOGIC;
signal axi_quad_spi_0_SPI_0_SCK_T : STD_LOGIC;
signal axi_quad_spi_0_SPI_0_SS_I : STD_LOGIC;
signal axi_quad_spi_0_SPI_0_SS_O : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_quad_spi_0_SPI_0_SS_T : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_IO0_I : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_IO0_O : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_IO0_T : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_IO1_I : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_IO1_O : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_IO1_T : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_IO2_I : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_IO2_O : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_IO2_T : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_IO3_I : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_IO3_O : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_IO3_T : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_SCK_I : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_SCK_O : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_SCK_T : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_SS_I : STD_LOGIC;
signal axi_quad_spi_1_SPI_0_SS_O : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_quad_spi_1_SPI_0_SS_T : STD_LOGIC;
signal axi_quad_spi_flash_ip2intc_irpt : STD_LOGIC;
signal axi_quad_spi_shield_ip2intc_irpt : STD_LOGIC;
signal axi_timer_0_interrupt : STD_LOGIC;
signal axi_uartlite_0_UART_RxD : STD_LOGIC;
signal axi_uartlite_0_UART_TxD : STD_LOGIC;
signal clk_wiz_1_clk_out2 : STD_LOGIC;
signal clk_wiz_1_clk_out3 : STD_LOGIC;
signal clk_wiz_1_clk_out4 : STD_LOGIC;
signal clk_wiz_1_locked : STD_LOGIC;
signal mdm_1_debug_sys_rst : STD_LOGIC;
signal microblaze_0_Clk : STD_LOGIC;
signal microblaze_0_M_AXI_DC_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_DC_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_DC_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_DC_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal microblaze_0_M_AXI_DC_ARLOCK : STD_LOGIC;
signal microblaze_0_M_AXI_DC_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_DC_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_DC_ARREADY : STD_LOGIC;
signal microblaze_0_M_AXI_DC_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_DC_ARVALID : STD_LOGIC;
signal microblaze_0_M_AXI_DC_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_DC_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_DC_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_DC_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal microblaze_0_M_AXI_DC_AWLOCK : STD_LOGIC;
signal microblaze_0_M_AXI_DC_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_DC_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_DC_AWREADY : STD_LOGIC;
signal microblaze_0_M_AXI_DC_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_DC_AWVALID : STD_LOGIC;
signal microblaze_0_M_AXI_DC_BREADY : STD_LOGIC;
signal microblaze_0_M_AXI_DC_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_DC_BVALID : STD_LOGIC;
signal microblaze_0_M_AXI_DC_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_DC_RLAST : STD_LOGIC;
signal microblaze_0_M_AXI_DC_RREADY : STD_LOGIC;
signal microblaze_0_M_AXI_DC_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_DC_RVALID : STD_LOGIC;
signal microblaze_0_M_AXI_DC_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_DC_WLAST : STD_LOGIC;
signal microblaze_0_M_AXI_DC_WREADY : STD_LOGIC;
signal microblaze_0_M_AXI_DC_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_DC_WVALID : STD_LOGIC;
signal microblaze_0_M_AXI_IC_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_IC_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_IC_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_IC_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal microblaze_0_M_AXI_IC_ARLOCK : STD_LOGIC;
signal microblaze_0_M_AXI_IC_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_IC_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_M_AXI_IC_ARREADY : STD_LOGIC;
signal microblaze_0_M_AXI_IC_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_M_AXI_IC_ARVALID : STD_LOGIC;
signal microblaze_0_M_AXI_IC_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_M_AXI_IC_RLAST : STD_LOGIC;
signal microblaze_0_M_AXI_IC_RREADY : STD_LOGIC;
signal microblaze_0_M_AXI_IC_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_M_AXI_IC_RVALID : STD_LOGIC;
signal microblaze_0_axi_dp_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_dp_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_axi_dp_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_dp_ARVALID : STD_LOGIC;
signal microblaze_0_axi_dp_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_dp_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_axi_dp_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_dp_AWVALID : STD_LOGIC;
signal microblaze_0_axi_dp_BREADY : STD_LOGIC;
signal microblaze_0_axi_dp_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_dp_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_dp_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_dp_RREADY : STD_LOGIC;
signal microblaze_0_axi_dp_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_dp_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_dp_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_dp_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_dp_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_dp_WVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M01_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M01_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M02_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M03_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M03_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M03_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M03_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M03_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M04_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M04_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M04_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M04_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M04_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M04_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M04_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M04_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M04_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M04_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M04_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M04_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M04_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M04_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M04_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M04_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M04_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M05_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M05_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M05_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M05_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M05_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M05_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M05_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M05_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M05_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M05_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M05_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M05_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M05_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M05_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M05_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M05_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M05_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M06_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M06_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M06_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M06_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M06_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M06_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M06_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M06_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M06_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M06_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M06_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M06_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M06_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M06_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M06_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M06_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M06_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M07_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M07_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M07_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M07_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M07_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M07_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M07_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M07_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M07_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M07_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M07_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M07_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M07_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M07_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M07_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M07_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M07_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M08_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M08_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M08_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M08_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M08_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M08_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M08_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M08_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M08_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M08_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M08_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M08_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M08_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M08_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M08_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M08_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M08_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M09_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M09_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M09_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M09_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M09_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M09_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M09_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M09_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M09_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M09_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M09_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M09_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M09_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M09_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M09_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M09_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M09_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M11_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M11_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M11_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M11_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M11_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M11_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M11_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M11_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M11_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M11_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M11_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M11_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M11_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M11_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M11_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M11_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M11_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M12_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M12_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M12_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M12_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M12_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M12_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M12_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M12_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M12_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M12_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M12_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M12_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M12_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M12_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M12_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M12_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M12_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_M13_AXI_ARADDR : STD_LOGIC_VECTOR ( 10 downto 0 );
signal microblaze_0_axi_periph_M13_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M13_AXI_ARVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M13_AXI_AWADDR : STD_LOGIC_VECTOR ( 10 downto 0 );
signal microblaze_0_axi_periph_M13_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M13_AXI_AWVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M13_AXI_BREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M13_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M13_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M13_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M13_AXI_RREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M13_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M13_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M13_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M13_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M13_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M13_AXI_WVALID : STD_LOGIC;
signal microblaze_0_debug_CAPTURE : STD_LOGIC;
signal microblaze_0_debug_CLK : STD_LOGIC;
signal microblaze_0_debug_DISABLE : STD_LOGIC;
signal microblaze_0_debug_REG_EN : STD_LOGIC_VECTOR ( 0 to 7 );
signal microblaze_0_debug_RST : STD_LOGIC;
signal microblaze_0_debug_SHIFT : STD_LOGIC;
signal microblaze_0_debug_TDI : STD_LOGIC;
signal microblaze_0_debug_TDO : STD_LOGIC;
signal microblaze_0_debug_UPDATE : STD_LOGIC;
signal microblaze_0_dlmb_1_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_1_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_1_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal microblaze_0_dlmb_1_CE : STD_LOGIC;
signal microblaze_0_dlmb_1_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_1_READSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_1_READY : STD_LOGIC;
signal microblaze_0_dlmb_1_UE : STD_LOGIC;
signal microblaze_0_dlmb_1_WAIT : STD_LOGIC;
signal microblaze_0_dlmb_1_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_1_WRITESTROBE : STD_LOGIC;
signal microblaze_0_ilmb_1_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_1_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_1_CE : STD_LOGIC;
signal microblaze_0_ilmb_1_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_1_READSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_1_READY : STD_LOGIC;
signal microblaze_0_ilmb_1_UE : STD_LOGIC;
signal microblaze_0_ilmb_1_WAIT : STD_LOGIC;
signal microblaze_0_intc_axi_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_intc_axi_ARREADY : STD_LOGIC;
signal microblaze_0_intc_axi_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_intc_axi_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_intc_axi_AWREADY : STD_LOGIC;
signal microblaze_0_intc_axi_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_intc_axi_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_intc_axi_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_intc_axi_BVALID : STD_LOGIC;
signal microblaze_0_intc_axi_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_intc_axi_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_intc_axi_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_intc_axi_RVALID : STD_LOGIC;
signal microblaze_0_intc_axi_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_intc_axi_WREADY : STD_LOGIC;
signal microblaze_0_intc_axi_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_intc_axi_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_interrupt_ACK : STD_LOGIC_VECTOR ( 0 to 1 );
signal microblaze_0_interrupt_ADDRESS : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_interrupt_INTERRUPT : STD_LOGIC;
signal microblaze_0_intr : STD_LOGIC_VECTOR ( 6 downto 0 );
signal mig_7series_0_DDR3_ADDR : STD_LOGIC_VECTOR ( 13 downto 0 );
signal mig_7series_0_DDR3_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal mig_7series_0_DDR3_CAS_N : STD_LOGIC;
signal mig_7series_0_DDR3_CKE : STD_LOGIC_VECTOR ( 0 to 0 );
signal mig_7series_0_DDR3_CK_N : STD_LOGIC_VECTOR ( 0 to 0 );
signal mig_7series_0_DDR3_CK_P : STD_LOGIC_VECTOR ( 0 to 0 );
signal mig_7series_0_DDR3_CS_N : STD_LOGIC_VECTOR ( 0 to 0 );
signal mig_7series_0_DDR3_DM : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mig_7series_0_DDR3_DQ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal mig_7series_0_DDR3_DQS_N : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mig_7series_0_DDR3_DQS_P : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mig_7series_0_DDR3_ODT : STD_LOGIC_VECTOR ( 0 to 0 );
signal mig_7series_0_DDR3_RAS_N : STD_LOGIC;
signal mig_7series_0_DDR3_RESET_N : STD_LOGIC;
signal mig_7series_0_DDR3_WE_N : STD_LOGIC;
signal mig_7series_0_mmcm_locked : STD_LOGIC;
signal mig_7series_0_ui_clk : STD_LOGIC;
signal mig_7series_0_ui_clk_sync_rst : STD_LOGIC;
signal reset_1 : STD_LOGIC;
signal rst_clk_wiz_1_100M_bus_struct_reset : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_clk_wiz_1_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_clk_wiz_1_100M_mb_reset : STD_LOGIC;
signal rst_clk_wiz_1_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_mig_7series_0_83M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal sys_clock_1 : STD_LOGIC;
signal xadc_wiz_0_ip2intc_irpt : STD_LOGIC;
signal xadc_wiz_0_temp_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_axi_gpio_0_ip2intc_irpt_UNCONNECTED : STD_LOGIC;
signal NLW_axi_gpio_1_ip2intc_irpt_UNCONNECTED : STD_LOGIC;
signal NLW_axi_iic_0_gpo_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_axi_timer_0_generateout0_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_generateout1_UNCONNECTED : STD_LOGIC;
signal NLW_axi_timer_0_pwm0_UNCONNECTED : STD_LOGIC;
signal NLW_axi_uartlite_0_interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_M_AXI_IC_AWLOCK_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_M_AXI_IC_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_M_AXI_IC_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_M_AXI_IC_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_M_AXI_IC_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_M_AXI_DC_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_microblaze_0_M_AXI_DC_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_microblaze_0_M_AXI_IC_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_microblaze_0_M_AXI_IC_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_microblaze_0_M_AXI_IC_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_microblaze_0_M_AXI_IC_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_microblaze_0_M_AXI_IC_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_microblaze_0_M_AXI_IC_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_microblaze_0_M_AXI_IC_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_microblaze_0_M_AXI_IC_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_microblaze_0_M_AXI_IC_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_microblaze_0_M_AXI_IC_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_microblaze_0_M_AXI_IC_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_microblaze_0_axi_periph_M10_AXI_araddr_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_axi_periph_M10_AXI_arprot_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_axi_periph_M10_AXI_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_axi_periph_M10_AXI_awaddr_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_axi_periph_M10_AXI_awprot_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_axi_periph_M10_AXI_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_axi_periph_M10_AXI_bready_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_axi_periph_M10_AXI_rready_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_axi_periph_M10_AXI_wdata_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_axi_periph_M10_AXI_wstrb_UNCONNECTED : STD_LOGIC;
signal NLW_microblaze_0_axi_periph_M10_AXI_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_mig_7series_0_init_calib_complete_UNCONNECTED : STD_LOGIC;
signal NLW_rst_clk_wiz_1_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_mig_7series_0_83M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_mig_7series_0_83M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_mig_7series_0_83M_interconnect_aresetn_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_mig_7series_0_83M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xadc_wiz_0_alarm_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_busy_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_eoc_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_eos_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_user_temp_alarm_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_vccaux_alarm_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_vccint_alarm_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_channel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute BMM_INFO_PROCESSOR : string;
attribute BMM_INFO_PROCESSOR of microblaze_0 : label is "microblaze-le > system microblaze_0_local_memory/dlmb_bram_if_cntlr";
attribute KEEP_HIERARCHY : string;
attribute KEEP_HIERARCHY of microblaze_0 : label is "yes";
begin
DDR3_addr(13 downto 0) <= mig_7series_0_DDR3_ADDR(13 downto 0);
DDR3_ba(2 downto 0) <= mig_7series_0_DDR3_BA(2 downto 0);
DDR3_cas_n <= mig_7series_0_DDR3_CAS_N;
DDR3_ck_n(0) <= mig_7series_0_DDR3_CK_N(0);
DDR3_ck_p(0) <= mig_7series_0_DDR3_CK_P(0);
DDR3_cke(0) <= mig_7series_0_DDR3_CKE(0);
DDR3_cs_n(0) <= mig_7series_0_DDR3_CS_N(0);
DDR3_dm(1 downto 0) <= mig_7series_0_DDR3_DM(1 downto 0);
DDR3_odt(0) <= mig_7series_0_DDR3_ODT(0);
DDR3_ras_n <= mig_7series_0_DDR3_RAS_N;
DDR3_reset_n <= mig_7series_0_DDR3_RESET_N;
DDR3_we_n <= mig_7series_0_DDR3_WE_N;
Vaux0_1_V_N <= Vaux0_v_n;
Vaux0_1_V_P <= Vaux0_v_p;
Vaux10_1_V_N <= Vaux10_v_n;
Vaux10_1_V_P <= Vaux10_v_p;
Vaux12_1_V_N <= Vaux12_v_n;
Vaux12_1_V_P <= Vaux12_v_p;
Vaux13_1_V_N <= Vaux13_v_n;
Vaux13_1_V_P <= Vaux13_v_p;
Vaux14_1_V_N <= Vaux14_v_n;
Vaux14_1_V_P <= Vaux14_v_p;
Vaux15_1_V_N <= Vaux15_v_n;
Vaux15_1_V_P <= Vaux15_v_p;
Vaux1_1_V_N <= Vaux1_v_n;
Vaux1_1_V_P <= Vaux1_v_p;
Vaux2_1_V_N <= Vaux2_v_n;
Vaux2_1_V_P <= Vaux2_v_p;
Vaux4_1_V_N <= Vaux4_v_n;
Vaux4_1_V_P <= Vaux4_v_p;
Vaux5_1_V_N <= Vaux5_v_n;
Vaux5_1_V_P <= Vaux5_v_p;
Vaux6_1_V_N <= Vaux6_v_n;
Vaux6_1_V_P <= Vaux6_v_p;
Vaux7_1_V_N <= Vaux7_v_n;
Vaux7_1_V_P <= Vaux7_v_p;
Vaux9_1_V_N <= Vaux9_v_n;
Vaux9_1_V_P <= Vaux9_v_p;
Vp_Vn_1_V_N <= Vp_Vn_v_n;
Vp_Vn_1_V_P <= Vp_Vn_v_p;
axi_ethernetlite_0_MDIO_MDIO_I <= eth_mdio_mdc_mdio_i;
axi_ethernetlite_0_MII_COL <= eth_mii_col;
axi_ethernetlite_0_MII_CRS <= eth_mii_crs;
axi_ethernetlite_0_MII_RXD(3 downto 0) <= eth_mii_rxd(3 downto 0);
axi_ethernetlite_0_MII_RX_CLK <= eth_mii_rx_clk;
axi_ethernetlite_0_MII_RX_DV <= eth_mii_rx_dv;
axi_ethernetlite_0_MII_RX_ER <= eth_mii_rx_er;
axi_ethernetlite_0_MII_TX_CLK <= eth_mii_tx_clk;
axi_gpio_0_GPIO2_TRI_I(19 downto 0) <= shield_dp0_dp19_tri_i(19 downto 0);
axi_gpio_1_GPIO1_TRI_I(15 downto 0) <= shield_dp26_dp41_tri_i(15 downto 0);
axi_gpio_2_GPIO2_TRI_I(11 downto 0) <= rgb_led_tri_i(11 downto 0);
axi_gpio_2_GPIO_TRI_I(3 downto 0) <= led_4bits_tri_i(3 downto 0);
axi_gpio_pullup_GPIO_TRI_I(1 downto 0) <= i2c_pullups_tri_i(1 downto 0);
axi_gpio_sw_GPIO2_TRI_I(3 downto 0) <= push_buttons_4bits_tri_i(3 downto 0);
axi_gpio_sw_GPIO_TRI_I(3 downto 0) <= dip_switches_4bits_tri_i(3 downto 0);
axi_iic_0_IIC_SCL_I <= i2c_scl_i;
axi_iic_0_IIC_SDA_I <= i2c_sda_i;
axi_quad_spi_0_SPI_0_IO0_I <= spi_io0_i;
axi_quad_spi_0_SPI_0_IO1_I <= spi_io1_i;
axi_quad_spi_0_SPI_0_SCK_I <= spi_sck_i;
axi_quad_spi_0_SPI_0_SS_I <= spi_ss_i;
axi_quad_spi_1_SPI_0_IO0_I <= qspi_flash_io0_i;
axi_quad_spi_1_SPI_0_IO1_I <= qspi_flash_io1_i;
axi_quad_spi_1_SPI_0_IO2_I <= qspi_flash_io2_i;
axi_quad_spi_1_SPI_0_IO3_I <= qspi_flash_io3_i;
axi_quad_spi_1_SPI_0_SCK_I <= qspi_flash_sck_i;
axi_quad_spi_1_SPI_0_SS_I <= qspi_flash_ss_i;
axi_uartlite_0_UART_RxD <= usb_uart_rxd;
eth_mdio_mdc_mdc <= axi_ethernetlite_0_MDIO_MDC;
eth_mdio_mdc_mdio_o <= axi_ethernetlite_0_MDIO_MDIO_O;
eth_mdio_mdc_mdio_t <= axi_ethernetlite_0_MDIO_MDIO_T;
eth_mii_rst_n <= axi_ethernetlite_0_MII_RST_N;
eth_mii_tx_en <= axi_ethernetlite_0_MII_TX_EN;
eth_mii_txd(3 downto 0) <= axi_ethernetlite_0_MII_TXD(3 downto 0);
eth_ref_clk <= clk_wiz_1_clk_out4;
i2c_pullups_tri_o(1 downto 0) <= axi_gpio_pullup_GPIO_TRI_O(1 downto 0);
i2c_pullups_tri_t(1 downto 0) <= axi_gpio_pullup_GPIO_TRI_T(1 downto 0);
i2c_scl_o <= axi_iic_0_IIC_SCL_O;
i2c_scl_t <= axi_iic_0_IIC_SCL_T;
i2c_sda_o <= axi_iic_0_IIC_SDA_O;
i2c_sda_t <= axi_iic_0_IIC_SDA_T;
led_4bits_tri_o(3 downto 0) <= axi_gpio_2_GPIO_TRI_O(3 downto 0);
led_4bits_tri_t(3 downto 0) <= axi_gpio_2_GPIO_TRI_T(3 downto 0);
qspi_flash_io0_o <= axi_quad_spi_1_SPI_0_IO0_O;
qspi_flash_io0_t <= axi_quad_spi_1_SPI_0_IO0_T;
qspi_flash_io1_o <= axi_quad_spi_1_SPI_0_IO1_O;
qspi_flash_io1_t <= axi_quad_spi_1_SPI_0_IO1_T;
qspi_flash_io2_o <= axi_quad_spi_1_SPI_0_IO2_O;
qspi_flash_io2_t <= axi_quad_spi_1_SPI_0_IO2_T;
qspi_flash_io3_o <= axi_quad_spi_1_SPI_0_IO3_O;
qspi_flash_io3_t <= axi_quad_spi_1_SPI_0_IO3_T;
qspi_flash_sck_o <= axi_quad_spi_1_SPI_0_SCK_O;
qspi_flash_sck_t <= axi_quad_spi_1_SPI_0_SCK_T;
qspi_flash_ss_o <= axi_quad_spi_1_SPI_0_SS_O(0);
qspi_flash_ss_t <= axi_quad_spi_1_SPI_0_SS_T;
reset_1 <= reset;
rgb_led_tri_o(11 downto 0) <= axi_gpio_2_GPIO2_TRI_O(11 downto 0);
rgb_led_tri_t(11 downto 0) <= axi_gpio_2_GPIO2_TRI_T(11 downto 0);
shield_dp0_dp19_tri_o(19 downto 0) <= axi_gpio_0_GPIO2_TRI_O(19 downto 0);
shield_dp0_dp19_tri_t(19 downto 0) <= axi_gpio_0_GPIO2_TRI_T(19 downto 0);
shield_dp26_dp41_tri_o(15 downto 0) <= axi_gpio_1_GPIO1_TRI_O(15 downto 0);
shield_dp26_dp41_tri_t(15 downto 0) <= axi_gpio_1_GPIO1_TRI_T(15 downto 0);
spi_io0_o <= axi_quad_spi_0_SPI_0_IO0_O;
spi_io0_t <= axi_quad_spi_0_SPI_0_IO0_T;
spi_io1_o <= axi_quad_spi_0_SPI_0_IO1_O;
spi_io1_t <= axi_quad_spi_0_SPI_0_IO1_T;
spi_sck_o <= axi_quad_spi_0_SPI_0_SCK_O;
spi_sck_t <= axi_quad_spi_0_SPI_0_SCK_T;
spi_ss_o <= axi_quad_spi_0_SPI_0_SS_O(0);
spi_ss_t <= axi_quad_spi_0_SPI_0_SS_T;
sys_clock_1 <= sys_clock;
usb_uart_txd <= axi_uartlite_0_UART_TxD;
axi_ethernetlite_0: component system_axi_ethernetlite_0_0
port map (
ip2intc_irpt => axi_ethernetlite_0_ip2intc_irpt,
phy_col => axi_ethernetlite_0_MII_COL,
phy_crs => axi_ethernetlite_0_MII_CRS,
phy_dv => axi_ethernetlite_0_MII_RX_DV,
phy_mdc => axi_ethernetlite_0_MDIO_MDC,
phy_mdio_i => axi_ethernetlite_0_MDIO_MDIO_I,
phy_mdio_o => axi_ethernetlite_0_MDIO_MDIO_O,
phy_mdio_t => axi_ethernetlite_0_MDIO_MDIO_T,
phy_rst_n => axi_ethernetlite_0_MII_RST_N,
phy_rx_clk => axi_ethernetlite_0_MII_RX_CLK,
phy_rx_data(3 downto 0) => axi_ethernetlite_0_MII_RXD(3 downto 0),
phy_rx_er => axi_ethernetlite_0_MII_RX_ER,
phy_tx_clk => axi_ethernetlite_0_MII_TX_CLK,
phy_tx_data(3 downto 0) => axi_ethernetlite_0_MII_TXD(3 downto 0),
phy_tx_en => axi_ethernetlite_0_MII_TX_EN,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(12 downto 0) => microblaze_0_axi_periph_M01_AXI_ARADDR(12 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M01_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M01_AXI_ARVALID(0),
s_axi_awaddr(12 downto 0) => microblaze_0_axi_periph_M01_AXI_AWADDR(12 downto 0),
s_axi_awready => microblaze_0_axi_periph_M01_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M01_AXI_AWVALID(0),
s_axi_bready => microblaze_0_axi_periph_M01_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M01_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M01_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M01_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M01_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M01_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M01_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M01_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M01_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M01_AXI_WVALID(0)
);
axi_gpio_0: component system_axi_gpio_0_0
port map (
gpio_io_i(19 downto 0) => axi_gpio_0_GPIO2_TRI_I(19 downto 0),
gpio_io_o(19 downto 0) => axi_gpio_0_GPIO2_TRI_O(19 downto 0),
gpio_io_t(19 downto 0) => axi_gpio_0_GPIO2_TRI_T(19 downto 0),
ip2intc_irpt => NLW_axi_gpio_0_ip2intc_irpt_UNCONNECTED,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(8 downto 0) => microblaze_0_axi_periph_M11_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M11_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M11_AXI_ARVALID(0),
s_axi_awaddr(8 downto 0) => microblaze_0_axi_periph_M11_AXI_AWADDR(8 downto 0),
s_axi_awready => microblaze_0_axi_periph_M11_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M11_AXI_AWVALID(0),
s_axi_bready => microblaze_0_axi_periph_M11_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M11_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M11_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M11_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M11_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M11_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M11_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M11_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M11_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M11_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M11_AXI_WVALID(0)
);
axi_gpio_1: component system_axi_gpio_1_0
port map (
gpio_io_i(15 downto 0) => axi_gpio_1_GPIO1_TRI_I(15 downto 0),
gpio_io_o(15 downto 0) => axi_gpio_1_GPIO1_TRI_O(15 downto 0),
gpio_io_t(15 downto 0) => axi_gpio_1_GPIO1_TRI_T(15 downto 0),
ip2intc_irpt => NLW_axi_gpio_1_ip2intc_irpt_UNCONNECTED,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(8 downto 0) => microblaze_0_axi_periph_M12_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M12_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M12_AXI_ARVALID(0),
s_axi_awaddr(8 downto 0) => microblaze_0_axi_periph_M12_AXI_AWADDR(8 downto 0),
s_axi_awready => microblaze_0_axi_periph_M12_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M12_AXI_AWVALID(0),
s_axi_bready => microblaze_0_axi_periph_M12_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M12_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M12_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M12_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M12_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M12_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M12_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M12_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M12_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M12_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M12_AXI_WVALID(0)
);
axi_gpio_led: component system_axi_gpio_led_0
port map (
gpio2_io_i(11 downto 0) => axi_gpio_2_GPIO2_TRI_I(11 downto 0),
gpio2_io_o(11 downto 0) => axi_gpio_2_GPIO2_TRI_O(11 downto 0),
gpio2_io_t(11 downto 0) => axi_gpio_2_GPIO2_TRI_T(11 downto 0),
gpio_io_i(3 downto 0) => axi_gpio_2_GPIO_TRI_I(3 downto 0),
gpio_io_o(3 downto 0) => axi_gpio_2_GPIO_TRI_O(3 downto 0),
gpio_io_t(3 downto 0) => axi_gpio_2_GPIO_TRI_T(3 downto 0),
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(8 downto 0) => microblaze_0_axi_periph_M08_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M08_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M08_AXI_ARVALID(0),
s_axi_awaddr(8 downto 0) => microblaze_0_axi_periph_M08_AXI_AWADDR(8 downto 0),
s_axi_awready => microblaze_0_axi_periph_M08_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M08_AXI_AWVALID(0),
s_axi_bready => microblaze_0_axi_periph_M08_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M08_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M08_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M08_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M08_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M08_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M08_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M08_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M08_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M08_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M08_AXI_WVALID(0)
);
axi_gpio_pullup: component system_axi_gpio_pullup_0
port map (
gpio_io_i(1 downto 0) => axi_gpio_pullup_GPIO_TRI_I(1 downto 0),
gpio_io_o(1 downto 0) => axi_gpio_pullup_GPIO_TRI_O(1 downto 0),
gpio_io_t(1 downto 0) => axi_gpio_pullup_GPIO_TRI_T(1 downto 0),
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(8 downto 0) => microblaze_0_axi_periph_M09_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M09_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M09_AXI_ARVALID(0),
s_axi_awaddr(8 downto 0) => microblaze_0_axi_periph_M09_AXI_AWADDR(8 downto 0),
s_axi_awready => microblaze_0_axi_periph_M09_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M09_AXI_AWVALID(0),
s_axi_bready => microblaze_0_axi_periph_M09_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M09_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M09_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M09_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M09_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M09_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M09_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M09_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M09_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M09_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M09_AXI_WVALID(0)
);
axi_gpio_sw: component system_axi_gpio_sw_0
port map (
gpio2_io_i(3 downto 0) => axi_gpio_sw_GPIO2_TRI_I(3 downto 0),
gpio_io_i(3 downto 0) => axi_gpio_sw_GPIO_TRI_I(3 downto 0),
ip2intc_irpt => axi_gpio_sw_ip2intc_irpt,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(8 downto 0) => microblaze_0_axi_periph_M07_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M07_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M07_AXI_ARVALID(0),
s_axi_awaddr(8 downto 0) => microblaze_0_axi_periph_M07_AXI_AWADDR(8 downto 0),
s_axi_awready => microblaze_0_axi_periph_M07_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M07_AXI_AWVALID(0),
s_axi_bready => microblaze_0_axi_periph_M07_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M07_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M07_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M07_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M07_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M07_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M07_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M07_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M07_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M07_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M07_AXI_WVALID(0)
);
axi_iic_0: component system_axi_iic_0_0
port map (
gpo(0) => NLW_axi_iic_0_gpo_UNCONNECTED(0),
iic2intc_irpt => axi_iic_0_iic2intc_irpt,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(8 downto 0) => microblaze_0_axi_periph_M06_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M06_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M06_AXI_ARVALID(0),
s_axi_awaddr(8 downto 0) => microblaze_0_axi_periph_M06_AXI_AWADDR(8 downto 0),
s_axi_awready => microblaze_0_axi_periph_M06_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M06_AXI_AWVALID(0),
s_axi_bready => microblaze_0_axi_periph_M06_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M06_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M06_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M06_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M06_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M06_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M06_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M06_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M06_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M06_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M06_AXI_WVALID(0),
scl_i => axi_iic_0_IIC_SCL_I,
scl_o => axi_iic_0_IIC_SCL_O,
scl_t => axi_iic_0_IIC_SCL_T,
sda_i => axi_iic_0_IIC_SDA_I,
sda_o => axi_iic_0_IIC_SDA_O,
sda_t => axi_iic_0_IIC_SDA_T
);
axi_mem_intercon: entity work.system_axi_mem_intercon_0
port map (
ACLK => microblaze_0_Clk,
ARESETN => rst_clk_wiz_1_100M_interconnect_aresetn(0),
M00_ACLK => mig_7series_0_ui_clk,
M00_ARESETN => rst_mig_7series_0_83M_peripheral_aresetn(0),
M00_AXI_araddr(27 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(27 downto 0),
M00_AXI_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
M00_AXI_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
M00_AXI_arid(0) => axi_mem_intercon_M00_AXI_ARID(0),
M00_AXI_arlen(7 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(7 downto 0),
M00_AXI_arlock => axi_mem_intercon_M00_AXI_ARLOCK,
M00_AXI_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arqos(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0),
M00_AXI_arready => axi_mem_intercon_M00_AXI_ARREADY,
M00_AXI_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
M00_AXI_arvalid => axi_mem_intercon_M00_AXI_ARVALID,
M00_AXI_awaddr(27 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(27 downto 0),
M00_AXI_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
M00_AXI_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
M00_AXI_awid(0) => axi_mem_intercon_M00_AXI_AWID(0),
M00_AXI_awlen(7 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(7 downto 0),
M00_AXI_awlock => axi_mem_intercon_M00_AXI_AWLOCK,
M00_AXI_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awqos(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0),
M00_AXI_awready => axi_mem_intercon_M00_AXI_AWREADY,
M00_AXI_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
M00_AXI_awvalid => axi_mem_intercon_M00_AXI_AWVALID,
M00_AXI_bid(0) => axi_mem_intercon_M00_AXI_BID(0),
M00_AXI_bready => axi_mem_intercon_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => axi_mem_intercon_M00_AXI_BVALID,
M00_AXI_rdata(127 downto 0) => axi_mem_intercon_M00_AXI_RDATA(127 downto 0),
M00_AXI_rid(0) => axi_mem_intercon_M00_AXI_RID(0),
M00_AXI_rlast => axi_mem_intercon_M00_AXI_RLAST,
M00_AXI_rready => axi_mem_intercon_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_mem_intercon_M00_AXI_RVALID,
M00_AXI_wdata(127 downto 0) => axi_mem_intercon_M00_AXI_WDATA(127 downto 0),
M00_AXI_wlast => axi_mem_intercon_M00_AXI_WLAST,
M00_AXI_wready => axi_mem_intercon_M00_AXI_WREADY,
M00_AXI_wstrb(15 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(15 downto 0),
M00_AXI_wvalid => axi_mem_intercon_M00_AXI_WVALID,
S00_ACLK => microblaze_0_Clk,
S00_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => microblaze_0_M_AXI_DC_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => microblaze_0_M_AXI_DC_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => microblaze_0_M_AXI_DC_ARCACHE(3 downto 0),
S00_AXI_arlen(7 downto 0) => microblaze_0_M_AXI_DC_ARLEN(7 downto 0),
S00_AXI_arlock => microblaze_0_M_AXI_DC_ARLOCK,
S00_AXI_arprot(2 downto 0) => microblaze_0_M_AXI_DC_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => microblaze_0_M_AXI_DC_ARQOS(3 downto 0),
S00_AXI_arready => microblaze_0_M_AXI_DC_ARREADY,
S00_AXI_arsize(2 downto 0) => microblaze_0_M_AXI_DC_ARSIZE(2 downto 0),
S00_AXI_arvalid => microblaze_0_M_AXI_DC_ARVALID,
S00_AXI_awaddr(31 downto 0) => microblaze_0_M_AXI_DC_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => microblaze_0_M_AXI_DC_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => microblaze_0_M_AXI_DC_AWCACHE(3 downto 0),
S00_AXI_awlen(7 downto 0) => microblaze_0_M_AXI_DC_AWLEN(7 downto 0),
S00_AXI_awlock => microblaze_0_M_AXI_DC_AWLOCK,
S00_AXI_awprot(2 downto 0) => microblaze_0_M_AXI_DC_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => microblaze_0_M_AXI_DC_AWQOS(3 downto 0),
S00_AXI_awready => microblaze_0_M_AXI_DC_AWREADY,
S00_AXI_awsize(2 downto 0) => microblaze_0_M_AXI_DC_AWSIZE(2 downto 0),
S00_AXI_awvalid => microblaze_0_M_AXI_DC_AWVALID,
S00_AXI_bready => microblaze_0_M_AXI_DC_BREADY,
S00_AXI_bresp(1 downto 0) => microblaze_0_M_AXI_DC_BRESP(1 downto 0),
S00_AXI_bvalid => microblaze_0_M_AXI_DC_BVALID,
S00_AXI_rdata(31 downto 0) => microblaze_0_M_AXI_DC_RDATA(31 downto 0),
S00_AXI_rlast => microblaze_0_M_AXI_DC_RLAST,
S00_AXI_rready => microblaze_0_M_AXI_DC_RREADY,
S00_AXI_rresp(1 downto 0) => microblaze_0_M_AXI_DC_RRESP(1 downto 0),
S00_AXI_rvalid => microblaze_0_M_AXI_DC_RVALID,
S00_AXI_wdata(31 downto 0) => microblaze_0_M_AXI_DC_WDATA(31 downto 0),
S00_AXI_wlast => microblaze_0_M_AXI_DC_WLAST,
S00_AXI_wready => microblaze_0_M_AXI_DC_WREADY,
S00_AXI_wstrb(3 downto 0) => microblaze_0_M_AXI_DC_WSTRB(3 downto 0),
S00_AXI_wvalid => microblaze_0_M_AXI_DC_WVALID,
S01_ACLK => microblaze_0_Clk,
S01_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
S01_AXI_araddr(31 downto 0) => microblaze_0_M_AXI_IC_ARADDR(31 downto 0),
S01_AXI_arburst(1 downto 0) => microblaze_0_M_AXI_IC_ARBURST(1 downto 0),
S01_AXI_arcache(3 downto 0) => microblaze_0_M_AXI_IC_ARCACHE(3 downto 0),
S01_AXI_arlen(7 downto 0) => microblaze_0_M_AXI_IC_ARLEN(7 downto 0),
S01_AXI_arlock => microblaze_0_M_AXI_IC_ARLOCK,
S01_AXI_arprot(2 downto 0) => microblaze_0_M_AXI_IC_ARPROT(2 downto 0),
S01_AXI_arqos(3 downto 0) => microblaze_0_M_AXI_IC_ARQOS(3 downto 0),
S01_AXI_arready => microblaze_0_M_AXI_IC_ARREADY,
S01_AXI_arsize(2 downto 0) => microblaze_0_M_AXI_IC_ARSIZE(2 downto 0),
S01_AXI_arvalid => microblaze_0_M_AXI_IC_ARVALID,
S01_AXI_rdata(31 downto 0) => microblaze_0_M_AXI_IC_RDATA(31 downto 0),
S01_AXI_rlast => microblaze_0_M_AXI_IC_RLAST,
S01_AXI_rready => microblaze_0_M_AXI_IC_RREADY,
S01_AXI_rresp(1 downto 0) => microblaze_0_M_AXI_IC_RRESP(1 downto 0),
S01_AXI_rvalid => microblaze_0_M_AXI_IC_RVALID
);
axi_quad_spi_flash: component system_axi_quad_spi_flash_0
port map (
ext_spi_clk => microblaze_0_Clk,
io0_i => axi_quad_spi_1_SPI_0_IO0_I,
io0_o => axi_quad_spi_1_SPI_0_IO0_O,
io0_t => axi_quad_spi_1_SPI_0_IO0_T,
io1_i => axi_quad_spi_1_SPI_0_IO1_I,
io1_o => axi_quad_spi_1_SPI_0_IO1_O,
io1_t => axi_quad_spi_1_SPI_0_IO1_T,
io2_i => axi_quad_spi_1_SPI_0_IO2_I,
io2_o => axi_quad_spi_1_SPI_0_IO2_O,
io2_t => axi_quad_spi_1_SPI_0_IO2_T,
io3_i => axi_quad_spi_1_SPI_0_IO3_I,
io3_o => axi_quad_spi_1_SPI_0_IO3_O,
io3_t => axi_quad_spi_1_SPI_0_IO3_T,
ip2intc_irpt => axi_quad_spi_flash_ip2intc_irpt,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(6 downto 0) => microblaze_0_axi_periph_M05_AXI_ARADDR(6 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M05_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M05_AXI_ARVALID(0),
s_axi_awaddr(6 downto 0) => microblaze_0_axi_periph_M05_AXI_AWADDR(6 downto 0),
s_axi_awready => microblaze_0_axi_periph_M05_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M05_AXI_AWVALID(0),
s_axi_bready => microblaze_0_axi_periph_M05_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M05_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M05_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M05_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M05_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M05_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M05_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M05_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M05_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M05_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M05_AXI_WVALID(0),
sck_i => axi_quad_spi_1_SPI_0_SCK_I,
sck_o => axi_quad_spi_1_SPI_0_SCK_O,
sck_t => axi_quad_spi_1_SPI_0_SCK_T,
ss_i(0) => axi_quad_spi_1_SPI_0_SS_I,
ss_o(0) => axi_quad_spi_1_SPI_0_SS_O(0),
ss_t => axi_quad_spi_1_SPI_0_SS_T
);
axi_quad_spi_shield: component system_axi_quad_spi_shield_0
port map (
ext_spi_clk => microblaze_0_Clk,
io0_i => axi_quad_spi_0_SPI_0_IO0_I,
io0_o => axi_quad_spi_0_SPI_0_IO0_O,
io0_t => axi_quad_spi_0_SPI_0_IO0_T,
io1_i => axi_quad_spi_0_SPI_0_IO1_I,
io1_o => axi_quad_spi_0_SPI_0_IO1_O,
io1_t => axi_quad_spi_0_SPI_0_IO1_T,
ip2intc_irpt => axi_quad_spi_shield_ip2intc_irpt,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(6 downto 0) => microblaze_0_axi_periph_M04_AXI_ARADDR(6 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M04_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M04_AXI_ARVALID(0),
s_axi_awaddr(6 downto 0) => microblaze_0_axi_periph_M04_AXI_AWADDR(6 downto 0),
s_axi_awready => microblaze_0_axi_periph_M04_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M04_AXI_AWVALID(0),
s_axi_bready => microblaze_0_axi_periph_M04_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M04_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M04_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M04_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M04_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M04_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M04_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M04_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M04_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M04_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M04_AXI_WVALID(0),
sck_i => axi_quad_spi_0_SPI_0_SCK_I,
sck_o => axi_quad_spi_0_SPI_0_SCK_O,
sck_t => axi_quad_spi_0_SPI_0_SCK_T,
ss_i(0) => axi_quad_spi_0_SPI_0_SS_I,
ss_o(0) => axi_quad_spi_0_SPI_0_SS_O(0),
ss_t => axi_quad_spi_0_SPI_0_SS_T
);
axi_timer_0: component system_axi_timer_0_0
port map (
capturetrig0 => '0',
capturetrig1 => '0',
freeze => '0',
generateout0 => NLW_axi_timer_0_generateout0_UNCONNECTED,
generateout1 => NLW_axi_timer_0_generateout1_UNCONNECTED,
interrupt => axi_timer_0_interrupt,
pwm0 => NLW_axi_timer_0_pwm0_UNCONNECTED,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(4 downto 0) => microblaze_0_axi_periph_M02_AXI_ARADDR(4 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M02_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M02_AXI_ARVALID(0),
s_axi_awaddr(4 downto 0) => microblaze_0_axi_periph_M02_AXI_AWADDR(4 downto 0),
s_axi_awready => microblaze_0_axi_periph_M02_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M02_AXI_AWVALID(0),
s_axi_bready => microblaze_0_axi_periph_M02_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M02_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M02_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M02_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M02_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M02_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M02_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M02_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M02_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M02_AXI_WVALID(0)
);
axi_uartlite_0: component system_axi_uartlite_0_0
port map (
interrupt => NLW_axi_uartlite_0_interrupt_UNCONNECTED,
rx => axi_uartlite_0_UART_RxD,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(3 downto 0) => microblaze_0_axi_periph_M03_AXI_ARADDR(3 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M03_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M03_AXI_ARVALID(0),
s_axi_awaddr(3 downto 0) => microblaze_0_axi_periph_M03_AXI_AWADDR(3 downto 0),
s_axi_awready => microblaze_0_axi_periph_M03_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M03_AXI_AWVALID(0),
s_axi_bready => microblaze_0_axi_periph_M03_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M03_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M03_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M03_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M03_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M03_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M03_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M03_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M03_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M03_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M03_AXI_WVALID(0),
tx => axi_uartlite_0_UART_TxD
);
clk_wiz_1: component system_clk_wiz_1_0
port map (
clk_in1 => sys_clock_1,
clk_out1 => microblaze_0_Clk,
clk_out2 => clk_wiz_1_clk_out2,
clk_out3 => clk_wiz_1_clk_out3,
clk_out4 => clk_wiz_1_clk_out4,
locked => clk_wiz_1_locked,
resetn => reset_1
);
mdm_1: component system_mdm_1_0
port map (
Dbg_Capture_0 => microblaze_0_debug_CAPTURE,
Dbg_Clk_0 => microblaze_0_debug_CLK,
Dbg_Disable_0 => microblaze_0_debug_DISABLE,
Dbg_Reg_En_0(0 to 7) => microblaze_0_debug_REG_EN(0 to 7),
Dbg_Rst_0 => microblaze_0_debug_RST,
Dbg_Shift_0 => microblaze_0_debug_SHIFT,
Dbg_TDI_0 => microblaze_0_debug_TDI,
Dbg_TDO_0 => microblaze_0_debug_TDO,
Dbg_Update_0 => microblaze_0_debug_UPDATE,
Debug_SYS_Rst => mdm_1_debug_sys_rst
);
microblaze_0: component system_microblaze_0_0
port map (
Byte_Enable(0 to 3) => microblaze_0_dlmb_1_BE(0 to 3),
Clk => microblaze_0_Clk,
DCE => microblaze_0_dlmb_1_CE,
DReady => microblaze_0_dlmb_1_READY,
DUE => microblaze_0_dlmb_1_UE,
DWait => microblaze_0_dlmb_1_WAIT,
D_AS => microblaze_0_dlmb_1_ADDRSTROBE,
Data_Addr(0 to 31) => microblaze_0_dlmb_1_ABUS(0 to 31),
Data_Read(0 to 31) => microblaze_0_dlmb_1_READDBUS(0 to 31),
Data_Write(0 to 31) => microblaze_0_dlmb_1_WRITEDBUS(0 to 31),
Dbg_Capture => microblaze_0_debug_CAPTURE,
Dbg_Clk => microblaze_0_debug_CLK,
Dbg_Disable => microblaze_0_debug_DISABLE,
Dbg_Reg_En(0 to 7) => microblaze_0_debug_REG_EN(0 to 7),
Dbg_Shift => microblaze_0_debug_SHIFT,
Dbg_TDI => microblaze_0_debug_TDI,
Dbg_TDO => microblaze_0_debug_TDO,
Dbg_Update => microblaze_0_debug_UPDATE,
Debug_Rst => microblaze_0_debug_RST,
ICE => microblaze_0_ilmb_1_CE,
IFetch => microblaze_0_ilmb_1_READSTROBE,
IReady => microblaze_0_ilmb_1_READY,
IUE => microblaze_0_ilmb_1_UE,
IWAIT => microblaze_0_ilmb_1_WAIT,
I_AS => microblaze_0_ilmb_1_ADDRSTROBE,
Instr(0 to 31) => microblaze_0_ilmb_1_READDBUS(0 to 31),
Instr_Addr(0 to 31) => microblaze_0_ilmb_1_ABUS(0 to 31),
Interrupt => microblaze_0_interrupt_INTERRUPT,
Interrupt_Ack(0 to 1) => microblaze_0_interrupt_ACK(0 to 1),
Interrupt_Address(0) => microblaze_0_interrupt_ADDRESS(31),
Interrupt_Address(1) => microblaze_0_interrupt_ADDRESS(30),
Interrupt_Address(2) => microblaze_0_interrupt_ADDRESS(29),
Interrupt_Address(3) => microblaze_0_interrupt_ADDRESS(28),
Interrupt_Address(4) => microblaze_0_interrupt_ADDRESS(27),
Interrupt_Address(5) => microblaze_0_interrupt_ADDRESS(26),
Interrupt_Address(6) => microblaze_0_interrupt_ADDRESS(25),
Interrupt_Address(7) => microblaze_0_interrupt_ADDRESS(24),
Interrupt_Address(8) => microblaze_0_interrupt_ADDRESS(23),
Interrupt_Address(9) => microblaze_0_interrupt_ADDRESS(22),
Interrupt_Address(10) => microblaze_0_interrupt_ADDRESS(21),
Interrupt_Address(11) => microblaze_0_interrupt_ADDRESS(20),
Interrupt_Address(12) => microblaze_0_interrupt_ADDRESS(19),
Interrupt_Address(13) => microblaze_0_interrupt_ADDRESS(18),
Interrupt_Address(14) => microblaze_0_interrupt_ADDRESS(17),
Interrupt_Address(15) => microblaze_0_interrupt_ADDRESS(16),
Interrupt_Address(16) => microblaze_0_interrupt_ADDRESS(15),
Interrupt_Address(17) => microblaze_0_interrupt_ADDRESS(14),
Interrupt_Address(18) => microblaze_0_interrupt_ADDRESS(13),
Interrupt_Address(19) => microblaze_0_interrupt_ADDRESS(12),
Interrupt_Address(20) => microblaze_0_interrupt_ADDRESS(11),
Interrupt_Address(21) => microblaze_0_interrupt_ADDRESS(10),
Interrupt_Address(22) => microblaze_0_interrupt_ADDRESS(9),
Interrupt_Address(23) => microblaze_0_interrupt_ADDRESS(8),
Interrupt_Address(24) => microblaze_0_interrupt_ADDRESS(7),
Interrupt_Address(25) => microblaze_0_interrupt_ADDRESS(6),
Interrupt_Address(26) => microblaze_0_interrupt_ADDRESS(5),
Interrupt_Address(27) => microblaze_0_interrupt_ADDRESS(4),
Interrupt_Address(28) => microblaze_0_interrupt_ADDRESS(3),
Interrupt_Address(29) => microblaze_0_interrupt_ADDRESS(2),
Interrupt_Address(30) => microblaze_0_interrupt_ADDRESS(1),
Interrupt_Address(31) => microblaze_0_interrupt_ADDRESS(0),
M_AXI_DC_ARADDR(31 downto 0) => microblaze_0_M_AXI_DC_ARADDR(31 downto 0),
M_AXI_DC_ARBURST(1 downto 0) => microblaze_0_M_AXI_DC_ARBURST(1 downto 0),
M_AXI_DC_ARCACHE(3 downto 0) => microblaze_0_M_AXI_DC_ARCACHE(3 downto 0),
M_AXI_DC_ARID(0) => NLW_microblaze_0_M_AXI_DC_ARID_UNCONNECTED(0),
M_AXI_DC_ARLEN(7 downto 0) => microblaze_0_M_AXI_DC_ARLEN(7 downto 0),
M_AXI_DC_ARLOCK => microblaze_0_M_AXI_DC_ARLOCK,
M_AXI_DC_ARPROT(2 downto 0) => microblaze_0_M_AXI_DC_ARPROT(2 downto 0),
M_AXI_DC_ARQOS(3 downto 0) => microblaze_0_M_AXI_DC_ARQOS(3 downto 0),
M_AXI_DC_ARREADY => microblaze_0_M_AXI_DC_ARREADY,
M_AXI_DC_ARSIZE(2 downto 0) => microblaze_0_M_AXI_DC_ARSIZE(2 downto 0),
M_AXI_DC_ARVALID => microblaze_0_M_AXI_DC_ARVALID,
M_AXI_DC_AWADDR(31 downto 0) => microblaze_0_M_AXI_DC_AWADDR(31 downto 0),
M_AXI_DC_AWBURST(1 downto 0) => microblaze_0_M_AXI_DC_AWBURST(1 downto 0),
M_AXI_DC_AWCACHE(3 downto 0) => microblaze_0_M_AXI_DC_AWCACHE(3 downto 0),
M_AXI_DC_AWID(0) => NLW_microblaze_0_M_AXI_DC_AWID_UNCONNECTED(0),
M_AXI_DC_AWLEN(7 downto 0) => microblaze_0_M_AXI_DC_AWLEN(7 downto 0),
M_AXI_DC_AWLOCK => microblaze_0_M_AXI_DC_AWLOCK,
M_AXI_DC_AWPROT(2 downto 0) => microblaze_0_M_AXI_DC_AWPROT(2 downto 0),
M_AXI_DC_AWQOS(3 downto 0) => microblaze_0_M_AXI_DC_AWQOS(3 downto 0),
M_AXI_DC_AWREADY => microblaze_0_M_AXI_DC_AWREADY,
M_AXI_DC_AWSIZE(2 downto 0) => microblaze_0_M_AXI_DC_AWSIZE(2 downto 0),
M_AXI_DC_AWVALID => microblaze_0_M_AXI_DC_AWVALID,
M_AXI_DC_BID(0) => '0',
M_AXI_DC_BREADY => microblaze_0_M_AXI_DC_BREADY,
M_AXI_DC_BRESP(1 downto 0) => microblaze_0_M_AXI_DC_BRESP(1 downto 0),
M_AXI_DC_BVALID => microblaze_0_M_AXI_DC_BVALID,
M_AXI_DC_RDATA(31 downto 0) => microblaze_0_M_AXI_DC_RDATA(31 downto 0),
M_AXI_DC_RID(0) => '0',
M_AXI_DC_RLAST => microblaze_0_M_AXI_DC_RLAST,
M_AXI_DC_RREADY => microblaze_0_M_AXI_DC_RREADY,
M_AXI_DC_RRESP(1 downto 0) => microblaze_0_M_AXI_DC_RRESP(1 downto 0),
M_AXI_DC_RVALID => microblaze_0_M_AXI_DC_RVALID,
M_AXI_DC_WDATA(31 downto 0) => microblaze_0_M_AXI_DC_WDATA(31 downto 0),
M_AXI_DC_WLAST => microblaze_0_M_AXI_DC_WLAST,
M_AXI_DC_WREADY => microblaze_0_M_AXI_DC_WREADY,
M_AXI_DC_WSTRB(3 downto 0) => microblaze_0_M_AXI_DC_WSTRB(3 downto 0),
M_AXI_DC_WVALID => microblaze_0_M_AXI_DC_WVALID,
M_AXI_DP_ARADDR(31 downto 0) => microblaze_0_axi_dp_ARADDR(31 downto 0),
M_AXI_DP_ARPROT(2 downto 0) => microblaze_0_axi_dp_ARPROT(2 downto 0),
M_AXI_DP_ARREADY => microblaze_0_axi_dp_ARREADY(0),
M_AXI_DP_ARVALID => microblaze_0_axi_dp_ARVALID,
M_AXI_DP_AWADDR(31 downto 0) => microblaze_0_axi_dp_AWADDR(31 downto 0),
M_AXI_DP_AWPROT(2 downto 0) => microblaze_0_axi_dp_AWPROT(2 downto 0),
M_AXI_DP_AWREADY => microblaze_0_axi_dp_AWREADY(0),
M_AXI_DP_AWVALID => microblaze_0_axi_dp_AWVALID,
M_AXI_DP_BREADY => microblaze_0_axi_dp_BREADY,
M_AXI_DP_BRESP(1 downto 0) => microblaze_0_axi_dp_BRESP(1 downto 0),
M_AXI_DP_BVALID => microblaze_0_axi_dp_BVALID(0),
M_AXI_DP_RDATA(31 downto 0) => microblaze_0_axi_dp_RDATA(31 downto 0),
M_AXI_DP_RREADY => microblaze_0_axi_dp_RREADY,
M_AXI_DP_RRESP(1 downto 0) => microblaze_0_axi_dp_RRESP(1 downto 0),
M_AXI_DP_RVALID => microblaze_0_axi_dp_RVALID(0),
M_AXI_DP_WDATA(31 downto 0) => microblaze_0_axi_dp_WDATA(31 downto 0),
M_AXI_DP_WREADY => microblaze_0_axi_dp_WREADY(0),
M_AXI_DP_WSTRB(3 downto 0) => microblaze_0_axi_dp_WSTRB(3 downto 0),
M_AXI_DP_WVALID => microblaze_0_axi_dp_WVALID,
M_AXI_IC_ARADDR(31 downto 0) => microblaze_0_M_AXI_IC_ARADDR(31 downto 0),
M_AXI_IC_ARBURST(1 downto 0) => microblaze_0_M_AXI_IC_ARBURST(1 downto 0),
M_AXI_IC_ARCACHE(3 downto 0) => microblaze_0_M_AXI_IC_ARCACHE(3 downto 0),
M_AXI_IC_ARID(0) => NLW_microblaze_0_M_AXI_IC_ARID_UNCONNECTED(0),
M_AXI_IC_ARLEN(7 downto 0) => microblaze_0_M_AXI_IC_ARLEN(7 downto 0),
M_AXI_IC_ARLOCK => microblaze_0_M_AXI_IC_ARLOCK,
M_AXI_IC_ARPROT(2 downto 0) => microblaze_0_M_AXI_IC_ARPROT(2 downto 0),
M_AXI_IC_ARQOS(3 downto 0) => microblaze_0_M_AXI_IC_ARQOS(3 downto 0),
M_AXI_IC_ARREADY => microblaze_0_M_AXI_IC_ARREADY,
M_AXI_IC_ARSIZE(2 downto 0) => microblaze_0_M_AXI_IC_ARSIZE(2 downto 0),
M_AXI_IC_ARVALID => microblaze_0_M_AXI_IC_ARVALID,
M_AXI_IC_AWADDR(31 downto 0) => NLW_microblaze_0_M_AXI_IC_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_IC_AWBURST(1 downto 0) => NLW_microblaze_0_M_AXI_IC_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_IC_AWCACHE(3 downto 0) => NLW_microblaze_0_M_AXI_IC_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_IC_AWID(0) => NLW_microblaze_0_M_AXI_IC_AWID_UNCONNECTED(0),
M_AXI_IC_AWLEN(7 downto 0) => NLW_microblaze_0_M_AXI_IC_AWLEN_UNCONNECTED(7 downto 0),
M_AXI_IC_AWLOCK => NLW_microblaze_0_M_AXI_IC_AWLOCK_UNCONNECTED,
M_AXI_IC_AWPROT(2 downto 0) => NLW_microblaze_0_M_AXI_IC_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_IC_AWQOS(3 downto 0) => NLW_microblaze_0_M_AXI_IC_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_IC_AWREADY => '0',
M_AXI_IC_AWSIZE(2 downto 0) => NLW_microblaze_0_M_AXI_IC_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_IC_AWVALID => NLW_microblaze_0_M_AXI_IC_AWVALID_UNCONNECTED,
M_AXI_IC_BID(0) => '0',
M_AXI_IC_BREADY => NLW_microblaze_0_M_AXI_IC_BREADY_UNCONNECTED,
M_AXI_IC_BRESP(1 downto 0) => B"00",
M_AXI_IC_BVALID => '0',
M_AXI_IC_RDATA(31 downto 0) => microblaze_0_M_AXI_IC_RDATA(31 downto 0),
M_AXI_IC_RID(0) => '0',
M_AXI_IC_RLAST => microblaze_0_M_AXI_IC_RLAST,
M_AXI_IC_RREADY => microblaze_0_M_AXI_IC_RREADY,
M_AXI_IC_RRESP(1 downto 0) => microblaze_0_M_AXI_IC_RRESP(1 downto 0),
M_AXI_IC_RVALID => microblaze_0_M_AXI_IC_RVALID,
M_AXI_IC_WDATA(31 downto 0) => NLW_microblaze_0_M_AXI_IC_WDATA_UNCONNECTED(31 downto 0),
M_AXI_IC_WLAST => NLW_microblaze_0_M_AXI_IC_WLAST_UNCONNECTED,
M_AXI_IC_WREADY => '0',
M_AXI_IC_WSTRB(3 downto 0) => NLW_microblaze_0_M_AXI_IC_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_IC_WVALID => NLW_microblaze_0_M_AXI_IC_WVALID_UNCONNECTED,
Read_Strobe => microblaze_0_dlmb_1_READSTROBE,
Reset => rst_clk_wiz_1_100M_mb_reset,
Write_Strobe => microblaze_0_dlmb_1_WRITESTROBE
);
microblaze_0_axi_intc: component system_microblaze_0_axi_intc_0
port map (
interrupt_address(31 downto 0) => microblaze_0_interrupt_ADDRESS(31 downto 0),
intr(6 downto 0) => microblaze_0_intr(6 downto 0),
irq => microblaze_0_interrupt_INTERRUPT,
processor_ack(1) => microblaze_0_interrupt_ACK(0),
processor_ack(0) => microblaze_0_interrupt_ACK(1),
processor_clk => microblaze_0_Clk,
processor_rst => rst_clk_wiz_1_100M_mb_reset,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(8 downto 0) => microblaze_0_intc_axi_ARADDR(8 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_intc_axi_ARREADY,
s_axi_arvalid => microblaze_0_intc_axi_ARVALID(0),
s_axi_awaddr(8 downto 0) => microblaze_0_intc_axi_AWADDR(8 downto 0),
s_axi_awready => microblaze_0_intc_axi_AWREADY,
s_axi_awvalid => microblaze_0_intc_axi_AWVALID(0),
s_axi_bready => microblaze_0_intc_axi_BREADY(0),
s_axi_bresp(1 downto 0) => microblaze_0_intc_axi_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_intc_axi_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_intc_axi_RDATA(31 downto 0),
s_axi_rready => microblaze_0_intc_axi_RREADY(0),
s_axi_rresp(1 downto 0) => microblaze_0_intc_axi_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_intc_axi_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_intc_axi_WDATA(31 downto 0),
s_axi_wready => microblaze_0_intc_axi_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_intc_axi_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_intc_axi_WVALID(0)
);
microblaze_0_axi_periph: entity work.system_microblaze_0_axi_periph_0
port map (
ACLK => microblaze_0_Clk,
ARESETN => rst_clk_wiz_1_100M_interconnect_aresetn(0),
M00_ACLK => microblaze_0_Clk,
M00_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => microblaze_0_intc_axi_ARADDR(31 downto 0),
M00_AXI_arready(0) => microblaze_0_intc_axi_ARREADY,
M00_AXI_arvalid(0) => microblaze_0_intc_axi_ARVALID(0),
M00_AXI_awaddr(31 downto 0) => microblaze_0_intc_axi_AWADDR(31 downto 0),
M00_AXI_awready(0) => microblaze_0_intc_axi_AWREADY,
M00_AXI_awvalid(0) => microblaze_0_intc_axi_AWVALID(0),
M00_AXI_bready(0) => microblaze_0_intc_axi_BREADY(0),
M00_AXI_bresp(1 downto 0) => microblaze_0_intc_axi_BRESP(1 downto 0),
M00_AXI_bvalid(0) => microblaze_0_intc_axi_BVALID,
M00_AXI_rdata(31 downto 0) => microblaze_0_intc_axi_RDATA(31 downto 0),
M00_AXI_rready(0) => microblaze_0_intc_axi_RREADY(0),
M00_AXI_rresp(1 downto 0) => microblaze_0_intc_axi_RRESP(1 downto 0),
M00_AXI_rvalid(0) => microblaze_0_intc_axi_RVALID,
M00_AXI_wdata(31 downto 0) => microblaze_0_intc_axi_WDATA(31 downto 0),
M00_AXI_wready(0) => microblaze_0_intc_axi_WREADY,
M00_AXI_wstrb(3 downto 0) => microblaze_0_intc_axi_WSTRB(3 downto 0),
M00_AXI_wvalid(0) => microblaze_0_intc_axi_WVALID(0),
M01_ACLK => microblaze_0_Clk,
M01_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M01_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_M01_AXI_ARADDR(31 downto 0),
M01_AXI_arready(0) => microblaze_0_axi_periph_M01_AXI_ARREADY,
M01_AXI_arvalid(0) => microblaze_0_axi_periph_M01_AXI_ARVALID(0),
M01_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_M01_AXI_AWADDR(31 downto 0),
M01_AXI_awready(0) => microblaze_0_axi_periph_M01_AXI_AWREADY,
M01_AXI_awvalid(0) => microblaze_0_axi_periph_M01_AXI_AWVALID(0),
M01_AXI_bready(0) => microblaze_0_axi_periph_M01_AXI_BREADY(0),
M01_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid(0) => microblaze_0_axi_periph_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready(0) => microblaze_0_axi_periph_M01_AXI_RREADY(0),
M01_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid(0) => microblaze_0_axi_periph_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready(0) => microblaze_0_axi_periph_M01_AXI_WREADY,
M01_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
M01_AXI_wvalid(0) => microblaze_0_axi_periph_M01_AXI_WVALID(0),
M02_ACLK => microblaze_0_Clk,
M02_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M02_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_M02_AXI_ARADDR(31 downto 0),
M02_AXI_arready(0) => microblaze_0_axi_periph_M02_AXI_ARREADY,
M02_AXI_arvalid(0) => microblaze_0_axi_periph_M02_AXI_ARVALID(0),
M02_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_M02_AXI_AWADDR(31 downto 0),
M02_AXI_awready(0) => microblaze_0_axi_periph_M02_AXI_AWREADY,
M02_AXI_awvalid(0) => microblaze_0_axi_periph_M02_AXI_AWVALID(0),
M02_AXI_bready(0) => microblaze_0_axi_periph_M02_AXI_BREADY(0),
M02_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M02_AXI_BRESP(1 downto 0),
M02_AXI_bvalid(0) => microblaze_0_axi_periph_M02_AXI_BVALID,
M02_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M02_AXI_RDATA(31 downto 0),
M02_AXI_rready(0) => microblaze_0_axi_periph_M02_AXI_RREADY(0),
M02_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M02_AXI_RRESP(1 downto 0),
M02_AXI_rvalid(0) => microblaze_0_axi_periph_M02_AXI_RVALID,
M02_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M02_AXI_WDATA(31 downto 0),
M02_AXI_wready(0) => microblaze_0_axi_periph_M02_AXI_WREADY,
M02_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
M02_AXI_wvalid(0) => microblaze_0_axi_periph_M02_AXI_WVALID(0),
M03_ACLK => microblaze_0_Clk,
M03_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M03_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_M03_AXI_ARADDR(31 downto 0),
M03_AXI_arready(0) => microblaze_0_axi_periph_M03_AXI_ARREADY,
M03_AXI_arvalid(0) => microblaze_0_axi_periph_M03_AXI_ARVALID(0),
M03_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_M03_AXI_AWADDR(31 downto 0),
M03_AXI_awready(0) => microblaze_0_axi_periph_M03_AXI_AWREADY,
M03_AXI_awvalid(0) => microblaze_0_axi_periph_M03_AXI_AWVALID(0),
M03_AXI_bready(0) => microblaze_0_axi_periph_M03_AXI_BREADY(0),
M03_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M03_AXI_BRESP(1 downto 0),
M03_AXI_bvalid(0) => microblaze_0_axi_periph_M03_AXI_BVALID,
M03_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M03_AXI_RDATA(31 downto 0),
M03_AXI_rready(0) => microblaze_0_axi_periph_M03_AXI_RREADY(0),
M03_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M03_AXI_RRESP(1 downto 0),
M03_AXI_rvalid(0) => microblaze_0_axi_periph_M03_AXI_RVALID,
M03_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M03_AXI_WDATA(31 downto 0),
M03_AXI_wready(0) => microblaze_0_axi_periph_M03_AXI_WREADY,
M03_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M03_AXI_WSTRB(3 downto 0),
M03_AXI_wvalid(0) => microblaze_0_axi_periph_M03_AXI_WVALID(0),
M04_ACLK => microblaze_0_Clk,
M04_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M04_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_M04_AXI_ARADDR(31 downto 0),
M04_AXI_arready(0) => microblaze_0_axi_periph_M04_AXI_ARREADY,
M04_AXI_arvalid(0) => microblaze_0_axi_periph_M04_AXI_ARVALID(0),
M04_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_M04_AXI_AWADDR(31 downto 0),
M04_AXI_awready(0) => microblaze_0_axi_periph_M04_AXI_AWREADY,
M04_AXI_awvalid(0) => microblaze_0_axi_periph_M04_AXI_AWVALID(0),
M04_AXI_bready(0) => microblaze_0_axi_periph_M04_AXI_BREADY(0),
M04_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M04_AXI_BRESP(1 downto 0),
M04_AXI_bvalid(0) => microblaze_0_axi_periph_M04_AXI_BVALID,
M04_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M04_AXI_RDATA(31 downto 0),
M04_AXI_rready(0) => microblaze_0_axi_periph_M04_AXI_RREADY(0),
M04_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M04_AXI_RRESP(1 downto 0),
M04_AXI_rvalid(0) => microblaze_0_axi_periph_M04_AXI_RVALID,
M04_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M04_AXI_WDATA(31 downto 0),
M04_AXI_wready(0) => microblaze_0_axi_periph_M04_AXI_WREADY,
M04_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M04_AXI_WSTRB(3 downto 0),
M04_AXI_wvalid(0) => microblaze_0_axi_periph_M04_AXI_WVALID(0),
M05_ACLK => microblaze_0_Clk,
M05_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M05_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_M05_AXI_ARADDR(31 downto 0),
M05_AXI_arready(0) => microblaze_0_axi_periph_M05_AXI_ARREADY,
M05_AXI_arvalid(0) => microblaze_0_axi_periph_M05_AXI_ARVALID(0),
M05_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_M05_AXI_AWADDR(31 downto 0),
M05_AXI_awready(0) => microblaze_0_axi_periph_M05_AXI_AWREADY,
M05_AXI_awvalid(0) => microblaze_0_axi_periph_M05_AXI_AWVALID(0),
M05_AXI_bready(0) => microblaze_0_axi_periph_M05_AXI_BREADY(0),
M05_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M05_AXI_BRESP(1 downto 0),
M05_AXI_bvalid(0) => microblaze_0_axi_periph_M05_AXI_BVALID,
M05_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M05_AXI_RDATA(31 downto 0),
M05_AXI_rready(0) => microblaze_0_axi_periph_M05_AXI_RREADY(0),
M05_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M05_AXI_RRESP(1 downto 0),
M05_AXI_rvalid(0) => microblaze_0_axi_periph_M05_AXI_RVALID,
M05_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M05_AXI_WDATA(31 downto 0),
M05_AXI_wready(0) => microblaze_0_axi_periph_M05_AXI_WREADY,
M05_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M05_AXI_WSTRB(3 downto 0),
M05_AXI_wvalid(0) => microblaze_0_axi_periph_M05_AXI_WVALID(0),
M06_ACLK => microblaze_0_Clk,
M06_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M06_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_M06_AXI_ARADDR(31 downto 0),
M06_AXI_arready(0) => microblaze_0_axi_periph_M06_AXI_ARREADY,
M06_AXI_arvalid(0) => microblaze_0_axi_periph_M06_AXI_ARVALID(0),
M06_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_M06_AXI_AWADDR(31 downto 0),
M06_AXI_awready(0) => microblaze_0_axi_periph_M06_AXI_AWREADY,
M06_AXI_awvalid(0) => microblaze_0_axi_periph_M06_AXI_AWVALID(0),
M06_AXI_bready(0) => microblaze_0_axi_periph_M06_AXI_BREADY(0),
M06_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M06_AXI_BRESP(1 downto 0),
M06_AXI_bvalid(0) => microblaze_0_axi_periph_M06_AXI_BVALID,
M06_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M06_AXI_RDATA(31 downto 0),
M06_AXI_rready(0) => microblaze_0_axi_periph_M06_AXI_RREADY(0),
M06_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M06_AXI_RRESP(1 downto 0),
M06_AXI_rvalid(0) => microblaze_0_axi_periph_M06_AXI_RVALID,
M06_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M06_AXI_WDATA(31 downto 0),
M06_AXI_wready(0) => microblaze_0_axi_periph_M06_AXI_WREADY,
M06_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M06_AXI_WSTRB(3 downto 0),
M06_AXI_wvalid(0) => microblaze_0_axi_periph_M06_AXI_WVALID(0),
M07_ACLK => microblaze_0_Clk,
M07_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M07_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_M07_AXI_ARADDR(31 downto 0),
M07_AXI_arready(0) => microblaze_0_axi_periph_M07_AXI_ARREADY,
M07_AXI_arvalid(0) => microblaze_0_axi_periph_M07_AXI_ARVALID(0),
M07_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_M07_AXI_AWADDR(31 downto 0),
M07_AXI_awready(0) => microblaze_0_axi_periph_M07_AXI_AWREADY,
M07_AXI_awvalid(0) => microblaze_0_axi_periph_M07_AXI_AWVALID(0),
M07_AXI_bready(0) => microblaze_0_axi_periph_M07_AXI_BREADY(0),
M07_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M07_AXI_BRESP(1 downto 0),
M07_AXI_bvalid(0) => microblaze_0_axi_periph_M07_AXI_BVALID,
M07_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M07_AXI_RDATA(31 downto 0),
M07_AXI_rready(0) => microblaze_0_axi_periph_M07_AXI_RREADY(0),
M07_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M07_AXI_RRESP(1 downto 0),
M07_AXI_rvalid(0) => microblaze_0_axi_periph_M07_AXI_RVALID,
M07_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M07_AXI_WDATA(31 downto 0),
M07_AXI_wready(0) => microblaze_0_axi_periph_M07_AXI_WREADY,
M07_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M07_AXI_WSTRB(3 downto 0),
M07_AXI_wvalid(0) => microblaze_0_axi_periph_M07_AXI_WVALID(0),
M08_ACLK => microblaze_0_Clk,
M08_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M08_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_M08_AXI_ARADDR(31 downto 0),
M08_AXI_arready(0) => microblaze_0_axi_periph_M08_AXI_ARREADY,
M08_AXI_arvalid(0) => microblaze_0_axi_periph_M08_AXI_ARVALID(0),
M08_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_M08_AXI_AWADDR(31 downto 0),
M08_AXI_awready(0) => microblaze_0_axi_periph_M08_AXI_AWREADY,
M08_AXI_awvalid(0) => microblaze_0_axi_periph_M08_AXI_AWVALID(0),
M08_AXI_bready(0) => microblaze_0_axi_periph_M08_AXI_BREADY(0),
M08_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M08_AXI_BRESP(1 downto 0),
M08_AXI_bvalid(0) => microblaze_0_axi_periph_M08_AXI_BVALID,
M08_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M08_AXI_RDATA(31 downto 0),
M08_AXI_rready(0) => microblaze_0_axi_periph_M08_AXI_RREADY(0),
M08_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M08_AXI_RRESP(1 downto 0),
M08_AXI_rvalid(0) => microblaze_0_axi_periph_M08_AXI_RVALID,
M08_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M08_AXI_WDATA(31 downto 0),
M08_AXI_wready(0) => microblaze_0_axi_periph_M08_AXI_WREADY,
M08_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M08_AXI_WSTRB(3 downto 0),
M08_AXI_wvalid(0) => microblaze_0_axi_periph_M08_AXI_WVALID(0),
M09_ACLK => microblaze_0_Clk,
M09_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M09_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_M09_AXI_ARADDR(31 downto 0),
M09_AXI_arready(0) => microblaze_0_axi_periph_M09_AXI_ARREADY,
M09_AXI_arvalid(0) => microblaze_0_axi_periph_M09_AXI_ARVALID(0),
M09_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_M09_AXI_AWADDR(31 downto 0),
M09_AXI_awready(0) => microblaze_0_axi_periph_M09_AXI_AWREADY,
M09_AXI_awvalid(0) => microblaze_0_axi_periph_M09_AXI_AWVALID(0),
M09_AXI_bready(0) => microblaze_0_axi_periph_M09_AXI_BREADY(0),
M09_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M09_AXI_BRESP(1 downto 0),
M09_AXI_bvalid(0) => microblaze_0_axi_periph_M09_AXI_BVALID,
M09_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M09_AXI_RDATA(31 downto 0),
M09_AXI_rready(0) => microblaze_0_axi_periph_M09_AXI_RREADY(0),
M09_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M09_AXI_RRESP(1 downto 0),
M09_AXI_rvalid(0) => microblaze_0_axi_periph_M09_AXI_RVALID,
M09_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M09_AXI_WDATA(31 downto 0),
M09_AXI_wready(0) => microblaze_0_axi_periph_M09_AXI_WREADY,
M09_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M09_AXI_WSTRB(3 downto 0),
M09_AXI_wvalid(0) => microblaze_0_axi_periph_M09_AXI_WVALID(0),
M10_ACLK => microblaze_0_Clk,
M10_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M10_AXI_araddr => NLW_microblaze_0_axi_periph_M10_AXI_araddr_UNCONNECTED,
M10_AXI_arprot => NLW_microblaze_0_axi_periph_M10_AXI_arprot_UNCONNECTED,
M10_AXI_arready => '0',
M10_AXI_arvalid => NLW_microblaze_0_axi_periph_M10_AXI_arvalid_UNCONNECTED,
M10_AXI_awaddr => NLW_microblaze_0_axi_periph_M10_AXI_awaddr_UNCONNECTED,
M10_AXI_awprot => NLW_microblaze_0_axi_periph_M10_AXI_awprot_UNCONNECTED,
M10_AXI_awready => '0',
M10_AXI_awvalid => NLW_microblaze_0_axi_periph_M10_AXI_awvalid_UNCONNECTED,
M10_AXI_bready => NLW_microblaze_0_axi_periph_M10_AXI_bready_UNCONNECTED,
M10_AXI_bresp => '0',
M10_AXI_bvalid => '0',
M10_AXI_rdata => '0',
M10_AXI_rready => NLW_microblaze_0_axi_periph_M10_AXI_rready_UNCONNECTED,
M10_AXI_rresp => '0',
M10_AXI_rvalid => '0',
M10_AXI_wdata => NLW_microblaze_0_axi_periph_M10_AXI_wdata_UNCONNECTED,
M10_AXI_wready => '0',
M10_AXI_wstrb => NLW_microblaze_0_axi_periph_M10_AXI_wstrb_UNCONNECTED,
M10_AXI_wvalid => NLW_microblaze_0_axi_periph_M10_AXI_wvalid_UNCONNECTED,
M11_ACLK => microblaze_0_Clk,
M11_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M11_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_M11_AXI_ARADDR(31 downto 0),
M11_AXI_arready(0) => microblaze_0_axi_periph_M11_AXI_ARREADY,
M11_AXI_arvalid(0) => microblaze_0_axi_periph_M11_AXI_ARVALID(0),
M11_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_M11_AXI_AWADDR(31 downto 0),
M11_AXI_awready(0) => microblaze_0_axi_periph_M11_AXI_AWREADY,
M11_AXI_awvalid(0) => microblaze_0_axi_periph_M11_AXI_AWVALID(0),
M11_AXI_bready(0) => microblaze_0_axi_periph_M11_AXI_BREADY(0),
M11_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M11_AXI_BRESP(1 downto 0),
M11_AXI_bvalid(0) => microblaze_0_axi_periph_M11_AXI_BVALID,
M11_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M11_AXI_RDATA(31 downto 0),
M11_AXI_rready(0) => microblaze_0_axi_periph_M11_AXI_RREADY(0),
M11_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M11_AXI_RRESP(1 downto 0),
M11_AXI_rvalid(0) => microblaze_0_axi_periph_M11_AXI_RVALID,
M11_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M11_AXI_WDATA(31 downto 0),
M11_AXI_wready(0) => microblaze_0_axi_periph_M11_AXI_WREADY,
M11_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M11_AXI_WSTRB(3 downto 0),
M11_AXI_wvalid(0) => microblaze_0_axi_periph_M11_AXI_WVALID(0),
M12_ACLK => microblaze_0_Clk,
M12_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M12_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_M12_AXI_ARADDR(31 downto 0),
M12_AXI_arready(0) => microblaze_0_axi_periph_M12_AXI_ARREADY,
M12_AXI_arvalid(0) => microblaze_0_axi_periph_M12_AXI_ARVALID(0),
M12_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_M12_AXI_AWADDR(31 downto 0),
M12_AXI_awready(0) => microblaze_0_axi_periph_M12_AXI_AWREADY,
M12_AXI_awvalid(0) => microblaze_0_axi_periph_M12_AXI_AWVALID(0),
M12_AXI_bready(0) => microblaze_0_axi_periph_M12_AXI_BREADY(0),
M12_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M12_AXI_BRESP(1 downto 0),
M12_AXI_bvalid(0) => microblaze_0_axi_periph_M12_AXI_BVALID,
M12_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M12_AXI_RDATA(31 downto 0),
M12_AXI_rready(0) => microblaze_0_axi_periph_M12_AXI_RREADY(0),
M12_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M12_AXI_RRESP(1 downto 0),
M12_AXI_rvalid(0) => microblaze_0_axi_periph_M12_AXI_RVALID,
M12_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M12_AXI_WDATA(31 downto 0),
M12_AXI_wready(0) => microblaze_0_axi_periph_M12_AXI_WREADY,
M12_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M12_AXI_WSTRB(3 downto 0),
M12_AXI_wvalid(0) => microblaze_0_axi_periph_M12_AXI_WVALID(0),
M13_ACLK => mig_7series_0_ui_clk,
M13_ARESETN => rst_mig_7series_0_83M_peripheral_aresetn(0),
M13_AXI_araddr(10 downto 0) => microblaze_0_axi_periph_M13_AXI_ARADDR(10 downto 0),
M13_AXI_arready => microblaze_0_axi_periph_M13_AXI_ARREADY,
M13_AXI_arvalid => microblaze_0_axi_periph_M13_AXI_ARVALID,
M13_AXI_awaddr(10 downto 0) => microblaze_0_axi_periph_M13_AXI_AWADDR(10 downto 0),
M13_AXI_awready => microblaze_0_axi_periph_M13_AXI_AWREADY,
M13_AXI_awvalid => microblaze_0_axi_periph_M13_AXI_AWVALID,
M13_AXI_bready => microblaze_0_axi_periph_M13_AXI_BREADY,
M13_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M13_AXI_BRESP(1 downto 0),
M13_AXI_bvalid => microblaze_0_axi_periph_M13_AXI_BVALID,
M13_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M13_AXI_RDATA(31 downto 0),
M13_AXI_rready => microblaze_0_axi_periph_M13_AXI_RREADY,
M13_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M13_AXI_RRESP(1 downto 0),
M13_AXI_rvalid => microblaze_0_axi_periph_M13_AXI_RVALID,
M13_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M13_AXI_WDATA(31 downto 0),
M13_AXI_wready => microblaze_0_axi_periph_M13_AXI_WREADY,
M13_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M13_AXI_WSTRB(3 downto 0),
M13_AXI_wvalid => microblaze_0_axi_periph_M13_AXI_WVALID,
S00_ACLK => microblaze_0_Clk,
S00_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => microblaze_0_axi_dp_ARADDR(31 downto 0),
S00_AXI_arprot(2 downto 0) => microblaze_0_axi_dp_ARPROT(2 downto 0),
S00_AXI_arready(0) => microblaze_0_axi_dp_ARREADY(0),
S00_AXI_arvalid(0) => microblaze_0_axi_dp_ARVALID,
S00_AXI_awaddr(31 downto 0) => microblaze_0_axi_dp_AWADDR(31 downto 0),
S00_AXI_awprot(2 downto 0) => microblaze_0_axi_dp_AWPROT(2 downto 0),
S00_AXI_awready(0) => microblaze_0_axi_dp_AWREADY(0),
S00_AXI_awvalid(0) => microblaze_0_axi_dp_AWVALID,
S00_AXI_bready(0) => microblaze_0_axi_dp_BREADY,
S00_AXI_bresp(1 downto 0) => microblaze_0_axi_dp_BRESP(1 downto 0),
S00_AXI_bvalid(0) => microblaze_0_axi_dp_BVALID(0),
S00_AXI_rdata(31 downto 0) => microblaze_0_axi_dp_RDATA(31 downto 0),
S00_AXI_rready(0) => microblaze_0_axi_dp_RREADY,
S00_AXI_rresp(1 downto 0) => microblaze_0_axi_dp_RRESP(1 downto 0),
S00_AXI_rvalid(0) => microblaze_0_axi_dp_RVALID(0),
S00_AXI_wdata(31 downto 0) => microblaze_0_axi_dp_WDATA(31 downto 0),
S00_AXI_wready(0) => microblaze_0_axi_dp_WREADY(0),
S00_AXI_wstrb(3 downto 0) => microblaze_0_axi_dp_WSTRB(3 downto 0),
S00_AXI_wvalid(0) => microblaze_0_axi_dp_WVALID
);
microblaze_0_local_memory: entity work.microblaze_0_local_memory_imp_OGE0N8
port map (
DLMB_abus(0 to 31) => microblaze_0_dlmb_1_ABUS(0 to 31),
DLMB_addrstrobe => microblaze_0_dlmb_1_ADDRSTROBE,
DLMB_be(0 to 3) => microblaze_0_dlmb_1_BE(0 to 3),
DLMB_ce => microblaze_0_dlmb_1_CE,
DLMB_readdbus(0 to 31) => microblaze_0_dlmb_1_READDBUS(0 to 31),
DLMB_readstrobe => microblaze_0_dlmb_1_READSTROBE,
DLMB_ready => microblaze_0_dlmb_1_READY,
DLMB_ue => microblaze_0_dlmb_1_UE,
DLMB_wait => microblaze_0_dlmb_1_WAIT,
DLMB_writedbus(0 to 31) => microblaze_0_dlmb_1_WRITEDBUS(0 to 31),
DLMB_writestrobe => microblaze_0_dlmb_1_WRITESTROBE,
ILMB_abus(0 to 31) => microblaze_0_ilmb_1_ABUS(0 to 31),
ILMB_addrstrobe => microblaze_0_ilmb_1_ADDRSTROBE,
ILMB_ce => microblaze_0_ilmb_1_CE,
ILMB_readdbus(0 to 31) => microblaze_0_ilmb_1_READDBUS(0 to 31),
ILMB_readstrobe => microblaze_0_ilmb_1_READSTROBE,
ILMB_ready => microblaze_0_ilmb_1_READY,
ILMB_ue => microblaze_0_ilmb_1_UE,
ILMB_wait => microblaze_0_ilmb_1_WAIT,
LMB_Clk => microblaze_0_Clk,
SYS_Rst(0) => rst_clk_wiz_1_100M_bus_struct_reset(0)
);
microblaze_0_xlconcat: component system_microblaze_0_xlconcat_0
port map (
In0(0) => axi_timer_0_interrupt,
In1(0) => axi_ethernetlite_0_ip2intc_irpt,
In2(0) => axi_iic_0_iic2intc_irpt,
In3(0) => axi_gpio_sw_ip2intc_irpt,
In4(0) => axi_quad_spi_flash_ip2intc_irpt,
In5(0) => axi_quad_spi_shield_ip2intc_irpt,
In6(0) => xadc_wiz_0_ip2intc_irpt,
dout(6 downto 0) => microblaze_0_intr(6 downto 0)
);
mig_7series_0: component system_mig_7series_0_0
port map (
aresetn => rst_mig_7series_0_83M_peripheral_aresetn(0),
clk_ref_i => clk_wiz_1_clk_out3,
ddr3_addr(13 downto 0) => mig_7series_0_DDR3_ADDR(13 downto 0),
ddr3_ba(2 downto 0) => mig_7series_0_DDR3_BA(2 downto 0),
ddr3_cas_n => mig_7series_0_DDR3_CAS_N,
ddr3_ck_n(0) => mig_7series_0_DDR3_CK_N(0),
ddr3_ck_p(0) => mig_7series_0_DDR3_CK_P(0),
ddr3_cke(0) => mig_7series_0_DDR3_CKE(0),
ddr3_cs_n(0) => mig_7series_0_DDR3_CS_N(0),
ddr3_dm(1 downto 0) => mig_7series_0_DDR3_DM(1 downto 0),
ddr3_dq(15 downto 0) => DDR3_dq(15 downto 0),
ddr3_dqs_n(1 downto 0) => DDR3_dqs_n(1 downto 0),
ddr3_dqs_p(1 downto 0) => DDR3_dqs_p(1 downto 0),
ddr3_odt(0) => mig_7series_0_DDR3_ODT(0),
ddr3_ras_n => mig_7series_0_DDR3_RAS_N,
ddr3_reset_n => mig_7series_0_DDR3_RESET_N,
ddr3_we_n => mig_7series_0_DDR3_WE_N,
device_temp_i(11 downto 0) => xadc_wiz_0_temp_out(11 downto 0),
init_calib_complete => NLW_mig_7series_0_init_calib_complete_UNCONNECTED,
mmcm_locked => mig_7series_0_mmcm_locked,
s_axi_araddr(27 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(27 downto 0),
s_axi_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
s_axi_arid(0) => axi_mem_intercon_M00_AXI_ARID(0),
s_axi_arlen(7 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(7 downto 0),
s_axi_arlock => axi_mem_intercon_M00_AXI_ARLOCK,
s_axi_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0),
s_axi_arready => axi_mem_intercon_M00_AXI_ARREADY,
s_axi_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
s_axi_arvalid => axi_mem_intercon_M00_AXI_ARVALID,
s_axi_awaddr(27 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(27 downto 0),
s_axi_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
s_axi_awid(0) => axi_mem_intercon_M00_AXI_AWID(0),
s_axi_awlen(7 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(7 downto 0),
s_axi_awlock => axi_mem_intercon_M00_AXI_AWLOCK,
s_axi_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0),
s_axi_awready => axi_mem_intercon_M00_AXI_AWREADY,
s_axi_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
s_axi_awvalid => axi_mem_intercon_M00_AXI_AWVALID,
s_axi_bid(0) => axi_mem_intercon_M00_AXI_BID(0),
s_axi_bready => axi_mem_intercon_M00_AXI_BREADY,
s_axi_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
s_axi_bvalid => axi_mem_intercon_M00_AXI_BVALID,
s_axi_rdata(127 downto 0) => axi_mem_intercon_M00_AXI_RDATA(127 downto 0),
s_axi_rid(0) => axi_mem_intercon_M00_AXI_RID(0),
s_axi_rlast => axi_mem_intercon_M00_AXI_RLAST,
s_axi_rready => axi_mem_intercon_M00_AXI_RREADY,
s_axi_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
s_axi_rvalid => axi_mem_intercon_M00_AXI_RVALID,
s_axi_wdata(127 downto 0) => axi_mem_intercon_M00_AXI_WDATA(127 downto 0),
s_axi_wlast => axi_mem_intercon_M00_AXI_WLAST,
s_axi_wready => axi_mem_intercon_M00_AXI_WREADY,
s_axi_wstrb(15 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(15 downto 0),
s_axi_wvalid => axi_mem_intercon_M00_AXI_WVALID,
sys_clk_i => clk_wiz_1_clk_out2,
sys_rst => reset_1,
ui_clk => mig_7series_0_ui_clk,
ui_clk_sync_rst => mig_7series_0_ui_clk_sync_rst
);
rst_clk_wiz_1_100M: component system_rst_clk_wiz_1_100M_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => rst_clk_wiz_1_100M_bus_struct_reset(0),
dcm_locked => clk_wiz_1_locked,
ext_reset_in => reset_1,
interconnect_aresetn(0) => rst_clk_wiz_1_100M_interconnect_aresetn(0),
mb_debug_sys_rst => mdm_1_debug_sys_rst,
mb_reset => rst_clk_wiz_1_100M_mb_reset,
peripheral_aresetn(0) => rst_clk_wiz_1_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_clk_wiz_1_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => microblaze_0_Clk
);
rst_mig_7series_0_83M: component system_rst_mig_7series_0_83M_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_rst_mig_7series_0_83M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => mig_7series_0_mmcm_locked,
ext_reset_in => mig_7series_0_ui_clk_sync_rst,
interconnect_aresetn(0) => NLW_rst_mig_7series_0_83M_interconnect_aresetn_UNCONNECTED(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_rst_mig_7series_0_83M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_mig_7series_0_83M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_mig_7series_0_83M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => mig_7series_0_ui_clk
);
xadc_wiz_0: component system_xadc_wiz_0_0
port map (
alarm_out => NLW_xadc_wiz_0_alarm_out_UNCONNECTED,
busy_out => NLW_xadc_wiz_0_busy_out_UNCONNECTED,
channel_out(4 downto 0) => NLW_xadc_wiz_0_channel_out_UNCONNECTED(4 downto 0),
eoc_out => NLW_xadc_wiz_0_eoc_out_UNCONNECTED,
eos_out => NLW_xadc_wiz_0_eos_out_UNCONNECTED,
ip2intc_irpt => xadc_wiz_0_ip2intc_irpt,
s_axi_aclk => mig_7series_0_ui_clk,
s_axi_araddr(10 downto 0) => microblaze_0_axi_periph_M13_AXI_ARADDR(10 downto 0),
s_axi_aresetn => rst_mig_7series_0_83M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M13_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M13_AXI_ARVALID,
s_axi_awaddr(10 downto 0) => microblaze_0_axi_periph_M13_AXI_AWADDR(10 downto 0),
s_axi_awready => microblaze_0_axi_periph_M13_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M13_AXI_AWVALID,
s_axi_bready => microblaze_0_axi_periph_M13_AXI_BREADY,
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M13_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M13_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M13_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M13_AXI_RREADY,
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M13_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M13_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M13_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M13_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M13_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M13_AXI_WVALID,
temp_out(11 downto 0) => xadc_wiz_0_temp_out(11 downto 0),
user_temp_alarm_out => NLW_xadc_wiz_0_user_temp_alarm_out_UNCONNECTED,
vauxn0 => Vaux0_1_V_N,
vauxn1 => Vaux1_1_V_N,
vauxn10 => Vaux10_1_V_N,
vauxn12 => Vaux12_1_V_N,
vauxn13 => Vaux13_1_V_N,
vauxn14 => Vaux14_1_V_N,
vauxn15 => Vaux15_1_V_N,
vauxn2 => Vaux2_1_V_N,
vauxn4 => Vaux4_1_V_N,
vauxn5 => Vaux5_1_V_N,
vauxn6 => Vaux6_1_V_N,
vauxn7 => Vaux7_1_V_N,
vauxn9 => Vaux9_1_V_N,
vauxp0 => Vaux0_1_V_P,
vauxp1 => Vaux1_1_V_P,
vauxp10 => Vaux10_1_V_P,
vauxp12 => Vaux12_1_V_P,
vauxp13 => Vaux13_1_V_P,
vauxp14 => Vaux14_1_V_P,
vauxp15 => Vaux15_1_V_P,
vauxp2 => Vaux2_1_V_P,
vauxp4 => Vaux4_1_V_P,
vauxp5 => Vaux5_1_V_P,
vauxp6 => Vaux6_1_V_P,
vauxp7 => Vaux7_1_V_P,
vauxp9 => Vaux9_1_V_P,
vccaux_alarm_out => NLW_xadc_wiz_0_vccaux_alarm_out_UNCONNECTED,
vccint_alarm_out => NLW_xadc_wiz_0_vccint_alarm_out_UNCONNECTED,
vn_in => Vp_Vn_1_V_N,
vp_in => Vp_Vn_1_V_P
);
end STRUCTURE;
|
apache-2.0
|
01ccf3859c5aa8e3f74c20adf51bf37c
| 0.669069 | 2.794999 | false | false | false | false |
jeffmagina/ECE368
|
Lab2/VGA Part 1/clk100MHz.vhd
| 1 | 2,095 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Pixel CLK
-- Project Name: VGA
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: 100Mhz Clock
-- 50 Mhz to 100 Mhz
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity CLK_100MHZ is
port(CLK_IN: in std_logic;
CLK_OUT: inout std_logic);
end CLK_100MHZ;
architecture Behavioral of CLK_100MHZ is
component CLKDLL
generic (CLKDV_DIVIDE : real := 2.0;--2.0; -- (1.5, 2.0, 2.5,
-- 3.0, 4.0, 5.0, 8.0, 16.0)
DUTY_CYCLE_CORRECTION : Boolean := TRUE; -- (TRUE, FALSE)
STARTUP_WAIT : boolean := FALSE); -- (TRUE, FALSE)
port(CLK0 : out STD_ULOGIC;
CLK180 : out STD_ULOGIC;
CLK270 : out STD_ULOGIC;
CLK2X : out STD_ULOGIC;
CLK90 : out STD_ULOGIC;
CLKDV : out STD_ULOGIC;
LOCKED : out STD_ULOGIC;
CLKFB : in STD_ULOGIC;
CLKIN : in STD_ULOGIC;
RST : in STD_ULOGIC);
end component;
attribute CLKDV_DIVIDE : real;
attribute DUTY_CYCLE_CORRECTION : boolean;
attribute STARTUP_WAIT : boolean;
begin
CLKDLL_inst : CLKDLL
port map (
CLK0 => open, -- 0 degree DLL CLK ouptput
CLK180 => open, -- 180 degree DLL CLK output
CLK270 => open, -- 270 degree DLL CLK output
CLK2X => CLK_OUT, -- 2X DLL CLK output
CLK90 => open, -- 90 degree DLL CLK output
CLKDV => open, -- Divided DLL CLK out (CLKDV_DIVIDE)
LOCKED => open, -- DLL LOCK status output
CLKFB => CLK_OUT, -- DLL clock feedback
CLKIN => CLK_IN, -- Clock input (from IBUFG, BUFG or DLL)
RST => '0' -- DLL asynchronous reset input
);
end Behavioral;
|
mit
|
3cdc548a7e723a554fd01d77a79b8508
| 0.570883 | 3.734403 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 1/CU_tb.vhd
| 1 | 1,664 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY CU_tb IS
END CU_tb;
ARCHITECTURE behavior OF CU_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CU
PORT(
OP : IN std_logic_vector(1 downto 0);
OP3 : IN std_logic_vector(5 downto 0);
ALUOP : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
--Inputs
signal OP : std_logic_vector(1 downto 0) := (others => '0');
signal OP3 : std_logic_vector(5 downto 0) := (others => '0');
--Outputs
signal ALUOP : std_logic_vector(5 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CU PORT MAP (
OP => OP,
OP3 => OP3,
ALUOP => ALUOP
);
-- Stimulus process
stim_proc: process
begin
---------------Instrucciones Aritmetico Logicas---------------
OP<="10";
OP3<="000001";--0. AND
wait for 20 ns;
OP3<="000101";--1. ANDN
wait for 20 ns;
OP3<="000010";--2. OR
wait for 20 ns;
OP3<="000110";--3. ORN
wait for 20 ns;
OP3<="000011";--4. XOR
wait for 20 ns;
OP3<="000111";--5. XNOR
wait for 20 ns;
OP3<="000000";--6. ADD
wait for 20 ns;
OP3<="000100";--7. SUB
wait for 20 ns;
---------------Instrucciones artimetico logicas anun no definidas-------------------
OP3<="100101";--8. SLL
wait for 20 ns;
OP3<="100110";--9. SRL
wait for 20 ns;
OP3<="100111";--10.SRA
wait for 20 ns;
-----------------Otras Instrucciones(aun no definidas)-----------------------
OP<="00";
OP3<="010101";
wait;
end process;
END;
|
mit
|
d44a348d490264a3cdf57b9b029765cf
| 0.518029 | 3.466667 | false | false | false | false |
jeffmagina/ECE368
|
Lab2/VGA Part 2/vga_controller_tb.vhd
| 1 | 6,052 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: VGA_COLOR_TB
-- Project Name: VGA_COLOR
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: VGA_COLOR Test Bench
---------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY VGA_TOPLEVEL_tb_vhd IS
END VGA_TOPLEVEL_tb_vhd;
ARCHITECTURE behavior OF VGA_TOPLEVEL_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT VGA_TOPLEVEL
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
--SW : in STD_LOGIC_VECTOR (7 downto 0);
PS2_CLK : inout STD_LOGIC;
PS2_DATA : inout STD_LOGIC;
HSYNC : out STD_LOGIC;
VSYNC : out STD_LOGIC;
VGARED : out STD_LOGIC_VECTOR (2 downto 0);
VGAGRN : out STD_LOGIC_VECTOR (2 downto 0);
VGABLU : out STD_LOGIC_VECTOR (1 downto 0));
END COMPONENT;
SIGNAL CLK : STD_LOGIC := '0';
SIGNAL RST : STD_LOGIC := '0';
SIGNAL PS2_CLK : STD_LOGIC := '1';
SIGNAL PS2_DATA: STD_LOGIC := '1';
SIGNAL HSYNC : STD_LOGIC := '0';
SIGNAL VSYNC : STD_LOGIC := '0';
SIGNAL VGARED : STD_LOGIC_VECTOR(2 downto 0) := (others=>'0');
SIGNAL VGAGRN : STD_LOGIC_VECTOR(2 downto 0) := (others=>'0');
SIGNAL VGABLU : STD_LOGIC_VECTOR(1 downto 0) := (others=>'0');
--SIGNAL SW : STD_LOGIC_VECTOR(7 downto 0);
-- Constants
-- constant period : time := 20 ns; -- 25 MHz =(1/20E-9)/2
constant period : time := 10 ns; -- 50 MHz =(1/10E-9)/2
-- constant period : time := 5 ns; -- 100 MHz =(1/10E-9)/2
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: VGA_TOPLEVEL PORT MAP( CLK => CLK,
RST => RST,
--SW => SW,
PS2_CLK => PS2_CLK,
PS2_DATA=> PS2_DATA,
HSYNC => HSYNC,
VSYNC => VSYNC,
VGARED => VGARED,
VGAGRN => VGAGRN,
VGABLU => VGABLU);
-- Generate clock
gen_Clock: process
begin
CLK <= '0'; wait for period;
CLK <= '1'; wait for period;
end process gen_Clock;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
report "Start VGA_Controller Test Bench" severity NOTE;
--Simulate Pressing A
--Sending the Break Code X"F0"
--Start bit '0'
PS2_DATA <= '0';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 7 LSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 6
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 5
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 4
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 3
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 2
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 1
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 0 MSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Odd Parity Bit
PS2_DATA <= '1';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Stop Bit '1'
PS2_DATA <= '1';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- END Transmission
PS2_CLK <= '1';
wait for 100 us;
--Sending the Key Code X"1C"
--Start bit '0'
PS2_DATA <= '0';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 7 LSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 6
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 5
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 4
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 3
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 2
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 1
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 0 MSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Odd Parity Bit
PS2_DATA <= '0';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Stop Bit '1'
PS2_DATA <= '1';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- END Transmission
PS2_CLK <= '1';
wait for 100 us;
wait; -- will wait forever
END PROCESS;
END;
|
mit
|
8a9fe6115bdf4f831c6b8931ac267f85
| 0.433906 | 3.436684 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 2/PSR.vhd
| 1 | 722 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PSR is
Port ( NZVC : in STD_LOGIC_VECTOR (3 downto 0);
nCWP: in STD_LOGIC;
CLK: in STD_LOGIC;
rst: in STD_LOGIC;
CWP: out STD_LOGIC;
C : out STD_LOGIC);
end PSR;
architecture Behavioral of PSR is
signal PSRegister: std_logic_vector(4 downto 0):=(others=>'0');
begin
process(NZVC,nCWP,CLK,rst)
begin
if rst='1' then
PSRegister<=(others=>'0');
C<='0';
CWP<='0';
elsif rising_edge(CLK) then
if not(NZVC="1111") then
PSRegister(4 downto 1)<=NZVC;
end if;
PSRegister(0)<=nCWP;
CWP<=PSRegister(0);
--CWP<=nCWP;
C<=PSRegister(1);
--C<=NZVC(0);
end if;
end process;
end Behavioral;
|
mit
|
a74337391f02f66f364519512070d88a
| 0.601108 | 2.91129 | false | false | false | false |
aggroskater/ee4321-vhdl-digital-design
|
Project-4-4bit-ALU/alu.vhd
| 1 | 1,816 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity alu_4_bit is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
op : in STD_LOGIC_VECTOR (5 downto 0);
R : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end alu_4_bit;
architecture Behavioral of alu_4_bit is
--these signals carry internal outputs from the different blocks for routing to
--appropriate stages (mostly the output choice mux4)
signal add_sub_zero : std_logic:='0';
signal add_sub_Cout : std_logic:='0';
signal add_sub_overflow : std_logic:='0';
signal add_sub_R : std_logic_vector (3 downto 0);
signal comparator_R: std_logic_vector (3 downto 0) := (others => '0');
signal logical_R: std_logic_vector (3 downto 0);
signal shift_rot_R: std_logic_vector (3 downto 0);
begin
--adder/subtractor unit
add_sub: entity work.cla_4_bit port map (A, B, op(3), add_sub_R,
add_sub_Cout, add_sub_zero, add_sub_overflow);
--comparator unit
comparator: entity work.comparator port map (A, B, op(2 downto 0),
add_sub_zero, add_sub_Cout, add_sub_overflow, add_sub_R, comparator_R(0));
--logical unit
logical: entity work.logical port map (A, B, op(1 downto 0), logical_R);
--shift/rotate unit
shift_rot: entity work.shift_rotate port map (A, B, op(2 downto 0), shift_rot_R);
--output selection mux
output_choice_mux: entity work.mux4 port map (add_sub_R, comparator_R, logical_R,
shift_rot_R, op(5 downto 4), R);
--make sure Cout gets assigned
Cout <= add_sub_Cout;
end Behavioral;
--A note: This design is entirely combinatorial and likely purely insane. EVERY
--operation is carried out, and the output choice mux merely selects which
--block_R to push to the ALU's "R" output. This would be a truly terrible
--design as far as power constraints go.
|
agpl-3.0
|
c9a38f676bebd3d9de68ec8c7feb05f3
| 0.694934 | 3.098976 | false | false | false | false |
eaglewyng/FPGA2048
|
vga_timing.vhd
| 1 | 3,120 |
----------------------------------------------------------------------------------
-- Company: Brigham Young University
-- Engineer: Parker Brian Ridd
--
-- Create Date: 10:24:17 02/04/2014
-- Design Name:
-- Module Name: vga_timing - lab_arch
-- Project Name: Lab 5
-- Target Devices: Nexsys 2 by Digilent
-- Tool versions:
-- Description: VGA Controller for the lab 5 assignment
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_timing is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
HS : out STD_LOGIC;
VS : out STD_LOGIC;
pixel_x : out STD_LOGIC_VECTOR (9 downto 0);
pixel_y : out STD_LOGIC_VECTOR (9 downto 0);
last_column : out STD_LOGIC;
last_row : out STD_LOGIC;
blank : out STD_LOGIC);
end vga_timing;
architecture lab_arch of vga_timing is
--create signals for pixel clock
signal pixel_en, pxr_next : STD_LOGIC := '0';
--create signals for horizontal counter
signal hzr_reg, hzr_next: UNSIGNED(9 downto 0) := (others => '0');
signal hz_lastColumn : STD_LOGIC := '0';
--create signals for vertical counter
signal ver_reg, ver_next : UNSIGNED(9 downto 0) := (others => '0');
signal ver_lastRow : STD_LOGIC := '0';
begin
--BASE MODULE OF PIXEL CLOCK
process(clk, rst)
begin
if(rst = '1') then
pixel_en <= '0';
elsif(clk'event and clk = '1') then
pixel_en <= pxr_next;
end if;
end process;
--next state logic for pixel clock
pxr_next <=
not pixel_en;
--HORIZONTAL PIXEL COUNTER
process(clk, rst)
begin
if(rst = '1') then
hzr_reg <= (others => '0');
elsif(clk'event and clk = '1') then
hzr_reg <= hzr_next;
end if;
end process;
--next state logic for horizontal counter
hzr_next <=
(others => '0') when (hzr_reg = 799) and (pixel_en = '1') else
hzr_reg + 1 when pixel_en = '1' else
hzr_reg;
--output signal logic for horizontal counter
hz_lastColumn <=
'1' when hzr_reg = 639 else
'0';
HS <= '0' when (hzr_reg > 655) and (hzr_reg < 752) else
'1';
--VERTICAL PIXEL COUNTER
process(clk, rst)
begin
if(rst = '1') then
ver_reg <= (others => '0');
elsif(clk'event and clk = '1') then
ver_reg <= ver_next;
end if;
end process;
--next state logic for vertical counter
ver_next <=
(others => '0') when (ver_reg = 520) and (hzr_reg = 799) and (pixel_en = '1') else
ver_reg + 1 when (hzr_reg = 799) and (pixel_en = '1') else
ver_reg;
--output signal logic for vertical counter
ver_lastRow <=
'1' when ver_reg = 479 else
'0';
VS <=
'0' when (ver_reg > 489) and (ver_reg < 492) else
'1';
--LOGIC FOR THE BLANK SIGNAL
blank <=
'1' when (ver_reg > 479) else
'1' when (hzr_reg > 639) else
'0';
--OTHER OUTPUT ASSIGNMENTS
pixel_x <= std_logic_vector(hzr_reg);
pixel_y <= std_logic_vector(ver_reg);
last_column <= hz_lastColumn;
last_row <= ver_lastRow;
end lab_arch;
|
mit
|
3d238199bec9b0b26839370a9daadea2
| 0.583333 | 3.026188 | false | false | false | false |
daniw/add
|
rot_enc/mcu.vhd
| 1 | 4,752 |
-------------------------------------------------------------------------------
-- Entity: mcu
-- Author: Waj
-- Date : 11-May-13
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- Top-level description of a simple von-Neumann MCU.
-- All top-level component are instantiated here. Also, tri-state buffers for
-- bi-directional GPIO pins are described here.
-------------------------------------------------------------------------------
-- Total # of FFs: 0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity mcu is
port(rst : in std_logic;
clk : in std_logic;
-- LED(8:0) on S3E-Board (demonstrate tri-state buffers)
LED : inout std_logic_vector(7 downto 0);
-- SW(3:0) on S3E-Board
Switch : in std_logic_vector(3 downto 0);
-- Rotary encoder on S3E-Board
ROT_A : in std_logic;
ROT_B : in std_logic;
ROT_CENTER : in std_logic
);
end mcu;
architecture rtl of mcu is
-- CPU signals
signal cpu2bus : t_cpu2bus;
signal bus2cpu : t_bus2cpu;
-- ROM signals
signal bus2rom : t_bus2ros;
signal rom2bus : t_ros2bus;
-- ROM signals
signal bus2ram : t_bus2rws;
signal ram2bus : t_rws2bus;
-- GPIO signals
signal bus2gpio : t_bus2rws;
signal gpio2bus : t_rws2bus;
signal gpio_in : std_logic_vector(DW-1 downto 0);
signal gpio_out : std_logic_vector(DW-1 downto 0);
signal gpio_out_enb : std_logic_vector(DW-1 downto 0);
begin
-----------------------------------------------------------------------------
-- Connect GPIO(7:0) to LED(7:0)
-- Demonstrates the usage of tri-state buffers although this not required for
-- LED functionality.
-----------------------------------------------------------------------------
gpio_in(7 downto 0) <= LED;
gen_led_3state: for k in 0 to 7 generate
LED(k) <= gpio_out(k) when gpio_out_enb(k) = '1' else 'Z';
end generate;
-----------------------------------------------------------------------------
-- Connect SW(3:0) to GPIO(11:8)
-- NOTE: GPIO(11:8) is only connected as input, since the SITE TYPE of the 4
-- Switch pins is IBUF, which prevents the usage of tri-state IOBs.
-- Furthermore, even if IOBs were available, it would be dangerous to
-- use them here, since a wrong SW configuration could then cause
-- driver conflicts on these pins!!
-----------------------------------------------------------------------------
gpio_in(11 downto 8) <= Switch;
-----------------------------------------------------------------------------
-- Connect ROT_CENTER to GPIO(12)
-----------------------------------------------------------------------------
gpio_in(12) <= ROT_CENTER;
-- gen_sw_3state: for k in 8 to 11 generate
-- SW(k-8) <= gpio_out(k) when gpio_out_enb(k) = '1' else 'Z';
-- end generate;
-----------------------------------------------------------------------------
-- Instantiation of top-level components (assumed to be in library work)
-----------------------------------------------------------------------------
-- CPU ----------------------------------------------------------------------
i_cpu: entity work.cpu
port map(
rst => rst,
clk => clk,
bus_in => bus2cpu,
bus_out => cpu2bus
);
-- BUS ----------------------------------------------------------------------
i_bus: entity work.buss
port map(
rst => rst,
clk => clk,
cpu_in => cpu2bus,
cpu_out => bus2cpu,
rom_in => rom2bus,
rom_out => bus2rom,
ram_in => ram2bus,
ram_out => bus2ram,
gpio_in => gpio2bus,
gpio_out => bus2gpio
);
-- ROM ----------------------------------------------------------------------
i_rom: entity work.rom
port map(
clk => clk,
bus_in => bus2rom,
bus_out => rom2bus
);
-- RAM ----------------------------------------------------------------------
i_ram: entity work.ram
port map(
clk => clk,
bus_in => bus2ram,
bus_out => ram2bus
);
-- GPIO ---------------------------------------------------------------------
i_gpio: entity work.gpio
port map(
rst => rst,
clk => clk,
bus_in => bus2gpio,
bus_out => gpio2bus,
gpio_in => gpio_in,
gpio_out => gpio_out,
gpio_out_enb => gpio_out_enb,
enc_a => ROT_A,
enc_b => ROT_B
);
end rtl;
|
gpl-2.0
|
8823bc69db13aa70b1b8289609fc7b61
| 0.410985 | 4.231523 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_wiz_0_0_pselect_f.vhd
| 1 | 12,547 |
-------------------------------------------------------------------------------
-- system_xadc_wiz_0_0_pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: system_xadc_wiz_0_0_pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: system_xadc_wiz_0_0_pselect_f.vhd
-- system_xadc_wiz_0_0_family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v3_30_a
-- ~~~~~~
-- - Changed proc_common library version to v3_30_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library work;
use work.system_xadc_wiz_0_0_family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity system_xadc_wiz_0_0_pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity system_xadc_wiz_0_0_pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of system_xadc_wiz_0_0_pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS=0 -- LUT not supported.
or C_AB <= NLS; -- Just one LUT
-- needed.
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "system_xadc_wiz_0_0_pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
INFERRED_GEN : if (USE_INFERRED = TRUE ) generate
begin
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end generate INFERRED_GEN;
------------------------------------------------------------------------------
-- Build a structural decoder using the fast carry chain
------------------------------------------------------------------------------
GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate
constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS;
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
begin
carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain.
CS <= carry_chain(0); -- Assign end of carry chain to output.
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST
begin
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
constant NI : natural := i;
constant BTL : positive := min(NLS, C_AB-NI*NLS);-- num Bits This LUT
begin
lut_out(i) <= bo2sl(A(NI*NLS to NI*NLS+BTL-1) = -- LUT
BAR(NI*NLS to NI*NLS+BTL-1));
MUXCY_I: component MUXCY -- MUXCY
port map (
O => carry_chain(i),
CI => carry_chain(i+1),
DI => '0',
S => lut_out(i)
);
end generate GEN_DECODE;
end generate XST_WA;
end generate GEN_STRUCTURAL_A;
end imp;
|
apache-2.0
|
f4a4fd891b7fcddccb8628a5c577b8ce
| 0.413166 | 5.2874 | false | false | false | false |
aggroskater/ee4321-vhdl-digital-design
|
Project-3-4bit-CLA/cla_4_bit.vhd
| 1 | 1,596 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cla_4_bit is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
Sum : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end cla_4_bit;
architecture Behavioral of cla_4_bit is
--these wire the output of the CLL to each FA.
signal Cin1, Cin2, Cin3 : std_logic:='0';
--these wire the result of the add/sub check to each FA.
signal b0, b1, b2, b3 : std_logic:='0';
signal Bxor : std_logic_vector (3 downto 0);
begin
--add/sub control; this flips B if necessary.
Bxor(0) <= B(0) XOR Cin;
Bxor(1) <= B(1) XOR Cin;
Bxor(2) <= B(2) XOR Cin;
Bxor(3) <= B(3) XOR Cin;
--Carry-Look-Ahead Logic
CLL0: entity work.cl_logic port map (A,Bxor,Cin,Cin1,Cin2,Cin3,Cout);
--Full adders; for CLA, then individual Couts dangle; they are
--handled by the CLL module and are technically unnecessary for
--the CLA implementation.
FA0: entity work.full_adder_1_bit port map (A(0),Bxor(0),Cin,open,Sum(0));
FA1: entity work.full_adder_1_bit port map (A(1),Bxor(1),Cin1,open,Sum(1));
FA2: entity work.full_adder_1_bit port map (A(2),Bxor(2),Cin2,open,Sum(2));
FA3: entity work.full_adder_1_bit port map (A(3),Bxor(3),Cin3,open,Sum(3));
end Behavioral;
|
agpl-3.0
|
69e20e9cf0d2907535e53a36d4bbff33
| 0.683584 | 2.923077 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_gpio_led_0/sim/system_axi_gpio_led_0.vhd
| 1 | 9,607 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_13;
USE axi_gpio_v2_0_13.axi_gpio;
ENTITY system_axi_gpio_led_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END system_axi_gpio_led_0;
ARCHITECTURE system_axi_gpio_led_0_arch OF system_axi_gpio_led_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_gpio_led_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 12,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 1,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => gpio2_io_i,
gpio2_io_o => gpio2_io_o,
gpio2_io_t => gpio2_io_t
);
END system_axi_gpio_led_0_arch;
|
apache-2.0
|
ad39bf8cea73a412f7d0b2d6cb307b6a
| 0.680129 | 3.195941 | false | false | false | false |
jeffmagina/ECE368
|
Lab1/SevenSegment/SevenSeg_toplevel.vhd
| 2 | 1,711 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: SevenSeg_toplevel
-- Project Name: SevenSegmentDisplay
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
--
-- Description: 7-segment toplevel example
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
entity SSeg_toplevel is
port (
CLK : in STD_LOGIC; -- 50 MHz input
SW : in STD_LOGIC_VECTOR (7 downto 0);
BTN : in STD_LOGIC;
SEG : out STD_LOGIC_VECTOR (6 downto 0);
DP : out STD_LOGIC;
AN : out STD_LOGIC_VECTOR (3 downto 0)
);
end SSeg_toplevel;
architecture Structural of SSeg_toplevel is
signal s2 : STD_LOGIC_VECTOR (3 downto 0) := "1100";
signal s3 : STD_LOGIC_VECTOR (3 downto 0) := "1110";
signal enl : STD_LOGIC := '1';
signal dpc : STD_LOGIC_VECTOR (3 downto 0) := "1111";
signal cen : STD_LOGIC := '0';
begin
----- Structural Components: -----
SSeg: entity work.SSegDriver
port map( CLK => CLK,
RST => BTN,
EN => enl,
SEG_0 => SW(3 downto 0),
SEG_1 => SW(7 downto 4),
SEG_2 => s2,
SEG_3 => s3,
DP_CTRL => dpc,
COL_EN => cen,
SEG_OUT => SEG,
DP_OUT => DP,
AN_OUT => AN);
----- End Structural Components -----
end Structural;
|
mit
|
69f3aa50e9f7236a1a5a6e2a02f3bfe0
| 0.516657 | 3.836323 | false | false | false | false |
KPU-RISC/KPU
|
VHDL/Xor8Bits.vhd
| 1 | 1,460 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/20/2015 05:26:44 PM
-- Design Name:
-- Module Name: Xor8Bits - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Xor8Bit is
Port
(
InputA : in BIT_VECTOR(7 downto 0); -- 1st 8-bit input value
InputB : in BIT_VECTOR(7 downto 0); -- 2nd 8-bit input value
Output : out BIT_VECTOR(7 downto 0) -- 8-bit output value
);
end Xor8Bit;
architecture Behavioral of Xor8Bit is
begin
Output(0) <= InputA(0) xor InputB(0);
Output(1) <= InputA(1) xor InputB(1);
Output(2) <= InputA(2) xor InputB(2);
Output(3) <= InputA(3) xor InputB(3);
Output(4) <= InputA(4) xor InputB(4);
Output(5) <= InputA(5) xor InputB(5);
Output(6) <= InputA(6) xor InputB(6);
Output(7) <= InputA(7) xor InputB(7);
end Behavioral;
|
mit
|
4101956135a66e5c9fecdeefe9a633eb
| 0.578767 | 3.640898 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_mdm_1_0/system_mdm_1_0_sim_netlist.vhdl
| 1 | 521,036 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:46:23 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_mdm_1_0/system_mdm_1_0_sim_netlist.vhdl
-- Design : system_mdm_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_mdm_1_0_MB_BSCANE2 is
port (
Dbg_Capture_0 : out STD_LOGIC;
drck_i : out STD_LOGIC;
Ext_JTAG_RESET : out STD_LOGIC;
sel : out STD_LOGIC;
\Use_Serial_Unified_Completion.count_reg[5]\ : out STD_LOGIC;
Ext_JTAG_TDI : out STD_LOGIC;
Dbg_Update_31 : out STD_LOGIC;
\Use_Serial_Unified_Completion.count_reg[5]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
shift_n_reset : out STD_LOGIC;
AR : out STD_LOGIC_VECTOR ( 0 to 0 );
\Use_Serial_Unified_Completion.count_reg[5]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\shift_Count_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Use_Serial_Unified_Completion.mb_instr_overrun_reg\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
tdo : in STD_LOGIC;
\p_20_out__0\ : in STD_LOGIC;
\p_43_out__0\ : in STD_LOGIC;
Scan_Reset : in STD_LOGIC;
Scan_Reset_Sel : in STD_LOGIC;
\Use_Serial_Unified_Completion.count_reg[5]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
Dbg_TDO_0 : in STD_LOGIC;
\Use_Serial_Unified_Completion.sample_1_reg[15]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_mdm_1_0_MB_BSCANE2 : entity is "MB_BSCANE2";
end system_mdm_1_0_MB_BSCANE2;
architecture STRUCTURE of system_mdm_1_0_MB_BSCANE2 is
signal \^dbg_capture_0\ : STD_LOGIC;
signal \Use_E2.BSCANE2_I_n_3\ : STD_LOGIC;
signal \Use_E2.BSCANE2_I_n_6\ : STD_LOGIC;
signal \Use_E2.BSCANE2_I_n_8\ : STD_LOGIC;
signal \^use_serial_unified_completion.count_reg[5]\ : STD_LOGIC;
signal \^sel\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \Use_BSCAN.Config_Reg[30]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \Use_BSCAN.PORT_Selector[3]_i_1\ : label is "soft_lutpair18";
attribute box_type : string;
attribute box_type of \Use_E2.BSCANE2_I\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.completion_status[15]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.completion_status[15]_i_2\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.count[0]__0_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.count[5]_i_1\ : label is "soft_lutpair19";
begin
Dbg_Capture_0 <= \^dbg_capture_0\;
\Use_Serial_Unified_Completion.count_reg[5]\ <= \^use_serial_unified_completion.count_reg[5]\;
sel <= \^sel\;
\Use_BSCAN.Config_Reg[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => Scan_Reset,
I1 => Scan_Reset_Sel,
I2 => \^use_serial_unified_completion.count_reg[5]\,
O => shift_n_reset
);
\Use_BSCAN.PORT_Selector[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => Scan_Reset,
I1 => Scan_Reset_Sel,
I2 => \^sel\,
O => AR(0)
);
\Use_E2.BSCANE2_I\: unisim.vcomponents.BSCANE2
generic map(
DISABLE_JTAG => "FALSE",
JTAG_CHAIN => 2
)
port map (
CAPTURE => \^dbg_capture_0\,
DRCK => drck_i,
RESET => Ext_JTAG_RESET,
RUNTEST => \Use_E2.BSCANE2_I_n_3\,
SEL => \^sel\,
SHIFT => \^use_serial_unified_completion.count_reg[5]\,
TCK => \Use_E2.BSCANE2_I_n_6\,
TDI => Ext_JTAG_TDI,
TDO => tdo,
TMS => \Use_E2.BSCANE2_I_n_8\,
UPDATE => Dbg_Update_31
);
\Use_Serial_Unified_Completion.completion_status[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \p_43_out__0\,
I1 => \^dbg_capture_0\,
I2 => \^use_serial_unified_completion.count_reg[5]\,
O => E(0)
);
\Use_Serial_Unified_Completion.completion_status[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^dbg_capture_0\,
I1 => \Use_Serial_Unified_Completion.sample_1_reg[15]\(0),
O => D(0)
);
\Use_Serial_Unified_Completion.count[0]__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \p_20_out__0\,
I1 => \^dbg_capture_0\,
I2 => \^use_serial_unified_completion.count_reg[5]\,
O => \Use_Serial_Unified_Completion.count_reg[5]_0\(0)
);
\Use_Serial_Unified_Completion.count[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^dbg_capture_0\,
I1 => \Use_Serial_Unified_Completion.count_reg[5]_2\(0),
O => \Use_Serial_Unified_Completion.count_reg[5]_1\(0)
);
\Use_Serial_Unified_Completion.mb_instr_overrun_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Dbg_TDO_0,
I1 => \^dbg_capture_0\,
O => \Use_Serial_Unified_Completion.mb_instr_overrun_reg\
);
\shift_Count[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^use_serial_unified_completion.count_reg[5]\,
I1 => Q(0),
O => \shift_Count_reg[0]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_mdm_1_0_MB_BUFG is
port (
Dbg_Clk_31 : out STD_LOGIC;
drck_i : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_mdm_1_0_MB_BUFG : entity is "MB_BUFG";
end system_mdm_1_0_MB_BUFG;
architecture STRUCTURE of system_mdm_1_0_MB_BUFG is
attribute box_type : string;
attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.BUFG
port map (
I => drck_i,
O => Dbg_Clk_31
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_mdm_1_0_MB_FDC_1 is
port (
D_0 : out STD_LOGIC;
Dbg_Shift_0 : out STD_LOGIC;
\p_20_out__0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
\Use_Serial_Unified_Completion.completion_block_reg\ : out STD_LOGIC;
sample_1 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Use_Serial_Unified_Completion.sample_reg[15]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\shifting_Data1__0\ : out STD_LOGIC;
Dbg_Reg_En_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
CE : out STD_LOGIC;
\command_1_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Use_Serial_Unified_Completion.mb_instr_overrun_reg\ : out STD_LOGIC;
\Use_Serial_Unified_Completion.mb_instr_overrun_reg_0\ : out STD_LOGIC;
\Use_Serial_Unified_Completion.mb_instr_error_reg\ : out STD_LOGIC;
\Use_Serial_Unified_Completion.mb_data_overrun_reg\ : out STD_LOGIC;
\completion_ctrl_reg[0]\ : out STD_LOGIC;
\Use_Serial_Unified_Completion.completion_block_reg_0\ : out STD_LOGIC;
Debug_Rst_i_reg : out STD_LOGIC;
Debug_SYS_Rst_i_reg : out STD_LOGIC;
Ext_NM_BRK_i_reg : out STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]\ : in STD_LOGIC;
sel_n : in STD_LOGIC;
\command_reg[6]\ : in STD_LOGIC;
\command_reg[4]\ : in STD_LOGIC;
\command_reg[0]\ : in STD_LOGIC;
sync : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]_0\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
\Use_Serial_Unified_Completion.completion_block_reg_1\ : in STD_LOGIC;
\command_reg[7]\ : in STD_LOGIC;
\Use_Serial_Unified_Completion.completion_status_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
\Use_Serial_Unified_Completion.completion_status_reg[2]\ : in STD_LOGIC;
\Use_Serial_Unified_Completion.completion_status_reg[3]\ : in STD_LOGIC;
\Use_Serial_Unified_Completion.completion_status_reg[4]\ : in STD_LOGIC;
\Use_Serial_Unified_Completion.completion_status_reg[5]\ : in STD_LOGIC;
\Use_Serial_Unified_Completion.completion_status_reg[7]\ : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]_1\ : in STD_LOGIC;
\Use_Serial_Unified_Completion.sample_reg[15]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\tdi_shifter_reg[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\Use_BSCAN.PORT_Selector_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]_2\ : in STD_LOGIC;
\p_22_out__0\ : in STD_LOGIC;
\Use_Serial_Unified_Completion.count_reg[1]\ : in STD_LOGIC;
Dbg_TDO_0 : in STD_LOGIC;
\Use_Serial_Unified_Completion.count_reg[5]\ : in STD_LOGIC;
completion_ctrl : in STD_LOGIC;
\Use_Serial_Unified_Completion.sample_1_reg[15]\ : in STD_LOGIC;
Dbg_Rst_0 : in STD_LOGIC;
Debug_SYS_Rst : in STD_LOGIC;
Ext_NM_BRK : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_mdm_1_0_MB_FDC_1 : entity is "MB_FDC_1";
end system_mdm_1_0_MB_FDC_1;
architecture STRUCTURE of system_mdm_1_0_MB_FDC_1 is
signal \^d_0\ : STD_LOGIC;
signal Dbg_Shift_31_INST_0_i_2_n_0 : STD_LOGIC;
signal Debug_Rst_i0 : STD_LOGIC;
signal \^use_serial_unified_completion.completion_block_reg\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.mb_instr_overrun_i_4_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.mb_instr_overrun_i_6_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.sample_1[15]_i_2_n_0\ : STD_LOGIC;
signal \Using_FPGA.Native_i_2_n_0\ : STD_LOGIC;
signal completion_ctrl0 : STD_LOGIC;
signal data_cmd_noblock : STD_LOGIC;
signal \^p_20_out__0\ : STD_LOGIC;
signal \^sample_1\ : STD_LOGIC;
signal \^shifting_data1__0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \Dbg_Reg_En_0[0]_INST_0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \Dbg_Reg_En_0[1]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \Dbg_Reg_En_0[2]_INST_0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \Dbg_Reg_En_0[3]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \Dbg_Reg_En_0[4]_INST_0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \Dbg_Reg_En_0[5]_INST_0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \Dbg_Reg_En_0[6]_INST_0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \Dbg_Reg_En_0[7]_INST_0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of Dbg_Shift_31_INST_0_i_2 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Debug_Rst_i_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of Ext_NM_BRK_i_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of Ext_NM_BRK_i_i_3 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.completion_status[0]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.completion_status[15]_i_3\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.completion_status[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.mb_instr_overrun_i_5\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.sample[13]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.sample[14]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.sample_1[15]_i_2\ : label is "soft_lutpair9";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDC_1";
attribute box_type : string;
attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \Using_FPGA.Native_i_1__0\ : label is "soft_lutpair9";
begin
D_0 <= \^d_0\;
\Use_Serial_Unified_Completion.completion_block_reg\ <= \^use_serial_unified_completion.completion_block_reg\;
\p_20_out__0\ <= \^p_20_out__0\;
sample_1 <= \^sample_1\;
\shifting_Data1__0\ <= \^shifting_data1__0\;
\Dbg_Reg_En_0[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
I1 => data_cmd_noblock,
I2 => Q(7),
O => Dbg_Reg_En_0(0)
);
\Dbg_Reg_En_0[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
I1 => data_cmd_noblock,
I2 => Q(6),
O => Dbg_Reg_En_0(1)
);
\Dbg_Reg_En_0[2]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
I1 => data_cmd_noblock,
I2 => Q(5),
O => Dbg_Reg_En_0(2)
);
\Dbg_Reg_En_0[3]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
I1 => data_cmd_noblock,
I2 => Q(4),
O => Dbg_Reg_En_0(3)
);
\Dbg_Reg_En_0[4]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
I1 => data_cmd_noblock,
I2 => Q(3),
O => Dbg_Reg_En_0(4)
);
\Dbg_Reg_En_0[5]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
I1 => data_cmd_noblock,
I2 => Q(2),
O => Dbg_Reg_En_0(5)
);
\Dbg_Reg_En_0[6]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
I1 => data_cmd_noblock,
I2 => Q(1),
O => Dbg_Reg_En_0(6)
);
\Dbg_Reg_En_0[7]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
I1 => data_cmd_noblock,
I2 => Q(0),
O => Dbg_Reg_En_0(7)
);
Dbg_Shift_31_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF7FF00000000"
)
port map (
I0 => \command_reg[6]\,
I1 => Dbg_Shift_31_INST_0_i_2_n_0,
I2 => \command_reg[4]\,
I3 => \command_reg[0]\,
I4 => sync,
I5 => \Use_BSCAN.PORT_Selector_reg[0]_0\,
O => Dbg_Shift_0
);
Dbg_Shift_31_INST_0_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => data_cmd_noblock,
I1 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
O => Dbg_Shift_31_INST_0_i_2_n_0
);
Debug_Rst_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \tdi_shifter_reg[0]\(7),
I1 => Debug_Rst_i0,
I2 => Dbg_Rst_0,
O => Debug_Rst_i_reg
);
Debug_SYS_Rst_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \tdi_shifter_reg[0]\(6),
I1 => Debug_Rst_i0,
I2 => Debug_SYS_Rst,
O => Debug_SYS_Rst_i_reg
);
Ext_NM_BRK_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \tdi_shifter_reg[0]\(4),
I1 => Debug_Rst_i0,
I2 => Ext_NM_BRK,
O => Ext_NM_BRK_i_reg
);
Ext_NM_BRK_i_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00020000"
)
port map (
I0 => data_cmd_noblock,
I1 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
I2 => Q(1),
I3 => Q(5),
I4 => \command_reg[7]\,
O => Debug_Rst_i0
);
\Use_Serial_Unified_Completion.completion_block_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF5FFF5F000C0000"
)
port map (
I0 => \Use_BSCAN.PORT_Selector_reg[0]_1\,
I1 => \Use_Serial_Unified_Completion.sample_1_reg[15]\,
I2 => completion_ctrl0,
I3 => \^use_serial_unified_completion.completion_block_reg\,
I4 => completion_ctrl,
I5 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
O => \Use_Serial_Unified_Completion.completion_block_reg_0\
);
\Use_Serial_Unified_Completion.completion_status[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8F88"
)
port map (
I0 => \^use_serial_unified_completion.completion_block_reg\,
I1 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(1),
I2 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(0),
I3 => \^sample_1\,
O => D(0)
);
\Use_Serial_Unified_Completion.completion_status[15]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => Q(1),
I1 => Q(5),
I2 => data_cmd_noblock,
I3 => \command_reg[7]\,
O => \^use_serial_unified_completion.completion_block_reg\
);
\Use_Serial_Unified_Completion.completion_status[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF606060"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(1),
I1 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(0),
I2 => \^sample_1\,
I3 => \^use_serial_unified_completion.completion_block_reg\,
I4 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(2),
O => D(1)
);
\Use_Serial_Unified_Completion.completion_status[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF6A006A006A00"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(2),
I1 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(1),
I2 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(0),
I3 => \^sample_1\,
I4 => \^use_serial_unified_completion.completion_block_reg\,
I5 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(3),
O => D(2)
);
\Use_Serial_Unified_Completion.completion_status[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF606060"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(3),
I1 => \Use_Serial_Unified_Completion.completion_status_reg[2]\,
I2 => \^sample_1\,
I3 => \^use_serial_unified_completion.completion_block_reg\,
I4 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(4),
O => D(3)
);
\Use_Serial_Unified_Completion.completion_status[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF606060"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(4),
I1 => \Use_Serial_Unified_Completion.completion_status_reg[3]\,
I2 => \^sample_1\,
I3 => \^use_serial_unified_completion.completion_block_reg\,
I4 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(5),
O => D(4)
);
\Use_Serial_Unified_Completion.completion_status[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF484848"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(5),
I1 => \^sample_1\,
I2 => \Use_Serial_Unified_Completion.completion_status_reg[4]\,
I3 => \^use_serial_unified_completion.completion_block_reg\,
I4 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(6),
O => D(5)
);
\Use_Serial_Unified_Completion.completion_status[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF484848"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(6),
I1 => \^sample_1\,
I2 => \Use_Serial_Unified_Completion.completion_status_reg[5]\,
I3 => \^use_serial_unified_completion.completion_block_reg\,
I4 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(7),
O => D(6)
);
\Use_Serial_Unified_Completion.completion_status[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF488848884888"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(7),
I1 => \^sample_1\,
I2 => \Use_Serial_Unified_Completion.completion_status_reg[5]\,
I3 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(6),
I4 => \^use_serial_unified_completion.completion_block_reg\,
I5 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(8),
O => D(7)
);
\Use_Serial_Unified_Completion.completion_status[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF484848"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(8),
I1 => \^sample_1\,
I2 => \Use_Serial_Unified_Completion.completion_status_reg[7]\,
I3 => \^use_serial_unified_completion.completion_block_reg\,
I4 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(9),
O => D(8)
);
\Use_Serial_Unified_Completion.completion_status[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0CA00CA00CA00FA0"
)
port map (
I0 => \Use_BSCAN.PORT_Selector_reg[0]_0\,
I1 => completion_ctrl0,
I2 => \^use_serial_unified_completion.completion_block_reg\,
I3 => \Use_BSCAN.PORT_Selector_reg[0]_1\,
I4 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
I5 => data_cmd_noblock,
O => E(0)
);
\Use_Serial_Unified_Completion.completion_status[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF488848884888"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(9),
I1 => \^sample_1\,
I2 => \Use_Serial_Unified_Completion.completion_status_reg[7]\,
I3 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(8),
I4 => \^use_serial_unified_completion.completion_block_reg\,
I5 => \Use_Serial_Unified_Completion.completion_status_reg[10]\(10),
O => D(9)
);
\Use_Serial_Unified_Completion.completion_status[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000000000000"
)
port map (
I0 => \Use_Serial_Unified_Completion.sample_1[15]_i_2_n_0\,
I1 => Q(1),
I2 => Q(0),
I3 => Q(3),
I4 => Q(2),
I5 => \command_reg[0]\,
O => completion_ctrl0
);
\Use_Serial_Unified_Completion.count[0]__0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000080000000000"
)
port map (
I0 => Q(2),
I1 => Q(1),
I2 => Q(0),
I3 => Dbg_Shift_31_INST_0_i_2_n_0,
I4 => \command_reg[4]\,
I5 => \command_reg[0]\,
O => \^p_20_out__0\
);
\Use_Serial_Unified_Completion.count[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000040000000000"
)
port map (
I0 => Q(1),
I1 => Q(2),
I2 => Q(0),
I3 => Dbg_Shift_31_INST_0_i_2_n_0,
I4 => \command_reg[4]\,
I5 => \command_reg[0]\,
O => \^shifting_data1__0\
);
\Use_Serial_Unified_Completion.mb_data_overrun_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"113F333F11000000"
)
port map (
I0 => Dbg_TDO_0,
I1 => \Use_BSCAN.PORT_Selector_reg[0]_1\,
I2 => completion_ctrl0,
I3 => \^p_20_out__0\,
I4 => \Use_Serial_Unified_Completion.count_reg[5]\,
I5 => \Use_Serial_Unified_Completion.sample_reg[15]_0\(2),
O => \Use_Serial_Unified_Completion.mb_data_overrun_reg\
);
\Use_Serial_Unified_Completion.mb_instr_error_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0BFFFA0A08000"
)
port map (
I0 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
I1 => \p_22_out__0\,
I2 => \^shifting_data1__0\,
I3 => \Use_Serial_Unified_Completion.count_reg[1]\,
I4 => \Use_Serial_Unified_Completion.mb_instr_overrun_i_4_n_0\,
I5 => \Use_Serial_Unified_Completion.sample_reg[15]_0\(1),
O => \Use_Serial_Unified_Completion.mb_instr_error_reg\
);
\Use_Serial_Unified_Completion.mb_instr_overrun_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0FFBFA0A00080"
)
port map (
I0 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
I1 => \p_22_out__0\,
I2 => \^shifting_data1__0\,
I3 => \Use_Serial_Unified_Completion.count_reg[1]\,
I4 => \Use_Serial_Unified_Completion.mb_instr_overrun_i_4_n_0\,
I5 => \Use_Serial_Unified_Completion.sample_reg[15]_0\(0),
O => \Use_Serial_Unified_Completion.mb_instr_overrun_reg_0\
);
\Use_Serial_Unified_Completion.mb_instr_overrun_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00000008000000"
)
port map (
I0 => \command_reg[6]\,
I1 => Dbg_Shift_31_INST_0_i_2_n_0,
I2 => \command_reg[4]\,
I3 => \command_reg[0]\,
I4 => \Use_BSCAN.PORT_Selector_reg[0]_1\,
I5 => \Use_Serial_Unified_Completion.mb_instr_overrun_i_6_n_0\,
O => \Use_Serial_Unified_Completion.mb_instr_overrun_i_4_n_0\
);
\Use_Serial_Unified_Completion.mb_instr_overrun_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
I1 => data_cmd_noblock,
I2 => Q(5),
I3 => Q(3),
O => \Use_Serial_Unified_Completion.mb_instr_overrun_reg\
);
\Use_Serial_Unified_Completion.mb_instr_overrun_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080000000000000"
)
port map (
I0 => Q(2),
I1 => Q(3),
I2 => Q(0),
I3 => Q(1),
I4 => data_cmd_noblock,
I5 => Q(5),
O => \Use_Serial_Unified_Completion.mb_instr_overrun_i_6_n_0\
);
\Use_Serial_Unified_Completion.sample[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \Use_Serial_Unified_Completion.sample_reg[15]_0\(3),
I1 => \^sample_1\,
O => \Use_Serial_Unified_Completion.sample_reg[15]\(0)
);
\Use_Serial_Unified_Completion.sample[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \Use_Serial_Unified_Completion.sample_reg[15]_0\(4),
I1 => \^sample_1\,
O => \Use_Serial_Unified_Completion.sample_reg[15]\(1)
);
\Use_Serial_Unified_Completion.sample[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \Use_Serial_Unified_Completion.sample_reg[15]_0\(5),
I1 => \^sample_1\,
O => \Use_Serial_Unified_Completion.sample_reg[15]\(2)
);
\Use_Serial_Unified_Completion.sample_1[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFDF7FFFFFFFFFFF"
)
port map (
I0 => \command_reg[0]\,
I1 => Q(2),
I2 => Q(3),
I3 => Q(0),
I4 => Q(1),
I5 => \Use_Serial_Unified_Completion.sample_1[15]_i_2_n_0\,
O => \^sample_1\
);
\Use_Serial_Unified_Completion.sample_1[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => Q(5),
I1 => data_cmd_noblock,
O => \Use_Serial_Unified_Completion.sample_1[15]_i_2_n_0\
);
\Using_FPGA.Native\: unisim.vcomponents.FDCE
generic map(
INIT => '0',
IS_C_INVERTED => '1'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => '1',
CLR => sel_n,
D => \^d_0\,
Q => data_cmd_noblock
);
\Using_FPGA.Native_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000800"
)
port map (
I0 => \Using_FPGA.Native_i_2_n_0\,
I1 => \tdi_shifter_reg[0]\(3),
I2 => \tdi_shifter_reg[0]\(2),
I3 => \tdi_shifter_reg[0]\(0),
I4 => \tdi_shifter_reg[0]\(1),
O => CE
);
\Using_FPGA.Native_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => data_cmd_noblock,
O => \^d_0\
);
\Using_FPGA.Native_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000002000000000"
)
port map (
I0 => \tdi_shifter_reg[0]\(5),
I1 => \tdi_shifter_reg[0]\(4),
I2 => \tdi_shifter_reg[0]\(6),
I3 => \tdi_shifter_reg[0]\(7),
I4 => \Use_Serial_Unified_Completion.completion_block_reg_1\,
I5 => data_cmd_noblock,
O => \Using_FPGA.Native_i_2_n_0\
);
\command_1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000001000000"
)
port map (
I0 => \Use_BSCAN.PORT_Selector_reg[3]\(2),
I1 => \Use_BSCAN.PORT_Selector_reg[3]\(3),
I2 => \Use_BSCAN.PORT_Selector_reg[3]\(1),
I3 => \Use_BSCAN.PORT_Selector_reg[3]\(0),
I4 => sel,
I5 => Dbg_Shift_31_INST_0_i_2_n_0,
O => \command_1_reg[7]\(0)
);
\completion_ctrl[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \tdi_shifter_reg[0]\(7),
I1 => completion_ctrl0,
I2 => completion_ctrl,
O => \completion_ctrl_reg[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_mdm_1_0_MB_FDRE_1 is
port (
sync : out STD_LOGIC;
\p_22_out__0\ : out STD_LOGIC;
D_0 : in STD_LOGIC;
CE : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]\ : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]_0\ : in STD_LOGIC;
\command_reg[0]\ : in STD_LOGIC;
\Use_Serial_Unified_Completion.completion_block_reg\ : in STD_LOGIC;
\command_reg[6]\ : in STD_LOGIC;
\Use_Serial_Unified_Completion.count_reg[0]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_mdm_1_0_MB_FDRE_1 : entity is "MB_FDRE_1";
end system_mdm_1_0_MB_FDRE_1;
architecture STRUCTURE of system_mdm_1_0_MB_FDRE_1 is
signal \^sync\ : STD_LOGIC;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDRE_1";
attribute box_type : string;
attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
sync <= \^sync\;
\Use_Serial_Unified_Completion.mb_instr_overrun_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008AAAAAAA"
)
port map (
I0 => \Use_BSCAN.PORT_Selector_reg[0]_0\,
I1 => \^sync\,
I2 => \command_reg[0]\,
I3 => \Use_Serial_Unified_Completion.completion_block_reg\,
I4 => \command_reg[6]\,
I5 => \Use_Serial_Unified_Completion.count_reg[0]\,
O => \p_22_out__0\
);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '1'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => CE,
D => '1',
Q => \^sync\,
R => D_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_mdm_1_0_MB_SRL16E is
port (
tdo : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
\Use_BSCAN.PORT_Selector_reg[0]\ : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[2]\ : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\command_reg[0]\ : in STD_LOGIC;
\command_reg[5]\ : in STD_LOGIC;
\command_reg[0]_0\ : in STD_LOGIC;
\command_reg[3]\ : in STD_LOGIC;
\command_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Dbg_TDO_0 : in STD_LOGIC;
\Use_Serial_Unified_Completion.completion_status_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
config_TDO_2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_mdm_1_0_MB_SRL16E : entity is "MB_SRL16E";
end system_mdm_1_0_MB_SRL16E;
architecture STRUCTURE of system_mdm_1_0_MB_SRL16E is
signal \Use_E2.BSCANE2_I_i_4_n_0\ : STD_LOGIC;
signal \Use_E2.BSCANE2_I_i_8_n_0\ : STD_LOGIC;
signal \Use_unisim.MB_SRL16E_I1_n_0\ : STD_LOGIC;
attribute box_type : string;
attribute box_type of \Use_unisim.MB_SRL16E_I1\ : label is "PRIMITIVE";
attribute srl_name : string;
attribute srl_name of \Use_unisim.MB_SRL16E_I1\ : label is "U0/\MDM_Core_I1/JTAG_CONTROL_I/Use_Config_SRL16E.SRL16E_1/Use_unisim.MB_SRL16E_I1 ";
begin
\Use_E2.BSCANE2_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEAEAEAEAEA"
)
port map (
I0 => \Use_BSCAN.PORT_Selector_reg[2]\,
I1 => \Use_BSCAN.PORT_Selector_reg[0]_0\(0),
I2 => \command_reg[0]\,
I3 => \Use_E2.BSCANE2_I_i_4_n_0\,
I4 => \command_reg[5]\,
I5 => \command_reg[0]_0\,
O => tdo
);
\Use_E2.BSCANE2_I_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEEEBAAA"
)
port map (
I0 => \command_reg[3]\,
I1 => \command_reg[4]\(0),
I2 => \command_reg[4]\(2),
I3 => \Use_E2.BSCANE2_I_i_8_n_0\,
I4 => Dbg_TDO_0,
O => \Use_E2.BSCANE2_I_i_4_n_0\
);
\Use_E2.BSCANE2_I_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"FACA0ACA"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_status_reg[0]\(0),
I1 => \Use_unisim.MB_SRL16E_I1_n_0\,
I2 => \command_reg[4]\(1),
I3 => Q(4),
I4 => config_TDO_2,
O => \Use_E2.BSCANE2_I_i_8_n_0\
);
\Use_unisim.MB_SRL16E_I1\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0167",
IS_CLK_INVERTED => '0'
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => '0',
CLK => \Use_BSCAN.PORT_Selector_reg[0]\,
D => '0',
Q => \Use_unisim.MB_SRL16E_I1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_mdm_1_0_MB_SRL16E__parameterized1\ is
port (
config_TDO_2 : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\Use_BSCAN.PORT_Selector_reg[0]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_mdm_1_0_MB_SRL16E__parameterized1\ : entity is "MB_SRL16E";
end \system_mdm_1_0_MB_SRL16E__parameterized1\;
architecture STRUCTURE of \system_mdm_1_0_MB_SRL16E__parameterized1\ is
attribute box_type : string;
attribute box_type of \Use_unisim.MB_SRL16E_I1\ : label is "PRIMITIVE";
attribute srl_name : string;
attribute srl_name of \Use_unisim.MB_SRL16E_I1\ : label is "U0/\MDM_Core_I1/JTAG_CONTROL_I/Use_Config_SRL16E.SRL16E_2/Use_unisim.MB_SRL16E_I1 ";
begin
\Use_unisim.MB_SRL16E_I1\: unisim.vcomponents.SRL16E
generic map(
INIT => X"4287",
IS_CLK_INVERTED => '0'
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => '0',
CLK => \Use_BSCAN.PORT_Selector_reg[0]\,
D => '0',
Q => config_TDO_2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_mdm_1_0_MB_SRL16E__parameterized3\ is
port (
\tdi_shifter_reg[0]\ : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
\Use_BSCAN.PORT_Selector_reg[0]\ : in STD_LOGIC;
\command_reg[1]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
ID_TDO_2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_mdm_1_0_MB_SRL16E__parameterized3\ : entity is "MB_SRL16E";
end \system_mdm_1_0_MB_SRL16E__parameterized3\;
architecture STRUCTURE of \system_mdm_1_0_MB_SRL16E__parameterized3\ is
signal Q0_out : STD_LOGIC;
signal \Use_E2.BSCANE2_I_i_9_n_0\ : STD_LOGIC;
attribute box_type : string;
attribute box_type of \Use_unisim.MB_SRL16E_I1\ : label is "PRIMITIVE";
attribute srl_name : string;
attribute srl_name of \Use_unisim.MB_SRL16E_I1\ : label is "U0/\MDM_Core_I1/JTAG_CONTROL_I/Use_ID_SRL16E.SRL16E_ID_1/Use_unisim.MB_SRL16E_I1 ";
begin
\Use_E2.BSCANE2_I_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFB88CC"
)
port map (
I0 => \command_reg[1]\(2),
I1 => \command_reg[1]\(1),
I2 => \command_reg[1]\(3),
I3 => \command_reg[1]\(4),
I4 => \command_reg[1]\(5),
I5 => \Use_E2.BSCANE2_I_i_9_n_0\,
O => \tdi_shifter_reg[0]\
);
\Use_E2.BSCANE2_I_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"0101010000000100"
)
port map (
I0 => \command_reg[1]\(1),
I1 => \command_reg[1]\(0),
I2 => \command_reg[1]\(2),
I3 => Q0_out,
I4 => Q(4),
I5 => ID_TDO_2,
O => \Use_E2.BSCANE2_I_i_9_n_0\
);
\Use_unisim.MB_SRL16E_I1\: unisim.vcomponents.SRL16E
generic map(
INIT => X"4443",
IS_CLK_INVERTED => '0'
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => '0',
CLK => \Use_BSCAN.PORT_Selector_reg[0]\,
D => '0',
Q => Q0_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_mdm_1_0_MB_SRL16E__parameterized5\ is
port (
ID_TDO_2 : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\Use_BSCAN.PORT_Selector_reg[0]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_mdm_1_0_MB_SRL16E__parameterized5\ : entity is "MB_SRL16E";
end \system_mdm_1_0_MB_SRL16E__parameterized5\;
architecture STRUCTURE of \system_mdm_1_0_MB_SRL16E__parameterized5\ is
attribute box_type : string;
attribute box_type of \Use_unisim.MB_SRL16E_I1\ : label is "PRIMITIVE";
attribute srl_name : string;
attribute srl_name of \Use_unisim.MB_SRL16E_I1\ : label is "U0/\MDM_Core_I1/JTAG_CONTROL_I/Use_ID_SRL16E.SRL16E_ID_2/Use_unisim.MB_SRL16E_I1 ";
begin
\Use_unisim.MB_SRL16E_I1\: unisim.vcomponents.SRL16E
generic map(
INIT => X"584D",
IS_CLK_INVERTED => '0'
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => '0',
CLK => \Use_BSCAN.PORT_Selector_reg[0]\,
D => '0',
Q => ID_TDO_2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_mdm_1_0_JTAG_CONTROL is
port (
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
AR : out STD_LOGIC_VECTOR ( 0 to 0 );
Ext_NM_BRK : out STD_LOGIC;
Debug_SYS_Rst : out STD_LOGIC;
Dbg_Rst_0 : out STD_LOGIC;
Dbg_Shift_0 : out STD_LOGIC;
\p_20_out__0\ : out STD_LOGIC;
\Use_Serial_Unified_Completion.completion_block_reg_0\ : out STD_LOGIC;
Dbg_Reg_En_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
tdo : out STD_LOGIC;
\Use_Serial_Unified_Completion.count_reg[4]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Use_Serial_Unified_Completion.completion_status_reg[15]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Use_BSCAN.PORT_Selector_reg[0]\ : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]_0\ : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]_1\ : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]_2\ : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[2]\ : in STD_LOGIC;
Dbg_TDO_0 : in STD_LOGIC;
Scan_Reset : in STD_LOGIC;
Scan_Reset_Sel : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]_3\ : in STD_LOGIC;
Ext_JTAG_TDI : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 );
\command_reg[5]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\Use_Serial_Unified_Completion.count_reg[5]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\shift_Count_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_mdm_1_0_JTAG_CONTROL : entity is "JTAG_CONTROL";
end system_mdm_1_0_JTAG_CONTROL;
architecture STRUCTURE of system_mdm_1_0_JTAG_CONTROL is
signal A1 : STD_LOGIC;
signal A2 : STD_LOGIC;
signal A3 : STD_LOGIC;
signal \^ar\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal CE : STD_LOGIC;
signal D_0 : STD_LOGIC;
signal \^dbg_rst_0\ : STD_LOGIC;
signal Dbg_Shift_31_INST_0_i_1_n_0 : STD_LOGIC;
signal Dbg_Shift_31_INST_0_i_3_n_0 : STD_LOGIC;
signal Dbg_Shift_31_INST_0_i_4_n_0 : STD_LOGIC;
signal \^debug_sys_rst\ : STD_LOGIC;
signal \^ext_nm_brk\ : STD_LOGIC;
signal Ext_NM_BRK_i_i_4_n_0 : STD_LOGIC;
signal FDC_I_n_15 : STD_LOGIC;
signal FDC_I_n_16 : STD_LOGIC;
signal FDC_I_n_17 : STD_LOGIC;
signal FDC_I_n_18 : STD_LOGIC;
signal FDC_I_n_30 : STD_LOGIC;
signal FDC_I_n_31 : STD_LOGIC;
signal FDC_I_n_32 : STD_LOGIC;
signal FDC_I_n_33 : STD_LOGIC;
signal FDC_I_n_34 : STD_LOGIC;
signal FDC_I_n_35 : STD_LOGIC;
signal FDC_I_n_36 : STD_LOGIC;
signal FDC_I_n_37 : STD_LOGIC;
signal FDC_I_n_38 : STD_LOGIC;
signal ID_TDO_2 : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \Use_E2.BSCANE2_I_i_10_n_0\ : STD_LOGIC;
signal \Use_E2.BSCANE2_I_i_11_n_0\ : STD_LOGIC;
signal \Use_E2.BSCANE2_I_i_3_n_0\ : STD_LOGIC;
signal \Use_E2.BSCANE2_I_i_6_n_0\ : STD_LOGIC;
signal \Use_E2.BSCANE2_I_i_7_n_0\ : STD_LOGIC;
signal \Use_ID_SRL16E.SRL16E_ID_1_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.completion_block_i_2_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.completion_block_i_3_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.completion_block_i_4_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.completion_block_reg_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.completion_status[3]_i_2_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.completion_status[4]_i_2_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.completion_status[5]_i_2_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.completion_status[7]_i_2_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.completion_status[9]_i_4_n_0\ : STD_LOGIC;
signal \^use_serial_unified_completion.completion_status_reg[15]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \Use_Serial_Unified_Completion.count[0]__0_i_4_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.count[0]_i_1_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.count[1]_i_1_n_0\ : STD_LOGIC;
signal \^use_serial_unified_completion.count_reg[4]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \Use_Serial_Unified_Completion.count_reg__1\ : STD_LOGIC_VECTOR ( 0 to 4 );
signal \Use_Serial_Unified_Completion.count_reg_n_0_[0]\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.count_reg_n_0_[1]\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.mb_data_overrun_i_2_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.mb_data_overrun_i_3_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.mb_data_overrun_reg_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.mb_instr_error_reg_n_0\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.sample_1_reg_n_0_[10]\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.sample_1_reg_n_0_[11]\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.sample_1_reg_n_0_[12]\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.sample_1_reg_n_0_[13]\ : STD_LOGIC;
signal \Use_Serial_Unified_Completion.sample_1_reg_n_0_[14]\ : STD_LOGIC;
signal command : STD_LOGIC_VECTOR ( 0 to 7 );
signal \command[0]_i_1_n_0\ : STD_LOGIC;
signal command_1 : STD_LOGIC_VECTOR ( 0 to 7 );
signal command_10 : STD_LOGIC;
signal command_regn_0_0 : STD_LOGIC;
signal completion_ctrl : STD_LOGIC;
signal completion_status : STD_LOGIC_VECTOR ( 15 downto 0 );
signal config_TDO_2 : STD_LOGIC;
signal mb_instr_overrun : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 5 downto 1 );
signal p_0_in_1 : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 4 downto 1 );
signal p_1_in : STD_LOGIC_VECTOR ( 14 downto 0 );
signal \p_22_out__0\ : STD_LOGIC;
signal sample : STD_LOGIC_VECTOR ( 15 downto 13 );
attribute async_reg : string;
attribute async_reg of sample : signal is "true";
signal sample_1 : STD_LOGIC;
signal sel_n : STD_LOGIC;
signal sel_n_i_1_n_0 : STD_LOGIC;
signal \shift_Count_reg__0\ : STD_LOGIC_VECTOR ( 4 to 4 );
signal \shifting_Data1__0\ : STD_LOGIC;
signal sync : STD_LOGIC;
signal tdi_shifter0 : STD_LOGIC;
signal \tdi_shifter_reg_n_0_[1]\ : STD_LOGIC;
signal \tdi_shifter_reg_n_0_[2]\ : STD_LOGIC;
signal \tdi_shifter_reg_n_0_[3]\ : STD_LOGIC;
signal \tdi_shifter_reg_n_0_[4]\ : STD_LOGIC;
signal \tdi_shifter_reg_n_0_[5]\ : STD_LOGIC;
signal \tdi_shifter_reg_n_0_[6]\ : STD_LOGIC;
signal \tdi_shifter_reg_n_0_[7]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \Use_E2.BSCANE2_I_i_3\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \Use_E2.BSCANE2_I_i_6\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.completion_status[11]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.completion_status[12]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.completion_status[13]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.completion_status[14]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.completion_status[4]_i_2\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.completion_status[5]_i_2\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.count[0]__0_i_4\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.count[2]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.count[3]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \Use_Serial_Unified_Completion.mb_data_overrun_i_2\ : label is "soft_lutpair13";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Use_Serial_Unified_Completion.sample_reg[13]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Use_Serial_Unified_Completion.sample_reg[13]\ : label is "yes";
attribute ASYNC_REG_boolean of \Use_Serial_Unified_Completion.sample_reg[14]\ : label is std.standard.true;
attribute KEEP of \Use_Serial_Unified_Completion.sample_reg[14]\ : label is "yes";
attribute ASYNC_REG_boolean of \Use_Serial_Unified_Completion.sample_reg[15]\ : label is std.standard.true;
attribute KEEP of \Use_Serial_Unified_Completion.sample_reg[15]\ : label is "yes";
attribute SOFT_HLUTNM of \shift_Count[2]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \shift_Count[3]_i_1\ : label is "soft_lutpair10";
begin
AR(0) <= \^ar\(0);
Dbg_Rst_0 <= \^dbg_rst_0\;
Debug_SYS_Rst <= \^debug_sys_rst\;
Ext_NM_BRK <= \^ext_nm_brk\;
Q(0) <= \^q\(0);
\Use_Serial_Unified_Completion.completion_status_reg[15]_0\(0) <= \^use_serial_unified_completion.completion_status_reg[15]_0\(0);
\Use_Serial_Unified_Completion.count_reg[4]_0\(0) <= \^use_serial_unified_completion.count_reg[4]_0\(0);
Dbg_Shift_31_INST_0_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => command(6),
I1 => command(5),
I2 => command(7),
O => Dbg_Shift_31_INST_0_i_1_n_0
);
Dbg_Shift_31_INST_0_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => command(4),
I1 => command(2),
O => Dbg_Shift_31_INST_0_i_3_n_0
);
Dbg_Shift_31_INST_0_i_4: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => command(0),
I1 => command(1),
I2 => command(3),
O => Dbg_Shift_31_INST_0_i_4_n_0
);
Debug_Rst_i_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => '1',
CLR => \^ar\(0),
D => FDC_I_n_36,
Q => \^dbg_rst_0\
);
Debug_SYS_Rst_i_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => '1',
CLR => \^ar\(0),
D => FDC_I_n_37,
Q => \^debug_sys_rst\
);
Ext_NM_BRK_i_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => Scan_Reset,
I1 => Scan_Reset_Sel,
O => \^ar\(0)
);
Ext_NM_BRK_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => command(7),
I1 => command(4),
I2 => command(5),
I3 => command(3),
I4 => command(1),
I5 => command(0),
O => Ext_NM_BRK_i_i_4_n_0
);
Ext_NM_BRK_i_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => '1',
CLR => \^ar\(0),
D => FDC_I_n_38,
Q => \^ext_nm_brk\
);
FDC_I: entity work.system_mdm_1_0_MB_FDC_1
port map (
CE => CE,
D(9 downto 0) => p_1_in(9 downto 0),
D_0 => D_0,
Dbg_Reg_En_0(0 to 7) => Dbg_Reg_En_0(0 to 7),
Dbg_Rst_0 => \^dbg_rst_0\,
Dbg_Shift_0 => Dbg_Shift_0,
Dbg_TDO_0 => Dbg_TDO_0,
Debug_Rst_i_reg => FDC_I_n_36,
Debug_SYS_Rst => \^debug_sys_rst\,
Debug_SYS_Rst_i_reg => FDC_I_n_37,
E(0) => FDC_I_n_15,
Ext_NM_BRK => \^ext_nm_brk\,
Ext_NM_BRK_i_reg => FDC_I_n_38,
Q(7) => command(0),
Q(6) => command(1),
Q(5) => command(2),
Q(4) => command(3),
Q(3) => command(4),
Q(2) => command(5),
Q(1) => command(6),
Q(0) => command(7),
\Use_BSCAN.PORT_Selector_reg[0]\ => \Use_BSCAN.PORT_Selector_reg[0]\,
\Use_BSCAN.PORT_Selector_reg[0]_0\ => \Use_BSCAN.PORT_Selector_reg[0]_1\,
\Use_BSCAN.PORT_Selector_reg[0]_1\ => \Use_BSCAN.PORT_Selector_reg[0]_2\,
\Use_BSCAN.PORT_Selector_reg[0]_2\ => \Use_BSCAN.PORT_Selector_reg[0]_3\,
\Use_BSCAN.PORT_Selector_reg[3]\(3 downto 0) => \Use_BSCAN.PORT_Selector_reg[3]\(3 downto 0),
\Use_Serial_Unified_Completion.completion_block_reg\ => \Use_Serial_Unified_Completion.completion_block_reg_0\,
\Use_Serial_Unified_Completion.completion_block_reg_0\ => FDC_I_n_35,
\Use_Serial_Unified_Completion.completion_block_reg_1\ => \Use_Serial_Unified_Completion.completion_block_reg_n_0\,
\Use_Serial_Unified_Completion.completion_status_reg[10]\(10 downto 0) => completion_status(10 downto 0),
\Use_Serial_Unified_Completion.completion_status_reg[2]\ => \Use_Serial_Unified_Completion.completion_status[3]_i_2_n_0\,
\Use_Serial_Unified_Completion.completion_status_reg[3]\ => \Use_Serial_Unified_Completion.completion_status[4]_i_2_n_0\,
\Use_Serial_Unified_Completion.completion_status_reg[4]\ => \Use_Serial_Unified_Completion.completion_status[5]_i_2_n_0\,
\Use_Serial_Unified_Completion.completion_status_reg[5]\ => \Use_Serial_Unified_Completion.completion_status[7]_i_2_n_0\,
\Use_Serial_Unified_Completion.completion_status_reg[7]\ => \Use_Serial_Unified_Completion.completion_status[9]_i_4_n_0\,
\Use_Serial_Unified_Completion.count_reg[1]\ => \Use_Serial_Unified_Completion.count_reg_n_0_[1]\,
\Use_Serial_Unified_Completion.count_reg[5]\ => \Use_Serial_Unified_Completion.mb_data_overrun_i_2_n_0\,
\Use_Serial_Unified_Completion.mb_data_overrun_reg\ => FDC_I_n_33,
\Use_Serial_Unified_Completion.mb_instr_error_reg\ => FDC_I_n_32,
\Use_Serial_Unified_Completion.mb_instr_overrun_reg\ => FDC_I_n_30,
\Use_Serial_Unified_Completion.mb_instr_overrun_reg_0\ => FDC_I_n_31,
\Use_Serial_Unified_Completion.sample_1_reg[15]\ => \Use_Serial_Unified_Completion.completion_block_i_2_n_0\,
\Use_Serial_Unified_Completion.sample_reg[15]\(2) => FDC_I_n_16,
\Use_Serial_Unified_Completion.sample_reg[15]\(1) => FDC_I_n_17,
\Use_Serial_Unified_Completion.sample_reg[15]\(0) => FDC_I_n_18,
\Use_Serial_Unified_Completion.sample_reg[15]_0\(5 downto 3) => sample(15 downto 13),
\Use_Serial_Unified_Completion.sample_reg[15]_0\(2) => \Use_Serial_Unified_Completion.mb_data_overrun_reg_n_0\,
\Use_Serial_Unified_Completion.sample_reg[15]_0\(1) => \Use_Serial_Unified_Completion.mb_instr_error_reg_n_0\,
\Use_Serial_Unified_Completion.sample_reg[15]_0\(0) => mb_instr_overrun,
\command_1_reg[7]\(0) => command_10,
\command_reg[0]\ => Dbg_Shift_31_INST_0_i_4_n_0,
\command_reg[4]\ => Dbg_Shift_31_INST_0_i_3_n_0,
\command_reg[6]\ => Dbg_Shift_31_INST_0_i_1_n_0,
\command_reg[7]\ => Ext_NM_BRK_i_i_4_n_0,
completion_ctrl => completion_ctrl,
\completion_ctrl_reg[0]\ => FDC_I_n_34,
\p_20_out__0\ => \p_20_out__0\,
\p_22_out__0\ => \p_22_out__0\,
sample_1 => sample_1,
sel => sel,
sel_n => sel_n,
\shifting_Data1__0\ => \shifting_Data1__0\,
sync => sync,
\tdi_shifter_reg[0]\(7) => p_0_in_1,
\tdi_shifter_reg[0]\(6) => \tdi_shifter_reg_n_0_[1]\,
\tdi_shifter_reg[0]\(5) => \tdi_shifter_reg_n_0_[2]\,
\tdi_shifter_reg[0]\(4) => \tdi_shifter_reg_n_0_[3]\,
\tdi_shifter_reg[0]\(3) => \tdi_shifter_reg_n_0_[4]\,
\tdi_shifter_reg[0]\(2) => \tdi_shifter_reg_n_0_[5]\,
\tdi_shifter_reg[0]\(1) => \tdi_shifter_reg_n_0_[6]\,
\tdi_shifter_reg[0]\(0) => \tdi_shifter_reg_n_0_[7]\
);
SYNC_FDRE: entity work.system_mdm_1_0_MB_FDRE_1
port map (
CE => CE,
D_0 => D_0,
\Use_BSCAN.PORT_Selector_reg[0]\ => \Use_BSCAN.PORT_Selector_reg[0]_0\,
\Use_BSCAN.PORT_Selector_reg[0]_0\ => \Use_BSCAN.PORT_Selector_reg[0]_1\,
\Use_Serial_Unified_Completion.completion_block_reg\ => FDC_I_n_30,
\Use_Serial_Unified_Completion.count_reg[0]\ => \Use_Serial_Unified_Completion.count_reg_n_0_[0]\,
\command_reg[0]\ => Dbg_Shift_31_INST_0_i_4_n_0,
\command_reg[6]\ => Dbg_Shift_31_INST_0_i_1_n_0,
\p_22_out__0\ => \p_22_out__0\,
sync => sync
);
\Use_Config_SRL16E.SRL16E_1\: entity work.system_mdm_1_0_MB_SRL16E
port map (
Dbg_TDO_0 => Dbg_TDO_0,
Q(4) => \shift_Count_reg__0\(4),
Q(3) => A3,
Q(2) => A2,
Q(1) => A1,
Q(0) => \^q\(0),
\Use_BSCAN.PORT_Selector_reg[0]\ => \Use_BSCAN.PORT_Selector_reg[0]_0\,
\Use_BSCAN.PORT_Selector_reg[0]_0\(0) => \Use_BSCAN.PORT_Selector_reg[3]\(0),
\Use_BSCAN.PORT_Selector_reg[2]\ => \Use_BSCAN.PORT_Selector_reg[2]\,
\Use_Serial_Unified_Completion.completion_status_reg[0]\(0) => completion_status(0),
\command_reg[0]\ => \Use_E2.BSCANE2_I_i_3_n_0\,
\command_reg[0]_0\ => \Use_E2.BSCANE2_I_i_6_n_0\,
\command_reg[3]\ => \Use_E2.BSCANE2_I_i_7_n_0\,
\command_reg[4]\(2) => command(4),
\command_reg[4]\(1) => command(5),
\command_reg[4]\(0) => command(7),
\command_reg[5]\ => \Use_ID_SRL16E.SRL16E_ID_1_n_0\,
config_TDO_2 => config_TDO_2,
tdo => tdo
);
\Use_Config_SRL16E.SRL16E_2\: entity work.\system_mdm_1_0_MB_SRL16E__parameterized1\
port map (
Q(3) => A3,
Q(2) => A2,
Q(1) => A1,
Q(0) => \^q\(0),
\Use_BSCAN.PORT_Selector_reg[0]\ => \Use_BSCAN.PORT_Selector_reg[0]_0\,
config_TDO_2 => config_TDO_2
);
\Use_E2.BSCANE2_I_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFCFFFFFFFFFF"
)
port map (
I0 => command(1),
I1 => command(3),
I2 => command(5),
I3 => command(4),
I4 => command(2),
I5 => command(6),
O => \Use_E2.BSCANE2_I_i_10_n_0\
);
\Use_E2.BSCANE2_I_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000010000001"
)
port map (
I0 => command(1),
I1 => command(3),
I2 => command(2),
I3 => command(6),
I4 => command(4),
I5 => command(5),
O => \Use_E2.BSCANE2_I_i_11_n_0\
);
\Use_E2.BSCANE2_I_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => command(0),
I1 => Dbg_TDO_0,
I2 => \Use_BSCAN.PORT_Selector_reg[3]\(1),
O => \Use_E2.BSCANE2_I_i_3_n_0\
);
\Use_E2.BSCANE2_I_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"00F8"
)
port map (
I0 => \Use_E2.BSCANE2_I_i_10_n_0\,
I1 => Dbg_TDO_0,
I2 => \Use_E2.BSCANE2_I_i_11_n_0\,
I3 => command(0),
O => \Use_E2.BSCANE2_I_i_6_n_0\
);
\Use_E2.BSCANE2_I_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"88BC88FFAABEAABE"
)
port map (
I0 => command(3),
I1 => command(4),
I2 => command(5),
I3 => command(6),
I4 => command(1),
I5 => command(2),
O => \Use_E2.BSCANE2_I_i_7_n_0\
);
\Use_ID_SRL16E.SRL16E_ID_1\: entity work.\system_mdm_1_0_MB_SRL16E__parameterized3\
port map (
ID_TDO_2 => ID_TDO_2,
Q(4) => \shift_Count_reg__0\(4),
Q(3) => A3,
Q(2) => A2,
Q(1) => A1,
Q(0) => \^q\(0),
\Use_BSCAN.PORT_Selector_reg[0]\ => \Use_BSCAN.PORT_Selector_reg[0]_0\,
\command_reg[1]\(5) => command(1),
\command_reg[1]\(4) => command(2),
\command_reg[1]\(3) => command(4),
\command_reg[1]\(2) => command(5),
\command_reg[1]\(1) => command(6),
\command_reg[1]\(0) => command(7),
\tdi_shifter_reg[0]\ => \Use_ID_SRL16E.SRL16E_ID_1_n_0\
);
\Use_ID_SRL16E.SRL16E_ID_2\: entity work.\system_mdm_1_0_MB_SRL16E__parameterized5\
port map (
ID_TDO_2 => ID_TDO_2,
Q(3) => A3,
Q(2) => A2,
Q(1) => A1,
Q(0) => \^q\(0),
\Use_BSCAN.PORT_Selector_reg[0]\ => \Use_BSCAN.PORT_Selector_reg[0]_0\
);
\Use_Serial_Unified_Completion.completion_block_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFBAFFBABA"
)
port map (
I0 => \Use_Serial_Unified_Completion.completion_block_i_3_n_0\,
I1 => \^use_serial_unified_completion.completion_status_reg[15]_0\(0),
I2 => sample(15),
I3 => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[10]\,
I4 => mb_instr_overrun,
I5 => \Use_Serial_Unified_Completion.completion_block_i_4_n_0\,
O => \Use_Serial_Unified_Completion.completion_block_i_2_n_0\
);
\Use_Serial_Unified_Completion.completion_block_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[11]\,
I1 => \Use_Serial_Unified_Completion.mb_instr_error_reg_n_0\,
I2 => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[13]\,
I3 => sample(13),
O => \Use_Serial_Unified_Completion.completion_block_i_3_n_0\
);
\Use_Serial_Unified_Completion.completion_block_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[12]\,
I1 => \Use_Serial_Unified_Completion.mb_data_overrun_reg_n_0\,
I2 => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[14]\,
I3 => sample(14),
O => \Use_Serial_Unified_Completion.completion_block_i_4_n_0\
);
\Use_Serial_Unified_Completion.completion_block_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => FDC_I_n_35,
Q => \Use_Serial_Unified_Completion.completion_block_reg_n_0\
);
\Use_Serial_Unified_Completion.completion_status[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[10]\,
I1 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
I2 => completion_status(11),
O => p_1_in(10)
);
\Use_Serial_Unified_Completion.completion_status[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[11]\,
I1 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
I2 => completion_status(12),
O => p_1_in(11)
);
\Use_Serial_Unified_Completion.completion_status[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[12]\,
I1 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
I2 => completion_status(13),
O => p_1_in(12)
);
\Use_Serial_Unified_Completion.completion_status[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[13]\,
I1 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
I2 => completion_status(14),
O => p_1_in(13)
);
\Use_Serial_Unified_Completion.completion_status[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[14]\,
I1 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
I2 => completion_status(15),
O => p_1_in(14)
);
\Use_Serial_Unified_Completion.completion_status[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => completion_status(2),
I1 => completion_status(0),
I2 => completion_status(1),
O => \Use_Serial_Unified_Completion.completion_status[3]_i_2_n_0\
);
\Use_Serial_Unified_Completion.completion_status[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => completion_status(3),
I1 => completion_status(1),
I2 => completion_status(0),
I3 => completion_status(2),
O => \Use_Serial_Unified_Completion.completion_status[4]_i_2_n_0\
);
\Use_Serial_Unified_Completion.completion_status[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => completion_status(4),
I1 => completion_status(2),
I2 => completion_status(0),
I3 => completion_status(1),
I4 => completion_status(3),
O => \Use_Serial_Unified_Completion.completion_status[5]_i_2_n_0\
);
\Use_Serial_Unified_Completion.completion_status[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => completion_status(5),
I1 => completion_status(3),
I2 => completion_status(1),
I3 => completion_status(0),
I4 => completion_status(2),
I5 => completion_status(4),
O => \Use_Serial_Unified_Completion.completion_status[7]_i_2_n_0\
);
\Use_Serial_Unified_Completion.completion_status[9]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => completion_status(7),
I1 => \Use_Serial_Unified_Completion.completion_status[7]_i_2_n_0\,
I2 => completion_status(6),
O => \Use_Serial_Unified_Completion.completion_status[9]_i_4_n_0\
);
\Use_Serial_Unified_Completion.completion_status_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => FDC_I_n_15,
CLR => \^ar\(0),
D => p_1_in(0),
Q => completion_status(0)
);
\Use_Serial_Unified_Completion.completion_status_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => E(0),
CLR => \^ar\(0),
D => p_1_in(10),
Q => completion_status(10)
);
\Use_Serial_Unified_Completion.completion_status_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => E(0),
CLR => \^ar\(0),
D => p_1_in(11),
Q => completion_status(11)
);
\Use_Serial_Unified_Completion.completion_status_reg[12]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => E(0),
CLR => \^ar\(0),
D => p_1_in(12),
Q => completion_status(12)
);
\Use_Serial_Unified_Completion.completion_status_reg[13]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => E(0),
CLR => \^ar\(0),
D => p_1_in(13),
Q => completion_status(13)
);
\Use_Serial_Unified_Completion.completion_status_reg[14]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => E(0),
CLR => \^ar\(0),
D => p_1_in(14),
Q => completion_status(14)
);
\Use_Serial_Unified_Completion.completion_status_reg[15]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => E(0),
CLR => \^ar\(0),
D => D(0),
Q => completion_status(15)
);
\Use_Serial_Unified_Completion.completion_status_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => FDC_I_n_15,
CLR => \^ar\(0),
D => p_1_in(1),
Q => completion_status(1)
);
\Use_Serial_Unified_Completion.completion_status_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => FDC_I_n_15,
CLR => \^ar\(0),
D => p_1_in(2),
Q => completion_status(2)
);
\Use_Serial_Unified_Completion.completion_status_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => FDC_I_n_15,
CLR => \^ar\(0),
D => p_1_in(3),
Q => completion_status(3)
);
\Use_Serial_Unified_Completion.completion_status_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => FDC_I_n_15,
CLR => \^ar\(0),
D => p_1_in(4),
Q => completion_status(4)
);
\Use_Serial_Unified_Completion.completion_status_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => FDC_I_n_15,
CLR => \^ar\(0),
D => p_1_in(5),
Q => completion_status(5)
);
\Use_Serial_Unified_Completion.completion_status_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => FDC_I_n_15,
CLR => \^ar\(0),
D => p_1_in(6),
Q => completion_status(6)
);
\Use_Serial_Unified_Completion.completion_status_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => FDC_I_n_15,
CLR => \^ar\(0),
D => p_1_in(7),
Q => completion_status(7)
);
\Use_Serial_Unified_Completion.completion_status_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => FDC_I_n_15,
CLR => \^ar\(0),
D => p_1_in(8),
Q => completion_status(8)
);
\Use_Serial_Unified_Completion.completion_status_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => FDC_I_n_15,
CLR => \^ar\(0),
D => p_1_in(9),
Q => completion_status(9)
);
\Use_Serial_Unified_Completion.count[0]__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0078"
)
port map (
I0 => \Use_Serial_Unified_Completion.count_reg__1\(1),
I1 => \Use_Serial_Unified_Completion.count[0]__0_i_4_n_0\,
I2 => \Use_Serial_Unified_Completion.count_reg__1\(0),
I3 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
O => p_0_in(5)
);
\Use_Serial_Unified_Completion.count[0]__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \Use_Serial_Unified_Completion.count_reg__1\(2),
I1 => \Use_Serial_Unified_Completion.count_reg__1\(4),
I2 => \^use_serial_unified_completion.count_reg[4]_0\(0),
I3 => \Use_Serial_Unified_Completion.count_reg__1\(3),
O => \Use_Serial_Unified_Completion.count[0]__0_i_4_n_0\
);
\Use_Serial_Unified_Completion.count[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FF80FF00FF00"
)
port map (
I0 => \Use_Serial_Unified_Completion.count_reg_n_0_[1]\,
I1 => \Use_BSCAN.PORT_Selector_reg[0]_1\,
I2 => sync,
I3 => \Use_Serial_Unified_Completion.count_reg_n_0_[0]\,
I4 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
I5 => \shifting_Data1__0\,
O => \Use_Serial_Unified_Completion.count[0]_i_1_n_0\
);
\Use_Serial_Unified_Completion.count[1]__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000007FFF8000"
)
port map (
I0 => \Use_Serial_Unified_Completion.count_reg__1\(2),
I1 => \Use_Serial_Unified_Completion.count_reg__1\(4),
I2 => \^use_serial_unified_completion.count_reg[4]_0\(0),
I3 => \Use_Serial_Unified_Completion.count_reg__1\(3),
I4 => \Use_Serial_Unified_Completion.count_reg__1\(1),
I5 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
O => p_0_in(4)
);
\Use_Serial_Unified_Completion.count[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00F7FFFF00080000"
)
port map (
I0 => \Use_BSCAN.PORT_Selector_reg[0]_1\,
I1 => sync,
I2 => \Use_Serial_Unified_Completion.count_reg_n_0_[0]\,
I3 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
I4 => \shifting_Data1__0\,
I5 => \Use_Serial_Unified_Completion.count_reg_n_0_[1]\,
O => \Use_Serial_Unified_Completion.count[1]_i_1_n_0\
);
\Use_Serial_Unified_Completion.count[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00007F80"
)
port map (
I0 => \Use_Serial_Unified_Completion.count_reg__1\(3),
I1 => \^use_serial_unified_completion.count_reg[4]_0\(0),
I2 => \Use_Serial_Unified_Completion.count_reg__1\(4),
I3 => \Use_Serial_Unified_Completion.count_reg__1\(2),
I4 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
O => p_0_in(3)
);
\Use_Serial_Unified_Completion.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0078"
)
port map (
I0 => \Use_Serial_Unified_Completion.count_reg__1\(4),
I1 => \^use_serial_unified_completion.count_reg[4]_0\(0),
I2 => \Use_Serial_Unified_Completion.count_reg__1\(3),
I3 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
O => p_0_in(2)
);
\Use_Serial_Unified_Completion.count[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"06"
)
port map (
I0 => \^use_serial_unified_completion.count_reg[4]_0\(0),
I1 => \Use_Serial_Unified_Completion.count_reg__1\(4),
I2 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
O => p_0_in(1)
);
\Use_Serial_Unified_Completion.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => \Use_Serial_Unified_Completion.count[0]_i_1_n_0\,
Q => \Use_Serial_Unified_Completion.count_reg_n_0_[0]\
);
\Use_Serial_Unified_Completion.count_reg[0]__0\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => \command_reg[5]_0\(0),
CLR => \^ar\(0),
D => p_0_in(5),
Q => \Use_Serial_Unified_Completion.count_reg__1\(0)
);
\Use_Serial_Unified_Completion.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => \Use_Serial_Unified_Completion.count[1]_i_1_n_0\,
Q => \Use_Serial_Unified_Completion.count_reg_n_0_[1]\
);
\Use_Serial_Unified_Completion.count_reg[1]__0\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => \command_reg[5]_0\(0),
CLR => \^ar\(0),
D => p_0_in(4),
Q => \Use_Serial_Unified_Completion.count_reg__1\(1)
);
\Use_Serial_Unified_Completion.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => \command_reg[5]_0\(0),
CLR => \^ar\(0),
D => p_0_in(3),
Q => \Use_Serial_Unified_Completion.count_reg__1\(2)
);
\Use_Serial_Unified_Completion.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => \command_reg[5]_0\(0),
CLR => \^ar\(0),
D => p_0_in(2),
Q => \Use_Serial_Unified_Completion.count_reg__1\(3)
);
\Use_Serial_Unified_Completion.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => \command_reg[5]_0\(0),
CLR => \^ar\(0),
D => p_0_in(1),
Q => \Use_Serial_Unified_Completion.count_reg__1\(4)
);
\Use_Serial_Unified_Completion.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => \command_reg[5]_0\(0),
CLR => \^ar\(0),
D => \Use_Serial_Unified_Completion.count_reg[5]_0\(0),
Q => \^use_serial_unified_completion.count_reg[4]_0\(0)
);
\Use_Serial_Unified_Completion.mb_data_overrun_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \Use_Serial_Unified_Completion.mb_data_overrun_i_3_n_0\,
I1 => \^use_serial_unified_completion.count_reg[4]_0\(0),
I2 => \Use_Serial_Unified_Completion.count_reg__1\(4),
I3 => \Use_Serial_Unified_Completion.count_reg__1\(3),
O => \Use_Serial_Unified_Completion.mb_data_overrun_i_2_n_0\
);
\Use_Serial_Unified_Completion.mb_data_overrun_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => \Use_BSCAN.PORT_Selector_reg[0]_1\,
I1 => \Use_Serial_Unified_Completion.count_reg__1\(0),
I2 => \Use_Serial_Unified_Completion.count_reg__1\(1),
I3 => \Use_Serial_Unified_Completion.count_reg__1\(2),
O => \Use_Serial_Unified_Completion.mb_data_overrun_i_3_n_0\
);
\Use_Serial_Unified_Completion.mb_data_overrun_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => FDC_I_n_33,
Q => \Use_Serial_Unified_Completion.mb_data_overrun_reg_n_0\
);
\Use_Serial_Unified_Completion.mb_instr_error_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => FDC_I_n_32,
Q => \Use_Serial_Unified_Completion.mb_instr_error_reg_n_0\
);
\Use_Serial_Unified_Completion.mb_instr_overrun_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => FDC_I_n_31,
Q => mb_instr_overrun
);
\Use_Serial_Unified_Completion.sample_1_reg[10]\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => sample_1,
CLR => \^ar\(0),
D => mb_instr_overrun,
Q => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[10]\
);
\Use_Serial_Unified_Completion.sample_1_reg[11]\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => sample_1,
CLR => \^ar\(0),
D => \Use_Serial_Unified_Completion.mb_instr_error_reg_n_0\,
Q => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[11]\
);
\Use_Serial_Unified_Completion.sample_1_reg[12]\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => sample_1,
CLR => \^ar\(0),
D => \Use_Serial_Unified_Completion.mb_data_overrun_reg_n_0\,
Q => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[12]\
);
\Use_Serial_Unified_Completion.sample_1_reg[13]\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => sample_1,
CLR => \^ar\(0),
D => sample(13),
Q => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[13]\
);
\Use_Serial_Unified_Completion.sample_1_reg[14]\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => sample_1,
CLR => \^ar\(0),
D => sample(14),
Q => \Use_Serial_Unified_Completion.sample_1_reg_n_0_[14]\
);
\Use_Serial_Unified_Completion.sample_1_reg[15]\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => sample_1,
CLR => \^ar\(0),
D => sample(15),
Q => \^use_serial_unified_completion.completion_status_reg[15]_0\(0)
);
\Use_Serial_Unified_Completion.sample_reg[13]\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => FDC_I_n_18,
Q => sample(13)
);
\Use_Serial_Unified_Completion.sample_reg[14]\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => FDC_I_n_17,
Q => sample(14)
);
\Use_Serial_Unified_Completion.sample_reg[15]\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => FDC_I_n_16,
Q => sample(15)
);
\command[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000008"
)
port map (
I0 => sel,
I1 => \Use_BSCAN.PORT_Selector_reg[3]\(0),
I2 => \Use_BSCAN.PORT_Selector_reg[3]\(1),
I3 => \Use_BSCAN.PORT_Selector_reg[3]\(3),
I4 => \Use_BSCAN.PORT_Selector_reg[3]\(2),
O => \command[0]_i_1_n_0\
);
\command_1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => command_10,
CLR => \^ar\(0),
D => p_0_in_1,
Q => command_1(0)
);
\command_1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => command_10,
CLR => \^ar\(0),
D => \tdi_shifter_reg_n_0_[1]\,
Q => command_1(1)
);
\command_1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => command_10,
CLR => \^ar\(0),
D => \tdi_shifter_reg_n_0_[2]\,
Q => command_1(2)
);
\command_1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => command_10,
CLR => \^ar\(0),
D => \tdi_shifter_reg_n_0_[3]\,
Q => command_1(3)
);
\command_1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => command_10,
CLR => \^ar\(0),
D => \tdi_shifter_reg_n_0_[4]\,
Q => command_1(4)
);
\command_1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => command_10,
CLR => \^ar\(0),
D => \tdi_shifter_reg_n_0_[5]\,
Q => command_1(5)
);
\command_1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => command_10,
CLR => \^ar\(0),
D => \tdi_shifter_reg_n_0_[6]\,
Q => command_1(6)
);
\command_1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => command_10,
CLR => \^ar\(0),
D => \tdi_shifter_reg_n_0_[7]\,
Q => command_1(7)
);
\command_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => command_regn_0_0,
CE => \command[0]_i_1_n_0\,
CLR => \^ar\(0),
D => command_1(0),
Q => command(0)
);
\command_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => command_regn_0_0,
CE => \command[0]_i_1_n_0\,
CLR => \^ar\(0),
D => command_1(1),
Q => command(1)
);
\command_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => command_regn_0_0,
CE => \command[0]_i_1_n_0\,
CLR => \^ar\(0),
D => command_1(2),
Q => command(2)
);
\command_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => command_regn_0_0,
CE => \command[0]_i_1_n_0\,
CLR => \^ar\(0),
D => command_1(3),
Q => command(3)
);
\command_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => command_regn_0_0,
CE => \command[0]_i_1_n_0\,
CLR => \^ar\(0),
D => command_1(4),
Q => command(4)
);
\command_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => command_regn_0_0,
CE => \command[0]_i_1_n_0\,
CLR => \^ar\(0),
D => command_1(5),
Q => command(5)
);
\command_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => command_regn_0_0,
CE => \command[0]_i_1_n_0\,
CLR => \^ar\(0),
D => command_1(6),
Q => command(6)
);
\command_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => command_regn_0_0,
CE => \command[0]_i_1_n_0\,
CLR => \^ar\(0),
D => command_1(7),
Q => command(7)
);
command_regi_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \Use_BSCAN.PORT_Selector_reg[0]\,
O => command_regn_0_0
);
\completion_ctrl_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]\,
CE => '1',
CLR => \^ar\(0),
D => FDC_I_n_34,
Q => completion_ctrl
);
sel_n_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => \command[0]_i_1_n_0\,
I1 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
I2 => sel_n,
O => sel_n_i_1_n_0
);
sel_n_reg: unisim.vcomponents.FDPE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
D => sel_n_i_1_n_0,
PRE => \^ar\(0),
Q => sel_n
);
\shift_Count[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"48"
)
port map (
I0 => \^q\(0),
I1 => \Use_BSCAN.PORT_Selector_reg[0]_1\,
I2 => A1,
O => \p_0_in__0\(1)
);
\shift_Count[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7080"
)
port map (
I0 => A1,
I1 => \^q\(0),
I2 => \Use_BSCAN.PORT_Selector_reg[0]_1\,
I3 => A2,
O => \p_0_in__0\(2)
);
\shift_Count[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F008000"
)
port map (
I0 => A2,
I1 => \^q\(0),
I2 => A1,
I3 => \Use_BSCAN.PORT_Selector_reg[0]_1\,
I4 => A3,
O => \p_0_in__0\(3)
);
\shift_Count[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFF000080000000"
)
port map (
I0 => A3,
I1 => A1,
I2 => \^q\(0),
I3 => A2,
I4 => \Use_BSCAN.PORT_Selector_reg[0]_1\,
I5 => \shift_Count_reg__0\(4),
O => \p_0_in__0\(4)
);
\shift_Count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => \shift_Count_reg[0]_0\(0),
Q => \^q\(0)
);
\shift_Count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => \p_0_in__0\(1),
Q => A1
);
\shift_Count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => \p_0_in__0\(2),
Q => A2
);
\shift_Count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => \p_0_in__0\(3),
Q => A3
);
\shift_Count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
CLR => \^ar\(0),
D => \p_0_in__0\(4),
Q => \shift_Count_reg__0\(4)
);
\tdi_shifter[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100000000000000"
)
port map (
I0 => \Use_BSCAN.PORT_Selector_reg[3]\(2),
I1 => \Use_BSCAN.PORT_Selector_reg[3]\(3),
I2 => \Use_BSCAN.PORT_Selector_reg[3]\(1),
I3 => \Use_BSCAN.PORT_Selector_reg[3]\(0),
I4 => sel,
I5 => \Use_BSCAN.PORT_Selector_reg[0]_1\,
O => tdi_shifter0
);
\tdi_shifter_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => tdi_shifter0,
CLR => \^ar\(0),
D => Ext_JTAG_TDI,
Q => p_0_in_1
);
\tdi_shifter_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => tdi_shifter0,
CLR => \^ar\(0),
D => p_0_in_1,
Q => \tdi_shifter_reg_n_0_[1]\
);
\tdi_shifter_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => tdi_shifter0,
CLR => \^ar\(0),
D => \tdi_shifter_reg_n_0_[1]\,
Q => \tdi_shifter_reg_n_0_[2]\
);
\tdi_shifter_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => tdi_shifter0,
CLR => \^ar\(0),
D => \tdi_shifter_reg_n_0_[2]\,
Q => \tdi_shifter_reg_n_0_[3]\
);
\tdi_shifter_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => tdi_shifter0,
CLR => \^ar\(0),
D => \tdi_shifter_reg_n_0_[3]\,
Q => \tdi_shifter_reg_n_0_[4]\
);
\tdi_shifter_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => tdi_shifter0,
CLR => \^ar\(0),
D => \tdi_shifter_reg_n_0_[4]\,
Q => \tdi_shifter_reg_n_0_[5]\
);
\tdi_shifter_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => tdi_shifter0,
CLR => \^ar\(0),
D => \tdi_shifter_reg_n_0_[5]\,
Q => \tdi_shifter_reg_n_0_[6]\
);
\tdi_shifter_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => tdi_shifter0,
CLR => \^ar\(0),
D => \tdi_shifter_reg_n_0_[6]\,
Q => \tdi_shifter_reg_n_0_[7]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_mdm_1_0_MDM_Core is
port (
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
Dbg_Disable_0 : out STD_LOGIC;
Ext_NM_BRK : out STD_LOGIC;
Debug_SYS_Rst : out STD_LOGIC;
Dbg_Rst_0 : out STD_LOGIC;
Dbg_Shift_0 : out STD_LOGIC;
\p_20_out__0\ : out STD_LOGIC;
\p_43_out__0\ : out STD_LOGIC;
Dbg_Reg_En_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
tdo : out STD_LOGIC;
Ext_JTAG_SEL : out STD_LOGIC;
\Use_Serial_Unified_Completion.count_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Use_Serial_Unified_Completion.completion_status_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Use_BSCAN.PORT_Selector_reg[0]_0\ : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]_1\ : in STD_LOGIC;
shift_n_reset : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]_2\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
\Use_BSCAN.PORT_Selector_reg[0]_3\ : in STD_LOGIC;
sel : in STD_LOGIC;
Dbg_TDO_0 : in STD_LOGIC;
Ext_JTAG_TDO : in STD_LOGIC;
\Use_Serial_Unified_Completion.count_reg[5]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\shift_Count_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Scan_Reset : in STD_LOGIC;
Scan_Reset_Sel : in STD_LOGIC;
\Use_BSCAN.PORT_Selector_reg[0]_4\ : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
Ext_JTAG_TDI : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\command_reg[5]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_mdm_1_0_MDM_Core : entity is "MDM_Core";
end system_mdm_1_0_MDM_Core;
architecture STRUCTURE of system_mdm_1_0_MDM_Core is
signal Config_Reg : STD_LOGIC_VECTOR ( 0 to 0 );
signal MDM_SEL : STD_LOGIC;
signal PORT_Selector : STD_LOGIC_VECTOR ( 3 downto 0 );
signal PORT_Selector_1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal TDI_Shifter : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \Use_BSCAN.Config_Reg_reg[11]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_12_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg[12]_srl13_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_11_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg[27]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_1_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg[28]_srl2_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_0_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg[4]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_3_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg[5]_srl4_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_2_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_0_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_10_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_11_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_12_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_1_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_2_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_3_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_4_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_5_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_6_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_7_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_8_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_9_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_c_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_gate__0_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_gate__1_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_gate_n_0\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_n_0_[10]\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_n_0_[1]\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_n_0_[25]\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_n_0_[26]\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_n_0_[2]\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_n_0_[30]\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_n_0_[3]\ : STD_LOGIC;
signal \Use_BSCAN.Config_Reg_reg_n_0_[9]\ : STD_LOGIC;
signal \Use_BSCAN.PORT_Selector_regn_0_0\ : STD_LOGIC;
signal \Use_E2.BSCANE2_I_i_2_n_0\ : STD_LOGIC;
signal config_with_scan_reset : STD_LOGIC;
signal p_0_out : STD_LOGIC;
attribute srl_bus_name : string;
attribute srl_bus_name of \Use_BSCAN.Config_Reg_reg[12]_srl13_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_11\ : label is "U0/\MDM_Core_I1/Use_BSCAN.Config_Reg_reg ";
attribute srl_name : string;
attribute srl_name of \Use_BSCAN.Config_Reg_reg[12]_srl13_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_11\ : label is "U0/\MDM_Core_I1/Use_BSCAN.Config_Reg_reg[12]_srl13_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_11 ";
attribute srl_bus_name of \Use_BSCAN.Config_Reg_reg[28]_srl2_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_0\ : label is "U0/\MDM_Core_I1/Use_BSCAN.Config_Reg_reg ";
attribute srl_name of \Use_BSCAN.Config_Reg_reg[28]_srl2_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_0\ : label is "U0/\MDM_Core_I1/Use_BSCAN.Config_Reg_reg[28]_srl2_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_0 ";
attribute srl_bus_name of \Use_BSCAN.Config_Reg_reg[5]_srl4_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_2\ : label is "U0/\MDM_Core_I1/Use_BSCAN.Config_Reg_reg ";
attribute srl_name of \Use_BSCAN.Config_Reg_reg[5]_srl4_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_2\ : label is "U0/\MDM_Core_I1/Use_BSCAN.Config_Reg_reg[5]_srl4_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_2 ";
begin
Ext_JTAG_SEL_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"00000008"
)
port map (
I0 => sel,
I1 => PORT_Selector(1),
I2 => PORT_Selector(0),
I3 => PORT_Selector(3),
I4 => PORT_Selector(2),
O => Ext_JTAG_SEL
);
JTAG_CONTROL_I: entity work.system_mdm_1_0_JTAG_CONTROL
port map (
AR(0) => config_with_scan_reset,
D(0) => D(0),
Dbg_Reg_En_0(0 to 7) => Dbg_Reg_En_0(0 to 7),
Dbg_Rst_0 => Dbg_Rst_0,
Dbg_Shift_0 => Dbg_Shift_0,
Dbg_TDO_0 => Dbg_TDO_0,
Debug_SYS_Rst => Debug_SYS_Rst,
E(0) => E(0),
Ext_JTAG_TDI => Ext_JTAG_TDI,
Ext_NM_BRK => Ext_NM_BRK,
Q(0) => Q(0),
Scan_Reset => Scan_Reset,
Scan_Reset_Sel => Scan_Reset_Sel,
\Use_BSCAN.PORT_Selector_reg[0]\ => \Use_BSCAN.PORT_Selector_reg[0]_0\,
\Use_BSCAN.PORT_Selector_reg[0]_0\ => \Use_BSCAN.PORT_Selector_reg[0]_1\,
\Use_BSCAN.PORT_Selector_reg[0]_1\ => \Use_BSCAN.PORT_Selector_reg[0]_2\,
\Use_BSCAN.PORT_Selector_reg[0]_2\ => \Use_BSCAN.PORT_Selector_reg[0]_3\,
\Use_BSCAN.PORT_Selector_reg[0]_3\ => \Use_BSCAN.PORT_Selector_reg[0]_4\,
\Use_BSCAN.PORT_Selector_reg[2]\ => \Use_E2.BSCANE2_I_i_2_n_0\,
\Use_BSCAN.PORT_Selector_reg[3]\(3 downto 0) => PORT_Selector(3 downto 0),
\Use_Serial_Unified_Completion.completion_block_reg_0\ => \p_43_out__0\,
\Use_Serial_Unified_Completion.completion_status_reg[15]_0\(0) => \Use_Serial_Unified_Completion.completion_status_reg[15]\(0),
\Use_Serial_Unified_Completion.count_reg[4]_0\(0) => \Use_Serial_Unified_Completion.count_reg[4]\(0),
\Use_Serial_Unified_Completion.count_reg[5]_0\(0) => \Use_Serial_Unified_Completion.count_reg[5]\(0),
\command_reg[5]_0\(0) => \command_reg[5]\(0),
\p_20_out__0\ => \p_20_out__0\,
sel => sel,
\shift_Count_reg[0]_0\(0) => \shift_Count_reg[0]\(0),
tdo => tdo
);
\Use_BSCAN.Config_Reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_n_0_[1]\,
Q => Config_Reg(0)
);
\Use_BSCAN.Config_Reg_reg[10]\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_gate__0_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_n_0_[10]\
);
\Use_BSCAN.Config_Reg_reg[11]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_12\: unisim.vcomponents.FDRE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
D => \Use_BSCAN.Config_Reg_reg[12]_srl13_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_11_n_0\,
Q => \Use_BSCAN.Config_Reg_reg[11]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_12_n_0\,
R => '0'
);
\Use_BSCAN.Config_Reg_reg[12]_srl13_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_11\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '0',
A1 => '0',
A2 => '1',
A3 => '1',
CE => '1',
CLK => \Use_BSCAN.PORT_Selector_reg[0]_1\,
D => \Use_BSCAN.Config_Reg_reg_n_0_[25]\,
Q => \Use_BSCAN.Config_Reg_reg[12]_srl13_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_11_n_0\
);
\Use_BSCAN.Config_Reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
D => \Use_BSCAN.Config_Reg_reg_n_0_[2]\,
PRE => shift_n_reset,
Q => \Use_BSCAN.Config_Reg_reg_n_0_[1]\
);
\Use_BSCAN.Config_Reg_reg[25]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
D => \Use_BSCAN.Config_Reg_reg_n_0_[26]\,
PRE => shift_n_reset,
Q => \Use_BSCAN.Config_Reg_reg_n_0_[25]\
);
\Use_BSCAN.Config_Reg_reg[26]\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_gate_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_n_0_[26]\
);
\Use_BSCAN.Config_Reg_reg[27]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_1\: unisim.vcomponents.FDRE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
D => \Use_BSCAN.Config_Reg_reg[28]_srl2_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_0_n_0\,
Q => \Use_BSCAN.Config_Reg_reg[27]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_1_n_0\,
R => '0'
);
\Use_BSCAN.Config_Reg_reg[28]_srl2_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_0\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '0',
A2 => '0',
A3 => '0',
CE => '1',
CLK => \Use_BSCAN.PORT_Selector_reg[0]_1\,
D => \Use_BSCAN.Config_Reg_reg_n_0_[30]\,
Q => \Use_BSCAN.Config_Reg_reg[28]_srl2_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_0_n_0\
);
\Use_BSCAN.Config_Reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
D => \Use_BSCAN.Config_Reg_reg_n_0_[3]\,
PRE => shift_n_reset,
Q => \Use_BSCAN.Config_Reg_reg_n_0_[2]\
);
\Use_BSCAN.Config_Reg_reg[30]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
D => '0',
PRE => shift_n_reset,
Q => \Use_BSCAN.Config_Reg_reg_n_0_[30]\
);
\Use_BSCAN.Config_Reg_reg[3]\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_gate__1_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_n_0_[3]\
);
\Use_BSCAN.Config_Reg_reg[4]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_3\: unisim.vcomponents.FDRE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
D => \Use_BSCAN.Config_Reg_reg[5]_srl4_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_2_n_0\,
Q => \Use_BSCAN.Config_Reg_reg[4]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_3_n_0\,
R => '0'
);
\Use_BSCAN.Config_Reg_reg[5]_srl4_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_2\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '1',
A1 => '1',
A2 => '0',
A3 => '0',
CE => '1',
CLK => \Use_BSCAN.PORT_Selector_reg[0]_1\,
D => \Use_BSCAN.Config_Reg_reg_n_0_[9]\,
Q => \Use_BSCAN.Config_Reg_reg[5]_srl4_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_2_n_0\
);
\Use_BSCAN.Config_Reg_reg[9]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
D => \Use_BSCAN.Config_Reg_reg_n_0_[10]\,
PRE => shift_n_reset,
Q => \Use_BSCAN.Config_Reg_reg_n_0_[9]\
);
\Use_BSCAN.Config_Reg_reg_c\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => '1',
Q => \Use_BSCAN.Config_Reg_reg_c_n_0\
);
\Use_BSCAN.Config_Reg_reg_c_0\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_c_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_c_0_n_0\
);
\Use_BSCAN.Config_Reg_reg_c_1\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_c_0_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_c_1_n_0\
);
\Use_BSCAN.Config_Reg_reg_c_10\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_c_9_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_c_10_n_0\
);
\Use_BSCAN.Config_Reg_reg_c_11\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_c_10_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_c_11_n_0\
);
\Use_BSCAN.Config_Reg_reg_c_12\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_c_11_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_c_12_n_0\
);
\Use_BSCAN.Config_Reg_reg_c_2\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_c_1_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_c_2_n_0\
);
\Use_BSCAN.Config_Reg_reg_c_3\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_c_2_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_c_3_n_0\
);
\Use_BSCAN.Config_Reg_reg_c_4\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_c_3_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_c_4_n_0\
);
\Use_BSCAN.Config_Reg_reg_c_5\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_c_4_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_c_5_n_0\
);
\Use_BSCAN.Config_Reg_reg_c_6\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_c_5_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_c_6_n_0\
);
\Use_BSCAN.Config_Reg_reg_c_7\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_c_6_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_c_7_n_0\
);
\Use_BSCAN.Config_Reg_reg_c_8\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_c_7_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_c_8_n_0\
);
\Use_BSCAN.Config_Reg_reg_c_9\: unisim.vcomponents.FDCE
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => '1',
CLR => shift_n_reset,
D => \Use_BSCAN.Config_Reg_reg_c_8_n_0\,
Q => \Use_BSCAN.Config_Reg_reg_c_9_n_0\
);
\Use_BSCAN.Config_Reg_reg_gate\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \Use_BSCAN.Config_Reg_reg[27]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_1_n_0\,
I1 => \Use_BSCAN.Config_Reg_reg_c_1_n_0\,
O => \Use_BSCAN.Config_Reg_reg_gate_n_0\
);
\Use_BSCAN.Config_Reg_reg_gate__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \Use_BSCAN.Config_Reg_reg[11]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_12_n_0\,
I1 => \Use_BSCAN.Config_Reg_reg_c_12_n_0\,
O => \Use_BSCAN.Config_Reg_reg_gate__0_n_0\
);
\Use_BSCAN.Config_Reg_reg_gate__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \Use_BSCAN.Config_Reg_reg[4]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_3_n_0\,
I1 => \Use_BSCAN.Config_Reg_reg_c_3_n_0\,
O => \Use_BSCAN.Config_Reg_reg_gate__1_n_0\
);
\Use_BSCAN.PORT_Selector_1[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => sel,
I1 => PORT_Selector(0),
I2 => PORT_Selector(1),
I3 => PORT_Selector(3),
I4 => PORT_Selector(2),
O => MDM_SEL
);
\Use_BSCAN.PORT_Selector_1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => MDM_SEL,
CLR => AR(0),
D => TDI_Shifter(0),
Q => PORT_Selector_1(0)
);
\Use_BSCAN.PORT_Selector_1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => MDM_SEL,
CLR => AR(0),
D => TDI_Shifter(1),
Q => PORT_Selector_1(1)
);
\Use_BSCAN.PORT_Selector_1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => MDM_SEL,
CLR => AR(0),
D => TDI_Shifter(2),
Q => PORT_Selector_1(2)
);
\Use_BSCAN.PORT_Selector_1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => MDM_SEL,
CLR => AR(0),
D => TDI_Shifter(3),
Q => PORT_Selector_1(3)
);
\Use_BSCAN.PORT_Selector_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_regn_0_0\,
CE => '1',
CLR => AR(0),
D => PORT_Selector_1(0),
Q => PORT_Selector(0)
);
\Use_BSCAN.PORT_Selector_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_regn_0_0\,
CE => '1',
CLR => AR(0),
D => PORT_Selector_1(1),
Q => PORT_Selector(1)
);
\Use_BSCAN.PORT_Selector_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_regn_0_0\,
CE => '1',
CLR => AR(0),
D => PORT_Selector_1(2),
Q => PORT_Selector(2)
);
\Use_BSCAN.PORT_Selector_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_regn_0_0\,
CE => '1',
CLR => AR(0),
D => PORT_Selector_1(3),
Q => PORT_Selector(3)
);
\Use_BSCAN.PORT_Selector_regi_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \Use_BSCAN.PORT_Selector_reg[0]_0\,
O => \Use_BSCAN.PORT_Selector_regn_0_0\
);
\Use_BSCAN.TDI_Shifter[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => PORT_Selector(2),
I1 => PORT_Selector(3),
I2 => PORT_Selector(1),
I3 => PORT_Selector(0),
I4 => sel,
I5 => \Use_BSCAN.PORT_Selector_reg[0]_2\,
O => p_0_out
);
\Use_BSCAN.TDI_Shifter_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => p_0_out,
CLR => AR(0),
D => TDI_Shifter(1),
Q => TDI_Shifter(0)
);
\Use_BSCAN.TDI_Shifter_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => p_0_out,
CLR => AR(0),
D => TDI_Shifter(2),
Q => TDI_Shifter(1)
);
\Use_BSCAN.TDI_Shifter_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => p_0_out,
CLR => AR(0),
D => TDI_Shifter(3),
Q => TDI_Shifter(2)
);
\Use_BSCAN.TDI_Shifter_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_1\,
CE => p_0_out,
CLR => AR(0),
D => Ext_JTAG_TDI,
Q => TDI_Shifter(3)
);
\Use_BSCAN.jtag_disable_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => \Use_BSCAN.PORT_Selector_reg[0]_0\,
CE => '1',
D => '0',
PRE => config_with_scan_reset,
Q => Dbg_Disable_0
);
\Use_E2.BSCANE2_I_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEFEEEFFEEEE"
)
port map (
I0 => PORT_Selector(2),
I1 => PORT_Selector(3),
I2 => Ext_JTAG_TDO,
I3 => PORT_Selector(0),
I4 => Config_Reg(0),
I5 => PORT_Selector(1),
O => \Use_E2.BSCANE2_I_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_mdm_1_0_MDM is
port (
Config_Reset : in STD_LOGIC;
Scan_Reset_Sel : in STD_LOGIC;
Scan_Reset : in STD_LOGIC;
S_AXI_ACLK : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
M_AXI_ACLK : in STD_LOGIC;
M_AXI_ARESETN : in STD_LOGIC;
M_AXIS_ACLK : in STD_LOGIC;
M_AXIS_ARESETN : in STD_LOGIC;
Interrupt : out STD_LOGIC;
Ext_BRK : out STD_LOGIC;
Ext_NM_BRK : out STD_LOGIC;
Debug_SYS_Rst : out STD_LOGIC;
Trig_In_0 : in STD_LOGIC;
Trig_Ack_In_0 : out STD_LOGIC;
Trig_Out_0 : out STD_LOGIC;
Trig_Ack_Out_0 : in STD_LOGIC;
Trig_In_1 : in STD_LOGIC;
Trig_Ack_In_1 : out STD_LOGIC;
Trig_Out_1 : out STD_LOGIC;
Trig_Ack_Out_1 : in STD_LOGIC;
Trig_In_2 : in STD_LOGIC;
Trig_Ack_In_2 : out STD_LOGIC;
Trig_Out_2 : out STD_LOGIC;
Trig_Ack_Out_2 : in STD_LOGIC;
Trig_In_3 : in STD_LOGIC;
Trig_Ack_In_3 : out STD_LOGIC;
Trig_Out_3 : out STD_LOGIC;
Trig_Ack_Out_3 : in STD_LOGIC;
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_WVALID : in STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_BVALID : out STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
M_AXI_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_AWLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_AWLOCK : out STD_LOGIC;
M_AXI_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_AWVALID : out STD_LOGIC;
M_AXI_AWREADY : in STD_LOGIC;
M_AXI_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_WLAST : out STD_LOGIC;
M_AXI_WVALID : out STD_LOGIC;
M_AXI_WREADY : in STD_LOGIC;
M_AXI_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_BID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_BVALID : in STD_LOGIC;
M_AXI_BREADY : out STD_LOGIC;
M_AXI_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_ARLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_ARLOCK : out STD_LOGIC;
M_AXI_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_ARVALID : out STD_LOGIC;
M_AXI_ARREADY : in STD_LOGIC;
M_AXI_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_RLAST : in STD_LOGIC;
M_AXI_RVALID : in STD_LOGIC;
M_AXI_RREADY : out STD_LOGIC;
LMB_Data_Addr_0 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_0 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_0 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_0 : out STD_LOGIC;
LMB_Read_Strobe_0 : out STD_LOGIC;
LMB_Write_Strobe_0 : out STD_LOGIC;
LMB_Ready_0 : in STD_LOGIC;
LMB_Wait_0 : in STD_LOGIC;
LMB_CE_0 : in STD_LOGIC;
LMB_UE_0 : in STD_LOGIC;
LMB_Byte_Enable_0 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_1 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_1 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_1 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_1 : out STD_LOGIC;
LMB_Read_Strobe_1 : out STD_LOGIC;
LMB_Write_Strobe_1 : out STD_LOGIC;
LMB_Ready_1 : in STD_LOGIC;
LMB_Wait_1 : in STD_LOGIC;
LMB_CE_1 : in STD_LOGIC;
LMB_UE_1 : in STD_LOGIC;
LMB_Byte_Enable_1 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_2 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_2 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_2 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_2 : out STD_LOGIC;
LMB_Read_Strobe_2 : out STD_LOGIC;
LMB_Write_Strobe_2 : out STD_LOGIC;
LMB_Ready_2 : in STD_LOGIC;
LMB_Wait_2 : in STD_LOGIC;
LMB_CE_2 : in STD_LOGIC;
LMB_UE_2 : in STD_LOGIC;
LMB_Byte_Enable_2 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_3 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_3 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_3 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_3 : out STD_LOGIC;
LMB_Read_Strobe_3 : out STD_LOGIC;
LMB_Write_Strobe_3 : out STD_LOGIC;
LMB_Ready_3 : in STD_LOGIC;
LMB_Wait_3 : in STD_LOGIC;
LMB_CE_3 : in STD_LOGIC;
LMB_UE_3 : in STD_LOGIC;
LMB_Byte_Enable_3 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_4 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_4 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_4 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_4 : out STD_LOGIC;
LMB_Read_Strobe_4 : out STD_LOGIC;
LMB_Write_Strobe_4 : out STD_LOGIC;
LMB_Ready_4 : in STD_LOGIC;
LMB_Wait_4 : in STD_LOGIC;
LMB_CE_4 : in STD_LOGIC;
LMB_UE_4 : in STD_LOGIC;
LMB_Byte_Enable_4 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_5 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_5 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_5 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_5 : out STD_LOGIC;
LMB_Read_Strobe_5 : out STD_LOGIC;
LMB_Write_Strobe_5 : out STD_LOGIC;
LMB_Ready_5 : in STD_LOGIC;
LMB_Wait_5 : in STD_LOGIC;
LMB_CE_5 : in STD_LOGIC;
LMB_UE_5 : in STD_LOGIC;
LMB_Byte_Enable_5 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_6 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_6 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_6 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_6 : out STD_LOGIC;
LMB_Read_Strobe_6 : out STD_LOGIC;
LMB_Write_Strobe_6 : out STD_LOGIC;
LMB_Ready_6 : in STD_LOGIC;
LMB_Wait_6 : in STD_LOGIC;
LMB_CE_6 : in STD_LOGIC;
LMB_UE_6 : in STD_LOGIC;
LMB_Byte_Enable_6 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_7 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_7 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_7 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_7 : out STD_LOGIC;
LMB_Read_Strobe_7 : out STD_LOGIC;
LMB_Write_Strobe_7 : out STD_LOGIC;
LMB_Ready_7 : in STD_LOGIC;
LMB_Wait_7 : in STD_LOGIC;
LMB_CE_7 : in STD_LOGIC;
LMB_UE_7 : in STD_LOGIC;
LMB_Byte_Enable_7 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_8 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_8 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_8 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_8 : out STD_LOGIC;
LMB_Read_Strobe_8 : out STD_LOGIC;
LMB_Write_Strobe_8 : out STD_LOGIC;
LMB_Ready_8 : in STD_LOGIC;
LMB_Wait_8 : in STD_LOGIC;
LMB_CE_8 : in STD_LOGIC;
LMB_UE_8 : in STD_LOGIC;
LMB_Byte_Enable_8 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_9 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_9 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_9 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_9 : out STD_LOGIC;
LMB_Read_Strobe_9 : out STD_LOGIC;
LMB_Write_Strobe_9 : out STD_LOGIC;
LMB_Ready_9 : in STD_LOGIC;
LMB_Wait_9 : in STD_LOGIC;
LMB_CE_9 : in STD_LOGIC;
LMB_UE_9 : in STD_LOGIC;
LMB_Byte_Enable_9 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_10 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_10 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_10 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_10 : out STD_LOGIC;
LMB_Read_Strobe_10 : out STD_LOGIC;
LMB_Write_Strobe_10 : out STD_LOGIC;
LMB_Ready_10 : in STD_LOGIC;
LMB_Wait_10 : in STD_LOGIC;
LMB_CE_10 : in STD_LOGIC;
LMB_UE_10 : in STD_LOGIC;
LMB_Byte_Enable_10 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_11 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_11 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_11 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_11 : out STD_LOGIC;
LMB_Read_Strobe_11 : out STD_LOGIC;
LMB_Write_Strobe_11 : out STD_LOGIC;
LMB_Ready_11 : in STD_LOGIC;
LMB_Wait_11 : in STD_LOGIC;
LMB_CE_11 : in STD_LOGIC;
LMB_UE_11 : in STD_LOGIC;
LMB_Byte_Enable_11 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_12 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_12 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_12 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_12 : out STD_LOGIC;
LMB_Read_Strobe_12 : out STD_LOGIC;
LMB_Write_Strobe_12 : out STD_LOGIC;
LMB_Ready_12 : in STD_LOGIC;
LMB_Wait_12 : in STD_LOGIC;
LMB_CE_12 : in STD_LOGIC;
LMB_UE_12 : in STD_LOGIC;
LMB_Byte_Enable_12 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_13 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_13 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_13 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_13 : out STD_LOGIC;
LMB_Read_Strobe_13 : out STD_LOGIC;
LMB_Write_Strobe_13 : out STD_LOGIC;
LMB_Ready_13 : in STD_LOGIC;
LMB_Wait_13 : in STD_LOGIC;
LMB_CE_13 : in STD_LOGIC;
LMB_UE_13 : in STD_LOGIC;
LMB_Byte_Enable_13 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_14 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_14 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_14 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_14 : out STD_LOGIC;
LMB_Read_Strobe_14 : out STD_LOGIC;
LMB_Write_Strobe_14 : out STD_LOGIC;
LMB_Ready_14 : in STD_LOGIC;
LMB_Wait_14 : in STD_LOGIC;
LMB_CE_14 : in STD_LOGIC;
LMB_UE_14 : in STD_LOGIC;
LMB_Byte_Enable_14 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_15 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_15 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_15 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_15 : out STD_LOGIC;
LMB_Read_Strobe_15 : out STD_LOGIC;
LMB_Write_Strobe_15 : out STD_LOGIC;
LMB_Ready_15 : in STD_LOGIC;
LMB_Wait_15 : in STD_LOGIC;
LMB_CE_15 : in STD_LOGIC;
LMB_UE_15 : in STD_LOGIC;
LMB_Byte_Enable_15 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_16 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_16 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_16 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_16 : out STD_LOGIC;
LMB_Read_Strobe_16 : out STD_LOGIC;
LMB_Write_Strobe_16 : out STD_LOGIC;
LMB_Ready_16 : in STD_LOGIC;
LMB_Wait_16 : in STD_LOGIC;
LMB_CE_16 : in STD_LOGIC;
LMB_UE_16 : in STD_LOGIC;
LMB_Byte_Enable_16 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_17 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_17 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_17 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_17 : out STD_LOGIC;
LMB_Read_Strobe_17 : out STD_LOGIC;
LMB_Write_Strobe_17 : out STD_LOGIC;
LMB_Ready_17 : in STD_LOGIC;
LMB_Wait_17 : in STD_LOGIC;
LMB_CE_17 : in STD_LOGIC;
LMB_UE_17 : in STD_LOGIC;
LMB_Byte_Enable_17 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_18 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_18 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_18 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_18 : out STD_LOGIC;
LMB_Read_Strobe_18 : out STD_LOGIC;
LMB_Write_Strobe_18 : out STD_LOGIC;
LMB_Ready_18 : in STD_LOGIC;
LMB_Wait_18 : in STD_LOGIC;
LMB_CE_18 : in STD_LOGIC;
LMB_UE_18 : in STD_LOGIC;
LMB_Byte_Enable_18 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_19 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_19 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_19 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_19 : out STD_LOGIC;
LMB_Read_Strobe_19 : out STD_LOGIC;
LMB_Write_Strobe_19 : out STD_LOGIC;
LMB_Ready_19 : in STD_LOGIC;
LMB_Wait_19 : in STD_LOGIC;
LMB_CE_19 : in STD_LOGIC;
LMB_UE_19 : in STD_LOGIC;
LMB_Byte_Enable_19 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_20 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_20 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_20 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_20 : out STD_LOGIC;
LMB_Read_Strobe_20 : out STD_LOGIC;
LMB_Write_Strobe_20 : out STD_LOGIC;
LMB_Ready_20 : in STD_LOGIC;
LMB_Wait_20 : in STD_LOGIC;
LMB_CE_20 : in STD_LOGIC;
LMB_UE_20 : in STD_LOGIC;
LMB_Byte_Enable_20 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_21 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_21 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_21 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_21 : out STD_LOGIC;
LMB_Read_Strobe_21 : out STD_LOGIC;
LMB_Write_Strobe_21 : out STD_LOGIC;
LMB_Ready_21 : in STD_LOGIC;
LMB_Wait_21 : in STD_LOGIC;
LMB_CE_21 : in STD_LOGIC;
LMB_UE_21 : in STD_LOGIC;
LMB_Byte_Enable_21 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_22 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_22 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_22 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_22 : out STD_LOGIC;
LMB_Read_Strobe_22 : out STD_LOGIC;
LMB_Write_Strobe_22 : out STD_LOGIC;
LMB_Ready_22 : in STD_LOGIC;
LMB_Wait_22 : in STD_LOGIC;
LMB_CE_22 : in STD_LOGIC;
LMB_UE_22 : in STD_LOGIC;
LMB_Byte_Enable_22 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_23 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_23 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_23 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_23 : out STD_LOGIC;
LMB_Read_Strobe_23 : out STD_LOGIC;
LMB_Write_Strobe_23 : out STD_LOGIC;
LMB_Ready_23 : in STD_LOGIC;
LMB_Wait_23 : in STD_LOGIC;
LMB_CE_23 : in STD_LOGIC;
LMB_UE_23 : in STD_LOGIC;
LMB_Byte_Enable_23 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_24 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_24 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_24 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_24 : out STD_LOGIC;
LMB_Read_Strobe_24 : out STD_LOGIC;
LMB_Write_Strobe_24 : out STD_LOGIC;
LMB_Ready_24 : in STD_LOGIC;
LMB_Wait_24 : in STD_LOGIC;
LMB_CE_24 : in STD_LOGIC;
LMB_UE_24 : in STD_LOGIC;
LMB_Byte_Enable_24 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_25 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_25 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_25 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_25 : out STD_LOGIC;
LMB_Read_Strobe_25 : out STD_LOGIC;
LMB_Write_Strobe_25 : out STD_LOGIC;
LMB_Ready_25 : in STD_LOGIC;
LMB_Wait_25 : in STD_LOGIC;
LMB_CE_25 : in STD_LOGIC;
LMB_UE_25 : in STD_LOGIC;
LMB_Byte_Enable_25 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_26 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_26 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_26 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_26 : out STD_LOGIC;
LMB_Read_Strobe_26 : out STD_LOGIC;
LMB_Write_Strobe_26 : out STD_LOGIC;
LMB_Ready_26 : in STD_LOGIC;
LMB_Wait_26 : in STD_LOGIC;
LMB_CE_26 : in STD_LOGIC;
LMB_UE_26 : in STD_LOGIC;
LMB_Byte_Enable_26 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_27 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_27 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_27 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_27 : out STD_LOGIC;
LMB_Read_Strobe_27 : out STD_LOGIC;
LMB_Write_Strobe_27 : out STD_LOGIC;
LMB_Ready_27 : in STD_LOGIC;
LMB_Wait_27 : in STD_LOGIC;
LMB_CE_27 : in STD_LOGIC;
LMB_UE_27 : in STD_LOGIC;
LMB_Byte_Enable_27 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_28 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_28 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_28 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_28 : out STD_LOGIC;
LMB_Read_Strobe_28 : out STD_LOGIC;
LMB_Write_Strobe_28 : out STD_LOGIC;
LMB_Ready_28 : in STD_LOGIC;
LMB_Wait_28 : in STD_LOGIC;
LMB_CE_28 : in STD_LOGIC;
LMB_UE_28 : in STD_LOGIC;
LMB_Byte_Enable_28 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_29 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_29 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_29 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_29 : out STD_LOGIC;
LMB_Read_Strobe_29 : out STD_LOGIC;
LMB_Write_Strobe_29 : out STD_LOGIC;
LMB_Ready_29 : in STD_LOGIC;
LMB_Wait_29 : in STD_LOGIC;
LMB_CE_29 : in STD_LOGIC;
LMB_UE_29 : in STD_LOGIC;
LMB_Byte_Enable_29 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_30 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_30 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_30 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_30 : out STD_LOGIC;
LMB_Read_Strobe_30 : out STD_LOGIC;
LMB_Write_Strobe_30 : out STD_LOGIC;
LMB_Ready_30 : in STD_LOGIC;
LMB_Wait_30 : in STD_LOGIC;
LMB_CE_30 : in STD_LOGIC;
LMB_UE_30 : in STD_LOGIC;
LMB_Byte_Enable_30 : out STD_LOGIC_VECTOR ( 0 to 3 );
LMB_Data_Addr_31 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Read_31 : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Data_Write_31 : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Addr_Strobe_31 : out STD_LOGIC;
LMB_Read_Strobe_31 : out STD_LOGIC;
LMB_Write_Strobe_31 : out STD_LOGIC;
LMB_Ready_31 : in STD_LOGIC;
LMB_Wait_31 : in STD_LOGIC;
LMB_CE_31 : in STD_LOGIC;
LMB_UE_31 : in STD_LOGIC;
LMB_Byte_Enable_31 : out STD_LOGIC_VECTOR ( 0 to 3 );
M_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXIS_TID : out STD_LOGIC_VECTOR ( 6 downto 0 );
M_AXIS_TREADY : in STD_LOGIC;
M_AXIS_TVALID : out STD_LOGIC;
TRACE_CLK_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_Disable_0 : out STD_LOGIC;
Dbg_Clk_0 : out STD_LOGIC;
Dbg_TDI_0 : out STD_LOGIC;
Dbg_TDO_0 : in STD_LOGIC;
Dbg_Reg_En_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_0 : out STD_LOGIC;
Dbg_Shift_0 : out STD_LOGIC;
Dbg_Update_0 : out STD_LOGIC;
Dbg_Rst_0 : out STD_LOGIC;
Dbg_Trig_In_0 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_0 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_0 : out STD_LOGIC;
Dbg_TrData_0 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_0 : out STD_LOGIC;
Dbg_TrValid_0 : in STD_LOGIC;
Dbg_AWADDR_0 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_0 : out STD_LOGIC;
Dbg_AWREADY_0 : in STD_LOGIC;
Dbg_WDATA_0 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_0 : out STD_LOGIC;
Dbg_WREADY_0 : in STD_LOGIC;
Dbg_BRESP_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_0 : in STD_LOGIC;
Dbg_BREADY_0 : out STD_LOGIC;
Dbg_ARADDR_0 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_0 : out STD_LOGIC;
Dbg_ARREADY_0 : in STD_LOGIC;
Dbg_RDATA_0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_0 : in STD_LOGIC;
Dbg_RREADY_0 : out STD_LOGIC;
Dbg_Disable_1 : out STD_LOGIC;
Dbg_Clk_1 : out STD_LOGIC;
Dbg_TDI_1 : out STD_LOGIC;
Dbg_TDO_1 : in STD_LOGIC;
Dbg_Reg_En_1 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_1 : out STD_LOGIC;
Dbg_Shift_1 : out STD_LOGIC;
Dbg_Update_1 : out STD_LOGIC;
Dbg_Rst_1 : out STD_LOGIC;
Dbg_Trig_In_1 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_1 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_1 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_1 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_1 : out STD_LOGIC;
Dbg_TrData_1 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_1 : out STD_LOGIC;
Dbg_TrValid_1 : in STD_LOGIC;
Dbg_AWADDR_1 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_1 : out STD_LOGIC;
Dbg_AWREADY_1 : in STD_LOGIC;
Dbg_WDATA_1 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_1 : out STD_LOGIC;
Dbg_WREADY_1 : in STD_LOGIC;
Dbg_BRESP_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_1 : in STD_LOGIC;
Dbg_BREADY_1 : out STD_LOGIC;
Dbg_ARADDR_1 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_1 : out STD_LOGIC;
Dbg_ARREADY_1 : in STD_LOGIC;
Dbg_RDATA_1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_1 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_1 : in STD_LOGIC;
Dbg_RREADY_1 : out STD_LOGIC;
Dbg_Disable_2 : out STD_LOGIC;
Dbg_Clk_2 : out STD_LOGIC;
Dbg_TDI_2 : out STD_LOGIC;
Dbg_TDO_2 : in STD_LOGIC;
Dbg_Reg_En_2 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_2 : out STD_LOGIC;
Dbg_Shift_2 : out STD_LOGIC;
Dbg_Update_2 : out STD_LOGIC;
Dbg_Rst_2 : out STD_LOGIC;
Dbg_Trig_In_2 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_2 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_2 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_2 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_2 : out STD_LOGIC;
Dbg_TrData_2 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_2 : out STD_LOGIC;
Dbg_TrValid_2 : in STD_LOGIC;
Dbg_AWADDR_2 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_2 : out STD_LOGIC;
Dbg_AWREADY_2 : in STD_LOGIC;
Dbg_WDATA_2 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_2 : out STD_LOGIC;
Dbg_WREADY_2 : in STD_LOGIC;
Dbg_BRESP_2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_2 : in STD_LOGIC;
Dbg_BREADY_2 : out STD_LOGIC;
Dbg_ARADDR_2 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_2 : out STD_LOGIC;
Dbg_ARREADY_2 : in STD_LOGIC;
Dbg_RDATA_2 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_2 : in STD_LOGIC;
Dbg_RREADY_2 : out STD_LOGIC;
Dbg_Disable_3 : out STD_LOGIC;
Dbg_Clk_3 : out STD_LOGIC;
Dbg_TDI_3 : out STD_LOGIC;
Dbg_TDO_3 : in STD_LOGIC;
Dbg_Reg_En_3 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_3 : out STD_LOGIC;
Dbg_Shift_3 : out STD_LOGIC;
Dbg_Update_3 : out STD_LOGIC;
Dbg_Rst_3 : out STD_LOGIC;
Dbg_Trig_In_3 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_3 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_3 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_3 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_3 : out STD_LOGIC;
Dbg_TrData_3 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_3 : out STD_LOGIC;
Dbg_TrValid_3 : in STD_LOGIC;
Dbg_AWADDR_3 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_3 : out STD_LOGIC;
Dbg_AWREADY_3 : in STD_LOGIC;
Dbg_WDATA_3 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_3 : out STD_LOGIC;
Dbg_WREADY_3 : in STD_LOGIC;
Dbg_BRESP_3 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_3 : in STD_LOGIC;
Dbg_BREADY_3 : out STD_LOGIC;
Dbg_ARADDR_3 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_3 : out STD_LOGIC;
Dbg_ARREADY_3 : in STD_LOGIC;
Dbg_RDATA_3 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_3 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_3 : in STD_LOGIC;
Dbg_RREADY_3 : out STD_LOGIC;
Dbg_Disable_4 : out STD_LOGIC;
Dbg_Clk_4 : out STD_LOGIC;
Dbg_TDI_4 : out STD_LOGIC;
Dbg_TDO_4 : in STD_LOGIC;
Dbg_Reg_En_4 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_4 : out STD_LOGIC;
Dbg_Shift_4 : out STD_LOGIC;
Dbg_Update_4 : out STD_LOGIC;
Dbg_Rst_4 : out STD_LOGIC;
Dbg_Trig_In_4 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_4 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_4 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_4 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_4 : out STD_LOGIC;
Dbg_TrData_4 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_4 : out STD_LOGIC;
Dbg_TrValid_4 : in STD_LOGIC;
Dbg_AWADDR_4 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_4 : out STD_LOGIC;
Dbg_AWREADY_4 : in STD_LOGIC;
Dbg_WDATA_4 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_4 : out STD_LOGIC;
Dbg_WREADY_4 : in STD_LOGIC;
Dbg_BRESP_4 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_4 : in STD_LOGIC;
Dbg_BREADY_4 : out STD_LOGIC;
Dbg_ARADDR_4 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_4 : out STD_LOGIC;
Dbg_ARREADY_4 : in STD_LOGIC;
Dbg_RDATA_4 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_4 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_4 : in STD_LOGIC;
Dbg_RREADY_4 : out STD_LOGIC;
Dbg_Disable_5 : out STD_LOGIC;
Dbg_Clk_5 : out STD_LOGIC;
Dbg_TDI_5 : out STD_LOGIC;
Dbg_TDO_5 : in STD_LOGIC;
Dbg_Reg_En_5 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_5 : out STD_LOGIC;
Dbg_Shift_5 : out STD_LOGIC;
Dbg_Update_5 : out STD_LOGIC;
Dbg_Rst_5 : out STD_LOGIC;
Dbg_Trig_In_5 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_5 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_5 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_5 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_5 : out STD_LOGIC;
Dbg_TrData_5 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_5 : out STD_LOGIC;
Dbg_TrValid_5 : in STD_LOGIC;
Dbg_AWADDR_5 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_5 : out STD_LOGIC;
Dbg_AWREADY_5 : in STD_LOGIC;
Dbg_WDATA_5 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_5 : out STD_LOGIC;
Dbg_WREADY_5 : in STD_LOGIC;
Dbg_BRESP_5 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_5 : in STD_LOGIC;
Dbg_BREADY_5 : out STD_LOGIC;
Dbg_ARADDR_5 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_5 : out STD_LOGIC;
Dbg_ARREADY_5 : in STD_LOGIC;
Dbg_RDATA_5 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_5 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_5 : in STD_LOGIC;
Dbg_RREADY_5 : out STD_LOGIC;
Dbg_Disable_6 : out STD_LOGIC;
Dbg_Clk_6 : out STD_LOGIC;
Dbg_TDI_6 : out STD_LOGIC;
Dbg_TDO_6 : in STD_LOGIC;
Dbg_Reg_En_6 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_6 : out STD_LOGIC;
Dbg_Shift_6 : out STD_LOGIC;
Dbg_Update_6 : out STD_LOGIC;
Dbg_Rst_6 : out STD_LOGIC;
Dbg_Trig_In_6 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_6 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_6 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_6 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_6 : out STD_LOGIC;
Dbg_TrData_6 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_6 : out STD_LOGIC;
Dbg_TrValid_6 : in STD_LOGIC;
Dbg_AWADDR_6 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_6 : out STD_LOGIC;
Dbg_AWREADY_6 : in STD_LOGIC;
Dbg_WDATA_6 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_6 : out STD_LOGIC;
Dbg_WREADY_6 : in STD_LOGIC;
Dbg_BRESP_6 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_6 : in STD_LOGIC;
Dbg_BREADY_6 : out STD_LOGIC;
Dbg_ARADDR_6 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_6 : out STD_LOGIC;
Dbg_ARREADY_6 : in STD_LOGIC;
Dbg_RDATA_6 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_6 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_6 : in STD_LOGIC;
Dbg_RREADY_6 : out STD_LOGIC;
Dbg_Disable_7 : out STD_LOGIC;
Dbg_Clk_7 : out STD_LOGIC;
Dbg_TDI_7 : out STD_LOGIC;
Dbg_TDO_7 : in STD_LOGIC;
Dbg_Reg_En_7 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_7 : out STD_LOGIC;
Dbg_Shift_7 : out STD_LOGIC;
Dbg_Update_7 : out STD_LOGIC;
Dbg_Rst_7 : out STD_LOGIC;
Dbg_Trig_In_7 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_7 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_7 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_7 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_7 : out STD_LOGIC;
Dbg_TrData_7 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_7 : out STD_LOGIC;
Dbg_TrValid_7 : in STD_LOGIC;
Dbg_AWADDR_7 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_7 : out STD_LOGIC;
Dbg_AWREADY_7 : in STD_LOGIC;
Dbg_WDATA_7 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_7 : out STD_LOGIC;
Dbg_WREADY_7 : in STD_LOGIC;
Dbg_BRESP_7 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_7 : in STD_LOGIC;
Dbg_BREADY_7 : out STD_LOGIC;
Dbg_ARADDR_7 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_7 : out STD_LOGIC;
Dbg_ARREADY_7 : in STD_LOGIC;
Dbg_RDATA_7 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_7 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_7 : in STD_LOGIC;
Dbg_RREADY_7 : out STD_LOGIC;
Dbg_Disable_8 : out STD_LOGIC;
Dbg_Clk_8 : out STD_LOGIC;
Dbg_TDI_8 : out STD_LOGIC;
Dbg_TDO_8 : in STD_LOGIC;
Dbg_Reg_En_8 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_8 : out STD_LOGIC;
Dbg_Shift_8 : out STD_LOGIC;
Dbg_Update_8 : out STD_LOGIC;
Dbg_Rst_8 : out STD_LOGIC;
Dbg_Trig_In_8 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_8 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_8 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_8 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_8 : out STD_LOGIC;
Dbg_TrData_8 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_8 : out STD_LOGIC;
Dbg_TrValid_8 : in STD_LOGIC;
Dbg_AWADDR_8 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_8 : out STD_LOGIC;
Dbg_AWREADY_8 : in STD_LOGIC;
Dbg_WDATA_8 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_8 : out STD_LOGIC;
Dbg_WREADY_8 : in STD_LOGIC;
Dbg_BRESP_8 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_8 : in STD_LOGIC;
Dbg_BREADY_8 : out STD_LOGIC;
Dbg_ARADDR_8 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_8 : out STD_LOGIC;
Dbg_ARREADY_8 : in STD_LOGIC;
Dbg_RDATA_8 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_8 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_8 : in STD_LOGIC;
Dbg_RREADY_8 : out STD_LOGIC;
Dbg_Disable_9 : out STD_LOGIC;
Dbg_Clk_9 : out STD_LOGIC;
Dbg_TDI_9 : out STD_LOGIC;
Dbg_TDO_9 : in STD_LOGIC;
Dbg_Reg_En_9 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_9 : out STD_LOGIC;
Dbg_Shift_9 : out STD_LOGIC;
Dbg_Update_9 : out STD_LOGIC;
Dbg_Rst_9 : out STD_LOGIC;
Dbg_Trig_In_9 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_9 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_9 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_9 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_9 : out STD_LOGIC;
Dbg_TrData_9 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_9 : out STD_LOGIC;
Dbg_TrValid_9 : in STD_LOGIC;
Dbg_AWADDR_9 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_9 : out STD_LOGIC;
Dbg_AWREADY_9 : in STD_LOGIC;
Dbg_WDATA_9 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_9 : out STD_LOGIC;
Dbg_WREADY_9 : in STD_LOGIC;
Dbg_BRESP_9 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_9 : in STD_LOGIC;
Dbg_BREADY_9 : out STD_LOGIC;
Dbg_ARADDR_9 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_9 : out STD_LOGIC;
Dbg_ARREADY_9 : in STD_LOGIC;
Dbg_RDATA_9 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_9 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_9 : in STD_LOGIC;
Dbg_RREADY_9 : out STD_LOGIC;
Dbg_Disable_10 : out STD_LOGIC;
Dbg_Clk_10 : out STD_LOGIC;
Dbg_TDI_10 : out STD_LOGIC;
Dbg_TDO_10 : in STD_LOGIC;
Dbg_Reg_En_10 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_10 : out STD_LOGIC;
Dbg_Shift_10 : out STD_LOGIC;
Dbg_Update_10 : out STD_LOGIC;
Dbg_Rst_10 : out STD_LOGIC;
Dbg_Trig_In_10 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_10 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_10 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_10 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_10 : out STD_LOGIC;
Dbg_TrData_10 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_10 : out STD_LOGIC;
Dbg_TrValid_10 : in STD_LOGIC;
Dbg_AWADDR_10 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_10 : out STD_LOGIC;
Dbg_AWREADY_10 : in STD_LOGIC;
Dbg_WDATA_10 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_10 : out STD_LOGIC;
Dbg_WREADY_10 : in STD_LOGIC;
Dbg_BRESP_10 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_10 : in STD_LOGIC;
Dbg_BREADY_10 : out STD_LOGIC;
Dbg_ARADDR_10 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_10 : out STD_LOGIC;
Dbg_ARREADY_10 : in STD_LOGIC;
Dbg_RDATA_10 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_10 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_10 : in STD_LOGIC;
Dbg_RREADY_10 : out STD_LOGIC;
Dbg_Disable_11 : out STD_LOGIC;
Dbg_Clk_11 : out STD_LOGIC;
Dbg_TDI_11 : out STD_LOGIC;
Dbg_TDO_11 : in STD_LOGIC;
Dbg_Reg_En_11 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_11 : out STD_LOGIC;
Dbg_Shift_11 : out STD_LOGIC;
Dbg_Update_11 : out STD_LOGIC;
Dbg_Rst_11 : out STD_LOGIC;
Dbg_Trig_In_11 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_11 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_11 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_11 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_11 : out STD_LOGIC;
Dbg_TrData_11 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_11 : out STD_LOGIC;
Dbg_TrValid_11 : in STD_LOGIC;
Dbg_AWADDR_11 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_11 : out STD_LOGIC;
Dbg_AWREADY_11 : in STD_LOGIC;
Dbg_WDATA_11 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_11 : out STD_LOGIC;
Dbg_WREADY_11 : in STD_LOGIC;
Dbg_BRESP_11 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_11 : in STD_LOGIC;
Dbg_BREADY_11 : out STD_LOGIC;
Dbg_ARADDR_11 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_11 : out STD_LOGIC;
Dbg_ARREADY_11 : in STD_LOGIC;
Dbg_RDATA_11 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_11 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_11 : in STD_LOGIC;
Dbg_RREADY_11 : out STD_LOGIC;
Dbg_Disable_12 : out STD_LOGIC;
Dbg_Clk_12 : out STD_LOGIC;
Dbg_TDI_12 : out STD_LOGIC;
Dbg_TDO_12 : in STD_LOGIC;
Dbg_Reg_En_12 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_12 : out STD_LOGIC;
Dbg_Shift_12 : out STD_LOGIC;
Dbg_Update_12 : out STD_LOGIC;
Dbg_Rst_12 : out STD_LOGIC;
Dbg_Trig_In_12 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_12 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_12 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_12 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_12 : out STD_LOGIC;
Dbg_TrData_12 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_12 : out STD_LOGIC;
Dbg_TrValid_12 : in STD_LOGIC;
Dbg_AWADDR_12 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_12 : out STD_LOGIC;
Dbg_AWREADY_12 : in STD_LOGIC;
Dbg_WDATA_12 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_12 : out STD_LOGIC;
Dbg_WREADY_12 : in STD_LOGIC;
Dbg_BRESP_12 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_12 : in STD_LOGIC;
Dbg_BREADY_12 : out STD_LOGIC;
Dbg_ARADDR_12 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_12 : out STD_LOGIC;
Dbg_ARREADY_12 : in STD_LOGIC;
Dbg_RDATA_12 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_12 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_12 : in STD_LOGIC;
Dbg_RREADY_12 : out STD_LOGIC;
Dbg_Disable_13 : out STD_LOGIC;
Dbg_Clk_13 : out STD_LOGIC;
Dbg_TDI_13 : out STD_LOGIC;
Dbg_TDO_13 : in STD_LOGIC;
Dbg_Reg_En_13 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_13 : out STD_LOGIC;
Dbg_Shift_13 : out STD_LOGIC;
Dbg_Update_13 : out STD_LOGIC;
Dbg_Rst_13 : out STD_LOGIC;
Dbg_Trig_In_13 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_13 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_13 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_13 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_13 : out STD_LOGIC;
Dbg_TrData_13 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_13 : out STD_LOGIC;
Dbg_TrValid_13 : in STD_LOGIC;
Dbg_AWADDR_13 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_13 : out STD_LOGIC;
Dbg_AWREADY_13 : in STD_LOGIC;
Dbg_WDATA_13 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_13 : out STD_LOGIC;
Dbg_WREADY_13 : in STD_LOGIC;
Dbg_BRESP_13 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_13 : in STD_LOGIC;
Dbg_BREADY_13 : out STD_LOGIC;
Dbg_ARADDR_13 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_13 : out STD_LOGIC;
Dbg_ARREADY_13 : in STD_LOGIC;
Dbg_RDATA_13 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_13 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_13 : in STD_LOGIC;
Dbg_RREADY_13 : out STD_LOGIC;
Dbg_Disable_14 : out STD_LOGIC;
Dbg_Clk_14 : out STD_LOGIC;
Dbg_TDI_14 : out STD_LOGIC;
Dbg_TDO_14 : in STD_LOGIC;
Dbg_Reg_En_14 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_14 : out STD_LOGIC;
Dbg_Shift_14 : out STD_LOGIC;
Dbg_Update_14 : out STD_LOGIC;
Dbg_Rst_14 : out STD_LOGIC;
Dbg_Trig_In_14 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_14 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_14 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_14 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_14 : out STD_LOGIC;
Dbg_TrData_14 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_14 : out STD_LOGIC;
Dbg_TrValid_14 : in STD_LOGIC;
Dbg_AWADDR_14 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_14 : out STD_LOGIC;
Dbg_AWREADY_14 : in STD_LOGIC;
Dbg_WDATA_14 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_14 : out STD_LOGIC;
Dbg_WREADY_14 : in STD_LOGIC;
Dbg_BRESP_14 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_14 : in STD_LOGIC;
Dbg_BREADY_14 : out STD_LOGIC;
Dbg_ARADDR_14 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_14 : out STD_LOGIC;
Dbg_ARREADY_14 : in STD_LOGIC;
Dbg_RDATA_14 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_14 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_14 : in STD_LOGIC;
Dbg_RREADY_14 : out STD_LOGIC;
Dbg_Disable_15 : out STD_LOGIC;
Dbg_Clk_15 : out STD_LOGIC;
Dbg_TDI_15 : out STD_LOGIC;
Dbg_TDO_15 : in STD_LOGIC;
Dbg_Reg_En_15 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_15 : out STD_LOGIC;
Dbg_Shift_15 : out STD_LOGIC;
Dbg_Update_15 : out STD_LOGIC;
Dbg_Rst_15 : out STD_LOGIC;
Dbg_Trig_In_15 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_15 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_15 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_15 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_15 : out STD_LOGIC;
Dbg_TrData_15 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_15 : out STD_LOGIC;
Dbg_TrValid_15 : in STD_LOGIC;
Dbg_AWADDR_15 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_15 : out STD_LOGIC;
Dbg_AWREADY_15 : in STD_LOGIC;
Dbg_WDATA_15 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_15 : out STD_LOGIC;
Dbg_WREADY_15 : in STD_LOGIC;
Dbg_BRESP_15 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_15 : in STD_LOGIC;
Dbg_BREADY_15 : out STD_LOGIC;
Dbg_ARADDR_15 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_15 : out STD_LOGIC;
Dbg_ARREADY_15 : in STD_LOGIC;
Dbg_RDATA_15 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_15 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_15 : in STD_LOGIC;
Dbg_RREADY_15 : out STD_LOGIC;
Dbg_Disable_16 : out STD_LOGIC;
Dbg_Clk_16 : out STD_LOGIC;
Dbg_TDI_16 : out STD_LOGIC;
Dbg_TDO_16 : in STD_LOGIC;
Dbg_Reg_En_16 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_16 : out STD_LOGIC;
Dbg_Shift_16 : out STD_LOGIC;
Dbg_Update_16 : out STD_LOGIC;
Dbg_Rst_16 : out STD_LOGIC;
Dbg_Trig_In_16 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_16 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_16 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_16 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_16 : out STD_LOGIC;
Dbg_TrData_16 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_16 : out STD_LOGIC;
Dbg_TrValid_16 : in STD_LOGIC;
Dbg_AWADDR_16 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_16 : out STD_LOGIC;
Dbg_AWREADY_16 : in STD_LOGIC;
Dbg_WDATA_16 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_16 : out STD_LOGIC;
Dbg_WREADY_16 : in STD_LOGIC;
Dbg_BRESP_16 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_16 : in STD_LOGIC;
Dbg_BREADY_16 : out STD_LOGIC;
Dbg_ARADDR_16 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_16 : out STD_LOGIC;
Dbg_ARREADY_16 : in STD_LOGIC;
Dbg_RDATA_16 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_16 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_16 : in STD_LOGIC;
Dbg_RREADY_16 : out STD_LOGIC;
Dbg_Disable_17 : out STD_LOGIC;
Dbg_Clk_17 : out STD_LOGIC;
Dbg_TDI_17 : out STD_LOGIC;
Dbg_TDO_17 : in STD_LOGIC;
Dbg_Reg_En_17 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_17 : out STD_LOGIC;
Dbg_Shift_17 : out STD_LOGIC;
Dbg_Update_17 : out STD_LOGIC;
Dbg_Rst_17 : out STD_LOGIC;
Dbg_Trig_In_17 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_17 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_17 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_17 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_17 : out STD_LOGIC;
Dbg_TrData_17 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_17 : out STD_LOGIC;
Dbg_TrValid_17 : in STD_LOGIC;
Dbg_AWADDR_17 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_17 : out STD_LOGIC;
Dbg_AWREADY_17 : in STD_LOGIC;
Dbg_WDATA_17 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_17 : out STD_LOGIC;
Dbg_WREADY_17 : in STD_LOGIC;
Dbg_BRESP_17 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_17 : in STD_LOGIC;
Dbg_BREADY_17 : out STD_LOGIC;
Dbg_ARADDR_17 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_17 : out STD_LOGIC;
Dbg_ARREADY_17 : in STD_LOGIC;
Dbg_RDATA_17 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_17 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_17 : in STD_LOGIC;
Dbg_RREADY_17 : out STD_LOGIC;
Dbg_Disable_18 : out STD_LOGIC;
Dbg_Clk_18 : out STD_LOGIC;
Dbg_TDI_18 : out STD_LOGIC;
Dbg_TDO_18 : in STD_LOGIC;
Dbg_Reg_En_18 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_18 : out STD_LOGIC;
Dbg_Shift_18 : out STD_LOGIC;
Dbg_Update_18 : out STD_LOGIC;
Dbg_Rst_18 : out STD_LOGIC;
Dbg_Trig_In_18 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_18 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_18 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_18 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_18 : out STD_LOGIC;
Dbg_TrData_18 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_18 : out STD_LOGIC;
Dbg_TrValid_18 : in STD_LOGIC;
Dbg_AWADDR_18 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_18 : out STD_LOGIC;
Dbg_AWREADY_18 : in STD_LOGIC;
Dbg_WDATA_18 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_18 : out STD_LOGIC;
Dbg_WREADY_18 : in STD_LOGIC;
Dbg_BRESP_18 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_18 : in STD_LOGIC;
Dbg_BREADY_18 : out STD_LOGIC;
Dbg_ARADDR_18 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_18 : out STD_LOGIC;
Dbg_ARREADY_18 : in STD_LOGIC;
Dbg_RDATA_18 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_18 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_18 : in STD_LOGIC;
Dbg_RREADY_18 : out STD_LOGIC;
Dbg_Disable_19 : out STD_LOGIC;
Dbg_Clk_19 : out STD_LOGIC;
Dbg_TDI_19 : out STD_LOGIC;
Dbg_TDO_19 : in STD_LOGIC;
Dbg_Reg_En_19 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_19 : out STD_LOGIC;
Dbg_Shift_19 : out STD_LOGIC;
Dbg_Update_19 : out STD_LOGIC;
Dbg_Rst_19 : out STD_LOGIC;
Dbg_Trig_In_19 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_19 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_19 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_19 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_19 : out STD_LOGIC;
Dbg_TrData_19 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_19 : out STD_LOGIC;
Dbg_TrValid_19 : in STD_LOGIC;
Dbg_AWADDR_19 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_19 : out STD_LOGIC;
Dbg_AWREADY_19 : in STD_LOGIC;
Dbg_WDATA_19 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_19 : out STD_LOGIC;
Dbg_WREADY_19 : in STD_LOGIC;
Dbg_BRESP_19 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_19 : in STD_LOGIC;
Dbg_BREADY_19 : out STD_LOGIC;
Dbg_ARADDR_19 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_19 : out STD_LOGIC;
Dbg_ARREADY_19 : in STD_LOGIC;
Dbg_RDATA_19 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_19 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_19 : in STD_LOGIC;
Dbg_RREADY_19 : out STD_LOGIC;
Dbg_Disable_20 : out STD_LOGIC;
Dbg_Clk_20 : out STD_LOGIC;
Dbg_TDI_20 : out STD_LOGIC;
Dbg_TDO_20 : in STD_LOGIC;
Dbg_Reg_En_20 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_20 : out STD_LOGIC;
Dbg_Shift_20 : out STD_LOGIC;
Dbg_Update_20 : out STD_LOGIC;
Dbg_Rst_20 : out STD_LOGIC;
Dbg_Trig_In_20 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_20 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_20 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_20 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_20 : out STD_LOGIC;
Dbg_TrData_20 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_20 : out STD_LOGIC;
Dbg_TrValid_20 : in STD_LOGIC;
Dbg_AWADDR_20 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_20 : out STD_LOGIC;
Dbg_AWREADY_20 : in STD_LOGIC;
Dbg_WDATA_20 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_20 : out STD_LOGIC;
Dbg_WREADY_20 : in STD_LOGIC;
Dbg_BRESP_20 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_20 : in STD_LOGIC;
Dbg_BREADY_20 : out STD_LOGIC;
Dbg_ARADDR_20 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_20 : out STD_LOGIC;
Dbg_ARREADY_20 : in STD_LOGIC;
Dbg_RDATA_20 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_20 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_20 : in STD_LOGIC;
Dbg_RREADY_20 : out STD_LOGIC;
Dbg_Disable_21 : out STD_LOGIC;
Dbg_Clk_21 : out STD_LOGIC;
Dbg_TDI_21 : out STD_LOGIC;
Dbg_TDO_21 : in STD_LOGIC;
Dbg_Reg_En_21 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_21 : out STD_LOGIC;
Dbg_Shift_21 : out STD_LOGIC;
Dbg_Update_21 : out STD_LOGIC;
Dbg_Rst_21 : out STD_LOGIC;
Dbg_Trig_In_21 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_21 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_21 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_21 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_21 : out STD_LOGIC;
Dbg_TrData_21 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_21 : out STD_LOGIC;
Dbg_TrValid_21 : in STD_LOGIC;
Dbg_AWADDR_21 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_21 : out STD_LOGIC;
Dbg_AWREADY_21 : in STD_LOGIC;
Dbg_WDATA_21 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_21 : out STD_LOGIC;
Dbg_WREADY_21 : in STD_LOGIC;
Dbg_BRESP_21 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_21 : in STD_LOGIC;
Dbg_BREADY_21 : out STD_LOGIC;
Dbg_ARADDR_21 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_21 : out STD_LOGIC;
Dbg_ARREADY_21 : in STD_LOGIC;
Dbg_RDATA_21 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_21 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_21 : in STD_LOGIC;
Dbg_RREADY_21 : out STD_LOGIC;
Dbg_Disable_22 : out STD_LOGIC;
Dbg_Clk_22 : out STD_LOGIC;
Dbg_TDI_22 : out STD_LOGIC;
Dbg_TDO_22 : in STD_LOGIC;
Dbg_Reg_En_22 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_22 : out STD_LOGIC;
Dbg_Shift_22 : out STD_LOGIC;
Dbg_Update_22 : out STD_LOGIC;
Dbg_Rst_22 : out STD_LOGIC;
Dbg_Trig_In_22 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_22 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_22 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_22 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_22 : out STD_LOGIC;
Dbg_TrData_22 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_22 : out STD_LOGIC;
Dbg_TrValid_22 : in STD_LOGIC;
Dbg_AWADDR_22 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_22 : out STD_LOGIC;
Dbg_AWREADY_22 : in STD_LOGIC;
Dbg_WDATA_22 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_22 : out STD_LOGIC;
Dbg_WREADY_22 : in STD_LOGIC;
Dbg_BRESP_22 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_22 : in STD_LOGIC;
Dbg_BREADY_22 : out STD_LOGIC;
Dbg_ARADDR_22 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_22 : out STD_LOGIC;
Dbg_ARREADY_22 : in STD_LOGIC;
Dbg_RDATA_22 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_22 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_22 : in STD_LOGIC;
Dbg_RREADY_22 : out STD_LOGIC;
Dbg_Disable_23 : out STD_LOGIC;
Dbg_Clk_23 : out STD_LOGIC;
Dbg_TDI_23 : out STD_LOGIC;
Dbg_TDO_23 : in STD_LOGIC;
Dbg_Reg_En_23 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_23 : out STD_LOGIC;
Dbg_Shift_23 : out STD_LOGIC;
Dbg_Update_23 : out STD_LOGIC;
Dbg_Rst_23 : out STD_LOGIC;
Dbg_Trig_In_23 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_23 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_23 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_23 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_23 : out STD_LOGIC;
Dbg_TrData_23 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_23 : out STD_LOGIC;
Dbg_TrValid_23 : in STD_LOGIC;
Dbg_AWADDR_23 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_23 : out STD_LOGIC;
Dbg_AWREADY_23 : in STD_LOGIC;
Dbg_WDATA_23 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_23 : out STD_LOGIC;
Dbg_WREADY_23 : in STD_LOGIC;
Dbg_BRESP_23 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_23 : in STD_LOGIC;
Dbg_BREADY_23 : out STD_LOGIC;
Dbg_ARADDR_23 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_23 : out STD_LOGIC;
Dbg_ARREADY_23 : in STD_LOGIC;
Dbg_RDATA_23 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_23 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_23 : in STD_LOGIC;
Dbg_RREADY_23 : out STD_LOGIC;
Dbg_Disable_24 : out STD_LOGIC;
Dbg_Clk_24 : out STD_LOGIC;
Dbg_TDI_24 : out STD_LOGIC;
Dbg_TDO_24 : in STD_LOGIC;
Dbg_Reg_En_24 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_24 : out STD_LOGIC;
Dbg_Shift_24 : out STD_LOGIC;
Dbg_Update_24 : out STD_LOGIC;
Dbg_Rst_24 : out STD_LOGIC;
Dbg_Trig_In_24 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_24 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_24 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_24 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_24 : out STD_LOGIC;
Dbg_TrData_24 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_24 : out STD_LOGIC;
Dbg_TrValid_24 : in STD_LOGIC;
Dbg_AWADDR_24 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_24 : out STD_LOGIC;
Dbg_AWREADY_24 : in STD_LOGIC;
Dbg_WDATA_24 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_24 : out STD_LOGIC;
Dbg_WREADY_24 : in STD_LOGIC;
Dbg_BRESP_24 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_24 : in STD_LOGIC;
Dbg_BREADY_24 : out STD_LOGIC;
Dbg_ARADDR_24 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_24 : out STD_LOGIC;
Dbg_ARREADY_24 : in STD_LOGIC;
Dbg_RDATA_24 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_24 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_24 : in STD_LOGIC;
Dbg_RREADY_24 : out STD_LOGIC;
Dbg_Disable_25 : out STD_LOGIC;
Dbg_Clk_25 : out STD_LOGIC;
Dbg_TDI_25 : out STD_LOGIC;
Dbg_TDO_25 : in STD_LOGIC;
Dbg_Reg_En_25 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_25 : out STD_LOGIC;
Dbg_Shift_25 : out STD_LOGIC;
Dbg_Update_25 : out STD_LOGIC;
Dbg_Rst_25 : out STD_LOGIC;
Dbg_Trig_In_25 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_25 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_25 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_25 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_25 : out STD_LOGIC;
Dbg_TrData_25 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_25 : out STD_LOGIC;
Dbg_TrValid_25 : in STD_LOGIC;
Dbg_AWADDR_25 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_25 : out STD_LOGIC;
Dbg_AWREADY_25 : in STD_LOGIC;
Dbg_WDATA_25 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_25 : out STD_LOGIC;
Dbg_WREADY_25 : in STD_LOGIC;
Dbg_BRESP_25 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_25 : in STD_LOGIC;
Dbg_BREADY_25 : out STD_LOGIC;
Dbg_ARADDR_25 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_25 : out STD_LOGIC;
Dbg_ARREADY_25 : in STD_LOGIC;
Dbg_RDATA_25 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_25 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_25 : in STD_LOGIC;
Dbg_RREADY_25 : out STD_LOGIC;
Dbg_Disable_26 : out STD_LOGIC;
Dbg_Clk_26 : out STD_LOGIC;
Dbg_TDI_26 : out STD_LOGIC;
Dbg_TDO_26 : in STD_LOGIC;
Dbg_Reg_En_26 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_26 : out STD_LOGIC;
Dbg_Shift_26 : out STD_LOGIC;
Dbg_Update_26 : out STD_LOGIC;
Dbg_Rst_26 : out STD_LOGIC;
Dbg_Trig_In_26 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_26 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_26 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_26 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_26 : out STD_LOGIC;
Dbg_TrData_26 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_26 : out STD_LOGIC;
Dbg_TrValid_26 : in STD_LOGIC;
Dbg_AWADDR_26 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_26 : out STD_LOGIC;
Dbg_AWREADY_26 : in STD_LOGIC;
Dbg_WDATA_26 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_26 : out STD_LOGIC;
Dbg_WREADY_26 : in STD_LOGIC;
Dbg_BRESP_26 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_26 : in STD_LOGIC;
Dbg_BREADY_26 : out STD_LOGIC;
Dbg_ARADDR_26 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_26 : out STD_LOGIC;
Dbg_ARREADY_26 : in STD_LOGIC;
Dbg_RDATA_26 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_26 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_26 : in STD_LOGIC;
Dbg_RREADY_26 : out STD_LOGIC;
Dbg_Disable_27 : out STD_LOGIC;
Dbg_Clk_27 : out STD_LOGIC;
Dbg_TDI_27 : out STD_LOGIC;
Dbg_TDO_27 : in STD_LOGIC;
Dbg_Reg_En_27 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_27 : out STD_LOGIC;
Dbg_Shift_27 : out STD_LOGIC;
Dbg_Update_27 : out STD_LOGIC;
Dbg_Rst_27 : out STD_LOGIC;
Dbg_Trig_In_27 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_27 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_27 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_27 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_27 : out STD_LOGIC;
Dbg_TrData_27 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_27 : out STD_LOGIC;
Dbg_TrValid_27 : in STD_LOGIC;
Dbg_AWADDR_27 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_27 : out STD_LOGIC;
Dbg_AWREADY_27 : in STD_LOGIC;
Dbg_WDATA_27 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_27 : out STD_LOGIC;
Dbg_WREADY_27 : in STD_LOGIC;
Dbg_BRESP_27 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_27 : in STD_LOGIC;
Dbg_BREADY_27 : out STD_LOGIC;
Dbg_ARADDR_27 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_27 : out STD_LOGIC;
Dbg_ARREADY_27 : in STD_LOGIC;
Dbg_RDATA_27 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_27 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_27 : in STD_LOGIC;
Dbg_RREADY_27 : out STD_LOGIC;
Dbg_Disable_28 : out STD_LOGIC;
Dbg_Clk_28 : out STD_LOGIC;
Dbg_TDI_28 : out STD_LOGIC;
Dbg_TDO_28 : in STD_LOGIC;
Dbg_Reg_En_28 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_28 : out STD_LOGIC;
Dbg_Shift_28 : out STD_LOGIC;
Dbg_Update_28 : out STD_LOGIC;
Dbg_Rst_28 : out STD_LOGIC;
Dbg_Trig_In_28 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_28 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_28 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_28 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_28 : out STD_LOGIC;
Dbg_TrData_28 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_28 : out STD_LOGIC;
Dbg_TrValid_28 : in STD_LOGIC;
Dbg_AWADDR_28 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_28 : out STD_LOGIC;
Dbg_AWREADY_28 : in STD_LOGIC;
Dbg_WDATA_28 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_28 : out STD_LOGIC;
Dbg_WREADY_28 : in STD_LOGIC;
Dbg_BRESP_28 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_28 : in STD_LOGIC;
Dbg_BREADY_28 : out STD_LOGIC;
Dbg_ARADDR_28 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_28 : out STD_LOGIC;
Dbg_ARREADY_28 : in STD_LOGIC;
Dbg_RDATA_28 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_28 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_28 : in STD_LOGIC;
Dbg_RREADY_28 : out STD_LOGIC;
Dbg_Disable_29 : out STD_LOGIC;
Dbg_Clk_29 : out STD_LOGIC;
Dbg_TDI_29 : out STD_LOGIC;
Dbg_TDO_29 : in STD_LOGIC;
Dbg_Reg_En_29 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_29 : out STD_LOGIC;
Dbg_Shift_29 : out STD_LOGIC;
Dbg_Update_29 : out STD_LOGIC;
Dbg_Rst_29 : out STD_LOGIC;
Dbg_Trig_In_29 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_29 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_29 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_29 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_29 : out STD_LOGIC;
Dbg_TrData_29 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_29 : out STD_LOGIC;
Dbg_TrValid_29 : in STD_LOGIC;
Dbg_AWADDR_29 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_29 : out STD_LOGIC;
Dbg_AWREADY_29 : in STD_LOGIC;
Dbg_WDATA_29 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_29 : out STD_LOGIC;
Dbg_WREADY_29 : in STD_LOGIC;
Dbg_BRESP_29 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_29 : in STD_LOGIC;
Dbg_BREADY_29 : out STD_LOGIC;
Dbg_ARADDR_29 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_29 : out STD_LOGIC;
Dbg_ARREADY_29 : in STD_LOGIC;
Dbg_RDATA_29 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_29 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_29 : in STD_LOGIC;
Dbg_RREADY_29 : out STD_LOGIC;
Dbg_Disable_30 : out STD_LOGIC;
Dbg_Clk_30 : out STD_LOGIC;
Dbg_TDI_30 : out STD_LOGIC;
Dbg_TDO_30 : in STD_LOGIC;
Dbg_Reg_En_30 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_30 : out STD_LOGIC;
Dbg_Shift_30 : out STD_LOGIC;
Dbg_Update_30 : out STD_LOGIC;
Dbg_Rst_30 : out STD_LOGIC;
Dbg_Trig_In_30 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_30 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_30 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_30 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_30 : out STD_LOGIC;
Dbg_TrData_30 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_30 : out STD_LOGIC;
Dbg_TrValid_30 : in STD_LOGIC;
Dbg_AWADDR_30 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_30 : out STD_LOGIC;
Dbg_AWREADY_30 : in STD_LOGIC;
Dbg_WDATA_30 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_30 : out STD_LOGIC;
Dbg_WREADY_30 : in STD_LOGIC;
Dbg_BRESP_30 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_30 : in STD_LOGIC;
Dbg_BREADY_30 : out STD_LOGIC;
Dbg_ARADDR_30 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_30 : out STD_LOGIC;
Dbg_ARREADY_30 : in STD_LOGIC;
Dbg_RDATA_30 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_30 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_30 : in STD_LOGIC;
Dbg_RREADY_30 : out STD_LOGIC;
Dbg_Disable_31 : out STD_LOGIC;
Dbg_Clk_31 : out STD_LOGIC;
Dbg_TDI_31 : out STD_LOGIC;
Dbg_TDO_31 : in STD_LOGIC;
Dbg_Reg_En_31 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_31 : out STD_LOGIC;
Dbg_Shift_31 : out STD_LOGIC;
Dbg_Update_31 : out STD_LOGIC;
Dbg_Rst_31 : out STD_LOGIC;
Dbg_Trig_In_31 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_In_31 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Out_31 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Trig_Ack_Out_31 : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_TrClk_31 : out STD_LOGIC;
Dbg_TrData_31 : in STD_LOGIC_VECTOR ( 0 to 35 );
Dbg_TrReady_31 : out STD_LOGIC;
Dbg_TrValid_31 : in STD_LOGIC;
Dbg_AWADDR_31 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_AWVALID_31 : out STD_LOGIC;
Dbg_AWREADY_31 : in STD_LOGIC;
Dbg_WDATA_31 : out STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_WVALID_31 : out STD_LOGIC;
Dbg_WREADY_31 : in STD_LOGIC;
Dbg_BRESP_31 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_BVALID_31 : in STD_LOGIC;
Dbg_BREADY_31 : out STD_LOGIC;
Dbg_ARADDR_31 : out STD_LOGIC_VECTOR ( 14 downto 2 );
Dbg_ARVALID_31 : out STD_LOGIC;
Dbg_ARREADY_31 : in STD_LOGIC;
Dbg_RDATA_31 : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dbg_RRESP_31 : in STD_LOGIC_VECTOR ( 1 downto 0 );
Dbg_RVALID_31 : in STD_LOGIC;
Dbg_RREADY_31 : out STD_LOGIC;
bscan_ext_tdi : in STD_LOGIC;
bscan_ext_reset : in STD_LOGIC;
bscan_ext_shift : in STD_LOGIC;
bscan_ext_update : in STD_LOGIC;
bscan_ext_capture : in STD_LOGIC;
bscan_ext_sel : in STD_LOGIC;
bscan_ext_drck : in STD_LOGIC;
bscan_ext_tdo : out STD_LOGIC;
Ext_JTAG_DRCK : out STD_LOGIC;
Ext_JTAG_RESET : out STD_LOGIC;
Ext_JTAG_SEL : out STD_LOGIC;
Ext_JTAG_CAPTURE : out STD_LOGIC;
Ext_JTAG_SHIFT : out STD_LOGIC;
Ext_JTAG_UPDATE : out STD_LOGIC;
Ext_JTAG_TDI : out STD_LOGIC;
Ext_JTAG_TDO : in STD_LOGIC
);
attribute C_DATA_SIZE : integer;
attribute C_DATA_SIZE of system_mdm_1_0_MDM : entity is 32;
attribute C_DBG_MEM_ACCESS : integer;
attribute C_DBG_MEM_ACCESS of system_mdm_1_0_MDM : entity is 0;
attribute C_DBG_REG_ACCESS : integer;
attribute C_DBG_REG_ACCESS of system_mdm_1_0_MDM : entity is 0;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of system_mdm_1_0_MDM : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of system_mdm_1_0_MDM : entity is "artix7";
attribute C_INTERCONNECT : integer;
attribute C_INTERCONNECT of system_mdm_1_0_MDM : entity is 2;
attribute C_JTAG_CHAIN : integer;
attribute C_JTAG_CHAIN of system_mdm_1_0_MDM : entity is 2;
attribute C_MB_DBG_PORTS : integer;
attribute C_MB_DBG_PORTS of system_mdm_1_0_MDM : entity is 1;
attribute C_M_AXIS_DATA_WIDTH : integer;
attribute C_M_AXIS_DATA_WIDTH of system_mdm_1_0_MDM : entity is 32;
attribute C_M_AXIS_ID_WIDTH : integer;
attribute C_M_AXIS_ID_WIDTH of system_mdm_1_0_MDM : entity is 7;
attribute C_M_AXI_ADDR_WIDTH : integer;
attribute C_M_AXI_ADDR_WIDTH of system_mdm_1_0_MDM : entity is 32;
attribute C_M_AXI_DATA_WIDTH : integer;
attribute C_M_AXI_DATA_WIDTH of system_mdm_1_0_MDM : entity is 32;
attribute C_M_AXI_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_THREAD_ID_WIDTH of system_mdm_1_0_MDM : entity is 1;
attribute C_S_AXI_ACLK_FREQ_HZ : integer;
attribute C_S_AXI_ACLK_FREQ_HZ of system_mdm_1_0_MDM : entity is 100000000;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of system_mdm_1_0_MDM : entity is 4;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_mdm_1_0_MDM : entity is 32;
attribute C_TRACE_CLK_FREQ_HZ : integer;
attribute C_TRACE_CLK_FREQ_HZ of system_mdm_1_0_MDM : entity is 200000000;
attribute C_TRACE_CLK_OUT_PHASE : integer;
attribute C_TRACE_CLK_OUT_PHASE of system_mdm_1_0_MDM : entity is 90;
attribute C_TRACE_DATA_WIDTH : integer;
attribute C_TRACE_DATA_WIDTH of system_mdm_1_0_MDM : entity is 32;
attribute C_TRACE_OUTPUT : integer;
attribute C_TRACE_OUTPUT of system_mdm_1_0_MDM : entity is 0;
attribute C_USE_BSCAN : integer;
attribute C_USE_BSCAN of system_mdm_1_0_MDM : entity is 0;
attribute C_USE_CONFIG_RESET : integer;
attribute C_USE_CONFIG_RESET of system_mdm_1_0_MDM : entity is 0;
attribute C_USE_CROSS_TRIGGER : integer;
attribute C_USE_CROSS_TRIGGER of system_mdm_1_0_MDM : entity is 0;
attribute C_USE_UART : integer;
attribute C_USE_UART of system_mdm_1_0_MDM : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_mdm_1_0_MDM : entity is "MDM";
end system_mdm_1_0_MDM;
architecture STRUCTURE of system_mdm_1_0_MDM is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^dbg_clk_31\ : STD_LOGIC;
signal \^dbg_shift_0\ : STD_LOGIC;
signal \^dbg_update_31\ : STD_LOGIC;
signal \^ext_jtag_capture\ : STD_LOGIC;
signal \^ext_jtag_shift\ : STD_LOGIC;
signal \^ext_jtag_tdi\ : STD_LOGIC;
signal \JTAG_CONTROL_I/Use_Serial_Unified_Completion.count_reg\ : STD_LOGIC_VECTOR ( 5 to 5 );
signal \JTAG_CONTROL_I/p_20_out__0\ : STD_LOGIC;
signal \JTAG_CONTROL_I/p_43_out__0\ : STD_LOGIC;
signal \JTAG_CONTROL_I/sel\ : STD_LOGIC;
signal MDM_Core_I1_n_0 : STD_LOGIC;
signal MDM_Core_I1_n_19 : STD_LOGIC;
signal \Use_E2.BSCAN_I_n_13\ : STD_LOGIC;
signal \Use_E2.BSCAN_I_n_8\ : STD_LOGIC;
signal drck_i : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_1_in : STD_LOGIC_VECTOR ( 15 to 15 );
signal sel : STD_LOGIC;
signal sel_n_reset : STD_LOGIC;
signal shift_n_reset : STD_LOGIC;
signal tdo : STD_LOGIC;
begin
Dbg_ARADDR_0(14) <= \<const0>\;
Dbg_ARADDR_0(13) <= \<const0>\;
Dbg_ARADDR_0(12) <= \<const0>\;
Dbg_ARADDR_0(11) <= \<const0>\;
Dbg_ARADDR_0(10) <= \<const0>\;
Dbg_ARADDR_0(9) <= \<const0>\;
Dbg_ARADDR_0(8) <= \<const0>\;
Dbg_ARADDR_0(7) <= \<const0>\;
Dbg_ARADDR_0(6) <= \<const0>\;
Dbg_ARADDR_0(5) <= \<const0>\;
Dbg_ARADDR_0(4) <= \<const0>\;
Dbg_ARADDR_0(3) <= \<const0>\;
Dbg_ARADDR_0(2) <= \<const0>\;
Dbg_ARADDR_1(14) <= \<const0>\;
Dbg_ARADDR_1(13) <= \<const0>\;
Dbg_ARADDR_1(12) <= \<const0>\;
Dbg_ARADDR_1(11) <= \<const0>\;
Dbg_ARADDR_1(10) <= \<const0>\;
Dbg_ARADDR_1(9) <= \<const0>\;
Dbg_ARADDR_1(8) <= \<const0>\;
Dbg_ARADDR_1(7) <= \<const0>\;
Dbg_ARADDR_1(6) <= \<const0>\;
Dbg_ARADDR_1(5) <= \<const0>\;
Dbg_ARADDR_1(4) <= \<const0>\;
Dbg_ARADDR_1(3) <= \<const0>\;
Dbg_ARADDR_1(2) <= \<const0>\;
Dbg_ARADDR_10(14) <= \<const0>\;
Dbg_ARADDR_10(13) <= \<const0>\;
Dbg_ARADDR_10(12) <= \<const0>\;
Dbg_ARADDR_10(11) <= \<const0>\;
Dbg_ARADDR_10(10) <= \<const0>\;
Dbg_ARADDR_10(9) <= \<const0>\;
Dbg_ARADDR_10(8) <= \<const0>\;
Dbg_ARADDR_10(7) <= \<const0>\;
Dbg_ARADDR_10(6) <= \<const0>\;
Dbg_ARADDR_10(5) <= \<const0>\;
Dbg_ARADDR_10(4) <= \<const0>\;
Dbg_ARADDR_10(3) <= \<const0>\;
Dbg_ARADDR_10(2) <= \<const0>\;
Dbg_ARADDR_11(14) <= \<const0>\;
Dbg_ARADDR_11(13) <= \<const0>\;
Dbg_ARADDR_11(12) <= \<const0>\;
Dbg_ARADDR_11(11) <= \<const0>\;
Dbg_ARADDR_11(10) <= \<const0>\;
Dbg_ARADDR_11(9) <= \<const0>\;
Dbg_ARADDR_11(8) <= \<const0>\;
Dbg_ARADDR_11(7) <= \<const0>\;
Dbg_ARADDR_11(6) <= \<const0>\;
Dbg_ARADDR_11(5) <= \<const0>\;
Dbg_ARADDR_11(4) <= \<const0>\;
Dbg_ARADDR_11(3) <= \<const0>\;
Dbg_ARADDR_11(2) <= \<const0>\;
Dbg_ARADDR_12(14) <= \<const0>\;
Dbg_ARADDR_12(13) <= \<const0>\;
Dbg_ARADDR_12(12) <= \<const0>\;
Dbg_ARADDR_12(11) <= \<const0>\;
Dbg_ARADDR_12(10) <= \<const0>\;
Dbg_ARADDR_12(9) <= \<const0>\;
Dbg_ARADDR_12(8) <= \<const0>\;
Dbg_ARADDR_12(7) <= \<const0>\;
Dbg_ARADDR_12(6) <= \<const0>\;
Dbg_ARADDR_12(5) <= \<const0>\;
Dbg_ARADDR_12(4) <= \<const0>\;
Dbg_ARADDR_12(3) <= \<const0>\;
Dbg_ARADDR_12(2) <= \<const0>\;
Dbg_ARADDR_13(14) <= \<const0>\;
Dbg_ARADDR_13(13) <= \<const0>\;
Dbg_ARADDR_13(12) <= \<const0>\;
Dbg_ARADDR_13(11) <= \<const0>\;
Dbg_ARADDR_13(10) <= \<const0>\;
Dbg_ARADDR_13(9) <= \<const0>\;
Dbg_ARADDR_13(8) <= \<const0>\;
Dbg_ARADDR_13(7) <= \<const0>\;
Dbg_ARADDR_13(6) <= \<const0>\;
Dbg_ARADDR_13(5) <= \<const0>\;
Dbg_ARADDR_13(4) <= \<const0>\;
Dbg_ARADDR_13(3) <= \<const0>\;
Dbg_ARADDR_13(2) <= \<const0>\;
Dbg_ARADDR_14(14) <= \<const0>\;
Dbg_ARADDR_14(13) <= \<const0>\;
Dbg_ARADDR_14(12) <= \<const0>\;
Dbg_ARADDR_14(11) <= \<const0>\;
Dbg_ARADDR_14(10) <= \<const0>\;
Dbg_ARADDR_14(9) <= \<const0>\;
Dbg_ARADDR_14(8) <= \<const0>\;
Dbg_ARADDR_14(7) <= \<const0>\;
Dbg_ARADDR_14(6) <= \<const0>\;
Dbg_ARADDR_14(5) <= \<const0>\;
Dbg_ARADDR_14(4) <= \<const0>\;
Dbg_ARADDR_14(3) <= \<const0>\;
Dbg_ARADDR_14(2) <= \<const0>\;
Dbg_ARADDR_15(14) <= \<const0>\;
Dbg_ARADDR_15(13) <= \<const0>\;
Dbg_ARADDR_15(12) <= \<const0>\;
Dbg_ARADDR_15(11) <= \<const0>\;
Dbg_ARADDR_15(10) <= \<const0>\;
Dbg_ARADDR_15(9) <= \<const0>\;
Dbg_ARADDR_15(8) <= \<const0>\;
Dbg_ARADDR_15(7) <= \<const0>\;
Dbg_ARADDR_15(6) <= \<const0>\;
Dbg_ARADDR_15(5) <= \<const0>\;
Dbg_ARADDR_15(4) <= \<const0>\;
Dbg_ARADDR_15(3) <= \<const0>\;
Dbg_ARADDR_15(2) <= \<const0>\;
Dbg_ARADDR_16(14) <= \<const0>\;
Dbg_ARADDR_16(13) <= \<const0>\;
Dbg_ARADDR_16(12) <= \<const0>\;
Dbg_ARADDR_16(11) <= \<const0>\;
Dbg_ARADDR_16(10) <= \<const0>\;
Dbg_ARADDR_16(9) <= \<const0>\;
Dbg_ARADDR_16(8) <= \<const0>\;
Dbg_ARADDR_16(7) <= \<const0>\;
Dbg_ARADDR_16(6) <= \<const0>\;
Dbg_ARADDR_16(5) <= \<const0>\;
Dbg_ARADDR_16(4) <= \<const0>\;
Dbg_ARADDR_16(3) <= \<const0>\;
Dbg_ARADDR_16(2) <= \<const0>\;
Dbg_ARADDR_17(14) <= \<const0>\;
Dbg_ARADDR_17(13) <= \<const0>\;
Dbg_ARADDR_17(12) <= \<const0>\;
Dbg_ARADDR_17(11) <= \<const0>\;
Dbg_ARADDR_17(10) <= \<const0>\;
Dbg_ARADDR_17(9) <= \<const0>\;
Dbg_ARADDR_17(8) <= \<const0>\;
Dbg_ARADDR_17(7) <= \<const0>\;
Dbg_ARADDR_17(6) <= \<const0>\;
Dbg_ARADDR_17(5) <= \<const0>\;
Dbg_ARADDR_17(4) <= \<const0>\;
Dbg_ARADDR_17(3) <= \<const0>\;
Dbg_ARADDR_17(2) <= \<const0>\;
Dbg_ARADDR_18(14) <= \<const0>\;
Dbg_ARADDR_18(13) <= \<const0>\;
Dbg_ARADDR_18(12) <= \<const0>\;
Dbg_ARADDR_18(11) <= \<const0>\;
Dbg_ARADDR_18(10) <= \<const0>\;
Dbg_ARADDR_18(9) <= \<const0>\;
Dbg_ARADDR_18(8) <= \<const0>\;
Dbg_ARADDR_18(7) <= \<const0>\;
Dbg_ARADDR_18(6) <= \<const0>\;
Dbg_ARADDR_18(5) <= \<const0>\;
Dbg_ARADDR_18(4) <= \<const0>\;
Dbg_ARADDR_18(3) <= \<const0>\;
Dbg_ARADDR_18(2) <= \<const0>\;
Dbg_ARADDR_19(14) <= \<const0>\;
Dbg_ARADDR_19(13) <= \<const0>\;
Dbg_ARADDR_19(12) <= \<const0>\;
Dbg_ARADDR_19(11) <= \<const0>\;
Dbg_ARADDR_19(10) <= \<const0>\;
Dbg_ARADDR_19(9) <= \<const0>\;
Dbg_ARADDR_19(8) <= \<const0>\;
Dbg_ARADDR_19(7) <= \<const0>\;
Dbg_ARADDR_19(6) <= \<const0>\;
Dbg_ARADDR_19(5) <= \<const0>\;
Dbg_ARADDR_19(4) <= \<const0>\;
Dbg_ARADDR_19(3) <= \<const0>\;
Dbg_ARADDR_19(2) <= \<const0>\;
Dbg_ARADDR_2(14) <= \<const0>\;
Dbg_ARADDR_2(13) <= \<const0>\;
Dbg_ARADDR_2(12) <= \<const0>\;
Dbg_ARADDR_2(11) <= \<const0>\;
Dbg_ARADDR_2(10) <= \<const0>\;
Dbg_ARADDR_2(9) <= \<const0>\;
Dbg_ARADDR_2(8) <= \<const0>\;
Dbg_ARADDR_2(7) <= \<const0>\;
Dbg_ARADDR_2(6) <= \<const0>\;
Dbg_ARADDR_2(5) <= \<const0>\;
Dbg_ARADDR_2(4) <= \<const0>\;
Dbg_ARADDR_2(3) <= \<const0>\;
Dbg_ARADDR_2(2) <= \<const0>\;
Dbg_ARADDR_20(14) <= \<const0>\;
Dbg_ARADDR_20(13) <= \<const0>\;
Dbg_ARADDR_20(12) <= \<const0>\;
Dbg_ARADDR_20(11) <= \<const0>\;
Dbg_ARADDR_20(10) <= \<const0>\;
Dbg_ARADDR_20(9) <= \<const0>\;
Dbg_ARADDR_20(8) <= \<const0>\;
Dbg_ARADDR_20(7) <= \<const0>\;
Dbg_ARADDR_20(6) <= \<const0>\;
Dbg_ARADDR_20(5) <= \<const0>\;
Dbg_ARADDR_20(4) <= \<const0>\;
Dbg_ARADDR_20(3) <= \<const0>\;
Dbg_ARADDR_20(2) <= \<const0>\;
Dbg_ARADDR_21(14) <= \<const0>\;
Dbg_ARADDR_21(13) <= \<const0>\;
Dbg_ARADDR_21(12) <= \<const0>\;
Dbg_ARADDR_21(11) <= \<const0>\;
Dbg_ARADDR_21(10) <= \<const0>\;
Dbg_ARADDR_21(9) <= \<const0>\;
Dbg_ARADDR_21(8) <= \<const0>\;
Dbg_ARADDR_21(7) <= \<const0>\;
Dbg_ARADDR_21(6) <= \<const0>\;
Dbg_ARADDR_21(5) <= \<const0>\;
Dbg_ARADDR_21(4) <= \<const0>\;
Dbg_ARADDR_21(3) <= \<const0>\;
Dbg_ARADDR_21(2) <= \<const0>\;
Dbg_ARADDR_22(14) <= \<const0>\;
Dbg_ARADDR_22(13) <= \<const0>\;
Dbg_ARADDR_22(12) <= \<const0>\;
Dbg_ARADDR_22(11) <= \<const0>\;
Dbg_ARADDR_22(10) <= \<const0>\;
Dbg_ARADDR_22(9) <= \<const0>\;
Dbg_ARADDR_22(8) <= \<const0>\;
Dbg_ARADDR_22(7) <= \<const0>\;
Dbg_ARADDR_22(6) <= \<const0>\;
Dbg_ARADDR_22(5) <= \<const0>\;
Dbg_ARADDR_22(4) <= \<const0>\;
Dbg_ARADDR_22(3) <= \<const0>\;
Dbg_ARADDR_22(2) <= \<const0>\;
Dbg_ARADDR_23(14) <= \<const0>\;
Dbg_ARADDR_23(13) <= \<const0>\;
Dbg_ARADDR_23(12) <= \<const0>\;
Dbg_ARADDR_23(11) <= \<const0>\;
Dbg_ARADDR_23(10) <= \<const0>\;
Dbg_ARADDR_23(9) <= \<const0>\;
Dbg_ARADDR_23(8) <= \<const0>\;
Dbg_ARADDR_23(7) <= \<const0>\;
Dbg_ARADDR_23(6) <= \<const0>\;
Dbg_ARADDR_23(5) <= \<const0>\;
Dbg_ARADDR_23(4) <= \<const0>\;
Dbg_ARADDR_23(3) <= \<const0>\;
Dbg_ARADDR_23(2) <= \<const0>\;
Dbg_ARADDR_24(14) <= \<const0>\;
Dbg_ARADDR_24(13) <= \<const0>\;
Dbg_ARADDR_24(12) <= \<const0>\;
Dbg_ARADDR_24(11) <= \<const0>\;
Dbg_ARADDR_24(10) <= \<const0>\;
Dbg_ARADDR_24(9) <= \<const0>\;
Dbg_ARADDR_24(8) <= \<const0>\;
Dbg_ARADDR_24(7) <= \<const0>\;
Dbg_ARADDR_24(6) <= \<const0>\;
Dbg_ARADDR_24(5) <= \<const0>\;
Dbg_ARADDR_24(4) <= \<const0>\;
Dbg_ARADDR_24(3) <= \<const0>\;
Dbg_ARADDR_24(2) <= \<const0>\;
Dbg_ARADDR_25(14) <= \<const0>\;
Dbg_ARADDR_25(13) <= \<const0>\;
Dbg_ARADDR_25(12) <= \<const0>\;
Dbg_ARADDR_25(11) <= \<const0>\;
Dbg_ARADDR_25(10) <= \<const0>\;
Dbg_ARADDR_25(9) <= \<const0>\;
Dbg_ARADDR_25(8) <= \<const0>\;
Dbg_ARADDR_25(7) <= \<const0>\;
Dbg_ARADDR_25(6) <= \<const0>\;
Dbg_ARADDR_25(5) <= \<const0>\;
Dbg_ARADDR_25(4) <= \<const0>\;
Dbg_ARADDR_25(3) <= \<const0>\;
Dbg_ARADDR_25(2) <= \<const0>\;
Dbg_ARADDR_26(14) <= \<const0>\;
Dbg_ARADDR_26(13) <= \<const0>\;
Dbg_ARADDR_26(12) <= \<const0>\;
Dbg_ARADDR_26(11) <= \<const0>\;
Dbg_ARADDR_26(10) <= \<const0>\;
Dbg_ARADDR_26(9) <= \<const0>\;
Dbg_ARADDR_26(8) <= \<const0>\;
Dbg_ARADDR_26(7) <= \<const0>\;
Dbg_ARADDR_26(6) <= \<const0>\;
Dbg_ARADDR_26(5) <= \<const0>\;
Dbg_ARADDR_26(4) <= \<const0>\;
Dbg_ARADDR_26(3) <= \<const0>\;
Dbg_ARADDR_26(2) <= \<const0>\;
Dbg_ARADDR_27(14) <= \<const0>\;
Dbg_ARADDR_27(13) <= \<const0>\;
Dbg_ARADDR_27(12) <= \<const0>\;
Dbg_ARADDR_27(11) <= \<const0>\;
Dbg_ARADDR_27(10) <= \<const0>\;
Dbg_ARADDR_27(9) <= \<const0>\;
Dbg_ARADDR_27(8) <= \<const0>\;
Dbg_ARADDR_27(7) <= \<const0>\;
Dbg_ARADDR_27(6) <= \<const0>\;
Dbg_ARADDR_27(5) <= \<const0>\;
Dbg_ARADDR_27(4) <= \<const0>\;
Dbg_ARADDR_27(3) <= \<const0>\;
Dbg_ARADDR_27(2) <= \<const0>\;
Dbg_ARADDR_28(14) <= \<const0>\;
Dbg_ARADDR_28(13) <= \<const0>\;
Dbg_ARADDR_28(12) <= \<const0>\;
Dbg_ARADDR_28(11) <= \<const0>\;
Dbg_ARADDR_28(10) <= \<const0>\;
Dbg_ARADDR_28(9) <= \<const0>\;
Dbg_ARADDR_28(8) <= \<const0>\;
Dbg_ARADDR_28(7) <= \<const0>\;
Dbg_ARADDR_28(6) <= \<const0>\;
Dbg_ARADDR_28(5) <= \<const0>\;
Dbg_ARADDR_28(4) <= \<const0>\;
Dbg_ARADDR_28(3) <= \<const0>\;
Dbg_ARADDR_28(2) <= \<const0>\;
Dbg_ARADDR_29(14) <= \<const0>\;
Dbg_ARADDR_29(13) <= \<const0>\;
Dbg_ARADDR_29(12) <= \<const0>\;
Dbg_ARADDR_29(11) <= \<const0>\;
Dbg_ARADDR_29(10) <= \<const0>\;
Dbg_ARADDR_29(9) <= \<const0>\;
Dbg_ARADDR_29(8) <= \<const0>\;
Dbg_ARADDR_29(7) <= \<const0>\;
Dbg_ARADDR_29(6) <= \<const0>\;
Dbg_ARADDR_29(5) <= \<const0>\;
Dbg_ARADDR_29(4) <= \<const0>\;
Dbg_ARADDR_29(3) <= \<const0>\;
Dbg_ARADDR_29(2) <= \<const0>\;
Dbg_ARADDR_3(14) <= \<const0>\;
Dbg_ARADDR_3(13) <= \<const0>\;
Dbg_ARADDR_3(12) <= \<const0>\;
Dbg_ARADDR_3(11) <= \<const0>\;
Dbg_ARADDR_3(10) <= \<const0>\;
Dbg_ARADDR_3(9) <= \<const0>\;
Dbg_ARADDR_3(8) <= \<const0>\;
Dbg_ARADDR_3(7) <= \<const0>\;
Dbg_ARADDR_3(6) <= \<const0>\;
Dbg_ARADDR_3(5) <= \<const0>\;
Dbg_ARADDR_3(4) <= \<const0>\;
Dbg_ARADDR_3(3) <= \<const0>\;
Dbg_ARADDR_3(2) <= \<const0>\;
Dbg_ARADDR_30(14) <= \<const0>\;
Dbg_ARADDR_30(13) <= \<const0>\;
Dbg_ARADDR_30(12) <= \<const0>\;
Dbg_ARADDR_30(11) <= \<const0>\;
Dbg_ARADDR_30(10) <= \<const0>\;
Dbg_ARADDR_30(9) <= \<const0>\;
Dbg_ARADDR_30(8) <= \<const0>\;
Dbg_ARADDR_30(7) <= \<const0>\;
Dbg_ARADDR_30(6) <= \<const0>\;
Dbg_ARADDR_30(5) <= \<const0>\;
Dbg_ARADDR_30(4) <= \<const0>\;
Dbg_ARADDR_30(3) <= \<const0>\;
Dbg_ARADDR_30(2) <= \<const0>\;
Dbg_ARADDR_31(14) <= \<const0>\;
Dbg_ARADDR_31(13) <= \<const0>\;
Dbg_ARADDR_31(12) <= \<const0>\;
Dbg_ARADDR_31(11) <= \<const0>\;
Dbg_ARADDR_31(10) <= \<const0>\;
Dbg_ARADDR_31(9) <= \<const0>\;
Dbg_ARADDR_31(8) <= \<const0>\;
Dbg_ARADDR_31(7) <= \<const0>\;
Dbg_ARADDR_31(6) <= \<const0>\;
Dbg_ARADDR_31(5) <= \<const0>\;
Dbg_ARADDR_31(4) <= \<const0>\;
Dbg_ARADDR_31(3) <= \<const0>\;
Dbg_ARADDR_31(2) <= \<const0>\;
Dbg_ARADDR_4(14) <= \<const0>\;
Dbg_ARADDR_4(13) <= \<const0>\;
Dbg_ARADDR_4(12) <= \<const0>\;
Dbg_ARADDR_4(11) <= \<const0>\;
Dbg_ARADDR_4(10) <= \<const0>\;
Dbg_ARADDR_4(9) <= \<const0>\;
Dbg_ARADDR_4(8) <= \<const0>\;
Dbg_ARADDR_4(7) <= \<const0>\;
Dbg_ARADDR_4(6) <= \<const0>\;
Dbg_ARADDR_4(5) <= \<const0>\;
Dbg_ARADDR_4(4) <= \<const0>\;
Dbg_ARADDR_4(3) <= \<const0>\;
Dbg_ARADDR_4(2) <= \<const0>\;
Dbg_ARADDR_5(14) <= \<const0>\;
Dbg_ARADDR_5(13) <= \<const0>\;
Dbg_ARADDR_5(12) <= \<const0>\;
Dbg_ARADDR_5(11) <= \<const0>\;
Dbg_ARADDR_5(10) <= \<const0>\;
Dbg_ARADDR_5(9) <= \<const0>\;
Dbg_ARADDR_5(8) <= \<const0>\;
Dbg_ARADDR_5(7) <= \<const0>\;
Dbg_ARADDR_5(6) <= \<const0>\;
Dbg_ARADDR_5(5) <= \<const0>\;
Dbg_ARADDR_5(4) <= \<const0>\;
Dbg_ARADDR_5(3) <= \<const0>\;
Dbg_ARADDR_5(2) <= \<const0>\;
Dbg_ARADDR_6(14) <= \<const0>\;
Dbg_ARADDR_6(13) <= \<const0>\;
Dbg_ARADDR_6(12) <= \<const0>\;
Dbg_ARADDR_6(11) <= \<const0>\;
Dbg_ARADDR_6(10) <= \<const0>\;
Dbg_ARADDR_6(9) <= \<const0>\;
Dbg_ARADDR_6(8) <= \<const0>\;
Dbg_ARADDR_6(7) <= \<const0>\;
Dbg_ARADDR_6(6) <= \<const0>\;
Dbg_ARADDR_6(5) <= \<const0>\;
Dbg_ARADDR_6(4) <= \<const0>\;
Dbg_ARADDR_6(3) <= \<const0>\;
Dbg_ARADDR_6(2) <= \<const0>\;
Dbg_ARADDR_7(14) <= \<const0>\;
Dbg_ARADDR_7(13) <= \<const0>\;
Dbg_ARADDR_7(12) <= \<const0>\;
Dbg_ARADDR_7(11) <= \<const0>\;
Dbg_ARADDR_7(10) <= \<const0>\;
Dbg_ARADDR_7(9) <= \<const0>\;
Dbg_ARADDR_7(8) <= \<const0>\;
Dbg_ARADDR_7(7) <= \<const0>\;
Dbg_ARADDR_7(6) <= \<const0>\;
Dbg_ARADDR_7(5) <= \<const0>\;
Dbg_ARADDR_7(4) <= \<const0>\;
Dbg_ARADDR_7(3) <= \<const0>\;
Dbg_ARADDR_7(2) <= \<const0>\;
Dbg_ARADDR_8(14) <= \<const0>\;
Dbg_ARADDR_8(13) <= \<const0>\;
Dbg_ARADDR_8(12) <= \<const0>\;
Dbg_ARADDR_8(11) <= \<const0>\;
Dbg_ARADDR_8(10) <= \<const0>\;
Dbg_ARADDR_8(9) <= \<const0>\;
Dbg_ARADDR_8(8) <= \<const0>\;
Dbg_ARADDR_8(7) <= \<const0>\;
Dbg_ARADDR_8(6) <= \<const0>\;
Dbg_ARADDR_8(5) <= \<const0>\;
Dbg_ARADDR_8(4) <= \<const0>\;
Dbg_ARADDR_8(3) <= \<const0>\;
Dbg_ARADDR_8(2) <= \<const0>\;
Dbg_ARADDR_9(14) <= \<const0>\;
Dbg_ARADDR_9(13) <= \<const0>\;
Dbg_ARADDR_9(12) <= \<const0>\;
Dbg_ARADDR_9(11) <= \<const0>\;
Dbg_ARADDR_9(10) <= \<const0>\;
Dbg_ARADDR_9(9) <= \<const0>\;
Dbg_ARADDR_9(8) <= \<const0>\;
Dbg_ARADDR_9(7) <= \<const0>\;
Dbg_ARADDR_9(6) <= \<const0>\;
Dbg_ARADDR_9(5) <= \<const0>\;
Dbg_ARADDR_9(4) <= \<const0>\;
Dbg_ARADDR_9(3) <= \<const0>\;
Dbg_ARADDR_9(2) <= \<const0>\;
Dbg_ARVALID_0 <= \<const0>\;
Dbg_ARVALID_1 <= \<const0>\;
Dbg_ARVALID_10 <= \<const0>\;
Dbg_ARVALID_11 <= \<const0>\;
Dbg_ARVALID_12 <= \<const0>\;
Dbg_ARVALID_13 <= \<const0>\;
Dbg_ARVALID_14 <= \<const0>\;
Dbg_ARVALID_15 <= \<const0>\;
Dbg_ARVALID_16 <= \<const0>\;
Dbg_ARVALID_17 <= \<const0>\;
Dbg_ARVALID_18 <= \<const0>\;
Dbg_ARVALID_19 <= \<const0>\;
Dbg_ARVALID_2 <= \<const0>\;
Dbg_ARVALID_20 <= \<const0>\;
Dbg_ARVALID_21 <= \<const0>\;
Dbg_ARVALID_22 <= \<const0>\;
Dbg_ARVALID_23 <= \<const0>\;
Dbg_ARVALID_24 <= \<const0>\;
Dbg_ARVALID_25 <= \<const0>\;
Dbg_ARVALID_26 <= \<const0>\;
Dbg_ARVALID_27 <= \<const0>\;
Dbg_ARVALID_28 <= \<const0>\;
Dbg_ARVALID_29 <= \<const0>\;
Dbg_ARVALID_3 <= \<const0>\;
Dbg_ARVALID_30 <= \<const0>\;
Dbg_ARVALID_31 <= \<const0>\;
Dbg_ARVALID_4 <= \<const0>\;
Dbg_ARVALID_5 <= \<const0>\;
Dbg_ARVALID_6 <= \<const0>\;
Dbg_ARVALID_7 <= \<const0>\;
Dbg_ARVALID_8 <= \<const0>\;
Dbg_ARVALID_9 <= \<const0>\;
Dbg_AWADDR_0(14) <= \<const0>\;
Dbg_AWADDR_0(13) <= \<const0>\;
Dbg_AWADDR_0(12) <= \<const0>\;
Dbg_AWADDR_0(11) <= \<const0>\;
Dbg_AWADDR_0(10) <= \<const0>\;
Dbg_AWADDR_0(9) <= \<const0>\;
Dbg_AWADDR_0(8) <= \<const0>\;
Dbg_AWADDR_0(7) <= \<const0>\;
Dbg_AWADDR_0(6) <= \<const0>\;
Dbg_AWADDR_0(5) <= \<const0>\;
Dbg_AWADDR_0(4) <= \<const0>\;
Dbg_AWADDR_0(3) <= \<const0>\;
Dbg_AWADDR_0(2) <= \<const0>\;
Dbg_AWADDR_1(14) <= \<const0>\;
Dbg_AWADDR_1(13) <= \<const0>\;
Dbg_AWADDR_1(12) <= \<const0>\;
Dbg_AWADDR_1(11) <= \<const0>\;
Dbg_AWADDR_1(10) <= \<const0>\;
Dbg_AWADDR_1(9) <= \<const0>\;
Dbg_AWADDR_1(8) <= \<const0>\;
Dbg_AWADDR_1(7) <= \<const0>\;
Dbg_AWADDR_1(6) <= \<const0>\;
Dbg_AWADDR_1(5) <= \<const0>\;
Dbg_AWADDR_1(4) <= \<const0>\;
Dbg_AWADDR_1(3) <= \<const0>\;
Dbg_AWADDR_1(2) <= \<const0>\;
Dbg_AWADDR_10(14) <= \<const0>\;
Dbg_AWADDR_10(13) <= \<const0>\;
Dbg_AWADDR_10(12) <= \<const0>\;
Dbg_AWADDR_10(11) <= \<const0>\;
Dbg_AWADDR_10(10) <= \<const0>\;
Dbg_AWADDR_10(9) <= \<const0>\;
Dbg_AWADDR_10(8) <= \<const0>\;
Dbg_AWADDR_10(7) <= \<const0>\;
Dbg_AWADDR_10(6) <= \<const0>\;
Dbg_AWADDR_10(5) <= \<const0>\;
Dbg_AWADDR_10(4) <= \<const0>\;
Dbg_AWADDR_10(3) <= \<const0>\;
Dbg_AWADDR_10(2) <= \<const0>\;
Dbg_AWADDR_11(14) <= \<const0>\;
Dbg_AWADDR_11(13) <= \<const0>\;
Dbg_AWADDR_11(12) <= \<const0>\;
Dbg_AWADDR_11(11) <= \<const0>\;
Dbg_AWADDR_11(10) <= \<const0>\;
Dbg_AWADDR_11(9) <= \<const0>\;
Dbg_AWADDR_11(8) <= \<const0>\;
Dbg_AWADDR_11(7) <= \<const0>\;
Dbg_AWADDR_11(6) <= \<const0>\;
Dbg_AWADDR_11(5) <= \<const0>\;
Dbg_AWADDR_11(4) <= \<const0>\;
Dbg_AWADDR_11(3) <= \<const0>\;
Dbg_AWADDR_11(2) <= \<const0>\;
Dbg_AWADDR_12(14) <= \<const0>\;
Dbg_AWADDR_12(13) <= \<const0>\;
Dbg_AWADDR_12(12) <= \<const0>\;
Dbg_AWADDR_12(11) <= \<const0>\;
Dbg_AWADDR_12(10) <= \<const0>\;
Dbg_AWADDR_12(9) <= \<const0>\;
Dbg_AWADDR_12(8) <= \<const0>\;
Dbg_AWADDR_12(7) <= \<const0>\;
Dbg_AWADDR_12(6) <= \<const0>\;
Dbg_AWADDR_12(5) <= \<const0>\;
Dbg_AWADDR_12(4) <= \<const0>\;
Dbg_AWADDR_12(3) <= \<const0>\;
Dbg_AWADDR_12(2) <= \<const0>\;
Dbg_AWADDR_13(14) <= \<const0>\;
Dbg_AWADDR_13(13) <= \<const0>\;
Dbg_AWADDR_13(12) <= \<const0>\;
Dbg_AWADDR_13(11) <= \<const0>\;
Dbg_AWADDR_13(10) <= \<const0>\;
Dbg_AWADDR_13(9) <= \<const0>\;
Dbg_AWADDR_13(8) <= \<const0>\;
Dbg_AWADDR_13(7) <= \<const0>\;
Dbg_AWADDR_13(6) <= \<const0>\;
Dbg_AWADDR_13(5) <= \<const0>\;
Dbg_AWADDR_13(4) <= \<const0>\;
Dbg_AWADDR_13(3) <= \<const0>\;
Dbg_AWADDR_13(2) <= \<const0>\;
Dbg_AWADDR_14(14) <= \<const0>\;
Dbg_AWADDR_14(13) <= \<const0>\;
Dbg_AWADDR_14(12) <= \<const0>\;
Dbg_AWADDR_14(11) <= \<const0>\;
Dbg_AWADDR_14(10) <= \<const0>\;
Dbg_AWADDR_14(9) <= \<const0>\;
Dbg_AWADDR_14(8) <= \<const0>\;
Dbg_AWADDR_14(7) <= \<const0>\;
Dbg_AWADDR_14(6) <= \<const0>\;
Dbg_AWADDR_14(5) <= \<const0>\;
Dbg_AWADDR_14(4) <= \<const0>\;
Dbg_AWADDR_14(3) <= \<const0>\;
Dbg_AWADDR_14(2) <= \<const0>\;
Dbg_AWADDR_15(14) <= \<const0>\;
Dbg_AWADDR_15(13) <= \<const0>\;
Dbg_AWADDR_15(12) <= \<const0>\;
Dbg_AWADDR_15(11) <= \<const0>\;
Dbg_AWADDR_15(10) <= \<const0>\;
Dbg_AWADDR_15(9) <= \<const0>\;
Dbg_AWADDR_15(8) <= \<const0>\;
Dbg_AWADDR_15(7) <= \<const0>\;
Dbg_AWADDR_15(6) <= \<const0>\;
Dbg_AWADDR_15(5) <= \<const0>\;
Dbg_AWADDR_15(4) <= \<const0>\;
Dbg_AWADDR_15(3) <= \<const0>\;
Dbg_AWADDR_15(2) <= \<const0>\;
Dbg_AWADDR_16(14) <= \<const0>\;
Dbg_AWADDR_16(13) <= \<const0>\;
Dbg_AWADDR_16(12) <= \<const0>\;
Dbg_AWADDR_16(11) <= \<const0>\;
Dbg_AWADDR_16(10) <= \<const0>\;
Dbg_AWADDR_16(9) <= \<const0>\;
Dbg_AWADDR_16(8) <= \<const0>\;
Dbg_AWADDR_16(7) <= \<const0>\;
Dbg_AWADDR_16(6) <= \<const0>\;
Dbg_AWADDR_16(5) <= \<const0>\;
Dbg_AWADDR_16(4) <= \<const0>\;
Dbg_AWADDR_16(3) <= \<const0>\;
Dbg_AWADDR_16(2) <= \<const0>\;
Dbg_AWADDR_17(14) <= \<const0>\;
Dbg_AWADDR_17(13) <= \<const0>\;
Dbg_AWADDR_17(12) <= \<const0>\;
Dbg_AWADDR_17(11) <= \<const0>\;
Dbg_AWADDR_17(10) <= \<const0>\;
Dbg_AWADDR_17(9) <= \<const0>\;
Dbg_AWADDR_17(8) <= \<const0>\;
Dbg_AWADDR_17(7) <= \<const0>\;
Dbg_AWADDR_17(6) <= \<const0>\;
Dbg_AWADDR_17(5) <= \<const0>\;
Dbg_AWADDR_17(4) <= \<const0>\;
Dbg_AWADDR_17(3) <= \<const0>\;
Dbg_AWADDR_17(2) <= \<const0>\;
Dbg_AWADDR_18(14) <= \<const0>\;
Dbg_AWADDR_18(13) <= \<const0>\;
Dbg_AWADDR_18(12) <= \<const0>\;
Dbg_AWADDR_18(11) <= \<const0>\;
Dbg_AWADDR_18(10) <= \<const0>\;
Dbg_AWADDR_18(9) <= \<const0>\;
Dbg_AWADDR_18(8) <= \<const0>\;
Dbg_AWADDR_18(7) <= \<const0>\;
Dbg_AWADDR_18(6) <= \<const0>\;
Dbg_AWADDR_18(5) <= \<const0>\;
Dbg_AWADDR_18(4) <= \<const0>\;
Dbg_AWADDR_18(3) <= \<const0>\;
Dbg_AWADDR_18(2) <= \<const0>\;
Dbg_AWADDR_19(14) <= \<const0>\;
Dbg_AWADDR_19(13) <= \<const0>\;
Dbg_AWADDR_19(12) <= \<const0>\;
Dbg_AWADDR_19(11) <= \<const0>\;
Dbg_AWADDR_19(10) <= \<const0>\;
Dbg_AWADDR_19(9) <= \<const0>\;
Dbg_AWADDR_19(8) <= \<const0>\;
Dbg_AWADDR_19(7) <= \<const0>\;
Dbg_AWADDR_19(6) <= \<const0>\;
Dbg_AWADDR_19(5) <= \<const0>\;
Dbg_AWADDR_19(4) <= \<const0>\;
Dbg_AWADDR_19(3) <= \<const0>\;
Dbg_AWADDR_19(2) <= \<const0>\;
Dbg_AWADDR_2(14) <= \<const0>\;
Dbg_AWADDR_2(13) <= \<const0>\;
Dbg_AWADDR_2(12) <= \<const0>\;
Dbg_AWADDR_2(11) <= \<const0>\;
Dbg_AWADDR_2(10) <= \<const0>\;
Dbg_AWADDR_2(9) <= \<const0>\;
Dbg_AWADDR_2(8) <= \<const0>\;
Dbg_AWADDR_2(7) <= \<const0>\;
Dbg_AWADDR_2(6) <= \<const0>\;
Dbg_AWADDR_2(5) <= \<const0>\;
Dbg_AWADDR_2(4) <= \<const0>\;
Dbg_AWADDR_2(3) <= \<const0>\;
Dbg_AWADDR_2(2) <= \<const0>\;
Dbg_AWADDR_20(14) <= \<const0>\;
Dbg_AWADDR_20(13) <= \<const0>\;
Dbg_AWADDR_20(12) <= \<const0>\;
Dbg_AWADDR_20(11) <= \<const0>\;
Dbg_AWADDR_20(10) <= \<const0>\;
Dbg_AWADDR_20(9) <= \<const0>\;
Dbg_AWADDR_20(8) <= \<const0>\;
Dbg_AWADDR_20(7) <= \<const0>\;
Dbg_AWADDR_20(6) <= \<const0>\;
Dbg_AWADDR_20(5) <= \<const0>\;
Dbg_AWADDR_20(4) <= \<const0>\;
Dbg_AWADDR_20(3) <= \<const0>\;
Dbg_AWADDR_20(2) <= \<const0>\;
Dbg_AWADDR_21(14) <= \<const0>\;
Dbg_AWADDR_21(13) <= \<const0>\;
Dbg_AWADDR_21(12) <= \<const0>\;
Dbg_AWADDR_21(11) <= \<const0>\;
Dbg_AWADDR_21(10) <= \<const0>\;
Dbg_AWADDR_21(9) <= \<const0>\;
Dbg_AWADDR_21(8) <= \<const0>\;
Dbg_AWADDR_21(7) <= \<const0>\;
Dbg_AWADDR_21(6) <= \<const0>\;
Dbg_AWADDR_21(5) <= \<const0>\;
Dbg_AWADDR_21(4) <= \<const0>\;
Dbg_AWADDR_21(3) <= \<const0>\;
Dbg_AWADDR_21(2) <= \<const0>\;
Dbg_AWADDR_22(14) <= \<const0>\;
Dbg_AWADDR_22(13) <= \<const0>\;
Dbg_AWADDR_22(12) <= \<const0>\;
Dbg_AWADDR_22(11) <= \<const0>\;
Dbg_AWADDR_22(10) <= \<const0>\;
Dbg_AWADDR_22(9) <= \<const0>\;
Dbg_AWADDR_22(8) <= \<const0>\;
Dbg_AWADDR_22(7) <= \<const0>\;
Dbg_AWADDR_22(6) <= \<const0>\;
Dbg_AWADDR_22(5) <= \<const0>\;
Dbg_AWADDR_22(4) <= \<const0>\;
Dbg_AWADDR_22(3) <= \<const0>\;
Dbg_AWADDR_22(2) <= \<const0>\;
Dbg_AWADDR_23(14) <= \<const0>\;
Dbg_AWADDR_23(13) <= \<const0>\;
Dbg_AWADDR_23(12) <= \<const0>\;
Dbg_AWADDR_23(11) <= \<const0>\;
Dbg_AWADDR_23(10) <= \<const0>\;
Dbg_AWADDR_23(9) <= \<const0>\;
Dbg_AWADDR_23(8) <= \<const0>\;
Dbg_AWADDR_23(7) <= \<const0>\;
Dbg_AWADDR_23(6) <= \<const0>\;
Dbg_AWADDR_23(5) <= \<const0>\;
Dbg_AWADDR_23(4) <= \<const0>\;
Dbg_AWADDR_23(3) <= \<const0>\;
Dbg_AWADDR_23(2) <= \<const0>\;
Dbg_AWADDR_24(14) <= \<const0>\;
Dbg_AWADDR_24(13) <= \<const0>\;
Dbg_AWADDR_24(12) <= \<const0>\;
Dbg_AWADDR_24(11) <= \<const0>\;
Dbg_AWADDR_24(10) <= \<const0>\;
Dbg_AWADDR_24(9) <= \<const0>\;
Dbg_AWADDR_24(8) <= \<const0>\;
Dbg_AWADDR_24(7) <= \<const0>\;
Dbg_AWADDR_24(6) <= \<const0>\;
Dbg_AWADDR_24(5) <= \<const0>\;
Dbg_AWADDR_24(4) <= \<const0>\;
Dbg_AWADDR_24(3) <= \<const0>\;
Dbg_AWADDR_24(2) <= \<const0>\;
Dbg_AWADDR_25(14) <= \<const0>\;
Dbg_AWADDR_25(13) <= \<const0>\;
Dbg_AWADDR_25(12) <= \<const0>\;
Dbg_AWADDR_25(11) <= \<const0>\;
Dbg_AWADDR_25(10) <= \<const0>\;
Dbg_AWADDR_25(9) <= \<const0>\;
Dbg_AWADDR_25(8) <= \<const0>\;
Dbg_AWADDR_25(7) <= \<const0>\;
Dbg_AWADDR_25(6) <= \<const0>\;
Dbg_AWADDR_25(5) <= \<const0>\;
Dbg_AWADDR_25(4) <= \<const0>\;
Dbg_AWADDR_25(3) <= \<const0>\;
Dbg_AWADDR_25(2) <= \<const0>\;
Dbg_AWADDR_26(14) <= \<const0>\;
Dbg_AWADDR_26(13) <= \<const0>\;
Dbg_AWADDR_26(12) <= \<const0>\;
Dbg_AWADDR_26(11) <= \<const0>\;
Dbg_AWADDR_26(10) <= \<const0>\;
Dbg_AWADDR_26(9) <= \<const0>\;
Dbg_AWADDR_26(8) <= \<const0>\;
Dbg_AWADDR_26(7) <= \<const0>\;
Dbg_AWADDR_26(6) <= \<const0>\;
Dbg_AWADDR_26(5) <= \<const0>\;
Dbg_AWADDR_26(4) <= \<const0>\;
Dbg_AWADDR_26(3) <= \<const0>\;
Dbg_AWADDR_26(2) <= \<const0>\;
Dbg_AWADDR_27(14) <= \<const0>\;
Dbg_AWADDR_27(13) <= \<const0>\;
Dbg_AWADDR_27(12) <= \<const0>\;
Dbg_AWADDR_27(11) <= \<const0>\;
Dbg_AWADDR_27(10) <= \<const0>\;
Dbg_AWADDR_27(9) <= \<const0>\;
Dbg_AWADDR_27(8) <= \<const0>\;
Dbg_AWADDR_27(7) <= \<const0>\;
Dbg_AWADDR_27(6) <= \<const0>\;
Dbg_AWADDR_27(5) <= \<const0>\;
Dbg_AWADDR_27(4) <= \<const0>\;
Dbg_AWADDR_27(3) <= \<const0>\;
Dbg_AWADDR_27(2) <= \<const0>\;
Dbg_AWADDR_28(14) <= \<const0>\;
Dbg_AWADDR_28(13) <= \<const0>\;
Dbg_AWADDR_28(12) <= \<const0>\;
Dbg_AWADDR_28(11) <= \<const0>\;
Dbg_AWADDR_28(10) <= \<const0>\;
Dbg_AWADDR_28(9) <= \<const0>\;
Dbg_AWADDR_28(8) <= \<const0>\;
Dbg_AWADDR_28(7) <= \<const0>\;
Dbg_AWADDR_28(6) <= \<const0>\;
Dbg_AWADDR_28(5) <= \<const0>\;
Dbg_AWADDR_28(4) <= \<const0>\;
Dbg_AWADDR_28(3) <= \<const0>\;
Dbg_AWADDR_28(2) <= \<const0>\;
Dbg_AWADDR_29(14) <= \<const0>\;
Dbg_AWADDR_29(13) <= \<const0>\;
Dbg_AWADDR_29(12) <= \<const0>\;
Dbg_AWADDR_29(11) <= \<const0>\;
Dbg_AWADDR_29(10) <= \<const0>\;
Dbg_AWADDR_29(9) <= \<const0>\;
Dbg_AWADDR_29(8) <= \<const0>\;
Dbg_AWADDR_29(7) <= \<const0>\;
Dbg_AWADDR_29(6) <= \<const0>\;
Dbg_AWADDR_29(5) <= \<const0>\;
Dbg_AWADDR_29(4) <= \<const0>\;
Dbg_AWADDR_29(3) <= \<const0>\;
Dbg_AWADDR_29(2) <= \<const0>\;
Dbg_AWADDR_3(14) <= \<const0>\;
Dbg_AWADDR_3(13) <= \<const0>\;
Dbg_AWADDR_3(12) <= \<const0>\;
Dbg_AWADDR_3(11) <= \<const0>\;
Dbg_AWADDR_3(10) <= \<const0>\;
Dbg_AWADDR_3(9) <= \<const0>\;
Dbg_AWADDR_3(8) <= \<const0>\;
Dbg_AWADDR_3(7) <= \<const0>\;
Dbg_AWADDR_3(6) <= \<const0>\;
Dbg_AWADDR_3(5) <= \<const0>\;
Dbg_AWADDR_3(4) <= \<const0>\;
Dbg_AWADDR_3(3) <= \<const0>\;
Dbg_AWADDR_3(2) <= \<const0>\;
Dbg_AWADDR_30(14) <= \<const0>\;
Dbg_AWADDR_30(13) <= \<const0>\;
Dbg_AWADDR_30(12) <= \<const0>\;
Dbg_AWADDR_30(11) <= \<const0>\;
Dbg_AWADDR_30(10) <= \<const0>\;
Dbg_AWADDR_30(9) <= \<const0>\;
Dbg_AWADDR_30(8) <= \<const0>\;
Dbg_AWADDR_30(7) <= \<const0>\;
Dbg_AWADDR_30(6) <= \<const0>\;
Dbg_AWADDR_30(5) <= \<const0>\;
Dbg_AWADDR_30(4) <= \<const0>\;
Dbg_AWADDR_30(3) <= \<const0>\;
Dbg_AWADDR_30(2) <= \<const0>\;
Dbg_AWADDR_31(14) <= \<const0>\;
Dbg_AWADDR_31(13) <= \<const0>\;
Dbg_AWADDR_31(12) <= \<const0>\;
Dbg_AWADDR_31(11) <= \<const0>\;
Dbg_AWADDR_31(10) <= \<const0>\;
Dbg_AWADDR_31(9) <= \<const0>\;
Dbg_AWADDR_31(8) <= \<const0>\;
Dbg_AWADDR_31(7) <= \<const0>\;
Dbg_AWADDR_31(6) <= \<const0>\;
Dbg_AWADDR_31(5) <= \<const0>\;
Dbg_AWADDR_31(4) <= \<const0>\;
Dbg_AWADDR_31(3) <= \<const0>\;
Dbg_AWADDR_31(2) <= \<const0>\;
Dbg_AWADDR_4(14) <= \<const0>\;
Dbg_AWADDR_4(13) <= \<const0>\;
Dbg_AWADDR_4(12) <= \<const0>\;
Dbg_AWADDR_4(11) <= \<const0>\;
Dbg_AWADDR_4(10) <= \<const0>\;
Dbg_AWADDR_4(9) <= \<const0>\;
Dbg_AWADDR_4(8) <= \<const0>\;
Dbg_AWADDR_4(7) <= \<const0>\;
Dbg_AWADDR_4(6) <= \<const0>\;
Dbg_AWADDR_4(5) <= \<const0>\;
Dbg_AWADDR_4(4) <= \<const0>\;
Dbg_AWADDR_4(3) <= \<const0>\;
Dbg_AWADDR_4(2) <= \<const0>\;
Dbg_AWADDR_5(14) <= \<const0>\;
Dbg_AWADDR_5(13) <= \<const0>\;
Dbg_AWADDR_5(12) <= \<const0>\;
Dbg_AWADDR_5(11) <= \<const0>\;
Dbg_AWADDR_5(10) <= \<const0>\;
Dbg_AWADDR_5(9) <= \<const0>\;
Dbg_AWADDR_5(8) <= \<const0>\;
Dbg_AWADDR_5(7) <= \<const0>\;
Dbg_AWADDR_5(6) <= \<const0>\;
Dbg_AWADDR_5(5) <= \<const0>\;
Dbg_AWADDR_5(4) <= \<const0>\;
Dbg_AWADDR_5(3) <= \<const0>\;
Dbg_AWADDR_5(2) <= \<const0>\;
Dbg_AWADDR_6(14) <= \<const0>\;
Dbg_AWADDR_6(13) <= \<const0>\;
Dbg_AWADDR_6(12) <= \<const0>\;
Dbg_AWADDR_6(11) <= \<const0>\;
Dbg_AWADDR_6(10) <= \<const0>\;
Dbg_AWADDR_6(9) <= \<const0>\;
Dbg_AWADDR_6(8) <= \<const0>\;
Dbg_AWADDR_6(7) <= \<const0>\;
Dbg_AWADDR_6(6) <= \<const0>\;
Dbg_AWADDR_6(5) <= \<const0>\;
Dbg_AWADDR_6(4) <= \<const0>\;
Dbg_AWADDR_6(3) <= \<const0>\;
Dbg_AWADDR_6(2) <= \<const0>\;
Dbg_AWADDR_7(14) <= \<const0>\;
Dbg_AWADDR_7(13) <= \<const0>\;
Dbg_AWADDR_7(12) <= \<const0>\;
Dbg_AWADDR_7(11) <= \<const0>\;
Dbg_AWADDR_7(10) <= \<const0>\;
Dbg_AWADDR_7(9) <= \<const0>\;
Dbg_AWADDR_7(8) <= \<const0>\;
Dbg_AWADDR_7(7) <= \<const0>\;
Dbg_AWADDR_7(6) <= \<const0>\;
Dbg_AWADDR_7(5) <= \<const0>\;
Dbg_AWADDR_7(4) <= \<const0>\;
Dbg_AWADDR_7(3) <= \<const0>\;
Dbg_AWADDR_7(2) <= \<const0>\;
Dbg_AWADDR_8(14) <= \<const0>\;
Dbg_AWADDR_8(13) <= \<const0>\;
Dbg_AWADDR_8(12) <= \<const0>\;
Dbg_AWADDR_8(11) <= \<const0>\;
Dbg_AWADDR_8(10) <= \<const0>\;
Dbg_AWADDR_8(9) <= \<const0>\;
Dbg_AWADDR_8(8) <= \<const0>\;
Dbg_AWADDR_8(7) <= \<const0>\;
Dbg_AWADDR_8(6) <= \<const0>\;
Dbg_AWADDR_8(5) <= \<const0>\;
Dbg_AWADDR_8(4) <= \<const0>\;
Dbg_AWADDR_8(3) <= \<const0>\;
Dbg_AWADDR_8(2) <= \<const0>\;
Dbg_AWADDR_9(14) <= \<const0>\;
Dbg_AWADDR_9(13) <= \<const0>\;
Dbg_AWADDR_9(12) <= \<const0>\;
Dbg_AWADDR_9(11) <= \<const0>\;
Dbg_AWADDR_9(10) <= \<const0>\;
Dbg_AWADDR_9(9) <= \<const0>\;
Dbg_AWADDR_9(8) <= \<const0>\;
Dbg_AWADDR_9(7) <= \<const0>\;
Dbg_AWADDR_9(6) <= \<const0>\;
Dbg_AWADDR_9(5) <= \<const0>\;
Dbg_AWADDR_9(4) <= \<const0>\;
Dbg_AWADDR_9(3) <= \<const0>\;
Dbg_AWADDR_9(2) <= \<const0>\;
Dbg_AWVALID_0 <= \<const0>\;
Dbg_AWVALID_1 <= \<const0>\;
Dbg_AWVALID_10 <= \<const0>\;
Dbg_AWVALID_11 <= \<const0>\;
Dbg_AWVALID_12 <= \<const0>\;
Dbg_AWVALID_13 <= \<const0>\;
Dbg_AWVALID_14 <= \<const0>\;
Dbg_AWVALID_15 <= \<const0>\;
Dbg_AWVALID_16 <= \<const0>\;
Dbg_AWVALID_17 <= \<const0>\;
Dbg_AWVALID_18 <= \<const0>\;
Dbg_AWVALID_19 <= \<const0>\;
Dbg_AWVALID_2 <= \<const0>\;
Dbg_AWVALID_20 <= \<const0>\;
Dbg_AWVALID_21 <= \<const0>\;
Dbg_AWVALID_22 <= \<const0>\;
Dbg_AWVALID_23 <= \<const0>\;
Dbg_AWVALID_24 <= \<const0>\;
Dbg_AWVALID_25 <= \<const0>\;
Dbg_AWVALID_26 <= \<const0>\;
Dbg_AWVALID_27 <= \<const0>\;
Dbg_AWVALID_28 <= \<const0>\;
Dbg_AWVALID_29 <= \<const0>\;
Dbg_AWVALID_3 <= \<const0>\;
Dbg_AWVALID_30 <= \<const0>\;
Dbg_AWVALID_31 <= \<const0>\;
Dbg_AWVALID_4 <= \<const0>\;
Dbg_AWVALID_5 <= \<const0>\;
Dbg_AWVALID_6 <= \<const0>\;
Dbg_AWVALID_7 <= \<const0>\;
Dbg_AWVALID_8 <= \<const0>\;
Dbg_AWVALID_9 <= \<const0>\;
Dbg_BREADY_0 <= \<const0>\;
Dbg_BREADY_1 <= \<const0>\;
Dbg_BREADY_10 <= \<const0>\;
Dbg_BREADY_11 <= \<const0>\;
Dbg_BREADY_12 <= \<const0>\;
Dbg_BREADY_13 <= \<const0>\;
Dbg_BREADY_14 <= \<const0>\;
Dbg_BREADY_15 <= \<const0>\;
Dbg_BREADY_16 <= \<const0>\;
Dbg_BREADY_17 <= \<const0>\;
Dbg_BREADY_18 <= \<const0>\;
Dbg_BREADY_19 <= \<const0>\;
Dbg_BREADY_2 <= \<const0>\;
Dbg_BREADY_20 <= \<const0>\;
Dbg_BREADY_21 <= \<const0>\;
Dbg_BREADY_22 <= \<const0>\;
Dbg_BREADY_23 <= \<const0>\;
Dbg_BREADY_24 <= \<const0>\;
Dbg_BREADY_25 <= \<const0>\;
Dbg_BREADY_26 <= \<const0>\;
Dbg_BREADY_27 <= \<const0>\;
Dbg_BREADY_28 <= \<const0>\;
Dbg_BREADY_29 <= \<const0>\;
Dbg_BREADY_3 <= \<const0>\;
Dbg_BREADY_30 <= \<const0>\;
Dbg_BREADY_31 <= \<const0>\;
Dbg_BREADY_4 <= \<const0>\;
Dbg_BREADY_5 <= \<const0>\;
Dbg_BREADY_6 <= \<const0>\;
Dbg_BREADY_7 <= \<const0>\;
Dbg_BREADY_8 <= \<const0>\;
Dbg_BREADY_9 <= \<const0>\;
Dbg_Capture_0 <= \^ext_jtag_capture\;
Dbg_Capture_1 <= \^ext_jtag_capture\;
Dbg_Capture_10 <= \^ext_jtag_capture\;
Dbg_Capture_11 <= \^ext_jtag_capture\;
Dbg_Capture_12 <= \^ext_jtag_capture\;
Dbg_Capture_13 <= \^ext_jtag_capture\;
Dbg_Capture_14 <= \^ext_jtag_capture\;
Dbg_Capture_15 <= \^ext_jtag_capture\;
Dbg_Capture_16 <= \^ext_jtag_capture\;
Dbg_Capture_17 <= \^ext_jtag_capture\;
Dbg_Capture_18 <= \^ext_jtag_capture\;
Dbg_Capture_19 <= \^ext_jtag_capture\;
Dbg_Capture_2 <= \^ext_jtag_capture\;
Dbg_Capture_20 <= \^ext_jtag_capture\;
Dbg_Capture_21 <= \^ext_jtag_capture\;
Dbg_Capture_22 <= \^ext_jtag_capture\;
Dbg_Capture_23 <= \^ext_jtag_capture\;
Dbg_Capture_24 <= \^ext_jtag_capture\;
Dbg_Capture_25 <= \^ext_jtag_capture\;
Dbg_Capture_26 <= \^ext_jtag_capture\;
Dbg_Capture_27 <= \^ext_jtag_capture\;
Dbg_Capture_28 <= \^ext_jtag_capture\;
Dbg_Capture_29 <= \^ext_jtag_capture\;
Dbg_Capture_3 <= \^ext_jtag_capture\;
Dbg_Capture_30 <= \^ext_jtag_capture\;
Dbg_Capture_31 <= \^ext_jtag_capture\;
Dbg_Capture_4 <= \^ext_jtag_capture\;
Dbg_Capture_5 <= \^ext_jtag_capture\;
Dbg_Capture_6 <= \^ext_jtag_capture\;
Dbg_Capture_7 <= \^ext_jtag_capture\;
Dbg_Capture_8 <= \^ext_jtag_capture\;
Dbg_Capture_9 <= \^ext_jtag_capture\;
Dbg_Clk_0 <= \^dbg_clk_31\;
Dbg_Clk_1 <= \^dbg_clk_31\;
Dbg_Clk_10 <= \^dbg_clk_31\;
Dbg_Clk_11 <= \^dbg_clk_31\;
Dbg_Clk_12 <= \^dbg_clk_31\;
Dbg_Clk_13 <= \^dbg_clk_31\;
Dbg_Clk_14 <= \^dbg_clk_31\;
Dbg_Clk_15 <= \^dbg_clk_31\;
Dbg_Clk_16 <= \^dbg_clk_31\;
Dbg_Clk_17 <= \^dbg_clk_31\;
Dbg_Clk_18 <= \^dbg_clk_31\;
Dbg_Clk_19 <= \^dbg_clk_31\;
Dbg_Clk_2 <= \^dbg_clk_31\;
Dbg_Clk_20 <= \^dbg_clk_31\;
Dbg_Clk_21 <= \^dbg_clk_31\;
Dbg_Clk_22 <= \^dbg_clk_31\;
Dbg_Clk_23 <= \^dbg_clk_31\;
Dbg_Clk_24 <= \^dbg_clk_31\;
Dbg_Clk_25 <= \^dbg_clk_31\;
Dbg_Clk_26 <= \^dbg_clk_31\;
Dbg_Clk_27 <= \^dbg_clk_31\;
Dbg_Clk_28 <= \^dbg_clk_31\;
Dbg_Clk_29 <= \^dbg_clk_31\;
Dbg_Clk_3 <= \^dbg_clk_31\;
Dbg_Clk_30 <= \^dbg_clk_31\;
Dbg_Clk_31 <= \^dbg_clk_31\;
Dbg_Clk_4 <= \^dbg_clk_31\;
Dbg_Clk_5 <= \^dbg_clk_31\;
Dbg_Clk_6 <= \^dbg_clk_31\;
Dbg_Clk_7 <= \^dbg_clk_31\;
Dbg_Clk_8 <= \^dbg_clk_31\;
Dbg_Clk_9 <= \^dbg_clk_31\;
Dbg_Disable_1 <= \<const1>\;
Dbg_Disable_10 <= \<const1>\;
Dbg_Disable_11 <= \<const1>\;
Dbg_Disable_12 <= \<const1>\;
Dbg_Disable_13 <= \<const1>\;
Dbg_Disable_14 <= \<const1>\;
Dbg_Disable_15 <= \<const1>\;
Dbg_Disable_16 <= \<const1>\;
Dbg_Disable_17 <= \<const1>\;
Dbg_Disable_18 <= \<const1>\;
Dbg_Disable_19 <= \<const1>\;
Dbg_Disable_2 <= \<const1>\;
Dbg_Disable_20 <= \<const1>\;
Dbg_Disable_21 <= \<const1>\;
Dbg_Disable_22 <= \<const1>\;
Dbg_Disable_23 <= \<const1>\;
Dbg_Disable_24 <= \<const1>\;
Dbg_Disable_25 <= \<const1>\;
Dbg_Disable_26 <= \<const1>\;
Dbg_Disable_27 <= \<const1>\;
Dbg_Disable_28 <= \<const1>\;
Dbg_Disable_29 <= \<const1>\;
Dbg_Disable_3 <= \<const1>\;
Dbg_Disable_30 <= \<const1>\;
Dbg_Disable_31 <= \<const1>\;
Dbg_Disable_4 <= \<const1>\;
Dbg_Disable_5 <= \<const1>\;
Dbg_Disable_6 <= \<const1>\;
Dbg_Disable_7 <= \<const1>\;
Dbg_Disable_8 <= \<const1>\;
Dbg_Disable_9 <= \<const1>\;
Dbg_RREADY_0 <= \<const0>\;
Dbg_RREADY_1 <= \<const0>\;
Dbg_RREADY_10 <= \<const0>\;
Dbg_RREADY_11 <= \<const0>\;
Dbg_RREADY_12 <= \<const0>\;
Dbg_RREADY_13 <= \<const0>\;
Dbg_RREADY_14 <= \<const0>\;
Dbg_RREADY_15 <= \<const0>\;
Dbg_RREADY_16 <= \<const0>\;
Dbg_RREADY_17 <= \<const0>\;
Dbg_RREADY_18 <= \<const0>\;
Dbg_RREADY_19 <= \<const0>\;
Dbg_RREADY_2 <= \<const0>\;
Dbg_RREADY_20 <= \<const0>\;
Dbg_RREADY_21 <= \<const0>\;
Dbg_RREADY_22 <= \<const0>\;
Dbg_RREADY_23 <= \<const0>\;
Dbg_RREADY_24 <= \<const0>\;
Dbg_RREADY_25 <= \<const0>\;
Dbg_RREADY_26 <= \<const0>\;
Dbg_RREADY_27 <= \<const0>\;
Dbg_RREADY_28 <= \<const0>\;
Dbg_RREADY_29 <= \<const0>\;
Dbg_RREADY_3 <= \<const0>\;
Dbg_RREADY_30 <= \<const0>\;
Dbg_RREADY_31 <= \<const0>\;
Dbg_RREADY_4 <= \<const0>\;
Dbg_RREADY_5 <= \<const0>\;
Dbg_RREADY_6 <= \<const0>\;
Dbg_RREADY_7 <= \<const0>\;
Dbg_RREADY_8 <= \<const0>\;
Dbg_RREADY_9 <= \<const0>\;
Dbg_Reg_En_1(0) <= \<const0>\;
Dbg_Reg_En_1(1) <= \<const0>\;
Dbg_Reg_En_1(2) <= \<const0>\;
Dbg_Reg_En_1(3) <= \<const0>\;
Dbg_Reg_En_1(4) <= \<const0>\;
Dbg_Reg_En_1(5) <= \<const0>\;
Dbg_Reg_En_1(6) <= \<const0>\;
Dbg_Reg_En_1(7) <= \<const0>\;
Dbg_Reg_En_10(0) <= \<const0>\;
Dbg_Reg_En_10(1) <= \<const0>\;
Dbg_Reg_En_10(2) <= \<const0>\;
Dbg_Reg_En_10(3) <= \<const0>\;
Dbg_Reg_En_10(4) <= \<const0>\;
Dbg_Reg_En_10(5) <= \<const0>\;
Dbg_Reg_En_10(6) <= \<const0>\;
Dbg_Reg_En_10(7) <= \<const0>\;
Dbg_Reg_En_11(0) <= \<const0>\;
Dbg_Reg_En_11(1) <= \<const0>\;
Dbg_Reg_En_11(2) <= \<const0>\;
Dbg_Reg_En_11(3) <= \<const0>\;
Dbg_Reg_En_11(4) <= \<const0>\;
Dbg_Reg_En_11(5) <= \<const0>\;
Dbg_Reg_En_11(6) <= \<const0>\;
Dbg_Reg_En_11(7) <= \<const0>\;
Dbg_Reg_En_12(0) <= \<const0>\;
Dbg_Reg_En_12(1) <= \<const0>\;
Dbg_Reg_En_12(2) <= \<const0>\;
Dbg_Reg_En_12(3) <= \<const0>\;
Dbg_Reg_En_12(4) <= \<const0>\;
Dbg_Reg_En_12(5) <= \<const0>\;
Dbg_Reg_En_12(6) <= \<const0>\;
Dbg_Reg_En_12(7) <= \<const0>\;
Dbg_Reg_En_13(0) <= \<const0>\;
Dbg_Reg_En_13(1) <= \<const0>\;
Dbg_Reg_En_13(2) <= \<const0>\;
Dbg_Reg_En_13(3) <= \<const0>\;
Dbg_Reg_En_13(4) <= \<const0>\;
Dbg_Reg_En_13(5) <= \<const0>\;
Dbg_Reg_En_13(6) <= \<const0>\;
Dbg_Reg_En_13(7) <= \<const0>\;
Dbg_Reg_En_14(0) <= \<const0>\;
Dbg_Reg_En_14(1) <= \<const0>\;
Dbg_Reg_En_14(2) <= \<const0>\;
Dbg_Reg_En_14(3) <= \<const0>\;
Dbg_Reg_En_14(4) <= \<const0>\;
Dbg_Reg_En_14(5) <= \<const0>\;
Dbg_Reg_En_14(6) <= \<const0>\;
Dbg_Reg_En_14(7) <= \<const0>\;
Dbg_Reg_En_15(0) <= \<const0>\;
Dbg_Reg_En_15(1) <= \<const0>\;
Dbg_Reg_En_15(2) <= \<const0>\;
Dbg_Reg_En_15(3) <= \<const0>\;
Dbg_Reg_En_15(4) <= \<const0>\;
Dbg_Reg_En_15(5) <= \<const0>\;
Dbg_Reg_En_15(6) <= \<const0>\;
Dbg_Reg_En_15(7) <= \<const0>\;
Dbg_Reg_En_16(0) <= \<const0>\;
Dbg_Reg_En_16(1) <= \<const0>\;
Dbg_Reg_En_16(2) <= \<const0>\;
Dbg_Reg_En_16(3) <= \<const0>\;
Dbg_Reg_En_16(4) <= \<const0>\;
Dbg_Reg_En_16(5) <= \<const0>\;
Dbg_Reg_En_16(6) <= \<const0>\;
Dbg_Reg_En_16(7) <= \<const0>\;
Dbg_Reg_En_17(0) <= \<const0>\;
Dbg_Reg_En_17(1) <= \<const0>\;
Dbg_Reg_En_17(2) <= \<const0>\;
Dbg_Reg_En_17(3) <= \<const0>\;
Dbg_Reg_En_17(4) <= \<const0>\;
Dbg_Reg_En_17(5) <= \<const0>\;
Dbg_Reg_En_17(6) <= \<const0>\;
Dbg_Reg_En_17(7) <= \<const0>\;
Dbg_Reg_En_18(0) <= \<const0>\;
Dbg_Reg_En_18(1) <= \<const0>\;
Dbg_Reg_En_18(2) <= \<const0>\;
Dbg_Reg_En_18(3) <= \<const0>\;
Dbg_Reg_En_18(4) <= \<const0>\;
Dbg_Reg_En_18(5) <= \<const0>\;
Dbg_Reg_En_18(6) <= \<const0>\;
Dbg_Reg_En_18(7) <= \<const0>\;
Dbg_Reg_En_19(0) <= \<const0>\;
Dbg_Reg_En_19(1) <= \<const0>\;
Dbg_Reg_En_19(2) <= \<const0>\;
Dbg_Reg_En_19(3) <= \<const0>\;
Dbg_Reg_En_19(4) <= \<const0>\;
Dbg_Reg_En_19(5) <= \<const0>\;
Dbg_Reg_En_19(6) <= \<const0>\;
Dbg_Reg_En_19(7) <= \<const0>\;
Dbg_Reg_En_2(0) <= \<const0>\;
Dbg_Reg_En_2(1) <= \<const0>\;
Dbg_Reg_En_2(2) <= \<const0>\;
Dbg_Reg_En_2(3) <= \<const0>\;
Dbg_Reg_En_2(4) <= \<const0>\;
Dbg_Reg_En_2(5) <= \<const0>\;
Dbg_Reg_En_2(6) <= \<const0>\;
Dbg_Reg_En_2(7) <= \<const0>\;
Dbg_Reg_En_20(0) <= \<const0>\;
Dbg_Reg_En_20(1) <= \<const0>\;
Dbg_Reg_En_20(2) <= \<const0>\;
Dbg_Reg_En_20(3) <= \<const0>\;
Dbg_Reg_En_20(4) <= \<const0>\;
Dbg_Reg_En_20(5) <= \<const0>\;
Dbg_Reg_En_20(6) <= \<const0>\;
Dbg_Reg_En_20(7) <= \<const0>\;
Dbg_Reg_En_21(0) <= \<const0>\;
Dbg_Reg_En_21(1) <= \<const0>\;
Dbg_Reg_En_21(2) <= \<const0>\;
Dbg_Reg_En_21(3) <= \<const0>\;
Dbg_Reg_En_21(4) <= \<const0>\;
Dbg_Reg_En_21(5) <= \<const0>\;
Dbg_Reg_En_21(6) <= \<const0>\;
Dbg_Reg_En_21(7) <= \<const0>\;
Dbg_Reg_En_22(0) <= \<const0>\;
Dbg_Reg_En_22(1) <= \<const0>\;
Dbg_Reg_En_22(2) <= \<const0>\;
Dbg_Reg_En_22(3) <= \<const0>\;
Dbg_Reg_En_22(4) <= \<const0>\;
Dbg_Reg_En_22(5) <= \<const0>\;
Dbg_Reg_En_22(6) <= \<const0>\;
Dbg_Reg_En_22(7) <= \<const0>\;
Dbg_Reg_En_23(0) <= \<const0>\;
Dbg_Reg_En_23(1) <= \<const0>\;
Dbg_Reg_En_23(2) <= \<const0>\;
Dbg_Reg_En_23(3) <= \<const0>\;
Dbg_Reg_En_23(4) <= \<const0>\;
Dbg_Reg_En_23(5) <= \<const0>\;
Dbg_Reg_En_23(6) <= \<const0>\;
Dbg_Reg_En_23(7) <= \<const0>\;
Dbg_Reg_En_24(0) <= \<const0>\;
Dbg_Reg_En_24(1) <= \<const0>\;
Dbg_Reg_En_24(2) <= \<const0>\;
Dbg_Reg_En_24(3) <= \<const0>\;
Dbg_Reg_En_24(4) <= \<const0>\;
Dbg_Reg_En_24(5) <= \<const0>\;
Dbg_Reg_En_24(6) <= \<const0>\;
Dbg_Reg_En_24(7) <= \<const0>\;
Dbg_Reg_En_25(0) <= \<const0>\;
Dbg_Reg_En_25(1) <= \<const0>\;
Dbg_Reg_En_25(2) <= \<const0>\;
Dbg_Reg_En_25(3) <= \<const0>\;
Dbg_Reg_En_25(4) <= \<const0>\;
Dbg_Reg_En_25(5) <= \<const0>\;
Dbg_Reg_En_25(6) <= \<const0>\;
Dbg_Reg_En_25(7) <= \<const0>\;
Dbg_Reg_En_26(0) <= \<const0>\;
Dbg_Reg_En_26(1) <= \<const0>\;
Dbg_Reg_En_26(2) <= \<const0>\;
Dbg_Reg_En_26(3) <= \<const0>\;
Dbg_Reg_En_26(4) <= \<const0>\;
Dbg_Reg_En_26(5) <= \<const0>\;
Dbg_Reg_En_26(6) <= \<const0>\;
Dbg_Reg_En_26(7) <= \<const0>\;
Dbg_Reg_En_27(0) <= \<const0>\;
Dbg_Reg_En_27(1) <= \<const0>\;
Dbg_Reg_En_27(2) <= \<const0>\;
Dbg_Reg_En_27(3) <= \<const0>\;
Dbg_Reg_En_27(4) <= \<const0>\;
Dbg_Reg_En_27(5) <= \<const0>\;
Dbg_Reg_En_27(6) <= \<const0>\;
Dbg_Reg_En_27(7) <= \<const0>\;
Dbg_Reg_En_28(0) <= \<const0>\;
Dbg_Reg_En_28(1) <= \<const0>\;
Dbg_Reg_En_28(2) <= \<const0>\;
Dbg_Reg_En_28(3) <= \<const0>\;
Dbg_Reg_En_28(4) <= \<const0>\;
Dbg_Reg_En_28(5) <= \<const0>\;
Dbg_Reg_En_28(6) <= \<const0>\;
Dbg_Reg_En_28(7) <= \<const0>\;
Dbg_Reg_En_29(0) <= \<const0>\;
Dbg_Reg_En_29(1) <= \<const0>\;
Dbg_Reg_En_29(2) <= \<const0>\;
Dbg_Reg_En_29(3) <= \<const0>\;
Dbg_Reg_En_29(4) <= \<const0>\;
Dbg_Reg_En_29(5) <= \<const0>\;
Dbg_Reg_En_29(6) <= \<const0>\;
Dbg_Reg_En_29(7) <= \<const0>\;
Dbg_Reg_En_3(0) <= \<const0>\;
Dbg_Reg_En_3(1) <= \<const0>\;
Dbg_Reg_En_3(2) <= \<const0>\;
Dbg_Reg_En_3(3) <= \<const0>\;
Dbg_Reg_En_3(4) <= \<const0>\;
Dbg_Reg_En_3(5) <= \<const0>\;
Dbg_Reg_En_3(6) <= \<const0>\;
Dbg_Reg_En_3(7) <= \<const0>\;
Dbg_Reg_En_30(0) <= \<const0>\;
Dbg_Reg_En_30(1) <= \<const0>\;
Dbg_Reg_En_30(2) <= \<const0>\;
Dbg_Reg_En_30(3) <= \<const0>\;
Dbg_Reg_En_30(4) <= \<const0>\;
Dbg_Reg_En_30(5) <= \<const0>\;
Dbg_Reg_En_30(6) <= \<const0>\;
Dbg_Reg_En_30(7) <= \<const0>\;
Dbg_Reg_En_31(0) <= \<const0>\;
Dbg_Reg_En_31(1) <= \<const0>\;
Dbg_Reg_En_31(2) <= \<const0>\;
Dbg_Reg_En_31(3) <= \<const0>\;
Dbg_Reg_En_31(4) <= \<const0>\;
Dbg_Reg_En_31(5) <= \<const0>\;
Dbg_Reg_En_31(6) <= \<const0>\;
Dbg_Reg_En_31(7) <= \<const0>\;
Dbg_Reg_En_4(0) <= \<const0>\;
Dbg_Reg_En_4(1) <= \<const0>\;
Dbg_Reg_En_4(2) <= \<const0>\;
Dbg_Reg_En_4(3) <= \<const0>\;
Dbg_Reg_En_4(4) <= \<const0>\;
Dbg_Reg_En_4(5) <= \<const0>\;
Dbg_Reg_En_4(6) <= \<const0>\;
Dbg_Reg_En_4(7) <= \<const0>\;
Dbg_Reg_En_5(0) <= \<const0>\;
Dbg_Reg_En_5(1) <= \<const0>\;
Dbg_Reg_En_5(2) <= \<const0>\;
Dbg_Reg_En_5(3) <= \<const0>\;
Dbg_Reg_En_5(4) <= \<const0>\;
Dbg_Reg_En_5(5) <= \<const0>\;
Dbg_Reg_En_5(6) <= \<const0>\;
Dbg_Reg_En_5(7) <= \<const0>\;
Dbg_Reg_En_6(0) <= \<const0>\;
Dbg_Reg_En_6(1) <= \<const0>\;
Dbg_Reg_En_6(2) <= \<const0>\;
Dbg_Reg_En_6(3) <= \<const0>\;
Dbg_Reg_En_6(4) <= \<const0>\;
Dbg_Reg_En_6(5) <= \<const0>\;
Dbg_Reg_En_6(6) <= \<const0>\;
Dbg_Reg_En_6(7) <= \<const0>\;
Dbg_Reg_En_7(0) <= \<const0>\;
Dbg_Reg_En_7(1) <= \<const0>\;
Dbg_Reg_En_7(2) <= \<const0>\;
Dbg_Reg_En_7(3) <= \<const0>\;
Dbg_Reg_En_7(4) <= \<const0>\;
Dbg_Reg_En_7(5) <= \<const0>\;
Dbg_Reg_En_7(6) <= \<const0>\;
Dbg_Reg_En_7(7) <= \<const0>\;
Dbg_Reg_En_8(0) <= \<const0>\;
Dbg_Reg_En_8(1) <= \<const0>\;
Dbg_Reg_En_8(2) <= \<const0>\;
Dbg_Reg_En_8(3) <= \<const0>\;
Dbg_Reg_En_8(4) <= \<const0>\;
Dbg_Reg_En_8(5) <= \<const0>\;
Dbg_Reg_En_8(6) <= \<const0>\;
Dbg_Reg_En_8(7) <= \<const0>\;
Dbg_Reg_En_9(0) <= \<const0>\;
Dbg_Reg_En_9(1) <= \<const0>\;
Dbg_Reg_En_9(2) <= \<const0>\;
Dbg_Reg_En_9(3) <= \<const0>\;
Dbg_Reg_En_9(4) <= \<const0>\;
Dbg_Reg_En_9(5) <= \<const0>\;
Dbg_Reg_En_9(6) <= \<const0>\;
Dbg_Reg_En_9(7) <= \<const0>\;
Dbg_Rst_1 <= \<const0>\;
Dbg_Rst_10 <= \<const0>\;
Dbg_Rst_11 <= \<const0>\;
Dbg_Rst_12 <= \<const0>\;
Dbg_Rst_13 <= \<const0>\;
Dbg_Rst_14 <= \<const0>\;
Dbg_Rst_15 <= \<const0>\;
Dbg_Rst_16 <= \<const0>\;
Dbg_Rst_17 <= \<const0>\;
Dbg_Rst_18 <= \<const0>\;
Dbg_Rst_19 <= \<const0>\;
Dbg_Rst_2 <= \<const0>\;
Dbg_Rst_20 <= \<const0>\;
Dbg_Rst_21 <= \<const0>\;
Dbg_Rst_22 <= \<const0>\;
Dbg_Rst_23 <= \<const0>\;
Dbg_Rst_24 <= \<const0>\;
Dbg_Rst_25 <= \<const0>\;
Dbg_Rst_26 <= \<const0>\;
Dbg_Rst_27 <= \<const0>\;
Dbg_Rst_28 <= \<const0>\;
Dbg_Rst_29 <= \<const0>\;
Dbg_Rst_3 <= \<const0>\;
Dbg_Rst_30 <= \<const0>\;
Dbg_Rst_31 <= \<const0>\;
Dbg_Rst_4 <= \<const0>\;
Dbg_Rst_5 <= \<const0>\;
Dbg_Rst_6 <= \<const0>\;
Dbg_Rst_7 <= \<const0>\;
Dbg_Rst_8 <= \<const0>\;
Dbg_Rst_9 <= \<const0>\;
Dbg_Shift_0 <= \^dbg_shift_0\;
Dbg_Shift_1 <= \^dbg_shift_0\;
Dbg_Shift_10 <= \^dbg_shift_0\;
Dbg_Shift_11 <= \^dbg_shift_0\;
Dbg_Shift_12 <= \^dbg_shift_0\;
Dbg_Shift_13 <= \^dbg_shift_0\;
Dbg_Shift_14 <= \^dbg_shift_0\;
Dbg_Shift_15 <= \^dbg_shift_0\;
Dbg_Shift_16 <= \^dbg_shift_0\;
Dbg_Shift_17 <= \^dbg_shift_0\;
Dbg_Shift_18 <= \^dbg_shift_0\;
Dbg_Shift_19 <= \^dbg_shift_0\;
Dbg_Shift_2 <= \^dbg_shift_0\;
Dbg_Shift_20 <= \^dbg_shift_0\;
Dbg_Shift_21 <= \^dbg_shift_0\;
Dbg_Shift_22 <= \^dbg_shift_0\;
Dbg_Shift_23 <= \^dbg_shift_0\;
Dbg_Shift_24 <= \^dbg_shift_0\;
Dbg_Shift_25 <= \^dbg_shift_0\;
Dbg_Shift_26 <= \^dbg_shift_0\;
Dbg_Shift_27 <= \^dbg_shift_0\;
Dbg_Shift_28 <= \^dbg_shift_0\;
Dbg_Shift_29 <= \^dbg_shift_0\;
Dbg_Shift_3 <= \^dbg_shift_0\;
Dbg_Shift_30 <= \^dbg_shift_0\;
Dbg_Shift_31 <= \^dbg_shift_0\;
Dbg_Shift_4 <= \^dbg_shift_0\;
Dbg_Shift_5 <= \^dbg_shift_0\;
Dbg_Shift_6 <= \^dbg_shift_0\;
Dbg_Shift_7 <= \^dbg_shift_0\;
Dbg_Shift_8 <= \^dbg_shift_0\;
Dbg_Shift_9 <= \^dbg_shift_0\;
Dbg_TDI_0 <= \^ext_jtag_tdi\;
Dbg_TDI_1 <= \^ext_jtag_tdi\;
Dbg_TDI_10 <= \^ext_jtag_tdi\;
Dbg_TDI_11 <= \^ext_jtag_tdi\;
Dbg_TDI_12 <= \^ext_jtag_tdi\;
Dbg_TDI_13 <= \^ext_jtag_tdi\;
Dbg_TDI_14 <= \^ext_jtag_tdi\;
Dbg_TDI_15 <= \^ext_jtag_tdi\;
Dbg_TDI_16 <= \^ext_jtag_tdi\;
Dbg_TDI_17 <= \^ext_jtag_tdi\;
Dbg_TDI_18 <= \^ext_jtag_tdi\;
Dbg_TDI_19 <= \^ext_jtag_tdi\;
Dbg_TDI_2 <= \^ext_jtag_tdi\;
Dbg_TDI_20 <= \^ext_jtag_tdi\;
Dbg_TDI_21 <= \^ext_jtag_tdi\;
Dbg_TDI_22 <= \^ext_jtag_tdi\;
Dbg_TDI_23 <= \^ext_jtag_tdi\;
Dbg_TDI_24 <= \^ext_jtag_tdi\;
Dbg_TDI_25 <= \^ext_jtag_tdi\;
Dbg_TDI_26 <= \^ext_jtag_tdi\;
Dbg_TDI_27 <= \^ext_jtag_tdi\;
Dbg_TDI_28 <= \^ext_jtag_tdi\;
Dbg_TDI_29 <= \^ext_jtag_tdi\;
Dbg_TDI_3 <= \^ext_jtag_tdi\;
Dbg_TDI_30 <= \^ext_jtag_tdi\;
Dbg_TDI_31 <= \^ext_jtag_tdi\;
Dbg_TDI_4 <= \^ext_jtag_tdi\;
Dbg_TDI_5 <= \^ext_jtag_tdi\;
Dbg_TDI_6 <= \^ext_jtag_tdi\;
Dbg_TDI_7 <= \^ext_jtag_tdi\;
Dbg_TDI_8 <= \^ext_jtag_tdi\;
Dbg_TDI_9 <= \^ext_jtag_tdi\;
Dbg_TrClk_0 <= \<const0>\;
Dbg_TrClk_1 <= \<const0>\;
Dbg_TrClk_10 <= \<const0>\;
Dbg_TrClk_11 <= \<const0>\;
Dbg_TrClk_12 <= \<const0>\;
Dbg_TrClk_13 <= \<const0>\;
Dbg_TrClk_14 <= \<const0>\;
Dbg_TrClk_15 <= \<const0>\;
Dbg_TrClk_16 <= \<const0>\;
Dbg_TrClk_17 <= \<const0>\;
Dbg_TrClk_18 <= \<const0>\;
Dbg_TrClk_19 <= \<const0>\;
Dbg_TrClk_2 <= \<const0>\;
Dbg_TrClk_20 <= \<const0>\;
Dbg_TrClk_21 <= \<const0>\;
Dbg_TrClk_22 <= \<const0>\;
Dbg_TrClk_23 <= \<const0>\;
Dbg_TrClk_24 <= \<const0>\;
Dbg_TrClk_25 <= \<const0>\;
Dbg_TrClk_26 <= \<const0>\;
Dbg_TrClk_27 <= \<const0>\;
Dbg_TrClk_28 <= \<const0>\;
Dbg_TrClk_29 <= \<const0>\;
Dbg_TrClk_3 <= \<const0>\;
Dbg_TrClk_30 <= \<const0>\;
Dbg_TrClk_31 <= \<const0>\;
Dbg_TrClk_4 <= \<const0>\;
Dbg_TrClk_5 <= \<const0>\;
Dbg_TrClk_6 <= \<const0>\;
Dbg_TrClk_7 <= \<const0>\;
Dbg_TrClk_8 <= \<const0>\;
Dbg_TrClk_9 <= \<const0>\;
Dbg_TrReady_0 <= \<const0>\;
Dbg_TrReady_1 <= \<const0>\;
Dbg_TrReady_10 <= \<const0>\;
Dbg_TrReady_11 <= \<const0>\;
Dbg_TrReady_12 <= \<const0>\;
Dbg_TrReady_13 <= \<const0>\;
Dbg_TrReady_14 <= \<const0>\;
Dbg_TrReady_15 <= \<const0>\;
Dbg_TrReady_16 <= \<const0>\;
Dbg_TrReady_17 <= \<const0>\;
Dbg_TrReady_18 <= \<const0>\;
Dbg_TrReady_19 <= \<const0>\;
Dbg_TrReady_2 <= \<const0>\;
Dbg_TrReady_20 <= \<const0>\;
Dbg_TrReady_21 <= \<const0>\;
Dbg_TrReady_22 <= \<const0>\;
Dbg_TrReady_23 <= \<const0>\;
Dbg_TrReady_24 <= \<const0>\;
Dbg_TrReady_25 <= \<const0>\;
Dbg_TrReady_26 <= \<const0>\;
Dbg_TrReady_27 <= \<const0>\;
Dbg_TrReady_28 <= \<const0>\;
Dbg_TrReady_29 <= \<const0>\;
Dbg_TrReady_3 <= \<const0>\;
Dbg_TrReady_30 <= \<const0>\;
Dbg_TrReady_31 <= \<const0>\;
Dbg_TrReady_4 <= \<const0>\;
Dbg_TrReady_5 <= \<const0>\;
Dbg_TrReady_6 <= \<const0>\;
Dbg_TrReady_7 <= \<const0>\;
Dbg_TrReady_8 <= \<const0>\;
Dbg_TrReady_9 <= \<const0>\;
Dbg_Trig_Ack_In_0(0) <= \<const0>\;
Dbg_Trig_Ack_In_0(1) <= \<const0>\;
Dbg_Trig_Ack_In_0(2) <= \<const0>\;
Dbg_Trig_Ack_In_0(3) <= \<const0>\;
Dbg_Trig_Ack_In_0(4) <= \<const0>\;
Dbg_Trig_Ack_In_0(5) <= \<const0>\;
Dbg_Trig_Ack_In_0(6) <= \<const0>\;
Dbg_Trig_Ack_In_0(7) <= \<const0>\;
Dbg_Trig_Ack_In_1(0) <= \<const0>\;
Dbg_Trig_Ack_In_1(1) <= \<const0>\;
Dbg_Trig_Ack_In_1(2) <= \<const0>\;
Dbg_Trig_Ack_In_1(3) <= \<const0>\;
Dbg_Trig_Ack_In_1(4) <= \<const0>\;
Dbg_Trig_Ack_In_1(5) <= \<const0>\;
Dbg_Trig_Ack_In_1(6) <= \<const0>\;
Dbg_Trig_Ack_In_1(7) <= \<const0>\;
Dbg_Trig_Ack_In_10(0) <= \<const0>\;
Dbg_Trig_Ack_In_10(1) <= \<const0>\;
Dbg_Trig_Ack_In_10(2) <= \<const0>\;
Dbg_Trig_Ack_In_10(3) <= \<const0>\;
Dbg_Trig_Ack_In_10(4) <= \<const0>\;
Dbg_Trig_Ack_In_10(5) <= \<const0>\;
Dbg_Trig_Ack_In_10(6) <= \<const0>\;
Dbg_Trig_Ack_In_10(7) <= \<const0>\;
Dbg_Trig_Ack_In_11(0) <= \<const0>\;
Dbg_Trig_Ack_In_11(1) <= \<const0>\;
Dbg_Trig_Ack_In_11(2) <= \<const0>\;
Dbg_Trig_Ack_In_11(3) <= \<const0>\;
Dbg_Trig_Ack_In_11(4) <= \<const0>\;
Dbg_Trig_Ack_In_11(5) <= \<const0>\;
Dbg_Trig_Ack_In_11(6) <= \<const0>\;
Dbg_Trig_Ack_In_11(7) <= \<const0>\;
Dbg_Trig_Ack_In_12(0) <= \<const0>\;
Dbg_Trig_Ack_In_12(1) <= \<const0>\;
Dbg_Trig_Ack_In_12(2) <= \<const0>\;
Dbg_Trig_Ack_In_12(3) <= \<const0>\;
Dbg_Trig_Ack_In_12(4) <= \<const0>\;
Dbg_Trig_Ack_In_12(5) <= \<const0>\;
Dbg_Trig_Ack_In_12(6) <= \<const0>\;
Dbg_Trig_Ack_In_12(7) <= \<const0>\;
Dbg_Trig_Ack_In_13(0) <= \<const0>\;
Dbg_Trig_Ack_In_13(1) <= \<const0>\;
Dbg_Trig_Ack_In_13(2) <= \<const0>\;
Dbg_Trig_Ack_In_13(3) <= \<const0>\;
Dbg_Trig_Ack_In_13(4) <= \<const0>\;
Dbg_Trig_Ack_In_13(5) <= \<const0>\;
Dbg_Trig_Ack_In_13(6) <= \<const0>\;
Dbg_Trig_Ack_In_13(7) <= \<const0>\;
Dbg_Trig_Ack_In_14(0) <= \<const0>\;
Dbg_Trig_Ack_In_14(1) <= \<const0>\;
Dbg_Trig_Ack_In_14(2) <= \<const0>\;
Dbg_Trig_Ack_In_14(3) <= \<const0>\;
Dbg_Trig_Ack_In_14(4) <= \<const0>\;
Dbg_Trig_Ack_In_14(5) <= \<const0>\;
Dbg_Trig_Ack_In_14(6) <= \<const0>\;
Dbg_Trig_Ack_In_14(7) <= \<const0>\;
Dbg_Trig_Ack_In_15(0) <= \<const0>\;
Dbg_Trig_Ack_In_15(1) <= \<const0>\;
Dbg_Trig_Ack_In_15(2) <= \<const0>\;
Dbg_Trig_Ack_In_15(3) <= \<const0>\;
Dbg_Trig_Ack_In_15(4) <= \<const0>\;
Dbg_Trig_Ack_In_15(5) <= \<const0>\;
Dbg_Trig_Ack_In_15(6) <= \<const0>\;
Dbg_Trig_Ack_In_15(7) <= \<const0>\;
Dbg_Trig_Ack_In_16(0) <= \<const0>\;
Dbg_Trig_Ack_In_16(1) <= \<const0>\;
Dbg_Trig_Ack_In_16(2) <= \<const0>\;
Dbg_Trig_Ack_In_16(3) <= \<const0>\;
Dbg_Trig_Ack_In_16(4) <= \<const0>\;
Dbg_Trig_Ack_In_16(5) <= \<const0>\;
Dbg_Trig_Ack_In_16(6) <= \<const0>\;
Dbg_Trig_Ack_In_16(7) <= \<const0>\;
Dbg_Trig_Ack_In_17(0) <= \<const0>\;
Dbg_Trig_Ack_In_17(1) <= \<const0>\;
Dbg_Trig_Ack_In_17(2) <= \<const0>\;
Dbg_Trig_Ack_In_17(3) <= \<const0>\;
Dbg_Trig_Ack_In_17(4) <= \<const0>\;
Dbg_Trig_Ack_In_17(5) <= \<const0>\;
Dbg_Trig_Ack_In_17(6) <= \<const0>\;
Dbg_Trig_Ack_In_17(7) <= \<const0>\;
Dbg_Trig_Ack_In_18(0) <= \<const0>\;
Dbg_Trig_Ack_In_18(1) <= \<const0>\;
Dbg_Trig_Ack_In_18(2) <= \<const0>\;
Dbg_Trig_Ack_In_18(3) <= \<const0>\;
Dbg_Trig_Ack_In_18(4) <= \<const0>\;
Dbg_Trig_Ack_In_18(5) <= \<const0>\;
Dbg_Trig_Ack_In_18(6) <= \<const0>\;
Dbg_Trig_Ack_In_18(7) <= \<const0>\;
Dbg_Trig_Ack_In_19(0) <= \<const0>\;
Dbg_Trig_Ack_In_19(1) <= \<const0>\;
Dbg_Trig_Ack_In_19(2) <= \<const0>\;
Dbg_Trig_Ack_In_19(3) <= \<const0>\;
Dbg_Trig_Ack_In_19(4) <= \<const0>\;
Dbg_Trig_Ack_In_19(5) <= \<const0>\;
Dbg_Trig_Ack_In_19(6) <= \<const0>\;
Dbg_Trig_Ack_In_19(7) <= \<const0>\;
Dbg_Trig_Ack_In_2(0) <= \<const0>\;
Dbg_Trig_Ack_In_2(1) <= \<const0>\;
Dbg_Trig_Ack_In_2(2) <= \<const0>\;
Dbg_Trig_Ack_In_2(3) <= \<const0>\;
Dbg_Trig_Ack_In_2(4) <= \<const0>\;
Dbg_Trig_Ack_In_2(5) <= \<const0>\;
Dbg_Trig_Ack_In_2(6) <= \<const0>\;
Dbg_Trig_Ack_In_2(7) <= \<const0>\;
Dbg_Trig_Ack_In_20(0) <= \<const0>\;
Dbg_Trig_Ack_In_20(1) <= \<const0>\;
Dbg_Trig_Ack_In_20(2) <= \<const0>\;
Dbg_Trig_Ack_In_20(3) <= \<const0>\;
Dbg_Trig_Ack_In_20(4) <= \<const0>\;
Dbg_Trig_Ack_In_20(5) <= \<const0>\;
Dbg_Trig_Ack_In_20(6) <= \<const0>\;
Dbg_Trig_Ack_In_20(7) <= \<const0>\;
Dbg_Trig_Ack_In_21(0) <= \<const0>\;
Dbg_Trig_Ack_In_21(1) <= \<const0>\;
Dbg_Trig_Ack_In_21(2) <= \<const0>\;
Dbg_Trig_Ack_In_21(3) <= \<const0>\;
Dbg_Trig_Ack_In_21(4) <= \<const0>\;
Dbg_Trig_Ack_In_21(5) <= \<const0>\;
Dbg_Trig_Ack_In_21(6) <= \<const0>\;
Dbg_Trig_Ack_In_21(7) <= \<const0>\;
Dbg_Trig_Ack_In_22(0) <= \<const0>\;
Dbg_Trig_Ack_In_22(1) <= \<const0>\;
Dbg_Trig_Ack_In_22(2) <= \<const0>\;
Dbg_Trig_Ack_In_22(3) <= \<const0>\;
Dbg_Trig_Ack_In_22(4) <= \<const0>\;
Dbg_Trig_Ack_In_22(5) <= \<const0>\;
Dbg_Trig_Ack_In_22(6) <= \<const0>\;
Dbg_Trig_Ack_In_22(7) <= \<const0>\;
Dbg_Trig_Ack_In_23(0) <= \<const0>\;
Dbg_Trig_Ack_In_23(1) <= \<const0>\;
Dbg_Trig_Ack_In_23(2) <= \<const0>\;
Dbg_Trig_Ack_In_23(3) <= \<const0>\;
Dbg_Trig_Ack_In_23(4) <= \<const0>\;
Dbg_Trig_Ack_In_23(5) <= \<const0>\;
Dbg_Trig_Ack_In_23(6) <= \<const0>\;
Dbg_Trig_Ack_In_23(7) <= \<const0>\;
Dbg_Trig_Ack_In_24(0) <= \<const0>\;
Dbg_Trig_Ack_In_24(1) <= \<const0>\;
Dbg_Trig_Ack_In_24(2) <= \<const0>\;
Dbg_Trig_Ack_In_24(3) <= \<const0>\;
Dbg_Trig_Ack_In_24(4) <= \<const0>\;
Dbg_Trig_Ack_In_24(5) <= \<const0>\;
Dbg_Trig_Ack_In_24(6) <= \<const0>\;
Dbg_Trig_Ack_In_24(7) <= \<const0>\;
Dbg_Trig_Ack_In_25(0) <= \<const0>\;
Dbg_Trig_Ack_In_25(1) <= \<const0>\;
Dbg_Trig_Ack_In_25(2) <= \<const0>\;
Dbg_Trig_Ack_In_25(3) <= \<const0>\;
Dbg_Trig_Ack_In_25(4) <= \<const0>\;
Dbg_Trig_Ack_In_25(5) <= \<const0>\;
Dbg_Trig_Ack_In_25(6) <= \<const0>\;
Dbg_Trig_Ack_In_25(7) <= \<const0>\;
Dbg_Trig_Ack_In_26(0) <= \<const0>\;
Dbg_Trig_Ack_In_26(1) <= \<const0>\;
Dbg_Trig_Ack_In_26(2) <= \<const0>\;
Dbg_Trig_Ack_In_26(3) <= \<const0>\;
Dbg_Trig_Ack_In_26(4) <= \<const0>\;
Dbg_Trig_Ack_In_26(5) <= \<const0>\;
Dbg_Trig_Ack_In_26(6) <= \<const0>\;
Dbg_Trig_Ack_In_26(7) <= \<const0>\;
Dbg_Trig_Ack_In_27(0) <= \<const0>\;
Dbg_Trig_Ack_In_27(1) <= \<const0>\;
Dbg_Trig_Ack_In_27(2) <= \<const0>\;
Dbg_Trig_Ack_In_27(3) <= \<const0>\;
Dbg_Trig_Ack_In_27(4) <= \<const0>\;
Dbg_Trig_Ack_In_27(5) <= \<const0>\;
Dbg_Trig_Ack_In_27(6) <= \<const0>\;
Dbg_Trig_Ack_In_27(7) <= \<const0>\;
Dbg_Trig_Ack_In_28(0) <= \<const0>\;
Dbg_Trig_Ack_In_28(1) <= \<const0>\;
Dbg_Trig_Ack_In_28(2) <= \<const0>\;
Dbg_Trig_Ack_In_28(3) <= \<const0>\;
Dbg_Trig_Ack_In_28(4) <= \<const0>\;
Dbg_Trig_Ack_In_28(5) <= \<const0>\;
Dbg_Trig_Ack_In_28(6) <= \<const0>\;
Dbg_Trig_Ack_In_28(7) <= \<const0>\;
Dbg_Trig_Ack_In_29(0) <= \<const0>\;
Dbg_Trig_Ack_In_29(1) <= \<const0>\;
Dbg_Trig_Ack_In_29(2) <= \<const0>\;
Dbg_Trig_Ack_In_29(3) <= \<const0>\;
Dbg_Trig_Ack_In_29(4) <= \<const0>\;
Dbg_Trig_Ack_In_29(5) <= \<const0>\;
Dbg_Trig_Ack_In_29(6) <= \<const0>\;
Dbg_Trig_Ack_In_29(7) <= \<const0>\;
Dbg_Trig_Ack_In_3(0) <= \<const0>\;
Dbg_Trig_Ack_In_3(1) <= \<const0>\;
Dbg_Trig_Ack_In_3(2) <= \<const0>\;
Dbg_Trig_Ack_In_3(3) <= \<const0>\;
Dbg_Trig_Ack_In_3(4) <= \<const0>\;
Dbg_Trig_Ack_In_3(5) <= \<const0>\;
Dbg_Trig_Ack_In_3(6) <= \<const0>\;
Dbg_Trig_Ack_In_3(7) <= \<const0>\;
Dbg_Trig_Ack_In_30(0) <= \<const0>\;
Dbg_Trig_Ack_In_30(1) <= \<const0>\;
Dbg_Trig_Ack_In_30(2) <= \<const0>\;
Dbg_Trig_Ack_In_30(3) <= \<const0>\;
Dbg_Trig_Ack_In_30(4) <= \<const0>\;
Dbg_Trig_Ack_In_30(5) <= \<const0>\;
Dbg_Trig_Ack_In_30(6) <= \<const0>\;
Dbg_Trig_Ack_In_30(7) <= \<const0>\;
Dbg_Trig_Ack_In_31(0) <= \<const0>\;
Dbg_Trig_Ack_In_31(1) <= \<const0>\;
Dbg_Trig_Ack_In_31(2) <= \<const0>\;
Dbg_Trig_Ack_In_31(3) <= \<const0>\;
Dbg_Trig_Ack_In_31(4) <= \<const0>\;
Dbg_Trig_Ack_In_31(5) <= \<const0>\;
Dbg_Trig_Ack_In_31(6) <= \<const0>\;
Dbg_Trig_Ack_In_31(7) <= \<const0>\;
Dbg_Trig_Ack_In_4(0) <= \<const0>\;
Dbg_Trig_Ack_In_4(1) <= \<const0>\;
Dbg_Trig_Ack_In_4(2) <= \<const0>\;
Dbg_Trig_Ack_In_4(3) <= \<const0>\;
Dbg_Trig_Ack_In_4(4) <= \<const0>\;
Dbg_Trig_Ack_In_4(5) <= \<const0>\;
Dbg_Trig_Ack_In_4(6) <= \<const0>\;
Dbg_Trig_Ack_In_4(7) <= \<const0>\;
Dbg_Trig_Ack_In_5(0) <= \<const0>\;
Dbg_Trig_Ack_In_5(1) <= \<const0>\;
Dbg_Trig_Ack_In_5(2) <= \<const0>\;
Dbg_Trig_Ack_In_5(3) <= \<const0>\;
Dbg_Trig_Ack_In_5(4) <= \<const0>\;
Dbg_Trig_Ack_In_5(5) <= \<const0>\;
Dbg_Trig_Ack_In_5(6) <= \<const0>\;
Dbg_Trig_Ack_In_5(7) <= \<const0>\;
Dbg_Trig_Ack_In_6(0) <= \<const0>\;
Dbg_Trig_Ack_In_6(1) <= \<const0>\;
Dbg_Trig_Ack_In_6(2) <= \<const0>\;
Dbg_Trig_Ack_In_6(3) <= \<const0>\;
Dbg_Trig_Ack_In_6(4) <= \<const0>\;
Dbg_Trig_Ack_In_6(5) <= \<const0>\;
Dbg_Trig_Ack_In_6(6) <= \<const0>\;
Dbg_Trig_Ack_In_6(7) <= \<const0>\;
Dbg_Trig_Ack_In_7(0) <= \<const0>\;
Dbg_Trig_Ack_In_7(1) <= \<const0>\;
Dbg_Trig_Ack_In_7(2) <= \<const0>\;
Dbg_Trig_Ack_In_7(3) <= \<const0>\;
Dbg_Trig_Ack_In_7(4) <= \<const0>\;
Dbg_Trig_Ack_In_7(5) <= \<const0>\;
Dbg_Trig_Ack_In_7(6) <= \<const0>\;
Dbg_Trig_Ack_In_7(7) <= \<const0>\;
Dbg_Trig_Ack_In_8(0) <= \<const0>\;
Dbg_Trig_Ack_In_8(1) <= \<const0>\;
Dbg_Trig_Ack_In_8(2) <= \<const0>\;
Dbg_Trig_Ack_In_8(3) <= \<const0>\;
Dbg_Trig_Ack_In_8(4) <= \<const0>\;
Dbg_Trig_Ack_In_8(5) <= \<const0>\;
Dbg_Trig_Ack_In_8(6) <= \<const0>\;
Dbg_Trig_Ack_In_8(7) <= \<const0>\;
Dbg_Trig_Ack_In_9(0) <= \<const0>\;
Dbg_Trig_Ack_In_9(1) <= \<const0>\;
Dbg_Trig_Ack_In_9(2) <= \<const0>\;
Dbg_Trig_Ack_In_9(3) <= \<const0>\;
Dbg_Trig_Ack_In_9(4) <= \<const0>\;
Dbg_Trig_Ack_In_9(5) <= \<const0>\;
Dbg_Trig_Ack_In_9(6) <= \<const0>\;
Dbg_Trig_Ack_In_9(7) <= \<const0>\;
Dbg_Trig_Out_0(0) <= \<const0>\;
Dbg_Trig_Out_0(1) <= \<const0>\;
Dbg_Trig_Out_0(2) <= \<const0>\;
Dbg_Trig_Out_0(3) <= \<const0>\;
Dbg_Trig_Out_0(4) <= \<const0>\;
Dbg_Trig_Out_0(5) <= \<const0>\;
Dbg_Trig_Out_0(6) <= \<const0>\;
Dbg_Trig_Out_0(7) <= \<const0>\;
Dbg_Trig_Out_1(0) <= \<const0>\;
Dbg_Trig_Out_1(1) <= \<const0>\;
Dbg_Trig_Out_1(2) <= \<const0>\;
Dbg_Trig_Out_1(3) <= \<const0>\;
Dbg_Trig_Out_1(4) <= \<const0>\;
Dbg_Trig_Out_1(5) <= \<const0>\;
Dbg_Trig_Out_1(6) <= \<const0>\;
Dbg_Trig_Out_1(7) <= \<const0>\;
Dbg_Trig_Out_10(0) <= \<const0>\;
Dbg_Trig_Out_10(1) <= \<const0>\;
Dbg_Trig_Out_10(2) <= \<const0>\;
Dbg_Trig_Out_10(3) <= \<const0>\;
Dbg_Trig_Out_10(4) <= \<const0>\;
Dbg_Trig_Out_10(5) <= \<const0>\;
Dbg_Trig_Out_10(6) <= \<const0>\;
Dbg_Trig_Out_10(7) <= \<const0>\;
Dbg_Trig_Out_11(0) <= \<const0>\;
Dbg_Trig_Out_11(1) <= \<const0>\;
Dbg_Trig_Out_11(2) <= \<const0>\;
Dbg_Trig_Out_11(3) <= \<const0>\;
Dbg_Trig_Out_11(4) <= \<const0>\;
Dbg_Trig_Out_11(5) <= \<const0>\;
Dbg_Trig_Out_11(6) <= \<const0>\;
Dbg_Trig_Out_11(7) <= \<const0>\;
Dbg_Trig_Out_12(0) <= \<const0>\;
Dbg_Trig_Out_12(1) <= \<const0>\;
Dbg_Trig_Out_12(2) <= \<const0>\;
Dbg_Trig_Out_12(3) <= \<const0>\;
Dbg_Trig_Out_12(4) <= \<const0>\;
Dbg_Trig_Out_12(5) <= \<const0>\;
Dbg_Trig_Out_12(6) <= \<const0>\;
Dbg_Trig_Out_12(7) <= \<const0>\;
Dbg_Trig_Out_13(0) <= \<const0>\;
Dbg_Trig_Out_13(1) <= \<const0>\;
Dbg_Trig_Out_13(2) <= \<const0>\;
Dbg_Trig_Out_13(3) <= \<const0>\;
Dbg_Trig_Out_13(4) <= \<const0>\;
Dbg_Trig_Out_13(5) <= \<const0>\;
Dbg_Trig_Out_13(6) <= \<const0>\;
Dbg_Trig_Out_13(7) <= \<const0>\;
Dbg_Trig_Out_14(0) <= \<const0>\;
Dbg_Trig_Out_14(1) <= \<const0>\;
Dbg_Trig_Out_14(2) <= \<const0>\;
Dbg_Trig_Out_14(3) <= \<const0>\;
Dbg_Trig_Out_14(4) <= \<const0>\;
Dbg_Trig_Out_14(5) <= \<const0>\;
Dbg_Trig_Out_14(6) <= \<const0>\;
Dbg_Trig_Out_14(7) <= \<const0>\;
Dbg_Trig_Out_15(0) <= \<const0>\;
Dbg_Trig_Out_15(1) <= \<const0>\;
Dbg_Trig_Out_15(2) <= \<const0>\;
Dbg_Trig_Out_15(3) <= \<const0>\;
Dbg_Trig_Out_15(4) <= \<const0>\;
Dbg_Trig_Out_15(5) <= \<const0>\;
Dbg_Trig_Out_15(6) <= \<const0>\;
Dbg_Trig_Out_15(7) <= \<const0>\;
Dbg_Trig_Out_16(0) <= \<const0>\;
Dbg_Trig_Out_16(1) <= \<const0>\;
Dbg_Trig_Out_16(2) <= \<const0>\;
Dbg_Trig_Out_16(3) <= \<const0>\;
Dbg_Trig_Out_16(4) <= \<const0>\;
Dbg_Trig_Out_16(5) <= \<const0>\;
Dbg_Trig_Out_16(6) <= \<const0>\;
Dbg_Trig_Out_16(7) <= \<const0>\;
Dbg_Trig_Out_17(0) <= \<const0>\;
Dbg_Trig_Out_17(1) <= \<const0>\;
Dbg_Trig_Out_17(2) <= \<const0>\;
Dbg_Trig_Out_17(3) <= \<const0>\;
Dbg_Trig_Out_17(4) <= \<const0>\;
Dbg_Trig_Out_17(5) <= \<const0>\;
Dbg_Trig_Out_17(6) <= \<const0>\;
Dbg_Trig_Out_17(7) <= \<const0>\;
Dbg_Trig_Out_18(0) <= \<const0>\;
Dbg_Trig_Out_18(1) <= \<const0>\;
Dbg_Trig_Out_18(2) <= \<const0>\;
Dbg_Trig_Out_18(3) <= \<const0>\;
Dbg_Trig_Out_18(4) <= \<const0>\;
Dbg_Trig_Out_18(5) <= \<const0>\;
Dbg_Trig_Out_18(6) <= \<const0>\;
Dbg_Trig_Out_18(7) <= \<const0>\;
Dbg_Trig_Out_19(0) <= \<const0>\;
Dbg_Trig_Out_19(1) <= \<const0>\;
Dbg_Trig_Out_19(2) <= \<const0>\;
Dbg_Trig_Out_19(3) <= \<const0>\;
Dbg_Trig_Out_19(4) <= \<const0>\;
Dbg_Trig_Out_19(5) <= \<const0>\;
Dbg_Trig_Out_19(6) <= \<const0>\;
Dbg_Trig_Out_19(7) <= \<const0>\;
Dbg_Trig_Out_2(0) <= \<const0>\;
Dbg_Trig_Out_2(1) <= \<const0>\;
Dbg_Trig_Out_2(2) <= \<const0>\;
Dbg_Trig_Out_2(3) <= \<const0>\;
Dbg_Trig_Out_2(4) <= \<const0>\;
Dbg_Trig_Out_2(5) <= \<const0>\;
Dbg_Trig_Out_2(6) <= \<const0>\;
Dbg_Trig_Out_2(7) <= \<const0>\;
Dbg_Trig_Out_20(0) <= \<const0>\;
Dbg_Trig_Out_20(1) <= \<const0>\;
Dbg_Trig_Out_20(2) <= \<const0>\;
Dbg_Trig_Out_20(3) <= \<const0>\;
Dbg_Trig_Out_20(4) <= \<const0>\;
Dbg_Trig_Out_20(5) <= \<const0>\;
Dbg_Trig_Out_20(6) <= \<const0>\;
Dbg_Trig_Out_20(7) <= \<const0>\;
Dbg_Trig_Out_21(0) <= \<const0>\;
Dbg_Trig_Out_21(1) <= \<const0>\;
Dbg_Trig_Out_21(2) <= \<const0>\;
Dbg_Trig_Out_21(3) <= \<const0>\;
Dbg_Trig_Out_21(4) <= \<const0>\;
Dbg_Trig_Out_21(5) <= \<const0>\;
Dbg_Trig_Out_21(6) <= \<const0>\;
Dbg_Trig_Out_21(7) <= \<const0>\;
Dbg_Trig_Out_22(0) <= \<const0>\;
Dbg_Trig_Out_22(1) <= \<const0>\;
Dbg_Trig_Out_22(2) <= \<const0>\;
Dbg_Trig_Out_22(3) <= \<const0>\;
Dbg_Trig_Out_22(4) <= \<const0>\;
Dbg_Trig_Out_22(5) <= \<const0>\;
Dbg_Trig_Out_22(6) <= \<const0>\;
Dbg_Trig_Out_22(7) <= \<const0>\;
Dbg_Trig_Out_23(0) <= \<const0>\;
Dbg_Trig_Out_23(1) <= \<const0>\;
Dbg_Trig_Out_23(2) <= \<const0>\;
Dbg_Trig_Out_23(3) <= \<const0>\;
Dbg_Trig_Out_23(4) <= \<const0>\;
Dbg_Trig_Out_23(5) <= \<const0>\;
Dbg_Trig_Out_23(6) <= \<const0>\;
Dbg_Trig_Out_23(7) <= \<const0>\;
Dbg_Trig_Out_24(0) <= \<const0>\;
Dbg_Trig_Out_24(1) <= \<const0>\;
Dbg_Trig_Out_24(2) <= \<const0>\;
Dbg_Trig_Out_24(3) <= \<const0>\;
Dbg_Trig_Out_24(4) <= \<const0>\;
Dbg_Trig_Out_24(5) <= \<const0>\;
Dbg_Trig_Out_24(6) <= \<const0>\;
Dbg_Trig_Out_24(7) <= \<const0>\;
Dbg_Trig_Out_25(0) <= \<const0>\;
Dbg_Trig_Out_25(1) <= \<const0>\;
Dbg_Trig_Out_25(2) <= \<const0>\;
Dbg_Trig_Out_25(3) <= \<const0>\;
Dbg_Trig_Out_25(4) <= \<const0>\;
Dbg_Trig_Out_25(5) <= \<const0>\;
Dbg_Trig_Out_25(6) <= \<const0>\;
Dbg_Trig_Out_25(7) <= \<const0>\;
Dbg_Trig_Out_26(0) <= \<const0>\;
Dbg_Trig_Out_26(1) <= \<const0>\;
Dbg_Trig_Out_26(2) <= \<const0>\;
Dbg_Trig_Out_26(3) <= \<const0>\;
Dbg_Trig_Out_26(4) <= \<const0>\;
Dbg_Trig_Out_26(5) <= \<const0>\;
Dbg_Trig_Out_26(6) <= \<const0>\;
Dbg_Trig_Out_26(7) <= \<const0>\;
Dbg_Trig_Out_27(0) <= \<const0>\;
Dbg_Trig_Out_27(1) <= \<const0>\;
Dbg_Trig_Out_27(2) <= \<const0>\;
Dbg_Trig_Out_27(3) <= \<const0>\;
Dbg_Trig_Out_27(4) <= \<const0>\;
Dbg_Trig_Out_27(5) <= \<const0>\;
Dbg_Trig_Out_27(6) <= \<const0>\;
Dbg_Trig_Out_27(7) <= \<const0>\;
Dbg_Trig_Out_28(0) <= \<const0>\;
Dbg_Trig_Out_28(1) <= \<const0>\;
Dbg_Trig_Out_28(2) <= \<const0>\;
Dbg_Trig_Out_28(3) <= \<const0>\;
Dbg_Trig_Out_28(4) <= \<const0>\;
Dbg_Trig_Out_28(5) <= \<const0>\;
Dbg_Trig_Out_28(6) <= \<const0>\;
Dbg_Trig_Out_28(7) <= \<const0>\;
Dbg_Trig_Out_29(0) <= \<const0>\;
Dbg_Trig_Out_29(1) <= \<const0>\;
Dbg_Trig_Out_29(2) <= \<const0>\;
Dbg_Trig_Out_29(3) <= \<const0>\;
Dbg_Trig_Out_29(4) <= \<const0>\;
Dbg_Trig_Out_29(5) <= \<const0>\;
Dbg_Trig_Out_29(6) <= \<const0>\;
Dbg_Trig_Out_29(7) <= \<const0>\;
Dbg_Trig_Out_3(0) <= \<const0>\;
Dbg_Trig_Out_3(1) <= \<const0>\;
Dbg_Trig_Out_3(2) <= \<const0>\;
Dbg_Trig_Out_3(3) <= \<const0>\;
Dbg_Trig_Out_3(4) <= \<const0>\;
Dbg_Trig_Out_3(5) <= \<const0>\;
Dbg_Trig_Out_3(6) <= \<const0>\;
Dbg_Trig_Out_3(7) <= \<const0>\;
Dbg_Trig_Out_30(0) <= \<const0>\;
Dbg_Trig_Out_30(1) <= \<const0>\;
Dbg_Trig_Out_30(2) <= \<const0>\;
Dbg_Trig_Out_30(3) <= \<const0>\;
Dbg_Trig_Out_30(4) <= \<const0>\;
Dbg_Trig_Out_30(5) <= \<const0>\;
Dbg_Trig_Out_30(6) <= \<const0>\;
Dbg_Trig_Out_30(7) <= \<const0>\;
Dbg_Trig_Out_31(0) <= \<const0>\;
Dbg_Trig_Out_31(1) <= \<const0>\;
Dbg_Trig_Out_31(2) <= \<const0>\;
Dbg_Trig_Out_31(3) <= \<const0>\;
Dbg_Trig_Out_31(4) <= \<const0>\;
Dbg_Trig_Out_31(5) <= \<const0>\;
Dbg_Trig_Out_31(6) <= \<const0>\;
Dbg_Trig_Out_31(7) <= \<const0>\;
Dbg_Trig_Out_4(0) <= \<const0>\;
Dbg_Trig_Out_4(1) <= \<const0>\;
Dbg_Trig_Out_4(2) <= \<const0>\;
Dbg_Trig_Out_4(3) <= \<const0>\;
Dbg_Trig_Out_4(4) <= \<const0>\;
Dbg_Trig_Out_4(5) <= \<const0>\;
Dbg_Trig_Out_4(6) <= \<const0>\;
Dbg_Trig_Out_4(7) <= \<const0>\;
Dbg_Trig_Out_5(0) <= \<const0>\;
Dbg_Trig_Out_5(1) <= \<const0>\;
Dbg_Trig_Out_5(2) <= \<const0>\;
Dbg_Trig_Out_5(3) <= \<const0>\;
Dbg_Trig_Out_5(4) <= \<const0>\;
Dbg_Trig_Out_5(5) <= \<const0>\;
Dbg_Trig_Out_5(6) <= \<const0>\;
Dbg_Trig_Out_5(7) <= \<const0>\;
Dbg_Trig_Out_6(0) <= \<const0>\;
Dbg_Trig_Out_6(1) <= \<const0>\;
Dbg_Trig_Out_6(2) <= \<const0>\;
Dbg_Trig_Out_6(3) <= \<const0>\;
Dbg_Trig_Out_6(4) <= \<const0>\;
Dbg_Trig_Out_6(5) <= \<const0>\;
Dbg_Trig_Out_6(6) <= \<const0>\;
Dbg_Trig_Out_6(7) <= \<const0>\;
Dbg_Trig_Out_7(0) <= \<const0>\;
Dbg_Trig_Out_7(1) <= \<const0>\;
Dbg_Trig_Out_7(2) <= \<const0>\;
Dbg_Trig_Out_7(3) <= \<const0>\;
Dbg_Trig_Out_7(4) <= \<const0>\;
Dbg_Trig_Out_7(5) <= \<const0>\;
Dbg_Trig_Out_7(6) <= \<const0>\;
Dbg_Trig_Out_7(7) <= \<const0>\;
Dbg_Trig_Out_8(0) <= \<const0>\;
Dbg_Trig_Out_8(1) <= \<const0>\;
Dbg_Trig_Out_8(2) <= \<const0>\;
Dbg_Trig_Out_8(3) <= \<const0>\;
Dbg_Trig_Out_8(4) <= \<const0>\;
Dbg_Trig_Out_8(5) <= \<const0>\;
Dbg_Trig_Out_8(6) <= \<const0>\;
Dbg_Trig_Out_8(7) <= \<const0>\;
Dbg_Trig_Out_9(0) <= \<const0>\;
Dbg_Trig_Out_9(1) <= \<const0>\;
Dbg_Trig_Out_9(2) <= \<const0>\;
Dbg_Trig_Out_9(3) <= \<const0>\;
Dbg_Trig_Out_9(4) <= \<const0>\;
Dbg_Trig_Out_9(5) <= \<const0>\;
Dbg_Trig_Out_9(6) <= \<const0>\;
Dbg_Trig_Out_9(7) <= \<const0>\;
Dbg_Update_0 <= \^dbg_update_31\;
Dbg_Update_1 <= \^dbg_update_31\;
Dbg_Update_10 <= \^dbg_update_31\;
Dbg_Update_11 <= \^dbg_update_31\;
Dbg_Update_12 <= \^dbg_update_31\;
Dbg_Update_13 <= \^dbg_update_31\;
Dbg_Update_14 <= \^dbg_update_31\;
Dbg_Update_15 <= \^dbg_update_31\;
Dbg_Update_16 <= \^dbg_update_31\;
Dbg_Update_17 <= \^dbg_update_31\;
Dbg_Update_18 <= \^dbg_update_31\;
Dbg_Update_19 <= \^dbg_update_31\;
Dbg_Update_2 <= \^dbg_update_31\;
Dbg_Update_20 <= \^dbg_update_31\;
Dbg_Update_21 <= \^dbg_update_31\;
Dbg_Update_22 <= \^dbg_update_31\;
Dbg_Update_23 <= \^dbg_update_31\;
Dbg_Update_24 <= \^dbg_update_31\;
Dbg_Update_25 <= \^dbg_update_31\;
Dbg_Update_26 <= \^dbg_update_31\;
Dbg_Update_27 <= \^dbg_update_31\;
Dbg_Update_28 <= \^dbg_update_31\;
Dbg_Update_29 <= \^dbg_update_31\;
Dbg_Update_3 <= \^dbg_update_31\;
Dbg_Update_30 <= \^dbg_update_31\;
Dbg_Update_31 <= \^dbg_update_31\;
Dbg_Update_4 <= \^dbg_update_31\;
Dbg_Update_5 <= \^dbg_update_31\;
Dbg_Update_6 <= \^dbg_update_31\;
Dbg_Update_7 <= \^dbg_update_31\;
Dbg_Update_8 <= \^dbg_update_31\;
Dbg_Update_9 <= \^dbg_update_31\;
Dbg_WDATA_0(31) <= \<const0>\;
Dbg_WDATA_0(30) <= \<const0>\;
Dbg_WDATA_0(29) <= \<const0>\;
Dbg_WDATA_0(28) <= \<const0>\;
Dbg_WDATA_0(27) <= \<const0>\;
Dbg_WDATA_0(26) <= \<const0>\;
Dbg_WDATA_0(25) <= \<const0>\;
Dbg_WDATA_0(24) <= \<const0>\;
Dbg_WDATA_0(23) <= \<const0>\;
Dbg_WDATA_0(22) <= \<const0>\;
Dbg_WDATA_0(21) <= \<const0>\;
Dbg_WDATA_0(20) <= \<const0>\;
Dbg_WDATA_0(19) <= \<const0>\;
Dbg_WDATA_0(18) <= \<const0>\;
Dbg_WDATA_0(17) <= \<const0>\;
Dbg_WDATA_0(16) <= \<const0>\;
Dbg_WDATA_0(15) <= \<const0>\;
Dbg_WDATA_0(14) <= \<const0>\;
Dbg_WDATA_0(13) <= \<const0>\;
Dbg_WDATA_0(12) <= \<const0>\;
Dbg_WDATA_0(11) <= \<const0>\;
Dbg_WDATA_0(10) <= \<const0>\;
Dbg_WDATA_0(9) <= \<const0>\;
Dbg_WDATA_0(8) <= \<const0>\;
Dbg_WDATA_0(7) <= \<const0>\;
Dbg_WDATA_0(6) <= \<const0>\;
Dbg_WDATA_0(5) <= \<const0>\;
Dbg_WDATA_0(4) <= \<const0>\;
Dbg_WDATA_0(3) <= \<const0>\;
Dbg_WDATA_0(2) <= \<const0>\;
Dbg_WDATA_0(1) <= \<const0>\;
Dbg_WDATA_0(0) <= \<const0>\;
Dbg_WDATA_1(31) <= \<const0>\;
Dbg_WDATA_1(30) <= \<const0>\;
Dbg_WDATA_1(29) <= \<const0>\;
Dbg_WDATA_1(28) <= \<const0>\;
Dbg_WDATA_1(27) <= \<const0>\;
Dbg_WDATA_1(26) <= \<const0>\;
Dbg_WDATA_1(25) <= \<const0>\;
Dbg_WDATA_1(24) <= \<const0>\;
Dbg_WDATA_1(23) <= \<const0>\;
Dbg_WDATA_1(22) <= \<const0>\;
Dbg_WDATA_1(21) <= \<const0>\;
Dbg_WDATA_1(20) <= \<const0>\;
Dbg_WDATA_1(19) <= \<const0>\;
Dbg_WDATA_1(18) <= \<const0>\;
Dbg_WDATA_1(17) <= \<const0>\;
Dbg_WDATA_1(16) <= \<const0>\;
Dbg_WDATA_1(15) <= \<const0>\;
Dbg_WDATA_1(14) <= \<const0>\;
Dbg_WDATA_1(13) <= \<const0>\;
Dbg_WDATA_1(12) <= \<const0>\;
Dbg_WDATA_1(11) <= \<const0>\;
Dbg_WDATA_1(10) <= \<const0>\;
Dbg_WDATA_1(9) <= \<const0>\;
Dbg_WDATA_1(8) <= \<const0>\;
Dbg_WDATA_1(7) <= \<const0>\;
Dbg_WDATA_1(6) <= \<const0>\;
Dbg_WDATA_1(5) <= \<const0>\;
Dbg_WDATA_1(4) <= \<const0>\;
Dbg_WDATA_1(3) <= \<const0>\;
Dbg_WDATA_1(2) <= \<const0>\;
Dbg_WDATA_1(1) <= \<const0>\;
Dbg_WDATA_1(0) <= \<const0>\;
Dbg_WDATA_10(31) <= \<const0>\;
Dbg_WDATA_10(30) <= \<const0>\;
Dbg_WDATA_10(29) <= \<const0>\;
Dbg_WDATA_10(28) <= \<const0>\;
Dbg_WDATA_10(27) <= \<const0>\;
Dbg_WDATA_10(26) <= \<const0>\;
Dbg_WDATA_10(25) <= \<const0>\;
Dbg_WDATA_10(24) <= \<const0>\;
Dbg_WDATA_10(23) <= \<const0>\;
Dbg_WDATA_10(22) <= \<const0>\;
Dbg_WDATA_10(21) <= \<const0>\;
Dbg_WDATA_10(20) <= \<const0>\;
Dbg_WDATA_10(19) <= \<const0>\;
Dbg_WDATA_10(18) <= \<const0>\;
Dbg_WDATA_10(17) <= \<const0>\;
Dbg_WDATA_10(16) <= \<const0>\;
Dbg_WDATA_10(15) <= \<const0>\;
Dbg_WDATA_10(14) <= \<const0>\;
Dbg_WDATA_10(13) <= \<const0>\;
Dbg_WDATA_10(12) <= \<const0>\;
Dbg_WDATA_10(11) <= \<const0>\;
Dbg_WDATA_10(10) <= \<const0>\;
Dbg_WDATA_10(9) <= \<const0>\;
Dbg_WDATA_10(8) <= \<const0>\;
Dbg_WDATA_10(7) <= \<const0>\;
Dbg_WDATA_10(6) <= \<const0>\;
Dbg_WDATA_10(5) <= \<const0>\;
Dbg_WDATA_10(4) <= \<const0>\;
Dbg_WDATA_10(3) <= \<const0>\;
Dbg_WDATA_10(2) <= \<const0>\;
Dbg_WDATA_10(1) <= \<const0>\;
Dbg_WDATA_10(0) <= \<const0>\;
Dbg_WDATA_11(31) <= \<const0>\;
Dbg_WDATA_11(30) <= \<const0>\;
Dbg_WDATA_11(29) <= \<const0>\;
Dbg_WDATA_11(28) <= \<const0>\;
Dbg_WDATA_11(27) <= \<const0>\;
Dbg_WDATA_11(26) <= \<const0>\;
Dbg_WDATA_11(25) <= \<const0>\;
Dbg_WDATA_11(24) <= \<const0>\;
Dbg_WDATA_11(23) <= \<const0>\;
Dbg_WDATA_11(22) <= \<const0>\;
Dbg_WDATA_11(21) <= \<const0>\;
Dbg_WDATA_11(20) <= \<const0>\;
Dbg_WDATA_11(19) <= \<const0>\;
Dbg_WDATA_11(18) <= \<const0>\;
Dbg_WDATA_11(17) <= \<const0>\;
Dbg_WDATA_11(16) <= \<const0>\;
Dbg_WDATA_11(15) <= \<const0>\;
Dbg_WDATA_11(14) <= \<const0>\;
Dbg_WDATA_11(13) <= \<const0>\;
Dbg_WDATA_11(12) <= \<const0>\;
Dbg_WDATA_11(11) <= \<const0>\;
Dbg_WDATA_11(10) <= \<const0>\;
Dbg_WDATA_11(9) <= \<const0>\;
Dbg_WDATA_11(8) <= \<const0>\;
Dbg_WDATA_11(7) <= \<const0>\;
Dbg_WDATA_11(6) <= \<const0>\;
Dbg_WDATA_11(5) <= \<const0>\;
Dbg_WDATA_11(4) <= \<const0>\;
Dbg_WDATA_11(3) <= \<const0>\;
Dbg_WDATA_11(2) <= \<const0>\;
Dbg_WDATA_11(1) <= \<const0>\;
Dbg_WDATA_11(0) <= \<const0>\;
Dbg_WDATA_12(31) <= \<const0>\;
Dbg_WDATA_12(30) <= \<const0>\;
Dbg_WDATA_12(29) <= \<const0>\;
Dbg_WDATA_12(28) <= \<const0>\;
Dbg_WDATA_12(27) <= \<const0>\;
Dbg_WDATA_12(26) <= \<const0>\;
Dbg_WDATA_12(25) <= \<const0>\;
Dbg_WDATA_12(24) <= \<const0>\;
Dbg_WDATA_12(23) <= \<const0>\;
Dbg_WDATA_12(22) <= \<const0>\;
Dbg_WDATA_12(21) <= \<const0>\;
Dbg_WDATA_12(20) <= \<const0>\;
Dbg_WDATA_12(19) <= \<const0>\;
Dbg_WDATA_12(18) <= \<const0>\;
Dbg_WDATA_12(17) <= \<const0>\;
Dbg_WDATA_12(16) <= \<const0>\;
Dbg_WDATA_12(15) <= \<const0>\;
Dbg_WDATA_12(14) <= \<const0>\;
Dbg_WDATA_12(13) <= \<const0>\;
Dbg_WDATA_12(12) <= \<const0>\;
Dbg_WDATA_12(11) <= \<const0>\;
Dbg_WDATA_12(10) <= \<const0>\;
Dbg_WDATA_12(9) <= \<const0>\;
Dbg_WDATA_12(8) <= \<const0>\;
Dbg_WDATA_12(7) <= \<const0>\;
Dbg_WDATA_12(6) <= \<const0>\;
Dbg_WDATA_12(5) <= \<const0>\;
Dbg_WDATA_12(4) <= \<const0>\;
Dbg_WDATA_12(3) <= \<const0>\;
Dbg_WDATA_12(2) <= \<const0>\;
Dbg_WDATA_12(1) <= \<const0>\;
Dbg_WDATA_12(0) <= \<const0>\;
Dbg_WDATA_13(31) <= \<const0>\;
Dbg_WDATA_13(30) <= \<const0>\;
Dbg_WDATA_13(29) <= \<const0>\;
Dbg_WDATA_13(28) <= \<const0>\;
Dbg_WDATA_13(27) <= \<const0>\;
Dbg_WDATA_13(26) <= \<const0>\;
Dbg_WDATA_13(25) <= \<const0>\;
Dbg_WDATA_13(24) <= \<const0>\;
Dbg_WDATA_13(23) <= \<const0>\;
Dbg_WDATA_13(22) <= \<const0>\;
Dbg_WDATA_13(21) <= \<const0>\;
Dbg_WDATA_13(20) <= \<const0>\;
Dbg_WDATA_13(19) <= \<const0>\;
Dbg_WDATA_13(18) <= \<const0>\;
Dbg_WDATA_13(17) <= \<const0>\;
Dbg_WDATA_13(16) <= \<const0>\;
Dbg_WDATA_13(15) <= \<const0>\;
Dbg_WDATA_13(14) <= \<const0>\;
Dbg_WDATA_13(13) <= \<const0>\;
Dbg_WDATA_13(12) <= \<const0>\;
Dbg_WDATA_13(11) <= \<const0>\;
Dbg_WDATA_13(10) <= \<const0>\;
Dbg_WDATA_13(9) <= \<const0>\;
Dbg_WDATA_13(8) <= \<const0>\;
Dbg_WDATA_13(7) <= \<const0>\;
Dbg_WDATA_13(6) <= \<const0>\;
Dbg_WDATA_13(5) <= \<const0>\;
Dbg_WDATA_13(4) <= \<const0>\;
Dbg_WDATA_13(3) <= \<const0>\;
Dbg_WDATA_13(2) <= \<const0>\;
Dbg_WDATA_13(1) <= \<const0>\;
Dbg_WDATA_13(0) <= \<const0>\;
Dbg_WDATA_14(31) <= \<const0>\;
Dbg_WDATA_14(30) <= \<const0>\;
Dbg_WDATA_14(29) <= \<const0>\;
Dbg_WDATA_14(28) <= \<const0>\;
Dbg_WDATA_14(27) <= \<const0>\;
Dbg_WDATA_14(26) <= \<const0>\;
Dbg_WDATA_14(25) <= \<const0>\;
Dbg_WDATA_14(24) <= \<const0>\;
Dbg_WDATA_14(23) <= \<const0>\;
Dbg_WDATA_14(22) <= \<const0>\;
Dbg_WDATA_14(21) <= \<const0>\;
Dbg_WDATA_14(20) <= \<const0>\;
Dbg_WDATA_14(19) <= \<const0>\;
Dbg_WDATA_14(18) <= \<const0>\;
Dbg_WDATA_14(17) <= \<const0>\;
Dbg_WDATA_14(16) <= \<const0>\;
Dbg_WDATA_14(15) <= \<const0>\;
Dbg_WDATA_14(14) <= \<const0>\;
Dbg_WDATA_14(13) <= \<const0>\;
Dbg_WDATA_14(12) <= \<const0>\;
Dbg_WDATA_14(11) <= \<const0>\;
Dbg_WDATA_14(10) <= \<const0>\;
Dbg_WDATA_14(9) <= \<const0>\;
Dbg_WDATA_14(8) <= \<const0>\;
Dbg_WDATA_14(7) <= \<const0>\;
Dbg_WDATA_14(6) <= \<const0>\;
Dbg_WDATA_14(5) <= \<const0>\;
Dbg_WDATA_14(4) <= \<const0>\;
Dbg_WDATA_14(3) <= \<const0>\;
Dbg_WDATA_14(2) <= \<const0>\;
Dbg_WDATA_14(1) <= \<const0>\;
Dbg_WDATA_14(0) <= \<const0>\;
Dbg_WDATA_15(31) <= \<const0>\;
Dbg_WDATA_15(30) <= \<const0>\;
Dbg_WDATA_15(29) <= \<const0>\;
Dbg_WDATA_15(28) <= \<const0>\;
Dbg_WDATA_15(27) <= \<const0>\;
Dbg_WDATA_15(26) <= \<const0>\;
Dbg_WDATA_15(25) <= \<const0>\;
Dbg_WDATA_15(24) <= \<const0>\;
Dbg_WDATA_15(23) <= \<const0>\;
Dbg_WDATA_15(22) <= \<const0>\;
Dbg_WDATA_15(21) <= \<const0>\;
Dbg_WDATA_15(20) <= \<const0>\;
Dbg_WDATA_15(19) <= \<const0>\;
Dbg_WDATA_15(18) <= \<const0>\;
Dbg_WDATA_15(17) <= \<const0>\;
Dbg_WDATA_15(16) <= \<const0>\;
Dbg_WDATA_15(15) <= \<const0>\;
Dbg_WDATA_15(14) <= \<const0>\;
Dbg_WDATA_15(13) <= \<const0>\;
Dbg_WDATA_15(12) <= \<const0>\;
Dbg_WDATA_15(11) <= \<const0>\;
Dbg_WDATA_15(10) <= \<const0>\;
Dbg_WDATA_15(9) <= \<const0>\;
Dbg_WDATA_15(8) <= \<const0>\;
Dbg_WDATA_15(7) <= \<const0>\;
Dbg_WDATA_15(6) <= \<const0>\;
Dbg_WDATA_15(5) <= \<const0>\;
Dbg_WDATA_15(4) <= \<const0>\;
Dbg_WDATA_15(3) <= \<const0>\;
Dbg_WDATA_15(2) <= \<const0>\;
Dbg_WDATA_15(1) <= \<const0>\;
Dbg_WDATA_15(0) <= \<const0>\;
Dbg_WDATA_16(31) <= \<const0>\;
Dbg_WDATA_16(30) <= \<const0>\;
Dbg_WDATA_16(29) <= \<const0>\;
Dbg_WDATA_16(28) <= \<const0>\;
Dbg_WDATA_16(27) <= \<const0>\;
Dbg_WDATA_16(26) <= \<const0>\;
Dbg_WDATA_16(25) <= \<const0>\;
Dbg_WDATA_16(24) <= \<const0>\;
Dbg_WDATA_16(23) <= \<const0>\;
Dbg_WDATA_16(22) <= \<const0>\;
Dbg_WDATA_16(21) <= \<const0>\;
Dbg_WDATA_16(20) <= \<const0>\;
Dbg_WDATA_16(19) <= \<const0>\;
Dbg_WDATA_16(18) <= \<const0>\;
Dbg_WDATA_16(17) <= \<const0>\;
Dbg_WDATA_16(16) <= \<const0>\;
Dbg_WDATA_16(15) <= \<const0>\;
Dbg_WDATA_16(14) <= \<const0>\;
Dbg_WDATA_16(13) <= \<const0>\;
Dbg_WDATA_16(12) <= \<const0>\;
Dbg_WDATA_16(11) <= \<const0>\;
Dbg_WDATA_16(10) <= \<const0>\;
Dbg_WDATA_16(9) <= \<const0>\;
Dbg_WDATA_16(8) <= \<const0>\;
Dbg_WDATA_16(7) <= \<const0>\;
Dbg_WDATA_16(6) <= \<const0>\;
Dbg_WDATA_16(5) <= \<const0>\;
Dbg_WDATA_16(4) <= \<const0>\;
Dbg_WDATA_16(3) <= \<const0>\;
Dbg_WDATA_16(2) <= \<const0>\;
Dbg_WDATA_16(1) <= \<const0>\;
Dbg_WDATA_16(0) <= \<const0>\;
Dbg_WDATA_17(31) <= \<const0>\;
Dbg_WDATA_17(30) <= \<const0>\;
Dbg_WDATA_17(29) <= \<const0>\;
Dbg_WDATA_17(28) <= \<const0>\;
Dbg_WDATA_17(27) <= \<const0>\;
Dbg_WDATA_17(26) <= \<const0>\;
Dbg_WDATA_17(25) <= \<const0>\;
Dbg_WDATA_17(24) <= \<const0>\;
Dbg_WDATA_17(23) <= \<const0>\;
Dbg_WDATA_17(22) <= \<const0>\;
Dbg_WDATA_17(21) <= \<const0>\;
Dbg_WDATA_17(20) <= \<const0>\;
Dbg_WDATA_17(19) <= \<const0>\;
Dbg_WDATA_17(18) <= \<const0>\;
Dbg_WDATA_17(17) <= \<const0>\;
Dbg_WDATA_17(16) <= \<const0>\;
Dbg_WDATA_17(15) <= \<const0>\;
Dbg_WDATA_17(14) <= \<const0>\;
Dbg_WDATA_17(13) <= \<const0>\;
Dbg_WDATA_17(12) <= \<const0>\;
Dbg_WDATA_17(11) <= \<const0>\;
Dbg_WDATA_17(10) <= \<const0>\;
Dbg_WDATA_17(9) <= \<const0>\;
Dbg_WDATA_17(8) <= \<const0>\;
Dbg_WDATA_17(7) <= \<const0>\;
Dbg_WDATA_17(6) <= \<const0>\;
Dbg_WDATA_17(5) <= \<const0>\;
Dbg_WDATA_17(4) <= \<const0>\;
Dbg_WDATA_17(3) <= \<const0>\;
Dbg_WDATA_17(2) <= \<const0>\;
Dbg_WDATA_17(1) <= \<const0>\;
Dbg_WDATA_17(0) <= \<const0>\;
Dbg_WDATA_18(31) <= \<const0>\;
Dbg_WDATA_18(30) <= \<const0>\;
Dbg_WDATA_18(29) <= \<const0>\;
Dbg_WDATA_18(28) <= \<const0>\;
Dbg_WDATA_18(27) <= \<const0>\;
Dbg_WDATA_18(26) <= \<const0>\;
Dbg_WDATA_18(25) <= \<const0>\;
Dbg_WDATA_18(24) <= \<const0>\;
Dbg_WDATA_18(23) <= \<const0>\;
Dbg_WDATA_18(22) <= \<const0>\;
Dbg_WDATA_18(21) <= \<const0>\;
Dbg_WDATA_18(20) <= \<const0>\;
Dbg_WDATA_18(19) <= \<const0>\;
Dbg_WDATA_18(18) <= \<const0>\;
Dbg_WDATA_18(17) <= \<const0>\;
Dbg_WDATA_18(16) <= \<const0>\;
Dbg_WDATA_18(15) <= \<const0>\;
Dbg_WDATA_18(14) <= \<const0>\;
Dbg_WDATA_18(13) <= \<const0>\;
Dbg_WDATA_18(12) <= \<const0>\;
Dbg_WDATA_18(11) <= \<const0>\;
Dbg_WDATA_18(10) <= \<const0>\;
Dbg_WDATA_18(9) <= \<const0>\;
Dbg_WDATA_18(8) <= \<const0>\;
Dbg_WDATA_18(7) <= \<const0>\;
Dbg_WDATA_18(6) <= \<const0>\;
Dbg_WDATA_18(5) <= \<const0>\;
Dbg_WDATA_18(4) <= \<const0>\;
Dbg_WDATA_18(3) <= \<const0>\;
Dbg_WDATA_18(2) <= \<const0>\;
Dbg_WDATA_18(1) <= \<const0>\;
Dbg_WDATA_18(0) <= \<const0>\;
Dbg_WDATA_19(31) <= \<const0>\;
Dbg_WDATA_19(30) <= \<const0>\;
Dbg_WDATA_19(29) <= \<const0>\;
Dbg_WDATA_19(28) <= \<const0>\;
Dbg_WDATA_19(27) <= \<const0>\;
Dbg_WDATA_19(26) <= \<const0>\;
Dbg_WDATA_19(25) <= \<const0>\;
Dbg_WDATA_19(24) <= \<const0>\;
Dbg_WDATA_19(23) <= \<const0>\;
Dbg_WDATA_19(22) <= \<const0>\;
Dbg_WDATA_19(21) <= \<const0>\;
Dbg_WDATA_19(20) <= \<const0>\;
Dbg_WDATA_19(19) <= \<const0>\;
Dbg_WDATA_19(18) <= \<const0>\;
Dbg_WDATA_19(17) <= \<const0>\;
Dbg_WDATA_19(16) <= \<const0>\;
Dbg_WDATA_19(15) <= \<const0>\;
Dbg_WDATA_19(14) <= \<const0>\;
Dbg_WDATA_19(13) <= \<const0>\;
Dbg_WDATA_19(12) <= \<const0>\;
Dbg_WDATA_19(11) <= \<const0>\;
Dbg_WDATA_19(10) <= \<const0>\;
Dbg_WDATA_19(9) <= \<const0>\;
Dbg_WDATA_19(8) <= \<const0>\;
Dbg_WDATA_19(7) <= \<const0>\;
Dbg_WDATA_19(6) <= \<const0>\;
Dbg_WDATA_19(5) <= \<const0>\;
Dbg_WDATA_19(4) <= \<const0>\;
Dbg_WDATA_19(3) <= \<const0>\;
Dbg_WDATA_19(2) <= \<const0>\;
Dbg_WDATA_19(1) <= \<const0>\;
Dbg_WDATA_19(0) <= \<const0>\;
Dbg_WDATA_2(31) <= \<const0>\;
Dbg_WDATA_2(30) <= \<const0>\;
Dbg_WDATA_2(29) <= \<const0>\;
Dbg_WDATA_2(28) <= \<const0>\;
Dbg_WDATA_2(27) <= \<const0>\;
Dbg_WDATA_2(26) <= \<const0>\;
Dbg_WDATA_2(25) <= \<const0>\;
Dbg_WDATA_2(24) <= \<const0>\;
Dbg_WDATA_2(23) <= \<const0>\;
Dbg_WDATA_2(22) <= \<const0>\;
Dbg_WDATA_2(21) <= \<const0>\;
Dbg_WDATA_2(20) <= \<const0>\;
Dbg_WDATA_2(19) <= \<const0>\;
Dbg_WDATA_2(18) <= \<const0>\;
Dbg_WDATA_2(17) <= \<const0>\;
Dbg_WDATA_2(16) <= \<const0>\;
Dbg_WDATA_2(15) <= \<const0>\;
Dbg_WDATA_2(14) <= \<const0>\;
Dbg_WDATA_2(13) <= \<const0>\;
Dbg_WDATA_2(12) <= \<const0>\;
Dbg_WDATA_2(11) <= \<const0>\;
Dbg_WDATA_2(10) <= \<const0>\;
Dbg_WDATA_2(9) <= \<const0>\;
Dbg_WDATA_2(8) <= \<const0>\;
Dbg_WDATA_2(7) <= \<const0>\;
Dbg_WDATA_2(6) <= \<const0>\;
Dbg_WDATA_2(5) <= \<const0>\;
Dbg_WDATA_2(4) <= \<const0>\;
Dbg_WDATA_2(3) <= \<const0>\;
Dbg_WDATA_2(2) <= \<const0>\;
Dbg_WDATA_2(1) <= \<const0>\;
Dbg_WDATA_2(0) <= \<const0>\;
Dbg_WDATA_20(31) <= \<const0>\;
Dbg_WDATA_20(30) <= \<const0>\;
Dbg_WDATA_20(29) <= \<const0>\;
Dbg_WDATA_20(28) <= \<const0>\;
Dbg_WDATA_20(27) <= \<const0>\;
Dbg_WDATA_20(26) <= \<const0>\;
Dbg_WDATA_20(25) <= \<const0>\;
Dbg_WDATA_20(24) <= \<const0>\;
Dbg_WDATA_20(23) <= \<const0>\;
Dbg_WDATA_20(22) <= \<const0>\;
Dbg_WDATA_20(21) <= \<const0>\;
Dbg_WDATA_20(20) <= \<const0>\;
Dbg_WDATA_20(19) <= \<const0>\;
Dbg_WDATA_20(18) <= \<const0>\;
Dbg_WDATA_20(17) <= \<const0>\;
Dbg_WDATA_20(16) <= \<const0>\;
Dbg_WDATA_20(15) <= \<const0>\;
Dbg_WDATA_20(14) <= \<const0>\;
Dbg_WDATA_20(13) <= \<const0>\;
Dbg_WDATA_20(12) <= \<const0>\;
Dbg_WDATA_20(11) <= \<const0>\;
Dbg_WDATA_20(10) <= \<const0>\;
Dbg_WDATA_20(9) <= \<const0>\;
Dbg_WDATA_20(8) <= \<const0>\;
Dbg_WDATA_20(7) <= \<const0>\;
Dbg_WDATA_20(6) <= \<const0>\;
Dbg_WDATA_20(5) <= \<const0>\;
Dbg_WDATA_20(4) <= \<const0>\;
Dbg_WDATA_20(3) <= \<const0>\;
Dbg_WDATA_20(2) <= \<const0>\;
Dbg_WDATA_20(1) <= \<const0>\;
Dbg_WDATA_20(0) <= \<const0>\;
Dbg_WDATA_21(31) <= \<const0>\;
Dbg_WDATA_21(30) <= \<const0>\;
Dbg_WDATA_21(29) <= \<const0>\;
Dbg_WDATA_21(28) <= \<const0>\;
Dbg_WDATA_21(27) <= \<const0>\;
Dbg_WDATA_21(26) <= \<const0>\;
Dbg_WDATA_21(25) <= \<const0>\;
Dbg_WDATA_21(24) <= \<const0>\;
Dbg_WDATA_21(23) <= \<const0>\;
Dbg_WDATA_21(22) <= \<const0>\;
Dbg_WDATA_21(21) <= \<const0>\;
Dbg_WDATA_21(20) <= \<const0>\;
Dbg_WDATA_21(19) <= \<const0>\;
Dbg_WDATA_21(18) <= \<const0>\;
Dbg_WDATA_21(17) <= \<const0>\;
Dbg_WDATA_21(16) <= \<const0>\;
Dbg_WDATA_21(15) <= \<const0>\;
Dbg_WDATA_21(14) <= \<const0>\;
Dbg_WDATA_21(13) <= \<const0>\;
Dbg_WDATA_21(12) <= \<const0>\;
Dbg_WDATA_21(11) <= \<const0>\;
Dbg_WDATA_21(10) <= \<const0>\;
Dbg_WDATA_21(9) <= \<const0>\;
Dbg_WDATA_21(8) <= \<const0>\;
Dbg_WDATA_21(7) <= \<const0>\;
Dbg_WDATA_21(6) <= \<const0>\;
Dbg_WDATA_21(5) <= \<const0>\;
Dbg_WDATA_21(4) <= \<const0>\;
Dbg_WDATA_21(3) <= \<const0>\;
Dbg_WDATA_21(2) <= \<const0>\;
Dbg_WDATA_21(1) <= \<const0>\;
Dbg_WDATA_21(0) <= \<const0>\;
Dbg_WDATA_22(31) <= \<const0>\;
Dbg_WDATA_22(30) <= \<const0>\;
Dbg_WDATA_22(29) <= \<const0>\;
Dbg_WDATA_22(28) <= \<const0>\;
Dbg_WDATA_22(27) <= \<const0>\;
Dbg_WDATA_22(26) <= \<const0>\;
Dbg_WDATA_22(25) <= \<const0>\;
Dbg_WDATA_22(24) <= \<const0>\;
Dbg_WDATA_22(23) <= \<const0>\;
Dbg_WDATA_22(22) <= \<const0>\;
Dbg_WDATA_22(21) <= \<const0>\;
Dbg_WDATA_22(20) <= \<const0>\;
Dbg_WDATA_22(19) <= \<const0>\;
Dbg_WDATA_22(18) <= \<const0>\;
Dbg_WDATA_22(17) <= \<const0>\;
Dbg_WDATA_22(16) <= \<const0>\;
Dbg_WDATA_22(15) <= \<const0>\;
Dbg_WDATA_22(14) <= \<const0>\;
Dbg_WDATA_22(13) <= \<const0>\;
Dbg_WDATA_22(12) <= \<const0>\;
Dbg_WDATA_22(11) <= \<const0>\;
Dbg_WDATA_22(10) <= \<const0>\;
Dbg_WDATA_22(9) <= \<const0>\;
Dbg_WDATA_22(8) <= \<const0>\;
Dbg_WDATA_22(7) <= \<const0>\;
Dbg_WDATA_22(6) <= \<const0>\;
Dbg_WDATA_22(5) <= \<const0>\;
Dbg_WDATA_22(4) <= \<const0>\;
Dbg_WDATA_22(3) <= \<const0>\;
Dbg_WDATA_22(2) <= \<const0>\;
Dbg_WDATA_22(1) <= \<const0>\;
Dbg_WDATA_22(0) <= \<const0>\;
Dbg_WDATA_23(31) <= \<const0>\;
Dbg_WDATA_23(30) <= \<const0>\;
Dbg_WDATA_23(29) <= \<const0>\;
Dbg_WDATA_23(28) <= \<const0>\;
Dbg_WDATA_23(27) <= \<const0>\;
Dbg_WDATA_23(26) <= \<const0>\;
Dbg_WDATA_23(25) <= \<const0>\;
Dbg_WDATA_23(24) <= \<const0>\;
Dbg_WDATA_23(23) <= \<const0>\;
Dbg_WDATA_23(22) <= \<const0>\;
Dbg_WDATA_23(21) <= \<const0>\;
Dbg_WDATA_23(20) <= \<const0>\;
Dbg_WDATA_23(19) <= \<const0>\;
Dbg_WDATA_23(18) <= \<const0>\;
Dbg_WDATA_23(17) <= \<const0>\;
Dbg_WDATA_23(16) <= \<const0>\;
Dbg_WDATA_23(15) <= \<const0>\;
Dbg_WDATA_23(14) <= \<const0>\;
Dbg_WDATA_23(13) <= \<const0>\;
Dbg_WDATA_23(12) <= \<const0>\;
Dbg_WDATA_23(11) <= \<const0>\;
Dbg_WDATA_23(10) <= \<const0>\;
Dbg_WDATA_23(9) <= \<const0>\;
Dbg_WDATA_23(8) <= \<const0>\;
Dbg_WDATA_23(7) <= \<const0>\;
Dbg_WDATA_23(6) <= \<const0>\;
Dbg_WDATA_23(5) <= \<const0>\;
Dbg_WDATA_23(4) <= \<const0>\;
Dbg_WDATA_23(3) <= \<const0>\;
Dbg_WDATA_23(2) <= \<const0>\;
Dbg_WDATA_23(1) <= \<const0>\;
Dbg_WDATA_23(0) <= \<const0>\;
Dbg_WDATA_24(31) <= \<const0>\;
Dbg_WDATA_24(30) <= \<const0>\;
Dbg_WDATA_24(29) <= \<const0>\;
Dbg_WDATA_24(28) <= \<const0>\;
Dbg_WDATA_24(27) <= \<const0>\;
Dbg_WDATA_24(26) <= \<const0>\;
Dbg_WDATA_24(25) <= \<const0>\;
Dbg_WDATA_24(24) <= \<const0>\;
Dbg_WDATA_24(23) <= \<const0>\;
Dbg_WDATA_24(22) <= \<const0>\;
Dbg_WDATA_24(21) <= \<const0>\;
Dbg_WDATA_24(20) <= \<const0>\;
Dbg_WDATA_24(19) <= \<const0>\;
Dbg_WDATA_24(18) <= \<const0>\;
Dbg_WDATA_24(17) <= \<const0>\;
Dbg_WDATA_24(16) <= \<const0>\;
Dbg_WDATA_24(15) <= \<const0>\;
Dbg_WDATA_24(14) <= \<const0>\;
Dbg_WDATA_24(13) <= \<const0>\;
Dbg_WDATA_24(12) <= \<const0>\;
Dbg_WDATA_24(11) <= \<const0>\;
Dbg_WDATA_24(10) <= \<const0>\;
Dbg_WDATA_24(9) <= \<const0>\;
Dbg_WDATA_24(8) <= \<const0>\;
Dbg_WDATA_24(7) <= \<const0>\;
Dbg_WDATA_24(6) <= \<const0>\;
Dbg_WDATA_24(5) <= \<const0>\;
Dbg_WDATA_24(4) <= \<const0>\;
Dbg_WDATA_24(3) <= \<const0>\;
Dbg_WDATA_24(2) <= \<const0>\;
Dbg_WDATA_24(1) <= \<const0>\;
Dbg_WDATA_24(0) <= \<const0>\;
Dbg_WDATA_25(31) <= \<const0>\;
Dbg_WDATA_25(30) <= \<const0>\;
Dbg_WDATA_25(29) <= \<const0>\;
Dbg_WDATA_25(28) <= \<const0>\;
Dbg_WDATA_25(27) <= \<const0>\;
Dbg_WDATA_25(26) <= \<const0>\;
Dbg_WDATA_25(25) <= \<const0>\;
Dbg_WDATA_25(24) <= \<const0>\;
Dbg_WDATA_25(23) <= \<const0>\;
Dbg_WDATA_25(22) <= \<const0>\;
Dbg_WDATA_25(21) <= \<const0>\;
Dbg_WDATA_25(20) <= \<const0>\;
Dbg_WDATA_25(19) <= \<const0>\;
Dbg_WDATA_25(18) <= \<const0>\;
Dbg_WDATA_25(17) <= \<const0>\;
Dbg_WDATA_25(16) <= \<const0>\;
Dbg_WDATA_25(15) <= \<const0>\;
Dbg_WDATA_25(14) <= \<const0>\;
Dbg_WDATA_25(13) <= \<const0>\;
Dbg_WDATA_25(12) <= \<const0>\;
Dbg_WDATA_25(11) <= \<const0>\;
Dbg_WDATA_25(10) <= \<const0>\;
Dbg_WDATA_25(9) <= \<const0>\;
Dbg_WDATA_25(8) <= \<const0>\;
Dbg_WDATA_25(7) <= \<const0>\;
Dbg_WDATA_25(6) <= \<const0>\;
Dbg_WDATA_25(5) <= \<const0>\;
Dbg_WDATA_25(4) <= \<const0>\;
Dbg_WDATA_25(3) <= \<const0>\;
Dbg_WDATA_25(2) <= \<const0>\;
Dbg_WDATA_25(1) <= \<const0>\;
Dbg_WDATA_25(0) <= \<const0>\;
Dbg_WDATA_26(31) <= \<const0>\;
Dbg_WDATA_26(30) <= \<const0>\;
Dbg_WDATA_26(29) <= \<const0>\;
Dbg_WDATA_26(28) <= \<const0>\;
Dbg_WDATA_26(27) <= \<const0>\;
Dbg_WDATA_26(26) <= \<const0>\;
Dbg_WDATA_26(25) <= \<const0>\;
Dbg_WDATA_26(24) <= \<const0>\;
Dbg_WDATA_26(23) <= \<const0>\;
Dbg_WDATA_26(22) <= \<const0>\;
Dbg_WDATA_26(21) <= \<const0>\;
Dbg_WDATA_26(20) <= \<const0>\;
Dbg_WDATA_26(19) <= \<const0>\;
Dbg_WDATA_26(18) <= \<const0>\;
Dbg_WDATA_26(17) <= \<const0>\;
Dbg_WDATA_26(16) <= \<const0>\;
Dbg_WDATA_26(15) <= \<const0>\;
Dbg_WDATA_26(14) <= \<const0>\;
Dbg_WDATA_26(13) <= \<const0>\;
Dbg_WDATA_26(12) <= \<const0>\;
Dbg_WDATA_26(11) <= \<const0>\;
Dbg_WDATA_26(10) <= \<const0>\;
Dbg_WDATA_26(9) <= \<const0>\;
Dbg_WDATA_26(8) <= \<const0>\;
Dbg_WDATA_26(7) <= \<const0>\;
Dbg_WDATA_26(6) <= \<const0>\;
Dbg_WDATA_26(5) <= \<const0>\;
Dbg_WDATA_26(4) <= \<const0>\;
Dbg_WDATA_26(3) <= \<const0>\;
Dbg_WDATA_26(2) <= \<const0>\;
Dbg_WDATA_26(1) <= \<const0>\;
Dbg_WDATA_26(0) <= \<const0>\;
Dbg_WDATA_27(31) <= \<const0>\;
Dbg_WDATA_27(30) <= \<const0>\;
Dbg_WDATA_27(29) <= \<const0>\;
Dbg_WDATA_27(28) <= \<const0>\;
Dbg_WDATA_27(27) <= \<const0>\;
Dbg_WDATA_27(26) <= \<const0>\;
Dbg_WDATA_27(25) <= \<const0>\;
Dbg_WDATA_27(24) <= \<const0>\;
Dbg_WDATA_27(23) <= \<const0>\;
Dbg_WDATA_27(22) <= \<const0>\;
Dbg_WDATA_27(21) <= \<const0>\;
Dbg_WDATA_27(20) <= \<const0>\;
Dbg_WDATA_27(19) <= \<const0>\;
Dbg_WDATA_27(18) <= \<const0>\;
Dbg_WDATA_27(17) <= \<const0>\;
Dbg_WDATA_27(16) <= \<const0>\;
Dbg_WDATA_27(15) <= \<const0>\;
Dbg_WDATA_27(14) <= \<const0>\;
Dbg_WDATA_27(13) <= \<const0>\;
Dbg_WDATA_27(12) <= \<const0>\;
Dbg_WDATA_27(11) <= \<const0>\;
Dbg_WDATA_27(10) <= \<const0>\;
Dbg_WDATA_27(9) <= \<const0>\;
Dbg_WDATA_27(8) <= \<const0>\;
Dbg_WDATA_27(7) <= \<const0>\;
Dbg_WDATA_27(6) <= \<const0>\;
Dbg_WDATA_27(5) <= \<const0>\;
Dbg_WDATA_27(4) <= \<const0>\;
Dbg_WDATA_27(3) <= \<const0>\;
Dbg_WDATA_27(2) <= \<const0>\;
Dbg_WDATA_27(1) <= \<const0>\;
Dbg_WDATA_27(0) <= \<const0>\;
Dbg_WDATA_28(31) <= \<const0>\;
Dbg_WDATA_28(30) <= \<const0>\;
Dbg_WDATA_28(29) <= \<const0>\;
Dbg_WDATA_28(28) <= \<const0>\;
Dbg_WDATA_28(27) <= \<const0>\;
Dbg_WDATA_28(26) <= \<const0>\;
Dbg_WDATA_28(25) <= \<const0>\;
Dbg_WDATA_28(24) <= \<const0>\;
Dbg_WDATA_28(23) <= \<const0>\;
Dbg_WDATA_28(22) <= \<const0>\;
Dbg_WDATA_28(21) <= \<const0>\;
Dbg_WDATA_28(20) <= \<const0>\;
Dbg_WDATA_28(19) <= \<const0>\;
Dbg_WDATA_28(18) <= \<const0>\;
Dbg_WDATA_28(17) <= \<const0>\;
Dbg_WDATA_28(16) <= \<const0>\;
Dbg_WDATA_28(15) <= \<const0>\;
Dbg_WDATA_28(14) <= \<const0>\;
Dbg_WDATA_28(13) <= \<const0>\;
Dbg_WDATA_28(12) <= \<const0>\;
Dbg_WDATA_28(11) <= \<const0>\;
Dbg_WDATA_28(10) <= \<const0>\;
Dbg_WDATA_28(9) <= \<const0>\;
Dbg_WDATA_28(8) <= \<const0>\;
Dbg_WDATA_28(7) <= \<const0>\;
Dbg_WDATA_28(6) <= \<const0>\;
Dbg_WDATA_28(5) <= \<const0>\;
Dbg_WDATA_28(4) <= \<const0>\;
Dbg_WDATA_28(3) <= \<const0>\;
Dbg_WDATA_28(2) <= \<const0>\;
Dbg_WDATA_28(1) <= \<const0>\;
Dbg_WDATA_28(0) <= \<const0>\;
Dbg_WDATA_29(31) <= \<const0>\;
Dbg_WDATA_29(30) <= \<const0>\;
Dbg_WDATA_29(29) <= \<const0>\;
Dbg_WDATA_29(28) <= \<const0>\;
Dbg_WDATA_29(27) <= \<const0>\;
Dbg_WDATA_29(26) <= \<const0>\;
Dbg_WDATA_29(25) <= \<const0>\;
Dbg_WDATA_29(24) <= \<const0>\;
Dbg_WDATA_29(23) <= \<const0>\;
Dbg_WDATA_29(22) <= \<const0>\;
Dbg_WDATA_29(21) <= \<const0>\;
Dbg_WDATA_29(20) <= \<const0>\;
Dbg_WDATA_29(19) <= \<const0>\;
Dbg_WDATA_29(18) <= \<const0>\;
Dbg_WDATA_29(17) <= \<const0>\;
Dbg_WDATA_29(16) <= \<const0>\;
Dbg_WDATA_29(15) <= \<const0>\;
Dbg_WDATA_29(14) <= \<const0>\;
Dbg_WDATA_29(13) <= \<const0>\;
Dbg_WDATA_29(12) <= \<const0>\;
Dbg_WDATA_29(11) <= \<const0>\;
Dbg_WDATA_29(10) <= \<const0>\;
Dbg_WDATA_29(9) <= \<const0>\;
Dbg_WDATA_29(8) <= \<const0>\;
Dbg_WDATA_29(7) <= \<const0>\;
Dbg_WDATA_29(6) <= \<const0>\;
Dbg_WDATA_29(5) <= \<const0>\;
Dbg_WDATA_29(4) <= \<const0>\;
Dbg_WDATA_29(3) <= \<const0>\;
Dbg_WDATA_29(2) <= \<const0>\;
Dbg_WDATA_29(1) <= \<const0>\;
Dbg_WDATA_29(0) <= \<const0>\;
Dbg_WDATA_3(31) <= \<const0>\;
Dbg_WDATA_3(30) <= \<const0>\;
Dbg_WDATA_3(29) <= \<const0>\;
Dbg_WDATA_3(28) <= \<const0>\;
Dbg_WDATA_3(27) <= \<const0>\;
Dbg_WDATA_3(26) <= \<const0>\;
Dbg_WDATA_3(25) <= \<const0>\;
Dbg_WDATA_3(24) <= \<const0>\;
Dbg_WDATA_3(23) <= \<const0>\;
Dbg_WDATA_3(22) <= \<const0>\;
Dbg_WDATA_3(21) <= \<const0>\;
Dbg_WDATA_3(20) <= \<const0>\;
Dbg_WDATA_3(19) <= \<const0>\;
Dbg_WDATA_3(18) <= \<const0>\;
Dbg_WDATA_3(17) <= \<const0>\;
Dbg_WDATA_3(16) <= \<const0>\;
Dbg_WDATA_3(15) <= \<const0>\;
Dbg_WDATA_3(14) <= \<const0>\;
Dbg_WDATA_3(13) <= \<const0>\;
Dbg_WDATA_3(12) <= \<const0>\;
Dbg_WDATA_3(11) <= \<const0>\;
Dbg_WDATA_3(10) <= \<const0>\;
Dbg_WDATA_3(9) <= \<const0>\;
Dbg_WDATA_3(8) <= \<const0>\;
Dbg_WDATA_3(7) <= \<const0>\;
Dbg_WDATA_3(6) <= \<const0>\;
Dbg_WDATA_3(5) <= \<const0>\;
Dbg_WDATA_3(4) <= \<const0>\;
Dbg_WDATA_3(3) <= \<const0>\;
Dbg_WDATA_3(2) <= \<const0>\;
Dbg_WDATA_3(1) <= \<const0>\;
Dbg_WDATA_3(0) <= \<const0>\;
Dbg_WDATA_30(31) <= \<const0>\;
Dbg_WDATA_30(30) <= \<const0>\;
Dbg_WDATA_30(29) <= \<const0>\;
Dbg_WDATA_30(28) <= \<const0>\;
Dbg_WDATA_30(27) <= \<const0>\;
Dbg_WDATA_30(26) <= \<const0>\;
Dbg_WDATA_30(25) <= \<const0>\;
Dbg_WDATA_30(24) <= \<const0>\;
Dbg_WDATA_30(23) <= \<const0>\;
Dbg_WDATA_30(22) <= \<const0>\;
Dbg_WDATA_30(21) <= \<const0>\;
Dbg_WDATA_30(20) <= \<const0>\;
Dbg_WDATA_30(19) <= \<const0>\;
Dbg_WDATA_30(18) <= \<const0>\;
Dbg_WDATA_30(17) <= \<const0>\;
Dbg_WDATA_30(16) <= \<const0>\;
Dbg_WDATA_30(15) <= \<const0>\;
Dbg_WDATA_30(14) <= \<const0>\;
Dbg_WDATA_30(13) <= \<const0>\;
Dbg_WDATA_30(12) <= \<const0>\;
Dbg_WDATA_30(11) <= \<const0>\;
Dbg_WDATA_30(10) <= \<const0>\;
Dbg_WDATA_30(9) <= \<const0>\;
Dbg_WDATA_30(8) <= \<const0>\;
Dbg_WDATA_30(7) <= \<const0>\;
Dbg_WDATA_30(6) <= \<const0>\;
Dbg_WDATA_30(5) <= \<const0>\;
Dbg_WDATA_30(4) <= \<const0>\;
Dbg_WDATA_30(3) <= \<const0>\;
Dbg_WDATA_30(2) <= \<const0>\;
Dbg_WDATA_30(1) <= \<const0>\;
Dbg_WDATA_30(0) <= \<const0>\;
Dbg_WDATA_31(31) <= \<const0>\;
Dbg_WDATA_31(30) <= \<const0>\;
Dbg_WDATA_31(29) <= \<const0>\;
Dbg_WDATA_31(28) <= \<const0>\;
Dbg_WDATA_31(27) <= \<const0>\;
Dbg_WDATA_31(26) <= \<const0>\;
Dbg_WDATA_31(25) <= \<const0>\;
Dbg_WDATA_31(24) <= \<const0>\;
Dbg_WDATA_31(23) <= \<const0>\;
Dbg_WDATA_31(22) <= \<const0>\;
Dbg_WDATA_31(21) <= \<const0>\;
Dbg_WDATA_31(20) <= \<const0>\;
Dbg_WDATA_31(19) <= \<const0>\;
Dbg_WDATA_31(18) <= \<const0>\;
Dbg_WDATA_31(17) <= \<const0>\;
Dbg_WDATA_31(16) <= \<const0>\;
Dbg_WDATA_31(15) <= \<const0>\;
Dbg_WDATA_31(14) <= \<const0>\;
Dbg_WDATA_31(13) <= \<const0>\;
Dbg_WDATA_31(12) <= \<const0>\;
Dbg_WDATA_31(11) <= \<const0>\;
Dbg_WDATA_31(10) <= \<const0>\;
Dbg_WDATA_31(9) <= \<const0>\;
Dbg_WDATA_31(8) <= \<const0>\;
Dbg_WDATA_31(7) <= \<const0>\;
Dbg_WDATA_31(6) <= \<const0>\;
Dbg_WDATA_31(5) <= \<const0>\;
Dbg_WDATA_31(4) <= \<const0>\;
Dbg_WDATA_31(3) <= \<const0>\;
Dbg_WDATA_31(2) <= \<const0>\;
Dbg_WDATA_31(1) <= \<const0>\;
Dbg_WDATA_31(0) <= \<const0>\;
Dbg_WDATA_4(31) <= \<const0>\;
Dbg_WDATA_4(30) <= \<const0>\;
Dbg_WDATA_4(29) <= \<const0>\;
Dbg_WDATA_4(28) <= \<const0>\;
Dbg_WDATA_4(27) <= \<const0>\;
Dbg_WDATA_4(26) <= \<const0>\;
Dbg_WDATA_4(25) <= \<const0>\;
Dbg_WDATA_4(24) <= \<const0>\;
Dbg_WDATA_4(23) <= \<const0>\;
Dbg_WDATA_4(22) <= \<const0>\;
Dbg_WDATA_4(21) <= \<const0>\;
Dbg_WDATA_4(20) <= \<const0>\;
Dbg_WDATA_4(19) <= \<const0>\;
Dbg_WDATA_4(18) <= \<const0>\;
Dbg_WDATA_4(17) <= \<const0>\;
Dbg_WDATA_4(16) <= \<const0>\;
Dbg_WDATA_4(15) <= \<const0>\;
Dbg_WDATA_4(14) <= \<const0>\;
Dbg_WDATA_4(13) <= \<const0>\;
Dbg_WDATA_4(12) <= \<const0>\;
Dbg_WDATA_4(11) <= \<const0>\;
Dbg_WDATA_4(10) <= \<const0>\;
Dbg_WDATA_4(9) <= \<const0>\;
Dbg_WDATA_4(8) <= \<const0>\;
Dbg_WDATA_4(7) <= \<const0>\;
Dbg_WDATA_4(6) <= \<const0>\;
Dbg_WDATA_4(5) <= \<const0>\;
Dbg_WDATA_4(4) <= \<const0>\;
Dbg_WDATA_4(3) <= \<const0>\;
Dbg_WDATA_4(2) <= \<const0>\;
Dbg_WDATA_4(1) <= \<const0>\;
Dbg_WDATA_4(0) <= \<const0>\;
Dbg_WDATA_5(31) <= \<const0>\;
Dbg_WDATA_5(30) <= \<const0>\;
Dbg_WDATA_5(29) <= \<const0>\;
Dbg_WDATA_5(28) <= \<const0>\;
Dbg_WDATA_5(27) <= \<const0>\;
Dbg_WDATA_5(26) <= \<const0>\;
Dbg_WDATA_5(25) <= \<const0>\;
Dbg_WDATA_5(24) <= \<const0>\;
Dbg_WDATA_5(23) <= \<const0>\;
Dbg_WDATA_5(22) <= \<const0>\;
Dbg_WDATA_5(21) <= \<const0>\;
Dbg_WDATA_5(20) <= \<const0>\;
Dbg_WDATA_5(19) <= \<const0>\;
Dbg_WDATA_5(18) <= \<const0>\;
Dbg_WDATA_5(17) <= \<const0>\;
Dbg_WDATA_5(16) <= \<const0>\;
Dbg_WDATA_5(15) <= \<const0>\;
Dbg_WDATA_5(14) <= \<const0>\;
Dbg_WDATA_5(13) <= \<const0>\;
Dbg_WDATA_5(12) <= \<const0>\;
Dbg_WDATA_5(11) <= \<const0>\;
Dbg_WDATA_5(10) <= \<const0>\;
Dbg_WDATA_5(9) <= \<const0>\;
Dbg_WDATA_5(8) <= \<const0>\;
Dbg_WDATA_5(7) <= \<const0>\;
Dbg_WDATA_5(6) <= \<const0>\;
Dbg_WDATA_5(5) <= \<const0>\;
Dbg_WDATA_5(4) <= \<const0>\;
Dbg_WDATA_5(3) <= \<const0>\;
Dbg_WDATA_5(2) <= \<const0>\;
Dbg_WDATA_5(1) <= \<const0>\;
Dbg_WDATA_5(0) <= \<const0>\;
Dbg_WDATA_6(31) <= \<const0>\;
Dbg_WDATA_6(30) <= \<const0>\;
Dbg_WDATA_6(29) <= \<const0>\;
Dbg_WDATA_6(28) <= \<const0>\;
Dbg_WDATA_6(27) <= \<const0>\;
Dbg_WDATA_6(26) <= \<const0>\;
Dbg_WDATA_6(25) <= \<const0>\;
Dbg_WDATA_6(24) <= \<const0>\;
Dbg_WDATA_6(23) <= \<const0>\;
Dbg_WDATA_6(22) <= \<const0>\;
Dbg_WDATA_6(21) <= \<const0>\;
Dbg_WDATA_6(20) <= \<const0>\;
Dbg_WDATA_6(19) <= \<const0>\;
Dbg_WDATA_6(18) <= \<const0>\;
Dbg_WDATA_6(17) <= \<const0>\;
Dbg_WDATA_6(16) <= \<const0>\;
Dbg_WDATA_6(15) <= \<const0>\;
Dbg_WDATA_6(14) <= \<const0>\;
Dbg_WDATA_6(13) <= \<const0>\;
Dbg_WDATA_6(12) <= \<const0>\;
Dbg_WDATA_6(11) <= \<const0>\;
Dbg_WDATA_6(10) <= \<const0>\;
Dbg_WDATA_6(9) <= \<const0>\;
Dbg_WDATA_6(8) <= \<const0>\;
Dbg_WDATA_6(7) <= \<const0>\;
Dbg_WDATA_6(6) <= \<const0>\;
Dbg_WDATA_6(5) <= \<const0>\;
Dbg_WDATA_6(4) <= \<const0>\;
Dbg_WDATA_6(3) <= \<const0>\;
Dbg_WDATA_6(2) <= \<const0>\;
Dbg_WDATA_6(1) <= \<const0>\;
Dbg_WDATA_6(0) <= \<const0>\;
Dbg_WDATA_7(31) <= \<const0>\;
Dbg_WDATA_7(30) <= \<const0>\;
Dbg_WDATA_7(29) <= \<const0>\;
Dbg_WDATA_7(28) <= \<const0>\;
Dbg_WDATA_7(27) <= \<const0>\;
Dbg_WDATA_7(26) <= \<const0>\;
Dbg_WDATA_7(25) <= \<const0>\;
Dbg_WDATA_7(24) <= \<const0>\;
Dbg_WDATA_7(23) <= \<const0>\;
Dbg_WDATA_7(22) <= \<const0>\;
Dbg_WDATA_7(21) <= \<const0>\;
Dbg_WDATA_7(20) <= \<const0>\;
Dbg_WDATA_7(19) <= \<const0>\;
Dbg_WDATA_7(18) <= \<const0>\;
Dbg_WDATA_7(17) <= \<const0>\;
Dbg_WDATA_7(16) <= \<const0>\;
Dbg_WDATA_7(15) <= \<const0>\;
Dbg_WDATA_7(14) <= \<const0>\;
Dbg_WDATA_7(13) <= \<const0>\;
Dbg_WDATA_7(12) <= \<const0>\;
Dbg_WDATA_7(11) <= \<const0>\;
Dbg_WDATA_7(10) <= \<const0>\;
Dbg_WDATA_7(9) <= \<const0>\;
Dbg_WDATA_7(8) <= \<const0>\;
Dbg_WDATA_7(7) <= \<const0>\;
Dbg_WDATA_7(6) <= \<const0>\;
Dbg_WDATA_7(5) <= \<const0>\;
Dbg_WDATA_7(4) <= \<const0>\;
Dbg_WDATA_7(3) <= \<const0>\;
Dbg_WDATA_7(2) <= \<const0>\;
Dbg_WDATA_7(1) <= \<const0>\;
Dbg_WDATA_7(0) <= \<const0>\;
Dbg_WDATA_8(31) <= \<const0>\;
Dbg_WDATA_8(30) <= \<const0>\;
Dbg_WDATA_8(29) <= \<const0>\;
Dbg_WDATA_8(28) <= \<const0>\;
Dbg_WDATA_8(27) <= \<const0>\;
Dbg_WDATA_8(26) <= \<const0>\;
Dbg_WDATA_8(25) <= \<const0>\;
Dbg_WDATA_8(24) <= \<const0>\;
Dbg_WDATA_8(23) <= \<const0>\;
Dbg_WDATA_8(22) <= \<const0>\;
Dbg_WDATA_8(21) <= \<const0>\;
Dbg_WDATA_8(20) <= \<const0>\;
Dbg_WDATA_8(19) <= \<const0>\;
Dbg_WDATA_8(18) <= \<const0>\;
Dbg_WDATA_8(17) <= \<const0>\;
Dbg_WDATA_8(16) <= \<const0>\;
Dbg_WDATA_8(15) <= \<const0>\;
Dbg_WDATA_8(14) <= \<const0>\;
Dbg_WDATA_8(13) <= \<const0>\;
Dbg_WDATA_8(12) <= \<const0>\;
Dbg_WDATA_8(11) <= \<const0>\;
Dbg_WDATA_8(10) <= \<const0>\;
Dbg_WDATA_8(9) <= \<const0>\;
Dbg_WDATA_8(8) <= \<const0>\;
Dbg_WDATA_8(7) <= \<const0>\;
Dbg_WDATA_8(6) <= \<const0>\;
Dbg_WDATA_8(5) <= \<const0>\;
Dbg_WDATA_8(4) <= \<const0>\;
Dbg_WDATA_8(3) <= \<const0>\;
Dbg_WDATA_8(2) <= \<const0>\;
Dbg_WDATA_8(1) <= \<const0>\;
Dbg_WDATA_8(0) <= \<const0>\;
Dbg_WDATA_9(31) <= \<const0>\;
Dbg_WDATA_9(30) <= \<const0>\;
Dbg_WDATA_9(29) <= \<const0>\;
Dbg_WDATA_9(28) <= \<const0>\;
Dbg_WDATA_9(27) <= \<const0>\;
Dbg_WDATA_9(26) <= \<const0>\;
Dbg_WDATA_9(25) <= \<const0>\;
Dbg_WDATA_9(24) <= \<const0>\;
Dbg_WDATA_9(23) <= \<const0>\;
Dbg_WDATA_9(22) <= \<const0>\;
Dbg_WDATA_9(21) <= \<const0>\;
Dbg_WDATA_9(20) <= \<const0>\;
Dbg_WDATA_9(19) <= \<const0>\;
Dbg_WDATA_9(18) <= \<const0>\;
Dbg_WDATA_9(17) <= \<const0>\;
Dbg_WDATA_9(16) <= \<const0>\;
Dbg_WDATA_9(15) <= \<const0>\;
Dbg_WDATA_9(14) <= \<const0>\;
Dbg_WDATA_9(13) <= \<const0>\;
Dbg_WDATA_9(12) <= \<const0>\;
Dbg_WDATA_9(11) <= \<const0>\;
Dbg_WDATA_9(10) <= \<const0>\;
Dbg_WDATA_9(9) <= \<const0>\;
Dbg_WDATA_9(8) <= \<const0>\;
Dbg_WDATA_9(7) <= \<const0>\;
Dbg_WDATA_9(6) <= \<const0>\;
Dbg_WDATA_9(5) <= \<const0>\;
Dbg_WDATA_9(4) <= \<const0>\;
Dbg_WDATA_9(3) <= \<const0>\;
Dbg_WDATA_9(2) <= \<const0>\;
Dbg_WDATA_9(1) <= \<const0>\;
Dbg_WDATA_9(0) <= \<const0>\;
Dbg_WVALID_0 <= \<const0>\;
Dbg_WVALID_1 <= \<const0>\;
Dbg_WVALID_10 <= \<const0>\;
Dbg_WVALID_11 <= \<const0>\;
Dbg_WVALID_12 <= \<const0>\;
Dbg_WVALID_13 <= \<const0>\;
Dbg_WVALID_14 <= \<const0>\;
Dbg_WVALID_15 <= \<const0>\;
Dbg_WVALID_16 <= \<const0>\;
Dbg_WVALID_17 <= \<const0>\;
Dbg_WVALID_18 <= \<const0>\;
Dbg_WVALID_19 <= \<const0>\;
Dbg_WVALID_2 <= \<const0>\;
Dbg_WVALID_20 <= \<const0>\;
Dbg_WVALID_21 <= \<const0>\;
Dbg_WVALID_22 <= \<const0>\;
Dbg_WVALID_23 <= \<const0>\;
Dbg_WVALID_24 <= \<const0>\;
Dbg_WVALID_25 <= \<const0>\;
Dbg_WVALID_26 <= \<const0>\;
Dbg_WVALID_27 <= \<const0>\;
Dbg_WVALID_28 <= \<const0>\;
Dbg_WVALID_29 <= \<const0>\;
Dbg_WVALID_3 <= \<const0>\;
Dbg_WVALID_30 <= \<const0>\;
Dbg_WVALID_31 <= \<const0>\;
Dbg_WVALID_4 <= \<const0>\;
Dbg_WVALID_5 <= \<const0>\;
Dbg_WVALID_6 <= \<const0>\;
Dbg_WVALID_7 <= \<const0>\;
Dbg_WVALID_8 <= \<const0>\;
Dbg_WVALID_9 <= \<const0>\;
Ext_BRK <= \<const0>\;
Ext_JTAG_CAPTURE <= \^ext_jtag_capture\;
Ext_JTAG_DRCK <= \^dbg_clk_31\;
Ext_JTAG_SHIFT <= \^ext_jtag_shift\;
Ext_JTAG_TDI <= \^ext_jtag_tdi\;
Ext_JTAG_UPDATE <= \^dbg_update_31\;
Interrupt <= \<const0>\;
LMB_Addr_Strobe_0 <= \<const0>\;
LMB_Addr_Strobe_1 <= \<const0>\;
LMB_Addr_Strobe_10 <= \<const0>\;
LMB_Addr_Strobe_11 <= \<const0>\;
LMB_Addr_Strobe_12 <= \<const0>\;
LMB_Addr_Strobe_13 <= \<const0>\;
LMB_Addr_Strobe_14 <= \<const0>\;
LMB_Addr_Strobe_15 <= \<const0>\;
LMB_Addr_Strobe_16 <= \<const0>\;
LMB_Addr_Strobe_17 <= \<const0>\;
LMB_Addr_Strobe_18 <= \<const0>\;
LMB_Addr_Strobe_19 <= \<const0>\;
LMB_Addr_Strobe_2 <= \<const0>\;
LMB_Addr_Strobe_20 <= \<const0>\;
LMB_Addr_Strobe_21 <= \<const0>\;
LMB_Addr_Strobe_22 <= \<const0>\;
LMB_Addr_Strobe_23 <= \<const0>\;
LMB_Addr_Strobe_24 <= \<const0>\;
LMB_Addr_Strobe_25 <= \<const0>\;
LMB_Addr_Strobe_26 <= \<const0>\;
LMB_Addr_Strobe_27 <= \<const0>\;
LMB_Addr_Strobe_28 <= \<const0>\;
LMB_Addr_Strobe_29 <= \<const0>\;
LMB_Addr_Strobe_3 <= \<const0>\;
LMB_Addr_Strobe_30 <= \<const0>\;
LMB_Addr_Strobe_31 <= \<const0>\;
LMB_Addr_Strobe_4 <= \<const0>\;
LMB_Addr_Strobe_5 <= \<const0>\;
LMB_Addr_Strobe_6 <= \<const0>\;
LMB_Addr_Strobe_7 <= \<const0>\;
LMB_Addr_Strobe_8 <= \<const0>\;
LMB_Addr_Strobe_9 <= \<const0>\;
LMB_Byte_Enable_0(0) <= \<const0>\;
LMB_Byte_Enable_0(1) <= \<const0>\;
LMB_Byte_Enable_0(2) <= \<const0>\;
LMB_Byte_Enable_0(3) <= \<const0>\;
LMB_Byte_Enable_1(0) <= \<const0>\;
LMB_Byte_Enable_1(1) <= \<const0>\;
LMB_Byte_Enable_1(2) <= \<const0>\;
LMB_Byte_Enable_1(3) <= \<const0>\;
LMB_Byte_Enable_10(0) <= \<const0>\;
LMB_Byte_Enable_10(1) <= \<const0>\;
LMB_Byte_Enable_10(2) <= \<const0>\;
LMB_Byte_Enable_10(3) <= \<const0>\;
LMB_Byte_Enable_11(0) <= \<const0>\;
LMB_Byte_Enable_11(1) <= \<const0>\;
LMB_Byte_Enable_11(2) <= \<const0>\;
LMB_Byte_Enable_11(3) <= \<const0>\;
LMB_Byte_Enable_12(0) <= \<const0>\;
LMB_Byte_Enable_12(1) <= \<const0>\;
LMB_Byte_Enable_12(2) <= \<const0>\;
LMB_Byte_Enable_12(3) <= \<const0>\;
LMB_Byte_Enable_13(0) <= \<const0>\;
LMB_Byte_Enable_13(1) <= \<const0>\;
LMB_Byte_Enable_13(2) <= \<const0>\;
LMB_Byte_Enable_13(3) <= \<const0>\;
LMB_Byte_Enable_14(0) <= \<const0>\;
LMB_Byte_Enable_14(1) <= \<const0>\;
LMB_Byte_Enable_14(2) <= \<const0>\;
LMB_Byte_Enable_14(3) <= \<const0>\;
LMB_Byte_Enable_15(0) <= \<const0>\;
LMB_Byte_Enable_15(1) <= \<const0>\;
LMB_Byte_Enable_15(2) <= \<const0>\;
LMB_Byte_Enable_15(3) <= \<const0>\;
LMB_Byte_Enable_16(0) <= \<const0>\;
LMB_Byte_Enable_16(1) <= \<const0>\;
LMB_Byte_Enable_16(2) <= \<const0>\;
LMB_Byte_Enable_16(3) <= \<const0>\;
LMB_Byte_Enable_17(0) <= \<const0>\;
LMB_Byte_Enable_17(1) <= \<const0>\;
LMB_Byte_Enable_17(2) <= \<const0>\;
LMB_Byte_Enable_17(3) <= \<const0>\;
LMB_Byte_Enable_18(0) <= \<const0>\;
LMB_Byte_Enable_18(1) <= \<const0>\;
LMB_Byte_Enable_18(2) <= \<const0>\;
LMB_Byte_Enable_18(3) <= \<const0>\;
LMB_Byte_Enable_19(0) <= \<const0>\;
LMB_Byte_Enable_19(1) <= \<const0>\;
LMB_Byte_Enable_19(2) <= \<const0>\;
LMB_Byte_Enable_19(3) <= \<const0>\;
LMB_Byte_Enable_2(0) <= \<const0>\;
LMB_Byte_Enable_2(1) <= \<const0>\;
LMB_Byte_Enable_2(2) <= \<const0>\;
LMB_Byte_Enable_2(3) <= \<const0>\;
LMB_Byte_Enable_20(0) <= \<const0>\;
LMB_Byte_Enable_20(1) <= \<const0>\;
LMB_Byte_Enable_20(2) <= \<const0>\;
LMB_Byte_Enable_20(3) <= \<const0>\;
LMB_Byte_Enable_21(0) <= \<const0>\;
LMB_Byte_Enable_21(1) <= \<const0>\;
LMB_Byte_Enable_21(2) <= \<const0>\;
LMB_Byte_Enable_21(3) <= \<const0>\;
LMB_Byte_Enable_22(0) <= \<const0>\;
LMB_Byte_Enable_22(1) <= \<const0>\;
LMB_Byte_Enable_22(2) <= \<const0>\;
LMB_Byte_Enable_22(3) <= \<const0>\;
LMB_Byte_Enable_23(0) <= \<const0>\;
LMB_Byte_Enable_23(1) <= \<const0>\;
LMB_Byte_Enable_23(2) <= \<const0>\;
LMB_Byte_Enable_23(3) <= \<const0>\;
LMB_Byte_Enable_24(0) <= \<const0>\;
LMB_Byte_Enable_24(1) <= \<const0>\;
LMB_Byte_Enable_24(2) <= \<const0>\;
LMB_Byte_Enable_24(3) <= \<const0>\;
LMB_Byte_Enable_25(0) <= \<const0>\;
LMB_Byte_Enable_25(1) <= \<const0>\;
LMB_Byte_Enable_25(2) <= \<const0>\;
LMB_Byte_Enable_25(3) <= \<const0>\;
LMB_Byte_Enable_26(0) <= \<const0>\;
LMB_Byte_Enable_26(1) <= \<const0>\;
LMB_Byte_Enable_26(2) <= \<const0>\;
LMB_Byte_Enable_26(3) <= \<const0>\;
LMB_Byte_Enable_27(0) <= \<const0>\;
LMB_Byte_Enable_27(1) <= \<const0>\;
LMB_Byte_Enable_27(2) <= \<const0>\;
LMB_Byte_Enable_27(3) <= \<const0>\;
LMB_Byte_Enable_28(0) <= \<const0>\;
LMB_Byte_Enable_28(1) <= \<const0>\;
LMB_Byte_Enable_28(2) <= \<const0>\;
LMB_Byte_Enable_28(3) <= \<const0>\;
LMB_Byte_Enable_29(0) <= \<const0>\;
LMB_Byte_Enable_29(1) <= \<const0>\;
LMB_Byte_Enable_29(2) <= \<const0>\;
LMB_Byte_Enable_29(3) <= \<const0>\;
LMB_Byte_Enable_3(0) <= \<const0>\;
LMB_Byte_Enable_3(1) <= \<const0>\;
LMB_Byte_Enable_3(2) <= \<const0>\;
LMB_Byte_Enable_3(3) <= \<const0>\;
LMB_Byte_Enable_30(0) <= \<const0>\;
LMB_Byte_Enable_30(1) <= \<const0>\;
LMB_Byte_Enable_30(2) <= \<const0>\;
LMB_Byte_Enable_30(3) <= \<const0>\;
LMB_Byte_Enable_31(0) <= \<const0>\;
LMB_Byte_Enable_31(1) <= \<const0>\;
LMB_Byte_Enable_31(2) <= \<const0>\;
LMB_Byte_Enable_31(3) <= \<const0>\;
LMB_Byte_Enable_4(0) <= \<const0>\;
LMB_Byte_Enable_4(1) <= \<const0>\;
LMB_Byte_Enable_4(2) <= \<const0>\;
LMB_Byte_Enable_4(3) <= \<const0>\;
LMB_Byte_Enable_5(0) <= \<const0>\;
LMB_Byte_Enable_5(1) <= \<const0>\;
LMB_Byte_Enable_5(2) <= \<const0>\;
LMB_Byte_Enable_5(3) <= \<const0>\;
LMB_Byte_Enable_6(0) <= \<const0>\;
LMB_Byte_Enable_6(1) <= \<const0>\;
LMB_Byte_Enable_6(2) <= \<const0>\;
LMB_Byte_Enable_6(3) <= \<const0>\;
LMB_Byte_Enable_7(0) <= \<const0>\;
LMB_Byte_Enable_7(1) <= \<const0>\;
LMB_Byte_Enable_7(2) <= \<const0>\;
LMB_Byte_Enable_7(3) <= \<const0>\;
LMB_Byte_Enable_8(0) <= \<const0>\;
LMB_Byte_Enable_8(1) <= \<const0>\;
LMB_Byte_Enable_8(2) <= \<const0>\;
LMB_Byte_Enable_8(3) <= \<const0>\;
LMB_Byte_Enable_9(0) <= \<const0>\;
LMB_Byte_Enable_9(1) <= \<const0>\;
LMB_Byte_Enable_9(2) <= \<const0>\;
LMB_Byte_Enable_9(3) <= \<const0>\;
LMB_Data_Addr_0(0) <= \<const0>\;
LMB_Data_Addr_0(1) <= \<const0>\;
LMB_Data_Addr_0(2) <= \<const0>\;
LMB_Data_Addr_0(3) <= \<const0>\;
LMB_Data_Addr_0(4) <= \<const0>\;
LMB_Data_Addr_0(5) <= \<const0>\;
LMB_Data_Addr_0(6) <= \<const0>\;
LMB_Data_Addr_0(7) <= \<const0>\;
LMB_Data_Addr_0(8) <= \<const0>\;
LMB_Data_Addr_0(9) <= \<const0>\;
LMB_Data_Addr_0(10) <= \<const0>\;
LMB_Data_Addr_0(11) <= \<const0>\;
LMB_Data_Addr_0(12) <= \<const0>\;
LMB_Data_Addr_0(13) <= \<const0>\;
LMB_Data_Addr_0(14) <= \<const0>\;
LMB_Data_Addr_0(15) <= \<const0>\;
LMB_Data_Addr_0(16) <= \<const0>\;
LMB_Data_Addr_0(17) <= \<const0>\;
LMB_Data_Addr_0(18) <= \<const0>\;
LMB_Data_Addr_0(19) <= \<const0>\;
LMB_Data_Addr_0(20) <= \<const0>\;
LMB_Data_Addr_0(21) <= \<const0>\;
LMB_Data_Addr_0(22) <= \<const0>\;
LMB_Data_Addr_0(23) <= \<const0>\;
LMB_Data_Addr_0(24) <= \<const0>\;
LMB_Data_Addr_0(25) <= \<const0>\;
LMB_Data_Addr_0(26) <= \<const0>\;
LMB_Data_Addr_0(27) <= \<const0>\;
LMB_Data_Addr_0(28) <= \<const0>\;
LMB_Data_Addr_0(29) <= \<const0>\;
LMB_Data_Addr_0(30) <= \<const0>\;
LMB_Data_Addr_0(31) <= \<const0>\;
LMB_Data_Addr_1(0) <= \<const0>\;
LMB_Data_Addr_1(1) <= \<const0>\;
LMB_Data_Addr_1(2) <= \<const0>\;
LMB_Data_Addr_1(3) <= \<const0>\;
LMB_Data_Addr_1(4) <= \<const0>\;
LMB_Data_Addr_1(5) <= \<const0>\;
LMB_Data_Addr_1(6) <= \<const0>\;
LMB_Data_Addr_1(7) <= \<const0>\;
LMB_Data_Addr_1(8) <= \<const0>\;
LMB_Data_Addr_1(9) <= \<const0>\;
LMB_Data_Addr_1(10) <= \<const0>\;
LMB_Data_Addr_1(11) <= \<const0>\;
LMB_Data_Addr_1(12) <= \<const0>\;
LMB_Data_Addr_1(13) <= \<const0>\;
LMB_Data_Addr_1(14) <= \<const0>\;
LMB_Data_Addr_1(15) <= \<const0>\;
LMB_Data_Addr_1(16) <= \<const0>\;
LMB_Data_Addr_1(17) <= \<const0>\;
LMB_Data_Addr_1(18) <= \<const0>\;
LMB_Data_Addr_1(19) <= \<const0>\;
LMB_Data_Addr_1(20) <= \<const0>\;
LMB_Data_Addr_1(21) <= \<const0>\;
LMB_Data_Addr_1(22) <= \<const0>\;
LMB_Data_Addr_1(23) <= \<const0>\;
LMB_Data_Addr_1(24) <= \<const0>\;
LMB_Data_Addr_1(25) <= \<const0>\;
LMB_Data_Addr_1(26) <= \<const0>\;
LMB_Data_Addr_1(27) <= \<const0>\;
LMB_Data_Addr_1(28) <= \<const0>\;
LMB_Data_Addr_1(29) <= \<const0>\;
LMB_Data_Addr_1(30) <= \<const0>\;
LMB_Data_Addr_1(31) <= \<const0>\;
LMB_Data_Addr_10(0) <= \<const0>\;
LMB_Data_Addr_10(1) <= \<const0>\;
LMB_Data_Addr_10(2) <= \<const0>\;
LMB_Data_Addr_10(3) <= \<const0>\;
LMB_Data_Addr_10(4) <= \<const0>\;
LMB_Data_Addr_10(5) <= \<const0>\;
LMB_Data_Addr_10(6) <= \<const0>\;
LMB_Data_Addr_10(7) <= \<const0>\;
LMB_Data_Addr_10(8) <= \<const0>\;
LMB_Data_Addr_10(9) <= \<const0>\;
LMB_Data_Addr_10(10) <= \<const0>\;
LMB_Data_Addr_10(11) <= \<const0>\;
LMB_Data_Addr_10(12) <= \<const0>\;
LMB_Data_Addr_10(13) <= \<const0>\;
LMB_Data_Addr_10(14) <= \<const0>\;
LMB_Data_Addr_10(15) <= \<const0>\;
LMB_Data_Addr_10(16) <= \<const0>\;
LMB_Data_Addr_10(17) <= \<const0>\;
LMB_Data_Addr_10(18) <= \<const0>\;
LMB_Data_Addr_10(19) <= \<const0>\;
LMB_Data_Addr_10(20) <= \<const0>\;
LMB_Data_Addr_10(21) <= \<const0>\;
LMB_Data_Addr_10(22) <= \<const0>\;
LMB_Data_Addr_10(23) <= \<const0>\;
LMB_Data_Addr_10(24) <= \<const0>\;
LMB_Data_Addr_10(25) <= \<const0>\;
LMB_Data_Addr_10(26) <= \<const0>\;
LMB_Data_Addr_10(27) <= \<const0>\;
LMB_Data_Addr_10(28) <= \<const0>\;
LMB_Data_Addr_10(29) <= \<const0>\;
LMB_Data_Addr_10(30) <= \<const0>\;
LMB_Data_Addr_10(31) <= \<const0>\;
LMB_Data_Addr_11(0) <= \<const0>\;
LMB_Data_Addr_11(1) <= \<const0>\;
LMB_Data_Addr_11(2) <= \<const0>\;
LMB_Data_Addr_11(3) <= \<const0>\;
LMB_Data_Addr_11(4) <= \<const0>\;
LMB_Data_Addr_11(5) <= \<const0>\;
LMB_Data_Addr_11(6) <= \<const0>\;
LMB_Data_Addr_11(7) <= \<const0>\;
LMB_Data_Addr_11(8) <= \<const0>\;
LMB_Data_Addr_11(9) <= \<const0>\;
LMB_Data_Addr_11(10) <= \<const0>\;
LMB_Data_Addr_11(11) <= \<const0>\;
LMB_Data_Addr_11(12) <= \<const0>\;
LMB_Data_Addr_11(13) <= \<const0>\;
LMB_Data_Addr_11(14) <= \<const0>\;
LMB_Data_Addr_11(15) <= \<const0>\;
LMB_Data_Addr_11(16) <= \<const0>\;
LMB_Data_Addr_11(17) <= \<const0>\;
LMB_Data_Addr_11(18) <= \<const0>\;
LMB_Data_Addr_11(19) <= \<const0>\;
LMB_Data_Addr_11(20) <= \<const0>\;
LMB_Data_Addr_11(21) <= \<const0>\;
LMB_Data_Addr_11(22) <= \<const0>\;
LMB_Data_Addr_11(23) <= \<const0>\;
LMB_Data_Addr_11(24) <= \<const0>\;
LMB_Data_Addr_11(25) <= \<const0>\;
LMB_Data_Addr_11(26) <= \<const0>\;
LMB_Data_Addr_11(27) <= \<const0>\;
LMB_Data_Addr_11(28) <= \<const0>\;
LMB_Data_Addr_11(29) <= \<const0>\;
LMB_Data_Addr_11(30) <= \<const0>\;
LMB_Data_Addr_11(31) <= \<const0>\;
LMB_Data_Addr_12(0) <= \<const0>\;
LMB_Data_Addr_12(1) <= \<const0>\;
LMB_Data_Addr_12(2) <= \<const0>\;
LMB_Data_Addr_12(3) <= \<const0>\;
LMB_Data_Addr_12(4) <= \<const0>\;
LMB_Data_Addr_12(5) <= \<const0>\;
LMB_Data_Addr_12(6) <= \<const0>\;
LMB_Data_Addr_12(7) <= \<const0>\;
LMB_Data_Addr_12(8) <= \<const0>\;
LMB_Data_Addr_12(9) <= \<const0>\;
LMB_Data_Addr_12(10) <= \<const0>\;
LMB_Data_Addr_12(11) <= \<const0>\;
LMB_Data_Addr_12(12) <= \<const0>\;
LMB_Data_Addr_12(13) <= \<const0>\;
LMB_Data_Addr_12(14) <= \<const0>\;
LMB_Data_Addr_12(15) <= \<const0>\;
LMB_Data_Addr_12(16) <= \<const0>\;
LMB_Data_Addr_12(17) <= \<const0>\;
LMB_Data_Addr_12(18) <= \<const0>\;
LMB_Data_Addr_12(19) <= \<const0>\;
LMB_Data_Addr_12(20) <= \<const0>\;
LMB_Data_Addr_12(21) <= \<const0>\;
LMB_Data_Addr_12(22) <= \<const0>\;
LMB_Data_Addr_12(23) <= \<const0>\;
LMB_Data_Addr_12(24) <= \<const0>\;
LMB_Data_Addr_12(25) <= \<const0>\;
LMB_Data_Addr_12(26) <= \<const0>\;
LMB_Data_Addr_12(27) <= \<const0>\;
LMB_Data_Addr_12(28) <= \<const0>\;
LMB_Data_Addr_12(29) <= \<const0>\;
LMB_Data_Addr_12(30) <= \<const0>\;
LMB_Data_Addr_12(31) <= \<const0>\;
LMB_Data_Addr_13(0) <= \<const0>\;
LMB_Data_Addr_13(1) <= \<const0>\;
LMB_Data_Addr_13(2) <= \<const0>\;
LMB_Data_Addr_13(3) <= \<const0>\;
LMB_Data_Addr_13(4) <= \<const0>\;
LMB_Data_Addr_13(5) <= \<const0>\;
LMB_Data_Addr_13(6) <= \<const0>\;
LMB_Data_Addr_13(7) <= \<const0>\;
LMB_Data_Addr_13(8) <= \<const0>\;
LMB_Data_Addr_13(9) <= \<const0>\;
LMB_Data_Addr_13(10) <= \<const0>\;
LMB_Data_Addr_13(11) <= \<const0>\;
LMB_Data_Addr_13(12) <= \<const0>\;
LMB_Data_Addr_13(13) <= \<const0>\;
LMB_Data_Addr_13(14) <= \<const0>\;
LMB_Data_Addr_13(15) <= \<const0>\;
LMB_Data_Addr_13(16) <= \<const0>\;
LMB_Data_Addr_13(17) <= \<const0>\;
LMB_Data_Addr_13(18) <= \<const0>\;
LMB_Data_Addr_13(19) <= \<const0>\;
LMB_Data_Addr_13(20) <= \<const0>\;
LMB_Data_Addr_13(21) <= \<const0>\;
LMB_Data_Addr_13(22) <= \<const0>\;
LMB_Data_Addr_13(23) <= \<const0>\;
LMB_Data_Addr_13(24) <= \<const0>\;
LMB_Data_Addr_13(25) <= \<const0>\;
LMB_Data_Addr_13(26) <= \<const0>\;
LMB_Data_Addr_13(27) <= \<const0>\;
LMB_Data_Addr_13(28) <= \<const0>\;
LMB_Data_Addr_13(29) <= \<const0>\;
LMB_Data_Addr_13(30) <= \<const0>\;
LMB_Data_Addr_13(31) <= \<const0>\;
LMB_Data_Addr_14(0) <= \<const0>\;
LMB_Data_Addr_14(1) <= \<const0>\;
LMB_Data_Addr_14(2) <= \<const0>\;
LMB_Data_Addr_14(3) <= \<const0>\;
LMB_Data_Addr_14(4) <= \<const0>\;
LMB_Data_Addr_14(5) <= \<const0>\;
LMB_Data_Addr_14(6) <= \<const0>\;
LMB_Data_Addr_14(7) <= \<const0>\;
LMB_Data_Addr_14(8) <= \<const0>\;
LMB_Data_Addr_14(9) <= \<const0>\;
LMB_Data_Addr_14(10) <= \<const0>\;
LMB_Data_Addr_14(11) <= \<const0>\;
LMB_Data_Addr_14(12) <= \<const0>\;
LMB_Data_Addr_14(13) <= \<const0>\;
LMB_Data_Addr_14(14) <= \<const0>\;
LMB_Data_Addr_14(15) <= \<const0>\;
LMB_Data_Addr_14(16) <= \<const0>\;
LMB_Data_Addr_14(17) <= \<const0>\;
LMB_Data_Addr_14(18) <= \<const0>\;
LMB_Data_Addr_14(19) <= \<const0>\;
LMB_Data_Addr_14(20) <= \<const0>\;
LMB_Data_Addr_14(21) <= \<const0>\;
LMB_Data_Addr_14(22) <= \<const0>\;
LMB_Data_Addr_14(23) <= \<const0>\;
LMB_Data_Addr_14(24) <= \<const0>\;
LMB_Data_Addr_14(25) <= \<const0>\;
LMB_Data_Addr_14(26) <= \<const0>\;
LMB_Data_Addr_14(27) <= \<const0>\;
LMB_Data_Addr_14(28) <= \<const0>\;
LMB_Data_Addr_14(29) <= \<const0>\;
LMB_Data_Addr_14(30) <= \<const0>\;
LMB_Data_Addr_14(31) <= \<const0>\;
LMB_Data_Addr_15(0) <= \<const0>\;
LMB_Data_Addr_15(1) <= \<const0>\;
LMB_Data_Addr_15(2) <= \<const0>\;
LMB_Data_Addr_15(3) <= \<const0>\;
LMB_Data_Addr_15(4) <= \<const0>\;
LMB_Data_Addr_15(5) <= \<const0>\;
LMB_Data_Addr_15(6) <= \<const0>\;
LMB_Data_Addr_15(7) <= \<const0>\;
LMB_Data_Addr_15(8) <= \<const0>\;
LMB_Data_Addr_15(9) <= \<const0>\;
LMB_Data_Addr_15(10) <= \<const0>\;
LMB_Data_Addr_15(11) <= \<const0>\;
LMB_Data_Addr_15(12) <= \<const0>\;
LMB_Data_Addr_15(13) <= \<const0>\;
LMB_Data_Addr_15(14) <= \<const0>\;
LMB_Data_Addr_15(15) <= \<const0>\;
LMB_Data_Addr_15(16) <= \<const0>\;
LMB_Data_Addr_15(17) <= \<const0>\;
LMB_Data_Addr_15(18) <= \<const0>\;
LMB_Data_Addr_15(19) <= \<const0>\;
LMB_Data_Addr_15(20) <= \<const0>\;
LMB_Data_Addr_15(21) <= \<const0>\;
LMB_Data_Addr_15(22) <= \<const0>\;
LMB_Data_Addr_15(23) <= \<const0>\;
LMB_Data_Addr_15(24) <= \<const0>\;
LMB_Data_Addr_15(25) <= \<const0>\;
LMB_Data_Addr_15(26) <= \<const0>\;
LMB_Data_Addr_15(27) <= \<const0>\;
LMB_Data_Addr_15(28) <= \<const0>\;
LMB_Data_Addr_15(29) <= \<const0>\;
LMB_Data_Addr_15(30) <= \<const0>\;
LMB_Data_Addr_15(31) <= \<const0>\;
LMB_Data_Addr_16(0) <= \<const0>\;
LMB_Data_Addr_16(1) <= \<const0>\;
LMB_Data_Addr_16(2) <= \<const0>\;
LMB_Data_Addr_16(3) <= \<const0>\;
LMB_Data_Addr_16(4) <= \<const0>\;
LMB_Data_Addr_16(5) <= \<const0>\;
LMB_Data_Addr_16(6) <= \<const0>\;
LMB_Data_Addr_16(7) <= \<const0>\;
LMB_Data_Addr_16(8) <= \<const0>\;
LMB_Data_Addr_16(9) <= \<const0>\;
LMB_Data_Addr_16(10) <= \<const0>\;
LMB_Data_Addr_16(11) <= \<const0>\;
LMB_Data_Addr_16(12) <= \<const0>\;
LMB_Data_Addr_16(13) <= \<const0>\;
LMB_Data_Addr_16(14) <= \<const0>\;
LMB_Data_Addr_16(15) <= \<const0>\;
LMB_Data_Addr_16(16) <= \<const0>\;
LMB_Data_Addr_16(17) <= \<const0>\;
LMB_Data_Addr_16(18) <= \<const0>\;
LMB_Data_Addr_16(19) <= \<const0>\;
LMB_Data_Addr_16(20) <= \<const0>\;
LMB_Data_Addr_16(21) <= \<const0>\;
LMB_Data_Addr_16(22) <= \<const0>\;
LMB_Data_Addr_16(23) <= \<const0>\;
LMB_Data_Addr_16(24) <= \<const0>\;
LMB_Data_Addr_16(25) <= \<const0>\;
LMB_Data_Addr_16(26) <= \<const0>\;
LMB_Data_Addr_16(27) <= \<const0>\;
LMB_Data_Addr_16(28) <= \<const0>\;
LMB_Data_Addr_16(29) <= \<const0>\;
LMB_Data_Addr_16(30) <= \<const0>\;
LMB_Data_Addr_16(31) <= \<const0>\;
LMB_Data_Addr_17(0) <= \<const0>\;
LMB_Data_Addr_17(1) <= \<const0>\;
LMB_Data_Addr_17(2) <= \<const0>\;
LMB_Data_Addr_17(3) <= \<const0>\;
LMB_Data_Addr_17(4) <= \<const0>\;
LMB_Data_Addr_17(5) <= \<const0>\;
LMB_Data_Addr_17(6) <= \<const0>\;
LMB_Data_Addr_17(7) <= \<const0>\;
LMB_Data_Addr_17(8) <= \<const0>\;
LMB_Data_Addr_17(9) <= \<const0>\;
LMB_Data_Addr_17(10) <= \<const0>\;
LMB_Data_Addr_17(11) <= \<const0>\;
LMB_Data_Addr_17(12) <= \<const0>\;
LMB_Data_Addr_17(13) <= \<const0>\;
LMB_Data_Addr_17(14) <= \<const0>\;
LMB_Data_Addr_17(15) <= \<const0>\;
LMB_Data_Addr_17(16) <= \<const0>\;
LMB_Data_Addr_17(17) <= \<const0>\;
LMB_Data_Addr_17(18) <= \<const0>\;
LMB_Data_Addr_17(19) <= \<const0>\;
LMB_Data_Addr_17(20) <= \<const0>\;
LMB_Data_Addr_17(21) <= \<const0>\;
LMB_Data_Addr_17(22) <= \<const0>\;
LMB_Data_Addr_17(23) <= \<const0>\;
LMB_Data_Addr_17(24) <= \<const0>\;
LMB_Data_Addr_17(25) <= \<const0>\;
LMB_Data_Addr_17(26) <= \<const0>\;
LMB_Data_Addr_17(27) <= \<const0>\;
LMB_Data_Addr_17(28) <= \<const0>\;
LMB_Data_Addr_17(29) <= \<const0>\;
LMB_Data_Addr_17(30) <= \<const0>\;
LMB_Data_Addr_17(31) <= \<const0>\;
LMB_Data_Addr_18(0) <= \<const0>\;
LMB_Data_Addr_18(1) <= \<const0>\;
LMB_Data_Addr_18(2) <= \<const0>\;
LMB_Data_Addr_18(3) <= \<const0>\;
LMB_Data_Addr_18(4) <= \<const0>\;
LMB_Data_Addr_18(5) <= \<const0>\;
LMB_Data_Addr_18(6) <= \<const0>\;
LMB_Data_Addr_18(7) <= \<const0>\;
LMB_Data_Addr_18(8) <= \<const0>\;
LMB_Data_Addr_18(9) <= \<const0>\;
LMB_Data_Addr_18(10) <= \<const0>\;
LMB_Data_Addr_18(11) <= \<const0>\;
LMB_Data_Addr_18(12) <= \<const0>\;
LMB_Data_Addr_18(13) <= \<const0>\;
LMB_Data_Addr_18(14) <= \<const0>\;
LMB_Data_Addr_18(15) <= \<const0>\;
LMB_Data_Addr_18(16) <= \<const0>\;
LMB_Data_Addr_18(17) <= \<const0>\;
LMB_Data_Addr_18(18) <= \<const0>\;
LMB_Data_Addr_18(19) <= \<const0>\;
LMB_Data_Addr_18(20) <= \<const0>\;
LMB_Data_Addr_18(21) <= \<const0>\;
LMB_Data_Addr_18(22) <= \<const0>\;
LMB_Data_Addr_18(23) <= \<const0>\;
LMB_Data_Addr_18(24) <= \<const0>\;
LMB_Data_Addr_18(25) <= \<const0>\;
LMB_Data_Addr_18(26) <= \<const0>\;
LMB_Data_Addr_18(27) <= \<const0>\;
LMB_Data_Addr_18(28) <= \<const0>\;
LMB_Data_Addr_18(29) <= \<const0>\;
LMB_Data_Addr_18(30) <= \<const0>\;
LMB_Data_Addr_18(31) <= \<const0>\;
LMB_Data_Addr_19(0) <= \<const0>\;
LMB_Data_Addr_19(1) <= \<const0>\;
LMB_Data_Addr_19(2) <= \<const0>\;
LMB_Data_Addr_19(3) <= \<const0>\;
LMB_Data_Addr_19(4) <= \<const0>\;
LMB_Data_Addr_19(5) <= \<const0>\;
LMB_Data_Addr_19(6) <= \<const0>\;
LMB_Data_Addr_19(7) <= \<const0>\;
LMB_Data_Addr_19(8) <= \<const0>\;
LMB_Data_Addr_19(9) <= \<const0>\;
LMB_Data_Addr_19(10) <= \<const0>\;
LMB_Data_Addr_19(11) <= \<const0>\;
LMB_Data_Addr_19(12) <= \<const0>\;
LMB_Data_Addr_19(13) <= \<const0>\;
LMB_Data_Addr_19(14) <= \<const0>\;
LMB_Data_Addr_19(15) <= \<const0>\;
LMB_Data_Addr_19(16) <= \<const0>\;
LMB_Data_Addr_19(17) <= \<const0>\;
LMB_Data_Addr_19(18) <= \<const0>\;
LMB_Data_Addr_19(19) <= \<const0>\;
LMB_Data_Addr_19(20) <= \<const0>\;
LMB_Data_Addr_19(21) <= \<const0>\;
LMB_Data_Addr_19(22) <= \<const0>\;
LMB_Data_Addr_19(23) <= \<const0>\;
LMB_Data_Addr_19(24) <= \<const0>\;
LMB_Data_Addr_19(25) <= \<const0>\;
LMB_Data_Addr_19(26) <= \<const0>\;
LMB_Data_Addr_19(27) <= \<const0>\;
LMB_Data_Addr_19(28) <= \<const0>\;
LMB_Data_Addr_19(29) <= \<const0>\;
LMB_Data_Addr_19(30) <= \<const0>\;
LMB_Data_Addr_19(31) <= \<const0>\;
LMB_Data_Addr_2(0) <= \<const0>\;
LMB_Data_Addr_2(1) <= \<const0>\;
LMB_Data_Addr_2(2) <= \<const0>\;
LMB_Data_Addr_2(3) <= \<const0>\;
LMB_Data_Addr_2(4) <= \<const0>\;
LMB_Data_Addr_2(5) <= \<const0>\;
LMB_Data_Addr_2(6) <= \<const0>\;
LMB_Data_Addr_2(7) <= \<const0>\;
LMB_Data_Addr_2(8) <= \<const0>\;
LMB_Data_Addr_2(9) <= \<const0>\;
LMB_Data_Addr_2(10) <= \<const0>\;
LMB_Data_Addr_2(11) <= \<const0>\;
LMB_Data_Addr_2(12) <= \<const0>\;
LMB_Data_Addr_2(13) <= \<const0>\;
LMB_Data_Addr_2(14) <= \<const0>\;
LMB_Data_Addr_2(15) <= \<const0>\;
LMB_Data_Addr_2(16) <= \<const0>\;
LMB_Data_Addr_2(17) <= \<const0>\;
LMB_Data_Addr_2(18) <= \<const0>\;
LMB_Data_Addr_2(19) <= \<const0>\;
LMB_Data_Addr_2(20) <= \<const0>\;
LMB_Data_Addr_2(21) <= \<const0>\;
LMB_Data_Addr_2(22) <= \<const0>\;
LMB_Data_Addr_2(23) <= \<const0>\;
LMB_Data_Addr_2(24) <= \<const0>\;
LMB_Data_Addr_2(25) <= \<const0>\;
LMB_Data_Addr_2(26) <= \<const0>\;
LMB_Data_Addr_2(27) <= \<const0>\;
LMB_Data_Addr_2(28) <= \<const0>\;
LMB_Data_Addr_2(29) <= \<const0>\;
LMB_Data_Addr_2(30) <= \<const0>\;
LMB_Data_Addr_2(31) <= \<const0>\;
LMB_Data_Addr_20(0) <= \<const0>\;
LMB_Data_Addr_20(1) <= \<const0>\;
LMB_Data_Addr_20(2) <= \<const0>\;
LMB_Data_Addr_20(3) <= \<const0>\;
LMB_Data_Addr_20(4) <= \<const0>\;
LMB_Data_Addr_20(5) <= \<const0>\;
LMB_Data_Addr_20(6) <= \<const0>\;
LMB_Data_Addr_20(7) <= \<const0>\;
LMB_Data_Addr_20(8) <= \<const0>\;
LMB_Data_Addr_20(9) <= \<const0>\;
LMB_Data_Addr_20(10) <= \<const0>\;
LMB_Data_Addr_20(11) <= \<const0>\;
LMB_Data_Addr_20(12) <= \<const0>\;
LMB_Data_Addr_20(13) <= \<const0>\;
LMB_Data_Addr_20(14) <= \<const0>\;
LMB_Data_Addr_20(15) <= \<const0>\;
LMB_Data_Addr_20(16) <= \<const0>\;
LMB_Data_Addr_20(17) <= \<const0>\;
LMB_Data_Addr_20(18) <= \<const0>\;
LMB_Data_Addr_20(19) <= \<const0>\;
LMB_Data_Addr_20(20) <= \<const0>\;
LMB_Data_Addr_20(21) <= \<const0>\;
LMB_Data_Addr_20(22) <= \<const0>\;
LMB_Data_Addr_20(23) <= \<const0>\;
LMB_Data_Addr_20(24) <= \<const0>\;
LMB_Data_Addr_20(25) <= \<const0>\;
LMB_Data_Addr_20(26) <= \<const0>\;
LMB_Data_Addr_20(27) <= \<const0>\;
LMB_Data_Addr_20(28) <= \<const0>\;
LMB_Data_Addr_20(29) <= \<const0>\;
LMB_Data_Addr_20(30) <= \<const0>\;
LMB_Data_Addr_20(31) <= \<const0>\;
LMB_Data_Addr_21(0) <= \<const0>\;
LMB_Data_Addr_21(1) <= \<const0>\;
LMB_Data_Addr_21(2) <= \<const0>\;
LMB_Data_Addr_21(3) <= \<const0>\;
LMB_Data_Addr_21(4) <= \<const0>\;
LMB_Data_Addr_21(5) <= \<const0>\;
LMB_Data_Addr_21(6) <= \<const0>\;
LMB_Data_Addr_21(7) <= \<const0>\;
LMB_Data_Addr_21(8) <= \<const0>\;
LMB_Data_Addr_21(9) <= \<const0>\;
LMB_Data_Addr_21(10) <= \<const0>\;
LMB_Data_Addr_21(11) <= \<const0>\;
LMB_Data_Addr_21(12) <= \<const0>\;
LMB_Data_Addr_21(13) <= \<const0>\;
LMB_Data_Addr_21(14) <= \<const0>\;
LMB_Data_Addr_21(15) <= \<const0>\;
LMB_Data_Addr_21(16) <= \<const0>\;
LMB_Data_Addr_21(17) <= \<const0>\;
LMB_Data_Addr_21(18) <= \<const0>\;
LMB_Data_Addr_21(19) <= \<const0>\;
LMB_Data_Addr_21(20) <= \<const0>\;
LMB_Data_Addr_21(21) <= \<const0>\;
LMB_Data_Addr_21(22) <= \<const0>\;
LMB_Data_Addr_21(23) <= \<const0>\;
LMB_Data_Addr_21(24) <= \<const0>\;
LMB_Data_Addr_21(25) <= \<const0>\;
LMB_Data_Addr_21(26) <= \<const0>\;
LMB_Data_Addr_21(27) <= \<const0>\;
LMB_Data_Addr_21(28) <= \<const0>\;
LMB_Data_Addr_21(29) <= \<const0>\;
LMB_Data_Addr_21(30) <= \<const0>\;
LMB_Data_Addr_21(31) <= \<const0>\;
LMB_Data_Addr_22(0) <= \<const0>\;
LMB_Data_Addr_22(1) <= \<const0>\;
LMB_Data_Addr_22(2) <= \<const0>\;
LMB_Data_Addr_22(3) <= \<const0>\;
LMB_Data_Addr_22(4) <= \<const0>\;
LMB_Data_Addr_22(5) <= \<const0>\;
LMB_Data_Addr_22(6) <= \<const0>\;
LMB_Data_Addr_22(7) <= \<const0>\;
LMB_Data_Addr_22(8) <= \<const0>\;
LMB_Data_Addr_22(9) <= \<const0>\;
LMB_Data_Addr_22(10) <= \<const0>\;
LMB_Data_Addr_22(11) <= \<const0>\;
LMB_Data_Addr_22(12) <= \<const0>\;
LMB_Data_Addr_22(13) <= \<const0>\;
LMB_Data_Addr_22(14) <= \<const0>\;
LMB_Data_Addr_22(15) <= \<const0>\;
LMB_Data_Addr_22(16) <= \<const0>\;
LMB_Data_Addr_22(17) <= \<const0>\;
LMB_Data_Addr_22(18) <= \<const0>\;
LMB_Data_Addr_22(19) <= \<const0>\;
LMB_Data_Addr_22(20) <= \<const0>\;
LMB_Data_Addr_22(21) <= \<const0>\;
LMB_Data_Addr_22(22) <= \<const0>\;
LMB_Data_Addr_22(23) <= \<const0>\;
LMB_Data_Addr_22(24) <= \<const0>\;
LMB_Data_Addr_22(25) <= \<const0>\;
LMB_Data_Addr_22(26) <= \<const0>\;
LMB_Data_Addr_22(27) <= \<const0>\;
LMB_Data_Addr_22(28) <= \<const0>\;
LMB_Data_Addr_22(29) <= \<const0>\;
LMB_Data_Addr_22(30) <= \<const0>\;
LMB_Data_Addr_22(31) <= \<const0>\;
LMB_Data_Addr_23(0) <= \<const0>\;
LMB_Data_Addr_23(1) <= \<const0>\;
LMB_Data_Addr_23(2) <= \<const0>\;
LMB_Data_Addr_23(3) <= \<const0>\;
LMB_Data_Addr_23(4) <= \<const0>\;
LMB_Data_Addr_23(5) <= \<const0>\;
LMB_Data_Addr_23(6) <= \<const0>\;
LMB_Data_Addr_23(7) <= \<const0>\;
LMB_Data_Addr_23(8) <= \<const0>\;
LMB_Data_Addr_23(9) <= \<const0>\;
LMB_Data_Addr_23(10) <= \<const0>\;
LMB_Data_Addr_23(11) <= \<const0>\;
LMB_Data_Addr_23(12) <= \<const0>\;
LMB_Data_Addr_23(13) <= \<const0>\;
LMB_Data_Addr_23(14) <= \<const0>\;
LMB_Data_Addr_23(15) <= \<const0>\;
LMB_Data_Addr_23(16) <= \<const0>\;
LMB_Data_Addr_23(17) <= \<const0>\;
LMB_Data_Addr_23(18) <= \<const0>\;
LMB_Data_Addr_23(19) <= \<const0>\;
LMB_Data_Addr_23(20) <= \<const0>\;
LMB_Data_Addr_23(21) <= \<const0>\;
LMB_Data_Addr_23(22) <= \<const0>\;
LMB_Data_Addr_23(23) <= \<const0>\;
LMB_Data_Addr_23(24) <= \<const0>\;
LMB_Data_Addr_23(25) <= \<const0>\;
LMB_Data_Addr_23(26) <= \<const0>\;
LMB_Data_Addr_23(27) <= \<const0>\;
LMB_Data_Addr_23(28) <= \<const0>\;
LMB_Data_Addr_23(29) <= \<const0>\;
LMB_Data_Addr_23(30) <= \<const0>\;
LMB_Data_Addr_23(31) <= \<const0>\;
LMB_Data_Addr_24(0) <= \<const0>\;
LMB_Data_Addr_24(1) <= \<const0>\;
LMB_Data_Addr_24(2) <= \<const0>\;
LMB_Data_Addr_24(3) <= \<const0>\;
LMB_Data_Addr_24(4) <= \<const0>\;
LMB_Data_Addr_24(5) <= \<const0>\;
LMB_Data_Addr_24(6) <= \<const0>\;
LMB_Data_Addr_24(7) <= \<const0>\;
LMB_Data_Addr_24(8) <= \<const0>\;
LMB_Data_Addr_24(9) <= \<const0>\;
LMB_Data_Addr_24(10) <= \<const0>\;
LMB_Data_Addr_24(11) <= \<const0>\;
LMB_Data_Addr_24(12) <= \<const0>\;
LMB_Data_Addr_24(13) <= \<const0>\;
LMB_Data_Addr_24(14) <= \<const0>\;
LMB_Data_Addr_24(15) <= \<const0>\;
LMB_Data_Addr_24(16) <= \<const0>\;
LMB_Data_Addr_24(17) <= \<const0>\;
LMB_Data_Addr_24(18) <= \<const0>\;
LMB_Data_Addr_24(19) <= \<const0>\;
LMB_Data_Addr_24(20) <= \<const0>\;
LMB_Data_Addr_24(21) <= \<const0>\;
LMB_Data_Addr_24(22) <= \<const0>\;
LMB_Data_Addr_24(23) <= \<const0>\;
LMB_Data_Addr_24(24) <= \<const0>\;
LMB_Data_Addr_24(25) <= \<const0>\;
LMB_Data_Addr_24(26) <= \<const0>\;
LMB_Data_Addr_24(27) <= \<const0>\;
LMB_Data_Addr_24(28) <= \<const0>\;
LMB_Data_Addr_24(29) <= \<const0>\;
LMB_Data_Addr_24(30) <= \<const0>\;
LMB_Data_Addr_24(31) <= \<const0>\;
LMB_Data_Addr_25(0) <= \<const0>\;
LMB_Data_Addr_25(1) <= \<const0>\;
LMB_Data_Addr_25(2) <= \<const0>\;
LMB_Data_Addr_25(3) <= \<const0>\;
LMB_Data_Addr_25(4) <= \<const0>\;
LMB_Data_Addr_25(5) <= \<const0>\;
LMB_Data_Addr_25(6) <= \<const0>\;
LMB_Data_Addr_25(7) <= \<const0>\;
LMB_Data_Addr_25(8) <= \<const0>\;
LMB_Data_Addr_25(9) <= \<const0>\;
LMB_Data_Addr_25(10) <= \<const0>\;
LMB_Data_Addr_25(11) <= \<const0>\;
LMB_Data_Addr_25(12) <= \<const0>\;
LMB_Data_Addr_25(13) <= \<const0>\;
LMB_Data_Addr_25(14) <= \<const0>\;
LMB_Data_Addr_25(15) <= \<const0>\;
LMB_Data_Addr_25(16) <= \<const0>\;
LMB_Data_Addr_25(17) <= \<const0>\;
LMB_Data_Addr_25(18) <= \<const0>\;
LMB_Data_Addr_25(19) <= \<const0>\;
LMB_Data_Addr_25(20) <= \<const0>\;
LMB_Data_Addr_25(21) <= \<const0>\;
LMB_Data_Addr_25(22) <= \<const0>\;
LMB_Data_Addr_25(23) <= \<const0>\;
LMB_Data_Addr_25(24) <= \<const0>\;
LMB_Data_Addr_25(25) <= \<const0>\;
LMB_Data_Addr_25(26) <= \<const0>\;
LMB_Data_Addr_25(27) <= \<const0>\;
LMB_Data_Addr_25(28) <= \<const0>\;
LMB_Data_Addr_25(29) <= \<const0>\;
LMB_Data_Addr_25(30) <= \<const0>\;
LMB_Data_Addr_25(31) <= \<const0>\;
LMB_Data_Addr_26(0) <= \<const0>\;
LMB_Data_Addr_26(1) <= \<const0>\;
LMB_Data_Addr_26(2) <= \<const0>\;
LMB_Data_Addr_26(3) <= \<const0>\;
LMB_Data_Addr_26(4) <= \<const0>\;
LMB_Data_Addr_26(5) <= \<const0>\;
LMB_Data_Addr_26(6) <= \<const0>\;
LMB_Data_Addr_26(7) <= \<const0>\;
LMB_Data_Addr_26(8) <= \<const0>\;
LMB_Data_Addr_26(9) <= \<const0>\;
LMB_Data_Addr_26(10) <= \<const0>\;
LMB_Data_Addr_26(11) <= \<const0>\;
LMB_Data_Addr_26(12) <= \<const0>\;
LMB_Data_Addr_26(13) <= \<const0>\;
LMB_Data_Addr_26(14) <= \<const0>\;
LMB_Data_Addr_26(15) <= \<const0>\;
LMB_Data_Addr_26(16) <= \<const0>\;
LMB_Data_Addr_26(17) <= \<const0>\;
LMB_Data_Addr_26(18) <= \<const0>\;
LMB_Data_Addr_26(19) <= \<const0>\;
LMB_Data_Addr_26(20) <= \<const0>\;
LMB_Data_Addr_26(21) <= \<const0>\;
LMB_Data_Addr_26(22) <= \<const0>\;
LMB_Data_Addr_26(23) <= \<const0>\;
LMB_Data_Addr_26(24) <= \<const0>\;
LMB_Data_Addr_26(25) <= \<const0>\;
LMB_Data_Addr_26(26) <= \<const0>\;
LMB_Data_Addr_26(27) <= \<const0>\;
LMB_Data_Addr_26(28) <= \<const0>\;
LMB_Data_Addr_26(29) <= \<const0>\;
LMB_Data_Addr_26(30) <= \<const0>\;
LMB_Data_Addr_26(31) <= \<const0>\;
LMB_Data_Addr_27(0) <= \<const0>\;
LMB_Data_Addr_27(1) <= \<const0>\;
LMB_Data_Addr_27(2) <= \<const0>\;
LMB_Data_Addr_27(3) <= \<const0>\;
LMB_Data_Addr_27(4) <= \<const0>\;
LMB_Data_Addr_27(5) <= \<const0>\;
LMB_Data_Addr_27(6) <= \<const0>\;
LMB_Data_Addr_27(7) <= \<const0>\;
LMB_Data_Addr_27(8) <= \<const0>\;
LMB_Data_Addr_27(9) <= \<const0>\;
LMB_Data_Addr_27(10) <= \<const0>\;
LMB_Data_Addr_27(11) <= \<const0>\;
LMB_Data_Addr_27(12) <= \<const0>\;
LMB_Data_Addr_27(13) <= \<const0>\;
LMB_Data_Addr_27(14) <= \<const0>\;
LMB_Data_Addr_27(15) <= \<const0>\;
LMB_Data_Addr_27(16) <= \<const0>\;
LMB_Data_Addr_27(17) <= \<const0>\;
LMB_Data_Addr_27(18) <= \<const0>\;
LMB_Data_Addr_27(19) <= \<const0>\;
LMB_Data_Addr_27(20) <= \<const0>\;
LMB_Data_Addr_27(21) <= \<const0>\;
LMB_Data_Addr_27(22) <= \<const0>\;
LMB_Data_Addr_27(23) <= \<const0>\;
LMB_Data_Addr_27(24) <= \<const0>\;
LMB_Data_Addr_27(25) <= \<const0>\;
LMB_Data_Addr_27(26) <= \<const0>\;
LMB_Data_Addr_27(27) <= \<const0>\;
LMB_Data_Addr_27(28) <= \<const0>\;
LMB_Data_Addr_27(29) <= \<const0>\;
LMB_Data_Addr_27(30) <= \<const0>\;
LMB_Data_Addr_27(31) <= \<const0>\;
LMB_Data_Addr_28(0) <= \<const0>\;
LMB_Data_Addr_28(1) <= \<const0>\;
LMB_Data_Addr_28(2) <= \<const0>\;
LMB_Data_Addr_28(3) <= \<const0>\;
LMB_Data_Addr_28(4) <= \<const0>\;
LMB_Data_Addr_28(5) <= \<const0>\;
LMB_Data_Addr_28(6) <= \<const0>\;
LMB_Data_Addr_28(7) <= \<const0>\;
LMB_Data_Addr_28(8) <= \<const0>\;
LMB_Data_Addr_28(9) <= \<const0>\;
LMB_Data_Addr_28(10) <= \<const0>\;
LMB_Data_Addr_28(11) <= \<const0>\;
LMB_Data_Addr_28(12) <= \<const0>\;
LMB_Data_Addr_28(13) <= \<const0>\;
LMB_Data_Addr_28(14) <= \<const0>\;
LMB_Data_Addr_28(15) <= \<const0>\;
LMB_Data_Addr_28(16) <= \<const0>\;
LMB_Data_Addr_28(17) <= \<const0>\;
LMB_Data_Addr_28(18) <= \<const0>\;
LMB_Data_Addr_28(19) <= \<const0>\;
LMB_Data_Addr_28(20) <= \<const0>\;
LMB_Data_Addr_28(21) <= \<const0>\;
LMB_Data_Addr_28(22) <= \<const0>\;
LMB_Data_Addr_28(23) <= \<const0>\;
LMB_Data_Addr_28(24) <= \<const0>\;
LMB_Data_Addr_28(25) <= \<const0>\;
LMB_Data_Addr_28(26) <= \<const0>\;
LMB_Data_Addr_28(27) <= \<const0>\;
LMB_Data_Addr_28(28) <= \<const0>\;
LMB_Data_Addr_28(29) <= \<const0>\;
LMB_Data_Addr_28(30) <= \<const0>\;
LMB_Data_Addr_28(31) <= \<const0>\;
LMB_Data_Addr_29(0) <= \<const0>\;
LMB_Data_Addr_29(1) <= \<const0>\;
LMB_Data_Addr_29(2) <= \<const0>\;
LMB_Data_Addr_29(3) <= \<const0>\;
LMB_Data_Addr_29(4) <= \<const0>\;
LMB_Data_Addr_29(5) <= \<const0>\;
LMB_Data_Addr_29(6) <= \<const0>\;
LMB_Data_Addr_29(7) <= \<const0>\;
LMB_Data_Addr_29(8) <= \<const0>\;
LMB_Data_Addr_29(9) <= \<const0>\;
LMB_Data_Addr_29(10) <= \<const0>\;
LMB_Data_Addr_29(11) <= \<const0>\;
LMB_Data_Addr_29(12) <= \<const0>\;
LMB_Data_Addr_29(13) <= \<const0>\;
LMB_Data_Addr_29(14) <= \<const0>\;
LMB_Data_Addr_29(15) <= \<const0>\;
LMB_Data_Addr_29(16) <= \<const0>\;
LMB_Data_Addr_29(17) <= \<const0>\;
LMB_Data_Addr_29(18) <= \<const0>\;
LMB_Data_Addr_29(19) <= \<const0>\;
LMB_Data_Addr_29(20) <= \<const0>\;
LMB_Data_Addr_29(21) <= \<const0>\;
LMB_Data_Addr_29(22) <= \<const0>\;
LMB_Data_Addr_29(23) <= \<const0>\;
LMB_Data_Addr_29(24) <= \<const0>\;
LMB_Data_Addr_29(25) <= \<const0>\;
LMB_Data_Addr_29(26) <= \<const0>\;
LMB_Data_Addr_29(27) <= \<const0>\;
LMB_Data_Addr_29(28) <= \<const0>\;
LMB_Data_Addr_29(29) <= \<const0>\;
LMB_Data_Addr_29(30) <= \<const0>\;
LMB_Data_Addr_29(31) <= \<const0>\;
LMB_Data_Addr_3(0) <= \<const0>\;
LMB_Data_Addr_3(1) <= \<const0>\;
LMB_Data_Addr_3(2) <= \<const0>\;
LMB_Data_Addr_3(3) <= \<const0>\;
LMB_Data_Addr_3(4) <= \<const0>\;
LMB_Data_Addr_3(5) <= \<const0>\;
LMB_Data_Addr_3(6) <= \<const0>\;
LMB_Data_Addr_3(7) <= \<const0>\;
LMB_Data_Addr_3(8) <= \<const0>\;
LMB_Data_Addr_3(9) <= \<const0>\;
LMB_Data_Addr_3(10) <= \<const0>\;
LMB_Data_Addr_3(11) <= \<const0>\;
LMB_Data_Addr_3(12) <= \<const0>\;
LMB_Data_Addr_3(13) <= \<const0>\;
LMB_Data_Addr_3(14) <= \<const0>\;
LMB_Data_Addr_3(15) <= \<const0>\;
LMB_Data_Addr_3(16) <= \<const0>\;
LMB_Data_Addr_3(17) <= \<const0>\;
LMB_Data_Addr_3(18) <= \<const0>\;
LMB_Data_Addr_3(19) <= \<const0>\;
LMB_Data_Addr_3(20) <= \<const0>\;
LMB_Data_Addr_3(21) <= \<const0>\;
LMB_Data_Addr_3(22) <= \<const0>\;
LMB_Data_Addr_3(23) <= \<const0>\;
LMB_Data_Addr_3(24) <= \<const0>\;
LMB_Data_Addr_3(25) <= \<const0>\;
LMB_Data_Addr_3(26) <= \<const0>\;
LMB_Data_Addr_3(27) <= \<const0>\;
LMB_Data_Addr_3(28) <= \<const0>\;
LMB_Data_Addr_3(29) <= \<const0>\;
LMB_Data_Addr_3(30) <= \<const0>\;
LMB_Data_Addr_3(31) <= \<const0>\;
LMB_Data_Addr_30(0) <= \<const0>\;
LMB_Data_Addr_30(1) <= \<const0>\;
LMB_Data_Addr_30(2) <= \<const0>\;
LMB_Data_Addr_30(3) <= \<const0>\;
LMB_Data_Addr_30(4) <= \<const0>\;
LMB_Data_Addr_30(5) <= \<const0>\;
LMB_Data_Addr_30(6) <= \<const0>\;
LMB_Data_Addr_30(7) <= \<const0>\;
LMB_Data_Addr_30(8) <= \<const0>\;
LMB_Data_Addr_30(9) <= \<const0>\;
LMB_Data_Addr_30(10) <= \<const0>\;
LMB_Data_Addr_30(11) <= \<const0>\;
LMB_Data_Addr_30(12) <= \<const0>\;
LMB_Data_Addr_30(13) <= \<const0>\;
LMB_Data_Addr_30(14) <= \<const0>\;
LMB_Data_Addr_30(15) <= \<const0>\;
LMB_Data_Addr_30(16) <= \<const0>\;
LMB_Data_Addr_30(17) <= \<const0>\;
LMB_Data_Addr_30(18) <= \<const0>\;
LMB_Data_Addr_30(19) <= \<const0>\;
LMB_Data_Addr_30(20) <= \<const0>\;
LMB_Data_Addr_30(21) <= \<const0>\;
LMB_Data_Addr_30(22) <= \<const0>\;
LMB_Data_Addr_30(23) <= \<const0>\;
LMB_Data_Addr_30(24) <= \<const0>\;
LMB_Data_Addr_30(25) <= \<const0>\;
LMB_Data_Addr_30(26) <= \<const0>\;
LMB_Data_Addr_30(27) <= \<const0>\;
LMB_Data_Addr_30(28) <= \<const0>\;
LMB_Data_Addr_30(29) <= \<const0>\;
LMB_Data_Addr_30(30) <= \<const0>\;
LMB_Data_Addr_30(31) <= \<const0>\;
LMB_Data_Addr_31(0) <= \<const0>\;
LMB_Data_Addr_31(1) <= \<const0>\;
LMB_Data_Addr_31(2) <= \<const0>\;
LMB_Data_Addr_31(3) <= \<const0>\;
LMB_Data_Addr_31(4) <= \<const0>\;
LMB_Data_Addr_31(5) <= \<const0>\;
LMB_Data_Addr_31(6) <= \<const0>\;
LMB_Data_Addr_31(7) <= \<const0>\;
LMB_Data_Addr_31(8) <= \<const0>\;
LMB_Data_Addr_31(9) <= \<const0>\;
LMB_Data_Addr_31(10) <= \<const0>\;
LMB_Data_Addr_31(11) <= \<const0>\;
LMB_Data_Addr_31(12) <= \<const0>\;
LMB_Data_Addr_31(13) <= \<const0>\;
LMB_Data_Addr_31(14) <= \<const0>\;
LMB_Data_Addr_31(15) <= \<const0>\;
LMB_Data_Addr_31(16) <= \<const0>\;
LMB_Data_Addr_31(17) <= \<const0>\;
LMB_Data_Addr_31(18) <= \<const0>\;
LMB_Data_Addr_31(19) <= \<const0>\;
LMB_Data_Addr_31(20) <= \<const0>\;
LMB_Data_Addr_31(21) <= \<const0>\;
LMB_Data_Addr_31(22) <= \<const0>\;
LMB_Data_Addr_31(23) <= \<const0>\;
LMB_Data_Addr_31(24) <= \<const0>\;
LMB_Data_Addr_31(25) <= \<const0>\;
LMB_Data_Addr_31(26) <= \<const0>\;
LMB_Data_Addr_31(27) <= \<const0>\;
LMB_Data_Addr_31(28) <= \<const0>\;
LMB_Data_Addr_31(29) <= \<const0>\;
LMB_Data_Addr_31(30) <= \<const0>\;
LMB_Data_Addr_31(31) <= \<const0>\;
LMB_Data_Addr_4(0) <= \<const0>\;
LMB_Data_Addr_4(1) <= \<const0>\;
LMB_Data_Addr_4(2) <= \<const0>\;
LMB_Data_Addr_4(3) <= \<const0>\;
LMB_Data_Addr_4(4) <= \<const0>\;
LMB_Data_Addr_4(5) <= \<const0>\;
LMB_Data_Addr_4(6) <= \<const0>\;
LMB_Data_Addr_4(7) <= \<const0>\;
LMB_Data_Addr_4(8) <= \<const0>\;
LMB_Data_Addr_4(9) <= \<const0>\;
LMB_Data_Addr_4(10) <= \<const0>\;
LMB_Data_Addr_4(11) <= \<const0>\;
LMB_Data_Addr_4(12) <= \<const0>\;
LMB_Data_Addr_4(13) <= \<const0>\;
LMB_Data_Addr_4(14) <= \<const0>\;
LMB_Data_Addr_4(15) <= \<const0>\;
LMB_Data_Addr_4(16) <= \<const0>\;
LMB_Data_Addr_4(17) <= \<const0>\;
LMB_Data_Addr_4(18) <= \<const0>\;
LMB_Data_Addr_4(19) <= \<const0>\;
LMB_Data_Addr_4(20) <= \<const0>\;
LMB_Data_Addr_4(21) <= \<const0>\;
LMB_Data_Addr_4(22) <= \<const0>\;
LMB_Data_Addr_4(23) <= \<const0>\;
LMB_Data_Addr_4(24) <= \<const0>\;
LMB_Data_Addr_4(25) <= \<const0>\;
LMB_Data_Addr_4(26) <= \<const0>\;
LMB_Data_Addr_4(27) <= \<const0>\;
LMB_Data_Addr_4(28) <= \<const0>\;
LMB_Data_Addr_4(29) <= \<const0>\;
LMB_Data_Addr_4(30) <= \<const0>\;
LMB_Data_Addr_4(31) <= \<const0>\;
LMB_Data_Addr_5(0) <= \<const0>\;
LMB_Data_Addr_5(1) <= \<const0>\;
LMB_Data_Addr_5(2) <= \<const0>\;
LMB_Data_Addr_5(3) <= \<const0>\;
LMB_Data_Addr_5(4) <= \<const0>\;
LMB_Data_Addr_5(5) <= \<const0>\;
LMB_Data_Addr_5(6) <= \<const0>\;
LMB_Data_Addr_5(7) <= \<const0>\;
LMB_Data_Addr_5(8) <= \<const0>\;
LMB_Data_Addr_5(9) <= \<const0>\;
LMB_Data_Addr_5(10) <= \<const0>\;
LMB_Data_Addr_5(11) <= \<const0>\;
LMB_Data_Addr_5(12) <= \<const0>\;
LMB_Data_Addr_5(13) <= \<const0>\;
LMB_Data_Addr_5(14) <= \<const0>\;
LMB_Data_Addr_5(15) <= \<const0>\;
LMB_Data_Addr_5(16) <= \<const0>\;
LMB_Data_Addr_5(17) <= \<const0>\;
LMB_Data_Addr_5(18) <= \<const0>\;
LMB_Data_Addr_5(19) <= \<const0>\;
LMB_Data_Addr_5(20) <= \<const0>\;
LMB_Data_Addr_5(21) <= \<const0>\;
LMB_Data_Addr_5(22) <= \<const0>\;
LMB_Data_Addr_5(23) <= \<const0>\;
LMB_Data_Addr_5(24) <= \<const0>\;
LMB_Data_Addr_5(25) <= \<const0>\;
LMB_Data_Addr_5(26) <= \<const0>\;
LMB_Data_Addr_5(27) <= \<const0>\;
LMB_Data_Addr_5(28) <= \<const0>\;
LMB_Data_Addr_5(29) <= \<const0>\;
LMB_Data_Addr_5(30) <= \<const0>\;
LMB_Data_Addr_5(31) <= \<const0>\;
LMB_Data_Addr_6(0) <= \<const0>\;
LMB_Data_Addr_6(1) <= \<const0>\;
LMB_Data_Addr_6(2) <= \<const0>\;
LMB_Data_Addr_6(3) <= \<const0>\;
LMB_Data_Addr_6(4) <= \<const0>\;
LMB_Data_Addr_6(5) <= \<const0>\;
LMB_Data_Addr_6(6) <= \<const0>\;
LMB_Data_Addr_6(7) <= \<const0>\;
LMB_Data_Addr_6(8) <= \<const0>\;
LMB_Data_Addr_6(9) <= \<const0>\;
LMB_Data_Addr_6(10) <= \<const0>\;
LMB_Data_Addr_6(11) <= \<const0>\;
LMB_Data_Addr_6(12) <= \<const0>\;
LMB_Data_Addr_6(13) <= \<const0>\;
LMB_Data_Addr_6(14) <= \<const0>\;
LMB_Data_Addr_6(15) <= \<const0>\;
LMB_Data_Addr_6(16) <= \<const0>\;
LMB_Data_Addr_6(17) <= \<const0>\;
LMB_Data_Addr_6(18) <= \<const0>\;
LMB_Data_Addr_6(19) <= \<const0>\;
LMB_Data_Addr_6(20) <= \<const0>\;
LMB_Data_Addr_6(21) <= \<const0>\;
LMB_Data_Addr_6(22) <= \<const0>\;
LMB_Data_Addr_6(23) <= \<const0>\;
LMB_Data_Addr_6(24) <= \<const0>\;
LMB_Data_Addr_6(25) <= \<const0>\;
LMB_Data_Addr_6(26) <= \<const0>\;
LMB_Data_Addr_6(27) <= \<const0>\;
LMB_Data_Addr_6(28) <= \<const0>\;
LMB_Data_Addr_6(29) <= \<const0>\;
LMB_Data_Addr_6(30) <= \<const0>\;
LMB_Data_Addr_6(31) <= \<const0>\;
LMB_Data_Addr_7(0) <= \<const0>\;
LMB_Data_Addr_7(1) <= \<const0>\;
LMB_Data_Addr_7(2) <= \<const0>\;
LMB_Data_Addr_7(3) <= \<const0>\;
LMB_Data_Addr_7(4) <= \<const0>\;
LMB_Data_Addr_7(5) <= \<const0>\;
LMB_Data_Addr_7(6) <= \<const0>\;
LMB_Data_Addr_7(7) <= \<const0>\;
LMB_Data_Addr_7(8) <= \<const0>\;
LMB_Data_Addr_7(9) <= \<const0>\;
LMB_Data_Addr_7(10) <= \<const0>\;
LMB_Data_Addr_7(11) <= \<const0>\;
LMB_Data_Addr_7(12) <= \<const0>\;
LMB_Data_Addr_7(13) <= \<const0>\;
LMB_Data_Addr_7(14) <= \<const0>\;
LMB_Data_Addr_7(15) <= \<const0>\;
LMB_Data_Addr_7(16) <= \<const0>\;
LMB_Data_Addr_7(17) <= \<const0>\;
LMB_Data_Addr_7(18) <= \<const0>\;
LMB_Data_Addr_7(19) <= \<const0>\;
LMB_Data_Addr_7(20) <= \<const0>\;
LMB_Data_Addr_7(21) <= \<const0>\;
LMB_Data_Addr_7(22) <= \<const0>\;
LMB_Data_Addr_7(23) <= \<const0>\;
LMB_Data_Addr_7(24) <= \<const0>\;
LMB_Data_Addr_7(25) <= \<const0>\;
LMB_Data_Addr_7(26) <= \<const0>\;
LMB_Data_Addr_7(27) <= \<const0>\;
LMB_Data_Addr_7(28) <= \<const0>\;
LMB_Data_Addr_7(29) <= \<const0>\;
LMB_Data_Addr_7(30) <= \<const0>\;
LMB_Data_Addr_7(31) <= \<const0>\;
LMB_Data_Addr_8(0) <= \<const0>\;
LMB_Data_Addr_8(1) <= \<const0>\;
LMB_Data_Addr_8(2) <= \<const0>\;
LMB_Data_Addr_8(3) <= \<const0>\;
LMB_Data_Addr_8(4) <= \<const0>\;
LMB_Data_Addr_8(5) <= \<const0>\;
LMB_Data_Addr_8(6) <= \<const0>\;
LMB_Data_Addr_8(7) <= \<const0>\;
LMB_Data_Addr_8(8) <= \<const0>\;
LMB_Data_Addr_8(9) <= \<const0>\;
LMB_Data_Addr_8(10) <= \<const0>\;
LMB_Data_Addr_8(11) <= \<const0>\;
LMB_Data_Addr_8(12) <= \<const0>\;
LMB_Data_Addr_8(13) <= \<const0>\;
LMB_Data_Addr_8(14) <= \<const0>\;
LMB_Data_Addr_8(15) <= \<const0>\;
LMB_Data_Addr_8(16) <= \<const0>\;
LMB_Data_Addr_8(17) <= \<const0>\;
LMB_Data_Addr_8(18) <= \<const0>\;
LMB_Data_Addr_8(19) <= \<const0>\;
LMB_Data_Addr_8(20) <= \<const0>\;
LMB_Data_Addr_8(21) <= \<const0>\;
LMB_Data_Addr_8(22) <= \<const0>\;
LMB_Data_Addr_8(23) <= \<const0>\;
LMB_Data_Addr_8(24) <= \<const0>\;
LMB_Data_Addr_8(25) <= \<const0>\;
LMB_Data_Addr_8(26) <= \<const0>\;
LMB_Data_Addr_8(27) <= \<const0>\;
LMB_Data_Addr_8(28) <= \<const0>\;
LMB_Data_Addr_8(29) <= \<const0>\;
LMB_Data_Addr_8(30) <= \<const0>\;
LMB_Data_Addr_8(31) <= \<const0>\;
LMB_Data_Addr_9(0) <= \<const0>\;
LMB_Data_Addr_9(1) <= \<const0>\;
LMB_Data_Addr_9(2) <= \<const0>\;
LMB_Data_Addr_9(3) <= \<const0>\;
LMB_Data_Addr_9(4) <= \<const0>\;
LMB_Data_Addr_9(5) <= \<const0>\;
LMB_Data_Addr_9(6) <= \<const0>\;
LMB_Data_Addr_9(7) <= \<const0>\;
LMB_Data_Addr_9(8) <= \<const0>\;
LMB_Data_Addr_9(9) <= \<const0>\;
LMB_Data_Addr_9(10) <= \<const0>\;
LMB_Data_Addr_9(11) <= \<const0>\;
LMB_Data_Addr_9(12) <= \<const0>\;
LMB_Data_Addr_9(13) <= \<const0>\;
LMB_Data_Addr_9(14) <= \<const0>\;
LMB_Data_Addr_9(15) <= \<const0>\;
LMB_Data_Addr_9(16) <= \<const0>\;
LMB_Data_Addr_9(17) <= \<const0>\;
LMB_Data_Addr_9(18) <= \<const0>\;
LMB_Data_Addr_9(19) <= \<const0>\;
LMB_Data_Addr_9(20) <= \<const0>\;
LMB_Data_Addr_9(21) <= \<const0>\;
LMB_Data_Addr_9(22) <= \<const0>\;
LMB_Data_Addr_9(23) <= \<const0>\;
LMB_Data_Addr_9(24) <= \<const0>\;
LMB_Data_Addr_9(25) <= \<const0>\;
LMB_Data_Addr_9(26) <= \<const0>\;
LMB_Data_Addr_9(27) <= \<const0>\;
LMB_Data_Addr_9(28) <= \<const0>\;
LMB_Data_Addr_9(29) <= \<const0>\;
LMB_Data_Addr_9(30) <= \<const0>\;
LMB_Data_Addr_9(31) <= \<const0>\;
LMB_Data_Write_0(0) <= \<const0>\;
LMB_Data_Write_0(1) <= \<const0>\;
LMB_Data_Write_0(2) <= \<const0>\;
LMB_Data_Write_0(3) <= \<const0>\;
LMB_Data_Write_0(4) <= \<const0>\;
LMB_Data_Write_0(5) <= \<const0>\;
LMB_Data_Write_0(6) <= \<const0>\;
LMB_Data_Write_0(7) <= \<const0>\;
LMB_Data_Write_0(8) <= \<const0>\;
LMB_Data_Write_0(9) <= \<const0>\;
LMB_Data_Write_0(10) <= \<const0>\;
LMB_Data_Write_0(11) <= \<const0>\;
LMB_Data_Write_0(12) <= \<const0>\;
LMB_Data_Write_0(13) <= \<const0>\;
LMB_Data_Write_0(14) <= \<const0>\;
LMB_Data_Write_0(15) <= \<const0>\;
LMB_Data_Write_0(16) <= \<const0>\;
LMB_Data_Write_0(17) <= \<const0>\;
LMB_Data_Write_0(18) <= \<const0>\;
LMB_Data_Write_0(19) <= \<const0>\;
LMB_Data_Write_0(20) <= \<const0>\;
LMB_Data_Write_0(21) <= \<const0>\;
LMB_Data_Write_0(22) <= \<const0>\;
LMB_Data_Write_0(23) <= \<const0>\;
LMB_Data_Write_0(24) <= \<const0>\;
LMB_Data_Write_0(25) <= \<const0>\;
LMB_Data_Write_0(26) <= \<const0>\;
LMB_Data_Write_0(27) <= \<const0>\;
LMB_Data_Write_0(28) <= \<const0>\;
LMB_Data_Write_0(29) <= \<const0>\;
LMB_Data_Write_0(30) <= \<const0>\;
LMB_Data_Write_0(31) <= \<const0>\;
LMB_Data_Write_1(0) <= \<const0>\;
LMB_Data_Write_1(1) <= \<const0>\;
LMB_Data_Write_1(2) <= \<const0>\;
LMB_Data_Write_1(3) <= \<const0>\;
LMB_Data_Write_1(4) <= \<const0>\;
LMB_Data_Write_1(5) <= \<const0>\;
LMB_Data_Write_1(6) <= \<const0>\;
LMB_Data_Write_1(7) <= \<const0>\;
LMB_Data_Write_1(8) <= \<const0>\;
LMB_Data_Write_1(9) <= \<const0>\;
LMB_Data_Write_1(10) <= \<const0>\;
LMB_Data_Write_1(11) <= \<const0>\;
LMB_Data_Write_1(12) <= \<const0>\;
LMB_Data_Write_1(13) <= \<const0>\;
LMB_Data_Write_1(14) <= \<const0>\;
LMB_Data_Write_1(15) <= \<const0>\;
LMB_Data_Write_1(16) <= \<const0>\;
LMB_Data_Write_1(17) <= \<const0>\;
LMB_Data_Write_1(18) <= \<const0>\;
LMB_Data_Write_1(19) <= \<const0>\;
LMB_Data_Write_1(20) <= \<const0>\;
LMB_Data_Write_1(21) <= \<const0>\;
LMB_Data_Write_1(22) <= \<const0>\;
LMB_Data_Write_1(23) <= \<const0>\;
LMB_Data_Write_1(24) <= \<const0>\;
LMB_Data_Write_1(25) <= \<const0>\;
LMB_Data_Write_1(26) <= \<const0>\;
LMB_Data_Write_1(27) <= \<const0>\;
LMB_Data_Write_1(28) <= \<const0>\;
LMB_Data_Write_1(29) <= \<const0>\;
LMB_Data_Write_1(30) <= \<const0>\;
LMB_Data_Write_1(31) <= \<const0>\;
LMB_Data_Write_10(0) <= \<const0>\;
LMB_Data_Write_10(1) <= \<const0>\;
LMB_Data_Write_10(2) <= \<const0>\;
LMB_Data_Write_10(3) <= \<const0>\;
LMB_Data_Write_10(4) <= \<const0>\;
LMB_Data_Write_10(5) <= \<const0>\;
LMB_Data_Write_10(6) <= \<const0>\;
LMB_Data_Write_10(7) <= \<const0>\;
LMB_Data_Write_10(8) <= \<const0>\;
LMB_Data_Write_10(9) <= \<const0>\;
LMB_Data_Write_10(10) <= \<const0>\;
LMB_Data_Write_10(11) <= \<const0>\;
LMB_Data_Write_10(12) <= \<const0>\;
LMB_Data_Write_10(13) <= \<const0>\;
LMB_Data_Write_10(14) <= \<const0>\;
LMB_Data_Write_10(15) <= \<const0>\;
LMB_Data_Write_10(16) <= \<const0>\;
LMB_Data_Write_10(17) <= \<const0>\;
LMB_Data_Write_10(18) <= \<const0>\;
LMB_Data_Write_10(19) <= \<const0>\;
LMB_Data_Write_10(20) <= \<const0>\;
LMB_Data_Write_10(21) <= \<const0>\;
LMB_Data_Write_10(22) <= \<const0>\;
LMB_Data_Write_10(23) <= \<const0>\;
LMB_Data_Write_10(24) <= \<const0>\;
LMB_Data_Write_10(25) <= \<const0>\;
LMB_Data_Write_10(26) <= \<const0>\;
LMB_Data_Write_10(27) <= \<const0>\;
LMB_Data_Write_10(28) <= \<const0>\;
LMB_Data_Write_10(29) <= \<const0>\;
LMB_Data_Write_10(30) <= \<const0>\;
LMB_Data_Write_10(31) <= \<const0>\;
LMB_Data_Write_11(0) <= \<const0>\;
LMB_Data_Write_11(1) <= \<const0>\;
LMB_Data_Write_11(2) <= \<const0>\;
LMB_Data_Write_11(3) <= \<const0>\;
LMB_Data_Write_11(4) <= \<const0>\;
LMB_Data_Write_11(5) <= \<const0>\;
LMB_Data_Write_11(6) <= \<const0>\;
LMB_Data_Write_11(7) <= \<const0>\;
LMB_Data_Write_11(8) <= \<const0>\;
LMB_Data_Write_11(9) <= \<const0>\;
LMB_Data_Write_11(10) <= \<const0>\;
LMB_Data_Write_11(11) <= \<const0>\;
LMB_Data_Write_11(12) <= \<const0>\;
LMB_Data_Write_11(13) <= \<const0>\;
LMB_Data_Write_11(14) <= \<const0>\;
LMB_Data_Write_11(15) <= \<const0>\;
LMB_Data_Write_11(16) <= \<const0>\;
LMB_Data_Write_11(17) <= \<const0>\;
LMB_Data_Write_11(18) <= \<const0>\;
LMB_Data_Write_11(19) <= \<const0>\;
LMB_Data_Write_11(20) <= \<const0>\;
LMB_Data_Write_11(21) <= \<const0>\;
LMB_Data_Write_11(22) <= \<const0>\;
LMB_Data_Write_11(23) <= \<const0>\;
LMB_Data_Write_11(24) <= \<const0>\;
LMB_Data_Write_11(25) <= \<const0>\;
LMB_Data_Write_11(26) <= \<const0>\;
LMB_Data_Write_11(27) <= \<const0>\;
LMB_Data_Write_11(28) <= \<const0>\;
LMB_Data_Write_11(29) <= \<const0>\;
LMB_Data_Write_11(30) <= \<const0>\;
LMB_Data_Write_11(31) <= \<const0>\;
LMB_Data_Write_12(0) <= \<const0>\;
LMB_Data_Write_12(1) <= \<const0>\;
LMB_Data_Write_12(2) <= \<const0>\;
LMB_Data_Write_12(3) <= \<const0>\;
LMB_Data_Write_12(4) <= \<const0>\;
LMB_Data_Write_12(5) <= \<const0>\;
LMB_Data_Write_12(6) <= \<const0>\;
LMB_Data_Write_12(7) <= \<const0>\;
LMB_Data_Write_12(8) <= \<const0>\;
LMB_Data_Write_12(9) <= \<const0>\;
LMB_Data_Write_12(10) <= \<const0>\;
LMB_Data_Write_12(11) <= \<const0>\;
LMB_Data_Write_12(12) <= \<const0>\;
LMB_Data_Write_12(13) <= \<const0>\;
LMB_Data_Write_12(14) <= \<const0>\;
LMB_Data_Write_12(15) <= \<const0>\;
LMB_Data_Write_12(16) <= \<const0>\;
LMB_Data_Write_12(17) <= \<const0>\;
LMB_Data_Write_12(18) <= \<const0>\;
LMB_Data_Write_12(19) <= \<const0>\;
LMB_Data_Write_12(20) <= \<const0>\;
LMB_Data_Write_12(21) <= \<const0>\;
LMB_Data_Write_12(22) <= \<const0>\;
LMB_Data_Write_12(23) <= \<const0>\;
LMB_Data_Write_12(24) <= \<const0>\;
LMB_Data_Write_12(25) <= \<const0>\;
LMB_Data_Write_12(26) <= \<const0>\;
LMB_Data_Write_12(27) <= \<const0>\;
LMB_Data_Write_12(28) <= \<const0>\;
LMB_Data_Write_12(29) <= \<const0>\;
LMB_Data_Write_12(30) <= \<const0>\;
LMB_Data_Write_12(31) <= \<const0>\;
LMB_Data_Write_13(0) <= \<const0>\;
LMB_Data_Write_13(1) <= \<const0>\;
LMB_Data_Write_13(2) <= \<const0>\;
LMB_Data_Write_13(3) <= \<const0>\;
LMB_Data_Write_13(4) <= \<const0>\;
LMB_Data_Write_13(5) <= \<const0>\;
LMB_Data_Write_13(6) <= \<const0>\;
LMB_Data_Write_13(7) <= \<const0>\;
LMB_Data_Write_13(8) <= \<const0>\;
LMB_Data_Write_13(9) <= \<const0>\;
LMB_Data_Write_13(10) <= \<const0>\;
LMB_Data_Write_13(11) <= \<const0>\;
LMB_Data_Write_13(12) <= \<const0>\;
LMB_Data_Write_13(13) <= \<const0>\;
LMB_Data_Write_13(14) <= \<const0>\;
LMB_Data_Write_13(15) <= \<const0>\;
LMB_Data_Write_13(16) <= \<const0>\;
LMB_Data_Write_13(17) <= \<const0>\;
LMB_Data_Write_13(18) <= \<const0>\;
LMB_Data_Write_13(19) <= \<const0>\;
LMB_Data_Write_13(20) <= \<const0>\;
LMB_Data_Write_13(21) <= \<const0>\;
LMB_Data_Write_13(22) <= \<const0>\;
LMB_Data_Write_13(23) <= \<const0>\;
LMB_Data_Write_13(24) <= \<const0>\;
LMB_Data_Write_13(25) <= \<const0>\;
LMB_Data_Write_13(26) <= \<const0>\;
LMB_Data_Write_13(27) <= \<const0>\;
LMB_Data_Write_13(28) <= \<const0>\;
LMB_Data_Write_13(29) <= \<const0>\;
LMB_Data_Write_13(30) <= \<const0>\;
LMB_Data_Write_13(31) <= \<const0>\;
LMB_Data_Write_14(0) <= \<const0>\;
LMB_Data_Write_14(1) <= \<const0>\;
LMB_Data_Write_14(2) <= \<const0>\;
LMB_Data_Write_14(3) <= \<const0>\;
LMB_Data_Write_14(4) <= \<const0>\;
LMB_Data_Write_14(5) <= \<const0>\;
LMB_Data_Write_14(6) <= \<const0>\;
LMB_Data_Write_14(7) <= \<const0>\;
LMB_Data_Write_14(8) <= \<const0>\;
LMB_Data_Write_14(9) <= \<const0>\;
LMB_Data_Write_14(10) <= \<const0>\;
LMB_Data_Write_14(11) <= \<const0>\;
LMB_Data_Write_14(12) <= \<const0>\;
LMB_Data_Write_14(13) <= \<const0>\;
LMB_Data_Write_14(14) <= \<const0>\;
LMB_Data_Write_14(15) <= \<const0>\;
LMB_Data_Write_14(16) <= \<const0>\;
LMB_Data_Write_14(17) <= \<const0>\;
LMB_Data_Write_14(18) <= \<const0>\;
LMB_Data_Write_14(19) <= \<const0>\;
LMB_Data_Write_14(20) <= \<const0>\;
LMB_Data_Write_14(21) <= \<const0>\;
LMB_Data_Write_14(22) <= \<const0>\;
LMB_Data_Write_14(23) <= \<const0>\;
LMB_Data_Write_14(24) <= \<const0>\;
LMB_Data_Write_14(25) <= \<const0>\;
LMB_Data_Write_14(26) <= \<const0>\;
LMB_Data_Write_14(27) <= \<const0>\;
LMB_Data_Write_14(28) <= \<const0>\;
LMB_Data_Write_14(29) <= \<const0>\;
LMB_Data_Write_14(30) <= \<const0>\;
LMB_Data_Write_14(31) <= \<const0>\;
LMB_Data_Write_15(0) <= \<const0>\;
LMB_Data_Write_15(1) <= \<const0>\;
LMB_Data_Write_15(2) <= \<const0>\;
LMB_Data_Write_15(3) <= \<const0>\;
LMB_Data_Write_15(4) <= \<const0>\;
LMB_Data_Write_15(5) <= \<const0>\;
LMB_Data_Write_15(6) <= \<const0>\;
LMB_Data_Write_15(7) <= \<const0>\;
LMB_Data_Write_15(8) <= \<const0>\;
LMB_Data_Write_15(9) <= \<const0>\;
LMB_Data_Write_15(10) <= \<const0>\;
LMB_Data_Write_15(11) <= \<const0>\;
LMB_Data_Write_15(12) <= \<const0>\;
LMB_Data_Write_15(13) <= \<const0>\;
LMB_Data_Write_15(14) <= \<const0>\;
LMB_Data_Write_15(15) <= \<const0>\;
LMB_Data_Write_15(16) <= \<const0>\;
LMB_Data_Write_15(17) <= \<const0>\;
LMB_Data_Write_15(18) <= \<const0>\;
LMB_Data_Write_15(19) <= \<const0>\;
LMB_Data_Write_15(20) <= \<const0>\;
LMB_Data_Write_15(21) <= \<const0>\;
LMB_Data_Write_15(22) <= \<const0>\;
LMB_Data_Write_15(23) <= \<const0>\;
LMB_Data_Write_15(24) <= \<const0>\;
LMB_Data_Write_15(25) <= \<const0>\;
LMB_Data_Write_15(26) <= \<const0>\;
LMB_Data_Write_15(27) <= \<const0>\;
LMB_Data_Write_15(28) <= \<const0>\;
LMB_Data_Write_15(29) <= \<const0>\;
LMB_Data_Write_15(30) <= \<const0>\;
LMB_Data_Write_15(31) <= \<const0>\;
LMB_Data_Write_16(0) <= \<const0>\;
LMB_Data_Write_16(1) <= \<const0>\;
LMB_Data_Write_16(2) <= \<const0>\;
LMB_Data_Write_16(3) <= \<const0>\;
LMB_Data_Write_16(4) <= \<const0>\;
LMB_Data_Write_16(5) <= \<const0>\;
LMB_Data_Write_16(6) <= \<const0>\;
LMB_Data_Write_16(7) <= \<const0>\;
LMB_Data_Write_16(8) <= \<const0>\;
LMB_Data_Write_16(9) <= \<const0>\;
LMB_Data_Write_16(10) <= \<const0>\;
LMB_Data_Write_16(11) <= \<const0>\;
LMB_Data_Write_16(12) <= \<const0>\;
LMB_Data_Write_16(13) <= \<const0>\;
LMB_Data_Write_16(14) <= \<const0>\;
LMB_Data_Write_16(15) <= \<const0>\;
LMB_Data_Write_16(16) <= \<const0>\;
LMB_Data_Write_16(17) <= \<const0>\;
LMB_Data_Write_16(18) <= \<const0>\;
LMB_Data_Write_16(19) <= \<const0>\;
LMB_Data_Write_16(20) <= \<const0>\;
LMB_Data_Write_16(21) <= \<const0>\;
LMB_Data_Write_16(22) <= \<const0>\;
LMB_Data_Write_16(23) <= \<const0>\;
LMB_Data_Write_16(24) <= \<const0>\;
LMB_Data_Write_16(25) <= \<const0>\;
LMB_Data_Write_16(26) <= \<const0>\;
LMB_Data_Write_16(27) <= \<const0>\;
LMB_Data_Write_16(28) <= \<const0>\;
LMB_Data_Write_16(29) <= \<const0>\;
LMB_Data_Write_16(30) <= \<const0>\;
LMB_Data_Write_16(31) <= \<const0>\;
LMB_Data_Write_17(0) <= \<const0>\;
LMB_Data_Write_17(1) <= \<const0>\;
LMB_Data_Write_17(2) <= \<const0>\;
LMB_Data_Write_17(3) <= \<const0>\;
LMB_Data_Write_17(4) <= \<const0>\;
LMB_Data_Write_17(5) <= \<const0>\;
LMB_Data_Write_17(6) <= \<const0>\;
LMB_Data_Write_17(7) <= \<const0>\;
LMB_Data_Write_17(8) <= \<const0>\;
LMB_Data_Write_17(9) <= \<const0>\;
LMB_Data_Write_17(10) <= \<const0>\;
LMB_Data_Write_17(11) <= \<const0>\;
LMB_Data_Write_17(12) <= \<const0>\;
LMB_Data_Write_17(13) <= \<const0>\;
LMB_Data_Write_17(14) <= \<const0>\;
LMB_Data_Write_17(15) <= \<const0>\;
LMB_Data_Write_17(16) <= \<const0>\;
LMB_Data_Write_17(17) <= \<const0>\;
LMB_Data_Write_17(18) <= \<const0>\;
LMB_Data_Write_17(19) <= \<const0>\;
LMB_Data_Write_17(20) <= \<const0>\;
LMB_Data_Write_17(21) <= \<const0>\;
LMB_Data_Write_17(22) <= \<const0>\;
LMB_Data_Write_17(23) <= \<const0>\;
LMB_Data_Write_17(24) <= \<const0>\;
LMB_Data_Write_17(25) <= \<const0>\;
LMB_Data_Write_17(26) <= \<const0>\;
LMB_Data_Write_17(27) <= \<const0>\;
LMB_Data_Write_17(28) <= \<const0>\;
LMB_Data_Write_17(29) <= \<const0>\;
LMB_Data_Write_17(30) <= \<const0>\;
LMB_Data_Write_17(31) <= \<const0>\;
LMB_Data_Write_18(0) <= \<const0>\;
LMB_Data_Write_18(1) <= \<const0>\;
LMB_Data_Write_18(2) <= \<const0>\;
LMB_Data_Write_18(3) <= \<const0>\;
LMB_Data_Write_18(4) <= \<const0>\;
LMB_Data_Write_18(5) <= \<const0>\;
LMB_Data_Write_18(6) <= \<const0>\;
LMB_Data_Write_18(7) <= \<const0>\;
LMB_Data_Write_18(8) <= \<const0>\;
LMB_Data_Write_18(9) <= \<const0>\;
LMB_Data_Write_18(10) <= \<const0>\;
LMB_Data_Write_18(11) <= \<const0>\;
LMB_Data_Write_18(12) <= \<const0>\;
LMB_Data_Write_18(13) <= \<const0>\;
LMB_Data_Write_18(14) <= \<const0>\;
LMB_Data_Write_18(15) <= \<const0>\;
LMB_Data_Write_18(16) <= \<const0>\;
LMB_Data_Write_18(17) <= \<const0>\;
LMB_Data_Write_18(18) <= \<const0>\;
LMB_Data_Write_18(19) <= \<const0>\;
LMB_Data_Write_18(20) <= \<const0>\;
LMB_Data_Write_18(21) <= \<const0>\;
LMB_Data_Write_18(22) <= \<const0>\;
LMB_Data_Write_18(23) <= \<const0>\;
LMB_Data_Write_18(24) <= \<const0>\;
LMB_Data_Write_18(25) <= \<const0>\;
LMB_Data_Write_18(26) <= \<const0>\;
LMB_Data_Write_18(27) <= \<const0>\;
LMB_Data_Write_18(28) <= \<const0>\;
LMB_Data_Write_18(29) <= \<const0>\;
LMB_Data_Write_18(30) <= \<const0>\;
LMB_Data_Write_18(31) <= \<const0>\;
LMB_Data_Write_19(0) <= \<const0>\;
LMB_Data_Write_19(1) <= \<const0>\;
LMB_Data_Write_19(2) <= \<const0>\;
LMB_Data_Write_19(3) <= \<const0>\;
LMB_Data_Write_19(4) <= \<const0>\;
LMB_Data_Write_19(5) <= \<const0>\;
LMB_Data_Write_19(6) <= \<const0>\;
LMB_Data_Write_19(7) <= \<const0>\;
LMB_Data_Write_19(8) <= \<const0>\;
LMB_Data_Write_19(9) <= \<const0>\;
LMB_Data_Write_19(10) <= \<const0>\;
LMB_Data_Write_19(11) <= \<const0>\;
LMB_Data_Write_19(12) <= \<const0>\;
LMB_Data_Write_19(13) <= \<const0>\;
LMB_Data_Write_19(14) <= \<const0>\;
LMB_Data_Write_19(15) <= \<const0>\;
LMB_Data_Write_19(16) <= \<const0>\;
LMB_Data_Write_19(17) <= \<const0>\;
LMB_Data_Write_19(18) <= \<const0>\;
LMB_Data_Write_19(19) <= \<const0>\;
LMB_Data_Write_19(20) <= \<const0>\;
LMB_Data_Write_19(21) <= \<const0>\;
LMB_Data_Write_19(22) <= \<const0>\;
LMB_Data_Write_19(23) <= \<const0>\;
LMB_Data_Write_19(24) <= \<const0>\;
LMB_Data_Write_19(25) <= \<const0>\;
LMB_Data_Write_19(26) <= \<const0>\;
LMB_Data_Write_19(27) <= \<const0>\;
LMB_Data_Write_19(28) <= \<const0>\;
LMB_Data_Write_19(29) <= \<const0>\;
LMB_Data_Write_19(30) <= \<const0>\;
LMB_Data_Write_19(31) <= \<const0>\;
LMB_Data_Write_2(0) <= \<const0>\;
LMB_Data_Write_2(1) <= \<const0>\;
LMB_Data_Write_2(2) <= \<const0>\;
LMB_Data_Write_2(3) <= \<const0>\;
LMB_Data_Write_2(4) <= \<const0>\;
LMB_Data_Write_2(5) <= \<const0>\;
LMB_Data_Write_2(6) <= \<const0>\;
LMB_Data_Write_2(7) <= \<const0>\;
LMB_Data_Write_2(8) <= \<const0>\;
LMB_Data_Write_2(9) <= \<const0>\;
LMB_Data_Write_2(10) <= \<const0>\;
LMB_Data_Write_2(11) <= \<const0>\;
LMB_Data_Write_2(12) <= \<const0>\;
LMB_Data_Write_2(13) <= \<const0>\;
LMB_Data_Write_2(14) <= \<const0>\;
LMB_Data_Write_2(15) <= \<const0>\;
LMB_Data_Write_2(16) <= \<const0>\;
LMB_Data_Write_2(17) <= \<const0>\;
LMB_Data_Write_2(18) <= \<const0>\;
LMB_Data_Write_2(19) <= \<const0>\;
LMB_Data_Write_2(20) <= \<const0>\;
LMB_Data_Write_2(21) <= \<const0>\;
LMB_Data_Write_2(22) <= \<const0>\;
LMB_Data_Write_2(23) <= \<const0>\;
LMB_Data_Write_2(24) <= \<const0>\;
LMB_Data_Write_2(25) <= \<const0>\;
LMB_Data_Write_2(26) <= \<const0>\;
LMB_Data_Write_2(27) <= \<const0>\;
LMB_Data_Write_2(28) <= \<const0>\;
LMB_Data_Write_2(29) <= \<const0>\;
LMB_Data_Write_2(30) <= \<const0>\;
LMB_Data_Write_2(31) <= \<const0>\;
LMB_Data_Write_20(0) <= \<const0>\;
LMB_Data_Write_20(1) <= \<const0>\;
LMB_Data_Write_20(2) <= \<const0>\;
LMB_Data_Write_20(3) <= \<const0>\;
LMB_Data_Write_20(4) <= \<const0>\;
LMB_Data_Write_20(5) <= \<const0>\;
LMB_Data_Write_20(6) <= \<const0>\;
LMB_Data_Write_20(7) <= \<const0>\;
LMB_Data_Write_20(8) <= \<const0>\;
LMB_Data_Write_20(9) <= \<const0>\;
LMB_Data_Write_20(10) <= \<const0>\;
LMB_Data_Write_20(11) <= \<const0>\;
LMB_Data_Write_20(12) <= \<const0>\;
LMB_Data_Write_20(13) <= \<const0>\;
LMB_Data_Write_20(14) <= \<const0>\;
LMB_Data_Write_20(15) <= \<const0>\;
LMB_Data_Write_20(16) <= \<const0>\;
LMB_Data_Write_20(17) <= \<const0>\;
LMB_Data_Write_20(18) <= \<const0>\;
LMB_Data_Write_20(19) <= \<const0>\;
LMB_Data_Write_20(20) <= \<const0>\;
LMB_Data_Write_20(21) <= \<const0>\;
LMB_Data_Write_20(22) <= \<const0>\;
LMB_Data_Write_20(23) <= \<const0>\;
LMB_Data_Write_20(24) <= \<const0>\;
LMB_Data_Write_20(25) <= \<const0>\;
LMB_Data_Write_20(26) <= \<const0>\;
LMB_Data_Write_20(27) <= \<const0>\;
LMB_Data_Write_20(28) <= \<const0>\;
LMB_Data_Write_20(29) <= \<const0>\;
LMB_Data_Write_20(30) <= \<const0>\;
LMB_Data_Write_20(31) <= \<const0>\;
LMB_Data_Write_21(0) <= \<const0>\;
LMB_Data_Write_21(1) <= \<const0>\;
LMB_Data_Write_21(2) <= \<const0>\;
LMB_Data_Write_21(3) <= \<const0>\;
LMB_Data_Write_21(4) <= \<const0>\;
LMB_Data_Write_21(5) <= \<const0>\;
LMB_Data_Write_21(6) <= \<const0>\;
LMB_Data_Write_21(7) <= \<const0>\;
LMB_Data_Write_21(8) <= \<const0>\;
LMB_Data_Write_21(9) <= \<const0>\;
LMB_Data_Write_21(10) <= \<const0>\;
LMB_Data_Write_21(11) <= \<const0>\;
LMB_Data_Write_21(12) <= \<const0>\;
LMB_Data_Write_21(13) <= \<const0>\;
LMB_Data_Write_21(14) <= \<const0>\;
LMB_Data_Write_21(15) <= \<const0>\;
LMB_Data_Write_21(16) <= \<const0>\;
LMB_Data_Write_21(17) <= \<const0>\;
LMB_Data_Write_21(18) <= \<const0>\;
LMB_Data_Write_21(19) <= \<const0>\;
LMB_Data_Write_21(20) <= \<const0>\;
LMB_Data_Write_21(21) <= \<const0>\;
LMB_Data_Write_21(22) <= \<const0>\;
LMB_Data_Write_21(23) <= \<const0>\;
LMB_Data_Write_21(24) <= \<const0>\;
LMB_Data_Write_21(25) <= \<const0>\;
LMB_Data_Write_21(26) <= \<const0>\;
LMB_Data_Write_21(27) <= \<const0>\;
LMB_Data_Write_21(28) <= \<const0>\;
LMB_Data_Write_21(29) <= \<const0>\;
LMB_Data_Write_21(30) <= \<const0>\;
LMB_Data_Write_21(31) <= \<const0>\;
LMB_Data_Write_22(0) <= \<const0>\;
LMB_Data_Write_22(1) <= \<const0>\;
LMB_Data_Write_22(2) <= \<const0>\;
LMB_Data_Write_22(3) <= \<const0>\;
LMB_Data_Write_22(4) <= \<const0>\;
LMB_Data_Write_22(5) <= \<const0>\;
LMB_Data_Write_22(6) <= \<const0>\;
LMB_Data_Write_22(7) <= \<const0>\;
LMB_Data_Write_22(8) <= \<const0>\;
LMB_Data_Write_22(9) <= \<const0>\;
LMB_Data_Write_22(10) <= \<const0>\;
LMB_Data_Write_22(11) <= \<const0>\;
LMB_Data_Write_22(12) <= \<const0>\;
LMB_Data_Write_22(13) <= \<const0>\;
LMB_Data_Write_22(14) <= \<const0>\;
LMB_Data_Write_22(15) <= \<const0>\;
LMB_Data_Write_22(16) <= \<const0>\;
LMB_Data_Write_22(17) <= \<const0>\;
LMB_Data_Write_22(18) <= \<const0>\;
LMB_Data_Write_22(19) <= \<const0>\;
LMB_Data_Write_22(20) <= \<const0>\;
LMB_Data_Write_22(21) <= \<const0>\;
LMB_Data_Write_22(22) <= \<const0>\;
LMB_Data_Write_22(23) <= \<const0>\;
LMB_Data_Write_22(24) <= \<const0>\;
LMB_Data_Write_22(25) <= \<const0>\;
LMB_Data_Write_22(26) <= \<const0>\;
LMB_Data_Write_22(27) <= \<const0>\;
LMB_Data_Write_22(28) <= \<const0>\;
LMB_Data_Write_22(29) <= \<const0>\;
LMB_Data_Write_22(30) <= \<const0>\;
LMB_Data_Write_22(31) <= \<const0>\;
LMB_Data_Write_23(0) <= \<const0>\;
LMB_Data_Write_23(1) <= \<const0>\;
LMB_Data_Write_23(2) <= \<const0>\;
LMB_Data_Write_23(3) <= \<const0>\;
LMB_Data_Write_23(4) <= \<const0>\;
LMB_Data_Write_23(5) <= \<const0>\;
LMB_Data_Write_23(6) <= \<const0>\;
LMB_Data_Write_23(7) <= \<const0>\;
LMB_Data_Write_23(8) <= \<const0>\;
LMB_Data_Write_23(9) <= \<const0>\;
LMB_Data_Write_23(10) <= \<const0>\;
LMB_Data_Write_23(11) <= \<const0>\;
LMB_Data_Write_23(12) <= \<const0>\;
LMB_Data_Write_23(13) <= \<const0>\;
LMB_Data_Write_23(14) <= \<const0>\;
LMB_Data_Write_23(15) <= \<const0>\;
LMB_Data_Write_23(16) <= \<const0>\;
LMB_Data_Write_23(17) <= \<const0>\;
LMB_Data_Write_23(18) <= \<const0>\;
LMB_Data_Write_23(19) <= \<const0>\;
LMB_Data_Write_23(20) <= \<const0>\;
LMB_Data_Write_23(21) <= \<const0>\;
LMB_Data_Write_23(22) <= \<const0>\;
LMB_Data_Write_23(23) <= \<const0>\;
LMB_Data_Write_23(24) <= \<const0>\;
LMB_Data_Write_23(25) <= \<const0>\;
LMB_Data_Write_23(26) <= \<const0>\;
LMB_Data_Write_23(27) <= \<const0>\;
LMB_Data_Write_23(28) <= \<const0>\;
LMB_Data_Write_23(29) <= \<const0>\;
LMB_Data_Write_23(30) <= \<const0>\;
LMB_Data_Write_23(31) <= \<const0>\;
LMB_Data_Write_24(0) <= \<const0>\;
LMB_Data_Write_24(1) <= \<const0>\;
LMB_Data_Write_24(2) <= \<const0>\;
LMB_Data_Write_24(3) <= \<const0>\;
LMB_Data_Write_24(4) <= \<const0>\;
LMB_Data_Write_24(5) <= \<const0>\;
LMB_Data_Write_24(6) <= \<const0>\;
LMB_Data_Write_24(7) <= \<const0>\;
LMB_Data_Write_24(8) <= \<const0>\;
LMB_Data_Write_24(9) <= \<const0>\;
LMB_Data_Write_24(10) <= \<const0>\;
LMB_Data_Write_24(11) <= \<const0>\;
LMB_Data_Write_24(12) <= \<const0>\;
LMB_Data_Write_24(13) <= \<const0>\;
LMB_Data_Write_24(14) <= \<const0>\;
LMB_Data_Write_24(15) <= \<const0>\;
LMB_Data_Write_24(16) <= \<const0>\;
LMB_Data_Write_24(17) <= \<const0>\;
LMB_Data_Write_24(18) <= \<const0>\;
LMB_Data_Write_24(19) <= \<const0>\;
LMB_Data_Write_24(20) <= \<const0>\;
LMB_Data_Write_24(21) <= \<const0>\;
LMB_Data_Write_24(22) <= \<const0>\;
LMB_Data_Write_24(23) <= \<const0>\;
LMB_Data_Write_24(24) <= \<const0>\;
LMB_Data_Write_24(25) <= \<const0>\;
LMB_Data_Write_24(26) <= \<const0>\;
LMB_Data_Write_24(27) <= \<const0>\;
LMB_Data_Write_24(28) <= \<const0>\;
LMB_Data_Write_24(29) <= \<const0>\;
LMB_Data_Write_24(30) <= \<const0>\;
LMB_Data_Write_24(31) <= \<const0>\;
LMB_Data_Write_25(0) <= \<const0>\;
LMB_Data_Write_25(1) <= \<const0>\;
LMB_Data_Write_25(2) <= \<const0>\;
LMB_Data_Write_25(3) <= \<const0>\;
LMB_Data_Write_25(4) <= \<const0>\;
LMB_Data_Write_25(5) <= \<const0>\;
LMB_Data_Write_25(6) <= \<const0>\;
LMB_Data_Write_25(7) <= \<const0>\;
LMB_Data_Write_25(8) <= \<const0>\;
LMB_Data_Write_25(9) <= \<const0>\;
LMB_Data_Write_25(10) <= \<const0>\;
LMB_Data_Write_25(11) <= \<const0>\;
LMB_Data_Write_25(12) <= \<const0>\;
LMB_Data_Write_25(13) <= \<const0>\;
LMB_Data_Write_25(14) <= \<const0>\;
LMB_Data_Write_25(15) <= \<const0>\;
LMB_Data_Write_25(16) <= \<const0>\;
LMB_Data_Write_25(17) <= \<const0>\;
LMB_Data_Write_25(18) <= \<const0>\;
LMB_Data_Write_25(19) <= \<const0>\;
LMB_Data_Write_25(20) <= \<const0>\;
LMB_Data_Write_25(21) <= \<const0>\;
LMB_Data_Write_25(22) <= \<const0>\;
LMB_Data_Write_25(23) <= \<const0>\;
LMB_Data_Write_25(24) <= \<const0>\;
LMB_Data_Write_25(25) <= \<const0>\;
LMB_Data_Write_25(26) <= \<const0>\;
LMB_Data_Write_25(27) <= \<const0>\;
LMB_Data_Write_25(28) <= \<const0>\;
LMB_Data_Write_25(29) <= \<const0>\;
LMB_Data_Write_25(30) <= \<const0>\;
LMB_Data_Write_25(31) <= \<const0>\;
LMB_Data_Write_26(0) <= \<const0>\;
LMB_Data_Write_26(1) <= \<const0>\;
LMB_Data_Write_26(2) <= \<const0>\;
LMB_Data_Write_26(3) <= \<const0>\;
LMB_Data_Write_26(4) <= \<const0>\;
LMB_Data_Write_26(5) <= \<const0>\;
LMB_Data_Write_26(6) <= \<const0>\;
LMB_Data_Write_26(7) <= \<const0>\;
LMB_Data_Write_26(8) <= \<const0>\;
LMB_Data_Write_26(9) <= \<const0>\;
LMB_Data_Write_26(10) <= \<const0>\;
LMB_Data_Write_26(11) <= \<const0>\;
LMB_Data_Write_26(12) <= \<const0>\;
LMB_Data_Write_26(13) <= \<const0>\;
LMB_Data_Write_26(14) <= \<const0>\;
LMB_Data_Write_26(15) <= \<const0>\;
LMB_Data_Write_26(16) <= \<const0>\;
LMB_Data_Write_26(17) <= \<const0>\;
LMB_Data_Write_26(18) <= \<const0>\;
LMB_Data_Write_26(19) <= \<const0>\;
LMB_Data_Write_26(20) <= \<const0>\;
LMB_Data_Write_26(21) <= \<const0>\;
LMB_Data_Write_26(22) <= \<const0>\;
LMB_Data_Write_26(23) <= \<const0>\;
LMB_Data_Write_26(24) <= \<const0>\;
LMB_Data_Write_26(25) <= \<const0>\;
LMB_Data_Write_26(26) <= \<const0>\;
LMB_Data_Write_26(27) <= \<const0>\;
LMB_Data_Write_26(28) <= \<const0>\;
LMB_Data_Write_26(29) <= \<const0>\;
LMB_Data_Write_26(30) <= \<const0>\;
LMB_Data_Write_26(31) <= \<const0>\;
LMB_Data_Write_27(0) <= \<const0>\;
LMB_Data_Write_27(1) <= \<const0>\;
LMB_Data_Write_27(2) <= \<const0>\;
LMB_Data_Write_27(3) <= \<const0>\;
LMB_Data_Write_27(4) <= \<const0>\;
LMB_Data_Write_27(5) <= \<const0>\;
LMB_Data_Write_27(6) <= \<const0>\;
LMB_Data_Write_27(7) <= \<const0>\;
LMB_Data_Write_27(8) <= \<const0>\;
LMB_Data_Write_27(9) <= \<const0>\;
LMB_Data_Write_27(10) <= \<const0>\;
LMB_Data_Write_27(11) <= \<const0>\;
LMB_Data_Write_27(12) <= \<const0>\;
LMB_Data_Write_27(13) <= \<const0>\;
LMB_Data_Write_27(14) <= \<const0>\;
LMB_Data_Write_27(15) <= \<const0>\;
LMB_Data_Write_27(16) <= \<const0>\;
LMB_Data_Write_27(17) <= \<const0>\;
LMB_Data_Write_27(18) <= \<const0>\;
LMB_Data_Write_27(19) <= \<const0>\;
LMB_Data_Write_27(20) <= \<const0>\;
LMB_Data_Write_27(21) <= \<const0>\;
LMB_Data_Write_27(22) <= \<const0>\;
LMB_Data_Write_27(23) <= \<const0>\;
LMB_Data_Write_27(24) <= \<const0>\;
LMB_Data_Write_27(25) <= \<const0>\;
LMB_Data_Write_27(26) <= \<const0>\;
LMB_Data_Write_27(27) <= \<const0>\;
LMB_Data_Write_27(28) <= \<const0>\;
LMB_Data_Write_27(29) <= \<const0>\;
LMB_Data_Write_27(30) <= \<const0>\;
LMB_Data_Write_27(31) <= \<const0>\;
LMB_Data_Write_28(0) <= \<const0>\;
LMB_Data_Write_28(1) <= \<const0>\;
LMB_Data_Write_28(2) <= \<const0>\;
LMB_Data_Write_28(3) <= \<const0>\;
LMB_Data_Write_28(4) <= \<const0>\;
LMB_Data_Write_28(5) <= \<const0>\;
LMB_Data_Write_28(6) <= \<const0>\;
LMB_Data_Write_28(7) <= \<const0>\;
LMB_Data_Write_28(8) <= \<const0>\;
LMB_Data_Write_28(9) <= \<const0>\;
LMB_Data_Write_28(10) <= \<const0>\;
LMB_Data_Write_28(11) <= \<const0>\;
LMB_Data_Write_28(12) <= \<const0>\;
LMB_Data_Write_28(13) <= \<const0>\;
LMB_Data_Write_28(14) <= \<const0>\;
LMB_Data_Write_28(15) <= \<const0>\;
LMB_Data_Write_28(16) <= \<const0>\;
LMB_Data_Write_28(17) <= \<const0>\;
LMB_Data_Write_28(18) <= \<const0>\;
LMB_Data_Write_28(19) <= \<const0>\;
LMB_Data_Write_28(20) <= \<const0>\;
LMB_Data_Write_28(21) <= \<const0>\;
LMB_Data_Write_28(22) <= \<const0>\;
LMB_Data_Write_28(23) <= \<const0>\;
LMB_Data_Write_28(24) <= \<const0>\;
LMB_Data_Write_28(25) <= \<const0>\;
LMB_Data_Write_28(26) <= \<const0>\;
LMB_Data_Write_28(27) <= \<const0>\;
LMB_Data_Write_28(28) <= \<const0>\;
LMB_Data_Write_28(29) <= \<const0>\;
LMB_Data_Write_28(30) <= \<const0>\;
LMB_Data_Write_28(31) <= \<const0>\;
LMB_Data_Write_29(0) <= \<const0>\;
LMB_Data_Write_29(1) <= \<const0>\;
LMB_Data_Write_29(2) <= \<const0>\;
LMB_Data_Write_29(3) <= \<const0>\;
LMB_Data_Write_29(4) <= \<const0>\;
LMB_Data_Write_29(5) <= \<const0>\;
LMB_Data_Write_29(6) <= \<const0>\;
LMB_Data_Write_29(7) <= \<const0>\;
LMB_Data_Write_29(8) <= \<const0>\;
LMB_Data_Write_29(9) <= \<const0>\;
LMB_Data_Write_29(10) <= \<const0>\;
LMB_Data_Write_29(11) <= \<const0>\;
LMB_Data_Write_29(12) <= \<const0>\;
LMB_Data_Write_29(13) <= \<const0>\;
LMB_Data_Write_29(14) <= \<const0>\;
LMB_Data_Write_29(15) <= \<const0>\;
LMB_Data_Write_29(16) <= \<const0>\;
LMB_Data_Write_29(17) <= \<const0>\;
LMB_Data_Write_29(18) <= \<const0>\;
LMB_Data_Write_29(19) <= \<const0>\;
LMB_Data_Write_29(20) <= \<const0>\;
LMB_Data_Write_29(21) <= \<const0>\;
LMB_Data_Write_29(22) <= \<const0>\;
LMB_Data_Write_29(23) <= \<const0>\;
LMB_Data_Write_29(24) <= \<const0>\;
LMB_Data_Write_29(25) <= \<const0>\;
LMB_Data_Write_29(26) <= \<const0>\;
LMB_Data_Write_29(27) <= \<const0>\;
LMB_Data_Write_29(28) <= \<const0>\;
LMB_Data_Write_29(29) <= \<const0>\;
LMB_Data_Write_29(30) <= \<const0>\;
LMB_Data_Write_29(31) <= \<const0>\;
LMB_Data_Write_3(0) <= \<const0>\;
LMB_Data_Write_3(1) <= \<const0>\;
LMB_Data_Write_3(2) <= \<const0>\;
LMB_Data_Write_3(3) <= \<const0>\;
LMB_Data_Write_3(4) <= \<const0>\;
LMB_Data_Write_3(5) <= \<const0>\;
LMB_Data_Write_3(6) <= \<const0>\;
LMB_Data_Write_3(7) <= \<const0>\;
LMB_Data_Write_3(8) <= \<const0>\;
LMB_Data_Write_3(9) <= \<const0>\;
LMB_Data_Write_3(10) <= \<const0>\;
LMB_Data_Write_3(11) <= \<const0>\;
LMB_Data_Write_3(12) <= \<const0>\;
LMB_Data_Write_3(13) <= \<const0>\;
LMB_Data_Write_3(14) <= \<const0>\;
LMB_Data_Write_3(15) <= \<const0>\;
LMB_Data_Write_3(16) <= \<const0>\;
LMB_Data_Write_3(17) <= \<const0>\;
LMB_Data_Write_3(18) <= \<const0>\;
LMB_Data_Write_3(19) <= \<const0>\;
LMB_Data_Write_3(20) <= \<const0>\;
LMB_Data_Write_3(21) <= \<const0>\;
LMB_Data_Write_3(22) <= \<const0>\;
LMB_Data_Write_3(23) <= \<const0>\;
LMB_Data_Write_3(24) <= \<const0>\;
LMB_Data_Write_3(25) <= \<const0>\;
LMB_Data_Write_3(26) <= \<const0>\;
LMB_Data_Write_3(27) <= \<const0>\;
LMB_Data_Write_3(28) <= \<const0>\;
LMB_Data_Write_3(29) <= \<const0>\;
LMB_Data_Write_3(30) <= \<const0>\;
LMB_Data_Write_3(31) <= \<const0>\;
LMB_Data_Write_30(0) <= \<const0>\;
LMB_Data_Write_30(1) <= \<const0>\;
LMB_Data_Write_30(2) <= \<const0>\;
LMB_Data_Write_30(3) <= \<const0>\;
LMB_Data_Write_30(4) <= \<const0>\;
LMB_Data_Write_30(5) <= \<const0>\;
LMB_Data_Write_30(6) <= \<const0>\;
LMB_Data_Write_30(7) <= \<const0>\;
LMB_Data_Write_30(8) <= \<const0>\;
LMB_Data_Write_30(9) <= \<const0>\;
LMB_Data_Write_30(10) <= \<const0>\;
LMB_Data_Write_30(11) <= \<const0>\;
LMB_Data_Write_30(12) <= \<const0>\;
LMB_Data_Write_30(13) <= \<const0>\;
LMB_Data_Write_30(14) <= \<const0>\;
LMB_Data_Write_30(15) <= \<const0>\;
LMB_Data_Write_30(16) <= \<const0>\;
LMB_Data_Write_30(17) <= \<const0>\;
LMB_Data_Write_30(18) <= \<const0>\;
LMB_Data_Write_30(19) <= \<const0>\;
LMB_Data_Write_30(20) <= \<const0>\;
LMB_Data_Write_30(21) <= \<const0>\;
LMB_Data_Write_30(22) <= \<const0>\;
LMB_Data_Write_30(23) <= \<const0>\;
LMB_Data_Write_30(24) <= \<const0>\;
LMB_Data_Write_30(25) <= \<const0>\;
LMB_Data_Write_30(26) <= \<const0>\;
LMB_Data_Write_30(27) <= \<const0>\;
LMB_Data_Write_30(28) <= \<const0>\;
LMB_Data_Write_30(29) <= \<const0>\;
LMB_Data_Write_30(30) <= \<const0>\;
LMB_Data_Write_30(31) <= \<const0>\;
LMB_Data_Write_31(0) <= \<const0>\;
LMB_Data_Write_31(1) <= \<const0>\;
LMB_Data_Write_31(2) <= \<const0>\;
LMB_Data_Write_31(3) <= \<const0>\;
LMB_Data_Write_31(4) <= \<const0>\;
LMB_Data_Write_31(5) <= \<const0>\;
LMB_Data_Write_31(6) <= \<const0>\;
LMB_Data_Write_31(7) <= \<const0>\;
LMB_Data_Write_31(8) <= \<const0>\;
LMB_Data_Write_31(9) <= \<const0>\;
LMB_Data_Write_31(10) <= \<const0>\;
LMB_Data_Write_31(11) <= \<const0>\;
LMB_Data_Write_31(12) <= \<const0>\;
LMB_Data_Write_31(13) <= \<const0>\;
LMB_Data_Write_31(14) <= \<const0>\;
LMB_Data_Write_31(15) <= \<const0>\;
LMB_Data_Write_31(16) <= \<const0>\;
LMB_Data_Write_31(17) <= \<const0>\;
LMB_Data_Write_31(18) <= \<const0>\;
LMB_Data_Write_31(19) <= \<const0>\;
LMB_Data_Write_31(20) <= \<const0>\;
LMB_Data_Write_31(21) <= \<const0>\;
LMB_Data_Write_31(22) <= \<const0>\;
LMB_Data_Write_31(23) <= \<const0>\;
LMB_Data_Write_31(24) <= \<const0>\;
LMB_Data_Write_31(25) <= \<const0>\;
LMB_Data_Write_31(26) <= \<const0>\;
LMB_Data_Write_31(27) <= \<const0>\;
LMB_Data_Write_31(28) <= \<const0>\;
LMB_Data_Write_31(29) <= \<const0>\;
LMB_Data_Write_31(30) <= \<const0>\;
LMB_Data_Write_31(31) <= \<const0>\;
LMB_Data_Write_4(0) <= \<const0>\;
LMB_Data_Write_4(1) <= \<const0>\;
LMB_Data_Write_4(2) <= \<const0>\;
LMB_Data_Write_4(3) <= \<const0>\;
LMB_Data_Write_4(4) <= \<const0>\;
LMB_Data_Write_4(5) <= \<const0>\;
LMB_Data_Write_4(6) <= \<const0>\;
LMB_Data_Write_4(7) <= \<const0>\;
LMB_Data_Write_4(8) <= \<const0>\;
LMB_Data_Write_4(9) <= \<const0>\;
LMB_Data_Write_4(10) <= \<const0>\;
LMB_Data_Write_4(11) <= \<const0>\;
LMB_Data_Write_4(12) <= \<const0>\;
LMB_Data_Write_4(13) <= \<const0>\;
LMB_Data_Write_4(14) <= \<const0>\;
LMB_Data_Write_4(15) <= \<const0>\;
LMB_Data_Write_4(16) <= \<const0>\;
LMB_Data_Write_4(17) <= \<const0>\;
LMB_Data_Write_4(18) <= \<const0>\;
LMB_Data_Write_4(19) <= \<const0>\;
LMB_Data_Write_4(20) <= \<const0>\;
LMB_Data_Write_4(21) <= \<const0>\;
LMB_Data_Write_4(22) <= \<const0>\;
LMB_Data_Write_4(23) <= \<const0>\;
LMB_Data_Write_4(24) <= \<const0>\;
LMB_Data_Write_4(25) <= \<const0>\;
LMB_Data_Write_4(26) <= \<const0>\;
LMB_Data_Write_4(27) <= \<const0>\;
LMB_Data_Write_4(28) <= \<const0>\;
LMB_Data_Write_4(29) <= \<const0>\;
LMB_Data_Write_4(30) <= \<const0>\;
LMB_Data_Write_4(31) <= \<const0>\;
LMB_Data_Write_5(0) <= \<const0>\;
LMB_Data_Write_5(1) <= \<const0>\;
LMB_Data_Write_5(2) <= \<const0>\;
LMB_Data_Write_5(3) <= \<const0>\;
LMB_Data_Write_5(4) <= \<const0>\;
LMB_Data_Write_5(5) <= \<const0>\;
LMB_Data_Write_5(6) <= \<const0>\;
LMB_Data_Write_5(7) <= \<const0>\;
LMB_Data_Write_5(8) <= \<const0>\;
LMB_Data_Write_5(9) <= \<const0>\;
LMB_Data_Write_5(10) <= \<const0>\;
LMB_Data_Write_5(11) <= \<const0>\;
LMB_Data_Write_5(12) <= \<const0>\;
LMB_Data_Write_5(13) <= \<const0>\;
LMB_Data_Write_5(14) <= \<const0>\;
LMB_Data_Write_5(15) <= \<const0>\;
LMB_Data_Write_5(16) <= \<const0>\;
LMB_Data_Write_5(17) <= \<const0>\;
LMB_Data_Write_5(18) <= \<const0>\;
LMB_Data_Write_5(19) <= \<const0>\;
LMB_Data_Write_5(20) <= \<const0>\;
LMB_Data_Write_5(21) <= \<const0>\;
LMB_Data_Write_5(22) <= \<const0>\;
LMB_Data_Write_5(23) <= \<const0>\;
LMB_Data_Write_5(24) <= \<const0>\;
LMB_Data_Write_5(25) <= \<const0>\;
LMB_Data_Write_5(26) <= \<const0>\;
LMB_Data_Write_5(27) <= \<const0>\;
LMB_Data_Write_5(28) <= \<const0>\;
LMB_Data_Write_5(29) <= \<const0>\;
LMB_Data_Write_5(30) <= \<const0>\;
LMB_Data_Write_5(31) <= \<const0>\;
LMB_Data_Write_6(0) <= \<const0>\;
LMB_Data_Write_6(1) <= \<const0>\;
LMB_Data_Write_6(2) <= \<const0>\;
LMB_Data_Write_6(3) <= \<const0>\;
LMB_Data_Write_6(4) <= \<const0>\;
LMB_Data_Write_6(5) <= \<const0>\;
LMB_Data_Write_6(6) <= \<const0>\;
LMB_Data_Write_6(7) <= \<const0>\;
LMB_Data_Write_6(8) <= \<const0>\;
LMB_Data_Write_6(9) <= \<const0>\;
LMB_Data_Write_6(10) <= \<const0>\;
LMB_Data_Write_6(11) <= \<const0>\;
LMB_Data_Write_6(12) <= \<const0>\;
LMB_Data_Write_6(13) <= \<const0>\;
LMB_Data_Write_6(14) <= \<const0>\;
LMB_Data_Write_6(15) <= \<const0>\;
LMB_Data_Write_6(16) <= \<const0>\;
LMB_Data_Write_6(17) <= \<const0>\;
LMB_Data_Write_6(18) <= \<const0>\;
LMB_Data_Write_6(19) <= \<const0>\;
LMB_Data_Write_6(20) <= \<const0>\;
LMB_Data_Write_6(21) <= \<const0>\;
LMB_Data_Write_6(22) <= \<const0>\;
LMB_Data_Write_6(23) <= \<const0>\;
LMB_Data_Write_6(24) <= \<const0>\;
LMB_Data_Write_6(25) <= \<const0>\;
LMB_Data_Write_6(26) <= \<const0>\;
LMB_Data_Write_6(27) <= \<const0>\;
LMB_Data_Write_6(28) <= \<const0>\;
LMB_Data_Write_6(29) <= \<const0>\;
LMB_Data_Write_6(30) <= \<const0>\;
LMB_Data_Write_6(31) <= \<const0>\;
LMB_Data_Write_7(0) <= \<const0>\;
LMB_Data_Write_7(1) <= \<const0>\;
LMB_Data_Write_7(2) <= \<const0>\;
LMB_Data_Write_7(3) <= \<const0>\;
LMB_Data_Write_7(4) <= \<const0>\;
LMB_Data_Write_7(5) <= \<const0>\;
LMB_Data_Write_7(6) <= \<const0>\;
LMB_Data_Write_7(7) <= \<const0>\;
LMB_Data_Write_7(8) <= \<const0>\;
LMB_Data_Write_7(9) <= \<const0>\;
LMB_Data_Write_7(10) <= \<const0>\;
LMB_Data_Write_7(11) <= \<const0>\;
LMB_Data_Write_7(12) <= \<const0>\;
LMB_Data_Write_7(13) <= \<const0>\;
LMB_Data_Write_7(14) <= \<const0>\;
LMB_Data_Write_7(15) <= \<const0>\;
LMB_Data_Write_7(16) <= \<const0>\;
LMB_Data_Write_7(17) <= \<const0>\;
LMB_Data_Write_7(18) <= \<const0>\;
LMB_Data_Write_7(19) <= \<const0>\;
LMB_Data_Write_7(20) <= \<const0>\;
LMB_Data_Write_7(21) <= \<const0>\;
LMB_Data_Write_7(22) <= \<const0>\;
LMB_Data_Write_7(23) <= \<const0>\;
LMB_Data_Write_7(24) <= \<const0>\;
LMB_Data_Write_7(25) <= \<const0>\;
LMB_Data_Write_7(26) <= \<const0>\;
LMB_Data_Write_7(27) <= \<const0>\;
LMB_Data_Write_7(28) <= \<const0>\;
LMB_Data_Write_7(29) <= \<const0>\;
LMB_Data_Write_7(30) <= \<const0>\;
LMB_Data_Write_7(31) <= \<const0>\;
LMB_Data_Write_8(0) <= \<const0>\;
LMB_Data_Write_8(1) <= \<const0>\;
LMB_Data_Write_8(2) <= \<const0>\;
LMB_Data_Write_8(3) <= \<const0>\;
LMB_Data_Write_8(4) <= \<const0>\;
LMB_Data_Write_8(5) <= \<const0>\;
LMB_Data_Write_8(6) <= \<const0>\;
LMB_Data_Write_8(7) <= \<const0>\;
LMB_Data_Write_8(8) <= \<const0>\;
LMB_Data_Write_8(9) <= \<const0>\;
LMB_Data_Write_8(10) <= \<const0>\;
LMB_Data_Write_8(11) <= \<const0>\;
LMB_Data_Write_8(12) <= \<const0>\;
LMB_Data_Write_8(13) <= \<const0>\;
LMB_Data_Write_8(14) <= \<const0>\;
LMB_Data_Write_8(15) <= \<const0>\;
LMB_Data_Write_8(16) <= \<const0>\;
LMB_Data_Write_8(17) <= \<const0>\;
LMB_Data_Write_8(18) <= \<const0>\;
LMB_Data_Write_8(19) <= \<const0>\;
LMB_Data_Write_8(20) <= \<const0>\;
LMB_Data_Write_8(21) <= \<const0>\;
LMB_Data_Write_8(22) <= \<const0>\;
LMB_Data_Write_8(23) <= \<const0>\;
LMB_Data_Write_8(24) <= \<const0>\;
LMB_Data_Write_8(25) <= \<const0>\;
LMB_Data_Write_8(26) <= \<const0>\;
LMB_Data_Write_8(27) <= \<const0>\;
LMB_Data_Write_8(28) <= \<const0>\;
LMB_Data_Write_8(29) <= \<const0>\;
LMB_Data_Write_8(30) <= \<const0>\;
LMB_Data_Write_8(31) <= \<const0>\;
LMB_Data_Write_9(0) <= \<const0>\;
LMB_Data_Write_9(1) <= \<const0>\;
LMB_Data_Write_9(2) <= \<const0>\;
LMB_Data_Write_9(3) <= \<const0>\;
LMB_Data_Write_9(4) <= \<const0>\;
LMB_Data_Write_9(5) <= \<const0>\;
LMB_Data_Write_9(6) <= \<const0>\;
LMB_Data_Write_9(7) <= \<const0>\;
LMB_Data_Write_9(8) <= \<const0>\;
LMB_Data_Write_9(9) <= \<const0>\;
LMB_Data_Write_9(10) <= \<const0>\;
LMB_Data_Write_9(11) <= \<const0>\;
LMB_Data_Write_9(12) <= \<const0>\;
LMB_Data_Write_9(13) <= \<const0>\;
LMB_Data_Write_9(14) <= \<const0>\;
LMB_Data_Write_9(15) <= \<const0>\;
LMB_Data_Write_9(16) <= \<const0>\;
LMB_Data_Write_9(17) <= \<const0>\;
LMB_Data_Write_9(18) <= \<const0>\;
LMB_Data_Write_9(19) <= \<const0>\;
LMB_Data_Write_9(20) <= \<const0>\;
LMB_Data_Write_9(21) <= \<const0>\;
LMB_Data_Write_9(22) <= \<const0>\;
LMB_Data_Write_9(23) <= \<const0>\;
LMB_Data_Write_9(24) <= \<const0>\;
LMB_Data_Write_9(25) <= \<const0>\;
LMB_Data_Write_9(26) <= \<const0>\;
LMB_Data_Write_9(27) <= \<const0>\;
LMB_Data_Write_9(28) <= \<const0>\;
LMB_Data_Write_9(29) <= \<const0>\;
LMB_Data_Write_9(30) <= \<const0>\;
LMB_Data_Write_9(31) <= \<const0>\;
LMB_Read_Strobe_0 <= \<const0>\;
LMB_Read_Strobe_1 <= \<const0>\;
LMB_Read_Strobe_10 <= \<const0>\;
LMB_Read_Strobe_11 <= \<const0>\;
LMB_Read_Strobe_12 <= \<const0>\;
LMB_Read_Strobe_13 <= \<const0>\;
LMB_Read_Strobe_14 <= \<const0>\;
LMB_Read_Strobe_15 <= \<const0>\;
LMB_Read_Strobe_16 <= \<const0>\;
LMB_Read_Strobe_17 <= \<const0>\;
LMB_Read_Strobe_18 <= \<const0>\;
LMB_Read_Strobe_19 <= \<const0>\;
LMB_Read_Strobe_2 <= \<const0>\;
LMB_Read_Strobe_20 <= \<const0>\;
LMB_Read_Strobe_21 <= \<const0>\;
LMB_Read_Strobe_22 <= \<const0>\;
LMB_Read_Strobe_23 <= \<const0>\;
LMB_Read_Strobe_24 <= \<const0>\;
LMB_Read_Strobe_25 <= \<const0>\;
LMB_Read_Strobe_26 <= \<const0>\;
LMB_Read_Strobe_27 <= \<const0>\;
LMB_Read_Strobe_28 <= \<const0>\;
LMB_Read_Strobe_29 <= \<const0>\;
LMB_Read_Strobe_3 <= \<const0>\;
LMB_Read_Strobe_30 <= \<const0>\;
LMB_Read_Strobe_31 <= \<const0>\;
LMB_Read_Strobe_4 <= \<const0>\;
LMB_Read_Strobe_5 <= \<const0>\;
LMB_Read_Strobe_6 <= \<const0>\;
LMB_Read_Strobe_7 <= \<const0>\;
LMB_Read_Strobe_8 <= \<const0>\;
LMB_Read_Strobe_9 <= \<const0>\;
LMB_Write_Strobe_0 <= \<const0>\;
LMB_Write_Strobe_1 <= \<const0>\;
LMB_Write_Strobe_10 <= \<const0>\;
LMB_Write_Strobe_11 <= \<const0>\;
LMB_Write_Strobe_12 <= \<const0>\;
LMB_Write_Strobe_13 <= \<const0>\;
LMB_Write_Strobe_14 <= \<const0>\;
LMB_Write_Strobe_15 <= \<const0>\;
LMB_Write_Strobe_16 <= \<const0>\;
LMB_Write_Strobe_17 <= \<const0>\;
LMB_Write_Strobe_18 <= \<const0>\;
LMB_Write_Strobe_19 <= \<const0>\;
LMB_Write_Strobe_2 <= \<const0>\;
LMB_Write_Strobe_20 <= \<const0>\;
LMB_Write_Strobe_21 <= \<const0>\;
LMB_Write_Strobe_22 <= \<const0>\;
LMB_Write_Strobe_23 <= \<const0>\;
LMB_Write_Strobe_24 <= \<const0>\;
LMB_Write_Strobe_25 <= \<const0>\;
LMB_Write_Strobe_26 <= \<const0>\;
LMB_Write_Strobe_27 <= \<const0>\;
LMB_Write_Strobe_28 <= \<const0>\;
LMB_Write_Strobe_29 <= \<const0>\;
LMB_Write_Strobe_3 <= \<const0>\;
LMB_Write_Strobe_30 <= \<const0>\;
LMB_Write_Strobe_31 <= \<const0>\;
LMB_Write_Strobe_4 <= \<const0>\;
LMB_Write_Strobe_5 <= \<const0>\;
LMB_Write_Strobe_6 <= \<const0>\;
LMB_Write_Strobe_7 <= \<const0>\;
LMB_Write_Strobe_8 <= \<const0>\;
LMB_Write_Strobe_9 <= \<const0>\;
M_AXIS_TDATA(31) <= \<const0>\;
M_AXIS_TDATA(30) <= \<const0>\;
M_AXIS_TDATA(29) <= \<const0>\;
M_AXIS_TDATA(28) <= \<const0>\;
M_AXIS_TDATA(27) <= \<const0>\;
M_AXIS_TDATA(26) <= \<const0>\;
M_AXIS_TDATA(25) <= \<const0>\;
M_AXIS_TDATA(24) <= \<const0>\;
M_AXIS_TDATA(23) <= \<const0>\;
M_AXIS_TDATA(22) <= \<const0>\;
M_AXIS_TDATA(21) <= \<const0>\;
M_AXIS_TDATA(20) <= \<const0>\;
M_AXIS_TDATA(19) <= \<const0>\;
M_AXIS_TDATA(18) <= \<const0>\;
M_AXIS_TDATA(17) <= \<const0>\;
M_AXIS_TDATA(16) <= \<const0>\;
M_AXIS_TDATA(15) <= \<const0>\;
M_AXIS_TDATA(14) <= \<const0>\;
M_AXIS_TDATA(13) <= \<const0>\;
M_AXIS_TDATA(12) <= \<const0>\;
M_AXIS_TDATA(11) <= \<const0>\;
M_AXIS_TDATA(10) <= \<const0>\;
M_AXIS_TDATA(9) <= \<const0>\;
M_AXIS_TDATA(8) <= \<const0>\;
M_AXIS_TDATA(7) <= \<const0>\;
M_AXIS_TDATA(6) <= \<const0>\;
M_AXIS_TDATA(5) <= \<const0>\;
M_AXIS_TDATA(4) <= \<const0>\;
M_AXIS_TDATA(3) <= \<const0>\;
M_AXIS_TDATA(2) <= \<const0>\;
M_AXIS_TDATA(1) <= \<const0>\;
M_AXIS_TDATA(0) <= \<const0>\;
M_AXIS_TID(6) <= \<const0>\;
M_AXIS_TID(5) <= \<const0>\;
M_AXIS_TID(4) <= \<const0>\;
M_AXIS_TID(3) <= \<const0>\;
M_AXIS_TID(2) <= \<const0>\;
M_AXIS_TID(1) <= \<const0>\;
M_AXIS_TID(0) <= \<const0>\;
M_AXIS_TVALID <= \<const0>\;
M_AXI_ARADDR(31) <= \<const0>\;
M_AXI_ARADDR(30) <= \<const0>\;
M_AXI_ARADDR(29) <= \<const0>\;
M_AXI_ARADDR(28) <= \<const0>\;
M_AXI_ARADDR(27) <= \<const0>\;
M_AXI_ARADDR(26) <= \<const0>\;
M_AXI_ARADDR(25) <= \<const0>\;
M_AXI_ARADDR(24) <= \<const0>\;
M_AXI_ARADDR(23) <= \<const0>\;
M_AXI_ARADDR(22) <= \<const0>\;
M_AXI_ARADDR(21) <= \<const0>\;
M_AXI_ARADDR(20) <= \<const0>\;
M_AXI_ARADDR(19) <= \<const0>\;
M_AXI_ARADDR(18) <= \<const0>\;
M_AXI_ARADDR(17) <= \<const0>\;
M_AXI_ARADDR(16) <= \<const0>\;
M_AXI_ARADDR(15) <= \<const0>\;
M_AXI_ARADDR(14) <= \<const0>\;
M_AXI_ARADDR(13) <= \<const0>\;
M_AXI_ARADDR(12) <= \<const0>\;
M_AXI_ARADDR(11) <= \<const0>\;
M_AXI_ARADDR(10) <= \<const0>\;
M_AXI_ARADDR(9) <= \<const0>\;
M_AXI_ARADDR(8) <= \<const0>\;
M_AXI_ARADDR(7) <= \<const0>\;
M_AXI_ARADDR(6) <= \<const0>\;
M_AXI_ARADDR(5) <= \<const0>\;
M_AXI_ARADDR(4) <= \<const0>\;
M_AXI_ARADDR(3) <= \<const0>\;
M_AXI_ARADDR(2) <= \<const0>\;
M_AXI_ARADDR(1) <= \<const0>\;
M_AXI_ARADDR(0) <= \<const0>\;
M_AXI_ARBURST(1) <= \<const0>\;
M_AXI_ARBURST(0) <= \<const0>\;
M_AXI_ARCACHE(3) <= \<const0>\;
M_AXI_ARCACHE(2) <= \<const0>\;
M_AXI_ARCACHE(1) <= \<const0>\;
M_AXI_ARCACHE(0) <= \<const0>\;
M_AXI_ARID(0) <= \<const0>\;
M_AXI_ARLEN(7) <= \<const0>\;
M_AXI_ARLEN(6) <= \<const0>\;
M_AXI_ARLEN(5) <= \<const0>\;
M_AXI_ARLEN(4) <= \<const0>\;
M_AXI_ARLEN(3) <= \<const0>\;
M_AXI_ARLEN(2) <= \<const0>\;
M_AXI_ARLEN(1) <= \<const0>\;
M_AXI_ARLEN(0) <= \<const0>\;
M_AXI_ARLOCK <= \<const0>\;
M_AXI_ARPROT(2) <= \<const0>\;
M_AXI_ARPROT(1) <= \<const0>\;
M_AXI_ARPROT(0) <= \<const0>\;
M_AXI_ARQOS(3) <= \<const0>\;
M_AXI_ARQOS(2) <= \<const0>\;
M_AXI_ARQOS(1) <= \<const0>\;
M_AXI_ARQOS(0) <= \<const0>\;
M_AXI_ARSIZE(2) <= \<const0>\;
M_AXI_ARSIZE(1) <= \<const0>\;
M_AXI_ARSIZE(0) <= \<const0>\;
M_AXI_ARVALID <= \<const0>\;
M_AXI_AWADDR(31) <= \<const0>\;
M_AXI_AWADDR(30) <= \<const0>\;
M_AXI_AWADDR(29) <= \<const0>\;
M_AXI_AWADDR(28) <= \<const0>\;
M_AXI_AWADDR(27) <= \<const0>\;
M_AXI_AWADDR(26) <= \<const0>\;
M_AXI_AWADDR(25) <= \<const0>\;
M_AXI_AWADDR(24) <= \<const0>\;
M_AXI_AWADDR(23) <= \<const0>\;
M_AXI_AWADDR(22) <= \<const0>\;
M_AXI_AWADDR(21) <= \<const0>\;
M_AXI_AWADDR(20) <= \<const0>\;
M_AXI_AWADDR(19) <= \<const0>\;
M_AXI_AWADDR(18) <= \<const0>\;
M_AXI_AWADDR(17) <= \<const0>\;
M_AXI_AWADDR(16) <= \<const0>\;
M_AXI_AWADDR(15) <= \<const0>\;
M_AXI_AWADDR(14) <= \<const0>\;
M_AXI_AWADDR(13) <= \<const0>\;
M_AXI_AWADDR(12) <= \<const0>\;
M_AXI_AWADDR(11) <= \<const0>\;
M_AXI_AWADDR(10) <= \<const0>\;
M_AXI_AWADDR(9) <= \<const0>\;
M_AXI_AWADDR(8) <= \<const0>\;
M_AXI_AWADDR(7) <= \<const0>\;
M_AXI_AWADDR(6) <= \<const0>\;
M_AXI_AWADDR(5) <= \<const0>\;
M_AXI_AWADDR(4) <= \<const0>\;
M_AXI_AWADDR(3) <= \<const0>\;
M_AXI_AWADDR(2) <= \<const0>\;
M_AXI_AWADDR(1) <= \<const0>\;
M_AXI_AWADDR(0) <= \<const0>\;
M_AXI_AWBURST(1) <= \<const0>\;
M_AXI_AWBURST(0) <= \<const0>\;
M_AXI_AWCACHE(3) <= \<const0>\;
M_AXI_AWCACHE(2) <= \<const0>\;
M_AXI_AWCACHE(1) <= \<const0>\;
M_AXI_AWCACHE(0) <= \<const0>\;
M_AXI_AWID(0) <= \<const0>\;
M_AXI_AWLEN(7) <= \<const0>\;
M_AXI_AWLEN(6) <= \<const0>\;
M_AXI_AWLEN(5) <= \<const0>\;
M_AXI_AWLEN(4) <= \<const0>\;
M_AXI_AWLEN(3) <= \<const0>\;
M_AXI_AWLEN(2) <= \<const0>\;
M_AXI_AWLEN(1) <= \<const0>\;
M_AXI_AWLEN(0) <= \<const0>\;
M_AXI_AWLOCK <= \<const0>\;
M_AXI_AWPROT(2) <= \<const0>\;
M_AXI_AWPROT(1) <= \<const0>\;
M_AXI_AWPROT(0) <= \<const0>\;
M_AXI_AWQOS(3) <= \<const0>\;
M_AXI_AWQOS(2) <= \<const0>\;
M_AXI_AWQOS(1) <= \<const0>\;
M_AXI_AWQOS(0) <= \<const0>\;
M_AXI_AWSIZE(2) <= \<const0>\;
M_AXI_AWSIZE(1) <= \<const0>\;
M_AXI_AWSIZE(0) <= \<const0>\;
M_AXI_AWVALID <= \<const0>\;
M_AXI_BREADY <= \<const0>\;
M_AXI_RREADY <= \<const0>\;
M_AXI_WDATA(31) <= \<const0>\;
M_AXI_WDATA(30) <= \<const0>\;
M_AXI_WDATA(29) <= \<const0>\;
M_AXI_WDATA(28) <= \<const0>\;
M_AXI_WDATA(27) <= \<const0>\;
M_AXI_WDATA(26) <= \<const0>\;
M_AXI_WDATA(25) <= \<const0>\;
M_AXI_WDATA(24) <= \<const0>\;
M_AXI_WDATA(23) <= \<const0>\;
M_AXI_WDATA(22) <= \<const0>\;
M_AXI_WDATA(21) <= \<const0>\;
M_AXI_WDATA(20) <= \<const0>\;
M_AXI_WDATA(19) <= \<const0>\;
M_AXI_WDATA(18) <= \<const0>\;
M_AXI_WDATA(17) <= \<const0>\;
M_AXI_WDATA(16) <= \<const0>\;
M_AXI_WDATA(15) <= \<const0>\;
M_AXI_WDATA(14) <= \<const0>\;
M_AXI_WDATA(13) <= \<const0>\;
M_AXI_WDATA(12) <= \<const0>\;
M_AXI_WDATA(11) <= \<const0>\;
M_AXI_WDATA(10) <= \<const0>\;
M_AXI_WDATA(9) <= \<const0>\;
M_AXI_WDATA(8) <= \<const0>\;
M_AXI_WDATA(7) <= \<const0>\;
M_AXI_WDATA(6) <= \<const0>\;
M_AXI_WDATA(5) <= \<const0>\;
M_AXI_WDATA(4) <= \<const0>\;
M_AXI_WDATA(3) <= \<const0>\;
M_AXI_WDATA(2) <= \<const0>\;
M_AXI_WDATA(1) <= \<const0>\;
M_AXI_WDATA(0) <= \<const0>\;
M_AXI_WLAST <= \<const0>\;
M_AXI_WSTRB(3) <= \<const0>\;
M_AXI_WSTRB(2) <= \<const0>\;
M_AXI_WSTRB(1) <= \<const0>\;
M_AXI_WSTRB(0) <= \<const0>\;
M_AXI_WVALID <= \<const0>\;
S_AXI_ARREADY <= \<const0>\;
S_AXI_AWREADY <= \<const0>\;
S_AXI_BRESP(1) <= \<const0>\;
S_AXI_BRESP(0) <= \<const0>\;
S_AXI_BVALID <= \<const0>\;
S_AXI_RDATA(31) <= \<const0>\;
S_AXI_RDATA(30) <= \<const0>\;
S_AXI_RDATA(29) <= \<const0>\;
S_AXI_RDATA(28) <= \<const0>\;
S_AXI_RDATA(27) <= \<const0>\;
S_AXI_RDATA(26) <= \<const0>\;
S_AXI_RDATA(25) <= \<const0>\;
S_AXI_RDATA(24) <= \<const0>\;
S_AXI_RDATA(23) <= \<const0>\;
S_AXI_RDATA(22) <= \<const0>\;
S_AXI_RDATA(21) <= \<const0>\;
S_AXI_RDATA(20) <= \<const0>\;
S_AXI_RDATA(19) <= \<const0>\;
S_AXI_RDATA(18) <= \<const0>\;
S_AXI_RDATA(17) <= \<const0>\;
S_AXI_RDATA(16) <= \<const0>\;
S_AXI_RDATA(15) <= \<const0>\;
S_AXI_RDATA(14) <= \<const0>\;
S_AXI_RDATA(13) <= \<const0>\;
S_AXI_RDATA(12) <= \<const0>\;
S_AXI_RDATA(11) <= \<const0>\;
S_AXI_RDATA(10) <= \<const0>\;
S_AXI_RDATA(9) <= \<const0>\;
S_AXI_RDATA(8) <= \<const0>\;
S_AXI_RDATA(7) <= \<const0>\;
S_AXI_RDATA(6) <= \<const0>\;
S_AXI_RDATA(5) <= \<const0>\;
S_AXI_RDATA(4) <= \<const0>\;
S_AXI_RDATA(3) <= \<const0>\;
S_AXI_RDATA(2) <= \<const0>\;
S_AXI_RDATA(1) <= \<const0>\;
S_AXI_RDATA(0) <= \<const0>\;
S_AXI_RRESP(1) <= \<const0>\;
S_AXI_RRESP(0) <= \<const0>\;
S_AXI_RVALID <= \<const0>\;
S_AXI_WREADY <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \<const1>\;
TRACE_DATA(31) <= \<const0>\;
TRACE_DATA(30) <= \<const0>\;
TRACE_DATA(29) <= \<const0>\;
TRACE_DATA(28) <= \<const0>\;
TRACE_DATA(27) <= \<const0>\;
TRACE_DATA(26) <= \<const0>\;
TRACE_DATA(25) <= \<const0>\;
TRACE_DATA(24) <= \<const0>\;
TRACE_DATA(23) <= \<const0>\;
TRACE_DATA(22) <= \<const0>\;
TRACE_DATA(21) <= \<const0>\;
TRACE_DATA(20) <= \<const0>\;
TRACE_DATA(19) <= \<const0>\;
TRACE_DATA(18) <= \<const0>\;
TRACE_DATA(17) <= \<const0>\;
TRACE_DATA(16) <= \<const0>\;
TRACE_DATA(15) <= \<const0>\;
TRACE_DATA(14) <= \<const0>\;
TRACE_DATA(13) <= \<const0>\;
TRACE_DATA(12) <= \<const0>\;
TRACE_DATA(11) <= \<const0>\;
TRACE_DATA(10) <= \<const0>\;
TRACE_DATA(9) <= \<const0>\;
TRACE_DATA(8) <= \<const0>\;
TRACE_DATA(7) <= \<const0>\;
TRACE_DATA(6) <= \<const0>\;
TRACE_DATA(5) <= \<const0>\;
TRACE_DATA(4) <= \<const0>\;
TRACE_DATA(3) <= \<const0>\;
TRACE_DATA(2) <= \<const0>\;
TRACE_DATA(1) <= \<const0>\;
TRACE_DATA(0) <= \<const0>\;
Trig_Ack_In_0 <= \<const0>\;
Trig_Ack_In_1 <= \<const0>\;
Trig_Ack_In_2 <= \<const0>\;
Trig_Ack_In_3 <= \<const0>\;
Trig_Out_0 <= \<const0>\;
Trig_Out_1 <= \<const0>\;
Trig_Out_2 <= \<const0>\;
Trig_Out_3 <= \<const0>\;
bscan_ext_tdo <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
MDM_Core_I1: entity work.system_mdm_1_0_MDM_Core
port map (
AR(0) => sel_n_reset,
D(0) => p_1_in(15),
Dbg_Disable_0 => Dbg_Disable_0,
Dbg_Reg_En_0(0 to 7) => Dbg_Reg_En_0(0 to 7),
Dbg_Rst_0 => Dbg_Rst_0,
Dbg_Shift_0 => \^dbg_shift_0\,
Dbg_TDO_0 => Dbg_TDO_0,
Debug_SYS_Rst => Debug_SYS_Rst,
E(0) => \Use_E2.BSCAN_I_n_8\,
Ext_JTAG_SEL => Ext_JTAG_SEL,
Ext_JTAG_TDI => \^ext_jtag_tdi\,
Ext_JTAG_TDO => Ext_JTAG_TDO,
Ext_NM_BRK => Ext_NM_BRK,
Q(0) => MDM_Core_I1_n_0,
Scan_Reset => Scan_Reset,
Scan_Reset_Sel => Scan_Reset_Sel,
\Use_BSCAN.PORT_Selector_reg[0]_0\ => \^dbg_update_31\,
\Use_BSCAN.PORT_Selector_reg[0]_1\ => \^dbg_clk_31\,
\Use_BSCAN.PORT_Selector_reg[0]_2\ => \^ext_jtag_shift\,
\Use_BSCAN.PORT_Selector_reg[0]_3\ => \^ext_jtag_capture\,
\Use_BSCAN.PORT_Selector_reg[0]_4\ => \Use_E2.BSCAN_I_n_13\,
\Use_Serial_Unified_Completion.completion_status_reg[15]\(0) => MDM_Core_I1_n_19,
\Use_Serial_Unified_Completion.count_reg[4]\(0) => \JTAG_CONTROL_I/Use_Serial_Unified_Completion.count_reg\(5),
\Use_Serial_Unified_Completion.count_reg[5]\(0) => p_0_in(0),
\command_reg[5]\(0) => \JTAG_CONTROL_I/sel\,
\p_20_out__0\ => \JTAG_CONTROL_I/p_20_out__0\,
\p_43_out__0\ => \JTAG_CONTROL_I/p_43_out__0\,
sel => sel,
\shift_Count_reg[0]\(0) => \p_0_in__0\(0),
shift_n_reset => shift_n_reset,
tdo => tdo
);
\No_Dbg_Reg_Access.BUFG_DRCK\: entity work.system_mdm_1_0_MB_BUFG
port map (
Dbg_Clk_31 => \^dbg_clk_31\,
drck_i => drck_i
);
\Use_E2.BSCAN_I\: entity work.system_mdm_1_0_MB_BSCANE2
port map (
AR(0) => sel_n_reset,
D(0) => p_1_in(15),
Dbg_Capture_0 => \^ext_jtag_capture\,
Dbg_TDO_0 => Dbg_TDO_0,
Dbg_Update_31 => \^dbg_update_31\,
E(0) => \Use_E2.BSCAN_I_n_8\,
Ext_JTAG_RESET => Ext_JTAG_RESET,
Ext_JTAG_TDI => \^ext_jtag_tdi\,
Q(0) => MDM_Core_I1_n_0,
Scan_Reset => Scan_Reset,
Scan_Reset_Sel => Scan_Reset_Sel,
\Use_Serial_Unified_Completion.count_reg[5]\ => \^ext_jtag_shift\,
\Use_Serial_Unified_Completion.count_reg[5]_0\(0) => \JTAG_CONTROL_I/sel\,
\Use_Serial_Unified_Completion.count_reg[5]_1\(0) => p_0_in(0),
\Use_Serial_Unified_Completion.count_reg[5]_2\(0) => \JTAG_CONTROL_I/Use_Serial_Unified_Completion.count_reg\(5),
\Use_Serial_Unified_Completion.mb_instr_overrun_reg\ => \Use_E2.BSCAN_I_n_13\,
\Use_Serial_Unified_Completion.sample_1_reg[15]\(0) => MDM_Core_I1_n_19,
drck_i => drck_i,
\p_20_out__0\ => \JTAG_CONTROL_I/p_20_out__0\,
\p_43_out__0\ => \JTAG_CONTROL_I/p_43_out__0\,
sel => sel,
\shift_Count_reg[0]\(0) => \p_0_in__0\(0),
shift_n_reset => shift_n_reset,
tdo => tdo
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_mdm_1_0 is
port (
Debug_SYS_Rst : out STD_LOGIC;
Dbg_Clk_0 : out STD_LOGIC;
Dbg_TDI_0 : out STD_LOGIC;
Dbg_TDO_0 : in STD_LOGIC;
Dbg_Reg_En_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_0 : out STD_LOGIC;
Dbg_Shift_0 : out STD_LOGIC;
Dbg_Update_0 : out STD_LOGIC;
Dbg_Rst_0 : out STD_LOGIC;
Dbg_Disable_0 : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_mdm_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_mdm_1_0 : entity is "system_mdm_1_0,MDM,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_mdm_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_mdm_1_0 : entity is "MDM,Vivado 2016.4";
end system_mdm_1_0;
architecture STRUCTURE of system_mdm_1_0 is
signal NLW_U0_Dbg_ARVALID_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARVALID_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_AWVALID_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_BREADY_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Capture_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Clk_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Disable_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_RREADY_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Rst_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Shift_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TDI_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrClk_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_TrReady_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_Update_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_WVALID_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Ext_BRK_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Ext_JTAG_CAPTURE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Ext_JTAG_DRCK_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Ext_JTAG_RESET_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Ext_JTAG_SEL_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Ext_JTAG_SHIFT_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Ext_JTAG_TDI_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Ext_JTAG_UPDATE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Ext_NM_BRK_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Addr_Strobe_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Read_Strobe_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_LMB_Write_Strobe_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_M_AXIS_TVALID_UNCONNECTED : STD_LOGIC;
signal NLW_U0_M_AXI_ARLOCK_UNCONNECTED : STD_LOGIC;
signal NLW_U0_M_AXI_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_U0_M_AXI_AWLOCK_UNCONNECTED : STD_LOGIC;
signal NLW_U0_M_AXI_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_U0_M_AXI_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_U0_M_AXI_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_U0_M_AXI_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_U0_M_AXI_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_U0_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_U0_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Trig_Ack_In_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Trig_Ack_In_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Trig_Ack_In_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Trig_Ack_In_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Trig_Out_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Trig_Out_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Trig_Out_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Trig_Out_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_bscan_ext_tdo_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Dbg_ARADDR_0_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_1_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_10_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_11_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_12_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_13_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_14_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_15_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_16_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_17_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_18_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_19_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_2_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_20_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_21_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_22_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_23_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_24_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_25_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_26_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_27_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_28_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_29_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_3_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_30_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_31_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_4_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_5_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_6_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_7_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_8_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_ARADDR_9_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_0_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_1_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_10_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_11_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_12_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_13_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_14_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_15_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_16_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_17_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_18_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_19_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_2_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_20_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_21_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_22_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_23_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_24_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_25_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_26_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_27_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_28_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_29_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_3_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_30_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_31_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_4_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_5_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_6_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_7_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_8_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_AWADDR_9_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 2 );
signal NLW_U0_Dbg_Reg_En_1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Reg_En_9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_0_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Ack_In_9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_0_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_Trig_Out_9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
signal NLW_U0_Dbg_WDATA_0_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_1_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_10_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_11_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_12_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_13_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_14_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_15_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_16_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_17_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_18_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_19_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_2_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_20_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_21_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_22_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_23_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_24_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_25_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_26_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_27_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_28_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_29_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_3_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_30_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_31_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_4_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_5_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_6_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_7_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_8_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_Dbg_WDATA_9_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_LMB_Byte_Enable_0_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Byte_Enable_9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_U0_LMB_Data_Addr_0_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Addr_9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_0_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_LMB_Data_Write_9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_M_AXIS_TDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_M_AXIS_TID_UNCONNECTED : STD_LOGIC_VECTOR ( 6 downto 0 );
signal NLW_U0_M_AXI_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_M_AXI_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_M_AXI_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_M_AXI_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_M_AXI_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_M_AXI_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_M_AXI_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_M_AXI_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_M_AXI_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_M_AXI_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_M_AXI_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_M_AXI_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_M_AXI_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_M_AXI_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_M_AXI_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_M_AXI_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_M_AXI_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_M_AXI_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_S_AXI_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_S_AXI_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_S_AXI_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute C_DATA_SIZE : integer;
attribute C_DATA_SIZE of U0 : label is 32;
attribute C_DBG_MEM_ACCESS : integer;
attribute C_DBG_MEM_ACCESS of U0 : label is 0;
attribute C_DBG_REG_ACCESS : integer;
attribute C_DBG_REG_ACCESS of U0 : label is 0;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_INTERCONNECT : integer;
attribute C_INTERCONNECT of U0 : label is 2;
attribute C_JTAG_CHAIN : integer;
attribute C_JTAG_CHAIN of U0 : label is 2;
attribute C_MB_DBG_PORTS : integer;
attribute C_MB_DBG_PORTS of U0 : label is 1;
attribute C_M_AXIS_DATA_WIDTH : integer;
attribute C_M_AXIS_DATA_WIDTH of U0 : label is 32;
attribute C_M_AXIS_ID_WIDTH : integer;
attribute C_M_AXIS_ID_WIDTH of U0 : label is 7;
attribute C_M_AXI_ADDR_WIDTH : integer;
attribute C_M_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_M_AXI_DATA_WIDTH : integer;
attribute C_M_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_M_AXI_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_THREAD_ID_WIDTH of U0 : label is 1;
attribute C_S_AXI_ACLK_FREQ_HZ : integer;
attribute C_S_AXI_ACLK_FREQ_HZ of U0 : label is 100000000;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 4;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRACE_CLK_FREQ_HZ : integer;
attribute C_TRACE_CLK_FREQ_HZ of U0 : label is 200000000;
attribute C_TRACE_CLK_OUT_PHASE : integer;
attribute C_TRACE_CLK_OUT_PHASE of U0 : label is 90;
attribute C_TRACE_DATA_WIDTH : integer;
attribute C_TRACE_DATA_WIDTH of U0 : label is 32;
attribute C_TRACE_OUTPUT : integer;
attribute C_TRACE_OUTPUT of U0 : label is 0;
attribute C_USE_BSCAN : integer;
attribute C_USE_BSCAN of U0 : label is 0;
attribute C_USE_CONFIG_RESET : integer;
attribute C_USE_CONFIG_RESET of U0 : label is 0;
attribute C_USE_CROSS_TRIGGER : integer;
attribute C_USE_CROSS_TRIGGER of U0 : label is 0;
attribute C_USE_UART : integer;
attribute C_USE_UART of U0 : label is 0;
begin
U0: entity work.system_mdm_1_0_MDM
port map (
Config_Reset => '0',
Dbg_ARADDR_0(14 downto 2) => NLW_U0_Dbg_ARADDR_0_UNCONNECTED(14 downto 2),
Dbg_ARADDR_1(14 downto 2) => NLW_U0_Dbg_ARADDR_1_UNCONNECTED(14 downto 2),
Dbg_ARADDR_10(14 downto 2) => NLW_U0_Dbg_ARADDR_10_UNCONNECTED(14 downto 2),
Dbg_ARADDR_11(14 downto 2) => NLW_U0_Dbg_ARADDR_11_UNCONNECTED(14 downto 2),
Dbg_ARADDR_12(14 downto 2) => NLW_U0_Dbg_ARADDR_12_UNCONNECTED(14 downto 2),
Dbg_ARADDR_13(14 downto 2) => NLW_U0_Dbg_ARADDR_13_UNCONNECTED(14 downto 2),
Dbg_ARADDR_14(14 downto 2) => NLW_U0_Dbg_ARADDR_14_UNCONNECTED(14 downto 2),
Dbg_ARADDR_15(14 downto 2) => NLW_U0_Dbg_ARADDR_15_UNCONNECTED(14 downto 2),
Dbg_ARADDR_16(14 downto 2) => NLW_U0_Dbg_ARADDR_16_UNCONNECTED(14 downto 2),
Dbg_ARADDR_17(14 downto 2) => NLW_U0_Dbg_ARADDR_17_UNCONNECTED(14 downto 2),
Dbg_ARADDR_18(14 downto 2) => NLW_U0_Dbg_ARADDR_18_UNCONNECTED(14 downto 2),
Dbg_ARADDR_19(14 downto 2) => NLW_U0_Dbg_ARADDR_19_UNCONNECTED(14 downto 2),
Dbg_ARADDR_2(14 downto 2) => NLW_U0_Dbg_ARADDR_2_UNCONNECTED(14 downto 2),
Dbg_ARADDR_20(14 downto 2) => NLW_U0_Dbg_ARADDR_20_UNCONNECTED(14 downto 2),
Dbg_ARADDR_21(14 downto 2) => NLW_U0_Dbg_ARADDR_21_UNCONNECTED(14 downto 2),
Dbg_ARADDR_22(14 downto 2) => NLW_U0_Dbg_ARADDR_22_UNCONNECTED(14 downto 2),
Dbg_ARADDR_23(14 downto 2) => NLW_U0_Dbg_ARADDR_23_UNCONNECTED(14 downto 2),
Dbg_ARADDR_24(14 downto 2) => NLW_U0_Dbg_ARADDR_24_UNCONNECTED(14 downto 2),
Dbg_ARADDR_25(14 downto 2) => NLW_U0_Dbg_ARADDR_25_UNCONNECTED(14 downto 2),
Dbg_ARADDR_26(14 downto 2) => NLW_U0_Dbg_ARADDR_26_UNCONNECTED(14 downto 2),
Dbg_ARADDR_27(14 downto 2) => NLW_U0_Dbg_ARADDR_27_UNCONNECTED(14 downto 2),
Dbg_ARADDR_28(14 downto 2) => NLW_U0_Dbg_ARADDR_28_UNCONNECTED(14 downto 2),
Dbg_ARADDR_29(14 downto 2) => NLW_U0_Dbg_ARADDR_29_UNCONNECTED(14 downto 2),
Dbg_ARADDR_3(14 downto 2) => NLW_U0_Dbg_ARADDR_3_UNCONNECTED(14 downto 2),
Dbg_ARADDR_30(14 downto 2) => NLW_U0_Dbg_ARADDR_30_UNCONNECTED(14 downto 2),
Dbg_ARADDR_31(14 downto 2) => NLW_U0_Dbg_ARADDR_31_UNCONNECTED(14 downto 2),
Dbg_ARADDR_4(14 downto 2) => NLW_U0_Dbg_ARADDR_4_UNCONNECTED(14 downto 2),
Dbg_ARADDR_5(14 downto 2) => NLW_U0_Dbg_ARADDR_5_UNCONNECTED(14 downto 2),
Dbg_ARADDR_6(14 downto 2) => NLW_U0_Dbg_ARADDR_6_UNCONNECTED(14 downto 2),
Dbg_ARADDR_7(14 downto 2) => NLW_U0_Dbg_ARADDR_7_UNCONNECTED(14 downto 2),
Dbg_ARADDR_8(14 downto 2) => NLW_U0_Dbg_ARADDR_8_UNCONNECTED(14 downto 2),
Dbg_ARADDR_9(14 downto 2) => NLW_U0_Dbg_ARADDR_9_UNCONNECTED(14 downto 2),
Dbg_ARREADY_0 => '0',
Dbg_ARREADY_1 => '0',
Dbg_ARREADY_10 => '0',
Dbg_ARREADY_11 => '0',
Dbg_ARREADY_12 => '0',
Dbg_ARREADY_13 => '0',
Dbg_ARREADY_14 => '0',
Dbg_ARREADY_15 => '0',
Dbg_ARREADY_16 => '0',
Dbg_ARREADY_17 => '0',
Dbg_ARREADY_18 => '0',
Dbg_ARREADY_19 => '0',
Dbg_ARREADY_2 => '0',
Dbg_ARREADY_20 => '0',
Dbg_ARREADY_21 => '0',
Dbg_ARREADY_22 => '0',
Dbg_ARREADY_23 => '0',
Dbg_ARREADY_24 => '0',
Dbg_ARREADY_25 => '0',
Dbg_ARREADY_26 => '0',
Dbg_ARREADY_27 => '0',
Dbg_ARREADY_28 => '0',
Dbg_ARREADY_29 => '0',
Dbg_ARREADY_3 => '0',
Dbg_ARREADY_30 => '0',
Dbg_ARREADY_31 => '0',
Dbg_ARREADY_4 => '0',
Dbg_ARREADY_5 => '0',
Dbg_ARREADY_6 => '0',
Dbg_ARREADY_7 => '0',
Dbg_ARREADY_8 => '0',
Dbg_ARREADY_9 => '0',
Dbg_ARVALID_0 => NLW_U0_Dbg_ARVALID_0_UNCONNECTED,
Dbg_ARVALID_1 => NLW_U0_Dbg_ARVALID_1_UNCONNECTED,
Dbg_ARVALID_10 => NLW_U0_Dbg_ARVALID_10_UNCONNECTED,
Dbg_ARVALID_11 => NLW_U0_Dbg_ARVALID_11_UNCONNECTED,
Dbg_ARVALID_12 => NLW_U0_Dbg_ARVALID_12_UNCONNECTED,
Dbg_ARVALID_13 => NLW_U0_Dbg_ARVALID_13_UNCONNECTED,
Dbg_ARVALID_14 => NLW_U0_Dbg_ARVALID_14_UNCONNECTED,
Dbg_ARVALID_15 => NLW_U0_Dbg_ARVALID_15_UNCONNECTED,
Dbg_ARVALID_16 => NLW_U0_Dbg_ARVALID_16_UNCONNECTED,
Dbg_ARVALID_17 => NLW_U0_Dbg_ARVALID_17_UNCONNECTED,
Dbg_ARVALID_18 => NLW_U0_Dbg_ARVALID_18_UNCONNECTED,
Dbg_ARVALID_19 => NLW_U0_Dbg_ARVALID_19_UNCONNECTED,
Dbg_ARVALID_2 => NLW_U0_Dbg_ARVALID_2_UNCONNECTED,
Dbg_ARVALID_20 => NLW_U0_Dbg_ARVALID_20_UNCONNECTED,
Dbg_ARVALID_21 => NLW_U0_Dbg_ARVALID_21_UNCONNECTED,
Dbg_ARVALID_22 => NLW_U0_Dbg_ARVALID_22_UNCONNECTED,
Dbg_ARVALID_23 => NLW_U0_Dbg_ARVALID_23_UNCONNECTED,
Dbg_ARVALID_24 => NLW_U0_Dbg_ARVALID_24_UNCONNECTED,
Dbg_ARVALID_25 => NLW_U0_Dbg_ARVALID_25_UNCONNECTED,
Dbg_ARVALID_26 => NLW_U0_Dbg_ARVALID_26_UNCONNECTED,
Dbg_ARVALID_27 => NLW_U0_Dbg_ARVALID_27_UNCONNECTED,
Dbg_ARVALID_28 => NLW_U0_Dbg_ARVALID_28_UNCONNECTED,
Dbg_ARVALID_29 => NLW_U0_Dbg_ARVALID_29_UNCONNECTED,
Dbg_ARVALID_3 => NLW_U0_Dbg_ARVALID_3_UNCONNECTED,
Dbg_ARVALID_30 => NLW_U0_Dbg_ARVALID_30_UNCONNECTED,
Dbg_ARVALID_31 => NLW_U0_Dbg_ARVALID_31_UNCONNECTED,
Dbg_ARVALID_4 => NLW_U0_Dbg_ARVALID_4_UNCONNECTED,
Dbg_ARVALID_5 => NLW_U0_Dbg_ARVALID_5_UNCONNECTED,
Dbg_ARVALID_6 => NLW_U0_Dbg_ARVALID_6_UNCONNECTED,
Dbg_ARVALID_7 => NLW_U0_Dbg_ARVALID_7_UNCONNECTED,
Dbg_ARVALID_8 => NLW_U0_Dbg_ARVALID_8_UNCONNECTED,
Dbg_ARVALID_9 => NLW_U0_Dbg_ARVALID_9_UNCONNECTED,
Dbg_AWADDR_0(14 downto 2) => NLW_U0_Dbg_AWADDR_0_UNCONNECTED(14 downto 2),
Dbg_AWADDR_1(14 downto 2) => NLW_U0_Dbg_AWADDR_1_UNCONNECTED(14 downto 2),
Dbg_AWADDR_10(14 downto 2) => NLW_U0_Dbg_AWADDR_10_UNCONNECTED(14 downto 2),
Dbg_AWADDR_11(14 downto 2) => NLW_U0_Dbg_AWADDR_11_UNCONNECTED(14 downto 2),
Dbg_AWADDR_12(14 downto 2) => NLW_U0_Dbg_AWADDR_12_UNCONNECTED(14 downto 2),
Dbg_AWADDR_13(14 downto 2) => NLW_U0_Dbg_AWADDR_13_UNCONNECTED(14 downto 2),
Dbg_AWADDR_14(14 downto 2) => NLW_U0_Dbg_AWADDR_14_UNCONNECTED(14 downto 2),
Dbg_AWADDR_15(14 downto 2) => NLW_U0_Dbg_AWADDR_15_UNCONNECTED(14 downto 2),
Dbg_AWADDR_16(14 downto 2) => NLW_U0_Dbg_AWADDR_16_UNCONNECTED(14 downto 2),
Dbg_AWADDR_17(14 downto 2) => NLW_U0_Dbg_AWADDR_17_UNCONNECTED(14 downto 2),
Dbg_AWADDR_18(14 downto 2) => NLW_U0_Dbg_AWADDR_18_UNCONNECTED(14 downto 2),
Dbg_AWADDR_19(14 downto 2) => NLW_U0_Dbg_AWADDR_19_UNCONNECTED(14 downto 2),
Dbg_AWADDR_2(14 downto 2) => NLW_U0_Dbg_AWADDR_2_UNCONNECTED(14 downto 2),
Dbg_AWADDR_20(14 downto 2) => NLW_U0_Dbg_AWADDR_20_UNCONNECTED(14 downto 2),
Dbg_AWADDR_21(14 downto 2) => NLW_U0_Dbg_AWADDR_21_UNCONNECTED(14 downto 2),
Dbg_AWADDR_22(14 downto 2) => NLW_U0_Dbg_AWADDR_22_UNCONNECTED(14 downto 2),
Dbg_AWADDR_23(14 downto 2) => NLW_U0_Dbg_AWADDR_23_UNCONNECTED(14 downto 2),
Dbg_AWADDR_24(14 downto 2) => NLW_U0_Dbg_AWADDR_24_UNCONNECTED(14 downto 2),
Dbg_AWADDR_25(14 downto 2) => NLW_U0_Dbg_AWADDR_25_UNCONNECTED(14 downto 2),
Dbg_AWADDR_26(14 downto 2) => NLW_U0_Dbg_AWADDR_26_UNCONNECTED(14 downto 2),
Dbg_AWADDR_27(14 downto 2) => NLW_U0_Dbg_AWADDR_27_UNCONNECTED(14 downto 2),
Dbg_AWADDR_28(14 downto 2) => NLW_U0_Dbg_AWADDR_28_UNCONNECTED(14 downto 2),
Dbg_AWADDR_29(14 downto 2) => NLW_U0_Dbg_AWADDR_29_UNCONNECTED(14 downto 2),
Dbg_AWADDR_3(14 downto 2) => NLW_U0_Dbg_AWADDR_3_UNCONNECTED(14 downto 2),
Dbg_AWADDR_30(14 downto 2) => NLW_U0_Dbg_AWADDR_30_UNCONNECTED(14 downto 2),
Dbg_AWADDR_31(14 downto 2) => NLW_U0_Dbg_AWADDR_31_UNCONNECTED(14 downto 2),
Dbg_AWADDR_4(14 downto 2) => NLW_U0_Dbg_AWADDR_4_UNCONNECTED(14 downto 2),
Dbg_AWADDR_5(14 downto 2) => NLW_U0_Dbg_AWADDR_5_UNCONNECTED(14 downto 2),
Dbg_AWADDR_6(14 downto 2) => NLW_U0_Dbg_AWADDR_6_UNCONNECTED(14 downto 2),
Dbg_AWADDR_7(14 downto 2) => NLW_U0_Dbg_AWADDR_7_UNCONNECTED(14 downto 2),
Dbg_AWADDR_8(14 downto 2) => NLW_U0_Dbg_AWADDR_8_UNCONNECTED(14 downto 2),
Dbg_AWADDR_9(14 downto 2) => NLW_U0_Dbg_AWADDR_9_UNCONNECTED(14 downto 2),
Dbg_AWREADY_0 => '0',
Dbg_AWREADY_1 => '0',
Dbg_AWREADY_10 => '0',
Dbg_AWREADY_11 => '0',
Dbg_AWREADY_12 => '0',
Dbg_AWREADY_13 => '0',
Dbg_AWREADY_14 => '0',
Dbg_AWREADY_15 => '0',
Dbg_AWREADY_16 => '0',
Dbg_AWREADY_17 => '0',
Dbg_AWREADY_18 => '0',
Dbg_AWREADY_19 => '0',
Dbg_AWREADY_2 => '0',
Dbg_AWREADY_20 => '0',
Dbg_AWREADY_21 => '0',
Dbg_AWREADY_22 => '0',
Dbg_AWREADY_23 => '0',
Dbg_AWREADY_24 => '0',
Dbg_AWREADY_25 => '0',
Dbg_AWREADY_26 => '0',
Dbg_AWREADY_27 => '0',
Dbg_AWREADY_28 => '0',
Dbg_AWREADY_29 => '0',
Dbg_AWREADY_3 => '0',
Dbg_AWREADY_30 => '0',
Dbg_AWREADY_31 => '0',
Dbg_AWREADY_4 => '0',
Dbg_AWREADY_5 => '0',
Dbg_AWREADY_6 => '0',
Dbg_AWREADY_7 => '0',
Dbg_AWREADY_8 => '0',
Dbg_AWREADY_9 => '0',
Dbg_AWVALID_0 => NLW_U0_Dbg_AWVALID_0_UNCONNECTED,
Dbg_AWVALID_1 => NLW_U0_Dbg_AWVALID_1_UNCONNECTED,
Dbg_AWVALID_10 => NLW_U0_Dbg_AWVALID_10_UNCONNECTED,
Dbg_AWVALID_11 => NLW_U0_Dbg_AWVALID_11_UNCONNECTED,
Dbg_AWVALID_12 => NLW_U0_Dbg_AWVALID_12_UNCONNECTED,
Dbg_AWVALID_13 => NLW_U0_Dbg_AWVALID_13_UNCONNECTED,
Dbg_AWVALID_14 => NLW_U0_Dbg_AWVALID_14_UNCONNECTED,
Dbg_AWVALID_15 => NLW_U0_Dbg_AWVALID_15_UNCONNECTED,
Dbg_AWVALID_16 => NLW_U0_Dbg_AWVALID_16_UNCONNECTED,
Dbg_AWVALID_17 => NLW_U0_Dbg_AWVALID_17_UNCONNECTED,
Dbg_AWVALID_18 => NLW_U0_Dbg_AWVALID_18_UNCONNECTED,
Dbg_AWVALID_19 => NLW_U0_Dbg_AWVALID_19_UNCONNECTED,
Dbg_AWVALID_2 => NLW_U0_Dbg_AWVALID_2_UNCONNECTED,
Dbg_AWVALID_20 => NLW_U0_Dbg_AWVALID_20_UNCONNECTED,
Dbg_AWVALID_21 => NLW_U0_Dbg_AWVALID_21_UNCONNECTED,
Dbg_AWVALID_22 => NLW_U0_Dbg_AWVALID_22_UNCONNECTED,
Dbg_AWVALID_23 => NLW_U0_Dbg_AWVALID_23_UNCONNECTED,
Dbg_AWVALID_24 => NLW_U0_Dbg_AWVALID_24_UNCONNECTED,
Dbg_AWVALID_25 => NLW_U0_Dbg_AWVALID_25_UNCONNECTED,
Dbg_AWVALID_26 => NLW_U0_Dbg_AWVALID_26_UNCONNECTED,
Dbg_AWVALID_27 => NLW_U0_Dbg_AWVALID_27_UNCONNECTED,
Dbg_AWVALID_28 => NLW_U0_Dbg_AWVALID_28_UNCONNECTED,
Dbg_AWVALID_29 => NLW_U0_Dbg_AWVALID_29_UNCONNECTED,
Dbg_AWVALID_3 => NLW_U0_Dbg_AWVALID_3_UNCONNECTED,
Dbg_AWVALID_30 => NLW_U0_Dbg_AWVALID_30_UNCONNECTED,
Dbg_AWVALID_31 => NLW_U0_Dbg_AWVALID_31_UNCONNECTED,
Dbg_AWVALID_4 => NLW_U0_Dbg_AWVALID_4_UNCONNECTED,
Dbg_AWVALID_5 => NLW_U0_Dbg_AWVALID_5_UNCONNECTED,
Dbg_AWVALID_6 => NLW_U0_Dbg_AWVALID_6_UNCONNECTED,
Dbg_AWVALID_7 => NLW_U0_Dbg_AWVALID_7_UNCONNECTED,
Dbg_AWVALID_8 => NLW_U0_Dbg_AWVALID_8_UNCONNECTED,
Dbg_AWVALID_9 => NLW_U0_Dbg_AWVALID_9_UNCONNECTED,
Dbg_BREADY_0 => NLW_U0_Dbg_BREADY_0_UNCONNECTED,
Dbg_BREADY_1 => NLW_U0_Dbg_BREADY_1_UNCONNECTED,
Dbg_BREADY_10 => NLW_U0_Dbg_BREADY_10_UNCONNECTED,
Dbg_BREADY_11 => NLW_U0_Dbg_BREADY_11_UNCONNECTED,
Dbg_BREADY_12 => NLW_U0_Dbg_BREADY_12_UNCONNECTED,
Dbg_BREADY_13 => NLW_U0_Dbg_BREADY_13_UNCONNECTED,
Dbg_BREADY_14 => NLW_U0_Dbg_BREADY_14_UNCONNECTED,
Dbg_BREADY_15 => NLW_U0_Dbg_BREADY_15_UNCONNECTED,
Dbg_BREADY_16 => NLW_U0_Dbg_BREADY_16_UNCONNECTED,
Dbg_BREADY_17 => NLW_U0_Dbg_BREADY_17_UNCONNECTED,
Dbg_BREADY_18 => NLW_U0_Dbg_BREADY_18_UNCONNECTED,
Dbg_BREADY_19 => NLW_U0_Dbg_BREADY_19_UNCONNECTED,
Dbg_BREADY_2 => NLW_U0_Dbg_BREADY_2_UNCONNECTED,
Dbg_BREADY_20 => NLW_U0_Dbg_BREADY_20_UNCONNECTED,
Dbg_BREADY_21 => NLW_U0_Dbg_BREADY_21_UNCONNECTED,
Dbg_BREADY_22 => NLW_U0_Dbg_BREADY_22_UNCONNECTED,
Dbg_BREADY_23 => NLW_U0_Dbg_BREADY_23_UNCONNECTED,
Dbg_BREADY_24 => NLW_U0_Dbg_BREADY_24_UNCONNECTED,
Dbg_BREADY_25 => NLW_U0_Dbg_BREADY_25_UNCONNECTED,
Dbg_BREADY_26 => NLW_U0_Dbg_BREADY_26_UNCONNECTED,
Dbg_BREADY_27 => NLW_U0_Dbg_BREADY_27_UNCONNECTED,
Dbg_BREADY_28 => NLW_U0_Dbg_BREADY_28_UNCONNECTED,
Dbg_BREADY_29 => NLW_U0_Dbg_BREADY_29_UNCONNECTED,
Dbg_BREADY_3 => NLW_U0_Dbg_BREADY_3_UNCONNECTED,
Dbg_BREADY_30 => NLW_U0_Dbg_BREADY_30_UNCONNECTED,
Dbg_BREADY_31 => NLW_U0_Dbg_BREADY_31_UNCONNECTED,
Dbg_BREADY_4 => NLW_U0_Dbg_BREADY_4_UNCONNECTED,
Dbg_BREADY_5 => NLW_U0_Dbg_BREADY_5_UNCONNECTED,
Dbg_BREADY_6 => NLW_U0_Dbg_BREADY_6_UNCONNECTED,
Dbg_BREADY_7 => NLW_U0_Dbg_BREADY_7_UNCONNECTED,
Dbg_BREADY_8 => NLW_U0_Dbg_BREADY_8_UNCONNECTED,
Dbg_BREADY_9 => NLW_U0_Dbg_BREADY_9_UNCONNECTED,
Dbg_BRESP_0(1 downto 0) => B"00",
Dbg_BRESP_1(1 downto 0) => B"00",
Dbg_BRESP_10(1 downto 0) => B"00",
Dbg_BRESP_11(1 downto 0) => B"00",
Dbg_BRESP_12(1 downto 0) => B"00",
Dbg_BRESP_13(1 downto 0) => B"00",
Dbg_BRESP_14(1 downto 0) => B"00",
Dbg_BRESP_15(1 downto 0) => B"00",
Dbg_BRESP_16(1 downto 0) => B"00",
Dbg_BRESP_17(1 downto 0) => B"00",
Dbg_BRESP_18(1 downto 0) => B"00",
Dbg_BRESP_19(1 downto 0) => B"00",
Dbg_BRESP_2(1 downto 0) => B"00",
Dbg_BRESP_20(1 downto 0) => B"00",
Dbg_BRESP_21(1 downto 0) => B"00",
Dbg_BRESP_22(1 downto 0) => B"00",
Dbg_BRESP_23(1 downto 0) => B"00",
Dbg_BRESP_24(1 downto 0) => B"00",
Dbg_BRESP_25(1 downto 0) => B"00",
Dbg_BRESP_26(1 downto 0) => B"00",
Dbg_BRESP_27(1 downto 0) => B"00",
Dbg_BRESP_28(1 downto 0) => B"00",
Dbg_BRESP_29(1 downto 0) => B"00",
Dbg_BRESP_3(1 downto 0) => B"00",
Dbg_BRESP_30(1 downto 0) => B"00",
Dbg_BRESP_31(1 downto 0) => B"00",
Dbg_BRESP_4(1 downto 0) => B"00",
Dbg_BRESP_5(1 downto 0) => B"00",
Dbg_BRESP_6(1 downto 0) => B"00",
Dbg_BRESP_7(1 downto 0) => B"00",
Dbg_BRESP_8(1 downto 0) => B"00",
Dbg_BRESP_9(1 downto 0) => B"00",
Dbg_BVALID_0 => '0',
Dbg_BVALID_1 => '0',
Dbg_BVALID_10 => '0',
Dbg_BVALID_11 => '0',
Dbg_BVALID_12 => '0',
Dbg_BVALID_13 => '0',
Dbg_BVALID_14 => '0',
Dbg_BVALID_15 => '0',
Dbg_BVALID_16 => '0',
Dbg_BVALID_17 => '0',
Dbg_BVALID_18 => '0',
Dbg_BVALID_19 => '0',
Dbg_BVALID_2 => '0',
Dbg_BVALID_20 => '0',
Dbg_BVALID_21 => '0',
Dbg_BVALID_22 => '0',
Dbg_BVALID_23 => '0',
Dbg_BVALID_24 => '0',
Dbg_BVALID_25 => '0',
Dbg_BVALID_26 => '0',
Dbg_BVALID_27 => '0',
Dbg_BVALID_28 => '0',
Dbg_BVALID_29 => '0',
Dbg_BVALID_3 => '0',
Dbg_BVALID_30 => '0',
Dbg_BVALID_31 => '0',
Dbg_BVALID_4 => '0',
Dbg_BVALID_5 => '0',
Dbg_BVALID_6 => '0',
Dbg_BVALID_7 => '0',
Dbg_BVALID_8 => '0',
Dbg_BVALID_9 => '0',
Dbg_Capture_0 => Dbg_Capture_0,
Dbg_Capture_1 => NLW_U0_Dbg_Capture_1_UNCONNECTED,
Dbg_Capture_10 => NLW_U0_Dbg_Capture_10_UNCONNECTED,
Dbg_Capture_11 => NLW_U0_Dbg_Capture_11_UNCONNECTED,
Dbg_Capture_12 => NLW_U0_Dbg_Capture_12_UNCONNECTED,
Dbg_Capture_13 => NLW_U0_Dbg_Capture_13_UNCONNECTED,
Dbg_Capture_14 => NLW_U0_Dbg_Capture_14_UNCONNECTED,
Dbg_Capture_15 => NLW_U0_Dbg_Capture_15_UNCONNECTED,
Dbg_Capture_16 => NLW_U0_Dbg_Capture_16_UNCONNECTED,
Dbg_Capture_17 => NLW_U0_Dbg_Capture_17_UNCONNECTED,
Dbg_Capture_18 => NLW_U0_Dbg_Capture_18_UNCONNECTED,
Dbg_Capture_19 => NLW_U0_Dbg_Capture_19_UNCONNECTED,
Dbg_Capture_2 => NLW_U0_Dbg_Capture_2_UNCONNECTED,
Dbg_Capture_20 => NLW_U0_Dbg_Capture_20_UNCONNECTED,
Dbg_Capture_21 => NLW_U0_Dbg_Capture_21_UNCONNECTED,
Dbg_Capture_22 => NLW_U0_Dbg_Capture_22_UNCONNECTED,
Dbg_Capture_23 => NLW_U0_Dbg_Capture_23_UNCONNECTED,
Dbg_Capture_24 => NLW_U0_Dbg_Capture_24_UNCONNECTED,
Dbg_Capture_25 => NLW_U0_Dbg_Capture_25_UNCONNECTED,
Dbg_Capture_26 => NLW_U0_Dbg_Capture_26_UNCONNECTED,
Dbg_Capture_27 => NLW_U0_Dbg_Capture_27_UNCONNECTED,
Dbg_Capture_28 => NLW_U0_Dbg_Capture_28_UNCONNECTED,
Dbg_Capture_29 => NLW_U0_Dbg_Capture_29_UNCONNECTED,
Dbg_Capture_3 => NLW_U0_Dbg_Capture_3_UNCONNECTED,
Dbg_Capture_30 => NLW_U0_Dbg_Capture_30_UNCONNECTED,
Dbg_Capture_31 => NLW_U0_Dbg_Capture_31_UNCONNECTED,
Dbg_Capture_4 => NLW_U0_Dbg_Capture_4_UNCONNECTED,
Dbg_Capture_5 => NLW_U0_Dbg_Capture_5_UNCONNECTED,
Dbg_Capture_6 => NLW_U0_Dbg_Capture_6_UNCONNECTED,
Dbg_Capture_7 => NLW_U0_Dbg_Capture_7_UNCONNECTED,
Dbg_Capture_8 => NLW_U0_Dbg_Capture_8_UNCONNECTED,
Dbg_Capture_9 => NLW_U0_Dbg_Capture_9_UNCONNECTED,
Dbg_Clk_0 => Dbg_Clk_0,
Dbg_Clk_1 => NLW_U0_Dbg_Clk_1_UNCONNECTED,
Dbg_Clk_10 => NLW_U0_Dbg_Clk_10_UNCONNECTED,
Dbg_Clk_11 => NLW_U0_Dbg_Clk_11_UNCONNECTED,
Dbg_Clk_12 => NLW_U0_Dbg_Clk_12_UNCONNECTED,
Dbg_Clk_13 => NLW_U0_Dbg_Clk_13_UNCONNECTED,
Dbg_Clk_14 => NLW_U0_Dbg_Clk_14_UNCONNECTED,
Dbg_Clk_15 => NLW_U0_Dbg_Clk_15_UNCONNECTED,
Dbg_Clk_16 => NLW_U0_Dbg_Clk_16_UNCONNECTED,
Dbg_Clk_17 => NLW_U0_Dbg_Clk_17_UNCONNECTED,
Dbg_Clk_18 => NLW_U0_Dbg_Clk_18_UNCONNECTED,
Dbg_Clk_19 => NLW_U0_Dbg_Clk_19_UNCONNECTED,
Dbg_Clk_2 => NLW_U0_Dbg_Clk_2_UNCONNECTED,
Dbg_Clk_20 => NLW_U0_Dbg_Clk_20_UNCONNECTED,
Dbg_Clk_21 => NLW_U0_Dbg_Clk_21_UNCONNECTED,
Dbg_Clk_22 => NLW_U0_Dbg_Clk_22_UNCONNECTED,
Dbg_Clk_23 => NLW_U0_Dbg_Clk_23_UNCONNECTED,
Dbg_Clk_24 => NLW_U0_Dbg_Clk_24_UNCONNECTED,
Dbg_Clk_25 => NLW_U0_Dbg_Clk_25_UNCONNECTED,
Dbg_Clk_26 => NLW_U0_Dbg_Clk_26_UNCONNECTED,
Dbg_Clk_27 => NLW_U0_Dbg_Clk_27_UNCONNECTED,
Dbg_Clk_28 => NLW_U0_Dbg_Clk_28_UNCONNECTED,
Dbg_Clk_29 => NLW_U0_Dbg_Clk_29_UNCONNECTED,
Dbg_Clk_3 => NLW_U0_Dbg_Clk_3_UNCONNECTED,
Dbg_Clk_30 => NLW_U0_Dbg_Clk_30_UNCONNECTED,
Dbg_Clk_31 => NLW_U0_Dbg_Clk_31_UNCONNECTED,
Dbg_Clk_4 => NLW_U0_Dbg_Clk_4_UNCONNECTED,
Dbg_Clk_5 => NLW_U0_Dbg_Clk_5_UNCONNECTED,
Dbg_Clk_6 => NLW_U0_Dbg_Clk_6_UNCONNECTED,
Dbg_Clk_7 => NLW_U0_Dbg_Clk_7_UNCONNECTED,
Dbg_Clk_8 => NLW_U0_Dbg_Clk_8_UNCONNECTED,
Dbg_Clk_9 => NLW_U0_Dbg_Clk_9_UNCONNECTED,
Dbg_Disable_0 => Dbg_Disable_0,
Dbg_Disable_1 => NLW_U0_Dbg_Disable_1_UNCONNECTED,
Dbg_Disable_10 => NLW_U0_Dbg_Disable_10_UNCONNECTED,
Dbg_Disable_11 => NLW_U0_Dbg_Disable_11_UNCONNECTED,
Dbg_Disable_12 => NLW_U0_Dbg_Disable_12_UNCONNECTED,
Dbg_Disable_13 => NLW_U0_Dbg_Disable_13_UNCONNECTED,
Dbg_Disable_14 => NLW_U0_Dbg_Disable_14_UNCONNECTED,
Dbg_Disable_15 => NLW_U0_Dbg_Disable_15_UNCONNECTED,
Dbg_Disable_16 => NLW_U0_Dbg_Disable_16_UNCONNECTED,
Dbg_Disable_17 => NLW_U0_Dbg_Disable_17_UNCONNECTED,
Dbg_Disable_18 => NLW_U0_Dbg_Disable_18_UNCONNECTED,
Dbg_Disable_19 => NLW_U0_Dbg_Disable_19_UNCONNECTED,
Dbg_Disable_2 => NLW_U0_Dbg_Disable_2_UNCONNECTED,
Dbg_Disable_20 => NLW_U0_Dbg_Disable_20_UNCONNECTED,
Dbg_Disable_21 => NLW_U0_Dbg_Disable_21_UNCONNECTED,
Dbg_Disable_22 => NLW_U0_Dbg_Disable_22_UNCONNECTED,
Dbg_Disable_23 => NLW_U0_Dbg_Disable_23_UNCONNECTED,
Dbg_Disable_24 => NLW_U0_Dbg_Disable_24_UNCONNECTED,
Dbg_Disable_25 => NLW_U0_Dbg_Disable_25_UNCONNECTED,
Dbg_Disable_26 => NLW_U0_Dbg_Disable_26_UNCONNECTED,
Dbg_Disable_27 => NLW_U0_Dbg_Disable_27_UNCONNECTED,
Dbg_Disable_28 => NLW_U0_Dbg_Disable_28_UNCONNECTED,
Dbg_Disable_29 => NLW_U0_Dbg_Disable_29_UNCONNECTED,
Dbg_Disable_3 => NLW_U0_Dbg_Disable_3_UNCONNECTED,
Dbg_Disable_30 => NLW_U0_Dbg_Disable_30_UNCONNECTED,
Dbg_Disable_31 => NLW_U0_Dbg_Disable_31_UNCONNECTED,
Dbg_Disable_4 => NLW_U0_Dbg_Disable_4_UNCONNECTED,
Dbg_Disable_5 => NLW_U0_Dbg_Disable_5_UNCONNECTED,
Dbg_Disable_6 => NLW_U0_Dbg_Disable_6_UNCONNECTED,
Dbg_Disable_7 => NLW_U0_Dbg_Disable_7_UNCONNECTED,
Dbg_Disable_8 => NLW_U0_Dbg_Disable_8_UNCONNECTED,
Dbg_Disable_9 => NLW_U0_Dbg_Disable_9_UNCONNECTED,
Dbg_RDATA_0(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_1(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_10(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_11(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_12(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_13(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_14(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_15(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_16(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_17(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_18(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_19(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_2(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_20(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_21(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_22(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_23(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_24(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_25(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_26(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_27(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_28(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_29(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_3(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_30(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_31(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_4(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_5(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_6(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_7(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_8(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RDATA_9(31 downto 0) => B"00000000000000000000000000000000",
Dbg_RREADY_0 => NLW_U0_Dbg_RREADY_0_UNCONNECTED,
Dbg_RREADY_1 => NLW_U0_Dbg_RREADY_1_UNCONNECTED,
Dbg_RREADY_10 => NLW_U0_Dbg_RREADY_10_UNCONNECTED,
Dbg_RREADY_11 => NLW_U0_Dbg_RREADY_11_UNCONNECTED,
Dbg_RREADY_12 => NLW_U0_Dbg_RREADY_12_UNCONNECTED,
Dbg_RREADY_13 => NLW_U0_Dbg_RREADY_13_UNCONNECTED,
Dbg_RREADY_14 => NLW_U0_Dbg_RREADY_14_UNCONNECTED,
Dbg_RREADY_15 => NLW_U0_Dbg_RREADY_15_UNCONNECTED,
Dbg_RREADY_16 => NLW_U0_Dbg_RREADY_16_UNCONNECTED,
Dbg_RREADY_17 => NLW_U0_Dbg_RREADY_17_UNCONNECTED,
Dbg_RREADY_18 => NLW_U0_Dbg_RREADY_18_UNCONNECTED,
Dbg_RREADY_19 => NLW_U0_Dbg_RREADY_19_UNCONNECTED,
Dbg_RREADY_2 => NLW_U0_Dbg_RREADY_2_UNCONNECTED,
Dbg_RREADY_20 => NLW_U0_Dbg_RREADY_20_UNCONNECTED,
Dbg_RREADY_21 => NLW_U0_Dbg_RREADY_21_UNCONNECTED,
Dbg_RREADY_22 => NLW_U0_Dbg_RREADY_22_UNCONNECTED,
Dbg_RREADY_23 => NLW_U0_Dbg_RREADY_23_UNCONNECTED,
Dbg_RREADY_24 => NLW_U0_Dbg_RREADY_24_UNCONNECTED,
Dbg_RREADY_25 => NLW_U0_Dbg_RREADY_25_UNCONNECTED,
Dbg_RREADY_26 => NLW_U0_Dbg_RREADY_26_UNCONNECTED,
Dbg_RREADY_27 => NLW_U0_Dbg_RREADY_27_UNCONNECTED,
Dbg_RREADY_28 => NLW_U0_Dbg_RREADY_28_UNCONNECTED,
Dbg_RREADY_29 => NLW_U0_Dbg_RREADY_29_UNCONNECTED,
Dbg_RREADY_3 => NLW_U0_Dbg_RREADY_3_UNCONNECTED,
Dbg_RREADY_30 => NLW_U0_Dbg_RREADY_30_UNCONNECTED,
Dbg_RREADY_31 => NLW_U0_Dbg_RREADY_31_UNCONNECTED,
Dbg_RREADY_4 => NLW_U0_Dbg_RREADY_4_UNCONNECTED,
Dbg_RREADY_5 => NLW_U0_Dbg_RREADY_5_UNCONNECTED,
Dbg_RREADY_6 => NLW_U0_Dbg_RREADY_6_UNCONNECTED,
Dbg_RREADY_7 => NLW_U0_Dbg_RREADY_7_UNCONNECTED,
Dbg_RREADY_8 => NLW_U0_Dbg_RREADY_8_UNCONNECTED,
Dbg_RREADY_9 => NLW_U0_Dbg_RREADY_9_UNCONNECTED,
Dbg_RRESP_0(1 downto 0) => B"00",
Dbg_RRESP_1(1 downto 0) => B"00",
Dbg_RRESP_10(1 downto 0) => B"00",
Dbg_RRESP_11(1 downto 0) => B"00",
Dbg_RRESP_12(1 downto 0) => B"00",
Dbg_RRESP_13(1 downto 0) => B"00",
Dbg_RRESP_14(1 downto 0) => B"00",
Dbg_RRESP_15(1 downto 0) => B"00",
Dbg_RRESP_16(1 downto 0) => B"00",
Dbg_RRESP_17(1 downto 0) => B"00",
Dbg_RRESP_18(1 downto 0) => B"00",
Dbg_RRESP_19(1 downto 0) => B"00",
Dbg_RRESP_2(1 downto 0) => B"00",
Dbg_RRESP_20(1 downto 0) => B"00",
Dbg_RRESP_21(1 downto 0) => B"00",
Dbg_RRESP_22(1 downto 0) => B"00",
Dbg_RRESP_23(1 downto 0) => B"00",
Dbg_RRESP_24(1 downto 0) => B"00",
Dbg_RRESP_25(1 downto 0) => B"00",
Dbg_RRESP_26(1 downto 0) => B"00",
Dbg_RRESP_27(1 downto 0) => B"00",
Dbg_RRESP_28(1 downto 0) => B"00",
Dbg_RRESP_29(1 downto 0) => B"00",
Dbg_RRESP_3(1 downto 0) => B"00",
Dbg_RRESP_30(1 downto 0) => B"00",
Dbg_RRESP_31(1 downto 0) => B"00",
Dbg_RRESP_4(1 downto 0) => B"00",
Dbg_RRESP_5(1 downto 0) => B"00",
Dbg_RRESP_6(1 downto 0) => B"00",
Dbg_RRESP_7(1 downto 0) => B"00",
Dbg_RRESP_8(1 downto 0) => B"00",
Dbg_RRESP_9(1 downto 0) => B"00",
Dbg_RVALID_0 => '0',
Dbg_RVALID_1 => '0',
Dbg_RVALID_10 => '0',
Dbg_RVALID_11 => '0',
Dbg_RVALID_12 => '0',
Dbg_RVALID_13 => '0',
Dbg_RVALID_14 => '0',
Dbg_RVALID_15 => '0',
Dbg_RVALID_16 => '0',
Dbg_RVALID_17 => '0',
Dbg_RVALID_18 => '0',
Dbg_RVALID_19 => '0',
Dbg_RVALID_2 => '0',
Dbg_RVALID_20 => '0',
Dbg_RVALID_21 => '0',
Dbg_RVALID_22 => '0',
Dbg_RVALID_23 => '0',
Dbg_RVALID_24 => '0',
Dbg_RVALID_25 => '0',
Dbg_RVALID_26 => '0',
Dbg_RVALID_27 => '0',
Dbg_RVALID_28 => '0',
Dbg_RVALID_29 => '0',
Dbg_RVALID_3 => '0',
Dbg_RVALID_30 => '0',
Dbg_RVALID_31 => '0',
Dbg_RVALID_4 => '0',
Dbg_RVALID_5 => '0',
Dbg_RVALID_6 => '0',
Dbg_RVALID_7 => '0',
Dbg_RVALID_8 => '0',
Dbg_RVALID_9 => '0',
Dbg_Reg_En_0(0 to 7) => Dbg_Reg_En_0(0 to 7),
Dbg_Reg_En_1(0 to 7) => NLW_U0_Dbg_Reg_En_1_UNCONNECTED(0 to 7),
Dbg_Reg_En_10(0 to 7) => NLW_U0_Dbg_Reg_En_10_UNCONNECTED(0 to 7),
Dbg_Reg_En_11(0 to 7) => NLW_U0_Dbg_Reg_En_11_UNCONNECTED(0 to 7),
Dbg_Reg_En_12(0 to 7) => NLW_U0_Dbg_Reg_En_12_UNCONNECTED(0 to 7),
Dbg_Reg_En_13(0 to 7) => NLW_U0_Dbg_Reg_En_13_UNCONNECTED(0 to 7),
Dbg_Reg_En_14(0 to 7) => NLW_U0_Dbg_Reg_En_14_UNCONNECTED(0 to 7),
Dbg_Reg_En_15(0 to 7) => NLW_U0_Dbg_Reg_En_15_UNCONNECTED(0 to 7),
Dbg_Reg_En_16(0 to 7) => NLW_U0_Dbg_Reg_En_16_UNCONNECTED(0 to 7),
Dbg_Reg_En_17(0 to 7) => NLW_U0_Dbg_Reg_En_17_UNCONNECTED(0 to 7),
Dbg_Reg_En_18(0 to 7) => NLW_U0_Dbg_Reg_En_18_UNCONNECTED(0 to 7),
Dbg_Reg_En_19(0 to 7) => NLW_U0_Dbg_Reg_En_19_UNCONNECTED(0 to 7),
Dbg_Reg_En_2(0 to 7) => NLW_U0_Dbg_Reg_En_2_UNCONNECTED(0 to 7),
Dbg_Reg_En_20(0 to 7) => NLW_U0_Dbg_Reg_En_20_UNCONNECTED(0 to 7),
Dbg_Reg_En_21(0 to 7) => NLW_U0_Dbg_Reg_En_21_UNCONNECTED(0 to 7),
Dbg_Reg_En_22(0 to 7) => NLW_U0_Dbg_Reg_En_22_UNCONNECTED(0 to 7),
Dbg_Reg_En_23(0 to 7) => NLW_U0_Dbg_Reg_En_23_UNCONNECTED(0 to 7),
Dbg_Reg_En_24(0 to 7) => NLW_U0_Dbg_Reg_En_24_UNCONNECTED(0 to 7),
Dbg_Reg_En_25(0 to 7) => NLW_U0_Dbg_Reg_En_25_UNCONNECTED(0 to 7),
Dbg_Reg_En_26(0 to 7) => NLW_U0_Dbg_Reg_En_26_UNCONNECTED(0 to 7),
Dbg_Reg_En_27(0 to 7) => NLW_U0_Dbg_Reg_En_27_UNCONNECTED(0 to 7),
Dbg_Reg_En_28(0 to 7) => NLW_U0_Dbg_Reg_En_28_UNCONNECTED(0 to 7),
Dbg_Reg_En_29(0 to 7) => NLW_U0_Dbg_Reg_En_29_UNCONNECTED(0 to 7),
Dbg_Reg_En_3(0 to 7) => NLW_U0_Dbg_Reg_En_3_UNCONNECTED(0 to 7),
Dbg_Reg_En_30(0 to 7) => NLW_U0_Dbg_Reg_En_30_UNCONNECTED(0 to 7),
Dbg_Reg_En_31(0 to 7) => NLW_U0_Dbg_Reg_En_31_UNCONNECTED(0 to 7),
Dbg_Reg_En_4(0 to 7) => NLW_U0_Dbg_Reg_En_4_UNCONNECTED(0 to 7),
Dbg_Reg_En_5(0 to 7) => NLW_U0_Dbg_Reg_En_5_UNCONNECTED(0 to 7),
Dbg_Reg_En_6(0 to 7) => NLW_U0_Dbg_Reg_En_6_UNCONNECTED(0 to 7),
Dbg_Reg_En_7(0 to 7) => NLW_U0_Dbg_Reg_En_7_UNCONNECTED(0 to 7),
Dbg_Reg_En_8(0 to 7) => NLW_U0_Dbg_Reg_En_8_UNCONNECTED(0 to 7),
Dbg_Reg_En_9(0 to 7) => NLW_U0_Dbg_Reg_En_9_UNCONNECTED(0 to 7),
Dbg_Rst_0 => Dbg_Rst_0,
Dbg_Rst_1 => NLW_U0_Dbg_Rst_1_UNCONNECTED,
Dbg_Rst_10 => NLW_U0_Dbg_Rst_10_UNCONNECTED,
Dbg_Rst_11 => NLW_U0_Dbg_Rst_11_UNCONNECTED,
Dbg_Rst_12 => NLW_U0_Dbg_Rst_12_UNCONNECTED,
Dbg_Rst_13 => NLW_U0_Dbg_Rst_13_UNCONNECTED,
Dbg_Rst_14 => NLW_U0_Dbg_Rst_14_UNCONNECTED,
Dbg_Rst_15 => NLW_U0_Dbg_Rst_15_UNCONNECTED,
Dbg_Rst_16 => NLW_U0_Dbg_Rst_16_UNCONNECTED,
Dbg_Rst_17 => NLW_U0_Dbg_Rst_17_UNCONNECTED,
Dbg_Rst_18 => NLW_U0_Dbg_Rst_18_UNCONNECTED,
Dbg_Rst_19 => NLW_U0_Dbg_Rst_19_UNCONNECTED,
Dbg_Rst_2 => NLW_U0_Dbg_Rst_2_UNCONNECTED,
Dbg_Rst_20 => NLW_U0_Dbg_Rst_20_UNCONNECTED,
Dbg_Rst_21 => NLW_U0_Dbg_Rst_21_UNCONNECTED,
Dbg_Rst_22 => NLW_U0_Dbg_Rst_22_UNCONNECTED,
Dbg_Rst_23 => NLW_U0_Dbg_Rst_23_UNCONNECTED,
Dbg_Rst_24 => NLW_U0_Dbg_Rst_24_UNCONNECTED,
Dbg_Rst_25 => NLW_U0_Dbg_Rst_25_UNCONNECTED,
Dbg_Rst_26 => NLW_U0_Dbg_Rst_26_UNCONNECTED,
Dbg_Rst_27 => NLW_U0_Dbg_Rst_27_UNCONNECTED,
Dbg_Rst_28 => NLW_U0_Dbg_Rst_28_UNCONNECTED,
Dbg_Rst_29 => NLW_U0_Dbg_Rst_29_UNCONNECTED,
Dbg_Rst_3 => NLW_U0_Dbg_Rst_3_UNCONNECTED,
Dbg_Rst_30 => NLW_U0_Dbg_Rst_30_UNCONNECTED,
Dbg_Rst_31 => NLW_U0_Dbg_Rst_31_UNCONNECTED,
Dbg_Rst_4 => NLW_U0_Dbg_Rst_4_UNCONNECTED,
Dbg_Rst_5 => NLW_U0_Dbg_Rst_5_UNCONNECTED,
Dbg_Rst_6 => NLW_U0_Dbg_Rst_6_UNCONNECTED,
Dbg_Rst_7 => NLW_U0_Dbg_Rst_7_UNCONNECTED,
Dbg_Rst_8 => NLW_U0_Dbg_Rst_8_UNCONNECTED,
Dbg_Rst_9 => NLW_U0_Dbg_Rst_9_UNCONNECTED,
Dbg_Shift_0 => Dbg_Shift_0,
Dbg_Shift_1 => NLW_U0_Dbg_Shift_1_UNCONNECTED,
Dbg_Shift_10 => NLW_U0_Dbg_Shift_10_UNCONNECTED,
Dbg_Shift_11 => NLW_U0_Dbg_Shift_11_UNCONNECTED,
Dbg_Shift_12 => NLW_U0_Dbg_Shift_12_UNCONNECTED,
Dbg_Shift_13 => NLW_U0_Dbg_Shift_13_UNCONNECTED,
Dbg_Shift_14 => NLW_U0_Dbg_Shift_14_UNCONNECTED,
Dbg_Shift_15 => NLW_U0_Dbg_Shift_15_UNCONNECTED,
Dbg_Shift_16 => NLW_U0_Dbg_Shift_16_UNCONNECTED,
Dbg_Shift_17 => NLW_U0_Dbg_Shift_17_UNCONNECTED,
Dbg_Shift_18 => NLW_U0_Dbg_Shift_18_UNCONNECTED,
Dbg_Shift_19 => NLW_U0_Dbg_Shift_19_UNCONNECTED,
Dbg_Shift_2 => NLW_U0_Dbg_Shift_2_UNCONNECTED,
Dbg_Shift_20 => NLW_U0_Dbg_Shift_20_UNCONNECTED,
Dbg_Shift_21 => NLW_U0_Dbg_Shift_21_UNCONNECTED,
Dbg_Shift_22 => NLW_U0_Dbg_Shift_22_UNCONNECTED,
Dbg_Shift_23 => NLW_U0_Dbg_Shift_23_UNCONNECTED,
Dbg_Shift_24 => NLW_U0_Dbg_Shift_24_UNCONNECTED,
Dbg_Shift_25 => NLW_U0_Dbg_Shift_25_UNCONNECTED,
Dbg_Shift_26 => NLW_U0_Dbg_Shift_26_UNCONNECTED,
Dbg_Shift_27 => NLW_U0_Dbg_Shift_27_UNCONNECTED,
Dbg_Shift_28 => NLW_U0_Dbg_Shift_28_UNCONNECTED,
Dbg_Shift_29 => NLW_U0_Dbg_Shift_29_UNCONNECTED,
Dbg_Shift_3 => NLW_U0_Dbg_Shift_3_UNCONNECTED,
Dbg_Shift_30 => NLW_U0_Dbg_Shift_30_UNCONNECTED,
Dbg_Shift_31 => NLW_U0_Dbg_Shift_31_UNCONNECTED,
Dbg_Shift_4 => NLW_U0_Dbg_Shift_4_UNCONNECTED,
Dbg_Shift_5 => NLW_U0_Dbg_Shift_5_UNCONNECTED,
Dbg_Shift_6 => NLW_U0_Dbg_Shift_6_UNCONNECTED,
Dbg_Shift_7 => NLW_U0_Dbg_Shift_7_UNCONNECTED,
Dbg_Shift_8 => NLW_U0_Dbg_Shift_8_UNCONNECTED,
Dbg_Shift_9 => NLW_U0_Dbg_Shift_9_UNCONNECTED,
Dbg_TDI_0 => Dbg_TDI_0,
Dbg_TDI_1 => NLW_U0_Dbg_TDI_1_UNCONNECTED,
Dbg_TDI_10 => NLW_U0_Dbg_TDI_10_UNCONNECTED,
Dbg_TDI_11 => NLW_U0_Dbg_TDI_11_UNCONNECTED,
Dbg_TDI_12 => NLW_U0_Dbg_TDI_12_UNCONNECTED,
Dbg_TDI_13 => NLW_U0_Dbg_TDI_13_UNCONNECTED,
Dbg_TDI_14 => NLW_U0_Dbg_TDI_14_UNCONNECTED,
Dbg_TDI_15 => NLW_U0_Dbg_TDI_15_UNCONNECTED,
Dbg_TDI_16 => NLW_U0_Dbg_TDI_16_UNCONNECTED,
Dbg_TDI_17 => NLW_U0_Dbg_TDI_17_UNCONNECTED,
Dbg_TDI_18 => NLW_U0_Dbg_TDI_18_UNCONNECTED,
Dbg_TDI_19 => NLW_U0_Dbg_TDI_19_UNCONNECTED,
Dbg_TDI_2 => NLW_U0_Dbg_TDI_2_UNCONNECTED,
Dbg_TDI_20 => NLW_U0_Dbg_TDI_20_UNCONNECTED,
Dbg_TDI_21 => NLW_U0_Dbg_TDI_21_UNCONNECTED,
Dbg_TDI_22 => NLW_U0_Dbg_TDI_22_UNCONNECTED,
Dbg_TDI_23 => NLW_U0_Dbg_TDI_23_UNCONNECTED,
Dbg_TDI_24 => NLW_U0_Dbg_TDI_24_UNCONNECTED,
Dbg_TDI_25 => NLW_U0_Dbg_TDI_25_UNCONNECTED,
Dbg_TDI_26 => NLW_U0_Dbg_TDI_26_UNCONNECTED,
Dbg_TDI_27 => NLW_U0_Dbg_TDI_27_UNCONNECTED,
Dbg_TDI_28 => NLW_U0_Dbg_TDI_28_UNCONNECTED,
Dbg_TDI_29 => NLW_U0_Dbg_TDI_29_UNCONNECTED,
Dbg_TDI_3 => NLW_U0_Dbg_TDI_3_UNCONNECTED,
Dbg_TDI_30 => NLW_U0_Dbg_TDI_30_UNCONNECTED,
Dbg_TDI_31 => NLW_U0_Dbg_TDI_31_UNCONNECTED,
Dbg_TDI_4 => NLW_U0_Dbg_TDI_4_UNCONNECTED,
Dbg_TDI_5 => NLW_U0_Dbg_TDI_5_UNCONNECTED,
Dbg_TDI_6 => NLW_U0_Dbg_TDI_6_UNCONNECTED,
Dbg_TDI_7 => NLW_U0_Dbg_TDI_7_UNCONNECTED,
Dbg_TDI_8 => NLW_U0_Dbg_TDI_8_UNCONNECTED,
Dbg_TDI_9 => NLW_U0_Dbg_TDI_9_UNCONNECTED,
Dbg_TDO_0 => Dbg_TDO_0,
Dbg_TDO_1 => '0',
Dbg_TDO_10 => '0',
Dbg_TDO_11 => '0',
Dbg_TDO_12 => '0',
Dbg_TDO_13 => '0',
Dbg_TDO_14 => '0',
Dbg_TDO_15 => '0',
Dbg_TDO_16 => '0',
Dbg_TDO_17 => '0',
Dbg_TDO_18 => '0',
Dbg_TDO_19 => '0',
Dbg_TDO_2 => '0',
Dbg_TDO_20 => '0',
Dbg_TDO_21 => '0',
Dbg_TDO_22 => '0',
Dbg_TDO_23 => '0',
Dbg_TDO_24 => '0',
Dbg_TDO_25 => '0',
Dbg_TDO_26 => '0',
Dbg_TDO_27 => '0',
Dbg_TDO_28 => '0',
Dbg_TDO_29 => '0',
Dbg_TDO_3 => '0',
Dbg_TDO_30 => '0',
Dbg_TDO_31 => '0',
Dbg_TDO_4 => '0',
Dbg_TDO_5 => '0',
Dbg_TDO_6 => '0',
Dbg_TDO_7 => '0',
Dbg_TDO_8 => '0',
Dbg_TDO_9 => '0',
Dbg_TrClk_0 => NLW_U0_Dbg_TrClk_0_UNCONNECTED,
Dbg_TrClk_1 => NLW_U0_Dbg_TrClk_1_UNCONNECTED,
Dbg_TrClk_10 => NLW_U0_Dbg_TrClk_10_UNCONNECTED,
Dbg_TrClk_11 => NLW_U0_Dbg_TrClk_11_UNCONNECTED,
Dbg_TrClk_12 => NLW_U0_Dbg_TrClk_12_UNCONNECTED,
Dbg_TrClk_13 => NLW_U0_Dbg_TrClk_13_UNCONNECTED,
Dbg_TrClk_14 => NLW_U0_Dbg_TrClk_14_UNCONNECTED,
Dbg_TrClk_15 => NLW_U0_Dbg_TrClk_15_UNCONNECTED,
Dbg_TrClk_16 => NLW_U0_Dbg_TrClk_16_UNCONNECTED,
Dbg_TrClk_17 => NLW_U0_Dbg_TrClk_17_UNCONNECTED,
Dbg_TrClk_18 => NLW_U0_Dbg_TrClk_18_UNCONNECTED,
Dbg_TrClk_19 => NLW_U0_Dbg_TrClk_19_UNCONNECTED,
Dbg_TrClk_2 => NLW_U0_Dbg_TrClk_2_UNCONNECTED,
Dbg_TrClk_20 => NLW_U0_Dbg_TrClk_20_UNCONNECTED,
Dbg_TrClk_21 => NLW_U0_Dbg_TrClk_21_UNCONNECTED,
Dbg_TrClk_22 => NLW_U0_Dbg_TrClk_22_UNCONNECTED,
Dbg_TrClk_23 => NLW_U0_Dbg_TrClk_23_UNCONNECTED,
Dbg_TrClk_24 => NLW_U0_Dbg_TrClk_24_UNCONNECTED,
Dbg_TrClk_25 => NLW_U0_Dbg_TrClk_25_UNCONNECTED,
Dbg_TrClk_26 => NLW_U0_Dbg_TrClk_26_UNCONNECTED,
Dbg_TrClk_27 => NLW_U0_Dbg_TrClk_27_UNCONNECTED,
Dbg_TrClk_28 => NLW_U0_Dbg_TrClk_28_UNCONNECTED,
Dbg_TrClk_29 => NLW_U0_Dbg_TrClk_29_UNCONNECTED,
Dbg_TrClk_3 => NLW_U0_Dbg_TrClk_3_UNCONNECTED,
Dbg_TrClk_30 => NLW_U0_Dbg_TrClk_30_UNCONNECTED,
Dbg_TrClk_31 => NLW_U0_Dbg_TrClk_31_UNCONNECTED,
Dbg_TrClk_4 => NLW_U0_Dbg_TrClk_4_UNCONNECTED,
Dbg_TrClk_5 => NLW_U0_Dbg_TrClk_5_UNCONNECTED,
Dbg_TrClk_6 => NLW_U0_Dbg_TrClk_6_UNCONNECTED,
Dbg_TrClk_7 => NLW_U0_Dbg_TrClk_7_UNCONNECTED,
Dbg_TrClk_8 => NLW_U0_Dbg_TrClk_8_UNCONNECTED,
Dbg_TrClk_9 => NLW_U0_Dbg_TrClk_9_UNCONNECTED,
Dbg_TrData_0(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_1(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_10(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_11(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_12(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_13(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_14(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_15(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_16(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_17(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_18(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_19(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_2(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_20(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_21(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_22(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_23(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_24(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_25(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_26(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_27(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_28(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_29(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_3(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_30(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_31(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_4(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_5(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_6(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_7(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_8(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrData_9(0 to 35) => B"000000000000000000000000000000000000",
Dbg_TrReady_0 => NLW_U0_Dbg_TrReady_0_UNCONNECTED,
Dbg_TrReady_1 => NLW_U0_Dbg_TrReady_1_UNCONNECTED,
Dbg_TrReady_10 => NLW_U0_Dbg_TrReady_10_UNCONNECTED,
Dbg_TrReady_11 => NLW_U0_Dbg_TrReady_11_UNCONNECTED,
Dbg_TrReady_12 => NLW_U0_Dbg_TrReady_12_UNCONNECTED,
Dbg_TrReady_13 => NLW_U0_Dbg_TrReady_13_UNCONNECTED,
Dbg_TrReady_14 => NLW_U0_Dbg_TrReady_14_UNCONNECTED,
Dbg_TrReady_15 => NLW_U0_Dbg_TrReady_15_UNCONNECTED,
Dbg_TrReady_16 => NLW_U0_Dbg_TrReady_16_UNCONNECTED,
Dbg_TrReady_17 => NLW_U0_Dbg_TrReady_17_UNCONNECTED,
Dbg_TrReady_18 => NLW_U0_Dbg_TrReady_18_UNCONNECTED,
Dbg_TrReady_19 => NLW_U0_Dbg_TrReady_19_UNCONNECTED,
Dbg_TrReady_2 => NLW_U0_Dbg_TrReady_2_UNCONNECTED,
Dbg_TrReady_20 => NLW_U0_Dbg_TrReady_20_UNCONNECTED,
Dbg_TrReady_21 => NLW_U0_Dbg_TrReady_21_UNCONNECTED,
Dbg_TrReady_22 => NLW_U0_Dbg_TrReady_22_UNCONNECTED,
Dbg_TrReady_23 => NLW_U0_Dbg_TrReady_23_UNCONNECTED,
Dbg_TrReady_24 => NLW_U0_Dbg_TrReady_24_UNCONNECTED,
Dbg_TrReady_25 => NLW_U0_Dbg_TrReady_25_UNCONNECTED,
Dbg_TrReady_26 => NLW_U0_Dbg_TrReady_26_UNCONNECTED,
Dbg_TrReady_27 => NLW_U0_Dbg_TrReady_27_UNCONNECTED,
Dbg_TrReady_28 => NLW_U0_Dbg_TrReady_28_UNCONNECTED,
Dbg_TrReady_29 => NLW_U0_Dbg_TrReady_29_UNCONNECTED,
Dbg_TrReady_3 => NLW_U0_Dbg_TrReady_3_UNCONNECTED,
Dbg_TrReady_30 => NLW_U0_Dbg_TrReady_30_UNCONNECTED,
Dbg_TrReady_31 => NLW_U0_Dbg_TrReady_31_UNCONNECTED,
Dbg_TrReady_4 => NLW_U0_Dbg_TrReady_4_UNCONNECTED,
Dbg_TrReady_5 => NLW_U0_Dbg_TrReady_5_UNCONNECTED,
Dbg_TrReady_6 => NLW_U0_Dbg_TrReady_6_UNCONNECTED,
Dbg_TrReady_7 => NLW_U0_Dbg_TrReady_7_UNCONNECTED,
Dbg_TrReady_8 => NLW_U0_Dbg_TrReady_8_UNCONNECTED,
Dbg_TrReady_9 => NLW_U0_Dbg_TrReady_9_UNCONNECTED,
Dbg_TrValid_0 => '0',
Dbg_TrValid_1 => '0',
Dbg_TrValid_10 => '0',
Dbg_TrValid_11 => '0',
Dbg_TrValid_12 => '0',
Dbg_TrValid_13 => '0',
Dbg_TrValid_14 => '0',
Dbg_TrValid_15 => '0',
Dbg_TrValid_16 => '0',
Dbg_TrValid_17 => '0',
Dbg_TrValid_18 => '0',
Dbg_TrValid_19 => '0',
Dbg_TrValid_2 => '0',
Dbg_TrValid_20 => '0',
Dbg_TrValid_21 => '0',
Dbg_TrValid_22 => '0',
Dbg_TrValid_23 => '0',
Dbg_TrValid_24 => '0',
Dbg_TrValid_25 => '0',
Dbg_TrValid_26 => '0',
Dbg_TrValid_27 => '0',
Dbg_TrValid_28 => '0',
Dbg_TrValid_29 => '0',
Dbg_TrValid_3 => '0',
Dbg_TrValid_30 => '0',
Dbg_TrValid_31 => '0',
Dbg_TrValid_4 => '0',
Dbg_TrValid_5 => '0',
Dbg_TrValid_6 => '0',
Dbg_TrValid_7 => '0',
Dbg_TrValid_8 => '0',
Dbg_TrValid_9 => '0',
Dbg_Trig_Ack_In_0(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_0_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_1(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_1_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_10(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_10_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_11(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_11_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_12(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_12_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_13(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_13_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_14(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_14_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_15(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_15_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_16(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_16_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_17(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_17_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_18(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_18_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_19(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_19_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_2(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_2_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_20(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_20_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_21(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_21_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_22(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_22_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_23(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_23_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_24(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_24_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_25(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_25_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_26(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_26_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_27(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_27_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_28(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_28_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_29(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_29_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_3(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_3_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_30(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_30_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_31(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_31_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_4(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_4_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_5(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_5_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_6(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_6_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_7(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_7_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_8(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_8_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_In_9(0 to 7) => NLW_U0_Dbg_Trig_Ack_In_9_UNCONNECTED(0 to 7),
Dbg_Trig_Ack_Out_0(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_1(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_10(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_11(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_12(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_13(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_14(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_15(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_16(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_17(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_18(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_19(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_2(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_20(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_21(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_22(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_23(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_24(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_25(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_26(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_27(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_28(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_29(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_3(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_30(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_31(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_4(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_5(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_6(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_7(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_8(0 to 7) => B"00000000",
Dbg_Trig_Ack_Out_9(0 to 7) => B"00000000",
Dbg_Trig_In_0(0 to 7) => B"00000000",
Dbg_Trig_In_1(0 to 7) => B"00000000",
Dbg_Trig_In_10(0 to 7) => B"00000000",
Dbg_Trig_In_11(0 to 7) => B"00000000",
Dbg_Trig_In_12(0 to 7) => B"00000000",
Dbg_Trig_In_13(0 to 7) => B"00000000",
Dbg_Trig_In_14(0 to 7) => B"00000000",
Dbg_Trig_In_15(0 to 7) => B"00000000",
Dbg_Trig_In_16(0 to 7) => B"00000000",
Dbg_Trig_In_17(0 to 7) => B"00000000",
Dbg_Trig_In_18(0 to 7) => B"00000000",
Dbg_Trig_In_19(0 to 7) => B"00000000",
Dbg_Trig_In_2(0 to 7) => B"00000000",
Dbg_Trig_In_20(0 to 7) => B"00000000",
Dbg_Trig_In_21(0 to 7) => B"00000000",
Dbg_Trig_In_22(0 to 7) => B"00000000",
Dbg_Trig_In_23(0 to 7) => B"00000000",
Dbg_Trig_In_24(0 to 7) => B"00000000",
Dbg_Trig_In_25(0 to 7) => B"00000000",
Dbg_Trig_In_26(0 to 7) => B"00000000",
Dbg_Trig_In_27(0 to 7) => B"00000000",
Dbg_Trig_In_28(0 to 7) => B"00000000",
Dbg_Trig_In_29(0 to 7) => B"00000000",
Dbg_Trig_In_3(0 to 7) => B"00000000",
Dbg_Trig_In_30(0 to 7) => B"00000000",
Dbg_Trig_In_31(0 to 7) => B"00000000",
Dbg_Trig_In_4(0 to 7) => B"00000000",
Dbg_Trig_In_5(0 to 7) => B"00000000",
Dbg_Trig_In_6(0 to 7) => B"00000000",
Dbg_Trig_In_7(0 to 7) => B"00000000",
Dbg_Trig_In_8(0 to 7) => B"00000000",
Dbg_Trig_In_9(0 to 7) => B"00000000",
Dbg_Trig_Out_0(0 to 7) => NLW_U0_Dbg_Trig_Out_0_UNCONNECTED(0 to 7),
Dbg_Trig_Out_1(0 to 7) => NLW_U0_Dbg_Trig_Out_1_UNCONNECTED(0 to 7),
Dbg_Trig_Out_10(0 to 7) => NLW_U0_Dbg_Trig_Out_10_UNCONNECTED(0 to 7),
Dbg_Trig_Out_11(0 to 7) => NLW_U0_Dbg_Trig_Out_11_UNCONNECTED(0 to 7),
Dbg_Trig_Out_12(0 to 7) => NLW_U0_Dbg_Trig_Out_12_UNCONNECTED(0 to 7),
Dbg_Trig_Out_13(0 to 7) => NLW_U0_Dbg_Trig_Out_13_UNCONNECTED(0 to 7),
Dbg_Trig_Out_14(0 to 7) => NLW_U0_Dbg_Trig_Out_14_UNCONNECTED(0 to 7),
Dbg_Trig_Out_15(0 to 7) => NLW_U0_Dbg_Trig_Out_15_UNCONNECTED(0 to 7),
Dbg_Trig_Out_16(0 to 7) => NLW_U0_Dbg_Trig_Out_16_UNCONNECTED(0 to 7),
Dbg_Trig_Out_17(0 to 7) => NLW_U0_Dbg_Trig_Out_17_UNCONNECTED(0 to 7),
Dbg_Trig_Out_18(0 to 7) => NLW_U0_Dbg_Trig_Out_18_UNCONNECTED(0 to 7),
Dbg_Trig_Out_19(0 to 7) => NLW_U0_Dbg_Trig_Out_19_UNCONNECTED(0 to 7),
Dbg_Trig_Out_2(0 to 7) => NLW_U0_Dbg_Trig_Out_2_UNCONNECTED(0 to 7),
Dbg_Trig_Out_20(0 to 7) => NLW_U0_Dbg_Trig_Out_20_UNCONNECTED(0 to 7),
Dbg_Trig_Out_21(0 to 7) => NLW_U0_Dbg_Trig_Out_21_UNCONNECTED(0 to 7),
Dbg_Trig_Out_22(0 to 7) => NLW_U0_Dbg_Trig_Out_22_UNCONNECTED(0 to 7),
Dbg_Trig_Out_23(0 to 7) => NLW_U0_Dbg_Trig_Out_23_UNCONNECTED(0 to 7),
Dbg_Trig_Out_24(0 to 7) => NLW_U0_Dbg_Trig_Out_24_UNCONNECTED(0 to 7),
Dbg_Trig_Out_25(0 to 7) => NLW_U0_Dbg_Trig_Out_25_UNCONNECTED(0 to 7),
Dbg_Trig_Out_26(0 to 7) => NLW_U0_Dbg_Trig_Out_26_UNCONNECTED(0 to 7),
Dbg_Trig_Out_27(0 to 7) => NLW_U0_Dbg_Trig_Out_27_UNCONNECTED(0 to 7),
Dbg_Trig_Out_28(0 to 7) => NLW_U0_Dbg_Trig_Out_28_UNCONNECTED(0 to 7),
Dbg_Trig_Out_29(0 to 7) => NLW_U0_Dbg_Trig_Out_29_UNCONNECTED(0 to 7),
Dbg_Trig_Out_3(0 to 7) => NLW_U0_Dbg_Trig_Out_3_UNCONNECTED(0 to 7),
Dbg_Trig_Out_30(0 to 7) => NLW_U0_Dbg_Trig_Out_30_UNCONNECTED(0 to 7),
Dbg_Trig_Out_31(0 to 7) => NLW_U0_Dbg_Trig_Out_31_UNCONNECTED(0 to 7),
Dbg_Trig_Out_4(0 to 7) => NLW_U0_Dbg_Trig_Out_4_UNCONNECTED(0 to 7),
Dbg_Trig_Out_5(0 to 7) => NLW_U0_Dbg_Trig_Out_5_UNCONNECTED(0 to 7),
Dbg_Trig_Out_6(0 to 7) => NLW_U0_Dbg_Trig_Out_6_UNCONNECTED(0 to 7),
Dbg_Trig_Out_7(0 to 7) => NLW_U0_Dbg_Trig_Out_7_UNCONNECTED(0 to 7),
Dbg_Trig_Out_8(0 to 7) => NLW_U0_Dbg_Trig_Out_8_UNCONNECTED(0 to 7),
Dbg_Trig_Out_9(0 to 7) => NLW_U0_Dbg_Trig_Out_9_UNCONNECTED(0 to 7),
Dbg_Update_0 => Dbg_Update_0,
Dbg_Update_1 => NLW_U0_Dbg_Update_1_UNCONNECTED,
Dbg_Update_10 => NLW_U0_Dbg_Update_10_UNCONNECTED,
Dbg_Update_11 => NLW_U0_Dbg_Update_11_UNCONNECTED,
Dbg_Update_12 => NLW_U0_Dbg_Update_12_UNCONNECTED,
Dbg_Update_13 => NLW_U0_Dbg_Update_13_UNCONNECTED,
Dbg_Update_14 => NLW_U0_Dbg_Update_14_UNCONNECTED,
Dbg_Update_15 => NLW_U0_Dbg_Update_15_UNCONNECTED,
Dbg_Update_16 => NLW_U0_Dbg_Update_16_UNCONNECTED,
Dbg_Update_17 => NLW_U0_Dbg_Update_17_UNCONNECTED,
Dbg_Update_18 => NLW_U0_Dbg_Update_18_UNCONNECTED,
Dbg_Update_19 => NLW_U0_Dbg_Update_19_UNCONNECTED,
Dbg_Update_2 => NLW_U0_Dbg_Update_2_UNCONNECTED,
Dbg_Update_20 => NLW_U0_Dbg_Update_20_UNCONNECTED,
Dbg_Update_21 => NLW_U0_Dbg_Update_21_UNCONNECTED,
Dbg_Update_22 => NLW_U0_Dbg_Update_22_UNCONNECTED,
Dbg_Update_23 => NLW_U0_Dbg_Update_23_UNCONNECTED,
Dbg_Update_24 => NLW_U0_Dbg_Update_24_UNCONNECTED,
Dbg_Update_25 => NLW_U0_Dbg_Update_25_UNCONNECTED,
Dbg_Update_26 => NLW_U0_Dbg_Update_26_UNCONNECTED,
Dbg_Update_27 => NLW_U0_Dbg_Update_27_UNCONNECTED,
Dbg_Update_28 => NLW_U0_Dbg_Update_28_UNCONNECTED,
Dbg_Update_29 => NLW_U0_Dbg_Update_29_UNCONNECTED,
Dbg_Update_3 => NLW_U0_Dbg_Update_3_UNCONNECTED,
Dbg_Update_30 => NLW_U0_Dbg_Update_30_UNCONNECTED,
Dbg_Update_31 => NLW_U0_Dbg_Update_31_UNCONNECTED,
Dbg_Update_4 => NLW_U0_Dbg_Update_4_UNCONNECTED,
Dbg_Update_5 => NLW_U0_Dbg_Update_5_UNCONNECTED,
Dbg_Update_6 => NLW_U0_Dbg_Update_6_UNCONNECTED,
Dbg_Update_7 => NLW_U0_Dbg_Update_7_UNCONNECTED,
Dbg_Update_8 => NLW_U0_Dbg_Update_8_UNCONNECTED,
Dbg_Update_9 => NLW_U0_Dbg_Update_9_UNCONNECTED,
Dbg_WDATA_0(31 downto 0) => NLW_U0_Dbg_WDATA_0_UNCONNECTED(31 downto 0),
Dbg_WDATA_1(31 downto 0) => NLW_U0_Dbg_WDATA_1_UNCONNECTED(31 downto 0),
Dbg_WDATA_10(31 downto 0) => NLW_U0_Dbg_WDATA_10_UNCONNECTED(31 downto 0),
Dbg_WDATA_11(31 downto 0) => NLW_U0_Dbg_WDATA_11_UNCONNECTED(31 downto 0),
Dbg_WDATA_12(31 downto 0) => NLW_U0_Dbg_WDATA_12_UNCONNECTED(31 downto 0),
Dbg_WDATA_13(31 downto 0) => NLW_U0_Dbg_WDATA_13_UNCONNECTED(31 downto 0),
Dbg_WDATA_14(31 downto 0) => NLW_U0_Dbg_WDATA_14_UNCONNECTED(31 downto 0),
Dbg_WDATA_15(31 downto 0) => NLW_U0_Dbg_WDATA_15_UNCONNECTED(31 downto 0),
Dbg_WDATA_16(31 downto 0) => NLW_U0_Dbg_WDATA_16_UNCONNECTED(31 downto 0),
Dbg_WDATA_17(31 downto 0) => NLW_U0_Dbg_WDATA_17_UNCONNECTED(31 downto 0),
Dbg_WDATA_18(31 downto 0) => NLW_U0_Dbg_WDATA_18_UNCONNECTED(31 downto 0),
Dbg_WDATA_19(31 downto 0) => NLW_U0_Dbg_WDATA_19_UNCONNECTED(31 downto 0),
Dbg_WDATA_2(31 downto 0) => NLW_U0_Dbg_WDATA_2_UNCONNECTED(31 downto 0),
Dbg_WDATA_20(31 downto 0) => NLW_U0_Dbg_WDATA_20_UNCONNECTED(31 downto 0),
Dbg_WDATA_21(31 downto 0) => NLW_U0_Dbg_WDATA_21_UNCONNECTED(31 downto 0),
Dbg_WDATA_22(31 downto 0) => NLW_U0_Dbg_WDATA_22_UNCONNECTED(31 downto 0),
Dbg_WDATA_23(31 downto 0) => NLW_U0_Dbg_WDATA_23_UNCONNECTED(31 downto 0),
Dbg_WDATA_24(31 downto 0) => NLW_U0_Dbg_WDATA_24_UNCONNECTED(31 downto 0),
Dbg_WDATA_25(31 downto 0) => NLW_U0_Dbg_WDATA_25_UNCONNECTED(31 downto 0),
Dbg_WDATA_26(31 downto 0) => NLW_U0_Dbg_WDATA_26_UNCONNECTED(31 downto 0),
Dbg_WDATA_27(31 downto 0) => NLW_U0_Dbg_WDATA_27_UNCONNECTED(31 downto 0),
Dbg_WDATA_28(31 downto 0) => NLW_U0_Dbg_WDATA_28_UNCONNECTED(31 downto 0),
Dbg_WDATA_29(31 downto 0) => NLW_U0_Dbg_WDATA_29_UNCONNECTED(31 downto 0),
Dbg_WDATA_3(31 downto 0) => NLW_U0_Dbg_WDATA_3_UNCONNECTED(31 downto 0),
Dbg_WDATA_30(31 downto 0) => NLW_U0_Dbg_WDATA_30_UNCONNECTED(31 downto 0),
Dbg_WDATA_31(31 downto 0) => NLW_U0_Dbg_WDATA_31_UNCONNECTED(31 downto 0),
Dbg_WDATA_4(31 downto 0) => NLW_U0_Dbg_WDATA_4_UNCONNECTED(31 downto 0),
Dbg_WDATA_5(31 downto 0) => NLW_U0_Dbg_WDATA_5_UNCONNECTED(31 downto 0),
Dbg_WDATA_6(31 downto 0) => NLW_U0_Dbg_WDATA_6_UNCONNECTED(31 downto 0),
Dbg_WDATA_7(31 downto 0) => NLW_U0_Dbg_WDATA_7_UNCONNECTED(31 downto 0),
Dbg_WDATA_8(31 downto 0) => NLW_U0_Dbg_WDATA_8_UNCONNECTED(31 downto 0),
Dbg_WDATA_9(31 downto 0) => NLW_U0_Dbg_WDATA_9_UNCONNECTED(31 downto 0),
Dbg_WREADY_0 => '0',
Dbg_WREADY_1 => '0',
Dbg_WREADY_10 => '0',
Dbg_WREADY_11 => '0',
Dbg_WREADY_12 => '0',
Dbg_WREADY_13 => '0',
Dbg_WREADY_14 => '0',
Dbg_WREADY_15 => '0',
Dbg_WREADY_16 => '0',
Dbg_WREADY_17 => '0',
Dbg_WREADY_18 => '0',
Dbg_WREADY_19 => '0',
Dbg_WREADY_2 => '0',
Dbg_WREADY_20 => '0',
Dbg_WREADY_21 => '0',
Dbg_WREADY_22 => '0',
Dbg_WREADY_23 => '0',
Dbg_WREADY_24 => '0',
Dbg_WREADY_25 => '0',
Dbg_WREADY_26 => '0',
Dbg_WREADY_27 => '0',
Dbg_WREADY_28 => '0',
Dbg_WREADY_29 => '0',
Dbg_WREADY_3 => '0',
Dbg_WREADY_30 => '0',
Dbg_WREADY_31 => '0',
Dbg_WREADY_4 => '0',
Dbg_WREADY_5 => '0',
Dbg_WREADY_6 => '0',
Dbg_WREADY_7 => '0',
Dbg_WREADY_8 => '0',
Dbg_WREADY_9 => '0',
Dbg_WVALID_0 => NLW_U0_Dbg_WVALID_0_UNCONNECTED,
Dbg_WVALID_1 => NLW_U0_Dbg_WVALID_1_UNCONNECTED,
Dbg_WVALID_10 => NLW_U0_Dbg_WVALID_10_UNCONNECTED,
Dbg_WVALID_11 => NLW_U0_Dbg_WVALID_11_UNCONNECTED,
Dbg_WVALID_12 => NLW_U0_Dbg_WVALID_12_UNCONNECTED,
Dbg_WVALID_13 => NLW_U0_Dbg_WVALID_13_UNCONNECTED,
Dbg_WVALID_14 => NLW_U0_Dbg_WVALID_14_UNCONNECTED,
Dbg_WVALID_15 => NLW_U0_Dbg_WVALID_15_UNCONNECTED,
Dbg_WVALID_16 => NLW_U0_Dbg_WVALID_16_UNCONNECTED,
Dbg_WVALID_17 => NLW_U0_Dbg_WVALID_17_UNCONNECTED,
Dbg_WVALID_18 => NLW_U0_Dbg_WVALID_18_UNCONNECTED,
Dbg_WVALID_19 => NLW_U0_Dbg_WVALID_19_UNCONNECTED,
Dbg_WVALID_2 => NLW_U0_Dbg_WVALID_2_UNCONNECTED,
Dbg_WVALID_20 => NLW_U0_Dbg_WVALID_20_UNCONNECTED,
Dbg_WVALID_21 => NLW_U0_Dbg_WVALID_21_UNCONNECTED,
Dbg_WVALID_22 => NLW_U0_Dbg_WVALID_22_UNCONNECTED,
Dbg_WVALID_23 => NLW_U0_Dbg_WVALID_23_UNCONNECTED,
Dbg_WVALID_24 => NLW_U0_Dbg_WVALID_24_UNCONNECTED,
Dbg_WVALID_25 => NLW_U0_Dbg_WVALID_25_UNCONNECTED,
Dbg_WVALID_26 => NLW_U0_Dbg_WVALID_26_UNCONNECTED,
Dbg_WVALID_27 => NLW_U0_Dbg_WVALID_27_UNCONNECTED,
Dbg_WVALID_28 => NLW_U0_Dbg_WVALID_28_UNCONNECTED,
Dbg_WVALID_29 => NLW_U0_Dbg_WVALID_29_UNCONNECTED,
Dbg_WVALID_3 => NLW_U0_Dbg_WVALID_3_UNCONNECTED,
Dbg_WVALID_30 => NLW_U0_Dbg_WVALID_30_UNCONNECTED,
Dbg_WVALID_31 => NLW_U0_Dbg_WVALID_31_UNCONNECTED,
Dbg_WVALID_4 => NLW_U0_Dbg_WVALID_4_UNCONNECTED,
Dbg_WVALID_5 => NLW_U0_Dbg_WVALID_5_UNCONNECTED,
Dbg_WVALID_6 => NLW_U0_Dbg_WVALID_6_UNCONNECTED,
Dbg_WVALID_7 => NLW_U0_Dbg_WVALID_7_UNCONNECTED,
Dbg_WVALID_8 => NLW_U0_Dbg_WVALID_8_UNCONNECTED,
Dbg_WVALID_9 => NLW_U0_Dbg_WVALID_9_UNCONNECTED,
Debug_SYS_Rst => Debug_SYS_Rst,
Ext_BRK => NLW_U0_Ext_BRK_UNCONNECTED,
Ext_JTAG_CAPTURE => NLW_U0_Ext_JTAG_CAPTURE_UNCONNECTED,
Ext_JTAG_DRCK => NLW_U0_Ext_JTAG_DRCK_UNCONNECTED,
Ext_JTAG_RESET => NLW_U0_Ext_JTAG_RESET_UNCONNECTED,
Ext_JTAG_SEL => NLW_U0_Ext_JTAG_SEL_UNCONNECTED,
Ext_JTAG_SHIFT => NLW_U0_Ext_JTAG_SHIFT_UNCONNECTED,
Ext_JTAG_TDI => NLW_U0_Ext_JTAG_TDI_UNCONNECTED,
Ext_JTAG_TDO => '0',
Ext_JTAG_UPDATE => NLW_U0_Ext_JTAG_UPDATE_UNCONNECTED,
Ext_NM_BRK => NLW_U0_Ext_NM_BRK_UNCONNECTED,
Interrupt => NLW_U0_Interrupt_UNCONNECTED,
LMB_Addr_Strobe_0 => NLW_U0_LMB_Addr_Strobe_0_UNCONNECTED,
LMB_Addr_Strobe_1 => NLW_U0_LMB_Addr_Strobe_1_UNCONNECTED,
LMB_Addr_Strobe_10 => NLW_U0_LMB_Addr_Strobe_10_UNCONNECTED,
LMB_Addr_Strobe_11 => NLW_U0_LMB_Addr_Strobe_11_UNCONNECTED,
LMB_Addr_Strobe_12 => NLW_U0_LMB_Addr_Strobe_12_UNCONNECTED,
LMB_Addr_Strobe_13 => NLW_U0_LMB_Addr_Strobe_13_UNCONNECTED,
LMB_Addr_Strobe_14 => NLW_U0_LMB_Addr_Strobe_14_UNCONNECTED,
LMB_Addr_Strobe_15 => NLW_U0_LMB_Addr_Strobe_15_UNCONNECTED,
LMB_Addr_Strobe_16 => NLW_U0_LMB_Addr_Strobe_16_UNCONNECTED,
LMB_Addr_Strobe_17 => NLW_U0_LMB_Addr_Strobe_17_UNCONNECTED,
LMB_Addr_Strobe_18 => NLW_U0_LMB_Addr_Strobe_18_UNCONNECTED,
LMB_Addr_Strobe_19 => NLW_U0_LMB_Addr_Strobe_19_UNCONNECTED,
LMB_Addr_Strobe_2 => NLW_U0_LMB_Addr_Strobe_2_UNCONNECTED,
LMB_Addr_Strobe_20 => NLW_U0_LMB_Addr_Strobe_20_UNCONNECTED,
LMB_Addr_Strobe_21 => NLW_U0_LMB_Addr_Strobe_21_UNCONNECTED,
LMB_Addr_Strobe_22 => NLW_U0_LMB_Addr_Strobe_22_UNCONNECTED,
LMB_Addr_Strobe_23 => NLW_U0_LMB_Addr_Strobe_23_UNCONNECTED,
LMB_Addr_Strobe_24 => NLW_U0_LMB_Addr_Strobe_24_UNCONNECTED,
LMB_Addr_Strobe_25 => NLW_U0_LMB_Addr_Strobe_25_UNCONNECTED,
LMB_Addr_Strobe_26 => NLW_U0_LMB_Addr_Strobe_26_UNCONNECTED,
LMB_Addr_Strobe_27 => NLW_U0_LMB_Addr_Strobe_27_UNCONNECTED,
LMB_Addr_Strobe_28 => NLW_U0_LMB_Addr_Strobe_28_UNCONNECTED,
LMB_Addr_Strobe_29 => NLW_U0_LMB_Addr_Strobe_29_UNCONNECTED,
LMB_Addr_Strobe_3 => NLW_U0_LMB_Addr_Strobe_3_UNCONNECTED,
LMB_Addr_Strobe_30 => NLW_U0_LMB_Addr_Strobe_30_UNCONNECTED,
LMB_Addr_Strobe_31 => NLW_U0_LMB_Addr_Strobe_31_UNCONNECTED,
LMB_Addr_Strobe_4 => NLW_U0_LMB_Addr_Strobe_4_UNCONNECTED,
LMB_Addr_Strobe_5 => NLW_U0_LMB_Addr_Strobe_5_UNCONNECTED,
LMB_Addr_Strobe_6 => NLW_U0_LMB_Addr_Strobe_6_UNCONNECTED,
LMB_Addr_Strobe_7 => NLW_U0_LMB_Addr_Strobe_7_UNCONNECTED,
LMB_Addr_Strobe_8 => NLW_U0_LMB_Addr_Strobe_8_UNCONNECTED,
LMB_Addr_Strobe_9 => NLW_U0_LMB_Addr_Strobe_9_UNCONNECTED,
LMB_Byte_Enable_0(0 to 3) => NLW_U0_LMB_Byte_Enable_0_UNCONNECTED(0 to 3),
LMB_Byte_Enable_1(0 to 3) => NLW_U0_LMB_Byte_Enable_1_UNCONNECTED(0 to 3),
LMB_Byte_Enable_10(0 to 3) => NLW_U0_LMB_Byte_Enable_10_UNCONNECTED(0 to 3),
LMB_Byte_Enable_11(0 to 3) => NLW_U0_LMB_Byte_Enable_11_UNCONNECTED(0 to 3),
LMB_Byte_Enable_12(0 to 3) => NLW_U0_LMB_Byte_Enable_12_UNCONNECTED(0 to 3),
LMB_Byte_Enable_13(0 to 3) => NLW_U0_LMB_Byte_Enable_13_UNCONNECTED(0 to 3),
LMB_Byte_Enable_14(0 to 3) => NLW_U0_LMB_Byte_Enable_14_UNCONNECTED(0 to 3),
LMB_Byte_Enable_15(0 to 3) => NLW_U0_LMB_Byte_Enable_15_UNCONNECTED(0 to 3),
LMB_Byte_Enable_16(0 to 3) => NLW_U0_LMB_Byte_Enable_16_UNCONNECTED(0 to 3),
LMB_Byte_Enable_17(0 to 3) => NLW_U0_LMB_Byte_Enable_17_UNCONNECTED(0 to 3),
LMB_Byte_Enable_18(0 to 3) => NLW_U0_LMB_Byte_Enable_18_UNCONNECTED(0 to 3),
LMB_Byte_Enable_19(0 to 3) => NLW_U0_LMB_Byte_Enable_19_UNCONNECTED(0 to 3),
LMB_Byte_Enable_2(0 to 3) => NLW_U0_LMB_Byte_Enable_2_UNCONNECTED(0 to 3),
LMB_Byte_Enable_20(0 to 3) => NLW_U0_LMB_Byte_Enable_20_UNCONNECTED(0 to 3),
LMB_Byte_Enable_21(0 to 3) => NLW_U0_LMB_Byte_Enable_21_UNCONNECTED(0 to 3),
LMB_Byte_Enable_22(0 to 3) => NLW_U0_LMB_Byte_Enable_22_UNCONNECTED(0 to 3),
LMB_Byte_Enable_23(0 to 3) => NLW_U0_LMB_Byte_Enable_23_UNCONNECTED(0 to 3),
LMB_Byte_Enable_24(0 to 3) => NLW_U0_LMB_Byte_Enable_24_UNCONNECTED(0 to 3),
LMB_Byte_Enable_25(0 to 3) => NLW_U0_LMB_Byte_Enable_25_UNCONNECTED(0 to 3),
LMB_Byte_Enable_26(0 to 3) => NLW_U0_LMB_Byte_Enable_26_UNCONNECTED(0 to 3),
LMB_Byte_Enable_27(0 to 3) => NLW_U0_LMB_Byte_Enable_27_UNCONNECTED(0 to 3),
LMB_Byte_Enable_28(0 to 3) => NLW_U0_LMB_Byte_Enable_28_UNCONNECTED(0 to 3),
LMB_Byte_Enable_29(0 to 3) => NLW_U0_LMB_Byte_Enable_29_UNCONNECTED(0 to 3),
LMB_Byte_Enable_3(0 to 3) => NLW_U0_LMB_Byte_Enable_3_UNCONNECTED(0 to 3),
LMB_Byte_Enable_30(0 to 3) => NLW_U0_LMB_Byte_Enable_30_UNCONNECTED(0 to 3),
LMB_Byte_Enable_31(0 to 3) => NLW_U0_LMB_Byte_Enable_31_UNCONNECTED(0 to 3),
LMB_Byte_Enable_4(0 to 3) => NLW_U0_LMB_Byte_Enable_4_UNCONNECTED(0 to 3),
LMB_Byte_Enable_5(0 to 3) => NLW_U0_LMB_Byte_Enable_5_UNCONNECTED(0 to 3),
LMB_Byte_Enable_6(0 to 3) => NLW_U0_LMB_Byte_Enable_6_UNCONNECTED(0 to 3),
LMB_Byte_Enable_7(0 to 3) => NLW_U0_LMB_Byte_Enable_7_UNCONNECTED(0 to 3),
LMB_Byte_Enable_8(0 to 3) => NLW_U0_LMB_Byte_Enable_8_UNCONNECTED(0 to 3),
LMB_Byte_Enable_9(0 to 3) => NLW_U0_LMB_Byte_Enable_9_UNCONNECTED(0 to 3),
LMB_CE_0 => '0',
LMB_CE_1 => '0',
LMB_CE_10 => '0',
LMB_CE_11 => '0',
LMB_CE_12 => '0',
LMB_CE_13 => '0',
LMB_CE_14 => '0',
LMB_CE_15 => '0',
LMB_CE_16 => '0',
LMB_CE_17 => '0',
LMB_CE_18 => '0',
LMB_CE_19 => '0',
LMB_CE_2 => '0',
LMB_CE_20 => '0',
LMB_CE_21 => '0',
LMB_CE_22 => '0',
LMB_CE_23 => '0',
LMB_CE_24 => '0',
LMB_CE_25 => '0',
LMB_CE_26 => '0',
LMB_CE_27 => '0',
LMB_CE_28 => '0',
LMB_CE_29 => '0',
LMB_CE_3 => '0',
LMB_CE_30 => '0',
LMB_CE_31 => '0',
LMB_CE_4 => '0',
LMB_CE_5 => '0',
LMB_CE_6 => '0',
LMB_CE_7 => '0',
LMB_CE_8 => '0',
LMB_CE_9 => '0',
LMB_Data_Addr_0(0 to 31) => NLW_U0_LMB_Data_Addr_0_UNCONNECTED(0 to 31),
LMB_Data_Addr_1(0 to 31) => NLW_U0_LMB_Data_Addr_1_UNCONNECTED(0 to 31),
LMB_Data_Addr_10(0 to 31) => NLW_U0_LMB_Data_Addr_10_UNCONNECTED(0 to 31),
LMB_Data_Addr_11(0 to 31) => NLW_U0_LMB_Data_Addr_11_UNCONNECTED(0 to 31),
LMB_Data_Addr_12(0 to 31) => NLW_U0_LMB_Data_Addr_12_UNCONNECTED(0 to 31),
LMB_Data_Addr_13(0 to 31) => NLW_U0_LMB_Data_Addr_13_UNCONNECTED(0 to 31),
LMB_Data_Addr_14(0 to 31) => NLW_U0_LMB_Data_Addr_14_UNCONNECTED(0 to 31),
LMB_Data_Addr_15(0 to 31) => NLW_U0_LMB_Data_Addr_15_UNCONNECTED(0 to 31),
LMB_Data_Addr_16(0 to 31) => NLW_U0_LMB_Data_Addr_16_UNCONNECTED(0 to 31),
LMB_Data_Addr_17(0 to 31) => NLW_U0_LMB_Data_Addr_17_UNCONNECTED(0 to 31),
LMB_Data_Addr_18(0 to 31) => NLW_U0_LMB_Data_Addr_18_UNCONNECTED(0 to 31),
LMB_Data_Addr_19(0 to 31) => NLW_U0_LMB_Data_Addr_19_UNCONNECTED(0 to 31),
LMB_Data_Addr_2(0 to 31) => NLW_U0_LMB_Data_Addr_2_UNCONNECTED(0 to 31),
LMB_Data_Addr_20(0 to 31) => NLW_U0_LMB_Data_Addr_20_UNCONNECTED(0 to 31),
LMB_Data_Addr_21(0 to 31) => NLW_U0_LMB_Data_Addr_21_UNCONNECTED(0 to 31),
LMB_Data_Addr_22(0 to 31) => NLW_U0_LMB_Data_Addr_22_UNCONNECTED(0 to 31),
LMB_Data_Addr_23(0 to 31) => NLW_U0_LMB_Data_Addr_23_UNCONNECTED(0 to 31),
LMB_Data_Addr_24(0 to 31) => NLW_U0_LMB_Data_Addr_24_UNCONNECTED(0 to 31),
LMB_Data_Addr_25(0 to 31) => NLW_U0_LMB_Data_Addr_25_UNCONNECTED(0 to 31),
LMB_Data_Addr_26(0 to 31) => NLW_U0_LMB_Data_Addr_26_UNCONNECTED(0 to 31),
LMB_Data_Addr_27(0 to 31) => NLW_U0_LMB_Data_Addr_27_UNCONNECTED(0 to 31),
LMB_Data_Addr_28(0 to 31) => NLW_U0_LMB_Data_Addr_28_UNCONNECTED(0 to 31),
LMB_Data_Addr_29(0 to 31) => NLW_U0_LMB_Data_Addr_29_UNCONNECTED(0 to 31),
LMB_Data_Addr_3(0 to 31) => NLW_U0_LMB_Data_Addr_3_UNCONNECTED(0 to 31),
LMB_Data_Addr_30(0 to 31) => NLW_U0_LMB_Data_Addr_30_UNCONNECTED(0 to 31),
LMB_Data_Addr_31(0 to 31) => NLW_U0_LMB_Data_Addr_31_UNCONNECTED(0 to 31),
LMB_Data_Addr_4(0 to 31) => NLW_U0_LMB_Data_Addr_4_UNCONNECTED(0 to 31),
LMB_Data_Addr_5(0 to 31) => NLW_U0_LMB_Data_Addr_5_UNCONNECTED(0 to 31),
LMB_Data_Addr_6(0 to 31) => NLW_U0_LMB_Data_Addr_6_UNCONNECTED(0 to 31),
LMB_Data_Addr_7(0 to 31) => NLW_U0_LMB_Data_Addr_7_UNCONNECTED(0 to 31),
LMB_Data_Addr_8(0 to 31) => NLW_U0_LMB_Data_Addr_8_UNCONNECTED(0 to 31),
LMB_Data_Addr_9(0 to 31) => NLW_U0_LMB_Data_Addr_9_UNCONNECTED(0 to 31),
LMB_Data_Read_0(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_1(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_10(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_11(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_12(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_13(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_14(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_15(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_16(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_17(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_18(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_19(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_2(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_20(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_21(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_22(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_23(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_24(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_25(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_26(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_27(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_28(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_29(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_3(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_30(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_31(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_4(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_5(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_6(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_7(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_8(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Read_9(0 to 31) => B"00000000000000000000000000000000",
LMB_Data_Write_0(0 to 31) => NLW_U0_LMB_Data_Write_0_UNCONNECTED(0 to 31),
LMB_Data_Write_1(0 to 31) => NLW_U0_LMB_Data_Write_1_UNCONNECTED(0 to 31),
LMB_Data_Write_10(0 to 31) => NLW_U0_LMB_Data_Write_10_UNCONNECTED(0 to 31),
LMB_Data_Write_11(0 to 31) => NLW_U0_LMB_Data_Write_11_UNCONNECTED(0 to 31),
LMB_Data_Write_12(0 to 31) => NLW_U0_LMB_Data_Write_12_UNCONNECTED(0 to 31),
LMB_Data_Write_13(0 to 31) => NLW_U0_LMB_Data_Write_13_UNCONNECTED(0 to 31),
LMB_Data_Write_14(0 to 31) => NLW_U0_LMB_Data_Write_14_UNCONNECTED(0 to 31),
LMB_Data_Write_15(0 to 31) => NLW_U0_LMB_Data_Write_15_UNCONNECTED(0 to 31),
LMB_Data_Write_16(0 to 31) => NLW_U0_LMB_Data_Write_16_UNCONNECTED(0 to 31),
LMB_Data_Write_17(0 to 31) => NLW_U0_LMB_Data_Write_17_UNCONNECTED(0 to 31),
LMB_Data_Write_18(0 to 31) => NLW_U0_LMB_Data_Write_18_UNCONNECTED(0 to 31),
LMB_Data_Write_19(0 to 31) => NLW_U0_LMB_Data_Write_19_UNCONNECTED(0 to 31),
LMB_Data_Write_2(0 to 31) => NLW_U0_LMB_Data_Write_2_UNCONNECTED(0 to 31),
LMB_Data_Write_20(0 to 31) => NLW_U0_LMB_Data_Write_20_UNCONNECTED(0 to 31),
LMB_Data_Write_21(0 to 31) => NLW_U0_LMB_Data_Write_21_UNCONNECTED(0 to 31),
LMB_Data_Write_22(0 to 31) => NLW_U0_LMB_Data_Write_22_UNCONNECTED(0 to 31),
LMB_Data_Write_23(0 to 31) => NLW_U0_LMB_Data_Write_23_UNCONNECTED(0 to 31),
LMB_Data_Write_24(0 to 31) => NLW_U0_LMB_Data_Write_24_UNCONNECTED(0 to 31),
LMB_Data_Write_25(0 to 31) => NLW_U0_LMB_Data_Write_25_UNCONNECTED(0 to 31),
LMB_Data_Write_26(0 to 31) => NLW_U0_LMB_Data_Write_26_UNCONNECTED(0 to 31),
LMB_Data_Write_27(0 to 31) => NLW_U0_LMB_Data_Write_27_UNCONNECTED(0 to 31),
LMB_Data_Write_28(0 to 31) => NLW_U0_LMB_Data_Write_28_UNCONNECTED(0 to 31),
LMB_Data_Write_29(0 to 31) => NLW_U0_LMB_Data_Write_29_UNCONNECTED(0 to 31),
LMB_Data_Write_3(0 to 31) => NLW_U0_LMB_Data_Write_3_UNCONNECTED(0 to 31),
LMB_Data_Write_30(0 to 31) => NLW_U0_LMB_Data_Write_30_UNCONNECTED(0 to 31),
LMB_Data_Write_31(0 to 31) => NLW_U0_LMB_Data_Write_31_UNCONNECTED(0 to 31),
LMB_Data_Write_4(0 to 31) => NLW_U0_LMB_Data_Write_4_UNCONNECTED(0 to 31),
LMB_Data_Write_5(0 to 31) => NLW_U0_LMB_Data_Write_5_UNCONNECTED(0 to 31),
LMB_Data_Write_6(0 to 31) => NLW_U0_LMB_Data_Write_6_UNCONNECTED(0 to 31),
LMB_Data_Write_7(0 to 31) => NLW_U0_LMB_Data_Write_7_UNCONNECTED(0 to 31),
LMB_Data_Write_8(0 to 31) => NLW_U0_LMB_Data_Write_8_UNCONNECTED(0 to 31),
LMB_Data_Write_9(0 to 31) => NLW_U0_LMB_Data_Write_9_UNCONNECTED(0 to 31),
LMB_Read_Strobe_0 => NLW_U0_LMB_Read_Strobe_0_UNCONNECTED,
LMB_Read_Strobe_1 => NLW_U0_LMB_Read_Strobe_1_UNCONNECTED,
LMB_Read_Strobe_10 => NLW_U0_LMB_Read_Strobe_10_UNCONNECTED,
LMB_Read_Strobe_11 => NLW_U0_LMB_Read_Strobe_11_UNCONNECTED,
LMB_Read_Strobe_12 => NLW_U0_LMB_Read_Strobe_12_UNCONNECTED,
LMB_Read_Strobe_13 => NLW_U0_LMB_Read_Strobe_13_UNCONNECTED,
LMB_Read_Strobe_14 => NLW_U0_LMB_Read_Strobe_14_UNCONNECTED,
LMB_Read_Strobe_15 => NLW_U0_LMB_Read_Strobe_15_UNCONNECTED,
LMB_Read_Strobe_16 => NLW_U0_LMB_Read_Strobe_16_UNCONNECTED,
LMB_Read_Strobe_17 => NLW_U0_LMB_Read_Strobe_17_UNCONNECTED,
LMB_Read_Strobe_18 => NLW_U0_LMB_Read_Strobe_18_UNCONNECTED,
LMB_Read_Strobe_19 => NLW_U0_LMB_Read_Strobe_19_UNCONNECTED,
LMB_Read_Strobe_2 => NLW_U0_LMB_Read_Strobe_2_UNCONNECTED,
LMB_Read_Strobe_20 => NLW_U0_LMB_Read_Strobe_20_UNCONNECTED,
LMB_Read_Strobe_21 => NLW_U0_LMB_Read_Strobe_21_UNCONNECTED,
LMB_Read_Strobe_22 => NLW_U0_LMB_Read_Strobe_22_UNCONNECTED,
LMB_Read_Strobe_23 => NLW_U0_LMB_Read_Strobe_23_UNCONNECTED,
LMB_Read_Strobe_24 => NLW_U0_LMB_Read_Strobe_24_UNCONNECTED,
LMB_Read_Strobe_25 => NLW_U0_LMB_Read_Strobe_25_UNCONNECTED,
LMB_Read_Strobe_26 => NLW_U0_LMB_Read_Strobe_26_UNCONNECTED,
LMB_Read_Strobe_27 => NLW_U0_LMB_Read_Strobe_27_UNCONNECTED,
LMB_Read_Strobe_28 => NLW_U0_LMB_Read_Strobe_28_UNCONNECTED,
LMB_Read_Strobe_29 => NLW_U0_LMB_Read_Strobe_29_UNCONNECTED,
LMB_Read_Strobe_3 => NLW_U0_LMB_Read_Strobe_3_UNCONNECTED,
LMB_Read_Strobe_30 => NLW_U0_LMB_Read_Strobe_30_UNCONNECTED,
LMB_Read_Strobe_31 => NLW_U0_LMB_Read_Strobe_31_UNCONNECTED,
LMB_Read_Strobe_4 => NLW_U0_LMB_Read_Strobe_4_UNCONNECTED,
LMB_Read_Strobe_5 => NLW_U0_LMB_Read_Strobe_5_UNCONNECTED,
LMB_Read_Strobe_6 => NLW_U0_LMB_Read_Strobe_6_UNCONNECTED,
LMB_Read_Strobe_7 => NLW_U0_LMB_Read_Strobe_7_UNCONNECTED,
LMB_Read_Strobe_8 => NLW_U0_LMB_Read_Strobe_8_UNCONNECTED,
LMB_Read_Strobe_9 => NLW_U0_LMB_Read_Strobe_9_UNCONNECTED,
LMB_Ready_0 => '0',
LMB_Ready_1 => '0',
LMB_Ready_10 => '0',
LMB_Ready_11 => '0',
LMB_Ready_12 => '0',
LMB_Ready_13 => '0',
LMB_Ready_14 => '0',
LMB_Ready_15 => '0',
LMB_Ready_16 => '0',
LMB_Ready_17 => '0',
LMB_Ready_18 => '0',
LMB_Ready_19 => '0',
LMB_Ready_2 => '0',
LMB_Ready_20 => '0',
LMB_Ready_21 => '0',
LMB_Ready_22 => '0',
LMB_Ready_23 => '0',
LMB_Ready_24 => '0',
LMB_Ready_25 => '0',
LMB_Ready_26 => '0',
LMB_Ready_27 => '0',
LMB_Ready_28 => '0',
LMB_Ready_29 => '0',
LMB_Ready_3 => '0',
LMB_Ready_30 => '0',
LMB_Ready_31 => '0',
LMB_Ready_4 => '0',
LMB_Ready_5 => '0',
LMB_Ready_6 => '0',
LMB_Ready_7 => '0',
LMB_Ready_8 => '0',
LMB_Ready_9 => '0',
LMB_UE_0 => '0',
LMB_UE_1 => '0',
LMB_UE_10 => '0',
LMB_UE_11 => '0',
LMB_UE_12 => '0',
LMB_UE_13 => '0',
LMB_UE_14 => '0',
LMB_UE_15 => '0',
LMB_UE_16 => '0',
LMB_UE_17 => '0',
LMB_UE_18 => '0',
LMB_UE_19 => '0',
LMB_UE_2 => '0',
LMB_UE_20 => '0',
LMB_UE_21 => '0',
LMB_UE_22 => '0',
LMB_UE_23 => '0',
LMB_UE_24 => '0',
LMB_UE_25 => '0',
LMB_UE_26 => '0',
LMB_UE_27 => '0',
LMB_UE_28 => '0',
LMB_UE_29 => '0',
LMB_UE_3 => '0',
LMB_UE_30 => '0',
LMB_UE_31 => '0',
LMB_UE_4 => '0',
LMB_UE_5 => '0',
LMB_UE_6 => '0',
LMB_UE_7 => '0',
LMB_UE_8 => '0',
LMB_UE_9 => '0',
LMB_Wait_0 => '0',
LMB_Wait_1 => '0',
LMB_Wait_10 => '0',
LMB_Wait_11 => '0',
LMB_Wait_12 => '0',
LMB_Wait_13 => '0',
LMB_Wait_14 => '0',
LMB_Wait_15 => '0',
LMB_Wait_16 => '0',
LMB_Wait_17 => '0',
LMB_Wait_18 => '0',
LMB_Wait_19 => '0',
LMB_Wait_2 => '0',
LMB_Wait_20 => '0',
LMB_Wait_21 => '0',
LMB_Wait_22 => '0',
LMB_Wait_23 => '0',
LMB_Wait_24 => '0',
LMB_Wait_25 => '0',
LMB_Wait_26 => '0',
LMB_Wait_27 => '0',
LMB_Wait_28 => '0',
LMB_Wait_29 => '0',
LMB_Wait_3 => '0',
LMB_Wait_30 => '0',
LMB_Wait_31 => '0',
LMB_Wait_4 => '0',
LMB_Wait_5 => '0',
LMB_Wait_6 => '0',
LMB_Wait_7 => '0',
LMB_Wait_8 => '0',
LMB_Wait_9 => '0',
LMB_Write_Strobe_0 => NLW_U0_LMB_Write_Strobe_0_UNCONNECTED,
LMB_Write_Strobe_1 => NLW_U0_LMB_Write_Strobe_1_UNCONNECTED,
LMB_Write_Strobe_10 => NLW_U0_LMB_Write_Strobe_10_UNCONNECTED,
LMB_Write_Strobe_11 => NLW_U0_LMB_Write_Strobe_11_UNCONNECTED,
LMB_Write_Strobe_12 => NLW_U0_LMB_Write_Strobe_12_UNCONNECTED,
LMB_Write_Strobe_13 => NLW_U0_LMB_Write_Strobe_13_UNCONNECTED,
LMB_Write_Strobe_14 => NLW_U0_LMB_Write_Strobe_14_UNCONNECTED,
LMB_Write_Strobe_15 => NLW_U0_LMB_Write_Strobe_15_UNCONNECTED,
LMB_Write_Strobe_16 => NLW_U0_LMB_Write_Strobe_16_UNCONNECTED,
LMB_Write_Strobe_17 => NLW_U0_LMB_Write_Strobe_17_UNCONNECTED,
LMB_Write_Strobe_18 => NLW_U0_LMB_Write_Strobe_18_UNCONNECTED,
LMB_Write_Strobe_19 => NLW_U0_LMB_Write_Strobe_19_UNCONNECTED,
LMB_Write_Strobe_2 => NLW_U0_LMB_Write_Strobe_2_UNCONNECTED,
LMB_Write_Strobe_20 => NLW_U0_LMB_Write_Strobe_20_UNCONNECTED,
LMB_Write_Strobe_21 => NLW_U0_LMB_Write_Strobe_21_UNCONNECTED,
LMB_Write_Strobe_22 => NLW_U0_LMB_Write_Strobe_22_UNCONNECTED,
LMB_Write_Strobe_23 => NLW_U0_LMB_Write_Strobe_23_UNCONNECTED,
LMB_Write_Strobe_24 => NLW_U0_LMB_Write_Strobe_24_UNCONNECTED,
LMB_Write_Strobe_25 => NLW_U0_LMB_Write_Strobe_25_UNCONNECTED,
LMB_Write_Strobe_26 => NLW_U0_LMB_Write_Strobe_26_UNCONNECTED,
LMB_Write_Strobe_27 => NLW_U0_LMB_Write_Strobe_27_UNCONNECTED,
LMB_Write_Strobe_28 => NLW_U0_LMB_Write_Strobe_28_UNCONNECTED,
LMB_Write_Strobe_29 => NLW_U0_LMB_Write_Strobe_29_UNCONNECTED,
LMB_Write_Strobe_3 => NLW_U0_LMB_Write_Strobe_3_UNCONNECTED,
LMB_Write_Strobe_30 => NLW_U0_LMB_Write_Strobe_30_UNCONNECTED,
LMB_Write_Strobe_31 => NLW_U0_LMB_Write_Strobe_31_UNCONNECTED,
LMB_Write_Strobe_4 => NLW_U0_LMB_Write_Strobe_4_UNCONNECTED,
LMB_Write_Strobe_5 => NLW_U0_LMB_Write_Strobe_5_UNCONNECTED,
LMB_Write_Strobe_6 => NLW_U0_LMB_Write_Strobe_6_UNCONNECTED,
LMB_Write_Strobe_7 => NLW_U0_LMB_Write_Strobe_7_UNCONNECTED,
LMB_Write_Strobe_8 => NLW_U0_LMB_Write_Strobe_8_UNCONNECTED,
LMB_Write_Strobe_9 => NLW_U0_LMB_Write_Strobe_9_UNCONNECTED,
M_AXIS_ACLK => '0',
M_AXIS_ARESETN => '0',
M_AXIS_TDATA(31 downto 0) => NLW_U0_M_AXIS_TDATA_UNCONNECTED(31 downto 0),
M_AXIS_TID(6 downto 0) => NLW_U0_M_AXIS_TID_UNCONNECTED(6 downto 0),
M_AXIS_TREADY => '1',
M_AXIS_TVALID => NLW_U0_M_AXIS_TVALID_UNCONNECTED,
M_AXI_ACLK => '0',
M_AXI_ARADDR(31 downto 0) => NLW_U0_M_AXI_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_ARBURST(1 downto 0) => NLW_U0_M_AXI_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_ARCACHE(3 downto 0) => NLW_U0_M_AXI_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_ARESETN => '0',
M_AXI_ARID(0) => NLW_U0_M_AXI_ARID_UNCONNECTED(0),
M_AXI_ARLEN(7 downto 0) => NLW_U0_M_AXI_ARLEN_UNCONNECTED(7 downto 0),
M_AXI_ARLOCK => NLW_U0_M_AXI_ARLOCK_UNCONNECTED,
M_AXI_ARPROT(2 downto 0) => NLW_U0_M_AXI_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_ARQOS(3 downto 0) => NLW_U0_M_AXI_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_ARREADY => '0',
M_AXI_ARSIZE(2 downto 0) => NLW_U0_M_AXI_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_ARVALID => NLW_U0_M_AXI_ARVALID_UNCONNECTED,
M_AXI_AWADDR(31 downto 0) => NLW_U0_M_AXI_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_AWBURST(1 downto 0) => NLW_U0_M_AXI_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_AWCACHE(3 downto 0) => NLW_U0_M_AXI_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_AWID(0) => NLW_U0_M_AXI_AWID_UNCONNECTED(0),
M_AXI_AWLEN(7 downto 0) => NLW_U0_M_AXI_AWLEN_UNCONNECTED(7 downto 0),
M_AXI_AWLOCK => NLW_U0_M_AXI_AWLOCK_UNCONNECTED,
M_AXI_AWPROT(2 downto 0) => NLW_U0_M_AXI_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_AWQOS(3 downto 0) => NLW_U0_M_AXI_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_AWREADY => '0',
M_AXI_AWSIZE(2 downto 0) => NLW_U0_M_AXI_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_AWVALID => NLW_U0_M_AXI_AWVALID_UNCONNECTED,
M_AXI_BID(0) => '0',
M_AXI_BREADY => NLW_U0_M_AXI_BREADY_UNCONNECTED,
M_AXI_BRESP(1 downto 0) => B"00",
M_AXI_BVALID => '0',
M_AXI_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_RID(0) => '0',
M_AXI_RLAST => '0',
M_AXI_RREADY => NLW_U0_M_AXI_RREADY_UNCONNECTED,
M_AXI_RRESP(1 downto 0) => B"00",
M_AXI_RVALID => '0',
M_AXI_WDATA(31 downto 0) => NLW_U0_M_AXI_WDATA_UNCONNECTED(31 downto 0),
M_AXI_WLAST => NLW_U0_M_AXI_WLAST_UNCONNECTED,
M_AXI_WREADY => '0',
M_AXI_WSTRB(3 downto 0) => NLW_U0_M_AXI_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_WVALID => NLW_U0_M_AXI_WVALID_UNCONNECTED,
S_AXI_ACLK => '0',
S_AXI_ARADDR(3 downto 0) => B"0000",
S_AXI_ARESETN => '0',
S_AXI_ARREADY => NLW_U0_S_AXI_ARREADY_UNCONNECTED,
S_AXI_ARVALID => '0',
S_AXI_AWADDR(3 downto 0) => B"0000",
S_AXI_AWREADY => NLW_U0_S_AXI_AWREADY_UNCONNECTED,
S_AXI_AWVALID => '0',
S_AXI_BREADY => '0',
S_AXI_BRESP(1 downto 0) => NLW_U0_S_AXI_BRESP_UNCONNECTED(1 downto 0),
S_AXI_BVALID => NLW_U0_S_AXI_BVALID_UNCONNECTED,
S_AXI_RDATA(31 downto 0) => NLW_U0_S_AXI_RDATA_UNCONNECTED(31 downto 0),
S_AXI_RREADY => '0',
S_AXI_RRESP(1 downto 0) => NLW_U0_S_AXI_RRESP_UNCONNECTED(1 downto 0),
S_AXI_RVALID => NLW_U0_S_AXI_RVALID_UNCONNECTED,
S_AXI_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_WREADY => NLW_U0_S_AXI_WREADY_UNCONNECTED,
S_AXI_WSTRB(3 downto 0) => B"0000",
S_AXI_WVALID => '0',
Scan_Reset => '0',
Scan_Reset_Sel => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_U0_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_U0_TRACE_CTL_UNCONNECTED,
TRACE_DATA(31 downto 0) => NLW_U0_TRACE_DATA_UNCONNECTED(31 downto 0),
Trig_Ack_In_0 => NLW_U0_Trig_Ack_In_0_UNCONNECTED,
Trig_Ack_In_1 => NLW_U0_Trig_Ack_In_1_UNCONNECTED,
Trig_Ack_In_2 => NLW_U0_Trig_Ack_In_2_UNCONNECTED,
Trig_Ack_In_3 => NLW_U0_Trig_Ack_In_3_UNCONNECTED,
Trig_Ack_Out_0 => '0',
Trig_Ack_Out_1 => '0',
Trig_Ack_Out_2 => '0',
Trig_Ack_Out_3 => '0',
Trig_In_0 => '0',
Trig_In_1 => '0',
Trig_In_2 => '0',
Trig_In_3 => '0',
Trig_Out_0 => NLW_U0_Trig_Out_0_UNCONNECTED,
Trig_Out_1 => NLW_U0_Trig_Out_1_UNCONNECTED,
Trig_Out_2 => NLW_U0_Trig_Out_2_UNCONNECTED,
Trig_Out_3 => NLW_U0_Trig_Out_3_UNCONNECTED,
bscan_ext_capture => '0',
bscan_ext_drck => '0',
bscan_ext_reset => '0',
bscan_ext_sel => '0',
bscan_ext_shift => '0',
bscan_ext_tdi => '0',
bscan_ext_tdo => NLW_U0_bscan_ext_tdo_UNCONNECTED,
bscan_ext_update => '0'
);
end STRUCTURE;
|
apache-2.0
|
dd9be17c5946199d4f8ae43eba9d2f5e
| 0.590514 | 2.627434 | false | false | false | false |
eaglewyng/FPGA2048
|
seven_segment_display.vhd
| 1 | 3,657 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:07:57 01/29/2014
-- Design Name:
-- Module Name: seven_segment_display - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity seven_segment_display is
generic( COUNTER_BITS : natural := 15);
Port ( clk : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (15 downto 0);
dp_in : in STD_LOGIC_VECTOR (3 downto 0);
blank : in STD_LOGIC_VECTOR (3 downto 0);
seg : out STD_LOGIC_VECTOR (6 downto 0);
dp : out STD_LOGIC;
an : out STD_LOGIC_VECTOR (3 downto 0));
end seven_segment_display;
architecture Behavioral of seven_segment_display is
--make aliases for the in digits, because I know I will be confused if I don't
alias digit0in : std_logic_vector(3 downto 0) is data_in(3 downto 0);
alias digit1in : std_logic_vector(3 downto 0) is data_in(7 downto 4);
alias digit2in : std_logic_vector(3 downto 0) is data_in(11 downto 8);
alias digit3in : std_logic_vector(3 downto 0) is data_in(15 downto 12);
--make signals for the binary counter
signal r_next: unsigned(COUNTER_BITS-1 downto 0);
signal r_reg: unsigned(COUNTER_BITS-1 downto 0) := (others =>'0');
--make signal for the value to be displayed
signal dispVal : std_logic_vector(3 downto 0);
signal dp_inverted : std_logic_vector(3 downto 0);
signal top2 : std_logic_vector(1 downto 0);
begin
--binary conter--
process(clk)
begin
if(clk' event and clk = '1') then
r_reg <= r_next;
end if;
end process;
--nxt state
r_next <= r_reg + 1;
top2 <= std_logic_vector(r_reg(COUNTER_BITS-1 downto COUNTER_BITS-2));
dp_inverted <= not dp_in;
with top2 select
dp <= dp_inverted(0) when "00",
dp_inverted(1) when "01",
dp_inverted(2) when "10",
dp_inverted(3) when others;
--anode select logic
an(0) <= '1' when (blank(0) = '1') else
'0' when (r_reg(COUNTER_BITS-1 downto COUNTER_BITS-2) = "00") else
'1';
an(1) <= '1' when (blank(1) = '1') else
'0' when (r_reg(COUNTER_BITS-1 downto COUNTER_BITS-2) = "01") else
'1';
an(2) <= '1' when (blank(2) = '1') else
'0' when (r_reg(COUNTER_BITS-1 downto COUNTER_BITS-2) = "10") else
'1';
an(3) <= '1' when (blank(3) = '1') else
'0' when (r_reg(COUNTER_BITS-1 downto COUNTER_BITS-2) = "11") else
'1';
--data_in select logic
with top2 select
dispVal <= digit0in when "00",
digit1in when "01",
digit2in when "10",
digit3in when others;
--decode the selected logic into the digits
with dispVal select
seg <= "1000000" when "0000",
"1111001" when "0001",
"0100100" when "0010",
"0110000" when "0011",
"0011001" when "0100",
"0010010" when "0101",
"0000010" when "0110",
"1111000" when "0111",
"0000000" when "1000",
"0010000" when "1001",
"0001000" when "1010",
"0000011" when "1011",
"1000110" when "1100",
"0100001" when "1101",
"0000110" when "1110",
"0001110" when others;
end Behavioral;
|
mit
|
586748a57218ff5053732c28bbc75262
| 0.608422 | 3.163495 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 2/CU.vhd
| 1 | 1,771 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity CU is
Port ( OP : in STD_LOGIC_VECTOR (1 downto 0);
OP3 : in STD_LOGIC_VECTOR (5 downto 0);
ALUOP : out STD_LOGIC_VECTOR (5 downto 0));
end CU;
architecture Behavioral of CU is
begin
process(OP,OP3)
begin
case OP is
when "10"=>
case OP3 is --Instrucciones aritmetico logicas
when "000001"=>ALUOP<="000000"; --0. AND
when "000101"=>ALUOP<="000001"; --1. ANDN
when "000010"=>ALUOP<="000010"; --2. OR
when "000110"=>ALUOP<="000011"; --3. ORN
when "000011"=>ALUOP<="000100"; --4. XOR
when "000111"=>ALUOP<="000101"; --5. XNOR
when "000000"=>ALUOP<="000110"; --6. ADD
when "000100"=>ALUOP<="000111"; --7. SUB
when "100101"=>ALUOP<="001000"; --8. SLL
when "100110"=>ALUOP<="001001"; --9. SRL
when "100111"=>ALUOP<="001010"; --10. SRA
when "010001"=>ALUOP<="001011"; --11. ANDcc
when "010101"=>ALUOP<="001100"; --12. ANDNcc
when "010010"=>ALUOP<="001101"; --13. ORcc
when "010110"=>ALUOP<="001110"; --14. ORNcc
when "010011"=>ALUOP<="001111"; --15. XORcc
when "010111"=>ALUOP<="010000"; --16. XNORcc
when "010000"=>ALUOP<="010001"; --17. ADDcc
when "001000"=>ALUOP<="010010"; --18. ADDX
when "011000"=>ALUOP<="010011"; --19. ADDXcc
when "010100"=>ALUOP<="010100"; --20. SUBcc
when "001100"=>ALUOP<="010101"; --21. SUBX
when "011100"=>ALUOP<="010110"; --22. SUBXcc
when "111100"=>ALUOP<="010111"; --23. SAVE
when "111101"=>ALUOP<="011000"; --24. RESTORE
when others=> ALUOP<="111111"; --Instrucciones artimetico logicas no definidas
end case;
when others=>ALUOP<="111111"; --Otras instrucciones aun no definidas
end case;
end process;
end Behavioral;
|
mit
|
12c35eee7619915f0be11b2ffddac866
| 0.599097 | 3.214156 | false | false | false | false |
KPU-RISC/KPU
|
VHDL/InstructionDecoder.vhd
| 1 | 69,353 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/23/2015 03:41:27 PM
-- Design Name:
-- Module Name: InstructionDecoder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity InstructionDecoder is
port
(
TimingSignals : in BIT_VECTOR(7 downto 0); -- The 8 different timing states
Instruction : in BIT_VECTOR(7 downto 0); -- The instruction to execute
Flags : in BIT_VECTOR(7 downto 0); -- Content of the FLAGS register - needed for conditional jumps
-- ==============================================================
-- The various control lines of the CPU which go low/high
-- depending on the timing state and the instruction to execute:
-- ==============================================================
Load_PC : out BIT;
Select_PC : out BIT;
Load_SRAM: out BIT;
Select_SRAM: out BIT;
Return_SRAM: out BIT;
Load_INC: out BIT;
Select_INC: out BIT;
Load_INSTR: out BIT;
Select_INSTR_To_DataBus: out BIT;
Select_INSTR_To_ALU: out BIT;
Load_A_From_DataBus: out BIT;
Select_A_To_ALU: out BIT;
Load_B_From_DataBus: out BIT;
Select_B_To_ALU: out BIT;
Load_C_From_DataBus: out BIT;
Load_InternalA_From_DataBus: out BIT;
Select_InternalA_To_DataBus: out BIT;
Load_Flags: out BIT;
Select_A_To_DataBus: out BIT;
Select_B_To_DataBus: out BIT;
Select_C_To_DataBus: out BIT;
Load_D_From_DataBus: out BIT;
Select_D_To_DataBus: out BIT;
Load_E_From_DataBus: out BIT;
Select_E_To_DataBus: out BIT;
Load_F_From_DataBus: out BIT;
Select_F_To_DataBus: out BIT;
Load_G_From_DataBus: out BIT;
Select_G_To_DataBus: out BIT;
Load_H_From_DataBus: out BIT;
Select_H_To_DataBus: out BIT;
load_M_From_AddressBus: out BIT;
select_M_To_AddressBus: out BIT;
load_XL_From_DataBus: out BIT;
load_XH_From_DataBus: out BIT;
load_X_From_AddressBus: out BIT;
select_XL_To_DataBus: out BIT;
select_XH_To_DataBus: out BIT;
select_X_To_AddressBus: out BIT;
Load_J_From_AddressBus: out BIT;
Select_J_To_AddressBus: out BIT;
Load_SP_From_AddressBus: out BIT;
Select_SP_To_AddressBus: out BIT;
Load_BP_From_AddressBus: out BIT;
Select_BP_To_AddressBus: out BIT;
Load_Y_From_AddressBus: out BIT;
Select_Y_To_AddressBus: out BIT;
Load_Z_From_AddressBus: out BIT;
Select_Z_To_AddressBus: out BIT;
Load_Adder16Bit_InputA: out BIT;
Select_Adder16Bit_InputA: out BIT;
Load_Adder16Bit_InputB: out BIT;
Select_Adder16Bit_InputB: out BIT;
Load_Adder16Bit_OutputC: out BIT;
Select_Adder16Bit_OutputC: out BIT;
load_FlagsSaved_From_FlagsRegister: out BIT;
load_FlagsSaved_To_FlagsRegister: out BIT;
Load_FlagsFromDataBus: out BIT;
Select_FlagsToFlagsBus: out BIT;
Load_FlagsFromFlagsBus: out BIT;
Select_FlagsToDataBus: out BIT;
Select_Flags: out BIT;
Select_PortA_To_DataBus: out BIT;
Select_PortB_To_DataBus: out BIT;
Load_PortC_From_DataBus: out BIT;
Load_PortD_From_DataBus: out BIT;
StopCPU: out BIT
);
end InstructionDecoder;
architecture Behavioral of InstructionDecoder is
component Decoder3to8 is
Port
(
F : in BIT_VECTOR(2 downto 0); -- 3-Bit Function Code (Input)
X : out BIT_VECTOR(7 downto 0); -- 8-Bit State (Output)
Started: in BIT -- Is the CPU already running?
);
end component Decoder3to8;
signal NegatedInstruction : BIT_VECTOR(7 downto 0);
signal NegatedFlags : BIT_VECTOR(7 downto 0);
signal instruction_SETAB: BIT;
signal instruction_ALU: BIT;
signal instruction_MOV: BIT;
signal instruction_MOV16: BIT;
signal instruction_LOAD: BIT;
signal instruction_STORE: BIT;
signal instruction_JMP: BIT;
signal instruction_HLT: BIT;
signal instruction_JZ: BIT;
signal instruction_JNZ: BIT;
signal instruction_JNS: BIT;
signal instruction_JNC: BIT;
signal instruction_SAVE_FLAGS: BIT;
signal instruction_RESTORE_FLAGS: BIT;
signal instruction_NOP: BIT;
signal instruction_FLAGS_TO_OUTBUFFER: BIT;
signal instruction_INBUFFER_TO_FLAGS: BIT;
signal instruction_ADDER_16BIT: BIT;
signal instruction_STORE_FLAGS: BIT;
signal instruction_LOAD_FLAGS: BIT;
signal instruction_IN: BIT;
signal instruction_OUT: BIT;
-- Internal ALU instructions
signal instruction_MOV_ALU_IN: BIT;
signal instruction_MOV_ALU_OUT: BIT;
signal instruction_MOV_ALU_C_TO_AB: BIT;
signal MOV_DestinationRegister: BIT_VECTOR(7 downto 0);
signal MOV_SourceRegister: BIT_VECTOR(7 downto 0);
signal MOV16_DestinationRegister: BIT_VECTOR(7 downto 0);
signal MOV16_SourceRegister: BIT_VECTOR(7 downto 0);
-- Used by the Fetch/Increment cycle
signal Select_SRAM_FETCH: BIT;
signal Load_PC_FETCH: BIT;
signal Select_PC_FETCH: BIT;
signal Return_SRAM_FETCH: BIT;
-- Used by the SETAB opcode
signal Load_A_From_DataBus_SETAB: BIT;
signal Load_B_From_DataBus_SETAB: BIT;
-- Used by the ALU opcode
signal Load_C_From_DataBus_ALU: BIT;
signal Load_Flags_From_ALU: BIT;
-- Used by the MOV opcode
signal Select_D_To_DataBus_MOV: BIT;
signal Select_E_To_DataBus_MOV: BIT;
signal Select_F_To_DataBus_MOV: BIT;
signal Select_G_To_DataBus_MOV: BIT;
signal Select_H_To_DataBus_MOV: BIT;
signal Select_SP_To_DataBus_MOV: BIT;
signal Select_XL_To_DataBus_MOV: BIT;
signal Select_XH_To_DataBus_MOV: BIT;
signal Load_D_From_DataBus_MOV: BIT;
signal Load_E_From_DataBus_MOV: BIT;
signal Load_F_From_DataBus_MOV: BIT;
signal Load_G_From_DataBus_MOV: BIT;
signal Load_H_From_DataBus_MOV: BIT;
signal Load_SP_From_DataBus_MOV: BIT;
signal Load_XL_From_DataBus_MOV: BIT;
signal Load_XH_From_DataBus_MOV: BIT;
signal Load_J_From_DataBus_MOV: BIT;
-- Used by the MOV16 opcode
signal Select_M_To_AddressBus_MOV16: BIT;
signal Select_X_To_AddressBus_MOV16: BIT;
signal Load_M_From_AddressBus_MOV16: BIT;
signal Load_X_From_AddressBus_MOV16: BIT;
signal Select_J_To_AddressBus_MOV16: BIT;
signal Load_J_From_AddressBus_MOV16: BIT;
signal Select_SP_To_AddressBus_MOV16: BIT;
signal Load_SP_From_AddressBus_MOV16: BIT;
signal Select_PC_To_AddressBus_MOV16: BIT;
signal Load_PC_From_AddressBus_MOV16: BIT;
signal Select_BP_To_AddressBus_MOV16: BIT;
signal Load_BP_From_AddressBus_MOV16: BIT;
signal Select_Y_To_AddressBus_MOV16: BIT;
signal Load_Y_From_AddressBus_MOV16: BIT;
signal Select_Z_To_AddressBus_MOV16: BIT;
signal Load_Z_From_AddressBus_MOV16: BIT;
-- Used by the LOAD opcode
signal Select_SRAM_LOAD: BIT;
signal Return_SRAM_LOAD: BIT;
signal Load_D_From_DataBus_LOAD: BIT;
signal Load_E_From_DataBus_LOAD: BIT;
signal Load_F_From_DataBus_LOAD: BIT;
signal Load_G_From_DataBus_LOAD: BIT;
signal Load_H_From_DataBus_LOAD: BIT;
signal Load_XL_From_DataBus_LOAD: BIT;
signal Load_XH_From_DataBus_LOAD: BIT;
signal Select_M_To_AddressBus_LOAD: BIT;
-- Used by the STORE opcode
signal Load_SRAM_LOAD: BIT;
signal Select_D_To_DataBus_STORE: BIT;
signal Select_E_To_DataBus_STORE: BIT;
signal Select_F_To_DataBus_STORE: BIT;
signal Select_G_To_DataBus_STORE: BIT;
signal Select_H_To_DataBus_STORE: BIT;
signal Select_XL_To_DataBus_STORE: BIT;
signal Select_XH_To_DataBus_STORE: BIT;
signal Select_M_To_AddressBus_STORE: BIT;
signal Load_SRAM_STORE: BIT;
-- Used by the LOAD_FLAGS opcode
signal Load_SRAM_STORE_FLAGS: BIT;
signal Select_M_To_AddressBus_STORE_FLAGS: BIT;
-- Used by the STORE_FLAGS opcode
signal Select_SRAM_LOAD_FLAGS: BIT;
signal Select_M_To_AddressBus_LOAD_FLAGS: BIT;
signal Return_SRAM_LOAD_FLAGS: BIT;
-- Used by the JMP opcode
signal Load_PC_JMP: BIT;
signal Select_J_To_AddressBus_JMP: BIT;
-- Used by the JZ opcode
signal Load_PC_JZ: BIT;
signal Select_J_To_AddressBus_JZ: BIT;
signal Select_Flags_JZ: BIT;
-- Used by the JNS opcode
signal Load_PC_JNS: BIT;
signal Select_J_To_AddressBus_JNS: BIT;
signal Select_Flags_JNS: BIT;
-- Used by the JNC opcode
signal Load_PC_JNC: BIT;
signal Select_J_To_AddressBus_JNC: BIT;
signal Select_Flags_JNC: BIT;
-- Used by the JNZ opcode
signal Load_PC_JNZ: BIT;
signal Select_J_To_AddressBus_JNZ: BIT;
signal Select_Flags_JNZ: BIT;
-- Used by the SAVE_FLAGS opcode
signal Select_Flags_SAVE_FLAGS: BIT;
-- Used by the RESTORE_FLAGS opcode
signal Load_Flags_SAVE_FLAGS: BIT;
-- Used by the INBUFFER_TO_FLAGS opcode
signal Load_Flags_INBUFFER_TO_FLAGS: BIT;
-- Used by the FLAGS_TO_DATABUS opcode
signal Select_Flags_FLAGS_TO_OUTBUFFER: BIT;
-- Used by the MOV_ALU_IN opcode
signal Select_D_To_DataBus_MOV_ALU_IN: BIT;
signal Select_E_To_DataBus_MOV_ALU_IN: BIT;
signal Select_F_To_DataBus_MOV_ALU_IN: BIT;
signal Select_G_To_DataBus_MOV_ALU_IN: BIT;
signal Select_H_To_DataBus_MOV_ALU_IN: BIT;
signal Select_XL_To_DataBus_MOV_ALU_IN: BIT;
signal Select_XH_To_DataBus_MOV_ALU_IN: BIT;
signal Select_SP_To_DataBus_MOV_ALU_IN: BIT;
signal Load_A_From_DataBus_MOV_ALU_IN: BIT;
signal Load_B_From_DataBus_MOV_ALU_IN: BIT;
signal MOV_ALU_IN_SourceRegister: BIT_VECTOR(7 downto 0);
-- Used by the MOV_ALU_OUT opcode
signal Load_D_From_DataBus_MOV_ALU_OUT: BIT;
signal Load_E_From_DataBus_MOV_ALU_OUT: BIT;
signal Load_F_From_DataBus_MOV_ALU_OUT: BIT;
signal Load_G_From_DataBus_MOV_ALU_OUT: BIT;
signal Load_H_From_DataBus_MOV_ALU_OUT: BIT;
signal Load_XL_From_DataBus_MOV_ALU_OUT: BIT;
signal Load_XH_From_DataBus_MOV_ALU_OUT: BIT;
signal Load_SP_From_DataBus_MOV_ALU_OUT: BIT;
signal Load_J_From_DataBus_MOV_ALU_OUT: BIT;
signal Select_C_To_DataBus_MOV_ALU_OUT: BIT;
signal MOV_ALU_OUT_DestinationRegister: BIT_VECTOR(7 downto 0);
-- Used by the MOV_ALU_C_TO_AB opcode
signal Load_A_From_DataBus_MOV_ALU_C_TO_AB: BIT;
signal Load_B_From_DataBus_MOV_ALU_C_TO_AB: BIT;
signal Select_C_To_DataBus_MOV_ALU_C_TO_AB: BIT;
-- Used by the ADDER_16BIT opcode
signal Select_D_To_DataBus_ADDER_16BIT: BIT;
signal Select_X_To_AddressBus_ADDER_16BIT: BIT;
signal Load_X_From_AddressBus_ADDER_16BIT: BIT;
signal Select_J_To_AddressBus_ADDER_16BIT: BIT;
-- Used by the IN opcode
signal Load_XL_From_DataBus_IN: BIT;
-- Used by the OUT opcode
signal Select_XL_To_DataBus_OUT: BIT;
begin
-- Negate the instruction, so that we can afterwards probe
-- for a specific instruction
NegatedInstruction <= not(Instruction);
-- Negate the FLAGS
NegatedFlags <= not(Flags);
-- ================================================================
-- The following section implements the Fetch/Increment operations
-- ================================================================
Load_PC_FETCH <= TimingSignals(2); -- State #3
Select_PC_FETCH <= TimingSignals(0) or -- State #1
TimingSignals(1); -- State #2
-- We request the data from the RAM in the states #1 and #2
Select_SRAM_FETCH <= TimingSignals(0) or -- State #1
TimingSignals(1); -- State #2
-- Because the RAM has a latency of 1 clock cycle, we only return the
-- requested data from the RAM in state #2 (data in state #1 is still unstable!!!)
Return_SRAM_FETCH <= TimingSignals(1); -- State #2
Load_INC <= TimingSignals(0); -- State #1
Select_INC <= TimingSignals(2); -- State #3
Load_INSTR <= TimingSignals(1); -- State #2
-- ============================================================
-- Now we have to decode the instruction to enable the correct
-- Control Lines based on the provided timing signal
-- ============================================================
-- ---------------------------------------
-- Instruction "SETAB" - Format: 111DVVVV
-- ---------------------------------------
-- 111: OpCode
-- D: Destination ('0' = Register A, '1' = Register B)
-- VVVV: 4-bit value
-- Check if we execute the "SETAB" instruction - OpCode "111"
instruction_SETAB <= Instruction(7) and Instruction(6) and Instruction(5);
-- The "Select_INSTR" control line goes high, when we execute the
-- instruction "SETAB" and the time state is #4
-- This gates the instruction from the instruction register onto the data bus
Select_INSTR_To_DataBus <= instruction_SETAB and TimingSignals(3);
-- The instruction from the data bus is loaded into the register "Internal A"
Load_InternalA_From_DataBus <= instruction_SETAB and TimingSignals(3);
-- The first 4 bits from the register "Internal A" are gated back to the data bus
Select_InternalA_To_DataBus <= instruction_SETAB and TimingSignals(4);
-- The "Load_A" control line goes high, when we execute the
-- instruction "SETAB" and the time state is #4
-- This loads the data currently stored on the data bus into the Register "A"
Load_A_From_DataBus_SETAB <= instruction_SETAB and TimingSignals(4) and NegatedInstruction(4);
-- The "Load_B" control line goes high, when we execute the
-- instruction "SETAB" and the time state is #4
-- This loads the data currently stored on the data bus into the Register "B"
Load_B_From_DataBus_SETAB <= instruction_SETAB and TimingSignals(4) and Instruction(4);
-- ---------------------------------------
-- Instruction "ALU" - Format: 1000FFFF
-- ---------------------------------------
-- 1000: OpCode
-- FFFF: 4-bit function code
-- Check if we execute the "ALU" instruction - OpoCode "1000"
instruction_ALU <= Instruction(7) and NegatedInstruction(6) and NegatedInstruction(5) and NegatedInstruction(4);
instruction_NOP <= NegatedInstruction(3) and NegatedInstruction(2) and NegatedInstruction(1) and NegatedInstruction(0);
-- The "Select_A_To_ALU" and "Select_B_To_ALU" control lines are going high, when we execute
-- the instruction "ALU" and the time state is #4 or #5.
-- This transfers the content of the Register A and Register B into the ALU
-- for execution.
Select_A_To_ALU <= instruction_ALU and (TimingSignals(3) or TimingSignals(4));
Select_B_To_ALU <= instruction_ALU and (TimingSignals(3) or TimingSignals(4));
-- The "SELECT_INSTR" control line goes high, when we execute the instruction "ALU"
-- and the time state is #4 or #5.
-- This transfers the 4-bit function code of the Instruction Register into the ALU
-- for execution.
Select_INSTR_To_ALU <= instruction_ALU and (TimingSignals(3) or TimingSignals(4));
-- The "Select C" control line goes high, when we execute the instruction
-- "ALU" and the time state is #5.
-- This transfers the result of the ALU into the Register C.
Load_C_From_DataBus_ALU <= instruction_ALU and TimingSignals(4);
-- This transfers the result of the ALU Flags into the register FLAGS
Load_Flags_From_ALU <= instruction_ALU and TimingSignals(4) and not(instruction_NOP);
-- -------------------------------------------------
-- Instruction "MOV_ALU_C_TO_AB" - Format: 1010111D
-- -------------------------------------------------
-- 1010111: OpCode
-- D: Destination Register
-- => "0": Register A
-- => "1": Register B
-- Check if we execute the "MOV_ALU_OUT" instruction - OpCode "1010111"
instruction_MOV_ALU_C_TO_AB <= Instruction(7) and
NegatedInstruction(6) and
Instruction(5) and
NegatedInstruction(4) and
Instruction(3) and
Instruction(2) and
Instruction(1);
Load_A_From_DataBus_MOV_ALU_C_TO_AB <= instruction_MOV_ALU_C_TO_AB and NegatedInstruction(0) and (TimingSignals(4) or TimingSignals(5));
Load_B_From_DataBus_MOV_ALU_C_TO_AB <= instruction_MOV_ALU_C_TO_AB and Instruction(0) and (TimingSignals(4) or TimingSignals(5));
-- Select the register C of the ALU to the data bus
Select_C_To_DataBus_MOV_ALU_C_TO_AB <= instruction_MOV_ALU_C_TO_AB and (TimingSignals(4) or TimingSignals(5));
-- --------------------------------------------
-- Instruction "MOV_ALU_OUT" - Format: 11011DDD
-- --------------------------------------------
-- 11011: OpCode
-- DDD: Destination Register
-- => "000": Register D
-- => "001": Register E
-- => "010": Register F
-- => "011": Register G
-- => "100": Register H
-- => "101": <Not yet used>
-- => "110": Register XL
-- => "111": Register XH
-- Check if we execute the "MOV_ALU_OUT" instruction - OpCode "11011"
instruction_MOV_ALU_OUT <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
Instruction(4) and
Instruction(3);
-- Decode the destination and source register from the provided instruction
DestinationRegisterDecoder_MOV_ALU_OUT: Decoder3to8 port map(Instruction(2 downto 0), MOV_ALU_OUT_DestinationRegister, '1');
-- Load the specified register from the data bus
Load_D_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(0) and (TimingSignals(4) or TimingSignals(5));
Load_E_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(1) and (TimingSignals(4) or TimingSignals(5));
Load_F_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(2) and (TimingSignals(4) or TimingSignals(5));
Load_G_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(3) and (TimingSignals(4) or TimingSignals(5));
Load_H_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(4) and (TimingSignals(4) or TimingSignals(5));
Load_XL_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(6) and (TimingSignals(4) or TimingSignals(5));
Load_XH_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(7) and (TimingSignals(4) or TimingSignals(5));
-- Select the register C of the ALU to the data bus
Select_C_To_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and (TimingSignals(4) or TimingSignals(5));
-- --------------------------------------------
-- Instruction "MOV_ALU_IN" - Format: 1011DSSS
-- --------------------------------------------
-- 1011: OpCode
-- D: Destination Register
-- => "0": Register A
-- => "1": Register B
-- SSS: Source Register
-- => "000": Register D
-- => "001": Register E
-- => "010": Register F
-- => "011": Register G
-- => "100": Register H
-- => "101": <Not yet used>
-- => "110": Register XL
-- => "111": Register XH
-- Check if we execute the "MOV_ALU_IN" instruction - OpCode "1011"
instruction_MOV_ALU_IN <= Instruction(7) and
NegatedInstruction(6) and
Instruction(5) and
Instruction(4);
-- Decode the destination and source register from the provided instruction
SourceRegisterDecoder_MOV_ALU_IN: Decoder3to8 port map(Instruction(2 downto 0), MOV_ALU_IN_SourceRegister, '1');
-- Latch the specified register onto the data bus
Select_D_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(0) and (TimingSignals(4) or TimingSignals(5));
Select_E_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(1) and (TimingSignals(4) or TimingSignals(5));
Select_F_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(2) and (TimingSignals(4) or TimingSignals(5));
Select_G_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(3) and (TimingSignals(4) or TimingSignals(5));
Select_H_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(4) and (TimingSignals(4) or TimingSignals(5));
Select_XL_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(6) and (TimingSignals(4) or TimingSignals(5));
Select_XH_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(7) and (TimingSignals(4) or TimingSignals(5));
-- Load the specified register from the data bus
Load_A_From_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and NegatedInstruction(3) and TimingSignals(4);
Load_B_From_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and Instruction(3) and TimingSignals(4);
-- ---------------------------------------
-- Instruction "MOV" - Format: 00DDDSSS
-- ---------------------------------------
-- 00: OpCode
-- DDD: Destination Register
-- => "000": Register D
-- => "001": Register E
-- => "010": Register F
-- => "011": Register G
-- => "100": Register H
-- => "101": <Not yet used>
-- => "110": Register XL
-- => "111": Register XH
-- SSS: Source Register
-- => "000": Register D
-- => "001": Register E
-- => "010": Register F
-- => "011": Register G
-- => "100": Register H
-- => "101": <Not yet used>
-- => "110": Register XL
-- => "111": Register XH
-- Check if we execute the "MOV" instruction - OpCode "00"
instruction_MOV <= NegatedInstruction(7) and NegatedInstruction(6);
-- Decode the destination and source register from the provided instruction
DestinationRegisterDecoder: Decoder3to8 port map(Instruction(5 downto 3), MOV_DestinationRegister, '1');
SourceRegisterDecoder: Decoder3to8 port map(Instruction(2 downto 0), MOV_SourceRegister, '1');
-- Gate the specified register onto the data bus
Select_D_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(0) and (TimingSignals(4) or TimingSignals(5));
Select_E_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(1) and (TimingSignals(4) or TimingSignals(5));
Select_F_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(2) and (TimingSignals(4) or TimingSignals(5));
Select_G_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(3) and (TimingSignals(4) or TimingSignals(5));
Select_H_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(4) and (TimingSignals(4) or TimingSignals(5));
Select_XL_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(6) and (TimingSignals(4) or TimingSignals(5));
Select_XH_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(7) and (TimingSignals(4) or TimingSignals(5));
-- Load the specified register from the data bus
Load_D_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(0) and TimingSignals(4);
Load_E_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(1) and TimingSignals(4);
Load_F_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(2) and TimingSignals(4);
Load_G_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(3) and TimingSignals(4);
Load_H_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(4) and TimingSignals(4);
Load_XL_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(6) and TimingSignals(4);
Load_XH_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(7) and TimingSignals(4);
-- ---------------------------------------
-- Instruction "MOV16" - Format: 01DDDSSS
-- ---------------------------------------
-- 01: OpCode
-- DDD: Destination Register
-- => "000": Register M
-- => "001": Register X
-- => "010": Register J
-- => "011": Register SP
-- => "100": Register PC
-- => "101": Register BP
-- => "110": Register Y
-- => "111": Register Z
-- SSS: Source Register
-- => "000": Register M
-- => "001": Register X
-- => "010": Register J
-- => "011": Register SP
-- => "100": Register PC
-- => "101": Register BP
-- => "110": Register Y
-- => "111": Register Z
-- Check if we execute the "MOV16" instruction - OpCode "01"
instruction_MOV16 <= NegatedInstruction(7) and Instruction(6);
-- Decode the destination and source register from the provided instruction
DestinationRegisterDecoderMOV16: Decoder3to8 port map(Instruction(5 downto 3), MOV16_DestinationRegister, '1');
SourceRegisterDecoderMOV16: Decoder3to8 port map(Instruction(2 downto 0), MOV16_SourceRegister, '1');
-- Gate the specified register onto the data bus
Select_M_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(0) and (TimingSignals(4) or TimingSignals(5));
Select_X_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(1) and (TimingSignals(4) or TimingSignals(5));
Select_J_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(2) and (TimingSignals(4) or TimingSignals(5));
Select_SP_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(3) and (TimingSignals(4) or TimingSignals(5));
Select_PC_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(4) and (TimingSignals(4) or TimingSignals(5));
Select_BP_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(5) and (TimingSignals(4) or TimingSignals(5));
Select_Y_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(6) and (TimingSignals(4) or TimingSignals(5));
Select_Z_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(7) and (TimingSignals(4) or TimingSignals(5));
-- Load the specified register from the data bus
Load_M_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(0) and TimingSignals(4);
Load_X_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(1) and TimingSignals(4);
Load_J_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(2) and TimingSignals(4);
Load_SP_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(3) and TimingSignals(4);
Load_PC_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(4) and TimingSignals(4);
Load_BP_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(5) and TimingSignals(4);
Load_Y_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(6) and TimingSignals(4);
Load_Z_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(7) and TimingSignals(4);
-- -------------------------------------
-- Instruction "HLT" - Format: 11000011
-- -------------------------------------
-- Stops the execution of the CPU.
-- 11010011: OpCode
-- Check if we execute the "HLT" instruction - OpCode "11010011"
instruction_HLT <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
NegatedInstruction(3) and
NegatedInstruction(2) and
Instruction(1) and
Instruction(0);
-- Stops the CPU execution
StopCPU <= instruction_HLT;
-- ---------------------------------------
-- Instruction "LOAD" - Format: 10010DDD
-- ---------------------------------------
-- Loads a 8-bit value from SRAM memory into the specified register.
-- The SRAM memory address is stored in the register "M".
-- The transfer of the data to the register from the SRAM memory is done through the data bus.
-- 10010: OpCode
-- DDD: Destination Register
-- => "000": Register D
-- => "001": Register E
-- => "010": Register F
-- => "011": Register G
-- => "100": Register H
-- => "101": <Not used...>
-- => "110": Register XL
-- => "111": Register XH
-- Check if we execute the "LOAD" instruction - OpCode "10010"
instruction_LOAD <= Instruction(7) and
NegatedInstruction(6) and
NegatedInstruction(5) and
Instruction(4) and
NegatedInstruction(3);
-- Latch the SRAM memory address from register M onto the address bus
Select_M_To_AddressBus_LOAD <= instruction_LOAD and (TimingSignals(4) or TimingSignals(5));
-- Request the 8-bit from the RAM memory in the states #5, #6, and #7
Select_SRAM_LOAD <= instruction_LOAD and (TimingSignals(4) or TimingSignals(5) or TimingSignals(6));
-- Because the RAM has a latency of 1 clock cycle, we only return the
-- requested data from the RAM in state #7 (data in state #5, #6 is still unstable!!!)
-- This finally places the requested RAM data onto the data bus
Return_SRAM_LOAD <= TimingSignals(6); -- State #7
-- Load the Register D from the data bus
Load_D_From_DataBus_LOAD <= instruction_LOAD and
TimingSignals(6) and
NegatedInstruction(2) and
NegatedInstruction(1) and
NegatedInstruction(0);
-- Load the Register E from the data bus
Load_E_From_DataBus_LOAD <= instruction_LOAD and
TimingSignals(6) and
NegatedInstruction(2) and
NegatedInstruction(1) and
Instruction(0);
-- Load the Register F from the data bus
Load_F_From_DataBus_LOAD <= instruction_LOAD and
TimingSignals(6) and
NegatedInstruction(2) and
Instruction(1) and
NegatedInstruction(0);
-- Load the Register G from the data bus
Load_G_From_DataBus_LOAD <= instruction_LOAD and
TimingSignals(6) and
NegatedInstruction(2) and
Instruction(1) and
Instruction(0);
-- Load the Register H from the data bus
Load_H_From_DataBus_LOAD <= instruction_LOAD and
TimingSignals(6) and
Instruction(2) and
NegatedInstruction(1) and
NegatedInstruction(0);
-- Load the Register XL from the data bus
Load_XL_From_DataBus_LOAD <= instruction_LOAD and
TimingSignals(6) and
Instruction(2) and
Instruction(1) and
NegatedInstruction(0);
-- Load the Register XL from the data bus
Load_XH_From_DataBus_LOAD <= instruction_LOAD and
TimingSignals(6) and
Instruction(2) and
Instruction(1) and
Instruction(0);
-- ---------------------------------------
-- Instruction "STORE" - Format: 10011SSS
-- ---------------------------------------
-- Save a 8-bit value to SRAM memory from the specified register.
-- The SRAM memory address is stored in the register "M".
-- The transfer of the data from the register into the SRAM memory is done through the data bus.
-- 10011: OpCode
-- SSS: Source Register
-- => "000": Register D
-- => "001": Register E
-- => "010": Register F
-- => "011": Register G
-- => "100": Register H
-- => "101": <Not used...>
-- => "110": Register XL
-- => "111": Register XH
-- Check if we execute the "STORE" instruction - OpCode "10011"
instruction_STORE <= Instruction(7) and
NegatedInstruction(6) and
NegatedInstruction(5) and
Instruction(4) and
Instruction(3);
-- Selects the content of the register "M" onto the address bus
Select_M_To_AddressBus_STORE <= instruction_STORE and
(TimingSignals(4) or TimingSignals(5));
-- Select the Register D to the data bus
Select_D_To_DataBus_STORE <= instruction_STORE and
NegatedInstruction(2) and
NegatedInstruction(1) and
NegatedInstruction(0) and
(TimingSignals(4) or TimingSignals(5));
-- Select the Register E to the data bus
Select_E_To_DataBus_STORE <= instruction_STORE and
NegatedInstruction(2) and
NegatedInstruction(1) and
Instruction(0) and
(TimingSignals(4) or TimingSignals(5));
-- Select the Register F to the data bus
Select_F_To_DataBus_STORE <= instruction_STORE and
NegatedInstruction(2) and
Instruction(1) and
NegatedInstruction(0) and
(TimingSignals(4) or TimingSignals(5));
-- Select the Register G to the data bus
Select_G_To_DataBus_STORE <= instruction_STORE and
NegatedInstruction(2) and
Instruction(1) and
Instruction(0) and
(TimingSignals(4) or TimingSignals(5));
-- Select the Register H to the data bus
Select_H_To_DataBus_STORE <= instruction_STORE and
Instruction(2) and
NegatedInstruction(1) and
NegatedInstruction(0) and
(TimingSignals(4) or TimingSignals(5));
-- Select the Register XL to the data bus
Select_XL_To_DataBus_STORE <= instruction_STORE and
Instruction(2) and
Instruction(1) and
NegatedInstruction(0) and
(TimingSignals(4) or TimingSignals(5));
-- Select the Register XH to the data bus
Select_XH_To_DataBus_STORE <= instruction_STORE and
Instruction(2) and
Instruction(1) and
Instruction(0) and
(TimingSignals(4) or TimingSignals(5));
-- Enables the Load Line of the RAM memory and transfers the data from the data bus into
-- the memory address provided in register M
Load_SRAM_STORE <= instruction_STORE and
TimingSignals(5);
-- ---------------------------------------------
-- Instruction "STORE_FLAGS" - Format: 11001001
-- ---------------------------------------------
-- Selects the flags from the "FlagsOutBuffer" register onto the data bus
-- and stores it in the RAM.
-- 11001001: OpCode
-- Check if we execute the "STORE_FLAGS" instruction - OpCode "11001001"
instruction_STORE_FLAGS <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
Instruction(3) and
NegatedInstruction(2) and
NegatedInstruction(1) and
Instruction(0);
-- Selects the content of the register "M" onto the address bus
Select_M_To_AddressBus_STORE_FLAGS <= instruction_STORE_FLAGS and
(TimingSignals(4) or TimingSignals(5));
-- Selects the flags from the "FlagsOutBuffer" onto the data bus
Select_FlagsToDataBus <= instruction_STORE_FLAGS and
(TimingSignals(4) or TimingSignals(5));
-- Enables the Load Line of the RAM memory and transfers the data from the data bus into
-- the memory address provided in register M
Load_SRAM_STORE_FLAGS <= instruction_STORE_FLAGS and
TimingSignals(5);
-- ---------------------------------------------
-- Instruction "LOAD_FLAGS" - Format: 11001010
-- ---------------------------------------------
-- Loads the flags from the RAM and writes them into the "FlagsInBuffer" register.
-- and stores it onto the stack
-- 11001010: OpCode
-- Check if we execute the "STORE_FLAGS" instruction - OpCode "11001010"
instruction_LOAD_FLAGS <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
Instruction(3) and
NegatedInstruction(2) and
Instruction(1) and
NegatedInstruction(0);
-- Latch the SRAM memory address from register M onto the address bus
Select_M_To_AddressBus_LOAD_FLAGS <= instruction_LOAD_FLAGS and
(TimingSignals(4) or TimingSignals(5));
-- Request the 8-bit from the RAM memory in the states #5, #6, and #7
Select_SRAM_LOAD_FLAGS <= instruction_LOAD_FLAGS and
(TimingSignals(4) or TimingSignals(5) or TimingSignals(6));
-- Because the RAM has a latency of 1 clock cycle, we only return the
-- requested data from the RAM in state #7 (data in state #5, #6 is still unstable!!!)
-- This finally places the requested RAM data onto the data bus
Return_SRAM_LOAD_FLAGS <= TimingSignals(6); -- State #7
-- Selects the flags from the "FlagsOutBuffer" onto the data bus
Load_FlagsFromDataBus <= instruction_LOAD_FLAGS and
TimingSignals(6);
-- ---------------------------------------
-- Instruction "JMP" - Format: 11000010
-- ---------------------------------------
-- Unconditional jump to the address in the program code that is stored in the register "J".
-- The memory address from register "J" is loaded into the program counter.
-- In the next machine cycle the execution continues at the new program counter position.
-- 11000010: OpCode
-- Check if we execute the "JMP" instruction - OpCode "11000010"
instruction_JMP <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
NegatedInstruction(3) and
NegatedInstruction(2) and
Instruction(1) and
NegatedInstruction(0);
-- Select the target jump address to the address bus
Select_J_To_AddressBus_JMP <= instruction_JMP and
(TimingSignals(4) or TimingSignals(5));
-- Load the Program Counter from the address bus
Load_PC_JMP <= instruction_JMP and
TimingSignals(5);
-- --------------------------------------------
-- Instruction "SAVE_FLAGS" - Format: 11000100
-- --------------------------------------------
-- Saves the current content of the flags register into the "SavedFlags" register
-- 11000100: OpCode
-- Check if we execute the "SAVE_FLAGS" instruction - OpCode "11000100"
instruction_SAVE_FLAGS <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
NegatedInstruction(3) and
Instruction(2) and
NegatedInstruction(1) and
NegatedInstruction(0);
-- Enables the Select Line of the flags register to load the flags into the "SavedFlags" register
Select_Flags_SAVE_FLAGS <= instruction_SAVE_FLAGS and
TimingSignals(4);
-- Enables the Load Line of the "SavedFlags" register to load the flags into the "SavedFlags" register
Load_FlagsSaved_From_FlagsRegister <= instruction_SAVE_FLAGS and
TimingSignals(4);
-- -----------------------------------------------
-- Instruction "RESTORE_FLAGS" - Format: 11000101
-- -----------------------------------------------
-- Saves the current content of the flags register into the "SavedFlags" register
-- 11000101: OpCode
-- Check if we execute the "RESTORE_FLAGS" instruction - OpCode "11000101"
instruction_RESTORE_FLAGS <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
NegatedInstruction(3) and
Instruction(2) and
NegatedInstruction(1) and
Instruction(0);
-- Enables the Load Line of the flags register to load the "SavedFlags" register into the flags register
Load_Flags_SAVE_FLAGS <= instruction_RESTORE_FLAGS and
TimingSignals(4);
-- Enables the Select Line of the "SavedFlags" register to load the "SavedFlags" register into the flags register
Load_FlagsSaved_To_FlagsRegister <= instruction_RESTORE_FLAGS and
TimingSignals(4);
-- ----------------------------------------------------
-- Instruction "FLAGS_TO_OUTBUFFER" - Format: 11000110
-- ----------------------------------------------------
-- Writes the current content of the flags register onto the data bus
-- 11000110: OpCode
-- Check if we execute the "FLAGS_TO_OUTBUFFER" instruction - OpCode "11000110"
instruction_FLAGS_TO_OUTBUFFER <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
NegatedInstruction(3) and
Instruction(2) and
Instruction(1) and
NegatedInstruction(0);
-- Selects the content from the Flags register onto the Flags Bus
Select_Flags_FLAGS_TO_OUTBUFFER <= instruction_FLAGS_TO_OUTBUFFER and
TimingSignals(4);
-- Loads the content from the Flags Bus into the "FlagsOutBuffer" register
Load_FlagsFromFlagsBus <= instruction_FLAGS_TO_OUTBUFFER and
TimingSignals(4);
-- ---------------------------------------------------
-- Instruction "INBUFFER_TO_FLAGS" - Format: 11000111
-- ---------------------------------------------------
-- Writes the current content of the flags register onto the data bus
-- 11000111: OpCode
-- Check if we execute the "FLAGS_TO_INBUFFER" instruction - OpCode "11000111"
instruction_INBUFFER_TO_FLAGS <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
NegatedInstruction(3) and
Instruction(2) and
Instruction(1) and
Instruction(0);
-- Selects the content from the "FlagsInBuffer" register to the Flags Bus
Select_FlagsToFlagsBus <= instruction_INBUFFER_TO_FLAGS and
TimingSignals(4);
-- Loads the content from the Flags Bus into the Flags register
Load_Flags_INBUFFER_TO_FLAGS <= instruction_INBUFFER_TO_FLAGS and
TimingSignals(4);
-- ---------------------------------------
-- Instruction "JZ" - Format: 11000000
-- ---------------------------------------
-- Conditional jump to the address in the program code that is stored in the register "J".
-- The jump is only executed if the Zero-Flag in the FLAGS register is set to "1".
-- The memory address from register "J" is loaded into the program counter.
-- In the next machine cycle the execution continues at the new program counter position.
-- 11000000: OpCode
-- Check if we execute the "JZ" instruction - OpCode "11000000"
instruction_JZ <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
NegatedInstruction(3) and
NegatedInstruction(2) and
NegatedInstruction(1) and
NegatedInstruction(0);
Select_Flags_JZ <= instruction_JZ and
(TimingSignals(5) or TimingSignals(6) or TimingSignals(7));
-- Select the target jump address to the address bus
Select_J_To_AddressBus_JZ <= instruction_JZ and
Flags(1) and
(TimingSignals(6) or TimingSignals(7));
-- Load the Program Counter from the address bus
Load_PC_JZ <= instruction_JZ and
Flags(1) and
TimingSignals(7);
-- ---------------------------------------
-- Instruction "JNS" - Format: 11001011
-- ---------------------------------------
-- Conditional jump to the address in the program code that is stored in the register "J".
-- The jump is only executed if the Sign-Flag in the FLAGS register is set to "0".
-- The memory address from register "J" is loaded into the program counter.
-- In the next machine cycle the execution continues at the new program counter position.
-- 11001011: OpCode
-- Check if we execute the "JNS" instruction - OpCode "11001011"
instruction_JNS <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
Instruction(3) and
NegatedInstruction(2) and
Instruction(1) and
Instruction(0);
Select_Flags_JNS <= instruction_JNS and
(TimingSignals(5) or TimingSignals(6) or TimingSignals(7));
-- Select the target jump address to the address bus
Select_J_To_AddressBus_JNS <= instruction_JNS and
(not Flags(0)) and
(TimingSignals(6) or TimingSignals(7));
-- Load the Program Counter from the address bus
Load_PC_JNS <= instruction_JNS and
(not Flags(0)) and
TimingSignals(7);
-- ---------------------------------------
-- Instruction "JNC" - Format: 11010001
-- ---------------------------------------
-- Conditional jump to the address in the program code that is stored in the register "J".
-- The jump is only executed if the Carry-Flag in the FLAGS register is set to "0".
-- The memory address from register "J" is loaded into the program counter.
-- In the next machine cycle the execution continues at the new program counter position.
-- 11001011: OpCode
-- Check if we execute the "JNC" instruction - OpCode "11010001"
instruction_JNC <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
Instruction(4) and
NegatedInstruction(3) and
NegatedInstruction(2) and
NegatedInstruction(1) and
Instruction(0);
Select_Flags_JNC <= instruction_JNC and
(TimingSignals(5) or TimingSignals(6) or TimingSignals(7));
-- Select the target jump address to the address bus
Select_J_To_AddressBus_JNC <= instruction_JNC and
(not Flags(2)) and
(TimingSignals(6) or TimingSignals(7));
-- Load the Program Counter from the address bus
Load_PC_JNC <= instruction_JNC and
(not Flags(2)) and
TimingSignals(7);
-- ---------------------------------------
-- Instruction "JNZ" - Format: 11000001
-- ---------------------------------------
-- Conditional jump to the address in the program code that is stored in the register "J".
-- The jump is only executed if the Zero-Flag in the FLAGS register is set to "0".
-- The memory address from register "J" is loaded into the program counter.
-- In the next machine cycle the execution continues at the new program counter position.
-- 11000001: OpCode
-- Check if we execute the "JNZ" instruction - OpCode "11000001"
instruction_JNZ <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
NegatedInstruction(3) and
NegatedInstruction(2) and
NegatedInstruction(1) and
Instruction(0);
Select_Flags_JNZ <= instruction_JNZ and
(TimingSignals(5) or TimingSignals(6) or TimingSignals(7));
-- Select the target jump address to the address bus
Select_J_To_AddressBus_JNZ <= instruction_JNZ and
NegatedFlags(1) and
(TimingSignals(6) or TimingSignals(7));
-- Load the Program Counter from the address bus
Load_PC_JNZ <= instruction_JNZ and
NegatedFlags(1) and
TimingSignals(7);
-- ---------------------------------------------
-- Instruction "16BIT_ADDER" - Format: 11001000
-- ---------------------------------------------
-- Performs a 16-bit addition between the 16-bit value in register "X" and the
-- 8-bit value in register "D".
-- The result of the addition is put back into register "X".
-- 11001000: OpCode
-- Check if we execute the "16BIT_ADDER" instruction - OpCode "11001000"
instruction_ADDER_16BIT <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
Instruction(3) and
NegatedInstruction(2) and
NegatedInstruction(1) and
NegatedInstruction(0);
-- Select the content of register "X" to the address bus
Select_X_To_AddressBus_ADDER_16BIT <= instruction_ADDER_16BIT and
TimingSignals(3);
-- Load the A input of the 16-bit Adder from the address bus
Load_Adder16Bit_InputA <= instruction_ADDER_16BIT and
TimingSignals(3);
-- Select the content of register "J" to the address bus
Select_J_To_AddressBus_ADDER_16BIT <= instruction_ADDER_16BIT and
TimingSignals(4);
-- Load the B input of the 16-bit Adder from the address bus
Load_Adder16Bit_InputB <= instruction_ADDER_16BIT and
TimingSignals(4);
-- Select the A input into the 16-bit Adder
Select_Adder16Bit_InputA <= instruction_ADDER_16BIT and
(TimingSignals(5) or TimingSignals(6));
-- Select the B input into the 16-bit Adder
Select_Adder16Bit_InputB <= instruction_ADDER_16BIT and
(TimingSignals(5) or TimingSignals(6));
-- Load the output from the 16-bit adder into the C output
Load_Adder16Bit_OutputC <= instruction_ADDER_16BIT and
TimingSignals(6);
-- Select the output from the C output onto the address bus
Select_Adder16Bit_OutputC <= instruction_ADDER_16BIT and
TimingSignals(7);
-- Load the content from the address bus into the register "X"
Load_X_From_AddressBus_ADDER_16BIT <= instruction_ADDER_16BIT and
TimingSignals(7);
-- ---------------------------------------------
-- Instruction "IN" - Format: 1100110P
-- ---------------------------------------------
-- Reads from the specified input port and places the read value into the specified register.
-- 1100110P: OpCode
-- P: Port - "0" -> Input Port A, "1" -> Input Port B
-- Check if we execute the "IN" instruction - OpCode "1101"
instruction_IN <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
Instruction(3) and
Instruction(2) and
NegatedInstruction(1);
-- Select the input value from Input Port A to the data bus
Select_PortA_To_DataBus <= instruction_IN and
NegatedInstruction(0) and
(TimingSignals(3) or TimingSignals(4));
-- Select the input value from Input Port B to the data bus
Select_PortB_To_DataBus <= instruction_IN and
Instruction(0) and
(TimingSignals(3) or TimingSignals(4));
-- Load the Register XL from the data bus
Load_XL_From_DataBus_IN <= instruction_IN and
TimingSignals(4);
-- ---------------------------------------------
-- Instruction "OUT" - Format: 1100111P
-- ---------------------------------------------
-- Reads from the specified input port and places the read value into the specified register.
-- 1100111P: OpCode
-- P: Port - "0" -> Output Port C, "1" -> Output Port D
-- Check if we execute the "IN" instruction - OpCode "1100111"
instruction_OUT <= Instruction(7) and
Instruction(6) and
NegatedInstruction(5) and
NegatedInstruction(4) and
Instruction(3) and
Instruction(2) and
Instruction(1);
-- Select the register XL to the data bus
Select_XL_To_DataBus_OUT <= instruction_OUT and
(TimingSignals(3) or TimingSignals(4));
-- Select the output value from the data bus into the Output Port C
Load_PortC_From_DataBus <= instruction_OUT and
NegatedInstruction(0) and
TimingSignals(4);
-- Select the output value from the data bus into the Output Port D
Load_PortD_From_DataBus <= instruction_OUT and
Instruction(0) and
TimingSignals(4);
-- ================================================================
-- The following section enables the final CPU control lines
-- ================================================================
-- Enable/Disable Load Line of register A
Load_A_From_DataBus <= Load_A_From_DataBus_SETAB or
Load_A_From_DataBus_MOV_ALU_IN or
Load_A_From_DataBus_MOV_ALU_C_TO_AB;
-- Enable/Disable Load Line of register B
Load_B_From_DataBus <= Load_B_From_DataBus_SETAB or
Load_B_From_DataBus_MOV_ALU_IN or
Load_B_From_DataBus_MOV_ALU_C_TO_AB;
-- Enable/Disable Load Line of register C
Load_C_From_DataBus <= Load_C_From_DataBus_ALU;
-- Enable/Disable Load Line of register D
Load_D_From_DataBus <= Load_D_From_DataBus_MOV_ALU_OUT or
Load_D_From_DataBus_MOV or
Load_D_From_DataBus_LOAD;
-- Enable/Disable Load Line of register E
Load_E_From_DataBus <= Load_E_From_DataBus_MOV_ALU_OUT or
Load_E_From_DataBus_MOV or
Load_E_From_DataBus_LOAD;
-- Enable/Disable Load Line of register F
Load_F_From_DataBus <= Load_F_From_DataBus_MOV_ALU_OUT or
Load_F_From_DataBus_MOV or
Load_F_From_DataBus_LOAD;
-- Enable/Disable Load Line of register G
Load_G_From_DataBus <= Load_G_From_DataBus_MOV_ALU_OUT or
Load_G_From_DataBus_MOV or
Load_G_From_DataBus_LOAD;
-- Enable/Disable Load Line of register H
Load_H_From_DataBus <= Load_H_From_DataBus_MOV_ALU_OUT or
Load_H_From_DataBus_MOV or
Load_H_From_DataBus_LOAD;
-- Enable/Disable Load Line of register XL
Load_XL_From_DataBus <= Load_XL_From_DataBus_MOV_ALU_OUT or
Load_XL_From_DataBus_MOV or
Load_XL_From_DataBus_LOAD or
Load_XL_From_DataBus_IN;
-- Enable/Disable Load Line of register XH
Load_XH_From_DataBus <= Load_XH_From_DataBus_MOV_ALU_OUT or
Load_XH_From_DataBus_MOV or
Load_XH_From_DataBus_LOAD;
-- Enable/Disable the Load Line of register M
Load_M_From_AddressBus <= Load_M_From_AddressBus_MOV16;
-- Enable/Disable the Load Line of register X
Load_X_From_AddressBus <= Load_X_From_AddressBus_MOV16 or
Load_X_From_AddressBus_ADDER_16BIT;
-- Enable/Disable Load Line of register J
Load_J_From_AddressBus <= Load_J_From_AddressBus_MOV16;
-- Enable/Disable Load Line of register SP
Load_SP_From_AddressBus <= Load_SP_From_AddressBus_MOV16;
-- Enable/Disable Load Line of register BP
Load_BP_From_AddressBus <= Load_BP_From_AddressBus_MOV16;
-- Enable/Disable Load Line of register Y
Load_Y_From_AddressBus <= Load_Y_From_AddressBus_MOV16;
-- Enable/Disable Load Line of register Z
Load_Z_From_AddressBus <= Load_Z_From_AddressBus_MOV16;
-- Enable/Disable Select Line of register C
Select_C_To_DataBus <= Select_C_To_DataBus_MOV_ALU_OUT or
Select_C_To_DataBus_MOV_ALU_C_TO_AB;
-- Enable/Disable Select Line of register D
Select_D_To_DataBus <= Select_D_To_DataBus_MOV_ALU_IN or
Select_D_To_DataBus_MOV or
Select_D_To_DataBus_STORE or
Select_D_To_DataBus_ADDER_16BIT;
-- Enable/Disable Select Line of register E
Select_E_To_DataBus <= Select_E_To_DataBus_MOV_ALU_IN or
Select_E_To_DataBus_MOV or
Select_E_To_DataBus_STORE;
-- Enable/Disable Select Line of register F
Select_F_To_DataBus <= Select_F_To_DataBus_MOV_ALU_IN or
Select_F_To_DataBus_MOV or
Select_F_To_DataBus_STORE;
-- Enable/Disable Select Line of register G
Select_G_To_DataBus <= Select_G_To_DataBus_MOV_ALU_IN or
Select_G_To_DataBus_MOV or
Select_G_To_DataBus_STORE;
-- Enable/Disable Select Line of register H
Select_H_To_DataBus <= Select_H_To_DataBus_MOV_ALU_IN or
Select_H_To_DataBus_MOV or
Select_H_To_DataBus_STORE;
-- Enable/Disable Select Line of register XL
Select_XL_To_DataBus <= Select_XL_To_DataBus_MOV_ALU_IN or
Select_XL_To_DataBus_MOV or
Select_XL_To_DataBus_STORE or
Select_XL_To_DataBus_OUT;
-- Enable/Disable Select Line of register XH
Select_XH_To_DataBus <= Select_XH_To_DataBus_MOV_ALU_IN or
Select_XH_To_DataBus_MOV or
Select_XH_To_DataBus_STORE;
-- Enable/Disable the Select Line of register M
Select_M_To_AddressBus <= Select_M_To_AddressBus_MOV16 or
Select_M_To_AddressBus_LOAD or
Select_M_To_AddressBus_LOAD_FLAGS or
Select_M_To_AddressBus_STORE or
Select_M_To_AddressBus_STORE_FLAGS;
-- Enable/Disable the Select Line of register X
Select_X_To_AddressBus <= Select_X_To_AddressBus_MOV16 or
Select_X_To_AddressBus_ADDER_16BIT or
Select_X_To_AddressBus_ADDER_16BIT;
-- Enable/Disable Select Line of register SP
Select_SP_To_AddressBus <= Select_SP_To_AddressBus_MOV16;
-- Enable/Disable Select Line of register BP
Select_BP_To_AddressBus <= Select_BP_To_AddressBus_MOV16;
-- Enable/Disable Select Line of register Y
Select_Y_To_AddressBus <= Select_Y_To_AddressBus_MOV16;
-- Enable/Disable Select Line of register Z
Select_Z_To_AddressBus <= Select_Z_To_AddressBus_MOV16;
-- Enable/Disable Select Line of register J
Select_J_To_AddressBus <= Select_J_To_AddressBus_MOV16 or
Select_J_To_AddressBus_JMP or
Select_J_To_AddressBus_JZ or
Select_J_To_AddressBus_JNS or
Select_J_To_AddressBus_JNZ or
Select_J_To_AddressBus_JNC or
Select_J_To_AddressBus_ADDER_16BIT;
-- Enables the Select Line of the flags register
Select_Flags <= Select_Flags_JZ or
Select_Flags_SAVE_FLAGS or
Select_Flags_JNZ or
Select_Flags_JNS or
Select_Flags_JNC or
Select_Flags_FLAGS_TO_OUTBUFFER;
-- Enables the Load Line of the flags register
Load_Flags <= Load_Flags_From_ALU or
Load_Flags_SAVE_FLAGS or
Load_Flags_INBUFFER_TO_FLAGS;
-- Requests the data from the RAM to the data bus
Select_SRAM <= Select_SRAM_FETCH or
Select_SRAM_LOAD or
Select_SRAM_LOAD_FLAGS;
-- Loads the data from the data bus into the RAM
Load_SRAM <= Load_SRAM_STORE or
Load_SRAM_STORE_FLAGS;
-- Returns the requested data from the RAM onto the data bus
Return_SRAM <= Return_SRAM_FETCH or
Return_SRAM_LOAD or
Return_SRAM_LOAD_FLAGS;
-- Enable/Disable the Load Line of the Program Counter
Load_PC <= Load_PC_FETCH or
Load_PC_JMP or
Load_PC_JZ or
Load_PC_JNS or
Load_PC_JNZ or
Load_PC_JNC or
Load_PC_From_AddressBus_MOV16;
-- Enable/Disable the Load Line of the Program Counter
Select_PC <= Select_PC_FETCH or
Select_PC_To_AddressBus_MOV16;
end Behavioral;
|
mit
|
6a1f7b5992bdd1b867bdcff70c907032
| 0.53121 | 4.715966 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 1/MODULOPRINCIPAL.vhd
| 1 | 4,064 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MODULOPRINCIPAL is
Port ( rst : in STD_LOGIC;
CLK : in STD_LOGIC;
ALURESULT : out STD_LOGIC_VECTOR (31 downto 0));
end MODULOPRINCIPAL;
architecture Behavioral of MODULOPRINCIPAL is
COMPONENT PC
PORT(
rst : IN std_logic;
dataIn : IN std_logic_vector(31 downto 0);
CLK : IN std_logic;
DataOut : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT Sumador32bits
PORT(
Oper1 : IN std_logic_vector(31 downto 0);
Oper2 : IN std_logic_vector(31 downto 0);
Result : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT InstructionMemory
PORT(
Address : IN std_logic_vector(5 downto 0);
rst : IN std_logic;
Instruction : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT OMUXT
PORT(
Crs2 : IN std_logic_vector(31 downto 0);
SEUimm : IN std_logic_vector(31 downto 0);
i : IN std_logic;
oper2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT RF
PORT(
rs1 : IN std_logic_vector(4 downto 0);
rs2 : IN std_logic_vector(4 downto 0);
rd : IN std_logic_vector(4 downto 0);
DWR : IN std_logic_vector(31 downto 0);
rst : IN std_logic;
Crs1 : OUT std_logic_vector(31 downto 0);
Crs2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT SEU
PORT(
imm13 : IN std_logic_vector(12 downto 0);
SEUimm : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT ALU
PORT(
Oper1 : IN std_logic_vector(31 downto 0);
Oper2 : IN std_logic_vector(31 downto 0);
ALUOP : IN std_logic_vector(5 downto 0);
ALURESULT : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT CU
PORT(
OP : IN std_logic_vector(1 downto 0);
OP3 : IN std_logic_vector(5 downto 0);
ALUOP : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
signal B0:std_logic_vector(31 downto 0);--Result: conecta al sumador con el DataIn de nPC
signal B1:std_logic_vector(31 downto 0);--DataOut(nPC): conecta al nPC con el DataIn de PC
signal B2:std_logic_vector(31 downto 0);--DataOut(PC): conecta al PC con el address del IM y con el Oper2 de sumador32bits
signal B3:std_logic_vector(31 downto 0);--Instruction: conecta al IM con el CU(OP(31-30),OP3(24-19)),RF((18-14),rs2(4-0),rd(29-25)),
--SEU(imm13(12-0)) y OMUXT(i(13))
signal B4:std_logic_vector(5 downto 0); --ALUOP: conecta a CU y con la ALU
signal B5:std_logic_vector(31 downto 0);--ALURESULT: conecta a la ALU con el rd del RF, es la salida del Modulo Principal
signal B6:std_logic_vector(31 downto 0);--Crs1: conecta al RF con Oper1 de la ALU
signal B7:std_logic_vector(31 downto 0);--Crs2: conecta al RF con OMUXT
signal B8:std_logic_vector(31 downto 0);--SEUimm: conecta a SEU con OMUXT
signal B9:std_logic_vector(31 downto 0);--Oper2: conecta a OMUXT con el Oper2 de la ALU
begin
Inst_PC: PC PORT MAP(
rst => rst,
dataIn => B1,
CLK => CLK,
DataOut => B2
);
Inst_Sumador32bits: Sumador32bits PORT MAP(
Oper1 => "00000000000000000000000000000001",
Oper2 => B2,
Result => B0
);
Inst_nPC: PC PORT MAP(
rst => rst,
CLK => CLK,
DataIn => B0,
DataOut => B1
);
Inst_InstructionMemory: InstructionMemory PORT MAP(
Address => B2(5 downto 0),
rst => rst,
Instruction =>B3
);
Inst_OMUXT: OMUXT PORT MAP(
Crs2 => B7,
SEUimm => B8,
i => B3(13),
oper2 => B9
);
Inst_RF: RF PORT MAP(
rs1 => B3(18 downto 14),
rs2 => B3(4 downto 0),
rd => B3(29 downto 25),
DWR => B5,
rst => rst,
Crs1 => B6,
Crs2 => B7
);
Inst_SEU: SEU PORT MAP(
imm13 => B3(12 downto 0),
SEUimm => B8
);
Inst_ALU: ALU PORT MAP(
Oper1 => B6,
Oper2 => B9,
ALUOP => B4,
ALURESULT => B5
);
Inst_CU: CU PORT MAP(
OP => B3(31 downto 30),
OP3 =>B3(24 downto 19) ,
ALUOP => B4
);
ALURESULT<=B5;
end Behavioral;
|
mit
|
f56fe835dd4c224b5f1f10a545d5d0d3
| 0.620817 | 2.977289 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_iic_0_0/synth/system_axi_iic_0_0.vhd
| 1 | 10,024 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_iic:2.0
-- IP Revision: 14
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_axi_iic_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
iic2intc_irpt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
sda_i : IN STD_LOGIC;
sda_o : OUT STD_LOGIC;
sda_t : OUT STD_LOGIC;
scl_i : IN STD_LOGIC;
scl_o : OUT STD_LOGIC;
scl_t : OUT STD_LOGIC;
gpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_axi_iic_0_0;
ARCHITECTURE system_axi_iic_0_0_arch OF system_axi_iic_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_iic_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_iic IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_IIC_FREQ : INTEGER;
C_TEN_BIT_ADR : INTEGER;
C_GPO_WIDTH : INTEGER;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_SCL_INERTIAL_DELAY : INTEGER;
C_SDA_INERTIAL_DELAY : INTEGER;
C_SDA_LEVEL : INTEGER;
C_SMBUS_PMBUS_HOST : INTEGER;
C_DEFAULT_VALUE : STD_LOGIC_VECTOR(7 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
iic2intc_irpt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
sda_i : IN STD_LOGIC;
sda_o : OUT STD_LOGIC;
sda_t : OUT STD_LOGIC;
scl_i : IN STD_LOGIC;
scl_o : OUT STD_LOGIC;
scl_t : OUT STD_LOGIC;
gpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT axi_iic;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_axi_iic_0_0_arch: ARCHITECTURE IS "axi_iic,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_axi_iic_0_0_arch : ARCHITECTURE IS "system_axi_iic_0_0,axi_iic,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_axi_iic_0_0_arch: ARCHITECTURE IS "system_axi_iic_0_0,axi_iic,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_iic,x_ipVersion=2.0,x_ipCoreRevision=14,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_IIC_FREQ=100000,C_TEN_BIT_ADR=0,C_GPO_WIDTH=1,C_S_AXI_ACLK_FREQ_HZ=100000000,C_SCL_INERTIAL_DELAY=0,C_SDA_INERTIAL_DELAY=0,C_SDA_LEVEL=1,C_SMBUS_PMBUS_HOST=0,C_DEFAULT_VALUE=0x00}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF iic2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF sda_i: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_I";
ATTRIBUTE X_INTERFACE_INFO OF sda_o: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_O";
ATTRIBUTE X_INTERFACE_INFO OF sda_t: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_T";
ATTRIBUTE X_INTERFACE_INFO OF scl_i: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_I";
ATTRIBUTE X_INTERFACE_INFO OF scl_o: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_O";
ATTRIBUTE X_INTERFACE_INFO OF scl_t: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_T";
BEGIN
U0 : axi_iic
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_IIC_FREQ => 100000,
C_TEN_BIT_ADR => 0,
C_GPO_WIDTH => 1,
C_S_AXI_ACLK_FREQ_HZ => 100000000,
C_SCL_INERTIAL_DELAY => 0,
C_SDA_INERTIAL_DELAY => 0,
C_SDA_LEVEL => 1,
C_SMBUS_PMBUS_HOST => 0,
C_DEFAULT_VALUE => X"00"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
iic2intc_irpt => iic2intc_irpt,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
sda_i => sda_i,
sda_o => sda_o,
sda_t => sda_t,
scl_i => scl_i,
scl_o => scl_o,
scl_t => scl_t,
gpo => gpo
);
END system_axi_iic_0_0_arch;
|
apache-2.0
|
dcbe513643351e28968cdee2f30c5d4a
| 0.684657 | 3.180203 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_ilmb_v10_0/synth/system_ilmb_v10_0.vhd
| 1 | 9,019 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:lmb_v10:3.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY lmb_v10_v3_0_9;
USE lmb_v10_v3_0_9.lmb_v10;
ENTITY system_ilmb_v10_0 IS
PORT (
LMB_Clk : IN STD_LOGIC;
SYS_Rst : IN STD_LOGIC;
LMB_Rst : OUT STD_LOGIC;
M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
M_ReadStrobe : IN STD_LOGIC;
M_WriteStrobe : IN STD_LOGIC;
M_AddrStrobe : IN STD_LOGIC;
M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_ReadStrobe : OUT STD_LOGIC;
LMB_WriteStrobe : OUT STD_LOGIC;
LMB_AddrStrobe : OUT STD_LOGIC;
LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Ready : OUT STD_LOGIC;
LMB_Wait : OUT STD_LOGIC;
LMB_UE : OUT STD_LOGIC;
LMB_CE : OUT STD_LOGIC;
LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
);
END system_ilmb_v10_0;
ARCHITECTURE system_ilmb_v10_0_arch OF system_ilmb_v10_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ilmb_v10_0_arch: ARCHITECTURE IS "yes";
COMPONENT lmb_v10 IS
GENERIC (
C_LMB_NUM_SLAVES : INTEGER;
C_LMB_DWIDTH : INTEGER;
C_LMB_AWIDTH : INTEGER;
C_EXT_RESET_HIGH : INTEGER
);
PORT (
LMB_Clk : IN STD_LOGIC;
SYS_Rst : IN STD_LOGIC;
LMB_Rst : OUT STD_LOGIC;
M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
M_ReadStrobe : IN STD_LOGIC;
M_WriteStrobe : IN STD_LOGIC;
M_AddrStrobe : IN STD_LOGIC;
M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_ReadStrobe : OUT STD_LOGIC;
LMB_WriteStrobe : OUT STD_LOGIC;
LMB_AddrStrobe : OUT STD_LOGIC;
LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Ready : OUT STD_LOGIC;
LMB_Wait : OUT STD_LOGIC;
LMB_UE : OUT STD_LOGIC;
LMB_CE : OUT STD_LOGIC;
LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
);
END COMPONENT lmb_v10;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_ilmb_v10_0_arch: ARCHITECTURE IS "lmb_v10,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_ilmb_v10_0_arch : ARCHITECTURE IS "system_ilmb_v10_0,lmb_v10,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_ilmb_v10_0_arch: ARCHITECTURE IS "system_ilmb_v10_0,lmb_v10,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_v10,x_ipVersion=3.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_LMB_NUM_SLAVES=1,C_LMB_DWIDTH=32,C_LMB_AWIDTH=32,C_EXT_RESET_HIGH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF SYS_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.SYS_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 RST, xilinx.com:interface:lmb:1.0 LMB_M RST";
ATTRIBUTE X_INTERFACE_INFO OF M_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ABUS";
ATTRIBUTE X_INTERFACE_INFO OF M_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF M_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF M_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF M_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF M_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M BE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READY";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WAIT";
ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 UE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 CE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ABUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READY";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WAIT";
ATTRIBUTE X_INTERFACE_INFO OF LMB_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M UE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M CE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 BE";
BEGIN
U0 : lmb_v10
GENERIC MAP (
C_LMB_NUM_SLAVES => 1,
C_LMB_DWIDTH => 32,
C_LMB_AWIDTH => 32,
C_EXT_RESET_HIGH => 1
)
PORT MAP (
LMB_Clk => LMB_Clk,
SYS_Rst => SYS_Rst,
LMB_Rst => LMB_Rst,
M_ABus => M_ABus,
M_ReadStrobe => M_ReadStrobe,
M_WriteStrobe => M_WriteStrobe,
M_AddrStrobe => M_AddrStrobe,
M_DBus => M_DBus,
M_BE => M_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB_ABus => LMB_ABus,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadDBus => LMB_ReadDBus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_Ready => LMB_Ready,
LMB_Wait => LMB_Wait,
LMB_UE => LMB_UE,
LMB_CE => LMB_CE,
LMB_BE => LMB_BE
);
END system_ilmb_v10_0_arch;
|
apache-2.0
|
5842ecb210e0540d83c0470da755fffe
| 0.694756 | 3.317028 | false | true | false | false |
gustavogarciautp/Procesador
|
Entrega 2/RF_tb.vhd
| 1 | 2,902 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY RF_tb IS
END RF_tb;
ARCHITECTURE behavior OF RF_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RF
PORT(
rs1 : IN std_logic_vector(5 downto 0);
rs2 : IN std_logic_vector(5 downto 0);
rd : IN std_logic_vector(5 downto 0);
DWR : IN std_logic_vector(31 downto 0);
rst : IN std_logic;
Crs1 : OUT std_logic_vector(31 downto 0);
Crs2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal rs1 : std_logic_vector(5 downto 0) := (others => '0');
signal rs2 : std_logic_vector(5 downto 0) := (others => '0');
signal rd : std_logic_vector(5 downto 0) := (others => '0');
signal DWR : std_logic_vector(31 downto 0) := (others => '0');
signal rst : std_logic := '0';
--Outputs
signal Crs1 : std_logic_vector(31 downto 0);
signal Crs2 : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RF PORT MAP (
rs1 => rs1,
rs2 => rs2,
rd => rd,
DWR => DWR,
rst => rst,
Crs1 => Crs1,
Crs2 => Crs2
);
-- Stimulus process
stim_proc: process
begin
rst<='1';
wait for 20 ns;
rst<='0';
rs1<=(others=>'0');
rs2<="000101";
rd<="000001";
DWR<="00000000000000000000000000000101";
wait for 40 ns;
rs1<=(others=>'0');
rs2<="111000";
rd<="010000";
DWR<="11111111111111111111111111111000";
wait for 40 ns;
rs1<=(others=>'0');
rs2<="000100";
rd<="010001";
DWR<="00000000000000000000000000000100";
wait for 40 ns;
rs1<="000001";
rs2<="000010";
rd<="011000";
DWR<="00000000000000000000000000010100";
wait for 40 ns;
rs1<="010001";
rs2<="000001";
rd<="011001";
DWR<="00000000000000000000000000000010";
wait for 40 ns;
rs1<=(others=>'0');
rs2<=(others=>'0');
rd<=(others=>'0');
DWR<="00000000000000000000000000000000";
wait for 40 ns;
rs1<="000001";
rs2<="000011";
rd<="100000";
DWR<="00000000000000000000000000001000";
wait for 40 ns;
rs1<=(others=>'0');
rs2<=(others=>'0');
rd<=(others=>'0');
DWR<="00000000000000000000000000000000";
wait for 40 ns;
rs1<=(others=>'0');
rs2<="000100";
rd<=(others=>'0');
DWR<="11111111111111111111111111111100";
wait for 40 ns;
rs1<=(others=>'0');
rs2<="000001";
rd<="000010";
DWR<="00000000000000000000000000000101";
wait for 40 ns;
rs1<=(others=>'0');
rs2<="010000";
rd<="001000";
DWR<="11111111111111111111111111111000";
wait for 40 ns;
rst<='1';
rs1<="000001";
rs2<="000010";
rd<="001101";
DWR<="00000000000000000000000000001100";
wait;
end process;
END;
|
mit
|
0a8532b6e059e6686f67d18ebb90919b
| 0.555134 | 3.487981 | false | false | false | false |
eaglewyng/FPGA2048
|
game.vhd
| 1 | 6,143 |
----------------------------------------------------------------------------------
-- Engineers: Parker Ridd and Travis Chambers
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Game is
port (
clk : in std_logic;
sw0 : in std_logic;
btn : in std_logic_vector(3 downto 0);
seg : out std_logic_vector(6 downto 0);
dp : out std_logic;
an : out std_logic_vector(3 downto 0);
vgaRed : out std_logic_vector(2 downto 0);
vgaGreen : out std_logic_vector(2 downto 0);
vgaBlue : out std_logic_vector(1 downto 0);
HS : out std_logic;
VS : out std_logic
);
end Game;
architecture Behavioral of Game is
--GAME SIGNALS
signal rst : std_logic;
type state is (start, playing, endGame);
signal state_reg, state_next : state;
signal rgbOut : std_logic_vector(7 downto 0);
signal rgbFromGrid : std_logic_vector(7 downto 0);
--INPUTS to GRID
signal grid_color : std_logic_vector(7 downto 0);
--outputs from GRID
signal isVictory : std_logic;
signal game_over : std_logic;
signal draw_grid : std_logic;
--outputs from VGA
signal blank : std_logic;
--wires between entities
signal pixel_x : std_logic_vector(9 downto 0);
signal pixel_y : std_logic_vector(9 downto 0);
--debouncing signals
--function--
function log2c(n: integer) return integer is
variable m, p: integer;
begin
m := 0;
p := 1;
while p < n loop
m := m + 1;
p := p * 2;
end loop;
return m;
end log2c;
--HS and VS registers
signal hs_reg, hs_next, vs_reg, vs_next : STD_LOGIC;
signal hs_fromVGA, vs_fromVGA : STD_LOGIC;
--============================================================================
------------------Constant values---------------------------------------------
--============================================================================
constant COUNTER_SIZE : natural := 19;
signal btn_int1Debounced, btn_int1Debounced_next, btn_int2Debounced, btn_int2Debounced_next : STD_LOGIC_VECTOR(3 downto 0);
signal deb_counter_out, deb_counter_next : UNSIGNED(COUNTER_SIZE downto 0) := (OTHERS => '0'); --counter output
signal btn_debounced, btn_debounced_next : STD_LOGIC_VECTOR(3 downto 0);
signal counter_set : STD_LOGIC;
signal ssd_data_in : STD_LOGIC_VECTOR(15 downto 0);
begin
--============================================================================
------------------Registers---------------------------------------------------
--============================================================================
rst <= not sw0;
--state register
process(clk, rst)
begin
if rst = '1' then
state_reg <= start;
elsif rising_edge(clk) then
state_reg <= state_next;
hs_reg <= hs_next;
vs_reg <= vs_next;
end if;
end process;
vs_next <= vs_fromVGA;
hs_next <= hs_fromVGA;
VS <= vs_reg;
HS <= hs_reg;
--FSM
process(state_reg, sw0, game_over, isVictory)
begin
case state_reg is
when start =>
--display blank grid (no boxes)
grid_color <= "11101011";
if (sw0 = '1') then
state_next <= playing;
else
state_next <= start;
end if;
when playing =>
--generate 2 boxes of value 2 at random squares in the grid
--each button press will generate a new box and merge/move existing boxes
grid_color <= "10001110";
if (game_over = '1') then
state_next <= endGame;
else
state_next <= playing;
end if;
when endGame =>
--move back to start when sw0 = 0;
grid_color <= "11101011";
if (sw0 = '1') then
state_next <= endGame;
if (isVictory = '1') then
grid_color <= "11000100";
else
grid_color <= "11101001";
end if;
else
state_next <= start;
end if;
end case;
end process;
-------------------------------------------------------------
-- Game Logic for VGA
-------------------------------------------------------------
vgaRed <= rgbOut(7 downto 5);
vgaGreen <= rgbOut(4 downto 2);
vgaBlue <= rgbOut(1 downto 0);
rgbOut <= rgbFromGrid when draw_grid = '1' else
"00000000" when blank = '1' else
"11111111";
-------------------------------------------------------------
-- Entity Instantiations
-------------------------------------------------------------
Grid1 : entity work.Grid
port map(
clk => clk,
rst => rst,
grid_color =>grid_color,
pixel_x => pixel_x,
pixel_y => pixel_y,
btn => btn_debounced,
draw_grid => draw_grid,
rgbOut => rgbFromGrid,
gameOver => game_over,
score => ssd_data_in
);
SevenSeg : entity work.seven_segment_display
port map(
clk => clk,
data_in => ssd_data_in,
dp_in => "1111",
blank => "0000",
seg => seg,
dp => dp,
an => an
);
VGA : entity work.vga_timing
port map (
clk => clk,
rst => rst,
HS => hs_fromVGA,
VS => vs_fromVGA,
pixel_x => pixel_x,
pixel_y => pixel_y,
last_column => open,
last_row => open,
blank => blank
);
--============================================================================
------------------Debouncer Circuit-------------------------------------------
--============================================================================
process(clk, rst)
begin
if(rst = '1') then
btn_int1debounced <= (others => '0');
btn_int2debounced <= (others => '0');
btn_debounced <= (others => '0');
deb_counter_out <= (others => '0');
elsif(clk'event and clk = '1') then
btn_int1debounced <= btn_int1debounced_next;
btn_int2debounced <= btn_int2debounced_next;
btn_debounced <= btn_debounced_next;
deb_counter_out <= deb_counter_next;
end if;
end process;
counter_set <= '1' when btn_int2debounced /= btn_int1debounced else
'0';
deb_counter_next <= (others => '0') when counter_set = '1' else
deb_counter_out + 1;
btn_int1debounced_next <= btn;
btn_int2debounced_next <= btn_int1debounced;
btn_debounced_next <= btn_int2debounced when deb_counter_out(COUNTER_SIZE) = '1' else
btn_debounced;
end Behavioral;
|
mit
|
267b393e87d239c5e96f95fa42db3091
| 0.512779 | 3.500285 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_uartlite_0_0/system_axi_uartlite_0_0_sim_netlist.vhdl
| 1 | 125,504 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:46:56 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_uartlite_0_0/system_axi_uartlite_0_0_sim_netlist.vhdl
-- Design : system_axi_uartlite_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_baudrate is
port (
en_16x_Baud : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_baudrate : entity is "baudrate";
end system_axi_uartlite_0_0_baudrate;
architecture STRUCTURE of system_axi_uartlite_0_0_baudrate is
signal \^en_16x_baud\ : STD_LOGIC;
signal count : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \count[2]_i_2_n_0\ : STD_LOGIC;
signal \count[4]_i_2_n_0\ : STD_LOGIC;
signal \count[4]_i_3_n_0\ : STD_LOGIC;
signal \count[9]_i_2_n_0\ : STD_LOGIC;
signal count_0 : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \count[1]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \count[2]_i_2\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \count[3]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \count[4]_i_2\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \count[4]_i_3\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \count[9]_i_2\ : label is "soft_lutpair11";
begin
EN_16x_Baud_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \count[9]_i_2_n_0\,
I1 => count(5),
I2 => count(6),
I3 => count(9),
I4 => count(7),
I5 => count(8),
O => \^en_16x_baud\
);
EN_16x_Baud_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^en_16x_baud\,
Q => en_16x_Baud,
R => SR(0)
);
\count[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFF0000FFFE"
)
port map (
I0 => count(3),
I1 => count(4),
I2 => \count[2]_i_2_n_0\,
I3 => count(2),
I4 => count(0),
I5 => count(1),
O => count_0(0)
);
\count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => count(1),
I1 => count(0),
O => count_0(1)
);
\count[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E1E1E1E1E1E1E1E0"
)
port map (
I0 => count(1),
I1 => count(0),
I2 => count(2),
I3 => \count[2]_i_2_n_0\,
I4 => count(4),
I5 => count(3),
O => count_0(2)
);
\count[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => count(9),
I1 => count(7),
I2 => count(8),
I3 => count(6),
I4 => count(5),
O => \count[2]_i_2_n_0\
);
\count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAA9"
)
port map (
I0 => count(3),
I1 => count(1),
I2 => count(0),
I3 => count(2),
O => count_0(3)
);
\count[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A9A9A9A9A9A9A9A8"
)
port map (
I0 => count(4),
I1 => count(3),
I2 => \count[4]_i_2_n_0\,
I3 => \count[4]_i_3_n_0\,
I4 => count(6),
I5 => count(5),
O => count_0(4)
);
\count[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => count(1),
I1 => count(0),
I2 => count(2),
O => \count[4]_i_2_n_0\
);
\count[4]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => count(8),
I1 => count(7),
I2 => count(9),
O => \count[4]_i_3_n_0\
);
\count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF00000000FFFE"
)
port map (
I0 => count(9),
I1 => count(7),
I2 => count(8),
I3 => count(6),
I4 => count(5),
I5 => \count[9]_i_2_n_0\,
O => count_0(5)
);
\count[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A9A9A9A9A9A9A9A8"
)
port map (
I0 => count(6),
I1 => count(5),
I2 => \count[9]_i_2_n_0\,
I3 => count(8),
I4 => count(7),
I5 => count(9),
O => count_0(6)
);
\count[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAA9"
)
port map (
I0 => count(7),
I1 => count(6),
I2 => count(5),
I3 => \count[9]_i_2_n_0\,
O => count_0(7)
);
\count[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00FE01FF00FE00"
)
port map (
I0 => \count[9]_i_2_n_0\,
I1 => count(5),
I2 => count(6),
I3 => count(8),
I4 => count(7),
I5 => count(9),
O => count_0(8)
);
\count[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F0F0F0E1"
)
port map (
I0 => count(8),
I1 => count(7),
I2 => count(9),
I3 => count(6),
I4 => count(5),
I5 => \count[9]_i_2_n_0\,
O => count_0(9)
);
\count[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => count(4),
I1 => count(3),
I2 => count(2),
I3 => count(0),
I4 => count(1),
O => \count[9]_i_2_n_0\
);
\count_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => count_0(0),
Q => count(0),
R => SR(0)
);
\count_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => count_0(1),
Q => count(1),
R => SR(0)
);
\count_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => count_0(2),
Q => count(2),
R => SR(0)
);
\count_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => count_0(3),
Q => count(3),
R => SR(0)
);
\count_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => count_0(4),
Q => count(4),
R => SR(0)
);
\count_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => count_0(5),
Q => count(5),
R => SR(0)
);
\count_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => count_0(6),
Q => count(6),
R => SR(0)
);
\count_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => count_0(7),
Q => count(7),
R => SR(0)
);
\count_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => count_0(8),
Q => count(8),
R => SR(0)
);
\count_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => count_0(9),
Q => count(9),
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_cdc_sync is
port (
p_26_out : out STD_LOGIC;
scndry_out : out STD_LOGIC;
start_Edge_Detected : in STD_LOGIC;
EN_16x_Baud_reg : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 0 to 0 );
rx : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_cdc_sync : entity is "cdc_sync";
end system_axi_uartlite_0_0_cdc_sync;
architecture STRUCTURE of system_axi_uartlite_0_0_cdc_sync is
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rx,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
\SERIAL_TO_PARALLEL[1].fifo_din[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE00CE00"
)
port map (
I0 => \^scndry_out\,
I1 => start_Edge_Detected,
I2 => EN_16x_Baud_reg,
I3 => s_axi_aresetn,
I4 => \in\(0),
O => p_26_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_cntr_incr_decr_addn_f is
port (
SS : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
fifo_full_p1 : out STD_LOGIC;
tx_Start0 : out STD_LOGIC;
reset_TX_FIFO_reg : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
fifo_Read : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
tx_Buffer_Full : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
tx_Data_Enable_reg : in STD_LOGIC;
tx_DataBits : in STD_LOGIC;
tx_Start : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_cntr_incr_decr_addn_f : entity is "cntr_incr_decr_addn_f";
end system_axi_uartlite_0_0_cntr_incr_decr_addn_f;
architecture STRUCTURE of system_axi_uartlite_0_0_cntr_incr_decr_addn_f is
signal \FIFO_Full_i_2__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.cnt_i[3]_i_2__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.cnt_i[4]_i_3__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.cnt_i[4]_i_4__0_n_0\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^ss\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal addr_i_p1 : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[1]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[3]_i_2__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[4]_i_3__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[4]_i_4__0\ : label is "soft_lutpair19";
begin
Q(4 downto 0) <= \^q\(4 downto 0);
SS(0) <= \^ss\(0);
FIFO_Full_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000004090000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
I1 => \^q\(0),
I2 => \^q\(4),
I3 => fifo_Read,
I4 => \^q\(3),
I5 => \FIFO_Full_i_2__0_n_0\,
O => fifo_full_p1
);
\FIFO_Full_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^q\(1),
I1 => \^q\(2),
O => \FIFO_Full_i_2__0_n_0\
);
\INFERRED_GEN.cnt_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB4BBBB444B4444"
)
port map (
I0 => \^q\(4),
I1 => fifo_Read,
I2 => tx_Buffer_Full,
I3 => Bus_RNW_reg,
I4 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I5 => \^q\(0),
O => addr_i_p1(0)
);
\INFERRED_GEN.cnt_i[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA9A65AA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(4),
I2 => fifo_Read,
I3 => \^q\(0),
I4 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
O => addr_i_p1(1)
);
\INFERRED_GEN.cnt_i[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4FF0B00FFBF0040"
)
port map (
I0 => \^q\(4),
I1 => fifo_Read,
I2 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
I3 => \^q\(0),
I4 => \^q\(2),
I5 => \^q\(1),
O => addr_i_p1(2)
);
\INFERRED_GEN.cnt_i[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAA9AAAA"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(2),
I3 => \INFERRED_GEN.cnt_i[3]_i_2__0_n_0\,
I4 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
I5 => \^q\(0),
O => addr_i_p1(3)
);
\INFERRED_GEN.cnt_i[3]_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^q\(4),
I1 => fifo_Read,
O => \INFERRED_GEN.cnt_i[3]_i_2__0_n_0\
);
\INFERRED_GEN.cnt_i[4]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => reset_TX_FIFO_reg,
I1 => s_axi_aresetn,
O => \^ss\(0)
);
\INFERRED_GEN.cnt_i[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0FAFAF003F0F0"
)
port map (
I0 => \INFERRED_GEN.cnt_i[4]_i_3__0_n_0\,
I1 => fifo_Read,
I2 => \^q\(4),
I3 => \INFERRED_GEN.cnt_i[4]_i_4__0_n_0\,
I4 => \^q\(0),
I5 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
O => addr_i_p1(4)
);
\INFERRED_GEN.cnt_i[4]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => \^q\(3),
I1 => fifo_Read,
I2 => \^q\(2),
I3 => \^q\(1),
O => \INFERRED_GEN.cnt_i[4]_i_3__0_n_0\
);
\INFERRED_GEN.cnt_i[4]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^q\(2),
I1 => \^q\(1),
I2 => \^q\(3),
O => \INFERRED_GEN.cnt_i[4]_i_4__0_n_0\
);
\INFERRED_GEN.cnt_i_reg[0]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => addr_i_p1(0),
Q => \^q\(0),
S => \^ss\(0)
);
\INFERRED_GEN.cnt_i_reg[1]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => addr_i_p1(1),
Q => \^q\(1),
S => \^ss\(0)
);
\INFERRED_GEN.cnt_i_reg[2]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => addr_i_p1(2),
Q => \^q\(2),
S => \^ss\(0)
);
\INFERRED_GEN.cnt_i_reg[3]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => addr_i_p1(3),
Q => \^q\(3),
S => \^ss\(0)
);
\INFERRED_GEN.cnt_i_reg[4]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => addr_i_p1(4),
Q => \^q\(4),
S => \^ss\(0)
);
tx_Start_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0F02"
)
port map (
I0 => tx_Data_Enable_reg,
I1 => \^q\(4),
I2 => tx_DataBits,
I3 => tx_Start,
O => tx_Start0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_cntr_incr_decr_addn_f_2 is
port (
SS : out STD_LOGIC_VECTOR ( 0 to 0 );
fifo_full_p1 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
Interrupt0 : out STD_LOGIC;
reset_RX_FIFO_reg : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : in STD_LOGIC;
Bus_RNW_reg_reg : in STD_LOGIC;
fifo_Write : in STD_LOGIC;
FIFO_Full_reg : in STD_LOGIC;
valid_rx : in STD_LOGIC;
rx_Data_Present_Pre : in STD_LOGIC;
enable_interrupts : in STD_LOGIC;
\INFERRED_GEN.cnt_i_reg[4]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
tx_Buffer_Empty_Pre : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_cntr_incr_decr_addn_f_2 : entity is "cntr_incr_decr_addn_f";
end system_axi_uartlite_0_0_cntr_incr_decr_addn_f_2;
architecture STRUCTURE of system_axi_uartlite_0_0_cntr_incr_decr_addn_f_2 is
signal FIFO_Full_i_2_n_0 : STD_LOGIC;
signal \INFERRED_GEN.cnt_i[4]_i_4_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.cnt_i[4]_i_5__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.cnt_i[4]_i_6_n_0\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^ss\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal addr_i_p1 : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of FIFO_Full_i_2 : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[2]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[4]_i_4\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[4]_i_5__0\ : label is "soft_lutpair17";
begin
Q(4 downto 0) <= \^q\(4 downto 0);
SS(0) <= \^ss\(0);
\FIFO_Full_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000009040000"
)
port map (
I0 => \INFERRED_GEN.cnt_i[4]_i_6_n_0\,
I1 => \^q\(0),
I2 => \^q\(4),
I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
I4 => \^q\(3),
I5 => FIFO_Full_i_2_n_0,
O => fifo_full_p1
);
FIFO_Full_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^q\(1),
I1 => \^q\(2),
O => FIFO_Full_i_2_n_0
);
\INFERRED_GEN.cnt_i[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F70808F7"
)
port map (
I0 => Bus_RNW_reg,
I1 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I2 => \^q\(4),
I3 => \INFERRED_GEN.cnt_i[4]_i_6_n_0\,
I4 => \^q\(0),
O => addr_i_p1(0)
);
\INFERRED_GEN.cnt_i[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAA6A5595AAAA"
)
port map (
I0 => \^q\(1),
I1 => Bus_RNW_reg,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I3 => \^q\(4),
I4 => \^q\(0),
I5 => \INFERRED_GEN.cnt_i[4]_i_6_n_0\,
O => addr_i_p1(1)
);
\INFERRED_GEN.cnt_i[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE017F80"
)
port map (
I0 => \^q\(0),
I1 => Bus_RNW_reg_reg,
I2 => \^q\(1),
I3 => \^q\(2),
I4 => \INFERRED_GEN.cnt_i[4]_i_6_n_0\,
O => addr_i_p1(2)
);
\INFERRED_GEN.cnt_i[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0E178F0F0F0"
)
port map (
I0 => \^q\(0),
I1 => Bus_RNW_reg_reg,
I2 => \^q\(3),
I3 => \^q\(1),
I4 => \^q\(2),
I5 => \INFERRED_GEN.cnt_i[4]_i_6_n_0\,
O => addr_i_p1(3)
);
\INFERRED_GEN.cnt_i[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => reset_RX_FIFO_reg,
I1 => s_axi_aresetn,
O => \^ss\(0)
);
\INFERRED_GEN.cnt_i[4]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F4F4F00AF0F0"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
I1 => \INFERRED_GEN.cnt_i[4]_i_4_n_0\,
I2 => \^q\(4),
I3 => \INFERRED_GEN.cnt_i[4]_i_5__0_n_0\,
I4 => \^q\(0),
I5 => \INFERRED_GEN.cnt_i[4]_i_6_n_0\,
O => addr_i_p1(4)
);
\INFERRED_GEN.cnt_i[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(2),
I1 => \^q\(1),
I2 => \^q\(3),
O => \INFERRED_GEN.cnt_i[4]_i_4_n_0\
);
\INFERRED_GEN.cnt_i[4]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^q\(2),
I1 => \^q\(1),
I2 => \^q\(3),
O => \INFERRED_GEN.cnt_i[4]_i_5__0_n_0\
);
\INFERRED_GEN.cnt_i[4]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => fifo_Write,
I1 => FIFO_Full_reg,
I2 => valid_rx,
O => \INFERRED_GEN.cnt_i[4]_i_6_n_0\
);
\INFERRED_GEN.cnt_i_reg[0]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => addr_i_p1(0),
Q => \^q\(0),
S => \^ss\(0)
);
\INFERRED_GEN.cnt_i_reg[1]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => addr_i_p1(1),
Q => \^q\(1),
S => \^ss\(0)
);
\INFERRED_GEN.cnt_i_reg[2]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => addr_i_p1(2),
Q => \^q\(2),
S => \^ss\(0)
);
\INFERRED_GEN.cnt_i_reg[3]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => addr_i_p1(3),
Q => \^q\(3),
S => \^ss\(0)
);
\INFERRED_GEN.cnt_i_reg[4]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => addr_i_p1(4),
Q => \^q\(4),
S => \^ss\(0)
);
Interrupt_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"1010F010"
)
port map (
I0 => rx_Data_Present_Pre,
I1 => \^q\(4),
I2 => enable_interrupts,
I3 => \INFERRED_GEN.cnt_i_reg[4]_0\(0),
I4 => tx_Buffer_Empty_Pre,
O => Interrupt0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_dynshreg_f is
port (
mux_Out : out STD_LOGIC;
p_4_in : in STD_LOGIC;
\mux_sel_reg[2]\ : in STD_LOGIC;
\mux_sel_reg[0]\ : in STD_LOGIC;
fifo_wr : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_dynshreg_f : entity is "dynshreg_f";
end system_axi_uartlite_0_0_dynshreg_f;
architecture STRUCTURE of system_axi_uartlite_0_0_dynshreg_f is
signal fifo_DOut : STD_LOGIC_VECTOR ( 0 to 7 );
signal serial_Data_i_2_n_0 : STD_LOGIC;
signal serial_Data_i_3_n_0 : STD_LOGIC;
signal serial_Data_i_4_n_0 : STD_LOGIC;
signal serial_Data_i_5_n_0 : STD_LOGIC;
attribute srl_bus_name : string;
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][0]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name : string;
attribute srl_name of \INFERRED_GEN.data_reg[15][0]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][0]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][1]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][1]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][1]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][2]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][2]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][2]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][3]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][3]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][3]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][4]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][4]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][5]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][5]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][5]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][6]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][6]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][6]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][7]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][7]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][7]_srl16 ";
begin
\INFERRED_GEN.data_reg[15][0]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => s_axi_wdata(0),
Q => fifo_DOut(7)
);
\INFERRED_GEN.data_reg[15][1]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => s_axi_wdata(1),
Q => fifo_DOut(6)
);
\INFERRED_GEN.data_reg[15][2]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => s_axi_wdata(2),
Q => fifo_DOut(5)
);
\INFERRED_GEN.data_reg[15][3]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => s_axi_wdata(3),
Q => fifo_DOut(4)
);
\INFERRED_GEN.data_reg[15][4]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => s_axi_wdata(4),
Q => fifo_DOut(3)
);
\INFERRED_GEN.data_reg[15][5]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => s_axi_wdata(5),
Q => fifo_DOut(2)
);
\INFERRED_GEN.data_reg[15][6]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => s_axi_wdata(6),
Q => fifo_DOut(1)
);
\INFERRED_GEN.data_reg[15][7]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => s_axi_wdata(7),
Q => fifo_DOut(0)
);
serial_Data_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => serial_Data_i_2_n_0,
I1 => serial_Data_i_3_n_0,
I2 => serial_Data_i_4_n_0,
I3 => serial_Data_i_5_n_0,
O => mux_Out
);
serial_Data_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"44400040"
)
port map (
I0 => \mux_sel_reg[2]\,
I1 => p_4_in,
I2 => fifo_DOut(2),
I3 => \mux_sel_reg[0]\,
I4 => fifo_DOut(6),
O => serial_Data_i_2_n_0
);
serial_Data_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"88800080"
)
port map (
I0 => \mux_sel_reg[0]\,
I1 => \mux_sel_reg[2]\,
I2 => fifo_DOut(5),
I3 => p_4_in,
I4 => fifo_DOut(7),
O => serial_Data_i_3_n_0
);
serial_Data_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"44400040"
)
port map (
I0 => \mux_sel_reg[0]\,
I1 => \mux_sel_reg[2]\,
I2 => fifo_DOut(1),
I3 => p_4_in,
I4 => fifo_DOut(3),
O => serial_Data_i_4_n_0
);
serial_Data_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"000A000C"
)
port map (
I0 => fifo_DOut(4),
I1 => fifo_DOut(0),
I2 => p_4_in,
I3 => \mux_sel_reg[2]\,
I4 => \mux_sel_reg[0]\,
O => serial_Data_i_5_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_dynshreg_f_3 is
port (
\out\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
valid_rx : in STD_LOGIC;
FIFO_Full_reg : in STD_LOGIC;
fifo_Write : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 0 to 7 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_dynshreg_f_3 : entity is "dynshreg_f";
end system_axi_uartlite_0_0_dynshreg_f_3;
architecture STRUCTURE of system_axi_uartlite_0_0_dynshreg_f_3 is
signal fifo_wr : STD_LOGIC;
attribute srl_bus_name : string;
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][0]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name : string;
attribute srl_name of \INFERRED_GEN.data_reg[15][0]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][0]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][1]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][1]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][1]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][2]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][2]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][2]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][3]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][3]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][3]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][4]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][4]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][5]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][5]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][5]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][6]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][6]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][6]_srl16 ";
attribute srl_bus_name of \INFERRED_GEN.data_reg[15][7]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] ";
attribute srl_name of \INFERRED_GEN.data_reg[15][7]_srl16\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][7]_srl16 ";
begin
\INFERRED_GEN.data_reg[15][0]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => \in\(7),
Q => \out\(0)
);
\INFERRED_GEN.data_reg[15][0]_srl16_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => valid_rx,
I1 => FIFO_Full_reg,
I2 => fifo_Write,
O => fifo_wr
);
\INFERRED_GEN.data_reg[15][1]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => \in\(6),
Q => \out\(1)
);
\INFERRED_GEN.data_reg[15][2]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => \in\(5),
Q => \out\(2)
);
\INFERRED_GEN.data_reg[15][3]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => \in\(4),
Q => \out\(3)
);
\INFERRED_GEN.data_reg[15][4]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => \in\(3),
Q => \out\(4)
);
\INFERRED_GEN.data_reg[15][5]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => \in\(2),
Q => \out\(5)
);
\INFERRED_GEN.data_reg[15][6]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => \in\(1),
Q => \out\(6)
);
\INFERRED_GEN.data_reg[15][7]_srl16\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => Q(0),
A1 => Q(1),
A2 => Q(2),
A3 => Q(3),
CE => fifo_wr,
CLK => s_axi_aclk,
D => \in\(0),
Q => \out\(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_dynshreg_i_f is
port (
p_20_out : out STD_LOGIC;
\SERIAL_TO_PARALLEL[2].fifo_din_reg[2]\ : out STD_LOGIC;
p_17_out : out STD_LOGIC;
p_14_out : out STD_LOGIC;
p_11_out : out STD_LOGIC;
p_8_out : out STD_LOGIC;
p_5_out : out STD_LOGIC;
p_2_out : out STD_LOGIC;
status_reg_reg0 : out STD_LOGIC;
fifo_Write0 : out STD_LOGIC;
stop_Bit_Position_reg : out STD_LOGIC;
frame_err_ocrd_reg : out STD_LOGIC;
running_reg : out STD_LOGIC;
en_16x_Baud : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 0 to 7 );
start_Edge_Detected : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
stop_Bit_Position_reg_0 : in STD_LOGIC;
scndry_out : in STD_LOGIC;
clr_Status : in STD_LOGIC;
status_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
valid_rx : in STD_LOGIC;
frame_err_ocrd : in STD_LOGIC;
running_reg_0 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_dynshreg_i_f : entity is "dynshreg_i_f";
end system_axi_uartlite_0_0_dynshreg_i_f;
architecture STRUCTURE of system_axi_uartlite_0_0_dynshreg_i_f is
signal \INFERRED_GEN.data_reg[14][0]_srl15_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.data_reg[15]\ : STD_LOGIC;
signal \^serial_to_parallel[2].fifo_din_reg[2]\ : STD_LOGIC;
signal recycle : STD_LOGIC;
signal \status_reg[1]_i_2_n_0\ : STD_LOGIC;
attribute srl_bus_name : string;
attribute srl_bus_name of \INFERRED_GEN.data_reg[14][0]_srl15\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN.data_reg[14] ";
attribute srl_name : string;
attribute srl_name of \INFERRED_GEN.data_reg[14][0]_srl15\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN.data_reg[14][0]_srl15 ";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[14][0]_srl15_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \SERIAL_TO_PARALLEL[8].fifo_din[8]_i_2\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of fifo_Write_i_1 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of frame_err_ocrd_i_1 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of running_i_1 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \status_reg[1]_i_2\ : label is "soft_lutpair15";
begin
\SERIAL_TO_PARALLEL[2].fifo_din_reg[2]\ <= \^serial_to_parallel[2].fifo_din_reg[2]\;
\INFERRED_GEN.data_reg[14][0]_srl15\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
CE => en_16x_Baud,
CLK => s_axi_aclk,
D => recycle,
Q => \INFERRED_GEN.data_reg[14][0]_srl15_n_0\
);
\INFERRED_GEN.data_reg[14][0]_srl15_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4440"
)
port map (
I0 => stop_Bit_Position_reg_0,
I1 => valid_rx,
I2 => \INFERRED_GEN.data_reg[15]\,
I3 => start_Edge_Detected,
O => recycle
);
\INFERRED_GEN.data_reg[15][0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => en_16x_Baud,
D => \INFERRED_GEN.data_reg[14][0]_srl15_n_0\,
Q => \INFERRED_GEN.data_reg[15]\,
R => '0'
);
\SERIAL_TO_PARALLEL[2].fifo_din[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \in\(1),
I1 => \in\(0),
I2 => start_Edge_Detected,
I3 => s_axi_aresetn,
I4 => \^serial_to_parallel[2].fifo_din_reg[2]\,
O => p_20_out
);
\SERIAL_TO_PARALLEL[3].fifo_din[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \in\(2),
I1 => \in\(1),
I2 => start_Edge_Detected,
I3 => s_axi_aresetn,
I4 => \^serial_to_parallel[2].fifo_din_reg[2]\,
O => p_17_out
);
\SERIAL_TO_PARALLEL[4].fifo_din[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \in\(3),
I1 => \in\(2),
I2 => start_Edge_Detected,
I3 => s_axi_aresetn,
I4 => \^serial_to_parallel[2].fifo_din_reg[2]\,
O => p_14_out
);
\SERIAL_TO_PARALLEL[5].fifo_din[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \in\(4),
I1 => \in\(3),
I2 => start_Edge_Detected,
I3 => s_axi_aresetn,
I4 => \^serial_to_parallel[2].fifo_din_reg[2]\,
O => p_11_out
);
\SERIAL_TO_PARALLEL[6].fifo_din[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \in\(5),
I1 => \in\(4),
I2 => start_Edge_Detected,
I3 => s_axi_aresetn,
I4 => \^serial_to_parallel[2].fifo_din_reg[2]\,
O => p_8_out
);
\SERIAL_TO_PARALLEL[7].fifo_din[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \in\(6),
I1 => \in\(5),
I2 => start_Edge_Detected,
I3 => s_axi_aresetn,
I4 => \^serial_to_parallel[2].fifo_din_reg[2]\,
O => p_5_out
);
\SERIAL_TO_PARALLEL[8].fifo_din[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \in\(7),
I1 => \in\(6),
I2 => start_Edge_Detected,
I3 => s_axi_aresetn,
I4 => \^serial_to_parallel[2].fifo_din_reg[2]\,
O => p_2_out
);
\SERIAL_TO_PARALLEL[8].fifo_din[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"F7"
)
port map (
I0 => en_16x_Baud,
I1 => \INFERRED_GEN.data_reg[15]\,
I2 => stop_Bit_Position_reg_0,
O => \^serial_to_parallel[2].fifo_din_reg[2]\
);
fifo_Write_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \INFERRED_GEN.data_reg[15]\,
I1 => en_16x_Baud,
I2 => stop_Bit_Position_reg_0,
I3 => scndry_out,
O => fifo_Write0
);
frame_err_ocrd_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00FF0080"
)
port map (
I0 => \INFERRED_GEN.data_reg[15]\,
I1 => en_16x_Baud,
I2 => stop_Bit_Position_reg_0,
I3 => scndry_out,
I4 => frame_err_ocrd,
O => frame_err_ocrd_reg
);
running_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFA0A0"
)
port map (
I0 => start_Edge_Detected,
I1 => \INFERRED_GEN.data_reg[15]\,
I2 => en_16x_Baud,
I3 => stop_Bit_Position_reg_0,
I4 => running_reg_0,
O => running_reg
);
\status_reg[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0F000200"
)
port map (
I0 => \status_reg[1]_i_2_n_0\,
I1 => scndry_out,
I2 => clr_Status,
I3 => s_axi_aresetn,
I4 => status_reg(0),
O => status_reg_reg0
);
\status_reg[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => stop_Bit_Position_reg_0,
I1 => en_16x_Baud,
I2 => \INFERRED_GEN.data_reg[15]\,
O => \status_reg[1]_i_2_n_0\
);
stop_Bit_Position_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2CCC"
)
port map (
I0 => \in\(7),
I1 => stop_Bit_Position_reg_0,
I2 => en_16x_Baud,
I3 => \INFERRED_GEN.data_reg[15]\,
O => stop_Bit_Position_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_uartlite_0_0_dynshreg_i_f__parameterized0\ is
port (
tx_Data_Enable_reg : out STD_LOGIC;
en_16x_Baud : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
tx_Data_Enable_reg_0 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_uartlite_0_0_dynshreg_i_f__parameterized0\ : entity is "dynshreg_i_f";
end \system_axi_uartlite_0_0_dynshreg_i_f__parameterized0\;
architecture STRUCTURE of \system_axi_uartlite_0_0_dynshreg_i_f__parameterized0\ is
signal \INFERRED_GEN.data_reg[14][0]_srl15_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.data_reg_n_0_[15][0]\ : STD_LOGIC;
attribute srl_bus_name : string;
attribute srl_bus_name of \INFERRED_GEN.data_reg[14][0]_srl15\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN.data_reg[14] ";
attribute srl_name : string;
attribute srl_name of \INFERRED_GEN.data_reg[14][0]_srl15\ : label is "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN.data_reg[14][0]_srl15 ";
begin
\INFERRED_GEN.data_reg[14][0]_srl15\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0001"
)
port map (
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
CE => en_16x_Baud,
CLK => s_axi_aclk,
D => \INFERRED_GEN.data_reg_n_0_[15][0]\,
Q => \INFERRED_GEN.data_reg[14][0]_srl15_n_0\
);
\INFERRED_GEN.data_reg[15][0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => en_16x_Baud,
D => \INFERRED_GEN.data_reg[14][0]_srl15_n_0\,
Q => \INFERRED_GEN.data_reg_n_0_[15][0]\,
R => '0'
);
tx_Data_Enable_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => \INFERRED_GEN.data_reg_n_0_[15][0]\,
I1 => tx_Data_Enable_reg_0,
I2 => en_16x_Baud,
O => tx_Data_Enable_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_pselect_f is
port (
ce_expnd_i_3 : out STD_LOGIC;
\bus2ip_addr_i_reg[2]\ : in STD_LOGIC;
start2 : in STD_LOGIC;
\bus2ip_addr_i_reg[3]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_pselect_f : entity is "pselect_f";
end system_axi_uartlite_0_0_pselect_f;
architecture STRUCTURE of system_axi_uartlite_0_0_pselect_f is
begin
CS: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \bus2ip_addr_i_reg[2]\,
I1 => start2,
I2 => \bus2ip_addr_i_reg[3]\,
O => ce_expnd_i_3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_uartlite_0_0_pselect_f__parameterized1\ is
port (
ce_expnd_i_1 : out STD_LOGIC;
\bus2ip_addr_i_reg[3]\ : in STD_LOGIC;
start2 : in STD_LOGIC;
\bus2ip_addr_i_reg[2]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_uartlite_0_0_pselect_f__parameterized1\ : entity is "pselect_f";
end \system_axi_uartlite_0_0_pselect_f__parameterized1\;
architecture STRUCTURE of \system_axi_uartlite_0_0_pselect_f__parameterized1\ is
begin
CS: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \bus2ip_addr_i_reg[3]\,
I1 => start2,
I2 => \bus2ip_addr_i_reg[2]\,
O => ce_expnd_i_1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_address_decoder is
port (
tx_Buffer_Empty_Pre_reg : out STD_LOGIC;
\s_axi_rresp_i_reg[1]\ : out STD_LOGIC;
enable_interrupts_reg : out STD_LOGIC;
ip2bus_error : out STD_LOGIC;
fifo_wr : out STD_LOGIC;
\INFERRED_GEN.cnt_i_reg[2]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
\INFERRED_GEN.cnt_i_reg[2]_0\ : out STD_LOGIC;
\state_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arready : out STD_LOGIC;
FIFO_Full_reg : out STD_LOGIC;
reset_TX_FIFO : out STD_LOGIC;
reset_RX_FIFO : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bus2ip_rdce : out STD_LOGIC_VECTOR ( 0 to 0 );
enable_interrupts_reg_0 : out STD_LOGIC;
tx_Buffer_Empty_Pre_reg_0 : out STD_LOGIC;
s_axi_rvalid_i_reg : out STD_LOGIC;
s_axi_bvalid_i_reg : out STD_LOGIC;
\s_axi_bresp_i_reg[1]\ : out STD_LOGIC;
rx_Data_Present_Pre_reg : out STD_LOGIC;
start2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
tx_Buffer_Full : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
rx_Buffer_Full : in STD_LOGIC;
\INFERRED_GEN.cnt_i_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
enable_interrupts : in STD_LOGIC;
status_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[1]_0\ : in STD_LOGIC;
\state_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[0]\ : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_rvalid_i_reg_0 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_bvalid_i_reg_0 : in STD_LOGIC;
s_axi_bresp : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw_i : in STD_LOGIC;
\bus2ip_addr_i_reg[3]\ : in STD_LOGIC;
\bus2ip_addr_i_reg[2]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_address_decoder : entity is "address_decoder";
end system_axi_uartlite_0_0_address_decoder;
architecture STRUCTURE of system_axi_uartlite_0_0_address_decoder is
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : STD_LOGIC;
signal ce_expnd_i_0 : STD_LOGIC;
signal ce_expnd_i_1 : STD_LOGIC;
signal ce_expnd_i_2 : STD_LOGIC;
signal ce_expnd_i_3 : STD_LOGIC;
signal cs_ce_clr : STD_LOGIC;
signal \^enable_interrupts_reg\ : STD_LOGIC;
signal \^ip2bus_error\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal \^s_axi_rresp_i_reg[1]\ : STD_LOGIC;
signal \^tx_buffer_empty_pre_reg\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of Bus_RNW_reg_i_1 : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[3]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[4]_i_3\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \INFERRED_GEN.cnt_i[4]_i_5\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \INFERRED_GEN.data_reg[15][0]_srl16_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of clr_Status_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of enable_interrupts_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of reset_RX_FIFO_i_1 : label is "soft_lutpair7";
attribute SOFT_HLUTNM of reset_TX_FIFO_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of s_axi_arready_INST_0 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \s_axi_rdata_i[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \s_axi_rdata_i[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \s_axi_rdata_i[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_axi_rresp_i[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of s_axi_wready_INST_0 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of tx_Buffer_Empty_Pre_i_1 : label is "soft_lutpair6";
begin
enable_interrupts_reg <= \^enable_interrupts_reg\;
ip2bus_error <= \^ip2bus_error\;
s_axi_arready <= \^s_axi_arready\;
s_axi_awready <= \^s_axi_awready\;
\s_axi_rresp_i_reg[1]\ <= \^s_axi_rresp_i_reg[1]\;
tx_Buffer_Empty_Pre_reg <= \^tx_buffer_empty_pre_reg\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => bus2ip_rnw_i,
I1 => start2,
I2 => \^enable_interrupts_reg\,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => \^enable_interrupts_reg\,
R => '0'
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => ce_expnd_i_3,
Q => \^s_axi_rresp_i_reg[1]\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => start2,
I1 => \bus2ip_addr_i_reg[2]\,
I2 => \bus2ip_addr_i_reg[3]\,
O => ce_expnd_i_2
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => ce_expnd_i_2,
Q => \^tx_buffer_empty_pre_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => ce_expnd_i_1,
Q => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFEFFFF"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I1 => \^tx_buffer_empty_pre_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I3 => \^s_axi_rresp_i_reg[1]\,
I4 => s_axi_aresetn,
O => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \bus2ip_addr_i_reg[3]\,
I1 => start2,
I2 => \bus2ip_addr_i_reg[2]\,
O => ce_expnd_i_0
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => ce_expnd_i_0,
Q => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
R => cs_ce_clr
);
\INFERRED_GEN.cnt_i[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"F7"
)
port map (
I0 => \^enable_interrupts_reg\,
I1 => \^s_axi_rresp_i_reg[1]\,
I2 => Q(0),
O => \INFERRED_GEN.cnt_i_reg[2]_0\
);
\INFERRED_GEN.cnt_i[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^s_axi_rresp_i_reg[1]\,
I1 => \^enable_interrupts_reg\,
O => FIFO_Full_reg
);
\INFERRED_GEN.cnt_i[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \^tx_buffer_empty_pre_reg\,
I1 => \^enable_interrupts_reg\,
I2 => tx_Buffer_Full,
O => \INFERRED_GEN.cnt_i_reg[2]\
);
\INFERRED_GEN.data_reg[15][0]_srl16_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => tx_Buffer_Full,
I1 => \^enable_interrupts_reg\,
I2 => \^tx_buffer_empty_pre_reg\,
O => fifo_wr
);
\MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.system_axi_uartlite_0_0_pselect_f
port map (
\bus2ip_addr_i_reg[2]\ => \bus2ip_addr_i_reg[2]\,
\bus2ip_addr_i_reg[3]\ => \bus2ip_addr_i_reg[3]\,
ce_expnd_i_3 => ce_expnd_i_3,
start2 => start2
);
\MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_uartlite_0_0_pselect_f__parameterized1\
port map (
\bus2ip_addr_i_reg[2]\ => \bus2ip_addr_i_reg[2]\,
\bus2ip_addr_i_reg[3]\ => \bus2ip_addr_i_reg[3]\,
ce_expnd_i_1 => ce_expnd_i_1,
start2 => start2
);
clr_Status_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I1 => \^enable_interrupts_reg\,
O => bus2ip_rdce(0)
);
enable_interrupts_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(2),
I1 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I2 => \^enable_interrupts_reg\,
I3 => enable_interrupts,
O => enable_interrupts_reg_0
);
reset_RX_FIFO_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^enable_interrupts_reg\,
I1 => s_axi_wdata(1),
I2 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
O => reset_RX_FIFO
);
reset_TX_FIFO_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^enable_interrupts_reg\,
I1 => s_axi_wdata(0),
I2 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
O => reset_TX_FIFO
);
rx_Data_Present_Pre_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"002A"
)
port map (
I0 => s_axi_aresetn,
I1 => \^s_axi_rresp_i_reg[1]\,
I2 => \^enable_interrupts_reg\,
I3 => Q(0),
O => rx_Data_Present_Pre_reg
);
s_axi_arready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"F0F0F0E0"
)
port map (
I0 => \^s_axi_rresp_i_reg[1]\,
I1 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I2 => \^enable_interrupts_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I4 => \^tx_buffer_empty_pre_reg\,
O => \^s_axi_arready\
);
\s_axi_bresp_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \^ip2bus_error\,
I1 => \state_reg[1]_1\(1),
I2 => \state_reg[1]_1\(0),
I3 => s_axi_bresp(0),
O => \s_axi_bresp_i_reg[1]\
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_awready\,
I1 => \state_reg[1]_1\(1),
I2 => \state_reg[1]_1\(0),
I3 => s_axi_bready,
I4 => s_axi_bvalid_i_reg_0,
O => s_axi_bvalid_i_reg
);
\s_axi_rdata_i[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5C005000"
)
port map (
I0 => Q(0),
I1 => \out\(0),
I2 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I3 => \^enable_interrupts_reg\,
I4 => \^s_axi_rresp_i_reg[1]\,
O => D(0)
);
\s_axi_rdata_i[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AC00A000"
)
port map (
I0 => rx_Buffer_Full,
I1 => \out\(1),
I2 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I3 => \^enable_interrupts_reg\,
I4 => \^s_axi_rresp_i_reg[1]\,
O => D(1)
);
\s_axi_rdata_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AC00A000"
)
port map (
I0 => \INFERRED_GEN.cnt_i_reg[4]\(0),
I1 => \out\(2),
I2 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I3 => \^enable_interrupts_reg\,
I4 => \^s_axi_rresp_i_reg[1]\,
O => D(2)
);
\s_axi_rdata_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AC00A000"
)
port map (
I0 => tx_Buffer_Full,
I1 => \out\(3),
I2 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I3 => \^enable_interrupts_reg\,
I4 => \^s_axi_rresp_i_reg[1]\,
O => D(3)
);
\s_axi_rdata_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AC00A000"
)
port map (
I0 => enable_interrupts,
I1 => \out\(4),
I2 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I3 => \^enable_interrupts_reg\,
I4 => \^s_axi_rresp_i_reg[1]\,
O => D(4)
);
\s_axi_rdata_i[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AC00A000"
)
port map (
I0 => status_reg(0),
I1 => \out\(5),
I2 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I3 => \^enable_interrupts_reg\,
I4 => \^s_axi_rresp_i_reg[1]\,
O => D(5)
);
\s_axi_rdata_i[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AC00A000"
)
port map (
I0 => status_reg(1),
I1 => \out\(6),
I2 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I3 => \^enable_interrupts_reg\,
I4 => \^s_axi_rresp_i_reg[1]\,
O => D(6)
);
\s_axi_rdata_i[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \^s_axi_rresp_i_reg[1]\,
I1 => \^enable_interrupts_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I3 => \out\(7),
O => D(7)
);
\s_axi_rresp_i[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0880088"
)
port map (
I0 => \^tx_buffer_empty_pre_reg\,
I1 => tx_Buffer_Full,
I2 => \^s_axi_rresp_i_reg[1]\,
I3 => \^enable_interrupts_reg\,
I4 => Q(0),
O => \^ip2bus_error\
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => \state_reg[1]_1\(0),
I2 => \state_reg[1]_1\(1),
I3 => s_axi_rready,
I4 => s_axi_rvalid_i_reg_0,
O => s_axi_rvalid_i_reg
);
s_axi_wready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I1 => \^tx_buffer_empty_pre_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I3 => \^s_axi_rresp_i_reg[1]\,
I4 => \^enable_interrupts_reg\,
O => \^s_axi_awready\
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CEFFCEFC"
)
port map (
I0 => \^s_axi_awready\,
I1 => \state_reg[0]\,
I2 => \state_reg[1]_1\(0),
I3 => \state_reg[1]_1\(1),
I4 => s_axi_arvalid,
O => \state_reg[1]\(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CEFCCEFCCEFFCEFC"
)
port map (
I0 => \^s_axi_arready\,
I1 => \state_reg[1]_0\,
I2 => \state_reg[1]_1\(1),
I3 => \state_reg[1]_1\(0),
I4 => s_axi_wvalid,
I5 => s_axi_arvalid,
O => \state_reg[1]\(1)
);
tx_Buffer_Empty_Pre_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"8088"
)
port map (
I0 => \INFERRED_GEN.cnt_i_reg[4]\(0),
I1 => s_axi_aresetn,
I2 => \^enable_interrupts_reg\,
I3 => \^tx_buffer_empty_pre_reg\,
O => tx_Buffer_Empty_Pre_reg_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_srl_fifo_rbu_f is
port (
tx_Buffer_Full : out STD_LOGIC;
mux_Out : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
tx_Start0 : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
p_4_in : in STD_LOGIC;
\mux_sel_reg[2]\ : in STD_LOGIC;
\mux_sel_reg[0]\ : in STD_LOGIC;
reset_TX_FIFO_reg : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
fifo_Read : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
tx_Data_Enable_reg : in STD_LOGIC;
tx_DataBits : in STD_LOGIC;
tx_Start : in STD_LOGIC;
fifo_wr : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_srl_fifo_rbu_f : entity is "srl_fifo_rbu_f";
end system_axi_uartlite_0_0_srl_fifo_rbu_f;
architecture STRUCTURE of system_axi_uartlite_0_0_srl_fifo_rbu_f is
signal CNTR_INCR_DECR_ADDN_F_I_n_2 : STD_LOGIC;
signal CNTR_INCR_DECR_ADDN_F_I_n_3 : STD_LOGIC;
signal CNTR_INCR_DECR_ADDN_F_I_n_4 : STD_LOGIC;
signal CNTR_INCR_DECR_ADDN_F_I_n_5 : STD_LOGIC;
signal TX_FIFO_Reset : STD_LOGIC;
signal fifo_full_p1 : STD_LOGIC;
signal \^tx_buffer_full\ : STD_LOGIC;
begin
tx_Buffer_Full <= \^tx_buffer_full\;
CNTR_INCR_DECR_ADDN_F_I: entity work.system_axi_uartlite_0_0_cntr_incr_decr_addn_f
port map (
Bus_RNW_reg => Bus_RNW_reg,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
Q(4) => Q(0),
Q(3) => CNTR_INCR_DECR_ADDN_F_I_n_2,
Q(2) => CNTR_INCR_DECR_ADDN_F_I_n_3,
Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_4,
Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_5,
SS(0) => TX_FIFO_Reset,
fifo_Read => fifo_Read,
fifo_full_p1 => fifo_full_p1,
reset_TX_FIFO_reg => reset_TX_FIFO_reg,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
tx_Buffer_Full => \^tx_buffer_full\,
tx_DataBits => tx_DataBits,
tx_Data_Enable_reg => tx_Data_Enable_reg,
tx_Start => tx_Start,
tx_Start0 => tx_Start0
);
DYNSHREG_F_I: entity work.system_axi_uartlite_0_0_dynshreg_f
port map (
Q(3) => CNTR_INCR_DECR_ADDN_F_I_n_2,
Q(2) => CNTR_INCR_DECR_ADDN_F_I_n_3,
Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_4,
Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_5,
fifo_wr => fifo_wr,
mux_Out => mux_Out,
\mux_sel_reg[0]\ => \mux_sel_reg[0]\,
\mux_sel_reg[2]\ => \mux_sel_reg[2]\,
p_4_in => p_4_in,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0)
);
FIFO_Full_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => fifo_full_p1,
Q => \^tx_buffer_full\,
R => TX_FIFO_Reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_srl_fifo_rbu_f_1 is
port (
\status_reg_reg[2]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
Interrupt0 : out STD_LOGIC;
\status_reg_reg[2]_0\ : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
reset_RX_FIFO_reg : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : in STD_LOGIC;
Bus_RNW_reg_reg : in STD_LOGIC;
valid_rx : in STD_LOGIC;
fifo_Write : in STD_LOGIC;
rx_Data_Present_Pre : in STD_LOGIC;
enable_interrupts : in STD_LOGIC;
\INFERRED_GEN.cnt_i_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
tx_Buffer_Empty_Pre : in STD_LOGIC;
status_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
clr_Status : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 0 to 7 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_srl_fifo_rbu_f_1 : entity is "srl_fifo_rbu_f";
end system_axi_uartlite_0_0_srl_fifo_rbu_f_1;
architecture STRUCTURE of system_axi_uartlite_0_0_srl_fifo_rbu_f_1 is
signal CNTR_INCR_DECR_ADDN_F_I_n_3 : STD_LOGIC;
signal CNTR_INCR_DECR_ADDN_F_I_n_4 : STD_LOGIC;
signal CNTR_INCR_DECR_ADDN_F_I_n_5 : STD_LOGIC;
signal CNTR_INCR_DECR_ADDN_F_I_n_6 : STD_LOGIC;
signal RX_FIFO_Reset : STD_LOGIC;
signal fifo_full_p1 : STD_LOGIC;
signal \^status_reg_reg[2]\ : STD_LOGIC;
begin
\status_reg_reg[2]\ <= \^status_reg_reg[2]\;
CNTR_INCR_DECR_ADDN_F_I: entity work.system_axi_uartlite_0_0_cntr_incr_decr_addn_f_2
port map (
Bus_RNW_reg => Bus_RNW_reg,
Bus_RNW_reg_reg => Bus_RNW_reg_reg,
FIFO_Full_reg => \^status_reg_reg[2]\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
\INFERRED_GEN.cnt_i_reg[4]_0\(0) => \INFERRED_GEN.cnt_i_reg[4]\(0),
Interrupt0 => Interrupt0,
Q(4) => Q(0),
Q(3) => CNTR_INCR_DECR_ADDN_F_I_n_3,
Q(2) => CNTR_INCR_DECR_ADDN_F_I_n_4,
Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_5,
Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_6,
SS(0) => RX_FIFO_Reset,
enable_interrupts => enable_interrupts,
fifo_Write => fifo_Write,
fifo_full_p1 => fifo_full_p1,
reset_RX_FIFO_reg => reset_RX_FIFO_reg,
rx_Data_Present_Pre => rx_Data_Present_Pre,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
tx_Buffer_Empty_Pre => tx_Buffer_Empty_Pre,
valid_rx => valid_rx
);
DYNSHREG_F_I: entity work.system_axi_uartlite_0_0_dynshreg_f_3
port map (
FIFO_Full_reg => \^status_reg_reg[2]\,
Q(3) => CNTR_INCR_DECR_ADDN_F_I_n_3,
Q(2) => CNTR_INCR_DECR_ADDN_F_I_n_4,
Q(1) => CNTR_INCR_DECR_ADDN_F_I_n_5,
Q(0) => CNTR_INCR_DECR_ADDN_F_I_n_6,
fifo_Write => fifo_Write,
\in\(0 to 7) => \in\(0 to 7),
\out\(7 downto 0) => \out\(7 downto 0),
s_axi_aclk => s_axi_aclk,
valid_rx => valid_rx
);
FIFO_Full_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => fifo_full_p1,
Q => \^status_reg_reg[2]\,
R => RX_FIFO_Reset
);
\status_reg[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000EA00"
)
port map (
I0 => status_reg(0),
I1 => fifo_Write,
I2 => \^status_reg_reg[2]\,
I3 => s_axi_aresetn,
I4 => clr_Status,
O => \status_reg_reg[2]_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_slave_attachment is
port (
tx_Buffer_Empty_Pre_reg : out STD_LOGIC;
\s_axi_rresp_i_reg[1]_0\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
enable_interrupts_reg : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
fifo_wr : out STD_LOGIC;
\INFERRED_GEN.cnt_i_reg[2]\ : out STD_LOGIC;
\INFERRED_GEN.cnt_i_reg[2]_0\ : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
FIFO_Full_reg : out STD_LOGIC;
reset_TX_FIFO : out STD_LOGIC;
reset_RX_FIFO : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bus2ip_rdce : out STD_LOGIC_VECTOR ( 0 to 0 );
enable_interrupts_reg_0 : out STD_LOGIC;
tx_Buffer_Empty_Pre_reg_0 : out STD_LOGIC;
rx_Data_Present_Pre_reg : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
tx_Buffer_Full : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
rx_Buffer_Full : in STD_LOGIC;
\INFERRED_GEN.cnt_i_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
enable_interrupts : in STD_LOGIC;
status_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_slave_attachment : entity is "slave_attachment";
end system_axi_uartlite_0_0_slave_attachment;
architecture STRUCTURE of system_axi_uartlite_0_0_slave_attachment is
signal I_DECODER_n_15 : STD_LOGIC;
signal I_DECODER_n_16 : STD_LOGIC;
signal I_DECODER_n_25 : STD_LOGIC;
signal I_DECODER_n_26 : STD_LOGIC;
signal I_DECODER_n_27 : STD_LOGIC;
signal SIn_DBus : STD_LOGIC_VECTOR ( 0 to 7 );
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_2_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i_reg_n_0_[2]\ : STD_LOGIC;
signal \bus2ip_addr_i_reg_n_0_[3]\ : STD_LOGIC;
signal bus2ip_rnw_i : STD_LOGIC;
signal bus2ip_rnw_i_i_1_n_0 : STD_LOGIC;
signal ip2bus_error : STD_LOGIC;
signal rst : STD_LOGIC;
signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_rdata_i : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state[0]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bus2ip_addr_i[3]_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair9";
begin
s_axi_bresp(0) <= \^s_axi_bresp\(0);
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
I_DECODER: entity work.system_axi_uartlite_0_0_address_decoder
port map (
D(7) => SIn_DBus(0),
D(6) => SIn_DBus(1),
D(5) => SIn_DBus(2),
D(4) => SIn_DBus(3),
D(3) => SIn_DBus(4),
D(2) => SIn_DBus(5),
D(1) => SIn_DBus(6),
D(0) => SIn_DBus(7),
FIFO_Full_reg => FIFO_Full_reg,
\INFERRED_GEN.cnt_i_reg[2]\ => \INFERRED_GEN.cnt_i_reg[2]\,
\INFERRED_GEN.cnt_i_reg[2]_0\ => \INFERRED_GEN.cnt_i_reg[2]_0\,
\INFERRED_GEN.cnt_i_reg[4]\(0) => \INFERRED_GEN.cnt_i_reg[4]\(0),
Q(0) => Q(0),
\bus2ip_addr_i_reg[2]\ => \bus2ip_addr_i_reg_n_0_[2]\,
\bus2ip_addr_i_reg[3]\ => \bus2ip_addr_i_reg_n_0_[3]\,
bus2ip_rdce(0) => bus2ip_rdce(0),
bus2ip_rnw_i => bus2ip_rnw_i,
enable_interrupts => enable_interrupts,
enable_interrupts_reg => enable_interrupts_reg,
enable_interrupts_reg_0 => enable_interrupts_reg_0,
fifo_wr => fifo_wr,
ip2bus_error => ip2bus_error,
\out\(7 downto 0) => \out\(7 downto 0),
reset_RX_FIFO => reset_RX_FIFO,
reset_TX_FIFO => reset_TX_FIFO,
rx_Buffer_Full => rx_Buffer_Full,
rx_Data_Present_Pre_reg => rx_Data_Present_Pre_reg,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awready => s_axi_awready,
s_axi_bready => s_axi_bready,
s_axi_bresp(0) => \^s_axi_bresp\(0),
\s_axi_bresp_i_reg[1]\ => I_DECODER_n_27,
s_axi_bvalid_i_reg => I_DECODER_n_26,
s_axi_bvalid_i_reg_0 => \^s_axi_bvalid\,
s_axi_rready => s_axi_rready,
\s_axi_rresp_i_reg[1]\ => \s_axi_rresp_i_reg[1]_0\,
s_axi_rvalid_i_reg => I_DECODER_n_25,
s_axi_rvalid_i_reg_0 => \^s_axi_rvalid\,
s_axi_wdata(2 downto 0) => s_axi_wdata(2 downto 0),
s_axi_wvalid => \state[1]_i_3_n_0\,
start2 => start2,
\state_reg[0]\ => \state[0]_i_2_n_0\,
\state_reg[1]\(1) => I_DECODER_n_15,
\state_reg[1]\(0) => I_DECODER_n_16,
\state_reg[1]_0\ => \state[1]_i_2_n_0\,
\state_reg[1]_1\(1 downto 0) => state(1 downto 0),
status_reg(1 downto 0) => status_reg(1 downto 0),
tx_Buffer_Empty_Pre_reg => tx_Buffer_Empty_Pre_reg,
tx_Buffer_Empty_Pre_reg_0 => tx_Buffer_Empty_Pre_reg_0,
tx_Buffer_Full => tx_Buffer_Full
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => s_axi_awaddr(0),
I1 => \bus2ip_addr_i[3]_i_2_n_0\,
I2 => s_axi_araddr(0),
I3 => start2_i_1_n_0,
I4 => \bus2ip_addr_i_reg_n_0_[2]\,
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => s_axi_awaddr(1),
I1 => \bus2ip_addr_i[3]_i_2_n_0\,
I2 => s_axi_araddr(1),
I3 => start2_i_1_n_0,
I4 => \bus2ip_addr_i_reg_n_0_[3]\,
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => state(1),
I1 => state(0),
I2 => s_axi_arvalid,
O => \bus2ip_addr_i[3]_i_2_n_0\
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => \bus2ip_addr_i_reg_n_0_[2]\,
R => rst
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => \bus2ip_addr_i_reg_n_0_[3]\,
R => rst
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF7000000F0"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(0),
I4 => state(1),
I5 => bus2ip_rnw_i,
O => bus2ip_rnw_i_i_1_n_0
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => bus2ip_rnw_i_i_1_n_0,
Q => bus2ip_rnw_i,
R => rst
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => bus2ip_reset,
Q => rst,
R => '0'
);
\s_axi_bresp_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_27,
Q => \^s_axi_bresp\(0),
R => rst
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_26,
Q => \^s_axi_bvalid\,
R => rst
);
\s_axi_rdata_i[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => s_axi_rdata_i
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => SIn_DBus(7),
Q => s_axi_rdata(0),
R => rst
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => SIn_DBus(6),
Q => s_axi_rdata(1),
R => rst
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => SIn_DBus(5),
Q => s_axi_rdata(2),
R => rst
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => SIn_DBus(4),
Q => s_axi_rdata(3),
R => rst
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => SIn_DBus(3),
Q => s_axi_rdata(4),
R => rst
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => SIn_DBus(2),
Q => s_axi_rdata(5),
R => rst
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => SIn_DBus(1),
Q => s_axi_rdata(6),
R => rst
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => SIn_DBus(0),
Q => s_axi_rdata(7),
R => rst
);
\s_axi_rresp_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => ip2bus_error,
Q => s_axi_rresp(0),
R => rst
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_25,
Q => \^s_axi_rvalid\,
R => rst
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(0),
I4 => state(1),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => rst
);
\state[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"002A2A2A"
)
port map (
I0 => state(0),
I1 => \^s_axi_rvalid\,
I2 => s_axi_rready,
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => \state[0]_i_2_n_0\
);
\state[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"002A2A2A"
)
port map (
I0 => state(1),
I1 => \^s_axi_rvalid\,
I2 => s_axi_rready,
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_16,
Q => state(0),
R => rst
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_15,
Q => state(1),
R => rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_srl_fifo_f is
port (
tx_Buffer_Full : out STD_LOGIC;
mux_Out : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
tx_Start0 : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
p_4_in : in STD_LOGIC;
\mux_sel_reg[2]\ : in STD_LOGIC;
\mux_sel_reg[0]\ : in STD_LOGIC;
reset_TX_FIFO_reg : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
fifo_Read : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
tx_Data_Enable_reg : in STD_LOGIC;
tx_DataBits : in STD_LOGIC;
tx_Start : in STD_LOGIC;
fifo_wr : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_srl_fifo_f : entity is "srl_fifo_f";
end system_axi_uartlite_0_0_srl_fifo_f;
architecture STRUCTURE of system_axi_uartlite_0_0_srl_fifo_f is
begin
I_SRL_FIFO_RBU_F: entity work.system_axi_uartlite_0_0_srl_fifo_rbu_f
port map (
Bus_RNW_reg => Bus_RNW_reg,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
Q(0) => Q(0),
fifo_Read => fifo_Read,
fifo_wr => fifo_wr,
mux_Out => mux_Out,
\mux_sel_reg[0]\ => \mux_sel_reg[0]\,
\mux_sel_reg[2]\ => \mux_sel_reg[2]\,
p_4_in => p_4_in,
reset_TX_FIFO_reg => reset_TX_FIFO_reg,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
tx_Buffer_Full => tx_Buffer_Full,
tx_DataBits => tx_DataBits,
tx_Data_Enable_reg => tx_Data_Enable_reg,
tx_Start => tx_Start,
tx_Start0 => tx_Start0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_srl_fifo_f_0 is
port (
\status_reg_reg[2]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
Interrupt0 : out STD_LOGIC;
\status_reg_reg[2]_0\ : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
reset_RX_FIFO_reg : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : in STD_LOGIC;
Bus_RNW_reg_reg : in STD_LOGIC;
valid_rx : in STD_LOGIC;
fifo_Write : in STD_LOGIC;
rx_Data_Present_Pre : in STD_LOGIC;
enable_interrupts : in STD_LOGIC;
\INFERRED_GEN.cnt_i_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
tx_Buffer_Empty_Pre : in STD_LOGIC;
status_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
clr_Status : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 0 to 7 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_srl_fifo_f_0 : entity is "srl_fifo_f";
end system_axi_uartlite_0_0_srl_fifo_f_0;
architecture STRUCTURE of system_axi_uartlite_0_0_srl_fifo_f_0 is
begin
I_SRL_FIFO_RBU_F: entity work.system_axi_uartlite_0_0_srl_fifo_rbu_f_1
port map (
Bus_RNW_reg => Bus_RNW_reg,
Bus_RNW_reg_reg => Bus_RNW_reg_reg,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
\INFERRED_GEN.cnt_i_reg[4]\(0) => \INFERRED_GEN.cnt_i_reg[4]\(0),
Interrupt0 => Interrupt0,
Q(0) => Q(0),
clr_Status => clr_Status,
enable_interrupts => enable_interrupts,
fifo_Write => fifo_Write,
\in\(0 to 7) => \in\(0 to 7),
\out\(7 downto 0) => \out\(7 downto 0),
reset_RX_FIFO_reg => reset_RX_FIFO_reg,
rx_Data_Present_Pre => rx_Data_Present_Pre,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
status_reg(0) => status_reg(0),
\status_reg_reg[2]\ => \status_reg_reg[2]\,
\status_reg_reg[2]_0\ => \status_reg_reg[2]_0\,
tx_Buffer_Empty_Pre => tx_Buffer_Empty_Pre,
valid_rx => valid_rx
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_axi_lite_ipif is
port (
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
Bus_RNW_reg : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
fifo_wr : out STD_LOGIC;
\INFERRED_GEN.cnt_i_reg[2]\ : out STD_LOGIC;
\INFERRED_GEN.cnt_i_reg[2]_0\ : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
FIFO_Full_reg : out STD_LOGIC;
reset_TX_FIFO : out STD_LOGIC;
reset_RX_FIFO : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bus2ip_rdce : out STD_LOGIC_VECTOR ( 0 to 0 );
enable_interrupts_reg : out STD_LOGIC;
tx_Buffer_Empty_Pre_reg : out STD_LOGIC;
rx_Data_Present_Pre_reg : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
tx_Buffer_Full : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
rx_Buffer_Full : in STD_LOGIC;
\INFERRED_GEN.cnt_i_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
enable_interrupts : in STD_LOGIC;
status_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_axi_lite_ipif : entity is "axi_lite_ipif";
end system_axi_uartlite_0_0_axi_lite_ipif;
architecture STRUCTURE of system_axi_uartlite_0_0_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.system_axi_uartlite_0_0_slave_attachment
port map (
FIFO_Full_reg => FIFO_Full_reg,
\INFERRED_GEN.cnt_i_reg[2]\ => \INFERRED_GEN.cnt_i_reg[2]\,
\INFERRED_GEN.cnt_i_reg[2]_0\ => \INFERRED_GEN.cnt_i_reg[2]_0\,
\INFERRED_GEN.cnt_i_reg[4]\(0) => \INFERRED_GEN.cnt_i_reg[4]\(0),
Q(0) => Q(0),
bus2ip_rdce(0) => bus2ip_rdce(0),
bus2ip_reset => bus2ip_reset,
enable_interrupts => enable_interrupts,
enable_interrupts_reg => Bus_RNW_reg,
enable_interrupts_reg_0 => enable_interrupts_reg,
fifo_wr => fifo_wr,
\out\(7 downto 0) => \out\(7 downto 0),
reset_RX_FIFO => reset_RX_FIFO,
reset_TX_FIFO => reset_TX_FIFO,
rx_Buffer_Full => rx_Buffer_Full,
rx_Data_Present_Pre_reg => rx_Data_Present_Pre_reg,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(1 downto 0) => s_axi_araddr(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(1 downto 0) => s_axi_awaddr(1 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(0) => s_axi_bresp(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(7 downto 0) => s_axi_rdata(7 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(0) => s_axi_rresp(0),
\s_axi_rresp_i_reg[1]_0\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(2 downto 0) => s_axi_wdata(2 downto 0),
s_axi_wvalid => s_axi_wvalid,
status_reg(1 downto 0) => status_reg(1 downto 0),
tx_Buffer_Empty_Pre_reg => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
tx_Buffer_Empty_Pre_reg_0 => tx_Buffer_Empty_Pre_reg,
tx_Buffer_Full => tx_Buffer_Full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_uartlite_rx is
port (
\status_reg_reg[2]\ : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
status_reg_reg0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
Interrupt0 : out STD_LOGIC;
\status_reg_reg[2]_0\ : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
en_16x_Baud : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
clr_Status : in STD_LOGIC;
status_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
reset_RX_FIFO_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : in STD_LOGIC;
Bus_RNW_reg_reg : in STD_LOGIC;
rx_Data_Present_Pre : in STD_LOGIC;
enable_interrupts : in STD_LOGIC;
\INFERRED_GEN.cnt_i_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
tx_Buffer_Empty_Pre : in STD_LOGIC;
rx : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_uartlite_rx : entity is "uartlite_rx";
end system_axi_uartlite_0_0_uartlite_rx;
architecture STRUCTURE of system_axi_uartlite_0_0_uartlite_rx is
signal DELAY_16_I_n_1 : STD_LOGIC;
signal DELAY_16_I_n_10 : STD_LOGIC;
signal DELAY_16_I_n_11 : STD_LOGIC;
signal DELAY_16_I_n_12 : STD_LOGIC;
signal RX_D2 : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal fifo_Write : STD_LOGIC;
signal fifo_Write0 : STD_LOGIC;
signal fifo_din : STD_LOGIC_VECTOR ( 1 to 8 );
signal frame_err_ocrd : STD_LOGIC;
signal p_11_out : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_17_out : STD_LOGIC;
signal p_20_out : STD_LOGIC;
signal p_26_out : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal running_reg_n_0 : STD_LOGIC;
signal rx_1 : STD_LOGIC;
signal rx_2 : STD_LOGIC;
signal rx_3 : STD_LOGIC;
signal rx_4 : STD_LOGIC;
signal rx_5 : STD_LOGIC;
signal rx_6 : STD_LOGIC;
signal rx_7 : STD_LOGIC;
signal rx_8 : STD_LOGIC;
signal rx_9 : STD_LOGIC;
signal start_Edge_Detected : STD_LOGIC;
signal start_Edge_Detected0 : STD_LOGIC;
signal start_Edge_Detected_i_2_n_0 : STD_LOGIC;
signal stop_Bit_Position_reg_n_0 : STD_LOGIC;
signal valid_rx : STD_LOGIC;
signal valid_rx_i_1_n_0 : STD_LOGIC;
begin
SR(0) <= \^sr\(0);
DELAY_16_I: entity work.system_axi_uartlite_0_0_dynshreg_i_f
port map (
\SERIAL_TO_PARALLEL[2].fifo_din_reg[2]\ => DELAY_16_I_n_1,
clr_Status => clr_Status,
en_16x_Baud => en_16x_Baud,
fifo_Write0 => fifo_Write0,
frame_err_ocrd => frame_err_ocrd,
frame_err_ocrd_reg => DELAY_16_I_n_11,
\in\(0 to 7) => fifo_din(1 to 8),
p_11_out => p_11_out,
p_14_out => p_14_out,
p_17_out => p_17_out,
p_20_out => p_20_out,
p_2_out => p_2_out,
p_5_out => p_5_out,
p_8_out => p_8_out,
running_reg => DELAY_16_I_n_12,
running_reg_0 => running_reg_n_0,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
scndry_out => RX_D2,
start_Edge_Detected => start_Edge_Detected,
status_reg(0) => status_reg(1),
status_reg_reg0 => status_reg_reg0,
stop_Bit_Position_reg => DELAY_16_I_n_10,
stop_Bit_Position_reg_0 => stop_Bit_Position_reg_n_0,
valid_rx => valid_rx
);
INPUT_DOUBLE_REGS3: entity work.system_axi_uartlite_0_0_cdc_sync
port map (
EN_16x_Baud_reg => DELAY_16_I_n_1,
\in\(0) => fifo_din(1),
p_26_out => p_26_out,
rx => rx,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
scndry_out => RX_D2,
start_Edge_Detected => start_Edge_Detected
);
Interrupt_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^sr\(0)
);
\SERIAL_TO_PARALLEL[1].fifo_din_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_26_out,
Q => fifo_din(1),
R => '0'
);
\SERIAL_TO_PARALLEL[2].fifo_din_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_20_out,
Q => fifo_din(2),
R => '0'
);
\SERIAL_TO_PARALLEL[3].fifo_din_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_17_out,
Q => fifo_din(3),
R => '0'
);
\SERIAL_TO_PARALLEL[4].fifo_din_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_14_out,
Q => fifo_din(4),
R => '0'
);
\SERIAL_TO_PARALLEL[5].fifo_din_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_11_out,
Q => fifo_din(5),
R => '0'
);
\SERIAL_TO_PARALLEL[6].fifo_din_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_8_out,
Q => fifo_din(6),
R => '0'
);
\SERIAL_TO_PARALLEL[7].fifo_din_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_5_out,
Q => fifo_din(7),
R => '0'
);
\SERIAL_TO_PARALLEL[8].fifo_din_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_2_out,
Q => fifo_din(8),
R => '0'
);
SRL_FIFO_I: entity work.system_axi_uartlite_0_0_srl_fifo_f_0
port map (
Bus_RNW_reg => Bus_RNW_reg,
Bus_RNW_reg_reg => Bus_RNW_reg_reg,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
\INFERRED_GEN.cnt_i_reg[4]\(0) => \INFERRED_GEN.cnt_i_reg[4]\(0),
Interrupt0 => Interrupt0,
Q(0) => Q(0),
clr_Status => clr_Status,
enable_interrupts => enable_interrupts,
fifo_Write => fifo_Write,
\in\(0 to 7) => fifo_din(1 to 8),
\out\(7 downto 0) => \out\(7 downto 0),
reset_RX_FIFO_reg => reset_RX_FIFO_reg,
rx_Data_Present_Pre => rx_Data_Present_Pre,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
status_reg(0) => status_reg(0),
\status_reg_reg[2]\ => \status_reg_reg[2]\,
\status_reg_reg[2]_0\ => \status_reg_reg[2]_0\,
tx_Buffer_Empty_Pre => tx_Buffer_Empty_Pre,
valid_rx => valid_rx
);
fifo_Write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => fifo_Write0,
Q => fifo_Write,
R => \^sr\(0)
);
frame_err_ocrd_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => DELAY_16_I_n_11,
Q => frame_err_ocrd,
R => \^sr\(0)
);
running_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => DELAY_16_I_n_12,
Q => running_reg_n_0,
R => \^sr\(0)
);
rx_1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => en_16x_Baud,
D => RX_D2,
Q => rx_1,
R => \^sr\(0)
);
rx_2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => en_16x_Baud,
D => rx_1,
Q => rx_2,
R => \^sr\(0)
);
rx_3_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => en_16x_Baud,
D => rx_2,
Q => rx_3,
R => \^sr\(0)
);
rx_4_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => en_16x_Baud,
D => rx_3,
Q => rx_4,
R => \^sr\(0)
);
rx_5_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => en_16x_Baud,
D => rx_4,
Q => rx_5,
R => \^sr\(0)
);
rx_6_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => en_16x_Baud,
D => rx_5,
Q => rx_6,
R => \^sr\(0)
);
rx_7_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => en_16x_Baud,
D => rx_6,
Q => rx_7,
R => \^sr\(0)
);
rx_8_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => en_16x_Baud,
D => rx_7,
Q => rx_8,
R => \^sr\(0)
);
rx_9_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => en_16x_Baud,
D => rx_8,
Q => rx_9,
R => \^sr\(0)
);
start_Edge_Detected_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000010"
)
port map (
I0 => rx_8,
I1 => rx_2,
I2 => start_Edge_Detected_i_2_n_0,
I3 => rx_3,
I4 => rx_1,
I5 => frame_err_ocrd,
O => start_Edge_Detected0
);
start_Edge_Detected_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000010"
)
port map (
I0 => rx_5,
I1 => rx_7,
I2 => rx_9,
I3 => running_reg_n_0,
I4 => rx_6,
I5 => rx_4,
O => start_Edge_Detected_i_2_n_0
);
start_Edge_Detected_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => en_16x_Baud,
D => start_Edge_Detected0,
Q => start_Edge_Detected,
R => \^sr\(0)
);
stop_Bit_Position_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => DELAY_16_I_n_10,
Q => stop_Bit_Position_reg_n_0,
R => \^sr\(0)
);
valid_rx_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => start_Edge_Detected,
I1 => fifo_Write,
I2 => valid_rx,
O => valid_rx_i_1_n_0
);
valid_rx_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => valid_rx_i_1_n_0,
Q => valid_rx,
R => \^sr\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_uartlite_tx is
port (
tx_Buffer_Full : out STD_LOGIC;
tx : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
en_16x_Baud : in STD_LOGIC;
reset_TX_FIFO_reg : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
fifo_wr : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_uartlite_tx : entity is "uartlite_tx";
end system_axi_uartlite_0_0_uartlite_tx;
architecture STRUCTURE of system_axi_uartlite_0_0_uartlite_tx is
signal MID_START_BIT_SRL16_I_n_0 : STD_LOGIC;
signal TX0 : STD_LOGIC;
signal fifo_Read : STD_LOGIC;
signal fifo_Read0 : STD_LOGIC;
signal mux_Out : STD_LOGIC;
signal \mux_sel[0]_i_1_n_0\ : STD_LOGIC;
signal \mux_sel[1]_i_1_n_0\ : STD_LOGIC;
signal \mux_sel[2]_i_1_n_0\ : STD_LOGIC;
signal \mux_sel_reg_n_0_[0]\ : STD_LOGIC;
signal \mux_sel_reg_n_0_[2]\ : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal serial_Data : STD_LOGIC;
signal tx_DataBits : STD_LOGIC;
signal tx_DataBits0 : STD_LOGIC;
signal tx_Data_Enable_reg_n_0 : STD_LOGIC;
signal tx_Start : STD_LOGIC;
signal tx_Start0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \mux_sel[0]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \mux_sel[1]_i_1\ : label is "soft_lutpair20";
begin
MID_START_BIT_SRL16_I: entity work.\system_axi_uartlite_0_0_dynshreg_i_f__parameterized0\
port map (
en_16x_Baud => en_16x_Baud,
s_axi_aclk => s_axi_aclk,
tx_Data_Enable_reg => MID_START_BIT_SRL16_I_n_0,
tx_Data_Enable_reg_0 => tx_Data_Enable_reg_n_0
);
SRL_FIFO_I: entity work.system_axi_uartlite_0_0_srl_fifo_f
port map (
Bus_RNW_reg => Bus_RNW_reg,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
Q(0) => Q(0),
fifo_Read => fifo_Read,
fifo_wr => fifo_wr,
mux_Out => mux_Out,
\mux_sel_reg[0]\ => \mux_sel_reg_n_0_[0]\,
\mux_sel_reg[2]\ => \mux_sel_reg_n_0_[2]\,
p_4_in => p_4_in,
reset_TX_FIFO_reg => reset_TX_FIFO_reg,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
tx_Buffer_Full => tx_Buffer_Full,
tx_DataBits => tx_DataBits,
tx_Data_Enable_reg => tx_Data_Enable_reg_n_0,
tx_Start => tx_Start,
tx_Start0 => tx_Start0
);
TX_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"31"
)
port map (
I0 => tx_DataBits,
I1 => tx_Start,
I2 => serial_Data,
O => TX0
);
TX_reg: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => TX0,
Q => tx,
S => SR(0)
);
fifo_Read_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0100"
)
port map (
I0 => \mux_sel_reg_n_0_[0]\,
I1 => \mux_sel_reg_n_0_[2]\,
I2 => p_4_in,
I3 => tx_Data_Enable_reg_n_0,
O => fifo_Read0
);
fifo_Read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => fifo_Read0,
Q => fifo_Read,
R => SR(0)
);
\mux_sel[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"E1F0F1F0"
)
port map (
I0 => p_4_in,
I1 => \mux_sel_reg_n_0_[2]\,
I2 => \mux_sel_reg_n_0_[0]\,
I3 => tx_Data_Enable_reg_n_0,
I4 => tx_DataBits,
O => \mux_sel[0]_i_1_n_0\
);
\mux_sel[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"99AAABAA"
)
port map (
I0 => p_4_in,
I1 => \mux_sel_reg_n_0_[2]\,
I2 => \mux_sel_reg_n_0_[0]\,
I3 => tx_Data_Enable_reg_n_0,
I4 => tx_DataBits,
O => \mux_sel[1]_i_1_n_0\
);
\mux_sel[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7777888C"
)
port map (
I0 => tx_DataBits,
I1 => tx_Data_Enable_reg_n_0,
I2 => \mux_sel_reg_n_0_[0]\,
I3 => p_4_in,
I4 => \mux_sel_reg_n_0_[2]\,
O => \mux_sel[2]_i_1_n_0\
);
\mux_sel_reg[0]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \mux_sel[0]_i_1_n_0\,
Q => \mux_sel_reg_n_0_[0]\,
S => SR(0)
);
\mux_sel_reg[1]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \mux_sel[1]_i_1_n_0\,
Q => p_4_in,
S => SR(0)
);
\mux_sel_reg[2]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \mux_sel[2]_i_1_n_0\,
Q => \mux_sel_reg_n_0_[2]\,
S => SR(0)
);
serial_Data_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => mux_Out,
Q => serial_Data,
R => SR(0)
);
tx_DataBits_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0F08"
)
port map (
I0 => tx_Start,
I1 => tx_Data_Enable_reg_n_0,
I2 => fifo_Read,
I3 => tx_DataBits,
O => tx_DataBits0
);
tx_DataBits_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => tx_DataBits0,
Q => tx_DataBits,
R => SR(0)
);
tx_Data_Enable_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => MID_START_BIT_SRL16_I_n_0,
Q => tx_Data_Enable_reg_n_0,
R => SR(0)
);
tx_Start_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => tx_Start0,
Q => tx_Start,
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_uartlite_core is
port (
status_reg : out STD_LOGIC_VECTOR ( 1 downto 0 );
bus2ip_reset : out STD_LOGIC;
rx_Buffer_Full : out STD_LOGIC;
tx_Buffer_Full : out STD_LOGIC;
tx : out STD_LOGIC;
interrupt : out STD_LOGIC;
enable_interrupts : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
FIFO_Full_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
reset_TX_FIFO : in STD_LOGIC;
reset_RX_FIFO : in STD_LOGIC;
bus2ip_rdce : in STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\ : in STD_LOGIC;
\INFERRED_GEN.cnt_i_reg[4]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : in STD_LOGIC;
Bus_RNW_reg_reg : in STD_LOGIC;
rx : in STD_LOGIC;
fifo_wr : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_uartlite_core : entity is "uartlite_core";
end system_axi_uartlite_0_0_uartlite_core;
architecture STRUCTURE of system_axi_uartlite_0_0_uartlite_core is
signal Interrupt0 : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal UARTLITE_RX_I_n_5 : STD_LOGIC;
signal \^bus2ip_reset\ : STD_LOGIC;
signal clr_Status : STD_LOGIC;
signal en_16x_Baud : STD_LOGIC;
signal \^enable_interrupts\ : STD_LOGIC;
signal reset_RX_FIFO_reg_n_0 : STD_LOGIC;
signal reset_TX_FIFO_reg_n_0 : STD_LOGIC;
signal rx_Data_Present_Pre : STD_LOGIC;
signal \^status_reg\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal status_reg_reg0 : STD_LOGIC;
signal tx_Buffer_Empty_Pre : STD_LOGIC;
begin
Q(0) <= \^q\(0);
bus2ip_reset <= \^bus2ip_reset\;
enable_interrupts <= \^enable_interrupts\;
status_reg(1 downto 0) <= \^status_reg\(1 downto 0);
BAUD_RATE_I: entity work.system_axi_uartlite_0_0_baudrate
port map (
SR(0) => \^bus2ip_reset\,
en_16x_Baud => en_16x_Baud,
s_axi_aclk => s_axi_aclk
);
Interrupt_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Interrupt0,
Q => interrupt,
R => \^bus2ip_reset\
);
UARTLITE_RX_I: entity work.system_axi_uartlite_0_0_uartlite_rx
port map (
Bus_RNW_reg => Bus_RNW_reg,
Bus_RNW_reg_reg => Bus_RNW_reg_reg,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
\INFERRED_GEN.cnt_i_reg[4]\(0) => \^q\(0),
Interrupt0 => Interrupt0,
Q(0) => FIFO_Full_reg(0),
SR(0) => \^bus2ip_reset\,
clr_Status => clr_Status,
en_16x_Baud => en_16x_Baud,
enable_interrupts => \^enable_interrupts\,
\out\(7 downto 0) => \out\(7 downto 0),
reset_RX_FIFO_reg => reset_RX_FIFO_reg_n_0,
rx => rx,
rx_Data_Present_Pre => rx_Data_Present_Pre,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
status_reg(1 downto 0) => \^status_reg\(1 downto 0),
status_reg_reg0 => status_reg_reg0,
\status_reg_reg[2]\ => rx_Buffer_Full,
\status_reg_reg[2]_0\ => UARTLITE_RX_I_n_5,
tx_Buffer_Empty_Pre => tx_Buffer_Empty_Pre
);
UARTLITE_TX_I: entity work.system_axi_uartlite_0_0_uartlite_tx
port map (
Bus_RNW_reg => Bus_RNW_reg,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
Q(0) => \^q\(0),
SR(0) => \^bus2ip_reset\,
en_16x_Baud => en_16x_Baud,
fifo_wr => fifo_wr,
reset_TX_FIFO_reg => reset_TX_FIFO_reg_n_0,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
tx => tx,
tx_Buffer_Full => tx_Buffer_Full
);
clr_Status_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => bus2ip_rdce(0),
Q => clr_Status,
R => \^bus2ip_reset\
);
enable_interrupts_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\,
Q => \^enable_interrupts\,
R => \^bus2ip_reset\
);
reset_RX_FIFO_reg: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => reset_RX_FIFO,
Q => reset_RX_FIFO_reg_n_0,
S => \^bus2ip_reset\
);
reset_TX_FIFO_reg: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => reset_TX_FIFO,
Q => reset_TX_FIFO_reg_n_0,
S => \^bus2ip_reset\
);
rx_Data_Present_Pre_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
Q => rx_Data_Present_Pre,
R => '0'
);
\status_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => status_reg_reg0,
Q => \^status_reg\(1),
R => '0'
);
\status_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => UARTLITE_RX_I_n_5,
Q => \^status_reg\(0),
R => '0'
);
tx_Buffer_Empty_Pre_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INFERRED_GEN.cnt_i_reg[4]\,
Q => tx_Buffer_Empty_Pre,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0_axi_uartlite is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
interrupt : out STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
rx : in STD_LOGIC;
tx : out STD_LOGIC
);
attribute C_BAUDRATE : integer;
attribute C_BAUDRATE of system_axi_uartlite_0_0_axi_uartlite : entity is 9600;
attribute C_DATA_BITS : integer;
attribute C_DATA_BITS of system_axi_uartlite_0_0_axi_uartlite : entity is 8;
attribute C_FAMILY : string;
attribute C_FAMILY of system_axi_uartlite_0_0_axi_uartlite : entity is "artix7";
attribute C_ODD_PARITY : integer;
attribute C_ODD_PARITY of system_axi_uartlite_0_0_axi_uartlite : entity is 0;
attribute C_S_AXI_ACLK_FREQ_HZ : integer;
attribute C_S_AXI_ACLK_FREQ_HZ of system_axi_uartlite_0_0_axi_uartlite : entity is 100000000;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of system_axi_uartlite_0_0_axi_uartlite : entity is 4;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_axi_uartlite_0_0_axi_uartlite : entity is 32;
attribute C_USE_PARITY : integer;
attribute C_USE_PARITY of system_axi_uartlite_0_0_axi_uartlite : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_uartlite_0_0_axi_uartlite : entity is "axi_uartlite";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_uartlite_0_0_axi_uartlite : entity is "yes";
end system_axi_uartlite_0_0_axi_uartlite;
architecture STRUCTURE of system_axi_uartlite_0_0_axi_uartlite is
signal \<const0>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_11 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_16 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_17 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_18 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_8 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_9 : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : STD_LOGIC;
signal \UARTLITE_RX_I/rx_Data_Empty\ : STD_LOGIC;
signal \UARTLITE_TX_I/fifo_wr\ : STD_LOGIC;
signal bus2ip_rdce : STD_LOGIC_VECTOR ( 1 to 1 );
signal bus2ip_reset : STD_LOGIC;
signal enable_interrupts : STD_LOGIC;
signal reset_RX_FIFO : STD_LOGIC;
signal reset_TX_FIFO : STD_LOGIC;
signal rx_Buffer_Full : STD_LOGIC;
signal rx_Data : STD_LOGIC_VECTOR ( 0 to 7 );
signal \^s_axi_awready\ : STD_LOGIC;
signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^s_axi_rresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal status_reg : STD_LOGIC_VECTOR ( 1 to 2 );
signal tx_Buffer_Empty : STD_LOGIC;
signal tx_Buffer_Full : STD_LOGIC;
begin
s_axi_awready <= \^s_axi_awready\;
s_axi_bresp(1) <= \^s_axi_bresp\(1);
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7 downto 0) <= \^s_axi_rdata\(7 downto 0);
s_axi_rresp(1) <= \^s_axi_rresp\(1);
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_awready\;
AXI_LITE_IPIF_I: entity work.system_axi_uartlite_0_0_axi_lite_ipif
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
FIFO_Full_reg => AXI_LITE_IPIF_I_n_11,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\INFERRED_GEN.cnt_i_reg[2]\ => AXI_LITE_IPIF_I_n_8,
\INFERRED_GEN.cnt_i_reg[2]_0\ => AXI_LITE_IPIF_I_n_9,
\INFERRED_GEN.cnt_i_reg[4]\(0) => tx_Buffer_Empty,
Q(0) => \UARTLITE_RX_I/rx_Data_Empty\,
bus2ip_rdce(0) => bus2ip_rdce(1),
bus2ip_reset => bus2ip_reset,
enable_interrupts => enable_interrupts,
enable_interrupts_reg => AXI_LITE_IPIF_I_n_16,
fifo_wr => \UARTLITE_TX_I/fifo_wr\,
\out\(7) => rx_Data(0),
\out\(6) => rx_Data(1),
\out\(5) => rx_Data(2),
\out\(4) => rx_Data(3),
\out\(3) => rx_Data(4),
\out\(2) => rx_Data(5),
\out\(1) => rx_Data(6),
\out\(0) => rx_Data(7),
reset_RX_FIFO => reset_RX_FIFO,
reset_TX_FIFO => reset_TX_FIFO,
rx_Buffer_Full => rx_Buffer_Full,
rx_Data_Present_Pre_reg => AXI_LITE_IPIF_I_n_18,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(1 downto 0) => s_axi_araddr(3 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(1 downto 0) => s_axi_awaddr(3 downto 2),
s_axi_awready => \^s_axi_awready\,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(0) => \^s_axi_bresp\(1),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(7 downto 0) => \^s_axi_rdata\(7 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(0) => \^s_axi_rresp\(1),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(2) => s_axi_wdata(4),
s_axi_wdata(1 downto 0) => s_axi_wdata(1 downto 0),
s_axi_wvalid => s_axi_wvalid,
status_reg(1) => status_reg(1),
status_reg(0) => status_reg(2),
tx_Buffer_Empty_Pre_reg => AXI_LITE_IPIF_I_n_17,
tx_Buffer_Full => tx_Buffer_Full
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
UARTLITE_CORE_I: entity work.system_axi_uartlite_0_0_uartlite_core
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
Bus_RNW_reg_reg => AXI_LITE_IPIF_I_n_9,
FIFO_Full_reg(0) => \UARTLITE_RX_I/rx_Data_Empty\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => AXI_LITE_IPIF_I_n_18,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ => AXI_LITE_IPIF_I_n_11,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => AXI_LITE_IPIF_I_n_8,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\ => AXI_LITE_IPIF_I_n_16,
\INFERRED_GEN.cnt_i_reg[4]\ => AXI_LITE_IPIF_I_n_17,
Q(0) => tx_Buffer_Empty,
bus2ip_rdce(0) => bus2ip_rdce(1),
bus2ip_reset => bus2ip_reset,
enable_interrupts => enable_interrupts,
fifo_wr => \UARTLITE_TX_I/fifo_wr\,
interrupt => interrupt,
\out\(7) => rx_Data(0),
\out\(6) => rx_Data(1),
\out\(5) => rx_Data(2),
\out\(4) => rx_Data(3),
\out\(3) => rx_Data(4),
\out\(2) => rx_Data(5),
\out\(1) => rx_Data(6),
\out\(0) => rx_Data(7),
reset_RX_FIFO => reset_RX_FIFO,
reset_TX_FIFO => reset_TX_FIFO,
rx => rx,
rx_Buffer_Full => rx_Buffer_Full,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
status_reg(1) => status_reg(1),
status_reg(0) => status_reg(2),
tx => tx,
tx_Buffer_Full => tx_Buffer_Full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_uartlite_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
interrupt : out STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
rx : in STD_LOGIC;
tx : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_axi_uartlite_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_axi_uartlite_0_0 : entity is "system_axi_uartlite_0_0,axi_uartlite,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_uartlite_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_axi_uartlite_0_0 : entity is "axi_uartlite,Vivado 2016.4";
end system_axi_uartlite_0_0;
architecture STRUCTURE of system_axi_uartlite_0_0 is
attribute C_BAUDRATE : integer;
attribute C_BAUDRATE of U0 : label is 9600;
attribute C_DATA_BITS : integer;
attribute C_DATA_BITS of U0 : label is 8;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_ODD_PARITY : integer;
attribute C_ODD_PARITY of U0 : label is 0;
attribute C_S_AXI_ACLK_FREQ_HZ : integer;
attribute C_S_AXI_ACLK_FREQ_HZ of U0 : label is 100000000;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 4;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_USE_PARITY : integer;
attribute C_USE_PARITY of U0 : label is 0;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.system_axi_uartlite_0_0_axi_uartlite
port map (
interrupt => interrupt,
rx => rx,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(3 downto 0) => s_axi_araddr(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(3 downto 0) => s_axi_awaddr(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid,
tx => tx
);
end STRUCTURE;
|
apache-2.0
|
9073acb46c64816f54aada89a996824d
| 0.563129 | 2.696691 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_quad_spi_flash_0/synth/system_axi_quad_spi_flash_0.vhd
| 1 | 17,774 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_quad_spi:3.2
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_quad_spi_v3_2_10;
USE axi_quad_spi_v3_2_10.axi_quad_spi;
ENTITY system_axi_quad_spi_flash_0 IS
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
io2_i : IN STD_LOGIC;
io2_o : OUT STD_LOGIC;
io2_t : OUT STD_LOGIC;
io3_i : IN STD_LOGIC;
io3_o : OUT STD_LOGIC;
io3_t : OUT STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END system_axi_quad_spi_flash_0;
ARCHITECTURE system_axi_quad_spi_flash_0_arch OF system_axi_quad_spi_flash_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_quad_spi_flash_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_quad_spi IS
GENERIC (
Async_Clk : INTEGER;
C_FAMILY : STRING;
C_SELECT_XPM : INTEGER;
C_SUB_FAMILY : STRING;
C_INSTANCE : STRING;
C_SPI_MEM_ADDR_BITS : INTEGER;
C_TYPE_OF_AXI4_INTERFACE : INTEGER;
C_XIP_MODE : INTEGER;
C_UC_FAMILY : INTEGER;
C_FIFO_DEPTH : INTEGER;
C_SCK_RATIO : INTEGER;
C_DUAL_QUAD_MODE : INTEGER;
C_NUM_SS_BITS : INTEGER;
C_NUM_TRANSFER_BITS : INTEGER;
C_SPI_MODE : INTEGER;
C_USE_STARTUP : INTEGER;
C_USE_STARTUP_EXT : INTEGER;
C_SPI_MEMORY : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI4_ADDR_WIDTH : INTEGER;
C_S_AXI4_DATA_WIDTH : INTEGER;
C_S_AXI4_ID_WIDTH : INTEGER;
C_SHARED_STARTUP : INTEGER;
C_S_AXI4_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI4_HIGHADDR : STD_LOGIC_VECTOR;
C_LSB_STUP : INTEGER
);
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi4_aclk : IN STD_LOGIC;
s_axi4_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi4_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_awaddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_awlock : IN STD_LOGIC;
s_axi4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awvalid : IN STD_LOGIC;
s_axi4_awready : OUT STD_LOGIC;
s_axi4_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_wlast : IN STD_LOGIC;
s_axi4_wvalid : IN STD_LOGIC;
s_axi4_wready : OUT STD_LOGIC;
s_axi4_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_bvalid : OUT STD_LOGIC;
s_axi4_bready : IN STD_LOGIC;
s_axi4_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_araddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_arlock : IN STD_LOGIC;
s_axi4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arvalid : IN STD_LOGIC;
s_axi4_arready : OUT STD_LOGIC;
s_axi4_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_rlast : OUT STD_LOGIC;
s_axi4_rvalid : OUT STD_LOGIC;
s_axi4_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
io2_i : IN STD_LOGIC;
io2_o : OUT STD_LOGIC;
io2_t : OUT STD_LOGIC;
io3_i : IN STD_LOGIC;
io3_o : OUT STD_LOGIC;
io3_t : OUT STD_LOGIC;
io0_1_i : IN STD_LOGIC;
io0_1_o : OUT STD_LOGIC;
io0_1_t : OUT STD_LOGIC;
io1_1_i : IN STD_LOGIC;
io1_1_o : OUT STD_LOGIC;
io1_1_t : OUT STD_LOGIC;
io2_1_i : IN STD_LOGIC;
io2_1_o : OUT STD_LOGIC;
io2_1_t : OUT STD_LOGIC;
io3_1_i : IN STD_LOGIC;
io3_1_o : OUT STD_LOGIC;
io3_1_t : OUT STD_LOGIC;
spisel : IN STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
ss_1_i : IN STD_LOGIC;
ss_1_o : OUT STD_LOGIC;
ss_1_t : OUT STD_LOGIC;
cfgclk : OUT STD_LOGIC;
cfgmclk : OUT STD_LOGIC;
eos : OUT STD_LOGIC;
preq : OUT STD_LOGIC;
clk : IN STD_LOGIC;
gsr : IN STD_LOGIC;
gts : IN STD_LOGIC;
keyclearb : IN STD_LOGIC;
usrcclkts : IN STD_LOGIC;
usrdoneo : IN STD_LOGIC;
usrdonets : IN STD_LOGIC;
pack : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END COMPONENT axi_quad_spi;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_axi_quad_spi_flash_0_arch: ARCHITECTURE IS "axi_quad_spi,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_axi_quad_spi_flash_0_arch : ARCHITECTURE IS "system_axi_quad_spi_flash_0,axi_quad_spi,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_axi_quad_spi_flash_0_arch: ARCHITECTURE IS "system_axi_quad_spi_flash_0,axi_quad_spi,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_quad_spi,x_ipVersion=3.2,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,Async_Clk=0,C_FAMILY=artix7,C_SELECT_XPM=0,C_SUB_FAMILY=artix7,C_INSTANCE=axi_quad_spi_inst,C_SPI_MEM_ADDR_BITS=24,C_TYPE_OF_AXI4_INTERFACE=0,C_XIP_MODE=0,C_UC_FAMILY=0,C_FIFO_DEPTH=16,C_SCK_RATIO=2,C_DUAL_QUAD_MODE=0,C_NUM_SS_BITS=1,C_NUM_TRANSFER_BITS=8,C_SPI_MODE=2,C_USE_STARTUP=0,C_USE_STARTU" &
"P_EXT=0,C_SPI_MEMORY=1,C_S_AXI_ADDR_WIDTH=7,C_S_AXI_DATA_WIDTH=32,C_S_AXI4_ADDR_WIDTH=24,C_S_AXI4_DATA_WIDTH=32,C_S_AXI4_ID_WIDTH=1,C_SHARED_STARTUP=0,C_S_AXI4_BASEADDR=0xFFFFFFFF,C_S_AXI4_HIGHADDR=0x00000000,C_LSB_STUP=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ext_spi_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 spi_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 lite_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 lite_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF io0_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_I";
ATTRIBUTE X_INTERFACE_INFO OF io0_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_O";
ATTRIBUTE X_INTERFACE_INFO OF io0_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_T";
ATTRIBUTE X_INTERFACE_INFO OF io1_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_I";
ATTRIBUTE X_INTERFACE_INFO OF io1_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_O";
ATTRIBUTE X_INTERFACE_INFO OF io1_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_T";
ATTRIBUTE X_INTERFACE_INFO OF io2_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO2_I";
ATTRIBUTE X_INTERFACE_INFO OF io2_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO2_O";
ATTRIBUTE X_INTERFACE_INFO OF io2_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO2_T";
ATTRIBUTE X_INTERFACE_INFO OF io3_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO3_I";
ATTRIBUTE X_INTERFACE_INFO OF io3_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO3_O";
ATTRIBUTE X_INTERFACE_INFO OF io3_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO3_T";
ATTRIBUTE X_INTERFACE_INFO OF sck_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_I";
ATTRIBUTE X_INTERFACE_INFO OF sck_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_O";
ATTRIBUTE X_INTERFACE_INFO OF sck_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_T";
ATTRIBUTE X_INTERFACE_INFO OF ss_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_I";
ATTRIBUTE X_INTERFACE_INFO OF ss_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_O";
ATTRIBUTE X_INTERFACE_INFO OF ss_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_T";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
BEGIN
U0 : axi_quad_spi
GENERIC MAP (
Async_Clk => 0,
C_FAMILY => "artix7",
C_SELECT_XPM => 0,
C_SUB_FAMILY => "artix7",
C_INSTANCE => "axi_quad_spi_inst",
C_SPI_MEM_ADDR_BITS => 24,
C_TYPE_OF_AXI4_INTERFACE => 0,
C_XIP_MODE => 0,
C_UC_FAMILY => 0,
C_FIFO_DEPTH => 16,
C_SCK_RATIO => 2,
C_DUAL_QUAD_MODE => 0,
C_NUM_SS_BITS => 1,
C_NUM_TRANSFER_BITS => 8,
C_SPI_MODE => 2,
C_USE_STARTUP => 0,
C_USE_STARTUP_EXT => 0,
C_SPI_MEMORY => 1,
C_S_AXI_ADDR_WIDTH => 7,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI4_ADDR_WIDTH => 24,
C_S_AXI4_DATA_WIDTH => 32,
C_S_AXI4_ID_WIDTH => 1,
C_SHARED_STARTUP => 0,
C_S_AXI4_BASEADDR => X"FFFFFFFF",
C_S_AXI4_HIGHADDR => X"00000000",
C_LSB_STUP => 0
)
PORT MAP (
ext_spi_clk => ext_spi_clk,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi4_aclk => '0',
s_axi4_aresetn => '0',
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi4_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_awlock => '0',
s_axi4_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awvalid => '0',
s_axi4_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi4_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_wlast => '0',
s_axi4_wvalid => '0',
s_axi4_bready => '0',
s_axi4_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_arlock => '0',
s_axi4_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arvalid => '0',
s_axi4_rready => '0',
io0_i => io0_i,
io0_o => io0_o,
io0_t => io0_t,
io1_i => io1_i,
io1_o => io1_o,
io1_t => io1_t,
io2_i => io2_i,
io2_o => io2_o,
io2_t => io2_t,
io3_i => io3_i,
io3_o => io3_o,
io3_t => io3_t,
io0_1_i => '0',
io1_1_i => '0',
io2_1_i => '0',
io3_1_i => '0',
spisel => '1',
sck_i => sck_i,
sck_o => sck_o,
sck_t => sck_t,
ss_i => ss_i,
ss_o => ss_o,
ss_t => ss_t,
ss_1_i => '0',
clk => '0',
gsr => '0',
gts => '0',
keyclearb => '0',
usrcclkts => '0',
usrdoneo => '1',
usrdonets => '0',
pack => '0',
ip2intc_irpt => ip2intc_irpt
);
END system_axi_quad_spi_flash_0_arch;
|
apache-2.0
|
19089293531684e2cd5707466c20f64c
| 0.644593 | 2.934456 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 3/DataMemory.vhd
| 1 | 880 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity DataMemory is
Port ( Crd : in STD_LOGIC_VECTOR (31 downto 0);
Address : in STD_LOGIC_VECTOR (31 downto 0);
WRENMEM : in STD_LOGIC;
--RDENMEM : in STD_LOGIC;
DATATOMEM : out STD_LOGIC_VECTOR (31 downto 0));
end DataMemory;
architecture Behavioral of DataMemory is
type ram_type is array (31 downto 0) of std_logic_vector (31 downto 0);
signal DM: ram_type:=(others => "00000000000000000000000000000000");
begin
process (Crd,Address,DM)--RDENMEM,DM)
begin
if WRENMEM='1' then
DM(conv_integer(Address(4 downto 0)))<=Crd;
DATATOMEM<=Crd;--(others=>'0');
--elsif RDENMEM='1' then
-- DATATOMEM<=DM(conv_integer(Address));
else
DATATOMEM<=DM(conv_integer(Address(4 downto 0)));
end if;
end process;
end Behavioral;
|
mit
|
bead7a434ba2261c7f482385dd148b49
| 0.660227 | 3.358779 | false | false | false | false |
jeffmagina/ECE368
|
Project1/EXECUTE/execute_tbd.vhd
| 1 | 3,627 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:02:59 04/04/2015
-- Design Name:
-- Module Name: C:/Users/Jeff Magina/Documents/GitHub/ECE368/Project1/EXECUTE/execute_tbd.vhd
-- Project Name: Execute
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: execute
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY execute_tbd IS
END execute_tbd;
ARCHITECTURE behavior OF execute_tbd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT execute
PORT(
CLK : IN std_logic;
OPCODE : IN std_logic_vector(3 downto 0);
OP1 : IN std_logic_vector(15 downto 0);
OP2 : IN std_logic_vector(15 downto 0);
FPU_OUT : OUT std_logic_vector(15 downto 0);
CCR : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal OPCODE : std_logic_vector(3 downto 0) := (others => '0');
signal OP1 : std_logic_vector(15 downto 0) := (others => '0');
signal OP2 : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal FPU_OUT : std_logic_vector(15 downto 0);
signal CCR : std_logic_vector(3 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: execute PORT MAP (
CLK => CLK,
OPCODE => OPCODE,
OP1 => OP1,
OP2 => OP2,
FPU_OUT => FPU_OUT,
CCR => CCR
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
tb: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- Add Reg A to Reg B
OPCODE <= x"0";
OP1 <= x"0003";
OP2 <= x"0001";
wait for CLK_period;
-- Subtract Reg A from Reg B
OPCODE <= x"1";
OP1 <= x"000F";
OP2 <= x"0003";
wait for CLK_period;
-- And
OPCODE <= x"2";
OP1 <= x"CC0F";
OP2 <= x"DE03";
wait for CLK_period;
-- OR
OPCODE <= x"3";
OP1 <= x"CC0F";
OP2 <= x"0D13";
wait for CLK_period;
-- MOV
OPCODE <= x"4";
OP1 <= x"000F";
OP2 <= x"0003";
wait for CLK_period;
-- ADDI
OPCODE <= x"5";
OP1 <= x"000F";
OP2 <= x"0003";
wait for CLK_period;
-- ANDI
OPCODE <= x"6";
OP1 <= x"000F";
OP2 <= x"0003";
wait for CLK_period;
-- SL
OPCODE <= x"7";
OP1 <= x"000F";
OP2 <= x"0003";
wait for CLK_period;
-- SR
OPCODE <= x"8";
OP1 <= x"000F";
OP2 <= x"0003";
wait for CLK_period;
-- LW
OPCODE <= x"9";
OP1 <= x"000F";
OP2 <= x"0003";
wait for CLK_period;
--SW
OPCODE <= x"A";
OP1 <= x"000F";
OP2 <= x"1002";
wait;
end process;
END;
|
mit
|
00b6c5f4e122919bbc27ddc6cba3ebd1
| 0.553626 | 3.206897 | false | false | false | false |
jeffmagina/ECE368
|
Lab1/ALU/alu_logic_unit.vhd
| 1 | 1,510 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Logic_Unit
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Logic Unit
-- Operations - AND, OR, CMP, ANDI
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Logic_Unit is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC_VECTOR (2 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
RESULT : out STD_LOGIC_VECTOR (7 downto 0));
end Logic_Unit;
architecture Combinational of Logic_Unit is
signal cmp: STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
with OP select
RESULT <=
A and B when "010", -- AND REG A, REG B
A or B when "011", -- OR REG A, REG B
x"00" when "100", -- CMP REG A, REG B
A and B when OTHERS;-- ANDI REG A, IMMED
--Compare Operation
cmp(3) <= '1' when a<b else '0'; -- N when s<r
cmp(2) <= '1' when a=b else '0'; -- Z when s=r
-- Choose CCR output
with OP select
ccr <=
cmp when "100",
"0000" when OTHERS;
end Combinational;
|
mit
|
7882c02e856b8e0999bfeb60ea5b4f73
| 0.542384 | 3.682927 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_wiz_0_0_ipif_pkg.vhd
| 1 | 53,567 |
-------------------------------------------------------------------------------
-- IPIF Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: system_xadc_wiz_0_0_ipif_pkg.vhd
-- Version: Intital
-- Description: This file contains the constants and functions used in the
-- ipif common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 02/21/02 -- Created from proc_common_pkg.vhd
--
-- DET 03/13/02 -- PLB IPIF development updates
-- ^^^^^^
-- - Commented out string types and string functions due to an XST
-- problem with string arrays and functions. THe string array
-- processing functions were replaced with comperable functions
-- operating on integer arrays.
-- ~~~~~~
--
--
-- DET 4/30/2002 Initial
-- ~~~~~~
-- - Added three functions: rebuild_slv32_array, rebuild_slv64_array, and
-- rebuild_int_array to support removal of unused elements from the
-- ARD arrays.
-- ^^^^^^ --
--
-- FLO 8/12/2002
-- ~~~~~~
-- - Added three functions: bits_needed_for_vac, bits_needed_for_occ,
-- and get_id_index_iboe.
-- (Removed provisional functions bits_needed_for_vacancy,
-- bits needed_for_occupancy, and bits_needed_for.)
-- ^^^^^^
--
-- FLO 3/24/2003
-- ~~~~~~
-- - Added dependent property paramters for channelized DMA.
-- - Added common property parameter array type.
-- - Definded the KEYHOLD_BURST common-property parameter.
-- ^^^^^^
--
-- FLO 10/22/2003
-- ~~~~~~
-- - Some adjustment to CHDMA parameterization.
-- - Cleanup of obsolete code and comments. (The former "XST workaround"
-- has become the officially deployed method.)
-- ^^^^^^
--
-- LSS 03/24/2004
-- ~~~~~~
-- - Added 5 functions
-- ^^^^^^
--
-- ALS 09/03/04
-- ^^^^^^
-- -- Added constants to describe the channel protocols used in MCH_OPB_IPIF
-- ~~~~~~
--
-- DET 1/17/2008 v3_30_a
-- ~~~~~~
-- - Changed proc_common library version to v3_30_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package system_xadc_wiz_0_0_ipif_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type SLV32_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 31);
subtype SLV64_TYPE is std_logic_vector(0 to 63);
type SLV64_ARRAY_TYPE is array (natural range <>) of SLV64_TYPE;
type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean;
function equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN;
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer;
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer;
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function S32 (in_string : string) return string;
--------------------------------------------------------------------------------
-- ARD support functions.
-- These function can be useful when operating with the ARD parameterization.
--------------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean;
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer)
return integer;
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE) return integer;
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer ;
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE;
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE;
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE;
-- 5 Functions Added 3/24/04
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE ;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Channel Protocols
-- The constant declarations below give symbolic-name aliases for values that
-- can be used in the C_MCH_PROTOCOL_ARRAY generic of the MCH_OPB_IPIF.
-------------------------------------------------------------------------------
constant XCL : integer := 0;
constant DAG : integer := 1;
--------------------------------------------------------------------------------
-- Address range types.
-- The constant declarations, below, give symbolic-name aliases for values
-- that can be used in the C_ARD_ID_ARRAY generic of IPIFs. The first set
-- gives aliases that are used to include IPIF services.
--------------------------------------------------------------------------------
-- IPIF module aliases
Constant IPIF_INTR : integer := 1;
Constant IPIF_RST : integer := 2;
Constant IPIF_SESR_SEAR : integer := 3;
Constant IPIF_DMA_SG : integer := 4;
Constant IPIF_WRFIFO_REG : integer := 5;
Constant IPIF_WRFIFO_DATA : integer := 6;
Constant IPIF_RDFIFO_REG : integer := 7;
Constant IPIF_RDFIFO_DATA : integer := 8;
Constant IPIF_CHDMA_CHANNELS : integer := 9;
Constant IPIF_CHDMA_GLOBAL_REGS : integer := 10;
Constant CHDMA_STATUS_FIFO : integer := 90;
-- Some predefined user module aliases
Constant USER_00 : integer := 100;
Constant USER_01 : integer := 101;
Constant USER_02 : integer := 102;
Constant USER_03 : integer := 103;
Constant USER_04 : integer := 104;
Constant USER_05 : integer := 105;
Constant USER_06 : integer := 106;
Constant USER_07 : integer := 107;
Constant USER_08 : integer := 108;
Constant USER_09 : integer := 109;
Constant USER_10 : integer := 110;
Constant USER_11 : integer := 111;
Constant USER_12 : integer := 112;
Constant USER_13 : integer := 113;
Constant USER_14 : integer := 114;
Constant USER_15 : integer := 115;
Constant USER_16 : integer := 116;
---( Start of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Dependent Properties (properties that depend on the type of
-- the address range, or in other words, address-range-specific parameters).
-- There is one property, i.e. one parameter, encoded as an integer at
-- each index of the properties array. There is one properties array for
-- each address range.
--
-- The C_ARD_DEPENDENT_PROPS_ARRAY generic parameter in (most) IPIFs is such
-- a properties array and it is usually giving its (static) value using a
-- VHDL aggregate construct. (--ToDo, give an example of this.)
--
-- The the "assigned" default value of a dependent property is zero. This value
-- is usually specified the aggregate by leaving its (index) name out so that
-- it is covered by an "others => 0" choice in the aggregate. Some parameters,
-- as noted in the definitions, below, have an "effective" default value that is
-- different from the assigned default value of zero. In such cases, the
-- function, eff_dp, given below, can be used to get the effective value of
-- the dependent property.
--------------------------------------------------------------------------------
constant DEPENDENT_PROPS_SIZE : integer := 32;
subtype DEPENDENT_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to DEPENDENT_PROPS_SIZE-1);
type DEPENDENT_PROPS_ARRAY_TYPE
is array (natural range <>) of DEPENDENT_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of dependent properties for the different types of
-- address ranges.
--
-- Example: Let C_ARD_DEPENDENT_PROPS_ARRAY hold the dependent properites
-- for a set of address ranges. Then, e.g.,
--
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(FIFO_CAPACITY_BITS)
--
-- gives the fifo capacity in bits, provided that the i'th address range
-- is of type IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals. (The right to change numerical index assignments
-- is reserved; applications using the names will not be affected by such
-- reassignments.)
--------------------------------------------------------------------------------
--
--ToDo, if the interrupt controller parameterization is ever moved to
-- C_ARD_DEPENDENT_PROPS_ARRAY, then the following declarations
-- could be uncommented and used.
---- IPIF_INTR IDX
---------------------------------------------------------------------------- ---
constant EXCLUDE_DEV_ISC : integer := 0;
-- 1 specifies that only the global interrupt
-- enable is present in the device interrupt source
-- controller and that the only source of interrupts
-- in the device is the IP interrupt source controller.
-- 0 specifies that the full device interrupt
-- source controller structure will be included.
constant INCLUDE_DEV_PENCODER : integer := 1;
-- 1 will include the Device IID in the device interrupt
-- source controller, 0 will exclude it.
--
-- IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA IDX
---------------------------------------------------------------------------- ---
constant FIFO_CAPACITY_BITS : integer := 0;
constant WR_WIDTH_BITS : integer := 1;
constant RD_WIDTH_BITS : integer := 2;
constant EXCLUDE_PACKET_MODE : integer := 3;
-- 1 Don't include packet mode features
-- 0 Include packet mode features
constant EXCLUDE_VACANCY : integer := 4;
-- 1 Don't include vacancy calculation
-- 0 Include vacancy calculation
-- See also the functions
-- bits_needed_for_vac and
-- bits_needed_for_occ that are declared below.
constant INCLUDE_DRE : integer := 5;
constant INCLUDE_AUTOPUSH_POP : integer := 6;
constant AUTOPUSH_POP_CE : integer := 7;
constant INCLUDE_CSUM : integer := 8;
--------------------------------------------------------------------------------
--
-- DMA_SG IDX
---------------------------------------------------------------------------- ---
--------------------------------------------------------------------------------
-- IPIF_CHDMA_CHANNELS IDX
---------------------------------------------------------------------------- ---
constant NUM_SUBS_FOR_PHYS_0 : integer :=0;
constant NUM_SUBS_FOR_PHYS_1 : integer :=1;
constant NUM_SUBS_FOR_PHYS_2 : integer :=2;
constant NUM_SUBS_FOR_PHYS_3 : integer :=3;
constant NUM_SUBS_FOR_PHYS_4 : integer :=4;
constant NUM_SUBS_FOR_PHYS_5 : integer :=5;
constant NUM_SUBS_FOR_PHYS_6 : integer :=6;
constant NUM_SUBS_FOR_PHYS_7 : integer :=7;
constant NUM_SUBS_FOR_PHYS_8 : integer :=8;
constant NUM_SUBS_FOR_PHYS_9 : integer :=9;
constant NUM_SUBS_FOR_PHYS_10 : integer :=10;
constant NUM_SUBS_FOR_PHYS_11 : integer :=11;
constant NUM_SUBS_FOR_PHYS_12 : integer :=12;
constant NUM_SUBS_FOR_PHYS_13 : integer :=13;
constant NUM_SUBS_FOR_PHYS_14 : integer :=14;
constant NUM_SUBS_FOR_PHYS_15 : integer :=15;
-- Gives the number of sub-channels for physical channel i.
--
-- These constants, which will be MAX_NUM_PHYS_CHANNELS in number (see
-- below), have consecutive values starting with 0 for
-- NUM_SUBS_FOR_PHYS_0. (The constants serve the purpose of giving symbolic
-- names for use in the dependent-properties aggregates that parameterize
-- an IPIF_CHDMA_CHANNELS address range.)
--
-- [Users can ignore this note for developers
-- If the number of physical channels changes, both the
-- IPIF_CHDMA_CHANNELS constants and MAX_NUM_PHYS_CHANNELS,
-- below, must be adjusted.
-- (Use of an array constant or a function of the form
-- NUM_SUBS_FOR_PHYS(i) to define the indices
-- runs afoul of LRM restrictions on non-locally static aggregate
-- choices. (Further, the LRM imposes perhaps unnecessarily
-- strict limits on what qualifies as a locally static primary.)
-- Note: This information is supplied for the benefit of anyone seeking
-- to improve the way that these NUM_SUBS_FOR_PHYS parameter
-- indices are defined.)
-- End of note for developers ]
--
-- The value associated with any index NUM_SUBS_FOR_PHYS_i in the
-- dependent-properties array must be even since TX and RX channels
-- come in pairs with the TX followed immediately by
-- the corresponding RX.
--
constant NUM_SIMPLE_DMA_CHANS : integer :=16;
-- The number of simple DMA channels.
constant NUM_SIMPLE_SG_CHANS : integer :=17;
-- The number of simple SG channels.
constant INTR_COALESCE : integer :=18;
-- 0 Interrupt coalescing is disabled
-- 1 Interrupt coalescing is enabled
constant CLK_PERIOD_PS : integer :=19;
-- The period of the OPB Bus clock in ps.
-- The default value of 0 is a special value that
-- is synonymous with 10000 ps (10 ns).
-- The value for CLK_PERIOD_PS is relevant only if (INTR_COALESCE = 1).
constant PACKET_WAIT_UNIT_NS : integer :=20;
-- Gives the unit for used for timing of pack-wait bounds.
-- The default value of 0 is a special value that
-- is synonymous with 1,000,000 ns (1 ms) and a non-default
-- value is typically only used for testing.
-- Relevant only if (INTR_COALESCE = 1).
constant BURST_SIZE : integer :=21;
-- 1, 2, 4, 8 or 16
-- The default value of 0 is a special value that
-- is synonymous with a burst size of 16.
-- Setting the BURST_SIZE to 1 effectively disables
-- bursts.
constant REMAINDER_AS_SINGLES : integer :=22;
-- 0 Remainder handled as a short burst
-- 1 Remainder handled as a series of singles
--------------------------------------------------------------------------------
-- The constant below is not the index of a dependent-properties
-- parameter (and, as such, would never appear as a choice in a
-- dependent-properties aggregate). Rather, it is fixed to the maximum
-- number of physical channels that an Address Range of type
-- IPIF_CHDMA_CHANNELS supports. It must be maintained in conjuction with
-- the constants named, e.g., NUM_SUBS_FOR_PHYS_15, above.
--------------------------------------------------------------------------------
constant MAX_NUM_PHYS_CHANNELS : natural := 16;
--------------------------------------------------------------------------
-- EXAMPLE: Here is an example dependent-properties aggregate for an
-- address range of type IPIF_CHDMA_CHANNELS.
-- To have a compact list of all of the CHDMA parameters, all are
-- shown, however three are commented out and the unneeded
-- MUM_SUBS_FOR_PHYS_x are excluded. The "OTHERS => 0" association
-- gives these parameters their default values, such that, for the example
--
-- - All physical channels above 2 have zero subchannels (effectively,
-- these physical channels are not used)
-- - There are no simple SG channels
-- - The packet-wait time unit is 1 ms
-- - Burst size is 16
--------------------------------------------------------------------------
-- (
-- NUM_SUBS_FOR_PHYS_0 => 8,
-- NUM_SUBS_FOR_PHYS_1 => 4,
-- NUM_SUBS_FOR_PHYS_2 => 14,
-- NUM_SIMPLE_DMA_CHANS => 1,
-- --NUM_SIMPLE_SG_CHANS => 5,
-- INTR_COALESCE => 1,
-- CLK_PERIOD_PS => 20000,
-- --PACKET_WAIT_UNIT_NS => 50000,
-- --BURST_SIZE => 1,
-- REMAINDER_AS_SINGLES => 1,
-- OTHERS => 0
-- )
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the vacancy (emptiness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the occupancy (fullness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Function eff_dp.
--
-- For some of the dependent properties, the default value of zero is meant
-- to imply an effective default value of other than zero (see e.g.
-- PKT_WAIT_UNIT_NS for the IPIF_CHDMA_CHANNELS address-range type). The
-- following function is used to get the (possibly default-adjusted)
-- value for a dependent property.
--
-- Example call:
--
-- eff_value_of_param :=
-- eff_dp(
-- C_IPIF_CHDMA_CHANNELS,
-- PACKET_WAIT_UNIT_NS,
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(PACKET_WAIT_UNIT_NS)
-- );
--
-- where C_ARD_DEPENDENT_PROPS_ARRAY(i) is an object of type
-- DEPENDENT_PROPS_ARRAY_TYPE, that was parameterized for an address range of
-- type C_IPIF_CHDMA_CHANNELS.
--------------------------------------------------------------------------------
function eff_dp(id : integer; -- The type of address range.
dep_prop : integer; -- The index of the dependent prop.
value : integer -- The value at that index.
) return integer; -- The effective value, possibly adjusted
-- if value has the default value of 0.
---) End of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Common Properties (properties that apply regardless of the
-- type of the address range). Structurally, these work the same as
-- the dependent properties.
--------------------------------------------------------------------------------
constant COMMON_PROPS_SIZE : integer := 2;
subtype COMMON_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to COMMON_PROPS_SIZE-1);
type COMMON_PROPS_ARRAY_TYPE
is array (natural range <>) of COMMON_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of the common properties.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals.
-- IDX
---------------------------------------------------------------------------- ---
constant KEYHOLE_BURST : integer := 0;
-- 1 All addresses of a burst are forced to the initial
-- address of the burst.
-- 0 Burst addresses follow the bus protocol.
-- IP interrupt mode array constants
Constant INTR_PASS_THRU : integer := 1;
Constant INTR_PASS_THRU_INV : integer := 2;
Constant INTR_REG_EVENT : integer := 3;
Constant INTR_REG_EVENT_INV : integer := 4;
Constant INTR_POS_EDGE_DETECT : integer := 5;
Constant INTR_NEG_EDGE_DETECT : integer := 6;
end system_xadc_wiz_0_0_ipif_pkg;
library work;
use work.system_xadc_wiz_0_0_proc_common_pkg.log2;
package body system_xadc_wiz_0_0_ipif_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function "="
--
-- This function can be used to overload the "=" operator when comparing
-- strings.
-----------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean is
constant tc: character := ' '; -- string termination character
variable i: integer := 1;
variable v1 : string(1 to s1'length) := s1;
variable v2 : string(1 to s2'length) := s2;
begin
while (i <= v1'length) and (v1(i) /= tc) and
(i <= v2'length) and (v2(i) /= tc) and
(v1(i) = v2(i))
loop
i := i+1;
end loop;
return ((i > v1'length) or (v1(i) = tc)) and
((i > v2'length) or (v2(i) = tc));
end;
----------------------------------------------------------------------------
-- Function equaluseCase
--
-- This function returns true if case sensitive string comparison determines
-- that str1 and str2 are the same.
-----------------------------------------------------------------------------
FUNCTION equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str1'range LOOP
IF NOT (str1(i) = str2(i)) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equaluseCase;
-----------------------------------------------------------------------------
-- Function calc_num_ce
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The array is input to
-- the function and an integer is returned reflecting the total number of
-- Chip Enables required for the CE, RdCE, and WrCE Buses
-----------------------------------------------------------------------------
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer is
Variable ce_num_sum : integer := 0;
begin
for i in 0 to (ce_num_array'length)-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
return(ce_num_sum);
end function calc_num_ce;
-----------------------------------------------------------------------------
-- Function calc_start_ce_index
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The CE Size array is
-- input to the function and an integer index representing the index of the
-- target module in the ce_num_array. An integer is returned reflecting the
-- starting index of the assigned Chip Enables within the CE, RdCE, and
-- WrCE Buses.
-----------------------------------------------------------------------------
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer is
Variable ce_num_sum : integer := 0;
begin
If (index = 0) Then
ce_num_sum := 0;
else
for i in 0 to index-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
End if;
return(ce_num_sum);
end function calc_start_ce_index;
-----------------------------------------------------------------------------
-- Function get_min_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the smallest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_min : Integer := 1024;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) < temp_min) Then
temp_min := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_min);
end function get_min_dwidth;
-----------------------------------------------------------------------------
-- Function get_max_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the largest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_max : Integer := 0;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) > temp_max) Then
temp_max := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_max);
end function get_max_dwidth;
-----------------------------------------------------------------------------
-- Function S32
--
-- This function is used to expand an input string to 32 characters by
-- padding with spaces. If the input string is larger than 32 characters,
-- it will truncate to 32 characters.
-----------------------------------------------------------------------------
function S32 (in_string : string) return string is
constant OUTPUT_STRING_LENGTH : integer := 32;
Constant space : character := ' ';
variable new_string : string(1 to 32);
Variable start_index : Integer := in_string'length+1;
begin
If (in_string'length < OUTPUT_STRING_LENGTH) Then
for i in 1 to in_string'length loop
new_string(i) := in_string(i);
End loop;
for j in start_index to OUTPUT_STRING_LENGTH loop
new_string(j) := space;
End loop;
else -- use first 32 chars of in_string (truncate the rest)
for k in 1 to OUTPUT_STRING_LENGTH loop
new_string(k) := in_string(k);
End loop;
End if;
return(new_string);
end function S32;
-----------------------------------------------------------------------------
-- Function get_id_index
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- id number is input to the function. A integer is returned reflecting the
-- array index of the id matching the id input number. This function
-- should only be called if the id number is known to exist in the
-- name_array input. This can be detirmined by using the find_ard_id
-- function.
-----------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := 10000; -- a really big number!
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then
match_index := array_index;
else
null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index;
--------------------------------------------------------------------------------
-- get_id_index but return a value in bounds on error (iboe).
--
-- This function is the same as get_id_index, except that when id does
-- not exist in id_array, the value returned is any index that is
-- within the index range of id_array.
--
-- This function would normally only be used where function find_ard_id
-- is used to establish the existence of id but, even when non-existent,
-- an element of one of the ARD arrays will be computed from the
-- returned get_id_index_iboe value. See, e.g., function bits_needed_for_vac
-- and the example call, below
--
-- bits_needed_for_vac(
-- find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA),
-- C_ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe(C_ARD_ID_ARRAY,
-- IPIF_RDFIFO_DATA))
-- )
--------------------------------------------------------------------------------
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := id_array'left; -- any valid array index
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then match_index := array_index;
else null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index_iboe;
-----------------------------------------------------------------------------
-- Function find_ard_id
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- integer id is input to the function. A boolean is returned reflecting the
-- presence (or not) of a number in the array matching the id input number.
-----------------------------------------------------------------------------
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean is
Variable match : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
End if;
End loop;
return(match);
end function find_ard_id;
-----------------------------------------------------------------------------
-- Function find_id_dwidth
--
-- This function is used to find the data width of a target module. If the
-- target module exists, the data width is extracted from the input dwidth
-- array. If the module is not in the ID array, the default input is
-- returned. This function is needed to assign data port size constraints on
-- unconstrained port widths.
-----------------------------------------------------------------------------
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer) return integer is
Variable id_present : Boolean := false;
Variable array_index : Integer := 0;
Variable dwidth : Integer := default;
begin
id_present := find_ard_id(id_array, id);
If (id_present) Then
array_index := get_id_index (id_array, id);
dwidth := dwidth_array(array_index);
else
null; -- use default input
End if;
Return (dwidth);
end function find_id_dwidth;
-----------------------------------------------------------------------------
-- Function cnt_ipif_id_blks
--
-- This function is used to detirmine the number of IPIF components specified
-- in the ARD ID Array. An integer is returned representing the number
-- of elements counted. User IDs are ignored in the counting process.
-----------------------------------------------------------------------------
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE)
return integer is
Variable blk_count : integer := 0;
Variable temp_id : integer;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_count := blk_count+1;
else -- go to next loop iteration
null;
End if;
End loop;
return(blk_count);
end function cnt_ipif_id_blks;
-----------------------------------------------------------------------------
-- Function get_ipif_id_dbus_index
--
-- This function is used to detirmine the IPIF relative index of a given
-- ID value. User IDs are ignored in the index detirmination.
-----------------------------------------------------------------------------
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer is
Variable blk_index : integer := 0;
Variable temp_id : integer;
Variable id_found : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (id_found) then
null;
elsif (temp_id = id) then
id_found := true;
elsif (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_index := blk_index+1;
else -- user block so do nothing
null;
End if;
End loop;
return(blk_index);
end function get_ipif_id_dbus_index;
------------------------------------------------------------------------------
-- Function: rebuild_slv32_array
--
-- Description:
-- This function takes an input slv32 array and rebuilds an output slv32
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr32_array : SLV32_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr32_array(array_index) := slv32_array(array_index);
end loop;
return(temp_baseaddr32_array);
end function rebuild_slv32_array;
------------------------------------------------------------------------------
-- Function: rebuild_slv64_array
--
-- Description:
-- This function takes an input slv64 array and rebuilds an output slv64
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr64_array : SLV64_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr64_array(array_index) := slv64_array(array_index);
end loop;
return(temp_baseaddr64_array);
end function rebuild_slv64_array;
------------------------------------------------------------------------------
-- Function: rebuild_int_array
--
-- Description:
-- This function takes an input integer array and rebuilds an output integer
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE is
-- Variables
variable temp_int_array : INTEGER_ARRAY_TYPE( 0 to num_valid_entry-1);
begin
for array_index in 0 to num_valid_entry-1 loop
temp_int_array(array_index) := int_array(array_index);
end loop;
return(temp_int_array);
end function rebuild_int_array;
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(RD_WIDTH_BITS)
);
end if;
end function bits_needed_for_vac;
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(WR_WIDTH_BITS)
);
end if;
end function bits_needed_for_occ;
function eff_dp(id : integer;
dep_prop : integer;
value : integer) return integer is
variable dp : integer := dep_prop;
type bo2na_type is array (boolean) of natural;
constant bo2na : bo2na_type := (0, 1);
begin
if value /= 0 then return value; end if; -- Not default
case id is
when IPIF_CHDMA_CHANNELS =>
-------------------
return( bo2na(dp = CLK_PERIOD_PS ) * 10000
+ bo2na(dp = PACKET_WAIT_UNIT_NS ) * 1000000
+ bo2na(dp = BURST_SIZE ) * 16
);
when others => return 0;
end case;
end eff_dp;
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE is
variable intr_mode_array : INTEGER_ARRAY_TYPE(0 to num_user_intr-1);
begin
for i in 0 to num_user_intr-1 loop
intr_mode_array(i) := intr_capture_mode;
end loop;
return intr_mode_array;
end function populate_intr_mode_array;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_id_array : INTEGER_ARRAY_TYPE(0 to ard_id_array'length);
begin
intr_ard_id_array(0 to ard_id_array'length-1) := ard_id_array;
if include_intr then
intr_ard_id_array(ard_id_array'length) := IPIF_INTR;
return intr_ard_id_array;
else
return ard_id_array;
end if;
end function add_intr_ard_id_array;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE is
variable intr_ard_addr_range_array : SLV64_ARRAY_TYPE(0 to ard_addr_range_array'length+1);
begin
intr_ard_addr_range_array(0 to ard_addr_range_array'length-1) := ard_addr_range_array;
if include_intr then
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR))
:= ZERO_ADDR_PAD & intr_baseaddr;
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR)+1)
:= ZERO_ADDR_PAD & intr_highaddr;
return intr_ard_addr_range_array;
else
return ard_addr_range_array;
end if;
end function add_intr_ard_addr_range_array;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_dwidth_array : INTEGER_ARRAY_TYPE(0 to ard_dwidth_array'length);
begin
intr_ard_dwidth_array(0 to ard_dwidth_array'length-1) := ard_dwidth_array;
if include_intr then
intr_ard_dwidth_array(get_id_index(ard_id_array, IPIF_INTR)) := intr_dwidth;
return intr_ard_dwidth_array;
else
return ard_dwidth_array;
end if;
end function add_intr_ard_dwidth_array;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_num_ce_array : INTEGER_ARRAY_TYPE(0 to ard_num_ce_array'length);
begin
intr_ard_num_ce_array(0 to ard_num_ce_array'length-1) := ard_num_ce_array;
if include_intr then
intr_ard_num_ce_array(get_id_index(ard_id_array, IPIF_INTR)) := 16;
return intr_ard_num_ce_array;
else
return ard_num_ce_array;
end if;
end function add_intr_ard_num_ce_array;
end package body system_xadc_wiz_0_0_ipif_pkg;
|
apache-2.0
|
0c6bd8cb4e2f4100d7761247f46ca6ad
| 0.491011 | 4.845062 | false | false | false | false |
alextrem/red-diamond
|
fpga/vhdl/i2s_tx.vhd
| 1 | 2,686 |
------------------------------------------------------------------------------
-- Company: Red Diamond
-- Engineer: Alexander Geissler
--
-- Create Date: 23:40:00 11/27/2016
-- Design Name: i2s_tx.vhd
-- Project Name: red-diamond
-- Target Device: EP4CE22C8N
-- Tool Versions: 16.0
-- Description: This is a i2s tx modul. Two 24 bit shift registers clock
-- data to a D/A.
-- Key Features:
-- - configure receiver/transmitter, clock master/slave
-- word select master/slave
-- - ARM AMBA AXI4-Lite Bus (in future)
-- - Justification modes: normal, left, right
-- - Up to 8 I2S instances, configurable in different ways
-- - Testmodes
--
-- Dependencies:
--
-- Revision:
-- Revision 0.1 - File created
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.i2s_pkg.all;
entity i2s_tx is
--generic ( DATA_WIDTH : integer range 16 to 24
--);
port (
-- Synchronous reset
reset_n : in std_logic;
-- Master clock
mclk : in std_logic;
-- I2S interface
-- input
i2s_in : in t_i2s_in;
-- output
i2s_out : out t_i2s_out
);
end entity;
architecture rtl of i2s_tx is
constant c_cos_rom : mem_array := cos_lut;
type t_reg_type is record
word_clock : std_logic;
temp_reg : std_logic_vector(23 downto 0);
counter : std_logic_vector(4 downto 0);
end record;
signal r, r_next : t_reg_type;
begin
comb_proc : process(reset_n, r)
variable v : t_reg_type;
begin
v := r;
v.counter := std_logic_vector(unsigned(r.counter) + 1);
-- toggle word clock when 32bit have been clocked in
if r.counter = b"10000" then -- 32
v.word_clock := not r.word_clock; -- toggle word clock
v.counter := b"00000"; -- reset counter
-- latch data to temporariy register when 32 bit have been counted
if r.word_clock = '0' then
v.temp_reg := i2s_in.l_channel;
else
v.temp_reg := i2s_in.r_channel;
end if;
end if;
-- shift data to output
v.temp_reg(23 downto 1) := r.temp_reg(22 downto 0);
if reset_n = '0' then
v.word_clock := '0'; -- 0=left, 1=right
v.counter := b"00000";
end if;
r_next <= v;
i2s_out.sdata <= r.temp_reg(23);
i2s_out.wclk <= r.word_clock;
end process comb_proc;
seq_proc : process(mclk)
begin
if rising_edge(mclk) then
r <= r_next;
end if;
end process seq_proc;
end rtl;
|
gpl-3.0
|
51a768e5b9283f5029c23434c5b2cb69
| 0.536485 | 3.430396 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 3/InstructionMemory.vhd
| 1 | 3,785 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity InstructionMemory is
Port ( Address : in STD_LOGIC_VECTOR (5 downto 0);
rst : in STD_LOGIC;
Instruction : out STD_LOGIC_VECTOR (31 downto 0));
end InstructionMemory;
architecture syn of InstructionMemory is
type rom_type is array (63 downto 0) of std_logic_vector (31 downto 0);
signal ROM : rom_type:= ("00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000",
"10010000000100000000000000010000",
"10110010000100000010000000000110","01111111111111111111111111110100",
"10100010000100000000000000010010","00010000101111111111111111111000",--"10000001110000000010000000000100",
"10100100000001000110000000000001","10100000000100000000000000010010",
"10100100000001000000000000011000",
"00000001000000000000000000000000","10000001110000111110000000000010",
"00000001000000000000000000000000","00101100100000000000000000000100",
"10000000101001000100000000011001","10100010000100000010000000000000",
"10100000000100000010000000000000","10110000000100000010000000001100",
"01000000000000000000000000001110");
--"00000000000000000000000000000000","10011110000001000100000000010000",
--"10101110100001010100000000010110","10101101001011010011000000010100",--"10101100100001010100000000010101",
--"10101011001011010011000000010011","10101000000100000010111111111111",
--"10100110100101000000000000010001","10100110100010000010011110101000",
--"10010000001001000100000000010010","10100100000001000010000000010000",
--"10100010000100000010000000010001","10100000000100000010000000001111");
begin
process(rst,Address,ROM)
begin
if rst='1' then
Instruction<=(others=>'0');
else
Instruction<=ROM(conv_integer(Address));
end if;
end process;
end syn;
|
mit
|
d0c4cf1d7cc3651b04d1d9e3ed1401bd
| 0.767239 | 7.852697 | false | false | false | false |
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